Update MSP432 projects to use updated driver library files.
Remove references to INCLUDE_pcTaskGetTaskName and INCLUDE_xTimerGetTimerDaemonTaskHandle, which are no longer required.
diff --git a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/RTOSDemo.cproj b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/RTOSDemo.cproj
index 478b930..f74f881 100644
--- a/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/RTOSDemo.cproj
+++ b/FreeRTOS/Demo/CORTEX_ATSAM3S-EK2_Atmel_Studio/RTOSDemo.cproj
@@ -2,7 +2,7 @@
<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">
<PropertyGroup>
<SchemaVersion>2.0</SchemaVersion>
- <ProjectVersion>6.0</ProjectVersion>
+ <ProjectVersion>7.0</ProjectVersion>
<ProjectGuid>{4c68ca75-30f2-4325-8b61-35952638d586}</ProjectGuid>
<Name>$(MSBuildProjectName)</Name>
<AssemblyName>$(MSBuildProjectName)</AssemblyName>
@@ -10,138 +10,142 @@
<AsfVersion>3.3.0</AsfVersion>
<AsfFrameworkConfig>
<framework-data>
- <options>
- <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />
- <option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />
- <option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />
- <option id="common.services.basic.clock" value="Add" config="" content-id="Atmel.ASF" />
- <option id="sam.drivers.usart" value="Add" config="" content-id="Atmel.ASF" />
- </options>
- <configurations>
- <configuration key="config.sam.pio.pio_handler" value="yes" default="yes" content-id="Atmel.ASF" />
- </configurations>
- <files>
- <file path="src/asf.h" framework="" version="3.3.0" source="./common/applications/user_application/sam3sd8c_sam3s_ek2/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/main.c" framework="" version="3.3.0" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/config/conf_board.h" framework="" version="3.3.0" source="common/applications/user_application/sam3sd8c_sam3s_ek2/conf_board.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/boards/board.h" framework="" version="3.3.0" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/gpio/gpio.h" framework="" version="3.3.0" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" framework="" version="3.3.0" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/utils/interrupt.h" framework="" version="3.3.0" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/utils/parts.h" framework="" version="3.3.0" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/boards/sam3s_ek2/init.c" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/init.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/boards/sam3s_ek2/led.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/led.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/boards/sam3s_ek2/sam3s_ek2.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/sam3s_ek2.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/pio/pio.c" framework="" version="3.3.0" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/pio/pio.h" framework="" version="3.3.0" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/pio/pio_handler.c" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/pio/pio_handler.h" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_acc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_crccu.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pdc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pio.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_tc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_twi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_uart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_udp.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_usart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/sam3s8.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/sam3s8.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/include/sam3sd8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/sam3sd8c.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/exceptions.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/exceptions.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/exceptions.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/exceptions.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/compiler.h" framework="" version="3.3.0" source="sam/utils/compiler.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/header_files/io.h" framework="" version="3.3.0" source="sam/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld" framework="" version="3.3.0" source="sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/make/Makefile.in" framework="" version="3.3.0" source="sam/utils/make/Makefile.in" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/preprocessor/mrepeat.h" framework="" version="3.3.0" source="sam/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/preprocessor/preprocessor.h" framework="" version="3.3.0" source="sam/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/preprocessor/stringz.h" framework="" version="3.3.0" source="sam/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/preprocessor/tpaste.h" framework="" version="3.3.0" source="sam/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/utils/status_codes.h" framework="" version="3.3.0" source="sam/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" framework="" version="3.3.0" source="thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/thirdparty/CMSIS/Include/core_cm3.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cm3.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/thirdparty/CMSIS/Include/core_cmFunc.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cmFunc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/thirdparty/CMSIS/Include/core_cmInstr.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cmInstr.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/thirdparty/CMSIS/README.txt" framework="" version="3.3.0" source="thirdparty/CMSIS/README.txt" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/thirdparty/CMSIS/license.txt" framework="" version="3.3.0" source="thirdparty/CMSIS/license.txt" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/pmc/pmc.c" framework="" version="" source="sam\drivers\pmc\pmc.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/pmc/pmc.h" framework="" version="" source="sam\drivers\pmc\pmc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/pmc/sleep.h" framework="" version="" source="sam\drivers\pmc\sleep.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/usart/usart.c" framework="" version="" source="sam\drivers\usart\usart.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/sam/drivers/usart/usart.h" framework="" version="" source="sam\drivers\usart\usart.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/sam3s/sysclk.c" framework="" version="" source="common\services\clock\sam3s\sysclk.c" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/sam3s/pll.h" framework="" version="" source="common\services\clock\sam3s\pll.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/sam3s/osc.h" framework="" version="" source="common\services\clock\sam3s\osc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/genclk.h" framework="" version="" source="common\services\clock\genclk.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/osc.h" framework="" version="" source="common\services\clock\osc.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/sam3s/sysclk.h" framework="" version="" source="common\services\clock\sam3s\sysclk.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/sam3s/genclk.h" framework="" version="" source="common\services\clock\sam3s\genclk.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/sysclk.h" framework="" version="" source="common\services\clock\sysclk.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/asf/common/services/clock/pll.h" framework="" version="" source="common\services\clock\pll.h" changed="False" content-id="Atmel.ASF" />
- <file path="src/config/conf_clock.h" framework="" version="" source="common\services\clock\sam3s\module_config\conf_clock.h" changed="False" content-id="Atmel.ASF" />
- </files>
- <documentation help="http://asf.atmel.com/docs/3.3.0/common.applications.user_application.sam3s_ek2/html/index.html" />
- </framework-data>
+ <options>
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="common.services.basic.clock" value="Add" config="" content-id="Atmel.ASF" />
+ <option id="sam.drivers.usart" value="Add" config="" content-id="Atmel.ASF" />
+ </options>
+ <configurations>
+ <configuration key="config.sam.pio.pio_handler" value="yes" default="yes" content-id="Atmel.ASF" />
+ </configurations>
+ <files>
+ <file path="src/asf.h" framework="" version="3.3.0" source="./common/applications/user_application/sam3sd8c_sam3s_ek2/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/main.c" framework="" version="3.3.0" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/config/conf_board.h" framework="" version="3.3.0" source="common/applications/user_application/sam3sd8c_sam3s_ek2/conf_board.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/boards/board.h" framework="" version="3.3.0" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/gpio/gpio.h" framework="" version="3.3.0" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" framework="" version="3.3.0" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/utils/interrupt.h" framework="" version="3.3.0" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/utils/parts.h" framework="" version="3.3.0" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/boards/sam3s_ek2/init.c" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/init.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/boards/sam3s_ek2/led.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/led.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/boards/sam3s_ek2/sam3s_ek2.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/sam3s_ek2.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/pio/pio.c" framework="" version="3.3.0" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/pio/pio.h" framework="" version="3.3.0" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/pio/pio_handler.c" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/pio/pio_handler.h" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_acc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_crccu.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pdc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pio.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_tc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_twi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_uart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_udp.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_usart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/sam3s8.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/sam3s8.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/sam3sd8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/sam3sd8c.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/exceptions.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/exceptions.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/exceptions.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/exceptions.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/source/templates/system_sam3sd8.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/compiler.h" framework="" version="3.3.0" source="sam/utils/compiler.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/header_files/io.h" framework="" version="3.3.0" source="sam/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld" framework="" version="3.3.0" source="sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/make/Makefile.in" framework="" version="3.3.0" source="sam/utils/make/Makefile.in" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/preprocessor/mrepeat.h" framework="" version="3.3.0" source="sam/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/preprocessor/preprocessor.h" framework="" version="3.3.0" source="sam/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/preprocessor/stringz.h" framework="" version="3.3.0" source="sam/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/preprocessor/tpaste.h" framework="" version="3.3.0" source="sam/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/utils/status_codes.h" framework="" version="3.3.0" source="sam/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" framework="" version="3.3.0" source="thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/thirdparty/CMSIS/Include/core_cm3.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cm3.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/thirdparty/CMSIS/Include/core_cmFunc.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cmFunc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/thirdparty/CMSIS/Include/core_cmInstr.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cmInstr.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/thirdparty/CMSIS/README.txt" framework="" version="3.3.0" source="thirdparty/CMSIS/README.txt" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/thirdparty/CMSIS/license.txt" framework="" version="3.3.0" source="thirdparty/CMSIS/license.txt" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/pmc/pmc.c" framework="" version="" source="sam\drivers\pmc\pmc.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/pmc/pmc.h" framework="" version="" source="sam\drivers\pmc\pmc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/pmc/sleep.h" framework="" version="" source="sam\drivers\pmc\sleep.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/usart/usart.c" framework="" version="" source="sam\drivers\usart\usart.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/sam/drivers/usart/usart.h" framework="" version="" source="sam\drivers\usart\usart.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/sam3s/sysclk.c" framework="" version="" source="common\services\clock\sam3s\sysclk.c" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/sam3s/pll.h" framework="" version="" source="common\services\clock\sam3s\pll.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/sam3s/osc.h" framework="" version="" source="common\services\clock\sam3s\osc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/genclk.h" framework="" version="" source="common\services\clock\genclk.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/osc.h" framework="" version="" source="common\services\clock\osc.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/sam3s/sysclk.h" framework="" version="" source="common\services\clock\sam3s\sysclk.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/sam3s/genclk.h" framework="" version="" source="common\services\clock\sam3s\genclk.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/sysclk.h" framework="" version="" source="common\services\clock\sysclk.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/asf/common/services/clock/pll.h" framework="" version="" source="common\services\clock\pll.h" changed="False" content-id="Atmel.ASF" />
+ <file path="src/config/conf_clock.h" framework="" version="" source="common\services\clock\sam3s\module_config\conf_clock.h" changed="False" content-id="Atmel.ASF" />
+ </files>
+ <documentation help="" />
+ <offline-documentation help="" />
+ <dependencies>
+ <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.20.1" />
+ </dependencies>
+</framework-data>
</AsfFrameworkConfig>
<avrdevice>ATSAM3SD8C</avrdevice>
<avrdeviceseries>sam3sd</avrdeviceseries>
<Language>C</Language>
- <ToolchainName>com.Atmel.ARMGCC</ToolchainName>
+ <ToolchainName>com.Atmel.ARMGCC.C</ToolchainName>
<ArmGccProjectExtensions />
<OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
<OutputFileName>$(MSBuildProjectName)</OutputFileName>
@@ -182,117 +186,105 @@
</InterfaceProperties>
</ToolOptions>
</com_atmel_avrdbg_tool_samice>
+ <CacheFlash>true</CacheFlash>
+ <ProgFlashFromRam>true</ProgFlashFromRam>
+ <RamSnippetAddress />
+ <UncachedRange />
+ <preserveEEPROM>true</preserveEEPROM>
+ <BootSegment>2</BootSegment>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
- <ToolchainSettings>
- <ArmGcc>
- <armgcc.common.general.symbols>__SAM3SD8C__</armgcc.common.general.symbols>
- <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
- <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
- <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
- <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
- <armgcc.compiler.symbols.DefSymbols>
- <ListValues>
- <Value>BOARD=SAM3S_EK2</Value>
- <Value>__SAM3SD8C__</Value>
- </ListValues>
- </armgcc.compiler.symbols.DefSymbols>
- <armgcc.compiler.directories.IncludePaths>
- <ListValues>
- <Value>../src</Value>
- <Value>../src/asf/common/applications/user_application/sam3sd8c_sam3s_ek2</Value>
- <Value>../src/asf/common/boards</Value>
- <Value>../src/asf/common/services/gpio</Value>
- <Value>../src/asf/common/utils</Value>
- <Value>../src/asf/sam/boards</Value>
- <Value>../src/asf/sam/boards/sam3s_ek2</Value>
- <Value>../src/asf/sam/drivers/pio</Value>
- <Value>../src/asf/sam/utils</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/include</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/source/templates</Value>
- <Value>../src/asf/sam/utils/header_files</Value>
- <Value>../src/asf/sam/utils/preprocessor</Value>
- <Value>../src/asf/thirdparty/CMSIS/Include</Value>
- <Value>../src/config</Value>
- <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles</Value>
- <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include</Value>
- <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL</Value>
- <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3sd8\include</Value>
- <Value>../src/asf/sam/drivers/pmc</Value>
- <Value>../src/asf/sam/drivers/usart</Value>
- <Value>../src/asf/common/services/clock</Value>
- </ListValues>
- </armgcc.compiler.directories.IncludePaths>
- <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
- <armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>
- <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
- <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
- <armgcc.compiler.miscellaneous.OtherFlags>-pipe -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -Dprintf=iprintf</armgcc.compiler.miscellaneous.OtherFlags>
- <armgcc.linker.general.DoNotUseStandardStartFiles />
- <armgcc.linker.general.DoNotUseDefaultLibraries />
- <armgcc.linker.general.NoStartupOrDefaultLibs />
- <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
- <armgcc.linker.miscellaneous.LinkerFlags>-T../src/asf/sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb</armgcc.linker.miscellaneous.LinkerFlags>
- <armgcc.assembler.general.IncludePaths>
- <ListValues>
- <Value>../src</Value>
- <Value>../src/asf/common/applications/user_application/sam3sd8c_sam3s_ek2</Value>
- <Value>../src/asf/common/boards</Value>
- <Value>../src/asf/common/services/gpio</Value>
- <Value>../src/asf/common/utils</Value>
- <Value>../src/asf/sam/boards</Value>
- <Value>../src/asf/sam/boards/sam3s_ek2</Value>
- <Value>../src/asf/sam/drivers/pio</Value>
- <Value>../src/asf/sam/utils</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/include</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/source/templates</Value>
- <Value>../src/asf/sam/utils/header_files</Value>
- <Value>../src/asf/sam/utils/preprocessor</Value>
- <Value>../src/asf/thirdparty/CMSIS/Include</Value>
- <Value>../src/config</Value>
- <Value>../src/asf/sam/drivers/pmc</Value>
- <Value>../src/asf/sam/drivers/usart</Value>
- <Value>../src/asf/common/services/clock</Value>
- </ListValues>
- </armgcc.assembler.general.IncludePaths>
- <armgcc.preprocessingassembler.general.AssemblerFlags>-DBOARD=SAM3S_EK2 -D__SAM3SD8C__</armgcc.preprocessingassembler.general.AssemblerFlags>
- <armgcc.preprocessingassembler.general.IncludePaths>
- <ListValues>
- <Value>../src</Value>
- <Value>../src/asf/common/applications/user_application/sam3sd8c_sam3s_ek2</Value>
- <Value>../src/asf/common/boards</Value>
- <Value>../src/asf/common/services/gpio</Value>
- <Value>../src/asf/common/utils</Value>
- <Value>../src/asf/sam/boards</Value>
- <Value>../src/asf/sam/boards/sam3s_ek2</Value>
- <Value>../src/asf/sam/drivers/pio</Value>
- <Value>../src/asf/sam/utils</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/include</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/source/templates</Value>
- <Value>../src/asf/sam/utils/header_files</Value>
- <Value>../src/asf/sam/utils/preprocessor</Value>
- <Value>../src/asf/thirdparty/CMSIS/Include</Value>
- <Value>../src/config</Value>
- <Value>../src/asf/sam/drivers/pmc</Value>
- <Value>../src/asf/sam/drivers/usart</Value>
- <Value>../src/asf/common/services/clock</Value>
- </ListValues>
- </armgcc.preprocessingassembler.general.IncludePaths>
- </ArmGcc>
- </ToolchainSettings>
<GenerateHexFile>True</GenerateHexFile>
<GenerateMapFile>True</GenerateMapFile>
<GenerateListFile>True</GenerateListFile>
<GenerateEepFile>True</GenerateEepFile>
- </PropertyGroup>
- <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
<ToolchainSettings>
- <ArmGcc>
- <armgcc.common.general.symbols>__SAM3SD8C__</armgcc.common.general.symbols>
+ <ArmGcc xmlns="">
<armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
<armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
<armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
<armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+ <armgcc.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>BOARD=SAM3S_EK2</Value>
+ <Value>__SAM3SD8C__</Value>
+ </ListValues>
+ </armgcc.compiler.symbols.DefSymbols>
+ <armgcc.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>../src</Value>
+ <Value>../src/asf/common/applications/user_application/sam3sd8c_sam3s_ek2</Value>
+ <Value>../src/asf/common/boards</Value>
+ <Value>../src/asf/common/services/gpio</Value>
+ <Value>../src/asf/common/utils</Value>
+ <Value>../src/asf/sam/boards</Value>
+ <Value>../src/asf/sam/boards/sam3s_ek2</Value>
+ <Value>../src/asf/sam/drivers/pio</Value>
+ <Value>../src/asf/sam/utils</Value>
+ <Value>../src/asf/sam/utils/cmsis/sam3s8/include</Value>
+ <Value>../src/asf/sam/utils/cmsis/sam3s8/source/templates</Value>
+ <Value>../src/asf/sam/utils/header_files</Value>
+ <Value>../src/asf/sam/utils/preprocessor</Value>
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>
+ <Value>../src/config</Value>
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles</Value>
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include</Value>
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL</Value>
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3sd8\include</Value>
+ <Value>../src/asf/sam/drivers/pmc</Value>
+ <Value>../src/asf/sam/drivers/usart</Value>
+ <Value>../src/asf/common/services/clock</Value>
+ </ListValues>
+ </armgcc.compiler.directories.IncludePaths>
+ <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+ <armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+ <armgcc.compiler.miscellaneous.OtherFlags>-pipe -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -Dprintf=iprintf</armgcc.compiler.miscellaneous.OtherFlags>
+ <armgcc.linker.general.DoNotUseStandardStartFiles />
+ <armgcc.linker.general.DoNotUseDefaultLibraries />
+ <armgcc.linker.general.NoStartupOrDefaultLibs />
+ <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
+ <armgcc.linker.miscellaneous.LinkerFlags>-T../src/asf/sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb</armgcc.linker.miscellaneous.LinkerFlags>
+ <armgcc.preprocessingassembler.general.AssemblerFlags>-DBOARD=SAM3S_EK2 -D__SAM3SD8C__</armgcc.preprocessingassembler.general.AssemblerFlags>
+ <armgcc.preprocessingassembler.general.IncludePaths>
+ <ListValues>
+ <Value>../src</Value>
+ <Value>../src/asf/common/applications/user_application/sam3sd8c_sam3s_ek2</Value>
+ <Value>../src/asf/common/boards</Value>
+ <Value>../src/asf/common/services/gpio</Value>
+ <Value>../src/asf/common/utils</Value>
+ <Value>../src/asf/sam/boards</Value>
+ <Value>../src/asf/sam/boards/sam3s_ek2</Value>
+ <Value>../src/asf/sam/drivers/pio</Value>
+ <Value>../src/asf/sam/utils</Value>
+ <Value>../src/asf/sam/utils/cmsis/sam3s8/include</Value>
+ <Value>../src/asf/sam/utils/cmsis/sam3s8/source/templates</Value>
+ <Value>../src/asf/sam/utils/header_files</Value>
+ <Value>../src/asf/sam/utils/preprocessor</Value>
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>
+ <Value>../src/config</Value>
+ <Value>../src/asf/sam/drivers/pmc</Value>
+ <Value>../src/asf/sam/drivers/usart</Value>
+ <Value>../src/asf/common/services/clock</Value>
+ </ListValues>
+ </armgcc.preprocessingassembler.general.IncludePaths>
+</ArmGcc>
+ </ToolchainSettings>
+ </PropertyGroup>
+ <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+ <GenerateHexFile>True</GenerateHexFile>
+ <GenerateMapFile>True</GenerateMapFile>
+ <GenerateListFile>True</GenerateListFile>
+ <GenerateEepFile>True</GenerateEepFile>
+ <ToolchainSettings>
+ <ArmGcc xmlns="">
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
<armgcc.compiler.symbols.DefSymbols>
<ListValues>
<Value>BOARD=SAM3S_EK2</Value>
@@ -335,28 +327,6 @@
<armgcc.compiler.miscellaneous.OtherFlags>-pipe -Wall -Wextra -std=gnu99 -ffunction-sections -fdata-sections -Wformat=2 --param max-inline-insns-single=500 -Dprintf=iprintf</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>
<armgcc.linker.miscellaneous.LinkerFlags>-T../src/asf/sam/utils/linker_scripts/sam3s/sam3sd8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb</armgcc.linker.miscellaneous.LinkerFlags>
- <armgcc.assembler.general.IncludePaths>
- <ListValues>
- <Value>../src</Value>
- <Value>../src/asf/common/applications/user_application/sam3sd8c_sam3s_ek2</Value>
- <Value>../src/asf/common/boards</Value>
- <Value>../src/asf/common/services/gpio</Value>
- <Value>../src/asf/common/utils</Value>
- <Value>../src/asf/sam/boards</Value>
- <Value>../src/asf/sam/boards/sam3s_ek2</Value>
- <Value>../src/asf/sam/drivers/pio</Value>
- <Value>../src/asf/sam/utils</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/include</Value>
- <Value>../src/asf/sam/utils/cmsis/sam3s8/source/templates</Value>
- <Value>../src/asf/sam/utils/header_files</Value>
- <Value>../src/asf/sam/utils/preprocessor</Value>
- <Value>../src/asf/thirdparty/CMSIS/Include</Value>
- <Value>../src/config</Value>
- <Value>../src/asf/sam/drivers/pmc</Value>
- <Value>../src/asf/sam/drivers/usart</Value>
- <Value>../src/asf/common/services/clock</Value>
- </ListValues>
- </armgcc.assembler.general.IncludePaths>
<armgcc.preprocessingassembler.general.AssemblerFlags>-DBOARD=SAM3S_EK2 -D__SAM3SD8C__</armgcc.preprocessingassembler.general.AssemblerFlags>
<armgcc.preprocessingassembler.general.IncludePaths>
<ListValues>
@@ -382,10 +352,6 @@
</armgcc.preprocessingassembler.general.IncludePaths>
</ArmGcc>
</ToolchainSettings>
- <GenerateHexFile>True</GenerateHexFile>
- <GenerateMapFile>True</GenerateMapFile>
- <GenerateListFile>True</GenerateListFile>
- <GenerateEepFile>True</GenerateEepFile>
</PropertyGroup>
<ItemGroup>
<Compile Include="src\asf\thirdparty\FreeRTOS\include\croutine.h">
diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h
index a187314..ab51a5b 100644
--- a/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/FreeRTOSConfig.h
@@ -173,7 +173,7 @@
#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 130)
-#define configTOTAL_HEAP_SIZE (( size_t )(25000))
+#define configTOTAL_HEAP_SIZE (( size_t )(24000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY ( 0 )
#define configUSE_16_BIT_TICKS ( 0 )
@@ -237,7 +237,6 @@
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
-#define INCLUDE_pcTaskGetTaskName ( 0 )
#define INCLUDE_eTaskGetState ( 1 )
#define INCLUDE_xTimerPendFunctionCall ( 1 )
diff --git a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h
index 5279f99..5628347 100644
--- a/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_EFM32_Pearl_Gecko_Simplicity_Studio/FreeRTOSConfig.h
@@ -98,7 +98,7 @@
* See the comments at the top of main.c, main_full.c and main_low_power.c for
* more information.
*/
-#define configCREATE_LOW_POWER_DEMO 0
+#define configCREATE_LOW_POWER_DEMO 1
/* Some configuration is dependent on the demo being built. */
#if( configCREATE_LOW_POWER_DEMO == 0 )
@@ -150,7 +150,7 @@
#define configCPU_CLOCK_HZ ( CMU_ClockFreqGet( cmuClock_CORE ) )
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE (( unsigned short ) 130)
-#define configTOTAL_HEAP_SIZE (( size_t )(25000))
+#define configTOTAL_HEAP_SIZE (( size_t )(24000))
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY ( 0 )
#define configUSE_16_BIT_TICKS ( 0 )
@@ -214,7 +214,6 @@
#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )
#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )
#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )
-#define INCLUDE_pcTaskGetTaskName ( 0 )
#define INCLUDE_eTaskGetState ( 1 )
#define INCLUDE_xTimerPendFunctionCall ( 1 )
diff --git a/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h
index 82d11b8..81ca260 100644
--- a/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h
@@ -124,7 +124,6 @@
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
-#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj
index e3941f3..3a53b9e 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj
+++ b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/RTOSDemo.cproj
@@ -2,7 +2,7 @@
<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">
<PropertyGroup>
<SchemaVersion>2.0</SchemaVersion>
- <ProjectVersion>6.2</ProjectVersion>
+ <ProjectVersion>7.0</ProjectVersion>
<ProjectGuid>{257fe152-8d54-41ca-afe7-777de72fe329}</ProjectGuid>
<Name>$(MSBuildProjectName)</Name>
<AssemblyName>$(MSBuildProjectName)</AssemblyName>
@@ -180,7 +180,7 @@
<documentation help="http://asf.atmel.com/docs/3.11.0/common.applications.user_application.sam4e_ek/html/index.html" />
<offline-documentation help="" />
<dependencies>
- <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.11.0" />
+ <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.20.1" />
</dependencies>
<project id="common.applications.user_application.sam4e_ek" value="Add" config="" content-id="Atmel.ASF" />
<board id="board.sam4e_ek" value="Add" config="" content-id="Atmel.ASF" />
@@ -219,6 +219,7 @@
<ToolName>J-Link</ToolName>
</com_atmel_avrdbg_tool_samice>
<avrtoolinterface>SWD</avrtoolinterface>
+ <preserveEEPROM>true</preserveEEPROM>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
<ToolchainSettings>
@@ -380,12 +381,13 @@
<Value>../src/ASF/sam/drivers/tc</Value>
</ListValues>
</armgcc.compiler.directories.IncludePaths>
+ <armgcc.compiler.optimization.level>Optimize (-O1)</armgcc.compiler.optimization.level>
<armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>
<armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
<armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
<armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
<armgcc.compiler.warnings.ExtraWarnings>True</armgcc.compiler.warnings.ExtraWarnings>
- <armgcc.compiler.miscellaneous.OtherFlags>-pipe -fno-strict-aliasing -Wall -Wextra -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4</armgcc.compiler.miscellaneous.OtherFlags>
+ <armgcc.compiler.miscellaneous.OtherFlags>-pipe -fno-strict-aliasing -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -mfloat-abi=softfp -mfpu=vfpv4 -Wno-attributes -Wno-unused-function</armgcc.compiler.miscellaneous.OtherFlags>
<armgcc.linker.libraries.Libraries>
<ListValues>
<Value>m</Value>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h
index 8c9a5e4..943eed1 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_ATSAM4E_Atmel_Studio/src/ASF/sam/utils/compiler.h
@@ -153,12 +153,14 @@
* heuristics and inline the function no matter how big it thinks it
* becomes.
*/
-#if defined(__CC_ARM)
-# define __always_inline __forceinline
-#elif (defined __GNUC__)
-# define __always_inline inline __attribute__((__always_inline__))
-#elif (defined __ICCARM__)
-# define __always_inline _Pragma("inline=forced")
+#ifndef __always_inline
+ #if defined(__CC_ARM)
+ # define __always_inline __forceinline
+ #elif (defined __GNUC__)
+ # define __always_inline inline __attribute__((__always_inline__))
+ #elif (defined __ICCARM__)
+ # define __always_inline _Pragma("inline=forced")
+ #endif
#endif
/*! \brief This macro is used to test fatal errors.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c
index 11adcb5..e9bd14c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c
@@ -109,15 +109,15 @@
/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate
interrupts at a low frequency. The purpose being to bring the CPU out of its
sleep mode by an interrupt other than the tick interrupt, and therefore
-allowing an additional past through the code to be tested. */
+allowing an additional paths through the code to be tested. */
#define lpINCLUDE_TEST_TIMER 0
/* Some registers are accessed directly as the library is not compatible with
all the compilers used. */
-#define lpHTIMER_PRELOAD_REGISTER ( * ( uint16_t * ) 0x40009800 )
-#define lpHTIMER_CONTROL_REGISTER ( * ( uint16_t * ) 0x40009804 )
-#define lpHTIMER_COUNT_REGISTER ( * ( uint16_t * ) 0x40009808 )
-#define lpEC_GIRQ17_ENABLE_SET ( * ( uint32_t * ) 0x4000C0B8 )
+#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 )
+#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 )
+#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 )
+#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 )
#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )
/*
@@ -378,7 +378,7 @@
/* Undo the adjustment that was made to the reload value to account
for the fact that a time slice was part way through when this
function was called before working out how many complete tick
- periods this represents. (could have used [ulExpectedIdleTime *
+ periods this represents. (could have used [ulExpectedIdleTime *
ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on
the previous line, but this way avoids the multiplication). */
ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep );
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
index 1f5593a..e365dbf 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/.project
@@ -166,7 +166,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780710</id>
+ <id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -175,7 +175,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780715</id>
+ <id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -184,7 +184,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780721</id>
+ <id>1458999824885</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -193,7 +193,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780726</id>
+ <id>1458999824895</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -202,7 +202,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780730</id>
+ <id>1458999824895</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -211,7 +211,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780734</id>
+ <id>1458999824905</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -220,7 +220,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780739</id>
+ <id>1458999824905</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -229,7 +229,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780744</id>
+ <id>1458999824915</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -238,7 +238,7 @@
</matcher>
</filter>
<filter>
- <id>1424443780748</id>
+ <id>1458999824915</id>
<name>driverlib</name>
<type>5</type>
<matcher>
@@ -247,6 +247,15 @@
</matcher>
</filter>
<filter>
+ <id>1458999824925</id>
+ <name>driverlib</name>
+ <type>5</type>
+ <matcher>
+ <id>org.eclipse.ui.ide.multiFilter</id>
+ <arguments>1.0-name-matches-false-false-sysctl.c</arguments>
+ </matcher>
+ </filter>
+ <filter>
<id>1423578948112</id>
<name>system</name>
<type>9</type>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
index 52003a7..6ae9113 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/FreeRTOSConfig.h
@@ -124,7 +124,6 @@
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
-#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
index f3ab790..1bf878f 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/IntQueueTimer.c
@@ -104,17 +104,17 @@
void vInitialiseTimerForIntQueueTest( void )
{
/* Configure the timer channels. */
- MAP_Timer32_initModule( TIMER32_0_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
- MAP_Timer32_setCount( TIMER32_0_MODULE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
- MAP_Timer32_enableInterrupt( TIMER32_0_MODULE );
- MAP_Timer32_startTimer( TIMER32_0_MODULE, false );
+ MAP_Timer32_initModule( (uint32_t)TIMER32_0_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
+ MAP_Timer32_setCount( (uint32_t)TIMER32_0_BASE, CS_getMCLK() / tmrTIMER_0_FREQUENCY );
+ MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_0_BASE );
+ MAP_Timer32_startTimer( (uint32_t)TIMER32_0_BASE, false );
MAP_Interrupt_setPriority( INT_T32_INT1, tmrLOWER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT1 );
- MAP_Timer32_initModule( TIMER32_1_MODULE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
- MAP_Timer32_setCount( TIMER32_1_MODULE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
- MAP_Timer32_enableInterrupt( TIMER32_1_MODULE );
- MAP_Timer32_startTimer( TIMER32_1_MODULE, false );
+ MAP_Timer32_initModule( (uint32_t)TIMER32_1_BASE, TIMER32_PRESCALER_1, TIMER32_32BIT, TIMER32_PERIODIC_MODE );
+ MAP_Timer32_setCount( (uint32_t)TIMER32_1_BASE, CS_getMCLK() / tmrTIMER_1_FREQUENCY );
+ MAP_Timer32_enableInterrupt( (uint32_t)TIMER32_1_BASE );
+ MAP_Timer32_startTimer( (uint32_t)TIMER32_1_BASE, false );
MAP_Interrupt_setPriority( INT_T32_INT2, tmrHIGHER_PRIORITY );
MAP_Interrupt_enableInterrupt( INT_T32_INT2 );
}
@@ -122,14 +122,14 @@
void vT32_0_Handler( void )
{
- MAP_Timer32_clearInterruptFlag( TIMER32_0_MODULE );
+ MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_0_BASE );
portYIELD_FROM_ISR( xFirstTimerHandler() );
}
/*-----------------------------------------------------------*/
void vT32_1_Handler( void )
{
- MAP_Timer32_clearInterruptFlag( TIMER32_1_MODULE );
+ MAP_Timer32_clearInterruptFlag( (uint32_t)TIMER32_1_BASE );
portYIELD_FROM_ISR( xSecondTimerHandler() );
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
index ef83296..0cec2db 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/RegTest.c
@@ -68,7 +68,7 @@
*/
-__asm vRegTest1Implementation( void )
+__asm void vRegTest1Implementation( void )
{
PRESERVE8
IMPORT ulRegTest1LoopCounter
@@ -251,7 +251,7 @@
}
/*-----------------------------------------------------------*/
-__asm vRegTest2Implementation( void )
+__asm void vRegTest2Implementation( void )
{
PRESERVE8
IMPORT ulRegTest2LoopCounter
@@ -443,7 +443,7 @@
}
/*-----------------------------------------------------------*/
-__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
+__asm void vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )
{
PRESERVE8
@@ -460,7 +460,7 @@
}
/*-----------------------------------------------------------*/
-__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
+__asm void ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )
{
PRESERVE8
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
index 8135502..21d196a 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/Full_Demo/serial.c
@@ -107,7 +107,7 @@
static volatile const signed char *pcStringStart = NULL, *pcStringEnd = NULL;
static volatile TaskHandle_t xTransmittingTask = NULL;
-static EUSCI_A0_Type * const pxUARTA0 = ( EUSCI_A0_Type * ) EUSCI_A0_MODULE;
+static EUSCI_A_Type * const pxUARTA0 = ( EUSCI_A_Type * ) EUSCI_A0_BASE;
/* UART Configuration for 19200 baud. Value generated using the tool provided
on the following page:
@@ -137,10 +137,10 @@
configASSERT( xRxQueue );
/* Use the library functions to initialise and enable the UART. */
- MAP_UART_initModule( EUSCI_A0_MODULE, &xUARTConfig );
- MAP_UART_enableModule( EUSCI_A0_MODULE );
- MAP_UART_clearInterruptFlag( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
- MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_RECEIVE_INTERRUPT );
+ MAP_UART_initModule( EUSCI_A0_BASE, &xUARTConfig );
+ MAP_UART_enableModule( EUSCI_A0_BASE );
+ MAP_UART_clearInterruptFlag( EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT );
+ MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT );
/* The interrupt handler uses the FreeRTOS API function so its priority must
be at or below the configured maximum system call interrupt priority.
@@ -191,11 +191,11 @@
pcStringEnd = pcStringStart + usStringLength;
/* Start to send the first byte. */
- pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcString;
+ pxUARTA0->TXBUF = ( uint_fast8_t ) *pcString;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
- MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
+ MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
}
/*-----------------------------------------------------------*/
@@ -223,11 +223,11 @@
pcStringEnd = pcStringStart + sizeof( cOutChar );
/* Start to send the byte. */
- pxUARTA0->rTXBUF.r = ( uint_fast8_t ) cOutChar;
+ pxUARTA0->TXBUF = ( uint_fast8_t ) cOutChar;
/* Enable the interrupt then wait for the byte to be sent. The interrupt
will be disabled again in the ISR. */
- MAP_UART_enableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
+ MAP_UART_enableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
ulTaskNotifyTake( pdTRUE, xMaxWaitTime );
return pdPASS;
@@ -247,12 +247,12 @@
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
uint_fast8_t xInterruptStatus;
- xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_MODULE );
+ xInterruptStatus = MAP_UART_getEnabledInterruptStatus( EUSCI_A0_BASE );
if( ( xInterruptStatus & EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG ) != 0x00 )
{
/* Obtain the character. */
- ucChar = MAP_UART_receiveData( EUSCI_A0_MODULE );
+ ucChar = MAP_UART_receiveData( EUSCI_A0_BASE );
/* Send the character to the queue. Note the comments at the top of this
file with regards to the inefficiency of this method for anything other than
@@ -277,13 +277,13 @@
/* This is probably quite a heavy wait function just for writing to
the Tx register. An optimised design would probably replace this
with a simple register write. */
- pxUARTA0->rTXBUF.r = ( uint_fast8_t ) *pcStringStart;
+ pxUARTA0->TXBUF = ( uint_fast8_t ) *pcStringStart;
}
else
{
/* No more characters to send. Disable the interrupt and notify the
task, if the task is waiting. */
- MAP_UART_disableInterrupt( EUSCI_A0_MODULE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
+ MAP_UART_disableInterrupt( EUSCI_A0_BASE, EUSCI_A_UART_TRANSMIT_INTERRUPT );
if( xTransmittingTask != NULL )
{
vTaskNotifyGiveFromISR( xTransmittingTask, &xHigherPriorityTaskWoken );
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
index b34f889..4f34c9b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewd
@@ -12,7 +12,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>26</version>
+ <version>27</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -45,7 +45,7 @@
</option>
<option>
<name>MemFile</name>
- <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\MSP432P401R.svd</state>
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\MSP432P401R.ddf</state>
</option>
<option>
<name>RunToEnable</name>
@@ -85,11 +85,11 @@
</option>
<option>
<name>OCDynDriverList</name>
- <state>IJET_ID</state>
+ <state>CMSISDAP_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
- <state>7.40.1.8463</state>
+ <state>7.50.3.10745</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
@@ -207,6 +207,10 @@
<name>OCMulticoreSlaveConfiguration</name>
<state></state>
</option>
+ <option>
+ <name>OCDownloadExtraImage</name>
+ <state>1</state>
+ </option>
</data>
</settings>
<settings>
@@ -1064,7 +1068,7 @@
<name>PEMICRO_ID</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>1</version>
+ <version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -1076,19 +1080,6 @@
<state>1</state>
</option>
<option>
- <name>CCPEMicroInterfaceList</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCPEMicroResetDelay</name>
- <state></state>
- </option>
- <option>
- <name>CCPEMicroJtagSpeed</name>
- <state>#UNINITIALIZED#</state>
- </option>
- <option>
<name>CCJPEMicroShowSettings</name>
<state>0</state>
</option>
@@ -1100,36 +1091,6 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
- <option>
- <name>CCPEMicroUSBDevice</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCPEMicroSerialPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCJPEMicroTCPIPAutoScanNetwork</name>
- <state>1</state>
- </option>
- <option>
- <name>CCPEMicroTCPIP</name>
- <state>10.0.0.1</state>
- </option>
- <option>
- <name>CCPEMicroCommCmdLineProducer</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSTLinkInterfaceRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSTLinkInterfaceCmdLine</name>
- <state>0</state>
- </option>
</data>
</settings>
<settings>
@@ -1193,7 +1154,7 @@
<name>STLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>2</version>
+ <version>3</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -1225,6 +1186,71 @@
<name>CCSwoClockEdit</name>
<state>2000</state>
</option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCSTLinkDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkJtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -1256,7 +1282,7 @@
<name>XDS100_ID</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>2</version>
+ <version>4</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -1276,11 +1302,6 @@
<state>C:\ti\ccs_base</state>
</option>
<option>
- <name>CCXds100InterfaceList</name>
- <version>2</version>
- <state>9</state>
- </option>
- <option>
<name>BoardFile</name>
<state>Browse to your board file</state>
</option>
@@ -1292,6 +1313,129 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
+ <option>
+ <name>CCXds100BreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100DoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCXds100CatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CpuClockEdit</name>
+ <state>72.0</state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockEdit</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCXds100HWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ResetList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100JtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ProbeList</name>
+ <version>0</version>
+ <state>4</state>
+ </option>
</data>
</settings>
<debuggerPlugins>
@@ -1300,6 +1444,10 @@
<loadFlag>0</loadFlag>
</plugin>
<plugin>
+ <file>$TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
@@ -1379,7 +1527,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>26</version>
+ <version>27</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -1574,6 +1722,10 @@
<name>OCMulticoreSlaveConfiguration</name>
<state></state>
</option>
+ <option>
+ <name>OCDownloadExtraImage</name>
+ <state>1</state>
+ </option>
</data>
</settings>
<settings>
@@ -2431,7 +2583,7 @@
<name>PEMICRO_ID</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>1</version>
+ <version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -2443,19 +2595,6 @@
<state>1</state>
</option>
<option>
- <name>CCPEMicroInterfaceList</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCPEMicroResetDelay</name>
- <state></state>
- </option>
- <option>
- <name>CCPEMicroJtagSpeed</name>
- <state>#UNINITIALIZED#</state>
- </option>
- <option>
<name>CCJPEMicroShowSettings</name>
<state>0</state>
</option>
@@ -2467,36 +2606,6 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
- <option>
- <name>CCPEMicroUSBDevice</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCPEMicroSerialPort</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCJPEMicroTCPIPAutoScanNetwork</name>
- <state>1</state>
- </option>
- <option>
- <name>CCPEMicroTCPIP</name>
- <state>10.0.0.1</state>
- </option>
- <option>
- <name>CCPEMicroCommCmdLineProducer</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSTLinkInterfaceRadio</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSTLinkInterfaceCmdLine</name>
- <state>0</state>
- </option>
</data>
</settings>
<settings>
@@ -2560,7 +2669,7 @@
<name>STLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>2</version>
+ <version>3</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -2592,6 +2701,71 @@
<name>CCSwoClockEdit</name>
<state>2000</state>
</option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$PROJ_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCSTLinkDoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkCatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCSTLinkUsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSTLinkJtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -2623,7 +2797,7 @@
<name>XDS100_ID</name>
<archiveVersion>2</archiveVersion>
<data>
- <version>2</version>
+ <version>4</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -2643,11 +2817,6 @@
<state></state>
</option>
<option>
- <name>CCXds100InterfaceList</name>
- <version>2</version>
- <state>0</state>
- </option>
- <option>
<name>BoardFile</name>
<state></state>
</option>
@@ -2659,6 +2828,129 @@
<name>LogFile</name>
<state>$PROJ_DIR$\cspycomm.log</state>
</option>
+ <option>
+ <name>CCXds100BreakpointRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100DoUpdateBreakpoints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UpdateBreakpoints</name>
+ <state>_call_main</state>
+ </option>
+ <option>
+ <name>CCXds100CatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCORERESET</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchMMERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchNOCPERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchCHRERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchSTATERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchBUSERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchINTERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchHARDERR</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CatchDummy</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100CpuClockEdit</name>
+ <state>72.0</state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockAuto</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100SwoClockEdit</name>
+ <state>1000</state>
+ </option>
+ <option>
+ <name>CCXds100HWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ResetList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNo</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCXds100UsbSerialNoSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100JtagSpeedList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100InterfaceCmdLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCXds100ProbeList</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
</data>
</settings>
<debuggerPlugins>
@@ -2667,6 +2959,10 @@
<loadFlag>0</loadFlag>
</plugin>
<plugin>
+ <file>$TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
index 28e396c..c8ddfdb 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewp
@@ -12,7 +12,7 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
- <version>22</version>
+ <version>24</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -28,11 +28,6 @@
<state>IAR_Debug\List</state>
</option>
<option>
- <name>Variant</name>
- <version>21</version>
- <state>40</state>
- </option>
- <option>
<name>GEndianMode</name>
<state>0</state>
</option>
@@ -59,11 +54,6 @@
<state>0</state>
</option>
<option>
- <name>FPU</name>
- <version>3</version>
- <state>5</state>
- </option>
- <option>
<name>OGCoreOrChip</name>
<state>1</state>
</option>
@@ -87,7 +77,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
- <state>7.30.4.8186</state>
+ <state>7.50.3.10745</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -136,13 +126,8 @@
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
</option>
<option>
- <name>GFPUCoreSlave</name>
- <version>21</version>
- <state>40</state>
- </option>
- <option>
<name>GBECoreSlave</name>
- <version>21</version>
+ <version>22</version>
<state>40</state>
</option>
<option>
@@ -157,6 +142,34 @@
<name>GRuntimeLibThreads</name>
<state>0</state>
</option>
+ <option>
+ <name>CoreVariant</name>
+ <version>22</version>
+ <state>39</state>
+ </option>
+ <option>
+ <name>GFPUDeviceSlave</name>
+ <state>MSP432P401R TexasInstruments MSP432P401R</state>
+ </option>
+ <option>
+ <name>FPU2</name>
+ <version>0</version>
+ <state>4</state>
+ </option>
+ <option>
+ <name>NrRegs</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>NEON</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave2</name>
+ <version>22</version>
+ <state>39</state>
+ </option>
</data>
</settings>
<settings>
@@ -594,7 +607,7 @@
<debug>1</debug>
<option>
<name>OOCOutputFormat</name>
- <version>2</version>
+ <version>3</version>
<state>0</state>
</option>
<option>
@@ -641,7 +654,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
- <version>16</version>
+ <version>17</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -722,7 +735,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
- <state>$TOOLKIT_DIR$\config\linker\TexasInstruments\MSP432P401R.icf</state>
+ <state>$TOOLKIT_DIR$\config\linker\TexasInstruments\msp432p401r.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
@@ -925,6 +938,10 @@
<name>IlinkThreadsSlave</name>
<state>1</state>
</option>
+ <option>
+ <name>IlinkLogCallGraph</name>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -964,7 +981,7 @@
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
- <version>22</version>
+ <version>24</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -980,11 +997,6 @@
<state>Release\List</state>
</option>
<option>
- <name>Variant</name>
- <version>21</version>
- <state>0</state>
- </option>
- <option>
<name>GEndianMode</name>
<state>0</state>
</option>
@@ -1011,11 +1023,6 @@
<state>0</state>
</option>
<option>
- <name>FPU</name>
- <version>3</version>
- <state>0</state>
- </option>
- <option>
<name>OGCoreOrChip</name>
<state>1</state>
</option>
@@ -1039,7 +1046,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
- <state>6.30.1.53141</state>
+ <state>7.50.3.10745</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@@ -1051,7 +1058,7 @@
</option>
<option>
<name>OGChipSelectEditMenu</name>
- <state>TM4L2001H8PZI TexasInstruments TM4L2001H8PZI</state>
+ <state>Default None</state>
</option>
<option>
<name>GenLowLevelInterface</name>
@@ -1088,13 +1095,8 @@
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
</option>
<option>
- <name>GFPUCoreSlave</name>
- <version>21</version>
- <state>0</state>
- </option>
- <option>
<name>GBECoreSlave</name>
- <version>21</version>
+ <version>22</version>
<state>0</state>
</option>
<option>
@@ -1109,6 +1111,34 @@
<name>GRuntimeLibThreads</name>
<state>0</state>
</option>
+ <option>
+ <name>CoreVariant</name>
+ <version>22</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GFPUDeviceSlave</name>
+ <state>Default None</state>
+ </option>
+ <option>
+ <name>FPU2</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NrRegs</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NEON</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave2</name>
+ <version>22</version>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -1538,7 +1568,7 @@
<debug>0</debug>
<option>
<name>OOCOutputFormat</name>
- <version>2</version>
+ <version>3</version>
<state>0</state>
</option>
<option>
@@ -1585,7 +1615,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
- <version>16</version>
+ <version>17</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@@ -1869,6 +1899,10 @@
<name>IlinkThreadsSlave</name>
<state>1</state>
</option>
+ <option>
+ <name>IlinkLogCallGraph</name>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -1919,6 +1953,9 @@
<name>$PROJ_DIR$\driverlib\pcm.c</name>
</file>
<file>
+ <name>$PROJ_DIR$\driverlib\sysctl.c</name>
+ </file>
+ <file>
<name>$PROJ_DIR$\driverlib\timer32.c</name>
</file>
<file>
@@ -2074,6 +2111,9 @@
<file>
<name>$PROJ_DIR$\system\IAR\msp432_startup_ewarm.c</name>
</file>
+ <file>
+ <name>$PROJ_DIR$\system\IAR\system_msp432p401r.c</name>
+ </file>
</group>
<file>
<name>$PROJ_DIR$\FreeRTOSConfig.h</name>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
index e678aea..6c4e45c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.ewt
@@ -3,12 +3,974 @@
<project>
<fileVersion>2</fileVersion>
<configuration>
- <name>Debug</name>
+ <name>IAR_Debug</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
+ <name>C-STAT</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <version>1</version>
+ <cstatargs>
+ <useExtraArgs>0</useExtraArgs>
+ <extraArgs></extraArgs>
+ <analyzeTimeout>600</analyzeTimeout>
+ <enableParallel>0</enableParallel>
+ <parallelThreads>2</parallelThreads>
+ </cstatargs>
+ <cstatsettings>
+ <package checked="true" name="STDCHECKS">
+ <group checked="true" name="ARR">
+ <check checked="true" name="ARR-inv-index-pos"/>
+ <check checked="true" name="ARR-inv-index-ptr-pos"/>
+ <check checked="true" name="ARR-inv-index-ptr"/>
+ <check checked="true" name="ARR-inv-index"/>
+ <check checked="true" name="ARR-neg-index"/>
+ <check checked="true" name="ARR-uninit-index"/>
+ </group>
+ <group checked="true" name="ATH">
+ <check checked="true" name="ATH-cmp-float"/>
+ <check checked="true" name="ATH-cmp-unsign-neg"/>
+ <check checked="true" name="ATH-cmp-unsign-pos"/>
+ <check checked="true" name="ATH-div-0-assign"/>
+ <check checked="true" name="ATH-div-0-cmp-aft"/>
+ <check checked="true" name="ATH-div-0-cmp-bef"/>
+ <check checked="true" name="ATH-div-0-interval"/>
+ <check checked="true" name="ATH-div-0-pos"/>
+ <check checked="true" name="ATH-div-0-unchk-global"/>
+ <check checked="true" name="ATH-div-0-unchk-local"/>
+ <check checked="true" name="ATH-div-0-unchk-param"/>
+ <check checked="true" name="ATH-div-0"/>
+ <check checked="true" name="ATH-inc-bool"/>
+ <check checked="true" name="ATH-malloc-overrun"/>
+ <check checked="true" name="ATH-neg-check-nonneg"/>
+ <check checked="true" name="ATH-neg-check-pos"/>
+ <check checked="true" name="ATH-new-overrun"/>
+ <check checked="false" name="ATH-overflow-cast"/>
+ <check checked="true" name="ATH-overflow"/>
+ <check checked="true" name="ATH-shift-bounds"/>
+ <check checked="true" name="ATH-shift-neg"/>
+ <check checked="true" name="ATH-sizeof-by-sizeof"/>
+ </group>
+ <group checked="true" name="CAST">
+ <check checked="false" name="CAST-old-style"/>
+ </group>
+ <group checked="true" name="CATCH">
+ <check checked="true" name="CATCH-object-slicing"/>
+ <check checked="false" name="CATCH-xtor-bad-member"/>
+ </group>
+ <group checked="true" name="COMMA">
+ <check checked="false" name="COMMA-overload"/>
+ </group>
+ <group checked="true" name="COMMENT">
+ <check checked="true" name="COMMENT-nested"/>
+ </group>
+ <group checked="false" name="CONCURRENCY">
+ <check checked="true" name="CONCURRENCY-double-lock"/>
+ <check checked="true" name="CONCURRENCY-double-unlock"/>
+ <check checked="true" name="CONCURRENCY-lock-no-unlock"/>
+ <check checked="true" name="CONCURRENCY-sleep-while-locking"/>
+ </group>
+ <group checked="true" name="CONST">
+ <check checked="false" name="CONST-local"/>
+ <check checked="true" name="CONST-member-ret"/>
+ <check checked="false" name="CONST-param"/>
+ </group>
+ <group checked="true" name="COP">
+ <check checked="true" name="COP-alloc-ctor"/>
+ <check checked="true" name="COP-assign-op-ret"/>
+ <check checked="true" name="COP-assign-op-self"/>
+ <check checked="true" name="COP-assign-op"/>
+ <check checked="true" name="COP-copy-ctor"/>
+ <check checked="true" name="COP-dealloc-dtor"/>
+ <check checked="true" name="COP-dtor-throw"/>
+ <check checked="true" name="COP-dtor"/>
+ <check checked="true" name="COP-init-order"/>
+ <check checked="true" name="COP-init-uninit"/>
+ <check checked="true" name="COP-member-uninit"/>
+ </group>
+ <group checked="true" name="CPU">
+ <check checked="true" name="CPU-ctor-call-virt"/>
+ <check checked="false" name="CPU-ctor-implicit"/>
+ <check checked="true" name="CPU-delete-throw"/>
+ <check checked="true" name="CPU-delete-void"/>
+ <check checked="true" name="CPU-dtor-call-virt"/>
+ <check checked="true" name="CPU-malloc-class"/>
+ <check checked="true" name="CPU-nonvirt-dtor"/>
+ <check checked="true" name="CPU-return-ref-to-class-data"/>
+ </group>
+ <group checked="true" name="DECL">
+ <check checked="false" name="DECL-implicit-int"/>
+ </group>
+ <group checked="true" name="DEFINE">
+ <check checked="true" name="DEFINE-hash-multiple"/>
+ </group>
+ <group checked="true" name="ENUM">
+ <check checked="false" name="ENUM-bounds"/>
+ </group>
+ <group checked="true" name="EXP">
+ <check checked="true" name="EXP-cond-assign"/>
+ <check checked="true" name="EXP-dangling-else"/>
+ <check checked="true" name="EXP-loop-exit"/>
+ <check checked="false" name="EXP-main-ret-int"/>
+ <check checked="false" name="EXP-null-stmt"/>
+ <check checked="false" name="EXP-stray-semicolon"/>
+ </group>
+ <group checked="true" name="EXPR">
+ <check checked="true" name="EXPR-const-overflow"/>
+ </group>
+ <group checked="false" name="FPT">
+ <check checked="true" name="FPT-arith-address"/>
+ <check checked="true" name="FPT-arith"/>
+ <check checked="true" name="FPT-cmp-null"/>
+ <check checked="false" name="FPT-literal"/>
+ <check checked="true" name="FPT-misuse"/>
+ </group>
+ <group checked="true" name="FUNC">
+ <check checked="false" name="FUNC-implicit-decl"/>
+ <check checked="false" name="FUNC-unprototyped-all"/>
+ <check checked="true" name="FUNC-unprototyped-used"/>
+ </group>
+ <group checked="true" name="INCLUDE">
+ <check checked="false" name="INCLUDE-c-file"/>
+ </group>
+ <group checked="true" name="INT">
+ <check checked="false" name="INT-use-signed-as-unsigned-pos"/>
+ <check checked="true" name="INT-use-signed-as-unsigned"/>
+ </group>
+ <group checked="true" name="ITR">
+ <check checked="true" name="ITR-end-cmp-aft"/>
+ <check checked="true" name="ITR-end-cmp-bef"/>
+ <check checked="true" name="ITR-invalidated"/>
+ <check checked="true" name="ITR-mismatch-alg"/>
+ <check checked="true" name="ITR-store"/>
+ <check checked="true" name="ITR-uninit"/>
+ </group>
+ <group checked="true" name="LIB">
+ <check checked="false" name="LIB-bsearch-overrun-pos"/>
+ <check checked="false" name="LIB-bsearch-overrun"/>
+ <check checked="false" name="LIB-buf-size"/>
+ <check checked="false" name="LIB-fn-unsafe"/>
+ <check checked="false" name="LIB-fread-overrun-pos"/>
+ <check checked="true" name="LIB-fread-overrun"/>
+ <check checked="false" name="LIB-memchr-overrun-pos"/>
+ <check checked="true" name="LIB-memchr-overrun"/>
+ <check checked="false" name="LIB-memcpy-overrun-pos"/>
+ <check checked="true" name="LIB-memcpy-overrun"/>
+ <check checked="false" name="LIB-memset-overrun-pos"/>
+ <check checked="true" name="LIB-memset-overrun"/>
+ <check checked="false" name="LIB-putenv"/>
+ <check checked="false" name="LIB-qsort-overrun-pos"/>
+ <check checked="false" name="LIB-qsort-overrun"/>
+ <check checked="true" name="LIB-return-const"/>
+ <check checked="true" name="LIB-return-error"/>
+ <check checked="true" name="LIB-return-leak"/>
+ <check checked="true" name="LIB-return-neg"/>
+ <check checked="true" name="LIB-return-null"/>
+ <check checked="false" name="LIB-sprintf-overrun"/>
+ <check checked="false" name="LIB-std-sort-overrun-pos"/>
+ <check checked="true" name="LIB-std-sort-overrun"/>
+ <check checked="false" name="LIB-strcat-overrun-pos"/>
+ <check checked="true" name="LIB-strcat-overrun"/>
+ <check checked="false" name="LIB-strcpy-overrun-pos"/>
+ <check checked="true" name="LIB-strcpy-overrun"/>
+ <check checked="false" name="LIB-strncat-overrun-pos"/>
+ <check checked="true" name="LIB-strncat-overrun"/>
+ <check checked="false" name="LIB-strncmp-overrun-pos"/>
+ <check checked="true" name="LIB-strncmp-overrun"/>
+ <check checked="false" name="LIB-strncpy-overrun-pos"/>
+ <check checked="true" name="LIB-strncpy-overrun"/>
+ </group>
+ <group checked="true" name="LOGIC">
+ <check checked="false" name="LOGIC-overload"/>
+ </group>
+ <group checked="false" name="MEM">
+ <check checked="true" name="MEM-alias-double-free"/>
+ <check checked="true" name="MEM-delete-array-op"/>
+ <check checked="true" name="MEM-delete-op"/>
+ <check checked="true" name="MEM-double-free-alias"/>
+ <check checked="true" name="MEM-double-free-some"/>
+ <check checked="true" name="MEM-double-free"/>
+ <check checked="true" name="MEM-free-field"/>
+ <check checked="true" name="MEM-free-fptr"/>
+ <check checked="false" name="MEM-free-no-alloc-struct"/>
+ <check checked="true" name="MEM-free-no-alloc"/>
+ <check checked="true" name="MEM-free-no-use"/>
+ <check checked="true" name="MEM-free-op"/>
+ <check checked="true" name="MEM-free-struct-field"/>
+ <check checked="true" name="MEM-free-variable-alias"/>
+ <check checked="true" name="MEM-free-variable"/>
+ <check checked="true" name="MEM-leak-alias"/>
+ <check checked="false" name="MEM-leak"/>
+ <check checked="false" name="MEM-malloc-arith"/>
+ <check checked="true" name="MEM-malloc-diff-type"/>
+ <check checked="true" name="MEM-malloc-sizeof-ptr"/>
+ <check checked="true" name="MEM-malloc-sizeof"/>
+ <check checked="false" name="MEM-malloc-strlen"/>
+ <check checked="true" name="MEM-realloc-diff-type"/>
+ <check checked="true" name="MEM-return-free"/>
+ <check checked="true" name="MEM-return-no-assign"/>
+ <check checked="true" name="MEM-stack-alias"/>
+ <check checked="true" name="MEM-stack-global-alias"/>
+ <check checked="true" name="MEM-stack-global-field"/>
+ <check checked="true" name="MEM-stack-global"/>
+ <check checked="true" name="MEM-stack-param-ref"/>
+ <check checked="true" name="MEM-stack-param"/>
+ <check checked="true" name="MEM-stack-pos"/>
+ <check checked="true" name="MEM-stack-ref"/>
+ <check checked="true" name="MEM-stack"/>
+ <check checked="true" name="MEM-use-free-all"/>
+ <check checked="true" name="MEM-use-free-some"/>
+ </group>
+ <group checked="false" name="POR">
+ <check checked="true" name="POR-imp-cast-subscript"/>
+ <check checked="false" name="POR-imp-cast-ternary"/>
+ </group>
+ <group checked="true" name="PTR">
+ <check checked="true" name="PTR-arith-field"/>
+ <check checked="true" name="PTR-arith-stack"/>
+ <check checked="true" name="PTR-arith-var"/>
+ <check checked="true" name="PTR-cmp-str-lit"/>
+ <check checked="true" name="PTR-null-assign-fun-pos"/>
+ <check checked="true" name="PTR-null-assign-pos"/>
+ <check checked="true" name="PTR-null-assign"/>
+ <check checked="true" name="PTR-null-cmp-aft"/>
+ <check checked="true" name="PTR-null-cmp-bef-fun"/>
+ <check checked="true" name="PTR-null-cmp-bef"/>
+ <check checked="true" name="PTR-null-fun-pos"/>
+ <check checked="true" name="PTR-null-literal-pos"/>
+ <check checked="false" name="PTR-overload"/>
+ <check checked="true" name="PTR-singleton-arith-pos"/>
+ <check checked="true" name="PTR-singleton-arith"/>
+ <check checked="true" name="PTR-unchk-param-some"/>
+ <check checked="false" name="PTR-unchk-param"/>
+ <check checked="true" name="PTR-uninit-pos"/>
+ <check checked="true" name="PTR-uninit"/>
+ </group>
+ <group checked="true" name="RED">
+ <check checked="false" name="RED-case-reach"/>
+ <check checked="false" name="RED-cmp-always"/>
+ <check checked="false" name="RED-cmp-never"/>
+ <check checked="false" name="RED-cond-always"/>
+ <check checked="true" name="RED-cond-const-assign"/>
+ <check checked="false" name="RED-cond-const-expr"/>
+ <check checked="false" name="RED-cond-const"/>
+ <check checked="false" name="RED-cond-never"/>
+ <check checked="true" name="RED-dead"/>
+ <check checked="false" name="RED-expr"/>
+ <check checked="false" name="RED-func-no-effect"/>
+ <check checked="true" name="RED-local-hides-global"/>
+ <check checked="true" name="RED-local-hides-local"/>
+ <check checked="true" name="RED-local-hides-member"/>
+ <check checked="true" name="RED-local-hides-param"/>
+ <check checked="false" name="RED-no-effect"/>
+ <check checked="true" name="RED-self-assign"/>
+ <check checked="true" name="RED-unused-assign"/>
+ <check checked="false" name="RED-unused-param"/>
+ <check checked="false" name="RED-unused-return-val"/>
+ <check checked="false" name="RED-unused-val"/>
+ <check checked="true" name="RED-unused-var-all"/>
+ </group>
+ <group checked="true" name="RESOURCE">
+ <check checked="false" name="RESOURCE-deref-file"/>
+ <check checked="true" name="RESOURCE-double-close"/>
+ <check checked="true" name="RESOURCE-file-no-close-all"/>
+ <check checked="false" name="RESOURCE-file-pos-neg"/>
+ <check checked="true" name="RESOURCE-file-use-after-close"/>
+ <check checked="false" name="RESOURCE-implicit-deref-file"/>
+ <check checked="true" name="RESOURCE-write-ronly-file"/>
+ </group>
+ <group checked="false" name="SEM">
+ <check checked="false" name="SEM-const-call"/>
+ <check checked="false" name="SEM-const-global"/>
+ <check checked="false" name="SEM-pure-call"/>
+ <check checked="false" name="SEM-pure-global"/>
+ </group>
+ <group checked="true" name="SIZEOF">
+ <check checked="true" name="SIZEOF-side-effect"/>
+ </group>
+ <group checked="true" name="SPC">
+ <check checked="false" name="SPC-init-list"/>
+ <check checked="true" name="SPC-order"/>
+ <check checked="true" name="SPC-return"/>
+ <check checked="true" name="SPC-uninit-arr-all"/>
+ <check checked="true" name="SPC-uninit-struct-field-heap"/>
+ <check checked="true" name="SPC-uninit-struct-field"/>
+ <check checked="true" name="SPC-uninit-struct"/>
+ <check checked="true" name="SPC-uninit-var-all"/>
+ <check checked="true" name="SPC-uninit-var-some"/>
+ <check checked="false" name="SPC-volatile-reads"/>
+ <check checked="false" name="SPC-volatile-writes"/>
+ </group>
+ <group checked="true" name="STR">
+ <check checked="true" name="STR-trigraph"/>
+ </group>
+ <group checked="true" name="STRUCT">
+ <check checked="false" name="STRUCT-signed-bit"/>
+ </group>
+ <group checked="true" name="SWITCH">
+ <check checked="true" name="SWITCH-fall-through"/>
+ </group>
+ <group checked="true" name="THROW">
+ <check checked="false" name="THROW-empty"/>
+ <check checked="false" name="THROW-main"/>
+ <check checked="true" name="THROW-null"/>
+ <check checked="true" name="THROW-ptr"/>
+ <check checked="true" name="THROW-static"/>
+ <check checked="true" name="THROW-unhandled"/>
+ </group>
+ <group checked="true" name="UNION">
+ <check checked="true" name="UNION-overlap-assign"/>
+ <check checked="true" name="UNION-type-punning"/>
+ </group>
+ </package>
+ <package checked="false" name="MISRAC2004">
+ <group checked="false" name="MISRAC2004-1">
+ <check checked="true" name="MISRAC2004-1.1"/>
+ <check checked="true" name="MISRAC2004-1.2_a"/>
+ <check checked="true" name="MISRAC2004-1.2_b"/>
+ <check checked="true" name="MISRAC2004-1.2_c"/>
+ <check checked="true" name="MISRAC2004-1.2_d"/>
+ <check checked="true" name="MISRAC2004-1.2_e"/>
+ <check checked="true" name="MISRAC2004-1.2_f"/>
+ <check checked="true" name="MISRAC2004-1.2_g"/>
+ <check checked="true" name="MISRAC2004-1.2_h"/>
+ <check checked="true" name="MISRAC2004-1.2_i"/>
+ <check checked="true" name="MISRAC2004-1.2_j"/>
+ </group>
+ <group checked="true" name="MISRAC2004-2">
+ <check checked="true" name="MISRAC2004-2.1"/>
+ <check checked="true" name="MISRAC2004-2.2"/>
+ <check checked="true" name="MISRAC2004-2.3"/>
+ <check checked="false" name="MISRAC2004-2.4"/>
+ </group>
+ <group checked="true" name="MISRAC2004-4">
+ <check checked="true" name="MISRAC2004-4.2"/>
+ </group>
+ <group checked="true" name="MISRAC2004-5">
+ <check checked="true" name="MISRAC2004-5.2_a"/>
+ <check checked="true" name="MISRAC2004-5.2_b"/>
+ <check checked="true" name="MISRAC2004-5.2_c"/>
+ <check checked="true" name="MISRAC2004-5.3"/>
+ <check checked="true" name="MISRAC2004-5.4"/>
+ <check checked="false" name="MISRAC2004-5.5"/>
+ </group>
+ <group checked="true" name="MISRAC2004-6">
+ <check checked="true" name="MISRAC2004-6.1"/>
+ <check checked="false" name="MISRAC2004-6.3"/>
+ <check checked="true" name="MISRAC2004-6.4"/>
+ <check checked="true" name="MISRAC2004-6.5"/>
+ </group>
+ <group checked="true" name="MISRAC2004-7">
+ <check checked="true" name="MISRAC2004-7.1"/>
+ </group>
+ <group checked="true" name="MISRAC2004-8">
+ <check checked="true" name="MISRAC2004-8.1"/>
+ <check checked="true" name="MISRAC2004-8.2"/>
+ <check checked="true" name="MISRAC2004-8.5_a"/>
+ <check checked="true" name="MISRAC2004-8.5_b"/>
+ <check checked="true" name="MISRAC2004-8.12"/>
+ </group>
+ <group checked="true" name="MISRAC2004-9">
+ <check checked="true" name="MISRAC2004-9.1_a"/>
+ <check checked="true" name="MISRAC2004-9.1_b"/>
+ <check checked="true" name="MISRAC2004-9.1_c"/>
+ <check checked="true" name="MISRAC2004-9.2"/>
+ </group>
+ <group checked="true" name="MISRAC2004-10">
+ <check checked="true" name="MISRAC2004-10.1_a"/>
+ <check checked="true" name="MISRAC2004-10.1_b"/>
+ <check checked="true" name="MISRAC2004-10.1_c"/>
+ <check checked="true" name="MISRAC2004-10.1_d"/>
+ <check checked="true" name="MISRAC2004-10.2_a"/>
+ <check checked="true" name="MISRAC2004-10.2_b"/>
+ <check checked="true" name="MISRAC2004-10.2_c"/>
+ <check checked="true" name="MISRAC2004-10.2_d"/>
+ <check checked="true" name="MISRAC2004-10.3"/>
+ <check checked="true" name="MISRAC2004-10.4"/>
+ <check checked="true" name="MISRAC2004-10.5"/>
+ <check checked="true" name="MISRAC2004-10.6"/>
+ </group>
+ <group checked="true" name="MISRAC2004-11">
+ <check checked="true" name="MISRAC2004-11.1"/>
+ <check checked="false" name="MISRAC2004-11.3"/>
+ <check checked="false" name="MISRAC2004-11.4"/>
+ <check checked="true" name="MISRAC2004-11.5"/>
+ </group>
+ <group checked="true" name="MISRAC2004-12">
+ <check checked="false" name="MISRAC2004-12.1"/>
+ <check checked="true" name="MISRAC2004-12.2_a"/>
+ <check checked="true" name="MISRAC2004-12.2_b"/>
+ <check checked="true" name="MISRAC2004-12.2_c"/>
+ <check checked="true" name="MISRAC2004-12.3"/>
+ <check checked="true" name="MISRAC2004-12.4"/>
+ <check checked="false" name="MISRAC2004-12.6_a"/>
+ <check checked="false" name="MISRAC2004-12.6_b"/>
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<name>RuntimeChecking</name>
<archiveVersion>0</archiveVersion>
<data>
@@ -93,6 +1055,968 @@
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<debug>0</debug>
<settings>
+ <name>C-STAT</name>
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+ <group checked="true" name="MISRAC++2008-16-3">
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+ <check checked="false" name="MISRAC++2008-16-3-2"/>
+ </group>
+ <group checked="true" name="MISRAC++2008-17-0">
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+ <check checked="true" name="MISRAC++2008-17-0-3"/>
+ <check checked="true" name="MISRAC++2008-17-0-5"/>
+ </group>
+ <group checked="true" name="MISRAC++2008-18-0">
+ <check checked="true" name="MISRAC++2008-18-0-1"/>
+ <check checked="true" name="MISRAC++2008-18-0-2"/>
+ <check checked="true" name="MISRAC++2008-18-0-3"/>
+ <check checked="true" name="MISRAC++2008-18-0-4"/>
+ <check checked="true" name="MISRAC++2008-18-0-5"/>
+ </group>
+ <group checked="true" name="MISRAC++2008-18-2">
+ <check checked="true" name="MISRAC++2008-18-2-1"/>
+ </group>
+ <group checked="true" name="MISRAC++2008-18-4">
+ <check checked="true" name="MISRAC++2008-18-4-1"/>
+ </group>
+ <group checked="true" name="MISRAC++2008-18-7">
+ <check checked="true" name="MISRAC++2008-18-7-1"/>
+ </group>
+ <group checked="true" name="MISRAC++2008-19-3">
+ <check checked="true" name="MISRAC++2008-19-3-1"/>
+ </group>
+ <group checked="true" name="MISRAC++2008-27-0">
+ <check checked="true" name="MISRAC++2008-27-0-1"/>
+ </group>
+ </package>
+ </cstatsettings>
+ </data>
+ </settings>
+ <settings>
<name>RuntimeChecking</name>
<archiveVersion>0</archiveVersion>
<data>
@@ -191,6 +2115,9 @@
<name>$PROJ_DIR$\driverlib\pcm.c</name>
</file>
<file>
+ <name>$PROJ_DIR$\driverlib\sysctl.c</name>
+ </file>
+ <file>
<name>$PROJ_DIR$\driverlib\timer32.c</name>
</file>
<file>
@@ -346,6 +2273,9 @@
<file>
<name>$PROJ_DIR$\system\IAR\msp432_startup_ewarm.c</name>
</file>
+ <file>
+ <name>$PROJ_DIR$\system\IAR\system_msp432p401r.c</name>
+ </file>
</group>
<file>
<name>$PROJ_DIR$\FreeRTOSConfig.h</name>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
index 867b22e..d48e2f3 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvoptx
@@ -73,11 +73,33 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
- <tvExp>1</tvExp>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>4</CpuCode>
+ <Books>
+ <Book>
+ <Number>0</Number>
+ <Title>MSP432 Hardware Tools User's Guide (MSP-TS432PZ100)</Title>
+ <Path>http://www.ti.com/lit/pdf/slau571</Path>
+ </Book>
+ <Book>
+ <Number>1</Number>
+ <Title>MSP432 Quick Start Guide (MSP-EXP432P401R)</Title>
+ <Path>http://www.ti.com/lit/pdf/slau596</Path>
+ </Book>
+ <Book>
+ <Number>2</Number>
+ <Title>LaunchPad Development Kit User's Guide (MSP-EXP432P401R)</Title>
+ <Path>http://www.ti.com/lit/pdf/slau597</Path>
+ </Book>
+ <Book>
+ <Number>3</Number>
+ <Title>MSP432P401R LaunchPad Web page (MSP-EXP432P401R)</Title>
+ <Path>http://www.ti.com/tool/msp-exp432p401r</Path>
+ </Book>
+ </Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@@ -147,7 +169,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
- <Name>-UM0149MEE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
+ <Name>-UM0356BUE -O175 -S8 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1000000 -FC8000 -FN2 -FF0MSP432P4xx_MainFlash256kB.FLM -FS00 -FL040000 -FP0($$Device:MSP432P401R$Flash\MSP432P4xx_MainFlash256kB.FLM) -FF1MSP432P4xx_InfoFlash.FLM -FS1200000 -FL14000 -FP1($$Device:MSP432P401R$Flash\MSP432P4xx_InfoFlash.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
@@ -174,7 +196,7 @@
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
- <aLwin>1</aLwin>
+ <aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
@@ -199,6 +221,10 @@
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ <Lin2Executable></Lin2Executable>
+ <Lin2ConfigFile></Lin2ConfigFile>
+ <bLin2Auto>0</bLin2Auto>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
@@ -219,7 +245,6 @@
<FileNumber>1</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\system\Keil\startup_MSP432P4.s</PathWithFileName>
@@ -231,12 +256,11 @@
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
- <tvExp>1</tvExp>
- <Focus>0</Focus>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
- <PathWithFileName>.\system\Keil\system_MSP432P4.c</PathWithFileName>
- <FilenameWithoutPath>system_MSP432P4.c</FilenameWithoutPath>
+ <PathWithFileName>.\system\Keil\system_msp432p401r.c</PathWithFileName>
+ <FilenameWithoutPath>system_msp432p401r.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
@@ -244,7 +268,7 @@
<Group>
<GroupName>main</GroupName>
- <tvExp>0</tvExp>
+ <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -253,7 +277,6 @@
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
@@ -266,7 +289,6 @@
<FileNumber>4</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
@@ -287,7 +309,6 @@
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\SimplyBlinkyDemo\main_blinky.c</PathWithFileName>
@@ -308,7 +329,6 @@
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\event_groups.c</PathWithFileName>
@@ -321,7 +341,6 @@
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\list.c</PathWithFileName>
@@ -334,7 +353,6 @@
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\queue.c</PathWithFileName>
@@ -347,7 +365,6 @@
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
@@ -360,7 +377,6 @@
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\timers.c</PathWithFileName>
@@ -373,7 +389,6 @@
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\MemMang\heap_4.c</PathWithFileName>
@@ -386,7 +401,6 @@
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\RVDS\ARM_CM4F\port.c</PathWithFileName>
@@ -407,7 +421,6 @@
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\main_full.c</PathWithFileName>
@@ -420,7 +433,6 @@
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RunTimeStatsTimer.c</PathWithFileName>
@@ -433,7 +445,6 @@
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\serial.c</PathWithFileName>
@@ -446,7 +457,6 @@
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\BlockQ.c</PathWithFileName>
@@ -459,7 +469,6 @@
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\countsem.c</PathWithFileName>
@@ -472,7 +481,6 @@
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\EventGroupsDemo.c</PathWithFileName>
@@ -485,7 +493,6 @@
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\GenQTest.c</PathWithFileName>
@@ -498,7 +505,6 @@
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntSemTest.c</PathWithFileName>
@@ -511,7 +517,6 @@
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\recmutex.c</PathWithFileName>
@@ -524,7 +529,6 @@
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\semtest.c</PathWithFileName>
@@ -537,7 +541,6 @@
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\sp_flop.c</PathWithFileName>
@@ -550,7 +553,6 @@
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TaskNotify.c</PathWithFileName>
@@ -563,7 +565,6 @@
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\TimerDemo.c</PathWithFileName>
@@ -576,7 +577,6 @@
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c</PathWithFileName>
@@ -589,7 +589,6 @@
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\Sample-CLI-commands.c</PathWithFileName>
@@ -602,7 +601,6 @@
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\FreeRTOS-Plus\Demo\Common\FreeRTOS_Plus_CLI_Demos\UARTCommandConsole.c</PathWithFileName>
@@ -615,7 +613,6 @@
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\RegTest.c</PathWithFileName>
@@ -628,7 +625,6 @@
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Full_Demo\IntQueueTimer.c</PathWithFileName>
@@ -641,7 +637,6 @@
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\IntQueue.c</PathWithFileName>
@@ -662,7 +657,6 @@
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cpu.c</PathWithFileName>
@@ -675,7 +669,6 @@
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\cs.c</PathWithFileName>
@@ -688,7 +681,6 @@
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\gpio.c</PathWithFileName>
@@ -701,7 +693,6 @@
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\interrupt.c</PathWithFileName>
@@ -714,7 +705,6 @@
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\pcm.c</PathWithFileName>
@@ -727,7 +717,6 @@
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\uart.c</PathWithFileName>
@@ -740,7 +729,6 @@
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\wdt_a.c</PathWithFileName>
@@ -753,7 +741,6 @@
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\sysctl.c</PathWithFileName>
@@ -766,7 +753,6 @@
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\fpu.c</PathWithFileName>
@@ -779,7 +765,6 @@
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
- <Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\driverlib\timer32.c</PathWithFileName>
@@ -787,6 +772,18 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
+ <File>
+ <GroupNumber>6</GroupNumber>
+ <FileNumber>42</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\driverlib\rtc_c.c</PathWithFileName>
+ <FilenameWithoutPath>rtc_c.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
</Group>
<Group>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
index 6f4945c..a30e3b7 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/RTOSDemo.uvprojx
@@ -10,11 +10,13 @@
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060061::V5.06 update 1 (build 61)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>MSP432P401R</Device>
<Vendor>Texas Instruments</Vendor>
- <PackID>TI.MSP432.1.0.0</PackID>
+ <PackID>TexasInstruments.MSP432.1.0.3</PackID>
+ <PackURL>http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/mspkeil/latest/exports</PackURL>
<Cpu>IROM(0x00000000,0x00040000) IROM2(0x00200000,0x00004000) IRAM(0x20000000,0x00010000) IRAM2(0x01000000,0x00010000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@@ -83,6 +85,8 @@
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
@@ -121,47 +125,6 @@
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
- <Simulator>
- <UseSimulator>0</UseSimulator>
- <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
- <RunToMain>1</RunToMain>
- <RestoreBreakpoints>1</RestoreBreakpoints>
- <RestoreWatchpoints>1</RestoreWatchpoints>
- <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
- <RestoreFunctions>1</RestoreFunctions>
- <RestoreToolbox>1</RestoreToolbox>
- <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
- <RestoreSysVw>1</RestoreSysVw>
- </Simulator>
- <Target>
- <UseTarget>1</UseTarget>
- <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
- <RunToMain>1</RunToMain>
- <RestoreBreakpoints>1</RestoreBreakpoints>
- <RestoreWatchpoints>1</RestoreWatchpoints>
- <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
- <RestoreFunctions>0</RestoreFunctions>
- <RestoreToolbox>1</RestoreToolbox>
- <RestoreTracepoints>1</RestoreTracepoints>
- <RestoreSysVw>1</RestoreSysVw>
- </Target>
- <RunDebugAfterBuild>0</RunDebugAfterBuild>
- <TargetSelection>1</TargetSelection>
- <SimDlls>
- <CpuDll></CpuDll>
- <CpuDllArguments></CpuDllArguments>
- <PeripheralDll></PeripheralDll>
- <PeripheralDllArguments></PeripheralDllArguments>
- <InitializationFile></InitializationFile>
- </SimDlls>
- <TargetDlls>
- <CpuDll></CpuDll>
- <CpuDllArguments></CpuDllArguments>
- <PeripheralDll></PeripheralDll>
- <PeripheralDllArguments></PeripheralDllArguments>
- <InitializationFile></InitializationFile>
- <Driver>BIN\UL2CM3.DLL</Driver>
- </TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
@@ -226,6 +189,7 @@
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
@@ -358,13 +322,17 @@
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
- <uC99>0</uC99>
+ <uC99>1</uC99>
<useXO>0</useXO>
+ <v6Lang>1</v6Lang>
+ <v6LangP>1</v6LangP>
+ <vShortEn>1</vShortEn>
+ <vShortWch>1</vShortWch>
<VariousControls>
<MiscControls></MiscControls>
- <Define>keil __MSP432P401R__</Define>
+ <Define>keil __MSP432P401R__ NO_MSP_CLASSIC_DEFINES</Define>
<Undefine></Undefine>
- <IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F</IncludePath>
+ <IncludePath>.\driverlib;..\CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil;.\Full_Demo;..\Common\include;..\..\..\FreeRTOS-Plus\Source\FreeRTOS-Plus-CLI;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;.\driverlib\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -413,9 +381,9 @@
<FilePath>.\system\Keil\startup_MSP432P4.s</FilePath>
</File>
<File>
- <FileName>system_MSP432P4.c</FileName>
+ <FileName>system_msp432p401r.c</FileName>
<FileType>1</FileType>
- <FilePath>.\system\Keil\system_MSP432P4.c</FilePath>
+ <FilePath>.\system\Keil\system_msp432p401r.c</FilePath>
</File>
</Files>
</Group>
@@ -637,6 +605,11 @@
<FileType>1</FileType>
<FilePath>.\driverlib\timer32.c</FilePath>
</File>
+ <File>
+ <FileName>rtc_c.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\driverlib\rtc_c.c</FilePath>
+ </File>
</Files>
</Group>
<Group>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
index c39f1e5..8a5962f 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,16 +45,16 @@
/* Statics */
static volatile uint32_t* const _ctlRegs[32] =
-{ &ADC14->rMCTL0.r, &ADC14->rMCTL1.r, &ADC14->rMCTL2.r, &ADC14->rMCTL3.r,
- &ADC14->rMCTL4.r, &ADC14->rMCTL5.r, &ADC14->rMCTL6.r, &ADC14->rMCTL7.r,
- &ADC14->rMCTL8.r, &ADC14->rMCTL9.r, &ADC14->rMCTL10.r,
- &ADC14->rMCTL11.r, &ADC14->rMCTL12.r, &ADC14->rMCTL13.r,
- &ADC14->rMCTL14.r, &ADC14->rMCTL15.r, &ADC14->rMCTL16.r,
- &ADC14->rMCTL17.r, &ADC14->rMCTL18.r, &ADC14->rMCTL19.r,
- &ADC14->rMCTL20.r, &ADC14->rMCTL21.r, &ADC14->rMCTL22.r,
- &ADC14->rMCTL23.r, &ADC14->rMCTL24.r, &ADC14->rMCTL25.r,
- &ADC14->rMCTL26.r, &ADC14->rMCTL27.r, &ADC14->rMCTL28.r,
- &ADC14->rMCTL29.r, &ADC14->rMCTL30.r, &ADC14->rMCTL31.r };
+{ &ADC14->MCTL[0], &ADC14->MCTL[1], &ADC14->MCTL[2], &ADC14->MCTL[3],
+ &ADC14->MCTL[4], &ADC14->MCTL[5], &ADC14->MCTL[6], &ADC14->MCTL[7],
+ &ADC14->MCTL[8], &ADC14->MCTL[9], &ADC14->MCTL[10],
+ &ADC14->MCTL[11], &ADC14->MCTL[12], &ADC14->MCTL[13],
+ &ADC14->MCTL[14], &ADC14->MCTL[15], &ADC14->MCTL[16],
+ &ADC14->MCTL[17], &ADC14->MCTL[18], &ADC14->MCTL[19],
+ &ADC14->MCTL[20], &ADC14->MCTL[21], &ADC14->MCTL[22],
+ &ADC14->MCTL[23], &ADC14->MCTL[24], &ADC14->MCTL[25],
+ &ADC14->MCTL[26], &ADC14->MCTL[27], &ADC14->MCTL[28],
+ &ADC14->MCTL[29], &ADC14->MCTL[30], &ADC14->MCTL[31] };
static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
{
@@ -145,12 +145,12 @@
//*****************************************************************************
static bool ADCIsConversionRunning(void)
{
- return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
+ return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
}
void ADC14_enableModule(void)
{
- BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 1;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 1;
}
bool ADC14_disableModule(void)
@@ -158,7 +158,7 @@
if (ADCIsConversionRunning())
return false;
- BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS) = 0;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 0;
return true;
}
@@ -168,14 +168,14 @@
if (ADCIsConversionRunning())
return false;
- BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 1;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 1;
if (multiSampleConvert == ADC_MANUAL_ITERATION)
{
- BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 0;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 0;
} else
{
- BITBAND_PERI(ADC14->rCTL0.r, ADC14MSC_OFS) = 1;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 1;
}
return true;
@@ -186,7 +186,7 @@
if (ADCIsConversionRunning())
return false;
- BITBAND_PERI(ADC14->rCTL0.r, ADC14SHP_OFS) = 0;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 0;
return true;
}
@@ -225,11 +225,11 @@
if (ADCIsConversionRunning())
return false;
- ADC14->rCTL0.r = (ADC14->rCTL0.r
- & ~(ADC14PDIV_M | ADC14DIV_M | ADC14SSEL_M))
+ ADC14->CTL0 = (ADC14->CTL0
+ & ~(ADC14_CTL0_PDIV_MASK | ADC14_CTL0_DIV_MASK | ADC14_CTL0_SSEL_MASK))
| clockDivider | clockPredivider | clockSource;
- ADC14->rCTL1.r = (ADC14->rCTL1.r
+ ADC14->CTL1 = (ADC14->CTL1
& ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 | ADC_MAPINTCH0
| ADC_TEMPSENSEMAP | ADC_BATTMAP)) | internalChannelMask;
@@ -242,12 +242,12 @@
resolution == ADC_8BIT || resolution == ADC_10BIT
|| resolution == ADC_12BIT || resolution == ADC_14BIT);
- ADC14->rCTL1.r = (ADC14->rCTL1.r & ~ADC14RES_M) | resolution;
+ ADC14->CTL1 = (ADC14->CTL1 & ~ADC14_CTL1_RES_MASK) | resolution;
}
uint_fast32_t ADC14_getResolution(void)
{
- return ADC14->rCTL1.r & ADC14RES_M;
+ return ADC14->CTL1 & ADC14_CTL1_RES_MASK;
}
bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
@@ -267,13 +267,13 @@
if (invertSignal)
{
- ADC14->rCTL0.r = (ADC14->rCTL0.r
- & ~(ADC14ISSH | ADC14SHS_M)) | source
- | ADC14ISSH;
+ ADC14->CTL0 = (ADC14->CTL0
+ & ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source
+ | ADC14_CTL0_ISSH;
} else
{
- ADC14->rCTL0.r = (ADC14->rCTL0.r
- & ~(ADC14ISSH | ADC14SHS_M)) | source;
+ ADC14->CTL0 = (ADC14->CTL0
+ & ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source;
}
return true;
@@ -305,8 +305,8 @@
if (ADCIsConversionRunning())
return false;
- ADC14->rCTL0.r = (ADC14->rCTL0.r
- & ~(ADC14SHT0_M | ADC14SHT1_M)) | secondPulseWidth
+ ADC14->CTL0 = (ADC14->CTL0
+ & ~(ADC14_CTL0_SHT0_MASK | ADC14_CTL0_SHT1_MASK)) | secondPulseWidth
| (firstPulseWidth >> 4);
return true;
@@ -327,26 +327,26 @@
/* Clearing out any lingering EOS */
for (ii = 0; ii < 32; ii++)
{
- BITBAND_PERI(*(_ctlRegs[ii]), ADC14EOS_OFS) = 0;
+ BITBAND_PERI(*(_ctlRegs[ii]), ADC14_MCTLN_EOS_OFS) = 0;
}
/* Setting Start/Stop locations */
BITBAND_PERI(
(*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])),
- ADC14EOS_OFS) = 1;
+ ADC14_MCTLN_EOS_OFS) = 1;
- ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
+ ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryStart) << 16);
/* Setting multiple sample mode */
if (!repeatMode)
{
- ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
- | (ADC14CONSEQ_1);
+ ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+ | (ADC14_CTL0_CONSEQ_1);
} else
{
- ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
- | (ADC14CONSEQ_3);
+ ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+ | (ADC14_CTL0_CONSEQ_3);
}
return true;
@@ -361,18 +361,18 @@
return false;
/* Setting the destination register */
- ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14CSTARTADD_M))
+ ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
| (_getIndexForMemRegister(memoryDestination) << 16);
/* Setting single sample mode */
if (!repeatMode)
{
- ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
- | (ADC14CONSEQ_0);
+ ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+ | (ADC14_CTL0_CONSEQ_0);
} else
{
- ADC14->rCTL0.r = (ADC14->rCTL0.r & ~(ADC14CONSEQ_M))
- | (ADC14CONSEQ_2);
+ ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+ | (ADC14_CTL0_CONSEQ_2);
}
return true;
@@ -380,25 +380,25 @@
bool ADC14_enableConversion(void)
{
- if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
+ if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
return false;
- ADC14->rCTL0.r |= (ADC14ENC);
+ ADC14->CTL0 |= (ADC14_CTL0_ENC);
return true;
}
bool ADC14_toggleConversionTrigger(void)
{
- if (!BITBAND_PERI(ADC14->rCTL0.r, ADC14ON_OFS))
+ if (!BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
return false;
- if (BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS))
+ if (BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS))
{
- BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 0;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 0;
} else
{
- BITBAND_PERI(ADC14->rCTL0.r, ADC14SC_OFS) = 1;
+ BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 1;
}
return true;
@@ -406,12 +406,12 @@
void ADC14_disableConversion(void)
{
- ADC14->rCTL0.r &= ~(ADC14SC | ADC14ENC);
+ ADC14->CTL0 &= ~(ADC14_CTL0_SC | ADC14_CTL0_ENC);
}
bool ADC14_isBusy(void)
{
- return BITBAND_PERI(ADC14->rCTL0.r, ADC14BUSY_OFS);
+ return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
}
bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
@@ -444,14 +444,14 @@
if (differntialMode)
{
(*curReg) = ((*curReg)
- & ~(ADC14VRSEL_M | ADC14INCH_M
- | ADC14DIF))
- | (channelSelect | refSelect | ADC14DIF);
+ & ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
+ | ADC14_MCTLN_DIF))
+ | (channelSelect | refSelect | ADC14_MCTLN_DIF);
} else
{
(*curReg) = ((*curReg)
- & ~(ADC14VRSEL_M | ADC14INCH_M
- | ADC14DIF)) | (channelSelect | refSelect);
+ & ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
+ | ADC14_MCTLN_DIF)) | (channelSelect | refSelect);
}
}
@@ -489,11 +489,11 @@
if (windowSelect == ADC_COMP_WINDOW0)
{
(*curRegPoint) = ((*curRegPoint)
- & ~(ADC14WINC | ADC14WINCTH))
- | (ADC14WINC);
+ & ~(ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH))
+ | (ADC14_MCTLN_WINC);
} else if (windowSelect == ADC_COMP_WINDOW1)
{
- (*curRegPoint) |= ADC14WINC | ADC14WINCTH;
+ (*curRegPoint) |= ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH;
}
}
@@ -525,7 +525,7 @@
ii = ii << 1;
(*(_ctlRegs[_getIndexForMemRegister(currentReg)])) &=
- ~ADC14WINC;
+ ~ADC14_MCTLN_WINC;
}
@@ -536,20 +536,27 @@
{
if (ADCIsConversionRunning())
return false;
+
+ if(BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS))
+ {
+ low = ((low << 2) | (0x8000 & low)) & 0xFFFC;
+ high = ((high << 2) | (0x8000 & high)) & 0xFFFC;
+ }
if (window == ADC_COMP_WINDOW0)
{
- ADC14->rHI0.r = (high);
- ADC14->rLO0.r = (low);
+ ADC14->HI0 = (high);
+ ADC14->LO0 = (low);
} else if (window == ADC_COMP_WINDOW1)
{
- ADC14->rHI1.r = (high);
- ADC14->rLO1.r = (low);
+ ADC14->HI1 = (high);
+ ADC14->LO1 = (low);
} else
{
ASSERT(false);
+ return false;
}
return true;
@@ -562,10 +569,10 @@
if (resultFormat == ADC_UNSIGNED_BINARY)
{
- BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 0;
+ BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 0;
} else if (resultFormat == ADC_SIGNED_BINARY)
{
- BITBAND_PERI(ADC14->rCTL1.r, ADC14DF_OFS) = 1;
+ BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 1;
} else
{
ASSERT(false);
@@ -577,7 +584,7 @@
uint_fast16_t ADC14_getResult(uint32_t memorySelect)
{
return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)]
- + 0x80));
+ + 0x20));
}
void ADC14_getMultiSequenceResult(uint16_t* res)
@@ -585,16 +592,16 @@
uint32_t *startAddr, *curAddr;
uint32_t ii;
- startAddr = (uint32_t*) _ctlRegs[(ADC14->rCTL1.r & ADC14CSTARTADD_M)
+ startAddr = (uint32_t*) _ctlRegs[(ADC14->CTL1 & ADC14_CTL1_CSTARTADD_MASK)
>> 16];
curAddr = startAddr;
for (ii = 0; ii < 32; ii++)
{
- res[ii] = *(((uint16_t*) curAddr) + 0x80);
+ res[ii] = *(((uint16_t*) curAddr) + 0x40);
- if (BITBAND_PERI((*curAddr), ADC14EOS_OFS))
+ if (BITBAND_PERI((*curAddr), ADC14_MCTLN_EOS_OFS))
break;
if (curAddr == _ctlRegs[31])
@@ -627,7 +634,7 @@
foundEnd = true;
}
- res[ii] = *(((uint16_t*) firstPoint) + 0x80);
+ res[ii] = *(((uint16_t*) firstPoint) + 0x40);
if (firstPoint == _ctlRegs[31])
firstPoint = (uint32_t*) _ctlRegs[0];
@@ -641,7 +648,7 @@
if (ADCIsConversionRunning())
return false;
- BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 1;
+ BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 1;
return true;
}
@@ -651,7 +658,7 @@
if (ADCIsConversionRunning())
return false;
- BITBAND_PERI(ADC14->rCTL1.r, ADC14REFBURST_OFS) = 0;
+ BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 0;
return true;
}
@@ -664,12 +671,12 @@
switch (adcPowerMode)
{
case ADC_UNRESTRICTED_POWER_MODE:
- ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
- | (ADC14PWRMD_0);
+ ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
+ | (ADC14_CTL1_PWRMD_0);
break;
case ADC_ULTRA_LOW_POWER_MODE:
- ADC14->rCTL1.r = (ADC14->rCTL1.r & ~(ADC14PWRMD_M))
- | (ADC14PWRMD_2);
+ ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
+ | (ADC14_CTL1_PWRMD_2);
break;
default:
ASSERT(false);
@@ -683,31 +690,31 @@
{
uint32_t stat = mask & 0xFFFFFFFF;
- ADC14->rIER0.r |= stat;
+ ADC14->IER0 |= stat;
stat = (mask >> 32);
- ADC14->rIER1.r |= (stat);
+ ADC14->IER1 |= (stat);
}
void ADC14_disableInterrupt(uint_fast64_t mask)
{
uint32_t stat = mask & 0xFFFFFFFF;
- ADC14->rIER0.r &= ~stat;
+ ADC14->IER0 &= ~stat;
stat = (mask >> 32);
- ADC14->rIER1.r &= ~(stat);
+ ADC14->IER1 &= ~(stat);
}
uint_fast64_t ADC14_getInterruptStatus(void)
{
- uint_fast64_t status = ADC14->rIFGR1.r;
- return ((status << 32) | ADC14->rIFGR0.r);
+ uint_fast64_t status = ADC14->IFGR1;
+ return ((status << 32) | ADC14->IFGR0);
}
uint_fast64_t ADC14_getEnabledInterruptStatus(void)
{
- uint_fast64_t stat = ADC14->rIER1.r;
+ uint_fast64_t stat = ADC14->IER1;
- return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->rIER0.r);
+ return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->IER0);
}
@@ -715,9 +722,9 @@
{
uint32_t stat = mask & 0xFFFFFFFF;
- ADC14->rCLRIFGR0.r |= stat;
+ ADC14->CLRIFGR0 |= stat;
stat = (mask >> 32);
- ADC14->rCLRIFGR1.r |= (stat);
+ ADC14->CLRIFGR1 |= (stat);
}
void ADC14_registerInterrupt(void (*intHandler)(void))
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
index d17446e..3b3f0b7 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/adc14.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -71,57 +71,57 @@
//The following are values that can be passed to ADC14_initModule
//
//*****************************************************************************
-#define ADC_CLOCKSOURCE_ADCOSC (ADC14SSEL_0)
-#define ADC_CLOCKSOURCE_SYSOSC (ADC14SSEL_1)
-#define ADC_CLOCKSOURCE_ACLK (ADC14SSEL_2)
-#define ADC_CLOCKSOURCE_MCLK (ADC14SSEL_3)
-#define ADC_CLOCKSOURCE_SMCLK (ADC14SSEL_4)
-#define ADC_CLOCKSOURCE_HSMCLK (ADC14SSEL_5)
+#define ADC_CLOCKSOURCE_ADCOSC (ADC14_CTL0_SSEL_0)
+#define ADC_CLOCKSOURCE_SYSOSC (ADC14_CTL0_SSEL_1)
+#define ADC_CLOCKSOURCE_ACLK (ADC14_CTL0_SSEL_2)
+#define ADC_CLOCKSOURCE_MCLK (ADC14_CTL0_SSEL_3)
+#define ADC_CLOCKSOURCE_SMCLK (ADC14_CTL0_SSEL_4)
+#define ADC_CLOCKSOURCE_HSMCLK (ADC14_CTL0_SSEL_5)
-#define ADC_PREDIVIDER_1 (ADC14PDIV_0)
-#define ADC_PREDIVIDER_4 (ADC14PDIV_1)
-#define ADC_PREDIVIDER_32 (ADC14PDIV_2)
-#define ADC_PREDIVIDER_64 (ADC14PDIV_3)
+#define ADC_PREDIVIDER_1 (ADC14_CTL0_PDIV_0)
+#define ADC_PREDIVIDER_4 (ADC14_CTL0_PDIV_1)
+#define ADC_PREDIVIDER_32 (ADC14_CTL0_PDIV_2)
+#define ADC_PREDIVIDER_64 (ADC14_CTL0_PDIV_3)
-#define ADC_DIVIDER_1 (ADC14DIV_0)
-#define ADC_DIVIDER_2 (ADC14DIV_1)
-#define ADC_DIVIDER_3 (ADC14DIV_2)
-#define ADC_DIVIDER_4 (ADC14DIV_3)
-#define ADC_DIVIDER_5 (ADC14DIV_4)
-#define ADC_DIVIDER_6 (ADC14DIV_5)
-#define ADC_DIVIDER_7 (ADC14DIV_6)
-#define ADC_DIVIDER_8 (ADC14DIV_7)
+#define ADC_DIVIDER_1 (ADC14_CTL0_DIV_0)
+#define ADC_DIVIDER_2 (ADC14_CTL0_DIV_1)
+#define ADC_DIVIDER_3 (ADC14_CTL0_DIV_2)
+#define ADC_DIVIDER_4 (ADC14_CTL0_DIV_3)
+#define ADC_DIVIDER_5 (ADC14_CTL0_DIV_4)
+#define ADC_DIVIDER_6 (ADC14_CTL0_DIV_5)
+#define ADC_DIVIDER_7 (ADC14_CTL0_DIV_6)
+#define ADC_DIVIDER_8 (ADC14_CTL0_DIV_7)
-#define ADC_MAPINTCH3 (ADC14CH3MAP)
-#define ADC_MAPINTCH2 (ADC14CH2MAP)
-#define ADC_MAPINTCH1 (ADC14CH1MAP)
-#define ADC_MAPINTCH0 (ADC14CH0MAP)
-#define ADC_TEMPSENSEMAP (ADC14TCMAP)
-#define ADC_BATTMAP (ADC14BATMAP)
+#define ADC_MAPINTCH3 (ADC14_CTL1_CH3MAP)
+#define ADC_MAPINTCH2 (ADC14_CTL1_CH2MAP)
+#define ADC_MAPINTCH1 (ADC14_CTL1_CH1MAP)
+#define ADC_MAPINTCH0 (ADC14_CTL1_CH0MAP)
+#define ADC_TEMPSENSEMAP (ADC14_CTL1_TCMAP)
+#define ADC_BATTMAP (ADC14_CTL1_BATMAP)
#define ADC_NOROUTE 0
-#define ADC_8BIT ADC14RES_0
-#define ADC_10BIT ADC14RES_1
-#define ADC_12BIT ADC14RES_2
-#define ADC_14BIT ADC14RES_3
+#define ADC_8BIT ADC14_CTL1_RES_0
+#define ADC_10BIT ADC14_CTL1_RES_1
+#define ADC_12BIT ADC14_CTL1_RES_2
+#define ADC_14BIT ADC14_CTL1_RES_3
-#define ADC_TRIGGER_ADCSC ADC14SHS_0
-#define ADC_TRIGGER_SOURCE1 ADC14SHS_1
-#define ADC_TRIGGER_SOURCE2 ADC14SHS_2
-#define ADC_TRIGGER_SOURCE3 ADC14SHS_3
-#define ADC_TRIGGER_SOURCE4 ADC14SHS_4
-#define ADC_TRIGGER_SOURCE5 ADC14SHS_5
-#define ADC_TRIGGER_SOURCE6 ADC14SHS_6
-#define ADC_TRIGGER_SOURCE7 ADC14SHS_7
+#define ADC_TRIGGER_ADCSC ADC14_CTL0_SHS_0
+#define ADC_TRIGGER_SOURCE1 ADC14_CTL0_SHS_1
+#define ADC_TRIGGER_SOURCE2 ADC14_CTL0_SHS_2
+#define ADC_TRIGGER_SOURCE3 ADC14_CTL0_SHS_3
+#define ADC_TRIGGER_SOURCE4 ADC14_CTL0_SHS_4
+#define ADC_TRIGGER_SOURCE5 ADC14_CTL0_SHS_5
+#define ADC_TRIGGER_SOURCE6 ADC14_CTL0_SHS_6
+#define ADC_TRIGGER_SOURCE7 ADC14_CTL0_SHS_7
-#define ADC_PULSE_WIDTH_4 ADC14SHT1_0
-#define ADC_PULSE_WIDTH_8 ADC14SHT1_1
-#define ADC_PULSE_WIDTH_16 ADC14SHT1_2
-#define ADC_PULSE_WIDTH_32 ADC14SHT1_3
-#define ADC_PULSE_WIDTH_64 ADC14SHT1_4
-#define ADC_PULSE_WIDTH_96 ADC14SHT1_5
-#define ADC_PULSE_WIDTH_128 ADC14SHT1_6
-#define ADC_PULSE_WIDTH_192 ADC14SHT1_7
+#define ADC_PULSE_WIDTH_4 ADC14_CTL0_SHT1_0
+#define ADC_PULSE_WIDTH_8 ADC14_CTL0_SHT1_1
+#define ADC_PULSE_WIDTH_16 ADC14_CTL0_SHT1_2
+#define ADC_PULSE_WIDTH_32 ADC14_CTL0_SHT1_3
+#define ADC_PULSE_WIDTH_64 ADC14_CTL0_SHT1_4
+#define ADC_PULSE_WIDTH_96 ADC14_CTL0_SHT1_5
+#define ADC_PULSE_WIDTH_128 ADC14_CTL0_SHT1_6
+#define ADC_PULSE_WIDTH_192 ADC14_CTL0_SHT1_7
#define ADC_NONDIFFERENTIAL_INPUTS false
#define ADC_DIFFERENTIAL_INPUTS true
@@ -159,43 +159,43 @@
#define ADC_MEM30 0x40000000
#define ADC_MEM31 0x80000000
-#define ADC_VREFPOS_AVCC_VREFNEG_VSS (ADC14VRSEL_0)
-#define ADC_VREFPOS_INTBUF_VREFNEG_VSS (ADC14VRSEL_1)
-#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC14VRSEL_14)
-#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC14VRSEL_15)
+#define ADC_VREFPOS_AVCC_VREFNEG_VSS (ADC14_MCTLN_VRSEL_0)
+#define ADC_VREFPOS_INTBUF_VREFNEG_VSS (ADC14_MCTLN_VRSEL_1)
+#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_14)
+#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_15)
-#define ADC_INPUT_A0 (ADC14INCH_0)
-#define ADC_INPUT_A1 (ADC14INCH_1)
-#define ADC_INPUT_A2 (ADC14INCH_2)
-#define ADC_INPUT_A3 (ADC14INCH_3)
-#define ADC_INPUT_A4 (ADC14INCH_4)
-#define ADC_INPUT_A5 (ADC14INCH_5)
-#define ADC_INPUT_A6 (ADC14INCH_6)
-#define ADC_INPUT_A7 (ADC14INCH_7)
-#define ADC_INPUT_A8 (ADC14INCH_8)
-#define ADC_INPUT_A9 (ADC14INCH_9)
-#define ADC_INPUT_A10 (ADC14INCH_10)
-#define ADC_INPUT_A11 (ADC14INCH_11)
-#define ADC_INPUT_A12 (ADC14INCH_12)
-#define ADC_INPUT_A13 (ADC14INCH_13)
-#define ADC_INPUT_A14 (ADC14INCH_14)
-#define ADC_INPUT_A15 (ADC14INCH_15)
-#define ADC_INPUT_A16 (ADC14INCH_16)
-#define ADC_INPUT_A17 (ADC14INCH_17)
-#define ADC_INPUT_A18 (ADC14INCH_18)
-#define ADC_INPUT_A19 (ADC14INCH_19)
-#define ADC_INPUT_A20 (ADC14INCH_20)
-#define ADC_INPUT_A21 (ADC14INCH_21)
-#define ADC_INPUT_A22 (ADC14INCH_22)
-#define ADC_INPUT_A23 (ADC14INCH_23)
-#define ADC_INPUT_A24 (ADC14INCH_24)
-#define ADC_INPUT_A25 (ADC14INCH_25)
-#define ADC_INPUT_A26 (ADC14INCH_26)
-#define ADC_INPUT_A27 (ADC14INCH_27)
-#define ADC_INPUT_A28 (ADC14INCH_28)
-#define ADC_INPUT_A29 (ADC14INCH_29)
-#define ADC_INPUT_A30 (ADC14INCH_30)
-#define ADC_INPUT_A31 (ADC14INCH_31)
+#define ADC_INPUT_A0 (ADC14_MCTLN_INCH_0)
+#define ADC_INPUT_A1 (ADC14_MCTLN_INCH_1)
+#define ADC_INPUT_A2 (ADC14_MCTLN_INCH_2)
+#define ADC_INPUT_A3 (ADC14_MCTLN_INCH_3)
+#define ADC_INPUT_A4 (ADC14_MCTLN_INCH_4)
+#define ADC_INPUT_A5 (ADC14_MCTLN_INCH_5)
+#define ADC_INPUT_A6 (ADC14_MCTLN_INCH_6)
+#define ADC_INPUT_A7 (ADC14_MCTLN_INCH_7)
+#define ADC_INPUT_A8 (ADC14_MCTLN_INCH_8)
+#define ADC_INPUT_A9 (ADC14_MCTLN_INCH_9)
+#define ADC_INPUT_A10 (ADC14_MCTLN_INCH_10)
+#define ADC_INPUT_A11 (ADC14_MCTLN_INCH_11)
+#define ADC_INPUT_A12 (ADC14_MCTLN_INCH_12)
+#define ADC_INPUT_A13 (ADC14_MCTLN_INCH_13)
+#define ADC_INPUT_A14 (ADC14_MCTLN_INCH_14)
+#define ADC_INPUT_A15 (ADC14_MCTLN_INCH_15)
+#define ADC_INPUT_A16 (ADC14_MCTLN_INCH_16)
+#define ADC_INPUT_A17 (ADC14_MCTLN_INCH_17)
+#define ADC_INPUT_A18 (ADC14_MCTLN_INCH_18)
+#define ADC_INPUT_A19 (ADC14_MCTLN_INCH_19)
+#define ADC_INPUT_A20 (ADC14_MCTLN_INCH_20)
+#define ADC_INPUT_A21 (ADC14_MCTLN_INCH_21)
+#define ADC_INPUT_A22 (ADC14_MCTLN_INCH_22)
+#define ADC_INPUT_A23 (ADC14_MCTLN_INCH_23)
+#define ADC_INPUT_A24 (ADC14_MCTLN_INCH_24)
+#define ADC_INPUT_A25 (ADC14_MCTLN_INCH_25)
+#define ADC_INPUT_A26 (ADC14_MCTLN_INCH_26)
+#define ADC_INPUT_A27 (ADC14_MCTLN_INCH_27)
+#define ADC_INPUT_A28 (ADC14_MCTLN_INCH_28)
+#define ADC_INPUT_A29 (ADC14_MCTLN_INCH_29)
+#define ADC_INPUT_A30 (ADC14_MCTLN_INCH_30)
+#define ADC_INPUT_A31 (ADC14_MCTLN_INCH_31)
#define ADC_COMP_WINDOW0 0x00
#define ADC_COMP_WINDOW1 0x01
@@ -204,44 +204,44 @@
#define ADC_UNSIGNED_BINARY 0x01
#define ADC_MANUAL_ITERATION 0x00
-#define ADC_AUTOMATIC_ITERATION ADC14MSC
+#define ADC_AUTOMATIC_ITERATION ADC14_CTL0_MSC
-#define ADC_UNRESTRICTED_POWER_MODE ADC14PWRMD_0
-#define ADC_ULTRA_LOW_POWER_MODE ADC14PWRMD_2
+#define ADC_UNRESTRICTED_POWER_MODE ADC14_CTL1_PWRMD_0
+#define ADC_ULTRA_LOW_POWER_MODE ADC14_CTL1_PWRMD_2
-#define ADC_INT0 ADC14IE0
-#define ADC_INT1 ADC14IE1
-#define ADC_INT2 ADC14IE2
-#define ADC_INT3 ADC14IE3
-#define ADC_INT4 ADC14IE4
-#define ADC_INT5 ADC14IE5
-#define ADC_INT6 ADC14IE6
-#define ADC_INT7 ADC14IE7
-#define ADC_INT8 ADC14IE8
-#define ADC_INT9 ADC14IE9
-#define ADC_INT10 ADC14IE10
-#define ADC_INT11 ADC14IE11
-#define ADC_INT12 ADC14IE12
-#define ADC_INT13 ADC14IE13
-#define ADC_INT14 ADC14IE14
-#define ADC_INT15 ADC14IE15
-#define ADC_INT16 ADC14IE16
-#define ADC_INT17 ADC14IE17
-#define ADC_INT18 ADC14IE18
-#define ADC_INT19 ADC14IE19
-#define ADC_INT20 ADC14IE20
-#define ADC_INT21 ADC14IE21
-#define ADC_INT22 ADC14IE22
-#define ADC_INT23 ADC14IE23
-#define ADC_INT24 ADC14IE24
-#define ADC_INT25 ADC14IE25
-#define ADC_INT26 ADC14IE26
-#define ADC_INT27 ADC14IE27
-#define ADC_INT28 ADC14IE28
-#define ADC_INT29 ADC14IE29
-#define ADC_INT30 ADC14IE30
-#define ADC_INT31 ADC14IE31
+#define ADC_INT0 ADC14_IER0_IE0
+#define ADC_INT1 ADC14_IER0_IE1
+#define ADC_INT2 ADC14_IER0_IE2
+#define ADC_INT3 ADC14_IER0_IE3
+#define ADC_INT4 ADC14_IER0_IE4
+#define ADC_INT5 ADC14_IER0_IE5
+#define ADC_INT6 ADC14_IER0_IE6
+#define ADC_INT7 ADC14_IER0_IE7
+#define ADC_INT8 ADC14_IER0_IE8
+#define ADC_INT9 ADC14_IER0_IE9
+#define ADC_INT10 ADC14_IER0_IE10
+#define ADC_INT11 ADC14_IER0_IE11
+#define ADC_INT12 ADC14_IER0_IE12
+#define ADC_INT13 ADC14_IER0_IE13
+#define ADC_INT14 ADC14_IER0_IE14
+#define ADC_INT15 ADC14_IER0_IE15
+#define ADC_INT16 ADC14_IER0_IE16
+#define ADC_INT17 ADC14_IER0_IE17
+#define ADC_INT18 ADC14_IER0_IE18
+#define ADC_INT19 ADC14_IER0_IE19
+#define ADC_INT20 ADC14_IER0_IE20
+#define ADC_INT21 ADC14_IER0_IE21
+#define ADC_INT22 ADC14_IER0_IE22
+#define ADC_INT23 ADC14_IER0_IE23
+#define ADC_INT24 ADC14_IER0_IE24
+#define ADC_INT25 ADC14_IER0_IE25
+#define ADC_INT26 ADC14_IER0_IE26
+#define ADC_INT27 ADC14_IER0_IE27
+#define ADC_INT28 ADC14_IER0_IE28
+#define ADC_INT29 ADC14_IER0_IE29
+#define ADC_INT30 ADC14_IER0_IE30
+#define ADC_INT31 ADC14_IER0_IE31
#define ADC_IN_INT 0x0000000200000000
#define ADC_LO_INT 0x0000000400000000
#define ADC_HI_INT 0x0000000800000000
@@ -542,9 +542,6 @@
//!
//! Returns a boolean value that tells if a conversion/sample is in progress
//!
-//! Originally a public function, but moved to static. External customers should
-//! use the ADC14_isBusy function.
-//!
//! \return true if conversion is active, false otherwise
//
//*****************************************************************************
@@ -1026,8 +1023,8 @@
#define ADC14_enableModuleMultipleInstance(a) ADC14_enableModule()
#define ADC14_disableModuleMultipleInstance(a) ADC14_disableModule()
#define ADC14_initModuleMultipleInstance(a,b,c,d,e) ADC14_initModule(b,c,d,e)
-#define ADC14_setResolutionMutlipleInstance(a,b) ADC14_setResolution(b)
-#define ADC14_getResolutionMutlipleInstance(a) ADC14_getResolution()
+#define ADC14_setResolutionMultipleInstance(a,b) ADC14_setResolution(b)
+#define ADC14_getResolutionMultipleInstance(a) ADC14_getResolution()
#define ADC14_setSampleHoldTriggerMultipleInstance(a,b,c) ADC14_setSampleHoldTrigger(b,c)
#define ADC14_setSampleHoldTimeMultipleInstance(a,b,c) ADC14_setSampleHoldTime(b,c)
#define ADC14_configureMultiSequenceModeMultipleInstance(a,b,c,d) ADC14_configureMultiSequenceMode(b,c,d)
@@ -1036,7 +1033,7 @@
#define ADC14_disableConversionMultipleInstance(a) ADC14_disableConversion()
#define ADC14_toggleConversionTriggerMultipleInstance(a) ADC14_toggleConversionTrigger()
#define ADC14_isBusyMultipleInstance(a) ADC14_isBusy()
-#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_enableModule(b,c,d,e)
+#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_configureConversionMemory(b,c,d,e)
#define ADC14_enableComparatorWindowMultipleInstance(a,b,c) ADC14_enableComparatorWindow(b,c)
#define ADC14_disableComparatorWindowMultipleInstance(a,b) ADC14_disableComparatorWindow(b)
#define ADC14_setComparatorWindowValueMultipleInstance(a,b,c,d) ADC14_setComparatorWindowValue(b,c,d)
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
index 1abc241..a8def1a 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,23 +41,23 @@
bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
uint_fast16_t keyLength)
{
- uint8_t i;
+ uint_fast8_t i;
uint16_t sCipherKey;
- AES256_CMSIS(moduleInstance)->rCTL0.r |= 0;
+ AES256_CMSIS(moduleInstance)->CTL0 |= 0;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
return false;
@@ -69,11 +69,11 @@
{
sCipherKey = (uint16_t) (cipherKey[i]);
sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8);
- AES256_CMSIS(moduleInstance)->rKEY.r = sCipherKey;
+ AES256_CMSIS(moduleInstance)->KEY = sCipherKey;
}
// Wait until key is written
- while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS))
+ while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS))
;
return true;
@@ -82,33 +82,33 @@
void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * encryptedData)
{
- uint8_t i;
+ uint_fast8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to encrypt mode
- AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
+ AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
- AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+ AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
- // Encryption is initialized by setting AESKEYWR to 1
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+ // Encryption is initialized by setting AES256_STAT_KEYWR to 1
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
- while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+ while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
- tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
+ tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(encryptedData + i) = (uint8_t) tempData;
*(encryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
@@ -117,33 +117,33 @@
void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data,
uint8_t * decryptedData)
{
- uint8_t i;
+ uint_fast8_t i;
uint16_t tempData = 0;
uint16_t tempVariable = 0;
// Set module to decrypt mode
- AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
+ AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
- AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+ AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
// Wait unit finished ~167 MCLK
- while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+ while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
- tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
+ tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(decryptedData + i) = (uint8_t) tempData;
*(decryptedData + i + 1) = (uint8_t) (tempData >> 8);
}
@@ -156,21 +156,21 @@
uint16_t tempVariable = 0;
// Set module to decrypt mode
- AES256_CMSIS(moduleInstance)->rCTL0.r =
- (AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
+ AES256_CMSIS(moduleInstance)->CTL0 =
+ (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
@@ -184,11 +184,11 @@
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
- AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
+ AES256_CMSIS(moduleInstance)->KEY = tempVariable;
}
// Wait until key is processed ~52 MCLK
- while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+ while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
;
return true;
@@ -196,27 +196,27 @@
void AES256_clearInterruptFlag(uint32_t moduleInstance)
{
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIFG_OFS) = 0;
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIFG_OFS) = 0;
}
uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance)
{
- return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESRDYIFG_OFS);
+ return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_RDYIFG_OFS);
}
void AES256_enableInterrupt(uint32_t moduleInstance)
{
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 1;
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 1;
}
void AES256_disableInterrupt(uint32_t moduleInstance)
{
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESRDYIE_OFS) = 0;
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 0;
}
void AES256_reset(uint32_t moduleInstance)
{
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r,AESSWRST_OFS) = 1;
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_SWRST_OFS) = 1;
}
void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
@@ -225,63 +225,63 @@
uint16_t tempVariable = 0;
// Set module to encrypt mode
- AES256_CMSIS(moduleInstance)->rCTL0.r &= ~AESOP_M;
+ AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
// Write data to encrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i]);
tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
- AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+ AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
- // Encryption is initialized by setting AESKEYWR to 1
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+ // Encryption is initialized by setting AES256_STAT_KEYWR to 1
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
}
void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data)
{
- uint8_t i;
+ uint_fast8_t i;
uint16_t tempVariable = 0;
// Set module to decrypt mode
- AES256_CMSIS(moduleInstance)->rCTL0.r |= (AESOP_3);
+ AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
// Write data to decrypt to module
for (i = 0; i < 16; i = i + 2)
{
tempVariable = (uint16_t) (data[i + 1] << 8);
tempVariable = tempVariable | ((uint16_t) (data[i]));
- AES256_CMSIS(moduleInstance)->rDIN.r = tempVariable;
+ AES256_CMSIS(moduleInstance)->DIN = tempVariable;
}
// Key that is already written shall be used
// Now decryption starts
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESKEYWR_OFS) = 1;
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
}
bool AES256_startSetDecipherKey(uint32_t moduleInstance,
const uint8_t * cipherKey, uint_fast16_t keyLength)
{
- uint8_t i;
+ uint_fast8_t i;
uint16_t tempVariable = 0;
- AES256_CMSIS(moduleInstance)->rCTL0.r =
- (AES256_CMSIS(moduleInstance)->rCTL0.r & ~AESOP_M) | AESOP1;
+ AES256_CMSIS(moduleInstance)->CTL0 =
+ (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
switch (keyLength)
{
case AES256_KEYLENGTH_128BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__128BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
break;
case AES256_KEYLENGTH_192BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__192BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
break;
case AES256_KEYLENGTH_256BIT:
- AES256_CMSIS(moduleInstance)->rCTL0.r |= AESKL__256BIT;
+ AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
break;
default:
@@ -295,7 +295,7 @@
{
tempVariable = (uint16_t) (cipherKey[i]);
tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
- AES256_CMSIS(moduleInstance)->rKEY.r = tempVariable;
+ AES256_CMSIS(moduleInstance)->KEY = tempVariable;
}
return true;
@@ -307,13 +307,13 @@
uint16_t tempData = 0;
// If module is busy, exit and return failure
- if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS))
+ if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
return false;
// Write encrypted data back to variable
for (i = 0; i < 16; i = i + 2)
{
- tempData = AES256_CMSIS(moduleInstance)->rDOUT.r;
+ tempData = AES256_CMSIS(moduleInstance)->DOUT;
*(outputData + i) = (uint8_t) tempData;
*(outputData + i + 1) = (uint8_t) (tempData >> 8);
}
@@ -323,17 +323,17 @@
bool AES256_isBusy(uint32_t moduleInstance)
{
- return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rSTAT.r, AESBUSY_OFS);
+ return BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS);
}
void AES256_clearErrorFlag(uint32_t moduleInstance)
{
- BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS) = 0;
+ BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS) = 0;
}
uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance)
{
- return BITBAND_PERI(AES256_CMSIS(moduleInstance)->rCTL0.r, AESERRFG_OFS);
+ return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS);
}
void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
index 1bdca8a..a936fd4 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/aes256.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -89,7 +89,7 @@
// can be returned by the AES256_getErrorFlagStatus() function.
//
//*****************************************************************************
-#define AES256_ERROR_OCCURRED AESERRFG
+#define AES256_ERROR_OCCURRED AES256_CTL0_ERRFG
#define AES256_NO_ERROR 0x00
//*****************************************************************************
@@ -98,7 +98,7 @@
// can be returned by the AES256_isBusy() function.
//
//*****************************************************************************
-#define AES256_BUSY AESBUSY
+#define AES256_BUSY AES256_STAT_BUSY
#define AES256_NOT_BUSY 0x00
//*****************************************************************************
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
index 2ab133c..b2ffdfe 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -43,37 +43,37 @@
switch (input)
{
case COMP_E_INPUT0:
- return CEIPSEL_0;
+ return COMP_E_CTL0_IPSEL_0;
case COMP_E_INPUT1:
- return CEIPSEL_1;
+ return COMP_E_CTL0_IPSEL_1;
case COMP_E_INPUT2:
- return CEIPSEL_2;
+ return COMP_E_CTL0_IPSEL_2;
case COMP_E_INPUT3:
- return CEIPSEL_3;
+ return COMP_E_CTL0_IPSEL_3;
case COMP_E_INPUT4:
- return CEIPSEL_4;
+ return COMP_E_CTL0_IPSEL_4;
case COMP_E_INPUT5:
- return CEIPSEL_5;
+ return COMP_E_CTL0_IPSEL_5;
case COMP_E_INPUT6:
- return CEIPSEL_6;
+ return COMP_E_CTL0_IPSEL_6;
case COMP_E_INPUT7:
- return CEIPSEL_7;
+ return COMP_E_CTL0_IPSEL_7;
case COMP_E_INPUT8:
- return CEIPSEL_8;
+ return COMP_E_CTL0_IPSEL_8;
case COMP_E_INPUT9:
- return CEIPSEL_9;
+ return COMP_E_CTL0_IPSEL_9;
case COMP_E_INPUT10:
- return CEIPSEL_10;
+ return COMP_E_CTL0_IPSEL_10;
case COMP_E_INPUT11:
- return CEIPSEL_11;
+ return COMP_E_CTL0_IPSEL_11;
case COMP_E_INPUT12:
- return CEIPSEL_12;
+ return COMP_E_CTL0_IPSEL_12;
case COMP_E_INPUT13:
- return CEIPSEL_13;
+ return COMP_E_CTL0_IPSEL_13;
case COMP_E_INPUT14:
- return CEIPSEL_14;
+ return COMP_E_CTL0_IPSEL_14;
case COMP_E_INPUT15:
- return CEIPSEL_15;
+ return COMP_E_CTL0_IPSEL_15;
case COMP_E_VREF:
return COMP_E_VREF;
default:
@@ -98,40 +98,41 @@
<= COMP_E_FILTEROUTPUT_DLYLVL4);
/* Reset COMPE Control 1 & Interrupt Registers for initialization */
- COMP_E_CMSIS(comparator)->rCTL0.r = 0;
- COMP_E_CMSIS(comparator)->rINT.r = 0;
+ COMP_E_CMSIS(comparator)->CTL0 = 0;
+ COMP_E_CMSIS(comparator)->INT = 0;
// Set the Positive Terminal
if (COMP_E_VREF != positiveTerminalInput)
{
// Enable Positive Terminal Input Mux and Set to the appropriate input
- COMP_E_CMSIS(comparator)->rCTL0.r |= CEIPEN + positiveTerminalInput;
+ COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN
+ + positiveTerminalInput;
// Disable the input buffer
- COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << positiveTerminalInput);
+ COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r,CERSEL_OFS) = 0;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2,COMP_E_CTL2_RSEL_OFS) = 0;
}
// Set the Negative Terminal
if (COMP_E_VREF != negativeTerminalInput)
{
// Enable Negative Terminal Input Mux and Set to the appropriate input
- COMP_E_CMSIS(comparator)->rCTL0.r |= CEIMEN
+ COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IMEN
+ (negativeTerminalInput << 8);
// Disable the input buffer
- COMP_E_CMSIS(comparator)->rCTL3.r |= (1 << negativeTerminalInput);
+ COMP_E_CMSIS(comparator)->CTL3 |= (1 << negativeTerminalInput);
} else
{
// Reset and Set COMPE Control 2 Register
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CERSEL_OFS) = 1;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_RSEL_OFS) = 1;
}
// Reset and Set COMPE Control 1 Register
- COMP_E_CMSIS(comparator)->rCTL1.r = config->powerMode
+ COMP_E_CMSIS(comparator)->CTL1 = config->powerMode
+ config->outputFilterEnableAndDelayLevel
+ config->invertedOutputPolarity;
@@ -149,23 +150,23 @@
upperLimitSupplyVoltageFractionOf32
>= lowerLimitSupplyVoltageFractionOf32);
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEMRVS_OFS) = 0;
- COMP_E_CMSIS(comparator)->rCTL2.r &= CERSEL;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_MRVS_OFS) = 0;
+ COMP_E_CMSIS(comparator)->CTL2 &= COMP_E_CTL2_RSEL;
// Set Voltage Source(Vcc | Vref, resistor ladder or not)
if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)
{
- COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_1;
+ COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_1;
} else if (lowerLimitSupplyVoltageFractionOf32 == 32)
{
- COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_3;
+ COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_3;
} else
{
- COMP_E_CMSIS(comparator)->rCTL2.r |= CERS_2;
+ COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_2;
}
// Set COMPE Control 2 Register
- COMP_E_CMSIS(comparator)->rCTL2.r |= supplyVoltageReferenceBase
+ COMP_E_CMSIS(comparator)->CTL2 |= supplyVoltageReferenceBase
+ ((upperLimitSupplyVoltageFractionOf32 - 1) << 8)
+ (lowerLimitSupplyVoltageFractionOf32 - 1);
}
@@ -178,87 +179,87 @@
|| (referenceAccuracy == COMP_E_ACCURACY_CLOCKED));
if (referenceAccuracy)
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 1;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 1;
else
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL2.r, CEREFACC_OFS) = 0;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 0;
}
void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode)
{
- COMP_E_CMSIS(comparator)->rCTL1.r = (COMP_E_CMSIS(comparator)->rCTL1.r
- & ~(CEPWRMD_M)) | powerMode;
+ COMP_E_CMSIS(comparator)->CTL1 = (COMP_E_CMSIS(comparator)->CTL1
+ & ~(COMP_E_CTL1_PWRMD_MASK)) | powerMode;
}
void COMP_E_enableModule(uint32_t comparator)
{
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 1;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 1;
}
void COMP_E_disableModule(uint32_t comparator)
{
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEON_OFS) = 0;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 0;
}
void COMP_E_shortInputs(uint32_t comparator)
{
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 1;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 1;
}
void COMP_E_unshortInputs(uint32_t comparator)
{
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CESHORT_OFS) = 0;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 0;
}
void COMP_E_disableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
- COMP_E_CMSIS(comparator)->rCTL3.r |= (inputPort);
+ COMP_E_CMSIS(comparator)->CTL3 |= (inputPort);
}
void COMP_E_enableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
{
ASSERT(inputPort <= COMP_E_INPUT15);
- COMP_E_CMSIS(comparator)->rCTL3.r &= ~(inputPort);
+ COMP_E_CMSIS(comparator)->CTL3 &= ~(inputPort);
}
void COMP_E_swapIO(uint32_t comparator)
{
- COMP_E_CMSIS(comparator)->rCTL1.r ^= CEEX; // Toggle CEEX bit
+ COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_EX; // Toggle CEEX bit
}
uint8_t COMP_E_outputValue(uint32_t comparator)
{
- return COMP_E_CMSIS(comparator)->rCTL1.r & CEOUT;
+ return COMP_E_CMSIS(comparator)->CTL1 & COMP_E_CTL1_OUT;
}
void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
// Set the Interrupt enable bit
- COMP_E_CMSIS(comparator)->rINT.r |= mask;
+ COMP_E_CMSIS(comparator)->INT |= mask;
}
uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator)
{
return COMP_E_getInterruptStatus(comparator) &
- COMP_E_CMSIS(comparator)->rINT.r;
+ COMP_E_CMSIS(comparator)->INT;
}
void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask)
{
- COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
+ COMP_E_CMSIS(comparator)->INT &= ~(mask);
}
void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask)
{
- COMP_E_CMSIS(comparator)->rINT.r &= ~(mask);
+ COMP_E_CMSIS(comparator)->INT &= ~(mask);
}
uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator)
{
- return (COMP_E_CMSIS(comparator)->rINT.r & (COMP_E_OUTPUT_INTERRUPT_FLAG |
+ return (COMP_E_CMSIS(comparator)->INT & (COMP_E_OUTPUT_INTERRUPT_FLAG |
COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY |
COMP_E_INTERRUPT_FLAG_READY));
}
@@ -270,25 +271,25 @@
// Set the edge direction that will trigger an interrupt
if (COMP_E_RISINGEDGE == edgeDirection)
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 1;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 1;
else if (COMP_E_FALLINGEDGE == edgeDirection)
- BITBAND_PERI(COMP_E_CMSIS(comparator)->rCTL1.r, CEIES_OFS) = 0;
+ BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 0;
}
void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator)
{
- COMP_E_CMSIS(comparator)->rCTL1.r ^= CEIES;
+ COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_IES;
}
void COMP_E_registerInterrupt(uint32_t comparator, void (*intHandler)(void))
{
switch (comparator)
{
- case COMP_E0_MODULE:
+ case COMP_E0_BASE:
Interrupt_registerInterrupt(INT_COMP_E0, intHandler);
Interrupt_enableInterrupt(INT_COMP_E0);
break;
- case COMP_E1_MODULE:
+ case COMP_E1_BASE:
Interrupt_registerInterrupt(INT_COMP_E1, intHandler);
Interrupt_enableInterrupt(INT_COMP_E1);
break;
@@ -301,11 +302,11 @@
{
switch (comparator)
{
- case COMP_E0_MODULE:
+ case COMP_E0_BASE:
Interrupt_disableInterrupt(INT_COMP_E0);
Interrupt_unregisterInterrupt(INT_COMP_E0);
break;
- case COMP_E1_MODULE:
+ case COMP_E1_BASE:
Interrupt_disableInterrupt(INT_COMP_E1);
Interrupt_unregisterInterrupt(INT_COMP_E1);
break;
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
index d250d62..8ddefa4 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/comp_e.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -60,13 +60,13 @@
#include <msp.h>
/* Module defines for Comp */
-#define COMP_E_CMSIS(x) ((COMP_E0_Type *) x)
+#define COMP_E_CMSIS(x) ((COMP_E_Type *) x)
#define COMP_E_FILTEROUTPUT_OFF 0x00
-#define COMP_E_FILTEROUTPUT_DLYLVL1 (CEF + CEFDLY_0)
-#define COMP_E_FILTEROUTPUT_DLYLVL2 (CEF + CEFDLY_1)
-#define COMP_E_FILTEROUTPUT_DLYLVL3 (CEF + CEFDLY_2)
-#define COMP_E_FILTEROUTPUT_DLYLVL4 (CEF + CEFDLY_3)
+#define COMP_E_FILTEROUTPUT_DLYLVL1 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_0)
+#define COMP_E_FILTEROUTPUT_DLYLVL2 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_1)
+#define COMP_E_FILTEROUTPUT_DLYLVL3 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_2)
+#define COMP_E_FILTEROUTPUT_DLYLVL4 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_3)
#define COMP_E_INPUT0 (0x01)
#define COMP_E_INPUT1 (0x02)
@@ -86,38 +86,38 @@
#define COMP_E_INPUT15 (0x8000)
#define COMP_E_VREF (0x9F)
-#define COMP_E_NORMALOUTPUTPOLARITY (!(CEOUTPOL))
-#define COMP_E_INVERTEDOUTPUTPOLARITY (CEOUTPOL)
+#define COMP_E_NORMALOUTPUTPOLARITY (!(COMP_E_CTL1_OUTPOL))
+#define COMP_E_INVERTEDOUTPUTPOLARITY (COMP_E_CTL1_OUTPOL)
-#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (CEREFL_0)
-#define COMP_E_VREFBASE1_2V (CEREFL_1)
-#define COMP_E_VREFBASE2_0V (CEREFL_2)
-#define COMP_E_VREFBASE2_5V (CEREFL_3)
+#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (COMP_E_CTL2_CEREFL_0)
+#define COMP_E_VREFBASE1_2V (COMP_E_CTL2_CEREFL_1)
+#define COMP_E_VREFBASE2_0V (COMP_E_CTL2_CEREFL_2)
+#define COMP_E_VREFBASE2_5V (COMP_E_CTL2_CEREFL_3)
-#define COMP_E_ACCURACY_STATIC (!CEREFACC)
-#define COMP_E_ACCURACY_CLOCKED (CEREFACC)
+#define COMP_E_ACCURACY_STATIC (!COMP_E_CTL2_REFACC)
+#define COMP_E_ACCURACY_CLOCKED (COMP_E_CTL2_REFACC)
-#define COMP_E_HIGH_SPEED_MODE (CEPWRMD_0)
-#define COMP_E_NORMAL_MODE (CEPWRMD_1)
-#define COMP_E_ULTRA_LOW_POWER_MODE (CEPWRMD_2)
+#define COMP_E_HIGH_SPEED_MODE (COMP_E_CTL1_PWRMD_0)
+#define COMP_E_NORMAL_MODE (COMP_E_CTL1_PWRMD_1)
+#define COMP_E_ULTRA_LOW_POWER_MODE (COMP_E_CTL1_PWRMD_2)
-#define COMP_E_OUTPUT_INTERRUPT (CEIE)
-#define COMP_E_INVERTED_POLARITY_INTERRUPT (CEIIE)
-#define COMP_E_READY_INTERRUPT (CERDYIE)
+#define COMP_E_OUTPUT_INTERRUPT (COMP_E_INT_IE)
+#define COMP_E_INVERTED_POLARITY_INTERRUPT (COMP_E_INT_IIE)
+#define COMP_E_READY_INTERRUPT (COMP_E_INT_RDYIE)
-#define COMP_E_OUTPUT_INTERRUPT_FLAG (CEIFG)
-#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (CEIIFG)
-#define COMP_E_INTERRUPT_FLAG_READY (CERDYIFG)
+#define COMP_E_OUTPUT_INTERRUPT_FLAG (COMP_E_INT_IFG)
+#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (COMP_E_INT_IIFG)
+#define COMP_E_INTERRUPT_FLAG_READY (COMP_E_INT_RDYIFG)
-#define COMP_E_FALLINGEDGE (!(CEIES))
-#define COMP_E_RISINGEDGE (CEIES)
+#define COMP_E_FALLINGEDGE (!(COMP_E_CTL1_IES))
+#define COMP_E_RISINGEDGE (COMP_E_CTL1_IES)
-#define COMP_E_LOW (0x0)
-#define COMP_E_HIGH (CEOUT)
+#define COMP_E_LOW (0x0)
+#define COMP_E_HIGH (COMP_E_CTL1_OUT)
//*****************************************************************************
//
-//! \typedef COMP_E_Config
+//! ypedef COMP_E_Config
//! \brief Type definition for \link _COMP_E_Config \endlink structure
//!
//! \struct _COMP_E_Config
@@ -140,8 +140,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param config Configuration structure for the Comparator module
//!
//! <hr>
@@ -230,8 +230,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param supplyVoltageReferenceBase decides the source and max amount of
//! Voltage that can be used as a reference.
//! Valid values are
@@ -267,8 +267,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param referenceAccuracy is the reference accuracy setting of the
//! comparator. Clocked is for low power/low accuracy.
//! Valid values are
@@ -291,8 +291,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param powerMode decides the power mode
//! Valid values are
//! - \b COMP_E_HIGH_SPEED_MODE
@@ -311,8 +311,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This function sets the bit that enables the operation of the
//! Comparator module.
@@ -328,8 +328,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This function clears the CEON bit disabling the operation of the Comparator
//! module, saving from excess power consumption.
@@ -346,8 +346,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This function sets the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
@@ -364,8 +364,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This function clears the bit that shorts the devices attached to the input
//! pins chosen from the initialization of the comparator.
@@ -383,8 +383,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param inputPort is the port in which the input buffer will be disabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
@@ -425,8 +425,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param inputPort is the port in which the input buffer will be enabled.
//! Valid values are a logical OR of the following:
//! - \b COMP_E_INPUT0 [Default]
@@ -484,8 +484,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid parameters
//! vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! Returns the output value of the Comparator module.
//!
@@ -501,8 +501,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param mask is the bit mask of the interrupt sources to be enabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
@@ -527,8 +527,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param mask is the bit mask of the interrupt sources to be disabled.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
@@ -551,8 +551,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param mask is a bit mask of the interrupt sources to be cleared.
//! Mask value is the logical OR of any of the following
//! - \b COMP_E_INTERRUPT_FLAG - Output interrupt flag
@@ -575,8 +575,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This returns the interrupt status for the Comparator module based on which
//! flag is passed.
@@ -595,8 +595,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! Enables the indicated Comparator interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
@@ -615,8 +615,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//! \param edgeDirection determines which direction the edge would have to go
//! to generate an interrupt based on the non-inverted interrupt flag.
//! Valid values are
@@ -646,8 +646,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This function will toggle which direction the output will have to go,
//! whether rising or falling, to generate an interrupt based on a non-inverted
@@ -670,8 +670,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This function registers the handler to be called when a Comparator
//! interrupt occurs. This function enables the global interrupt in the
@@ -691,8 +691,8 @@
//!
//! \param comparator is the instance of the Comparator module. Valid
//! parameters vary from part to part, but can include:
-//! - \b COMP_E0
-//! - \b COMP_E1
+//! - \b COMP_E0_BASE
+//! - \b COMP_E1_BASE
//!
//! This function unregisters the handler to be called when Comparator E
//! interrupt occurs. This function also masks off the interrupt in the
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
index 1e70e51..de7f5fc 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -44,7 +44,7 @@
// on entry.
//
//*****************************************************************************
-#if defined(gcc)
+#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_cpsid(void)
{
uint32_t ret;
@@ -66,7 +66,7 @@
return(ret);
}
#endif
-#if defined(ewarm)
+#if defined(__ICCARM__)
uint32_t CPU_cpsid(void)
{
//
@@ -84,7 +84,7 @@
}
#pragma diag_default=Pe940
#endif
-#if defined(keil)
+#if defined(__CC_ARM)
__asm uint32_t CPU_cpsid(void)
{
//
@@ -95,7 +95,7 @@
bx lr
}
#endif
-#if defined(ccs)
+#if defined(__TI_ARM__)
uint32_t CPU_cpsid(void)
{
//
@@ -122,7 +122,7 @@
// interrupts are enabled or disabled).
//
//*****************************************************************************
-#if defined(gcc)
+#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_primask(void)
{
uint32_t ret;
@@ -143,7 +143,7 @@
return(ret);
}
#endif
-#if defined(ewarm)
+#if defined(__ICCARM__)
uint32_t CPU_primask(void)
{
//
@@ -160,7 +160,7 @@
}
#pragma diag_default=Pe940
#endif
-#if defined(keil)
+#if defined(__CC_ARM)
__asm uint32_t CPU_primask(void)
{
//
@@ -170,7 +170,7 @@
bx lr
}
#endif
-#if defined(ccs)
+#if defined(__TI_ARM__)
uint32_t CPU_primask(void)
{
//
@@ -196,7 +196,7 @@
// on entry.
//
//*****************************************************************************
-#if defined(gcc)
+#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_cpsie(void)
{
uint32_t ret;
@@ -218,7 +218,7 @@
return(ret);
}
#endif
-#if defined(ewarm)
+#if defined(__ICCARM__)
uint32_t CPU_cpsie(void)
{
//
@@ -236,7 +236,7 @@
}
#pragma diag_default=Pe940
#endif
-#if defined(keil)
+#if defined(__CC_ARM)
__asm uint32_t CPU_cpsie(void)
{
//
@@ -247,7 +247,7 @@
bx lr
}
#endif
-#if defined(ccs)
+#if defined(__TI_ARM__)
uint32_t CPU_cpsie(void)
{
//
@@ -273,7 +273,7 @@
// Wrapper function for the CPUWFI instruction.
//
//*****************************************************************************
-#if defined(gcc)
+#if defined(__GNUC__)
void __attribute__((naked)) CPU_wfi(void)
{
//
@@ -283,7 +283,7 @@
" bx lr\n");
}
#endif
-#if defined(ewarm)
+#if defined(__ICCARM__)
void CPU_wfi(void)
{
//
@@ -292,7 +292,7 @@
__asm(" wfi\n");
}
#endif
-#if defined(keil)
+#if defined(__CC_ARM)
__asm void CPU_wfi(void)
{
//
@@ -302,7 +302,7 @@
bx lr
}
#endif
-#if defined(ccs)
+#if defined(__TI_ARM__)
void CPU_wfi(void)
{
//
@@ -317,7 +317,7 @@
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
-#if defined(gcc)
+#if defined(__GNUC__)
void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -327,7 +327,7 @@
" bx lr\n");
}
#endif
-#if defined(ewarm)
+#if defined(__ICCARM__)
void CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -336,7 +336,7 @@
__asm(" msr BASEPRI, r0\n");
}
#endif
-#if defined(keil)
+#if defined(__CC_ARM)
__asm void CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -346,7 +346,7 @@
bx lr
}
#endif
-#if defined(ccs)
+#if defined(__TI_ARM__)
void CPU_basepriSet(uint32_t newBasepri)
{
//
@@ -361,7 +361,7 @@
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
-#if defined(gcc)
+#if defined(__GNUC__)
uint32_t __attribute__((naked)) CPU_basepriGet(void)
{
uint32_t ret;
@@ -382,7 +382,7 @@
return(ret);
}
#endif
-#if defined(ewarm)
+#if defined(__ICCARM__)
uint32_t CPU_basepriGet(void)
{
//
@@ -399,7 +399,7 @@
}
#pragma diag_default=Pe940
#endif
-#if defined(keil)
+#if defined(__CC_ARM)
__asm uint32_t CPU_basepriGet(void)
{
//
@@ -409,7 +409,7 @@
bx lr
}
#endif
-#if defined(ccs)
+#if defined(__TI_ARM__)
uint32_t CPU_basepriGet(void)
{
//
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
index 8ac6875..29df4b6 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cpu.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
index 8db29b40..8747c41 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,17 +37,18 @@
#include "crc32.h"
#include <msp.h>
#include <debug.h>
+#include <hw_memmap.h>
void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType)
{
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
- CRC32->rCRC16INIRES = seed;
+ CRC32->INIRES16 = seed;
else
{
- CRC32->rCRC32INIRES_HI = ((seed & 0xFFFF0000) >> 16);
- CRC32->rCRC32INIRES_LO = (seed & 0xFFFF);
+ CRC32->INIRES32_HI = ((seed & 0xFFFF0000) >> 16);
+ CRC32->INIRES32_LO = (seed & 0xFFFF);
}
}
@@ -56,9 +57,9 @@
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
- HWREG8(CRC32_BASE + OFS_CRC16DI) = dataIn;
+ HWREG8(&(CRC32->DI16)) = dataIn;
else
- HWREG8(CRC32_BASE + OFS_CRC32DI) = dataIn;
+ HWREG8(&(CRC32->DI32)) = dataIn;
}
void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
@@ -66,18 +67,18 @@
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
- CRC32->rCRC16DI = dataIn;
+ CRC32->DI16 = dataIn;
else
- CRC32->rCRC32DI = dataIn;
+ CRC32->DI32 = dataIn;
}
void CRC32_set32BitData(uint32_t dataIn)
{
- //CRC32->rCRC32DI = dataIn & 0xFFFF;
- //CRC32->rCRC32DI = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
+ //CRC32->DI32 = dataIn & 0xFFFF;
+ //CRC32->DI32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
- HWREG16(CRC32_BASE + OFS_CRC32DI) = dataIn & 0xFFFF;
- HWREG16(CRC32_BASE + OFS_CRC32DI) = (uint16_t)(
+ HWREG16(&(CRC32->DI32)) = dataIn & 0xFFFF;
+ HWREG16(&(CRC32->DI32)) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
}
@@ -86,9 +87,9 @@
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
- HWREG8(CRC32_BASE + OFS_CRC16DIRB) = dataIn;
+ HWREG8(&(CRC32->DIRB16)) = dataIn;
else
- HWREG8(CRC32_BASE + OFS_CRC32DIRB) = dataIn;
+ HWREG8(&(CRC32->DIRB32)) = dataIn;
}
void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
@@ -96,18 +97,20 @@
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
- CRC32->rCRC16DIRB = dataIn;
+ CRC32->DIRB16 = dataIn;
else
- CRC32->rCRC32DIRB = dataIn;
+ CRC32->DIRB32 = dataIn;
}
void CRC32_set32BitDataReversed(uint32_t dataIn)
{
- HWREG16(CRC32_BASE + OFS_CRC32DIRB) = dataIn & 0xFFFF;
- HWREG16(CRC32_BASE + OFS_CRC32DIRB) = (uint16_t)(
+ //CRC32->DIRB32 = dataIn & 0xFFFF;
+ //CRC32->DIRB32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
+
+ HWREG16(&(CRC32->DIRB32)) = dataIn & 0xFFFF;
+ HWREG16(&(CRC32->DIRB32)) = (uint16_t)(
(dataIn & 0xFFFF0000) >> 16);
- //CRC32->rCRC32DIRB = dataIn & 0xFFFF;
- //CRC32->rCRC32DIRB = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
+
}
uint32_t CRC32_getResult(uint_fast8_t crcType)
@@ -116,12 +119,12 @@
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
- return CRC32->rCRC16INIRES;
+ return CRC32->INIRES16;
else
{
- result = CRC32->rCRC32INIRES_HI;
+ result = CRC32->INIRES32_HI;
result = (result << 16);
- result |= CRC32->rCRC32INIRES_LO;
+ result |= CRC32->INIRES32_LO;
return (result);
}
}
@@ -132,12 +135,12 @@
ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
if (CRC16_MODE == crcType)
- return CRC32->rCRC16RESR;
+ return CRC32->RESR16;
else
{
- result = CRC32->rCRC32RESR_HI;
+ result = CRC32->RESR32_HI;
result = (result << 16);
- result |= CRC32->rCRC32RESR_LO;
+ result |= CRC32->RESR32_LO;
return (result);
}
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
index e385e7a..fec4f7a 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/crc32.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
index 40fa250..692fcd9 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -62,19 +62,19 @@
static uint32_t _CSGetHFXTFrequency()
{
if (hfxtFreq >= CS_1MHZ && hfxtFreq <= CS_4MHZ)
- return HFXTFREQ_0;
+ return CS_CTL2_HFXTFREQ_0;
else if (hfxtFreq > CS_4MHZ && hfxtFreq <= CS_8MHZ)
- return HFXTFREQ_1;
+ return CS_CTL2_HFXTFREQ_1;
else if (hfxtFreq > CS_8MHZ && hfxtFreq <= CS_16MHZ)
- return HFXTFREQ_2;
+ return CS_CTL2_HFXTFREQ_2;
else if (hfxtFreq > CS_16MHZ && hfxtFreq <= CS_24MHZ)
- return HFXTFREQ_3;
+ return CS_CTL2_HFXTFREQ_3;
else if (hfxtFreq > CS_24MHZ && hfxtFreq <= CS_32MHZ)
- return HFXTFREQ_4;
+ return CS_CTL2_HFXTFREQ_4;
else if (hfxtFreq > CS_32MHZ && hfxtFreq <= CS_40MHZ)
- return HFXTFREQ_5;
+ return CS_CTL2_HFXTFREQ_5;
else if (hfxtFreq > CS_40MHZ && hfxtFreq <= CS_48MHZ)
- return HFXTFREQ_5;
+ return CS_CTL2_HFXTFREQ_5;
else
{
ASSERT(false);
@@ -111,7 +111,7 @@
static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider)
{
- uint8_t bDivider;
+ uint_fast8_t bDivider;
bDivider = _CSGetDividerValue(wDivider);
@@ -119,32 +119,32 @@
{
case CS_LFXTCLK_SELECT:
{
- if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
+ if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
CS_clearInterruptFlag(CS_LFXT_FAULT);
- if (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
+ if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
- if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
+ if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
return (128000 / bDivider);
else
- return (32000 / bDivider);
+ return (32768 / bDivider);
}
}
return lfxtFreq / bDivider;
}
case CS_HFXTCLK_SELECT:
{
- if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
+ if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
CS_clearInterruptFlag(CS_HFXT_FAULT);
- if (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
+ if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
- if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
+ if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
return (128000 / bDivider);
else
- return (32000 / bDivider);
+ return (32768 / bDivider);
}
}
return hfxtFreq / bDivider;
@@ -153,10 +153,10 @@
return CS_VLOCLK_FREQUENCY / bDivider;
case CS_REFOCLK_SELECT:
{
- if (BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS))
+ if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
return (128000 / bDivider);
else
- return (32000 / bDivider);
+ return (32768 / bDivider);
}
case CS_DCOCLK_SELECT:
return (CS_getDCOFrequency() / bDivider);
@@ -175,24 +175,24 @@
{
uint32_t dcoFreq;
- switch (CS->rCTL0.r & DCORSEL_M)
+ switch (CS->CTL0 & CS_CTL0_DCORSEL_MASK)
{
- case DCORSEL_0:
+ case CS_CTL0_DCORSEL_0:
dcoFreq = 1500000;
break;
- case DCORSEL_1:
+ case CS_CTL0_DCORSEL_1:
dcoFreq = 3000000;
break;
- case DCORSEL_2:
+ case CS_CTL0_DCORSEL_2:
dcoFreq = 6000000;
break;
- case DCORSEL_3:
+ case CS_CTL0_DCORSEL_3:
dcoFreq = 12000000;
break;
- case DCORSEL_4:
+ case CS_CTL0_DCORSEL_4:
dcoFreq = 24000000;
break;
- case DCORSEL_5:
+ case CS_CTL0_DCORSEL_5:
dcoFreq = 48000000;
break;
default:
@@ -215,7 +215,7 @@
ASSERT(_CSIsClockDividerValid(clockSourceDivider));
/* Unlocking the CS Module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
switch (selectedClockSignal)
{
@@ -231,16 +231,16 @@
/* Waiting for the clock source ready bit to be valid before
* changing */
- while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS))
;
/* Setting the divider and source */
- CS->rCTL1.r = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS)
+ CS->CTL1 = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS)
| (clockSource << CS_ACLK_SRC_BITPOS))
- | (CS->rCTL1.r & ~(SELA_M | DIVA_M));
+ | (CS->CTL1 & ~(CS_CTL1_SELA_MASK | CS_CTL1_DIVA_MASK));
/* Waiting for ACLK to be ready again */
- while (!BITBAND_PERI(CS->rSTAT.r, ACLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS))
;
break;
@@ -250,15 +250,15 @@
/* Waiting for the clock source ready bit to be valid before
* changing */
- while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS))
;
- CS->rCTL1.r = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS)
+ CS->CTL1 = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS)
| (clockSource << CS_MCLK_SRC_BITPOS))
- | (CS->rCTL1.r & ~(SELM_M | DIVM_M));
+ | (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK));
/* Waiting for MCLK to be ready */
- while (!BITBAND_PERI(CS->rSTAT.r, MCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS))
;
break;
@@ -267,15 +267,15 @@
{
/* Waiting for the clock source ready bit to be valid before
* changing */
- while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS))
;
- CS->rCTL1.r = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS)
+ CS->CTL1 = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS)
| (clockSource << CS_HSMCLK_SRC_BITPOS))
- | (CS->rCTL1.r & ~(DIVS_M | SELS_M));
+ | (CS->CTL1 & ~(CS_CTL1_DIVS_MASK | CS_CTL1_SELS_MASK));
/* Waiting for SMCLK to be ready */
- while (!BITBAND_PERI(CS->rSTAT.r, SMCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS))
;
break;
@@ -284,15 +284,15 @@
{
/* Waiting for the clock source ready bit to be valid before
* changing */
- while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS))
;
- CS->rCTL1.r = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS)
+ CS->CTL1 = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS)
| (clockSource << CS_HSMCLK_SRC_BITPOS))
- | (CS->rCTL1.r & ~(DIVHS_M | SELS_M));
+ | (CS->CTL1 & ~(CS_CTL1_DIVHS_MASK | CS_CTL1_SELS_MASK));
/* Waiting for HSMCLK to be ready */
- while (!BITBAND_PERI(CS->rSTAT.r, HSMCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS))
;
break;
@@ -302,21 +302,21 @@
/* Waiting for the clock source ready bit to be valid before
* changing */
- while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS))
;
/* Setting the clock source and then returning
* (cannot divide CLK)
*/
if (clockSource == CS_LFXTCLK_SELECT)
- BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 0;
+ BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 0;
else if (clockSource == CS_REFOCLK_SELECT)
- BITBAND_PERI(CS->rCTL1.r, SELB_OFS) = 1;
+ BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 1;
else
ASSERT(false);
/* Waiting for BCLK to be ready */
- while (!BITBAND_PERI(CS->rSTAT.r, BCLK_READY_OFS))
+ while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS))
;
break;
@@ -329,22 +329,22 @@
}
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
-void CS_startHFXT(bool bypassMode)
+bool CS_startHFXT(bool bypassMode)
{
- CS_startHFXTWithTimeout(bypassMode, 0);
+ return CS_startHFXTWithTimeout(bypassMode, 0);
}
-void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
+bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
{
uint32_t wHFFreqRange;
- uint8_t bNMIStatus;
+ uint_fast8_t bNMIStatus;
bool boolTimeout;
/* Unlocking the CS Module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
@@ -355,50 +355,54 @@
boolTimeout = (timeout == 0) ? false : true;
/* Setting to maximum drive strength */
- BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
- CS->rCTL2.r = (CS->rCTL2.r & (~HFXTFREQ_M)) | (wHFFreqRange);
+ BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
+ CS->CTL2 = (CS->CTL2 & (~CS_CTL2_HFXTFREQ_MASK)) | (wHFFreqRange);
if (bypassMode)
{
- BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 1;
+ BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 1;
} else
{
- BITBAND_PERI(CS->rCTL2.r, HFXTBYPASS_OFS) = 0;
+ BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 0;
}
/* Starting and Waiting for frequency stabilization */
- BITBAND_PERI(CS->rCTL2.r, HFXT_EN_OFS) = 1;
- while (BITBAND_PERI(CS->rIFG.r, HFXTIFG_OFS))
+ BITBAND_PERI(CS->CTL2, CS_CTL2_HFXT_EN_OFS) = 1;
+ while (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if (boolTimeout && ((--timeout) == 0))
break;
- BITBAND_PERI(CS->rCLRIFG.r,CLR_HFXTIFG_OFS) = 1;
+ BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_HFXTIFG_OFS) = 1;
}
-
+
/* Setting the drive strength */
if (!bypassMode)
{
- if (wHFFreqRange != HFXTFREQ_0)
- BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 1;
+ if (wHFFreqRange != CS_CTL2_HFXTFREQ_0)
+ BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
else
- BITBAND_PERI(CS->rCTL2.r, HFXTDRIVE_OFS) = 0;
+ BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 0;
}
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
/* Enabling the NMI state */
SysCtl_enableNMISource(bNMIStatus);
+
+ if(boolTimeout && timeout == 0)
+ return false;
+ return true;
}
-void CS_startLFXT(uint32_t xtDrive)
+bool CS_startLFXT(uint32_t xtDrive)
{
- CS_startLFXTWithTimeout(xtDrive, 0);
+ return CS_startLFXTWithTimeout(xtDrive, 0);
}
-void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
+bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
{
uint8_t bNMIStatus;
bool boolBypassMode, boolTimeout;
@@ -411,7 +415,7 @@
|| (xtDrive == CS_LFXT_BYPASS));
/* Unlocking the CS Module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
/* Saving status and temporarily disabling NMIs for UCS faults */
bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC;
@@ -422,35 +426,40 @@
/* Setting to maximum drive strength */
if (boolBypassMode)
{
- BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 1;
+ BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 1;
} else
{
- CS->rCTL2.r |= (CS_LFXT_DRIVE3);
- BITBAND_PERI(CS->rCTL2.r, LFXTBYPASS_OFS) = 0;
+ CS->CTL2 |= (CS_LFXT_DRIVE3);
+ BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 0;
}
/* Waiting for frequency stabilization */
- BITBAND_PERI(CS->rCTL2.r, LFXT_EN_OFS) = 1;
+ BITBAND_PERI(CS->CTL2, CS_CTL2_LFXT_EN_OFS) = 1;
- while (BITBAND_PERI(CS->rIFG.r, LFXTIFG_OFS))
+ while (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
if (boolTimeout && ((--timeout) == 0))
break;
- BITBAND_PERI(CS->rCLRIFG.r,CLR_LFXTIFG_OFS) = 1;
+ BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_LFXTIFG_OFS) = 1;
}
/* Setting the drive strength */
if (!boolBypassMode)
{
- CS->rCTL2.r = ((CS->rCTL2.r & ~CS_LFXT_DRIVE3) | xtDrive);
+ CS->CTL2 = ((CS->CTL2 & ~CS_LFXT_DRIVE3) | xtDrive);
}
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
/* Enabling the NMI state */
SysCtl_enableNMISource(bNMIStatus);
+
+ if(boolTimeout && timeout == 0)
+ return false;
+
+ return true;
}
void CS_enableClockRequest(uint32_t selectClock)
@@ -460,12 +469,12 @@
|| selectClock == CS_SMCLK || selectClock == CS_MCLK);
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- CS->rCLKEN.r |= selectClock;
+ CS->CLKEN |= selectClock;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_disableClockRequest(uint32_t selectClock)
@@ -475,12 +484,12 @@
|| selectClock == CS_SMCLK || selectClock == CS_MCLK);
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- CS->rCLKEN.r &= ~selectClock;
+ CS->CLKEN &= ~selectClock;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency)
@@ -490,39 +499,64 @@
|| referenceFrequency == CS_REFO_128KHZ);
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- BITBAND_PERI(CS->rCLKEN.r, REFOFSEL_OFS) = referenceFrequency;
+ BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS) = referenceFrequency;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_enableDCOExternalResistor(void)
{
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 1;
+ BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 1;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
-void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData)
+void CS_setDCOExternalResistorCalibration(uint_fast8_t calData,
+ uint_fast8_t freqRange)
{
- CS->rDCOERCAL.r = (uiCalData);
+ uint_fast8_t rselVal;
+
+ /* Unlocking the module */
+ CS->KEY = CS_KEY;
+
+ rselVal = (CS->CTL0 | CS_CTL0_DCORSEL_MASK)>>CS_CTL0_DCORSEL_OFS;
+
+ CS->CTL0 &= ~CS_CTL0_DCORSEL_MASK;
+
+ if( (freqRange == CS_OVER32MHZ) && ( TLV->HWREV > DEVICE_PG1_1))
+ {
+ CS->DCOERCAL1 &= ~CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK;
+ CS->DCOERCAL1 |= (calData);
+ }
+ else
+ {
+ CS->DCOERCAL0 &= ~CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK;
+ CS->DCOERCAL0 |= (calData)<<CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS;
+ }
+
+ CS->CTL0 |= (rselVal)<<CS_CTL0_DCORSEL_OFS;
+
+ /* Locking the module */
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+
}
void CS_disableDCOExternalResistor(void)
{
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- BITBAND_PERI(CS->rCTL0.r,DCORES_OFS) = 0;
+ BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 0;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_setDCOCenteredFrequency(uint32_t dcoFreq)
@@ -535,32 +569,39 @@
|| dcoFreq == CS_DCO_FREQUENCY_48);
/* Unlocking the CS Module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
/* Resetting Tuning Parameters and Setting the frequency */
- CS->rCTL0.r = ((CS->rCTL0.r & ~DCORSEL_M) | dcoFreq);
+ CS->CTL0 = ((CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dcoFreq);
/* Locking the CS Module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_tuneDCOFrequency(int16_t tuneParameter)
{
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
+
+ uint16_t dcoTuneMask = 0x1FFF;
+ uint16_t dcoTuneSigned = 0x1000;
+
+ if (TLV->HWREV > DEVICE_PG1_1) {
+ dcoTuneMask = 0x3FF;
+ dcoTuneSigned = 0x200;
+ }
if (tuneParameter < 0)
{
- CS->rCTL0.r = ((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M)
- | 0x1000);
+ CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
+ & dcoTuneMask) | dcoTuneSigned);
}
else
{
- CS->rCTL0.r =
- ((CS->rCTL0.r & ~DCOTUNE_M) | (tuneParameter & DCOTUNE_M));
-
+ CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter
+ & dcoTuneMask));
}
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
uint32_t CS_getDCOFrequency(void)
@@ -569,57 +610,87 @@
int32_t calVal;
uint32_t centeredFreq;
int16_t dcoTune;
+ uint_fast8_t tlvLength;
+ SysCtl_CSCalTLV_Info *csInfo;
+ uint32_t retVal;
- dcoTune = CS->rCTL0.b.bDCOTUNE;
centeredFreq = _CSGetDOCFrequency();
+ /* Parsing the TLV and getting the maximum erase pulses */
+ SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**)&csInfo);
+
+ if(tlvLength == 0)
+ {
+ return centeredFreq;
+ }
+
+ /* Checking to see if we need to do signed conversion */
+ if ( TLV->HWREV > DEVICE_PG1_1)
+ {
+ dcoTune = CS->CTL0 & 0x3FF;
+ if (dcoTune & 0x200)
+ {
+ dcoTune = dcoTune | 0xFE00;
+ }
+ }
+ else
+ {
+ dcoTune = CS->CTL0 & 0x1FFF;
+ if (dcoTune & 0x1000)
+ {
+ dcoTune = dcoTune | 0xF000;
+ }
+ }
+
if (dcoTune == 0)
return (uint32_t) centeredFreq;
- /* Checking to see if we need to do signed conversion */
- if (dcoTune & 0x1000)
+ /* DCORSEL = 5 */
+ if ((centeredFreq == 48000000) && ( TLV->HWREV > DEVICE_PG1_1))
{
- dcoTune = dcoTune | 0xF000;
- }
-
- /* DCORSEL = 5, in final silicon this will have a different calibration
- value, but currently DCORSEL5 calibration is not populated
- if (centeredFreq == 48000000)
- {
- External Resistor
- if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
+ /* External Resistor */
+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
- dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
- calVal = TLV->rDCOER_FCAL_RSEL5;
- }
- Internal Resistor
- else
- {
- dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
- calVal = TLV->rDCOIR_FCAL_RSEL5;
- }
- }
- DCORSEL = 4
- else
- {*/
- /* External Resistor */
- if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
- {
- dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
- calVal = TLV->rDCOER_FCAL_RSEL04;
+ dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5);
+ calVal = csInfo->rDCOER_FCAL_RSEL5;
}
/* Internal Resistor */
else
{
- dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
- calVal = TLV->rDCOIR_FCAL_RSEL04;
+ dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5);
+ calVal = csInfo->rDCOIR_FCAL_RSEL5;
}
- /*}*/
+ }
+ /* DCORSEL = 4 */
+ else
+ {
+ /* External Resistor */
+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+ {
+ dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04);
+ calVal = csInfo->rDCOER_FCAL_RSEL04;
+ }
+ /* Internal Resistor */
+ else
+ {
+ dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04);
+ calVal = csInfo->rDCOIR_FCAL_RSEL04;
+ }
+ }
- return (uint32_t) ((centeredFreq)
- / (1
- - ((dcoConst * dcoTune)
- / (8 * (1 + dcoConst * (768 - calVal))))));
+ if( TLV->HWREV > DEVICE_PG1_1 )
+ {
+ retVal = (uint32_t) (centeredFreq)
+ / (1 - ((dcoConst * dcoTune)
+ / ((1 + dcoConst * (768 - calVal)))));
+ }
+ else
+ {
+ retVal = (uint32_t) (centeredFreq)
+ / (1 - ((dcoConst * dcoTune)
+ / (8 * (1 + dcoConst * (768 - calVal)))));
+ }
+ return retVal;
}
void CS_setDCOFrequency(uint32_t dcoFrequency)
@@ -627,8 +698,10 @@
int32_t nomFreq, calVal, dcoSigned;
int16_t dcoTune;
float dcoConst;
- // bool rsel5 = false;
+ bool rsel5 = false;
dcoSigned = (int32_t) dcoFrequency;
+ uint_fast8_t tlvLength;
+ SysCtl_CSCalTLV_Info *csInfo;
if (dcoFrequency < 2000000)
{
@@ -654,56 +727,62 @@
{
nomFreq = CS_48MHZ;
CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
- // rsel5 = true;
+ rsel5 = true;
} else
{
ASSERT(false);
return;
}
- if(dcoFrequency == nomFreq)
+ /* Parsing the TLV and getting the maximum erase pulses */
+ SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**)&csInfo);
+
+ if(dcoFrequency == nomFreq || tlvLength == 0)
{
CS_tuneDCOFrequency(0);
return;
}
- /* DCORSEL = 5, in final silicon this will have a different calibration
- value, but currently DCORSEL5 calibration is not populated
- if (rsel5)
+ if ((rsel5) && ( TLV->HWREV > DEVICE_PG1_1))
{
- External Resistor
- if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
+ /* External Resistor*/
+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
- dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL5);
- calVal = TLV->rDCOER_FCAL_RSEL5;
- }
- Internal Resistor
- else
- {
- dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL5);
- calVal = TLV->rDCOIR_FCAL_RSEL5;
- }
- }
- DCORSEL = 4
- else
- {*/
- /* External Resistor */
- if (BITBAND_PERI(CS->rCTL0.r, DCORES_OFS))
- {
- dcoConst = *((float *) &TLV->rDCOER_CONSTK_RSEL04);
- calVal = TLV->rDCOER_FCAL_RSEL04;
+ dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5);
+ calVal = csInfo->rDCOER_FCAL_RSEL5;
}
/* Internal Resistor */
else
{
- dcoConst = *((float *) &TLV->rDCOIR_CONSTK_RSEL04);
- calVal = TLV->rDCOIR_FCAL_RSEL04;
+ dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5);
+ calVal = csInfo->rDCOIR_FCAL_RSEL5;
}
- /*}*/
+ }
+ /* DCORSEL = 4 */
+ else
+ {
+ /* External Resistor */
+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+ {
+ dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04);
+ calVal = csInfo->rDCOER_FCAL_RSEL04;
+ }
+ /* Internal Resistor */
+ else
+ {
+ dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04);
+ calVal = csInfo->rDCOIR_FCAL_RSEL04;
+ }
+ }
- dcoTune = (int16_t) (((dcoSigned - nomFreq)
- * (1.0 + dcoConst * (768.0 - calVal)) * 8.0)
- / (dcoSigned * dcoConst));
+ if ( TLV->HWREV > DEVICE_PG1_1)
+ dcoTune = (int16_t) (((dcoSigned - nomFreq)
+ * (1.0f + dcoConst * (768.0f - calVal)))
+ / (dcoSigned * dcoConst));
+ else
+ dcoTune = (int16_t) (((dcoSigned - nomFreq)
+ * (1.0f + dcoConst * (768.0f - calVal)) * 8.0f)
+ / (dcoSigned * dcoConst));
CS_tuneDCOFrequency(dcoTune);
@@ -711,7 +790,7 @@
uint32_t CS_getBCLK(void)
{
- if (BITBAND_PERI(CS->rCTL1.r, SELB_OFS))
+ if (BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS))
return _CSComputeCLKFrequency(CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
else
return _CSComputeCLKFrequency(CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
@@ -721,8 +800,8 @@
{
uint32_t wSource, wDivider;
- wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
- wDivider = ((CS->rCTL1.r & DIVHS_M) << CS_HSMCLK_DIV_BITPOS);
+ wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS;
+ wDivider = ((CS->CTL1 & CS_CTL1_DIVHS_MASK) << CS_HSMCLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
@@ -731,8 +810,8 @@
{
uint32_t wSource, wDivider;
- wSource = (CS->rCTL1.r & SELA_M) >> CS_ACLK_SRC_BITPOS;
- wDivider = ((CS->rCTL1.r & DIVA_M) << CS_ACLK_DIV_BITPOS);
+ wSource = (CS->CTL1 & CS_CTL1_SELA_MASK) >> CS_ACLK_SRC_BITPOS;
+ wDivider = ((CS->CTL1 & CS_CTL1_DIVA_MASK) << CS_ACLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
@@ -741,8 +820,8 @@
{
uint32_t wDivider, wSource;
- wSource = (CS->rCTL1.r & SELS_M) >> CS_HSMCLK_SRC_BITPOS;
- wDivider = ((CS->rCTL1.r & DIVS_M));
+ wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS;
+ wDivider = ((CS->CTL1 & CS_CTL1_DIVS_MASK));
return _CSComputeCLKFrequency(wSource, wDivider);
@@ -752,8 +831,8 @@
{
uint32_t wSource, wDivider;
- wSource = (CS->rCTL1.r & SELM_M) << CS_MCLK_SRC_BITPOS;
- wDivider = ((CS->rCTL1.r & DIVM_M) << CS_MCLK_DIV_BITPOS);
+ wSource = (CS->CTL1 & CS_CTL1_SELM_MASK) << CS_MCLK_SRC_BITPOS;
+ wDivider = ((CS->CTL1 & CS_CTL1_DIVM_MASK) << CS_MCLK_DIV_BITPOS);
return _CSComputeCLKFrequency(wSource, wDivider);
}
@@ -764,18 +843,18 @@
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
- BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 1;
+ BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 1;
} else
{
- BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 1;
+ BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 1;
}
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_disableFaultCounter(uint_fast8_t counterSelect)
@@ -784,18 +863,18 @@
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
- BITBAND_PERI(CS->rCTL3.r, FCNTHF_EN_OFS) = 0;
+ BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 0;
} else
{
- BITBAND_PERI(CS->rCTL3.r, FCNTLF_EN_OFS) = 0;
+ BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 0;
}
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_resetFaultCounter(uint_fast8_t counterSelect)
@@ -804,18 +883,18 @@
counterSelect == CS_HFXT_FAULT_COUNTER);
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
- BITBAND_PERI(CS->rCTL3.r, RFCNTHF_OFS) = 1;
+ BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTHF_OFS) = 1;
} else
{
- BITBAND_PERI(CS->rCTL3.r, RFCNTLF_OFS) = 1;
+ BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTLF_OFS) = 1;
}
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_startFaultCounter(uint_fast8_t counterSelect, uint_fast8_t countValue)
@@ -829,61 +908,61 @@
countValue == CS_FAULT_COUNTER_32768_CYCLES);
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
if (counterSelect == CS_HFXT_FAULT_COUNTER)
{
- CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTHF_M) | (countValue << 4));
+ CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTHF_MASK) | (countValue << 4));
} else
{
- CS->rCTL3.r = ((CS->rCTL3.r & ~FCNTLF_M) | (countValue));
+ CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTLF_MASK) | (countValue));
}
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_enableInterrupt(uint32_t flags)
{
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- CS->rIE.r |= flags;
+ CS->IE |= flags;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_disableInterrupt(uint32_t flags)
{
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- CS->rIE.r &= ~flags;
+ CS->IE &= ~flags;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
uint32_t CS_getInterruptStatus(void)
{
- return CS->rIFG.r;
+ return CS->IFG;
}
uint32_t CS_getEnabledInterruptStatus(void)
{
- return CS_getInterruptStatus() & CS->rIE.r;
+ return CS_getInterruptStatus() & CS->IE;
}
void CS_clearInterruptFlag(uint32_t flags)
{
/* Unlocking the module */
- CS->rKEY.r = CS_KEY;
+ CS->KEY = CS_KEY;
- CS->rCLRIFG.r |= flags;
+ CS->CLRIFG |= flags;
/* Locking the module */
- BITBAND_PERI(CS->rKEY.r, CSKEY_OFS) = 1;
+ BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
}
void CS_registerInterrupt(void (*intHandler)(void))
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
index b152240..5c56609 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/cs.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -64,21 +64,21 @@
// Control specific variables
//
//*****************************************************************************
-#define CS_CLOCK_DIVIDER_1 DIVS_0
-#define CS_CLOCK_DIVIDER_2 DIVS_1
-#define CS_CLOCK_DIVIDER_4 DIVS_2
-#define CS_CLOCK_DIVIDER_8 DIVS_3
-#define CS_CLOCK_DIVIDER_16 DIVS_4
-#define CS_CLOCK_DIVIDER_32 DIVS_5
-#define CS_CLOCK_DIVIDER_64 DIVS_6
-#define CS_CLOCK_DIVIDER_128 DIVS_7
+#define CS_CLOCK_DIVIDER_1 CS_CTL1_DIVS_0
+#define CS_CLOCK_DIVIDER_2 CS_CTL1_DIVS_1
+#define CS_CLOCK_DIVIDER_4 CS_CTL1_DIVS_2
+#define CS_CLOCK_DIVIDER_8 CS_CTL1_DIVS_3
+#define CS_CLOCK_DIVIDER_16 CS_CTL1_DIVS_4
+#define CS_CLOCK_DIVIDER_32 CS_CTL1_DIVS_5
+#define CS_CLOCK_DIVIDER_64 CS_CTL1_DIVS_6
+#define CS_CLOCK_DIVIDER_128 CS_CTL1_DIVS_7
-#define CS_LFXTCLK_SELECT SELM_0
-#define CS_HFXTCLK_SELECT SELM_5
-#define CS_VLOCLK_SELECT SELM_1
-#define CS_REFOCLK_SELECT SELM_2
-#define CS_DCOCLK_SELECT SELM_3
-#define CS_MODOSC_SELECT SELM_4
+#define CS_LFXTCLK_SELECT CS_CTL1_SELM_0
+#define CS_HFXTCLK_SELECT CS_CTL1_SELM_5
+#define CS_VLOCLK_SELECT CS_CTL1_SELM_1
+#define CS_REFOCLK_SELECT CS_CTL1_SELM_2
+#define CS_DCOCLK_SELECT CS_CTL1_SELM_3
+#define CS_MODOSC_SELECT CS_CTL1_SELM_4
#define CS_KEY 0x695A
@@ -103,33 +103,29 @@
#define CS_MODCLK_FREQUENCY 24000000
/* Interrupts */
-#define CS_LFXT_FAULT LFXTIE
-#define CS_HFXT_FAULT HFXTIE
-#define CS_DCOMIN_FAULT DCOMINIE
-#define CS_DCOMAX_FAULT DCOMAXIE
-#define CS_DCORESISTOR_FAULT DCORIE
-#define CS_STARTCOUNT_LFXT_FAULT FCNTLFIE
-#define CS_STARTCOUNT_HFXT_FAULT FCNTHFIE
-#define CS_PLL_OUTOFLOCK PLLOOLIE
-#define CS_PLL_OUTOFSIGNAL PLLLOSIE
-#define CS_PLL_OUTOFRANGE PLLOORIE
-#define CS_REFCNT_PERIOD_COUNTER CALIE
+#define CS_LFXT_FAULT CS_IE_LFXTIE
+#define CS_HFXT_FAULT CS_IE_HFXTIE
+#define CS_DCO_OPEN_FAULT CS_IE_DCOR_OPNIE
+#define CS_STARTCOUNT_LFXT_FAULT CS_IE_FCNTLFIE
+#define CS_STARTCOUNT_HFXT_FAULT CS_IE_FCNTHFIE
+#define CS_DCO_SHORT_FAULT CS_IFG_DCOR_SHTIFG
-#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
-#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
+//#define CS_HFXT_DRIVE0 CS_CTL2_HFXTDRIVE_0
+//#define CS_HFXT_DRIVE1 CS_CTL2_HFXTDRIVE_1
+#define CS_HFXT_DRIVE CS_CTL2_HFXTDRIVE
#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS
-#define CS_LFXT_DRIVE0 LFXTDRIVE_0
-#define CS_LFXT_DRIVE1 LFXTDRIVE_1
-#define CS_LFXT_DRIVE2 LFXTDRIVE_2
-#define CS_LFXT_DRIVE3 LFXTDRIVE_3
-#define CS_LFXT_BYPASS LFXTBYPASS
+#define CS_LFXT_DRIVE0 CS_CTL2_LFXTDRIVE_0
+#define CS_LFXT_DRIVE1 CS_CTL2_LFXTDRIVE_1
+#define CS_LFXT_DRIVE2 CS_CTL2_LFXTDRIVE_2
+#define CS_LFXT_DRIVE3 CS_CTL2_LFXTDRIVE_3
+#define CS_LFXT_BYPASS CS_CTL2_LFXTBYPASS
-#define CS_ACLK ACLK_EN
-#define CS_MCLK MCLK_EN
-#define CS_SMCLK SMCLK_EN
-#define CS_HSMCLK HSMCLK_EN
-#define CS_BCLK BCLK_READY
+#define CS_ACLK CS_CLKEN_ACLK_EN
+#define CS_MCLK CS_CLKEN_MCLK_EN
+#define CS_SMCLK CS_CLKEN_SMCLK_EN
+#define CS_HSMCLK CS_CLKEN_HSMCLK_EN
+#define CS_BCLK CS_STAT_BCLK_READY
#define CS_LFXTCLK 0x01
@@ -146,20 +142,25 @@
#define CS_40MHZ 40000000
#define CS_48MHZ 48000000
-#define CS_DCO_FREQUENCY_1_5 DCORSEL_0
-#define CS_DCO_FREQUENCY_3 DCORSEL_1
-#define CS_DCO_FREQUENCY_6 DCORSEL_2
-#define CS_DCO_FREQUENCY_12 DCORSEL_3
-#define CS_DCO_FREQUENCY_24 DCORSEL_4
-#define CS_DCO_FREQUENCY_48 DCORSEL_5
+#define CS_DCO_FREQUENCY_1_5 CS_CTL0_DCORSEL_0
+#define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1
+#define CS_DCO_FREQUENCY_6 CS_CTL0_DCORSEL_2
+#define CS_DCO_FREQUENCY_12 CS_CTL0_DCORSEL_3
+#define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4
+#define CS_DCO_FREQUENCY_48 CS_CTL0_DCORSEL_5
#define CS_HFXT_FAULT_COUNTER 0x01
#define CS_LFXT_FAULT_COUNTER 0x02
-#define CS_FAULT_COUNTER_4096_CYCLES FCNTLF_0
-#define CS_FAULT_COUNTER_8192_CYCLES FCNTLF_1
-#define CS_FAULT_COUNTER_16384_CYCLES FCNTLF_2
-#define CS_FAULT_COUNTER_32768_CYCLES FCNTLF_3
+#define CS_FAULT_COUNTER_4096_CYCLES CS_CTL3_FCNTLF_0
+#define CS_FAULT_COUNTER_8192_CYCLES CS_CTL3_FCNTLF_1
+#define CS_FAULT_COUNTER_16384_CYCLES CS_CTL3_FCNTLF_2
+#define CS_FAULT_COUNTER_32768_CYCLES CS_CTL3_FCNTLF_3
+
+#define CS_OVER32MHZ 0x01
+#define CS_UNDER32MHZ 0x02
+
+#define DEVICE_PG1_1 0x42
//******************************************************************************
//
@@ -188,7 +189,11 @@
//!
//! Note that this function is blocking and will wait on the appropriate bit
//! to be set in the CSSTAT READY register to be set before setting the clock
-//! source
+//! source.
+//!
+//! Also note that when HSMCLK and SMCLK share the same clock signal. If you
+//! change the clock signal for HSMCLK, the clock signal for SMCLK will change
+//! also (and vice-versa).
//!
//! HFXTCLK is not available for BCLK or ACLK.
//!
@@ -235,11 +240,10 @@
//! \param bypassMode When this variable is set, the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
-//!
-//! \return NONE
+//! \return true if started correctly, false otherwise
//
//******************************************************************************
-extern void CS_startHFXT(bool bypassMode);
+extern bool CS_startHFXT(bool bypassMode);
//******************************************************************************
//
@@ -257,10 +261,10 @@
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
-//! \return NONE
+//! \return true if started correctly, false otherwise
//
//******************************************************************************
-extern void CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
+extern bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
//******************************************************************************
//
@@ -283,11 +287,10 @@
//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will start
//! in bypass mode and the signal can be generated by a digital square wave.
//!
-//!
-//! \return NONE
+//! \return true if started correctly, false otherwise
//
//******************************************************************************
-extern void CS_startLFXT(uint32_t xtDrive);
+extern bool CS_startLFXT(uint32_t xtDrive);
//******************************************************************************
//
@@ -315,10 +318,10 @@
//! \param timeout is the count value that gets decremented every time the loop
//! that clears oscillator fault flags gets executed.
//!
-//! \return NONE
+//! \return true if started correctly, false otherwise
//
//******************************************************************************
-extern void CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
+extern bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
//******************************************************************************
//
@@ -524,12 +527,17 @@
//! default, the value in the CS module is populated by the calibration
//! data of the suggested external resistor (see device datasheet).
//!
-//! \param uiCalData is the calibration data constant for the external resistor.
+//! \param calData is the calibration data constant for the external resistor.
+//!
+//! \param freqRange is the range of the DCO to set the external calibration
+//! for. Frequencies above 32MHZ have a different calibration value
+//! than frequencies below 32MHZ.
//!
//! \return None
//
//******************************************************************************
-extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData);
+extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData,
+ uint_fast8_t freqRange);
//******************************************************************************
//
@@ -647,13 +655,9 @@
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
-//! - \b CS_DCORESISTOR_FAULT,
+//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
-//! - \b CS_PLL_OUTOFLOCK,
-//! - \b CS_PLL_OUTOFSIGNAL,
-//! - \b CS_PLL_OUTOFRANGE,
-//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! This function enables the indicated clock system interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt;
@@ -678,13 +682,9 @@
//! - \b CS_HFXT_FAULT,
//! - \b CS_DCOMIN_FAULT,
//! - \b CS_DCOMAX_FAULT,
-//! - \b CS_DCORESISTOR_FAULT,
+//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
-//! - \b CS_PLL_OUTOFLOCK,
-//! - \b CS_PLL_OUTOFSIGNAL,
-//! - \b CS_PLL_OUTOFRANGE,
-//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@@ -704,15 +704,10 @@
//! \return The current interrupt status, enumerated as a bit field of
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
-//! - \b CS_DCOMIN_FAULT,
-//! - \b CS_DCOMAX_FAULT,
-//! - \b CS_DCORESISTOR_FAULT,
+//! - \b CS_DCO_OPEN_FAULT,
+//! - \b CS_DCO_SHORT_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
-//! - \b CS_PLL_OUTOFLOCK,
-//! - \b CS_PLL_OUTOFSIGNAL,
-//! - \b CS_PLL_OUTOFRANGE,
-//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@@ -728,15 +723,10 @@
//! \return The current interrupt status, enumerated as a bit field of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
-//! - \b CS_DCOMIN_FAULT,
-//! - \b CS_DCOMAX_FAULT,
-//! - \b CS_DCORESISTOR_FAULT,
+//! - \b CS_DCO_OPEN_FAULT,
+//! - \b CS_DCO_SHORT_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
-//! - \b CS_PLL_OUTOFLOCK,
-//! - \b CS_PLL_OUTOFSIGNAL,
-//! - \b CS_PLL_OUTOFRANGE,
-//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! \note The interrupt sources vary based on the part in use.
//! Please consult the data sheet for the part you are using to determine
@@ -753,15 +743,9 @@
//! be a logical OR of:
//! - \b CS_LFXT_FAULT,
//! - \b CS_HFXT_FAULT,
-//! - \b CS_DCOMIN_FAULT,
-//! - \b CS_DCOMAX_FAULT,
-//! - \b CS_DCORESISTOR_FAULT,
+//! - \b CS_DCO_OPEN_FAULT,
//! - \b CS_STARTCOUNT_LFXT_FAULT,
//! - \b CS_STARTCOUNT_HFXT_FAULT,
-//! - \b CS_PLL_OUTOFLOCK,
-//! - \b CS_PLL_OUTOFSIGNAL,
-//! - \b CS_PLL_OUTOFRANGE,
-//! - \b CS_REFCNT_PERIOD_COUNTER
//!
//! The specified clock system interrupt sources are cleared, so that they no
//! longer assert. This function must be called in the interrupt handler to
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
index 65c566e..fee0e3e 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/debug.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
index deada54..9a531d7 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,7 +45,7 @@
//
// Set the master enable bit in the config register.
//
- DMA->rCFG.r = DMA_CFG_;
+ DMA_Control->CFG = DMA_CFG_MASTEN;
}
void DMA_disableModule(void)
@@ -53,7 +53,7 @@
//
// Clear the master enable bit in the config register.
//
- DMA->rCFG.r = 0;
+ DMA_Control->CFG = 0;
}
uint32_t DMA_getErrorStatus(void)
@@ -61,7 +61,7 @@
//
// Return the DMA error status.
//
- return DMA->rERRCLR.r;
+ return DMA_Control->ERRCLR;
}
void DMA_clearErrorStatus(void)
@@ -69,7 +69,7 @@
//
// Clear the DMA error interrupt.
//
- DMA->rERRCLR.r = 1;
+ DMA_Control->ERRCLR = 1;
}
void DMA_enableChannel(uint32_t channelNum)
@@ -82,7 +82,7 @@
//
// Set the bit for this channel in the enable set register.
//
- DMA->rENASET = 1 << (channelNum & 0x0F);
+ DMA_Control->ENASET = 1 << (channelNum & 0x0F);
}
void DMA_disableChannel(uint32_t channelNum)
@@ -95,7 +95,7 @@
//
// Set the bit for this channel in the enable clear register.
//
- DMA->rENACLR = 1 << (channelNum & 0x0F);
+ DMA_Control->ENACLR = 1 << (channelNum & 0x0F);
}
bool DMA_isChannelEnabled(uint32_t channelNum)
@@ -109,7 +109,7 @@
// AND the specified channel bit with the enable register and return the
// result.
//
- return ((DMA->rENASET & (1 << (channelNum & 0x0F))) ? true : false);
+ return ((DMA_Control->ENASET & (1 << (channelNum & 0x0F))) ? true : false);
}
void DMA_setControlBase(void *controlTable)
@@ -123,7 +123,7 @@
//
// Program the base address into the register.
//
- DMA->rCTLBASE.r = (uint32_t) controlTable;
+ DMA_Control->CTLBASE = (uint32_t) controlTable;
}
void* DMA_getControlBase(void)
@@ -132,7 +132,7 @@
// Read the current value of the control base register and return it to
// the caller.
//
- return ((void *) DMA->rCTLBASE.r);
+ return ((void *) DMA_Control->CTLBASE);
}
void* DMA_getControlAlternateBase(void)
@@ -141,7 +141,7 @@
// Read the current value of the control base register and return it to
// the caller.
//
- return ((void *) DMA->rATLBASE);
+ return ((void *) DMA_Control->ATLBASE);
}
void DMA_requestChannel(uint32_t channelNum)
@@ -154,7 +154,7 @@
//
// Set the bit for this channel in the software DMA request register.
//
- DMA->rSWREQ = 1 << (channelNum & 0x0F);
+ DMA_Control->SWREQ = 1 << (channelNum & 0x0F);
}
void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
@@ -181,7 +181,7 @@
//
if (attr & UDMA_ATTR_USEBURST)
{
- DMA->rUSEBURSTSET = 1 << channelNum;
+ DMA_Control->USEBURSTSET = 1 << channelNum;
}
//
@@ -190,7 +190,7 @@
//
if (attr & UDMA_ATTR_ALTSELECT)
{
- DMA->rALTSET = 1 << channelNum;
+ DMA_Control->ALTSET = 1 << channelNum;
}
//
@@ -198,7 +198,7 @@
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
- DMA->rPRIOSET = 1 << channelNum;
+ DMA_Control->PRIOSET = 1 << channelNum;
}
//
@@ -206,7 +206,7 @@
//
if (attr & UDMA_ATTR_REQMASK)
{
- DMA->rREQMASKSET = 1 << channelNum;
+ DMA_Control->REQMASKSET = 1 << channelNum;
}
}
@@ -234,7 +234,7 @@
//
if (attr & UDMA_ATTR_USEBURST)
{
- DMA->rUSEBURSTCLR = 1 << channelNum;
+ DMA_Control->USEBURSTCLR = 1 << channelNum;
}
//
@@ -243,7 +243,7 @@
//
if (attr & UDMA_ATTR_ALTSELECT)
{
- DMA->rALTCLR = 1 << channelNum;
+ DMA_Control->ALTCLR = 1 << channelNum;
}
//
@@ -251,7 +251,7 @@
//
if (attr & UDMA_ATTR_HIGH_PRIORITY)
{
- DMA->rPRIOCLR = 1 << channelNum;
+ DMA_Control->PRIOCLR = 1 << channelNum;
}
//
@@ -259,7 +259,7 @@
//
if (attr & UDMA_ATTR_REQMASK)
{
- DMA->rREQMASKCLR = 1 << channelNum;
+ DMA_Control->REQMASKCLR = 1 << channelNum;
}
}
@@ -282,7 +282,7 @@
//
// Check to see if useburst bit is set for this channel.
//
- if (DMA->rUSEBURSTSET & (1 << channelNum))
+ if (DMA_Control->USEBURSTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_USEBURST;
}
@@ -290,7 +290,7 @@
//
// Check to see if the alternate control bit is set for this channel.
//
- if (DMA->rALTSET & (1 << channelNum))
+ if (DMA_Control->ALTSET & (1 << channelNum))
{
attr |= UDMA_ATTR_ALTSELECT;
}
@@ -298,7 +298,7 @@
//
// Check to see if the high priority bit is set for this channel.
//
- if (DMA->rPRIOSET & (1 << channelNum))
+ if (DMA_Control->PRIOSET & (1 << channelNum))
{
attr |= UDMA_ATTR_HIGH_PRIORITY;
}
@@ -306,7 +306,7 @@
//
// Check to see if the request mask bit is set for this channel.
//
- if (DMA->rREQMASKSET & (1 << channelNum))
+ if (DMA_Control->REQMASKSET & (1 << channelNum))
{
attr |= UDMA_ATTR_REQMASK;
}
@@ -325,7 +325,7 @@
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
- ASSERT(DMA->rCTLBASE != 0);
+ ASSERT(DMA_Control->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@@ -337,7 +337,7 @@
//
// Get the base address of the control table.
//
- pCtl = (DMA_ControlTable *) DMA->rCTLBASE.r;
+ pCtl = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off the fields to be
@@ -361,7 +361,7 @@
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
- ASSERT(DMA->rCTLBASE != 0);
+ ASSERT(DMA->CTLBASE != 0);
ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER);
ASSERT((transferSize != 0) && (transferSize <= 1024));
@@ -375,7 +375,7 @@
//
// Get the base address of the control table.
//
- controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+ controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off the mode and size
@@ -481,7 +481,7 @@
// Check the parameters
//
ASSERT((channelNum & 0xffff) < 8);
- ASSERT(DMA->rCTLBASE != 0);
+ ASSERT(DMA->CTLBASE != 0);
ASSERT(taskList != 0);
ASSERT(taskCount <= 1024);
ASSERT(taskCount != 0);
@@ -496,7 +496,7 @@
//
// Get the base address of the control table.
//
- controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+ controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get a handy pointer to the task list
@@ -537,7 +537,7 @@
// alt bit here to ensure that it is always cleared before a new SG
// transfer is started.
//
- DMA->rALTCLR = 1 << channelNum;
+ DMA_Control->ALTCLR = 1 << channelNum;
}
uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
@@ -549,7 +549,7 @@
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 16);
- ASSERT(DMA->rCTLBASE != 0);
+ ASSERT(DMA->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@@ -561,7 +561,7 @@
//
// Get the base address of the control table.
//
- controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+ controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off all but the size field
@@ -601,7 +601,7 @@
// Check the arguments.
//
ASSERT((channelStructIndex & 0xffff) < 64);
- ASSERT(DMA->rCTLBASE != 0);
+ ASSERT(DMA->CTLBASE != 0);
//
// In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
@@ -613,7 +613,7 @@
//
// Get the base address of the control table.
//
- controlTable = (DMA_ControlTable *) DMA->rCTLBASE.r;
+ controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
//
// Get the current control word value and mask off all but the mode field.
@@ -649,7 +649,7 @@
case DMA_CH0_EUSCIB1TX3:
case DMA_CH0_TIMERA0CCR0:
case DMA_CH0_AESTRIGGER0:
- DMA->rCH0_SRCCFG.r = (mapping >> 24) & 0x1F;
+ DMA_Channel->CH_SRCCFG[0] = (mapping >> 24) & 0x1F;
break;
case DMA_CH1_RESERVED0:
case DMA_CH1_EUSCIA0RX:
@@ -659,7 +659,7 @@
case DMA_CH1_EUSCIB1RX3:
case DMA_CH1_TIMERA0CCR2:
case DMA_CH1_AESTRIGGER1:
- DMA->rCH1_SRCCFG.r = (mapping >> 24) & 0x1F;
+ DMA_Channel->CH_SRCCFG[1] = (mapping >> 24) & 0x1F;
break;
case DMA_CH2_RESERVED0:
case DMA_CH2_EUSCIA1TX:
@@ -669,7 +669,7 @@
case DMA_CH2_EUSCIB2TX3:
case DMA_CH2_TIMERA1CCR0:
case DMA_CH2_AESTRIGGER2:
- DMA->rCH2_SRCCFG.r = (mapping >> 24) & 0x1F;
+ DMA_Channel->CH_SRCCFG[2] = (mapping >> 24) & 0x1F;
break;
case DMA_CH3_RESERVED0:
case DMA_CH3_EUSCIA1RX:
@@ -679,7 +679,7 @@
case DMA_CH3_EUSCIB2RX3:
case DMA_CH3_TIMERA1CCR2:
case DMA_CH3_RESERVED1:
- DMA->rCH3_SRCCFG.r = (mapping >> 24) & 0x1F;
+ DMA_Channel->CH_SRCCFG[3] = (mapping >> 24) & 0x1F;
break;
case DMA_CH4_RESERVED0:
case DMA_CH4_EUSCIA2TX:
@@ -689,7 +689,7 @@
case DMA_CH4_EUSCIB3TX3:
case DMA_CH4_TIMERA2CCR0:
case DMA_CH4_RESERVED1:
- DMA->rCH4_SRCCFG.r = (mapping >> 24) & 0x1F;
+ DMA_Channel->CH_SRCCFG[4] = (mapping >> 24) & 0x1F;
break;
case DMA_CH5_RESERVED0:
case DMA_CH5_EUSCIA2RX:
@@ -699,7 +699,7 @@
case DMA_CH5_EUSCIB3RX3:
case DMA_CH5_TIMERA2CCR2:
case DMA_CH5_RESERVED1:
- DMA->rCH5_SRCCFG.r = (mapping >> 24) & 0x1F;
+ DMA_Channel->CH_SRCCFG[5] = (mapping >> 24) & 0x1F;
break;
case DMA_CH6_RESERVED0:
case DMA_CH6_EUSCIA3TX:
@@ -709,7 +709,7 @@
case DMA_CH6_EUSCIB0TX3:
case DMA_CH6_TIMERA3CCR0:
case DMA_CH6_EXTERNALPIN:
- DMA->rCH6_SRCCFG.r = (mapping >> 24) & 0x1F;
+ DMA_Channel->CH_SRCCFG[6] = (mapping >> 24) & 0x1F;
break;
case DMA_CH7_RESERVED0:
case DMA_CH7_EUSCIA3RX:
@@ -718,8 +718,8 @@
case DMA_CH7_EUSCIB1RX2:
case DMA_CH7_EUSCIB0RX3:
case DMA_CH7_TIMERA3CCR2:
- case DMA_CH7_ADC12C:
- DMA->rCH7_SRCCFG.r = (mapping >> 24) & 0x1F;
+ case DMA_CH7_ADC14:
+ DMA_Channel->CH_SRCCFG[7] = (mapping >> 24) & 0x1F;
break;
default:
ASSERT(false);
@@ -735,16 +735,16 @@
if (interruptNumber == DMA_INT1)
{
- DMA->rINT1_SRCCFG.r = (DMA->rINT1_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
- | channel;
+ DMA_Channel->INT1_SRCCFG = (DMA_Channel->INT1_SRCCFG
+ & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT2)
{
- DMA->rINT2_SRCCFG.r = (DMA->rINT2_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
- | channel;
+ DMA_Channel->INT2_SRCCFG = (DMA_Channel->INT2_SRCCFG
+ & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
} else if (interruptNumber == DMA_INT3)
{
- DMA->rINT3_SRCCFG.r = (DMA->rINT3_SRCCFG.r & ~DMA_INT1_SRCCFG_INT_SRC_M)
- | channel;
+ DMA_Channel->INT3_SRCCFG = (DMA_Channel->INT3_SRCCFG
+ & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
}
/* Enabling the assigned interrupt */
@@ -753,17 +753,17 @@
void DMA_requestSoftwareTransfer(uint32_t channel)
{
- DMA->rSW_CHTRIG.r |= (1 << channel);
+ DMA_Channel->SW_CHTRIG |= (1 << channel);
}
uint32_t DMA_getInterruptStatus(void)
{
- return DMA->rINT0_SRCFLG.r;
+ return DMA_Channel->INT0_SRCFLG;
}
void DMA_clearInterruptFlag(uint32_t channel)
{
- DMA->rINT0_CLRFLG.r |= (1 << channel);
+ DMA_Channel->INT0_CLRFLG |= (1 << channel);
}
void DMA_enableInterrupt(uint32_t interruptNumber)
@@ -775,13 +775,13 @@
if (interruptNumber == DMA_INT1)
{
- DMA->rINT1_SRCCFG.r |= DMA_INT1_SRCCFG_EN;
+ DMA_Channel->INT1_SRCCFG |= DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
- DMA->rINT2_SRCCFG.r |= DMA_INT2_SRCCFG_EN;
+ DMA_Channel->INT2_SRCCFG |= DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
- DMA->rINT3_SRCCFG.r |= DMA_INT3_SRCCFG_EN;
+ DMA_Channel->INT3_SRCCFG |= DMA_INT3_SRCCFG_EN;
}
}
@@ -795,13 +795,13 @@
if (interruptNumber == DMA_INT1)
{
- DMA->rINT1_SRCCFG.r &= ~DMA_INT1_SRCCFG_EN;
+ DMA_Channel->INT1_SRCCFG &= ~DMA_INT1_SRCCFG_EN;
} else if (interruptNumber == DMA_INT2)
{
- DMA->rINT2_SRCCFG.r &= ~DMA_INT2_SRCCFG_EN;
+ DMA_Channel->INT2_SRCCFG &= ~DMA_INT2_SRCCFG_EN;
} else if (interruptNumber == DMA_INT3)
{
- DMA->rINT3_SRCCFG.r &= ~DMA_INT3_SRCCFG_EN;
+ DMA_Channel->INT3_SRCCFG &= ~DMA_INT3_SRCCFG_EN;
}
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
index 52ed5e2..39080d6 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/dma.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -348,7 +348,7 @@
#define DMA_CH7_EUSCIB1RX2 0x04000007
#define DMA_CH7_EUSCIB0RX3 0x05000007
#define DMA_CH7_TIMERA3CCR2 0x06000007
-#define DMA_CH7_ADC12C 0x07000007
+#define DMA_CH7_ADC14 0x07000007
//
// Different interrupt handlers to pass into DMA_registerInterrupt and
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
index 0aa0daf..770a930 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/driverlib.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
index 6850d89..98e7385 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/eusci.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,7 @@
#include <msp.h>
-#define EUSCI_A_CMSIS(x) ((EUSCI_A0_Type *) x)
-#define EUSCI_B_CMSIS(x) ((EUSCI_B0_Type *) x)
+#define EUSCI_A_CMSIS(x) ((EUSCI_A_Type *) x)
+#define EUSCI_B_CMSIS(x) ((EUSCI_B_Type *) x)
#endif /* EUSCI_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
index f9fca70..d7c0bec 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,10 +45,20 @@
#include <cpu.h>
#include <rom.h>
#include <sysctl.h>
+#include <hw_memmap.h>
-/* Statics */
-static const uint32_t MAX_PROGRAM_TRIES = 5;
-static const uint32_t MAX_ERASE_TRIES = 50;
+static const uint32_t MAX_ERASE_NO_TLV = 50;
+static const uint32_t MAX_PROGRAM_NO_TLV = 5;
+
+static volatile uint32_t* __getBurstProgramRegs[16] =
+{ &FLCTL->PRGBRST_DATA0_0, &FLCTL->PRGBRST_DATA0_1,
+&FLCTL->PRGBRST_DATA0_2, &FLCTL->PRGBRST_DATA0_3,
+&FLCTL->PRGBRST_DATA1_0, &FLCTL->PRGBRST_DATA1_1,
+&FLCTL->PRGBRST_DATA1_2, &FLCTL->PRGBRST_DATA1_3,
+&FLCTL->PRGBRST_DATA2_0, &FLCTL->PRGBRST_DATA2_1,
+&FLCTL->PRGBRST_DATA2_2, &FLCTL->PRGBRST_DATA2_3,
+&FLCTL->PRGBRST_DATA3_0, &FLCTL->PRGBRST_DATA3_1,
+&FLCTL->PRGBRST_DATA3_2, &FLCTL->PRGBRST_DATA3_3 };
static uint32_t getUserFlashSector(uint32_t addr)
{
@@ -129,105 +139,301 @@
}
}
-static bool _FlashCtl_Program8(uint32_t src, uint32_t dest)
+void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
+ uint32_t *bankNum)
+{
+ uint32_t bankLimit;
+
+ bankLimit = SysCtl_getFlashSize() / 2;
+
+ if (addr > bankLimit)
+ {
+ *(sectorNum) = FLASH_BANK1;
+ addr = (addr - bankLimit);
+ } else
+ {
+ *(sectorNum) = FLASH_BANK0;
+ }
+
+ *(bankNum) = (addr - __MAIN_MEMORY_START__) / 4096;
+}
+
+static bool _FlashCtl_Program8(uint32_t src, uint32_t dest, uint32_t mTries)
{
uint32_t ii;
+ uint8_t data;
/* Enabling the correct verification settings */
FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
- for(ii=0;ii<MAX_PROGRAM_TRIES;ii++)
+ data = HWREG8(src);
+
+ for (ii = 0; ii < mTries; ii++)
{
/* Clearing flags */
- FLCTL->rCLRIFG.r |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
+ FLCTL->CLRIFG |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
| FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
- HWREG8(dest) = HWREG8(src);
+ HWREG8(dest) = data;
while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
{
__no_operation();
}
- if ((BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_PRG_ERR_OFS))
- || (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r,
- FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
- && BITBAND_PERI(FLCTL->rIFG.r,
- FLCTL_IFG_AVPRE_OFS))
- || (BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_AVPST_OFS)))
+ /* Pre-Verify */
+ if ((BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
+ && BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPRE_OFS)))
{
- if(BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS))
+ data = __FlashCtl_remaskData8Pre(data, dest);
+
+ if (data != 0xFF)
{
FlashCtl_clearProgramVerification(FLASH_REGPRE);
+ continue;
}
+
}
- else
+
+ /* Post Verify */
+ if ((BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPST_OFS)))
{
- return true;
+ data = __FlashCtl_remaskData8Post(data, dest);
+
+ /* Seeing if we actually need to do another pulse */
+ if (data == 0xFF)
+ return true;
+
+ FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
+ continue;
}
+
+ /* If we got this far, return true */
+ return true;
+
}
return false;
}
-static bool _FlashCtl_Program32(uint32_t src, uint32_t dest)
+static bool _FlashCtl_Program32(uint32_t src, uint32_t dest, uint32_t mTries)
{
uint32_t ii;
+ uint32_t data;
/* Enabling the correct verification settings */
FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
- for(ii=0;ii<MAX_PROGRAM_TRIES;ii++)
+ data = HWREG32(src);
+
+ for (ii = 0; ii < mTries; ii++)
{
/* Clearing flags */
- FLCTL->rCLRIFG.r |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
+ FLCTL->CLRIFG |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED
| FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE);
- HWREG32(dest) = HWREG32(src);
+ HWREG32(dest) = data;
while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE))
{
__no_operation();
}
- if ((BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_PRG_ERR_OFS))
- || (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r,
- FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
- && BITBAND_PERI(FLCTL->rIFG.r,
- FLCTL_IFG_AVPRE_OFS))
- || (BITBAND_PERI(FLCTL->rIFG.r, FLCTL_IFG_AVPST_OFS)))
+ /* Pre-Verify */
+ if ((BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS)
+ && BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPRE_OFS)))
{
- if(BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS))
+ data = __FlashCtl_remaskData32Pre(data, dest);
+
+ if (data != 0xFFFFFFFF)
{
+
FlashCtl_clearProgramVerification(FLASH_REGPRE);
+ continue;
}
+
}
- else
+
+ /* Post Verify */
+ if ((BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPST_OFS)))
{
- return true;
+ data = __FlashCtl_remaskData32Post(data, dest);
+
+ /* Seeing if we actually need to do another pulse */
+ if (data == 0xFFFFFFFF)
+ return true;
+
+ FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
+ continue;
}
+
+ /* If we got this far, return true */
+ return true;
+
}
return false;
}
+static bool _FlashCtl_ProgramBurst(uint32_t src, uint32_t dest, uint32_t length,
+ uint32_t mTries)
+{
+ uint32_t bCalc, otpOffset, ii, jj;
+ bool res;
+
+ /* Setting verification */
+ FlashCtl_clearProgramVerification(FLASH_REGPRE | FLASH_REGPOST);
+ FlashCtl_setProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE);
+
+ /* Assume Failure */
+ res = false;
+
+ /* Waiting for idle status */
+ while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
+ != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
+ {
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
+ }
+
+ /* Setting/clearing INFO flash flags as appropriate */
+ if (dest > __MAIN_MEMORY_END__)
+ {
+ FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
+ & ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_1;
+ otpOffset = __INFO_FLASH_TECH_START__;
+ } else
+ {
+ FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
+ & ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_0;
+ otpOffset = __MAIN_MEMORY_START__;
+ }
+
+ bCalc = 0;
+ FLCTL->PRGBRST_STARTADDR = (dest - otpOffset);
+
+ /* Initially populating the burst registers */
+ while (bCalc < 16 && length != 0)
+ {
+ HWREG32(__getBurstProgramRegs[bCalc]) = HWREG32(src);
+ bCalc++;
+ length -= 4;
+ src += 4;
+ }
+
+ for (ii = 0; ii < mTries; ii++)
+ {
+ /* Clearing Flags */
+ FLCTL->CLRIFG |= (FLASH_BRSTPRGM_COMPLETE | FLASH_POSTVERIFY_FAILED
+ | FLASH_PREVERIFY_FAILED);
+
+ /* Waiting for idle status */
+ while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
+ != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
+ {
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
+ }
+
+ /* Start the burst program */
+ FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT
+ & ~(FLCTL_PRGBRST_CTLSTAT_LEN_MASK))
+ | ((bCalc / 4) << FLASH_BURST_PRG_BIT)
+ | FLCTL_PRGBRST_CTLSTAT_START;
+
+ /* Waiting for the burst to complete */
+ while ((FLCTL->PRGBRST_CTLSTAT &
+ FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
+ != FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE)
+ {
+ __no_operation();
+ }
+
+ /* Checking for errors and clearing/masking */
+
+ /* Address Error */
+ if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS))
+ {
+ goto BurstCleanUp;
+ }
+
+ /* Pre-Verify Error */
+ if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) && BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS))
+ {
+ __FlashCtl_remaskBurstDataPre(dest, bCalc * 4);
+
+ for (jj = 0; jj < bCalc; jj++)
+ {
+ if (HWREG32(__getBurstProgramRegs[jj])
+ != 0xFFFFFFFF)
+ {
+ FlashCtl_clearProgramVerification(FLASH_BURSTPRE);
+ break;
+ }
+ }
+
+ if (jj != bCalc)
+ continue;
+ }
+
+ /* Post-Verify Error */
+ if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS))
+ {
+ __FlashCtl_remaskBurstDataPost(dest, bCalc * 4);
+
+ for (jj = 0; jj < bCalc; jj++)
+ {
+ if ((HWREG32(__getBurstProgramRegs[jj]))
+ != 0xFFFFFFFF)
+ {
+ FlashCtl_setProgramVerification(
+ FLASH_BURSTPOST | FLASH_BURSTPRE);
+ break;
+ }
+ }
+
+ if (jj != bCalc)
+ continue;
+
+ }
+
+ /* If we got this far, the program happened */
+ res = true;
+ goto BurstCleanUp;
+ }
+
+ BurstCleanUp:
+ /* Waiting for idle status */
+ while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
+ != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
+ {
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
+ }
+ return res;
+}
+
void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank,
uint_fast8_t accessMethod)
{
if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
- BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFD_OFS) = 1;
+ BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFD_OFS) = 1;
else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
- BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFD_OFS) = 1;
+ BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFD_OFS) = 1;
else if (memoryBank == FLASH_BANK0
&& accessMethod == FLASH_INSTRUCTION_FETCH)
- BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFI_OFS) = 1;
+ BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFI_OFS) = 1;
else if (memoryBank == FLASH_BANK1
&& accessMethod == FLASH_INSTRUCTION_FETCH)
- BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFI_OFS) = 1;
+ BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFI_OFS) = 1;
else
ASSERT(false);
}
@@ -236,15 +442,15 @@
uint_fast8_t accessMethod)
{
if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ)
- BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFD_OFS) = 0;
+ BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFD_OFS) = 0;
else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ)
- BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFD_OFS) = 0;
+ BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFD_OFS) = 0;
else if (memoryBank == FLASH_BANK0
&& accessMethod == FLASH_INSTRUCTION_FETCH)
- BITBAND_PERI(FLCTL->rBANK0_RDCTL.r, FLCTL_BANK0_RDCTL_BUFI_OFS) = 0;
+ BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFI_OFS) = 0;
else if (memoryBank == FLASH_BANK1
&& accessMethod == FLASH_INSTRUCTION_FETCH)
- BITBAND_PERI(FLCTL->rBANK1_RDCTL.r, FLCTL_BANK1_RDCTL_BUFI_OFS) = 0;
+ BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFI_OFS) = 0;
else
ASSERT(false);
}
@@ -254,18 +460,18 @@
switch (memorySpace)
{
case FLASH_MAIN_MEMORY_SPACE_BANK0:
- FLCTL->rBANK0_MAIN_WEPROT.r &= ~sectorMask;
+ FLCTL->BANK0_MAIN_WEPROT &= ~sectorMask;
break;
case FLASH_MAIN_MEMORY_SPACE_BANK1:
- FLCTL->rBANK1_MAIN_WEPROT.r &= ~sectorMask;
+ FLCTL->BANK1_MAIN_WEPROT &= ~sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK0:
ASSERT(sectorMask <= 0x04);
- FLCTL->rBANK0_INFO_WEPROT.r &= ~sectorMask;
+ FLCTL->BANK0_INFO_WEPROT &= ~sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK1:
ASSERT(sectorMask <= 0x04);
- FLCTL->rBANK1_INFO_WEPROT.r &= ~sectorMask;
+ FLCTL->BANK1_INFO_WEPROT &= ~sectorMask;
break;
default:
@@ -281,18 +487,18 @@
switch (memorySpace)
{
case FLASH_MAIN_MEMORY_SPACE_BANK0:
- FLCTL->rBANK0_MAIN_WEPROT.r |= sectorMask;
+ FLCTL->BANK0_MAIN_WEPROT |= sectorMask;
break;
case FLASH_MAIN_MEMORY_SPACE_BANK1:
- FLCTL->rBANK1_MAIN_WEPROT.r |= sectorMask;
+ FLCTL->BANK1_MAIN_WEPROT |= sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK0:
ASSERT(sectorMask <= 0x04);
- FLCTL->rBANK0_INFO_WEPROT.r |= sectorMask;
+ FLCTL->BANK0_INFO_WEPROT |= sectorMask;
break;
case FLASH_INFO_MEMORY_SPACE_BANK1:
ASSERT(sectorMask <= 0x04);
- FLCTL->rBANK1_INFO_WEPROT.r |= sectorMask;
+ FLCTL->BANK1_INFO_WEPROT |= sectorMask;
break;
default:
@@ -308,15 +514,15 @@
switch (memorySpace)
{
case FLASH_MAIN_MEMORY_SPACE_BANK0:
- return FLCTL->rBANK0_MAIN_WEPROT.r & sector;
+ return FLCTL->BANK0_MAIN_WEPROT & sector;
case FLASH_MAIN_MEMORY_SPACE_BANK1:
- return FLCTL->rBANK1_MAIN_WEPROT.r & sector;
+ return FLCTL->BANK1_MAIN_WEPROT & sector;
case FLASH_INFO_MEMORY_SPACE_BANK0:
ASSERT(sector <= 0x04);
- return FLCTL->rBANK0_INFO_WEPROT.r & sector;
+ return FLCTL->BANK0_INFO_WEPROT & sector;
case FLASH_INFO_MEMORY_SPACE_BANK1:
ASSERT(sector <= 0x04);
- return FLCTL->rBANK1_INFO_WEPROT.r & sector;
+ return FLCTL->BANK1_INFO_WEPROT & sector;
default:
return false;
}
@@ -326,19 +532,82 @@
uint_fast8_t pattern)
{
uint32_t memoryPattern, addr, otpOffset;
+ uint32_t b0WaitState, b1WaitState, intStatus;
+ uint32_t bankOneStart, startBank, endBank;
+ uint_fast8_t b0readMode, b1readMode;
uint_fast8_t memoryType;
+ bool res;
ASSERT(pattern == FLASH_0_PATTERN || pattern == FLASH_1_PATTERN);
+ /* Saving interrupt context and disabling interrupts for program
+ * operation
+ */
+ intStatus = CPU_primask();
+ Interrupt_disableMaster();
+
+ /* Casting and determining the memory that we need to use */
addr = (uint32_t) verifyAddr;
- memoryPattern = (pattern == FLASH_1_PATTERN) ? 0xFFFFFFFF : 0;
- memoryType = (addr > __MAIN_MEMORY_END__) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
+ memoryType =
+ (addr > __MAIN_MEMORY_END__) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
+
+ /* Assuming Failure */
+ res = false;
+
+ /* Finding out which bank we are in */
+ if(addr > SysCtl_getFlashSize())
+ {
+ bankOneStart = __INFO_FLASH_TECH_MIDDLE__;
+ }
+ else
+ {
+ bankOneStart = SysCtl_getFlashSize() / 2;
+ }
+ startBank = addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
+ endBank = (addr + length) < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
+
+ /* Saving context and changing read modes */
+ b0WaitState = FlashCtl_getWaitState(startBank);
+ b0readMode = FlashCtl_getReadMode(startBank);
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setWaitState(startBank, (2 * b0WaitState) + 1);
+
+ if(startBank != endBank)
+ {
+ b1WaitState = FlashCtl_getWaitState(endBank);
+ b1readMode = FlashCtl_getReadMode(endBank);
+ FlashCtl_setWaitState(endBank, (2 * b1WaitState) + 1);
+ }
+
+ /* Changing to the relevant VERIFY mode */
+ if (pattern == FLASH_1_PATTERN)
+ {
+ FlashCtl_setReadMode(startBank, FLASH_ERASE_VERIFY_READ_MODE);
+
+ if(startBank != endBank)
+ {
+ FlashCtl_setReadMode(endBank, FLASH_ERASE_VERIFY_READ_MODE);
+ }
+
+ memoryPattern = 0xFFFFFFFF;
+ } else
+ {
+ FlashCtl_setReadMode(startBank, FLASH_PROGRAM_VERIFY_READ_MODE);
+
+ if(startBank != endBank)
+ {
+ FlashCtl_setReadMode(endBank, FLASH_PROGRAM_VERIFY_READ_MODE);
+ }
+
+ memoryPattern = 0;
+ }
/* Taking care of byte accesses */
while ((addr & 0x03) && (length > 0))
{
if (HWREG8(addr++) != ((uint8_t) memoryPattern))
- return false;
+ goto FlashVerifyCleanup;
length--;
}
@@ -346,7 +615,7 @@
while (((addr & 0x0F)) && (length > 3))
{
if (HWREG32(addr) != memoryPattern)
- return false;
+ goto FlashVerifyCleanup;
addr = addr + 4;
length = length - 4;
@@ -355,66 +624,57 @@
/* Burst Verify */
if (length > 63)
{
-
/* Setting/clearing INFO flash flags as appropriate */
if (addr > __MAIN_MEMORY_END__)
{
- FLCTL->rRDBRST_CTLSTAT.r = (FLCTL->rRDBRST_CTLSTAT.r
- & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M)
+ FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT
+ & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK)
| FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1;
- otpOffset = 0x00200000;
+ otpOffset = __INFO_FLASH_TECH_START__;
} else
{
- FLCTL->rRDBRST_CTLSTAT.r = (FLCTL->rRDBRST_CTLSTAT.r
- & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M)
+ FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT
+ & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK)
| FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0;
otpOffset = __MAIN_MEMORY_START__;
}
/* Clearing any lingering fault flags and preparing burst verify*/
- BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
- 1;
- FLCTL->rRDBRST_FAILCNT.r = 0;
- FLCTL->rRDBRST_STARTADDR.r = addr - otpOffset;
- FLCTL->rRDBRST_LEN.r = (length & 0xFFFFFFF0);
- addr += FLCTL->rRDBRST_LEN.r;
+ BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
+ FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) = 1;
+ FLCTL->RDBRST_FAILCNT = 0;
+ FLCTL->RDBRST_STARTADDR = addr - otpOffset;
+ FLCTL->RDBRST_LEN = (length & 0xFFFFFFF0);
+ addr += FLCTL->RDBRST_LEN;
length = length & 0xF;
/* Starting Burst Verify */
- FLCTL->rRDBRST_CTLSTAT.r = (FLCTL_RDBRST_CTLSTAT_STOP_FAIL | pattern
+ FLCTL->RDBRST_CTLSTAT = (FLCTL_RDBRST_CTLSTAT_STOP_FAIL | pattern
| memoryType | FLCTL_RDBRST_CTLSTAT_START);
/* While the burst read hasn't finished */
- while ((FLCTL->rRDBRST_CTLSTAT.r & FLCTL_RDBRST_CTLSTAT_BRST_STAT_M)
+ while ((FLCTL->RDBRST_CTLSTAT & FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK)
!= FLCTL_RDBRST_CTLSTAT_BRST_STAT_3)
{
__no_operation();
}
/* Checking for a verification/access error/failure */
- if (BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r,
+ if (BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS)
- || BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r,
+ || BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS)
- || FLCTL->rRDBRST_FAILCNT.r)
+ || FLCTL->RDBRST_FAILCNT)
{
- /* Clearing the Read Burst flag and returning */
- BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
- 1;
- return false;
+ goto FlashVerifyCleanup;
}
-
- /* Clearing the Read Burst flag */
- BITBAND_PERI(FLCTL->rRDBRST_CTLSTAT.r, FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) =
- 1;
-
}
/* Remaining Words */
while (length > 3)
{
if (HWREG32(addr) != memoryPattern)
- return false;
+ goto FlashVerifyCleanup;
addr = addr + 4;
length = length - 4;
@@ -424,30 +684,53 @@
while (length > 0)
{
if (HWREG8(addr++) != ((uint8_t) memoryPattern))
- return false;
+ goto FlashVerifyCleanup;
length--;
}
- return true;
+ /* If we got this far, that means it no failure happened */
+ res = true;
+
+ FlashVerifyCleanup:
+
+ /* Clearing the Read Burst flag and returning */
+ BITBAND_PERI(FLCTL->RDBRST_CTLSTAT,
+ FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) = 1;
+
+ FlashCtl_setReadMode(startBank, b0readMode);
+ FlashCtl_setWaitState(startBank, b0WaitState);
+
+ if(startBank != endBank)
+ {
+ FlashCtl_setReadMode(endBank, b1readMode);
+ FlashCtl_setWaitState(endBank, b1WaitState);
+ }
+
+ if(intStatus == 0)
+ Interrupt_enableMaster();
+
+ return res;
}
bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode)
{
- if (FLCTL->rPOWER_STAT.r & FLCTL_POWER_STAT_RD_2T)
+ if (FLCTL->POWER_STAT & FLCTL_POWER_STAT_RD_2T)
return false;
if (flashBank == FLASH_BANK0)
{
- FLCTL->rBANK0_RDCTL.r = (FLCTL->rBANK0_RDCTL.r
- & ~FLCTL_BANK0_RDCTL_RD_MODE_M) | readMode;
- while (FLCTL->rBANK0_RDCTL.b.bRD_MODE != readMode)
+ FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL
+ & ~FLCTL_BANK0_RDCTL_RD_MODE_MASK) | readMode;
+ while ((FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_MASK)
+ != readMode)
;
} else if (flashBank == FLASH_BANK1)
{
- FLCTL->rBANK1_RDCTL.r = (FLCTL->rBANK1_RDCTL.r
- & ~FLCTL_BANK1_RDCTL_RD_MODE_M) | readMode;
- while (FLCTL->rBANK1_RDCTL.b.bRD_MODE != readMode)
+ FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL
+ & ~FLCTL_BANK1_RDCTL_RD_MODE_MASK) | readMode;
+ while ((FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_MASK)
+ != readMode)
;
} else
{
@@ -462,10 +745,10 @@
{
if (flashBank == FLASH_BANK0)
{
- return FLCTL->rBANK0_RDCTL.b.bRD_MODE;
+ return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_MASK);
} else if (flashBank == FLASH_BANK1)
{
- return FLCTL->rBANK1_RDCTL.b.bRD_MODE;
+ return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_MASK);
} else
{
ASSERT(false);
@@ -473,113 +756,281 @@
}
}
+void FlashCtl_initiateMassErase(void)
+{
+ /* Clearing old mass erase flags */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
+
+ /* Performing the mass erase */
+ FLCTL->ERASE_CTLSTAT |= (FLCTL_ERASE_CTLSTAT_MODE
+ | FLCTL_ERASE_CTLSTAT_START);
+}
+
bool FlashCtl_performMassErase(void)
{
- uint32_t userFlash, ii, jj, sector;
+ uint32_t userFlash, ii, sector, intStatus;
+ bool res;
- /* Trying a mass erase in ROM first. If it fails (should be rare), going
- * through and erasing each sector one-by-one
+ /* Saving interrupt context and disabling interrupts for program
+ * operation
*/
- if (!FlashInternal_performMassErase(true))
+ intStatus = CPU_primask();
+ Interrupt_disableMaster();
+
+ /* Assume Failure */
+ res = false;
+
+ /* Clearing old mass erase flags */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
+
+ /* Performing the mass erase */
+ FLCTL->ERASE_CTLSTAT |= (FLCTL_ERASE_CTLSTAT_MODE
+ | FLCTL_ERASE_CTLSTAT_START);
+
+ while ((FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
+ == FLCTL_ERASE_CTLSTAT_STATUS_1
+ || (FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
+ == FLCTL_ERASE_CTLSTAT_STATUS_2)
{
- userFlash = SysCtl_getFlashSize() / 2;
+ __no_operation();
+ }
- for (ii = __MAIN_MEMORY_START__; ii < userFlash; ii += 4096)
+ /* Return false if an address error */
+ if (BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS))
+ goto MassEraseCleanup;
+
+ /* Changing to erase verify */
+ userFlash = SysCtl_getFlashSize() / 2;
+
+ for (ii = __MAIN_MEMORY_START__; ii < userFlash; ii += 4096)
+ {
+ sector = getUserFlashSector(ii);
+
+ if (!((FLCTL->BANK0_MAIN_WEPROT) & sector))
{
- sector = getUserFlashSector(ii);
-
- if (!((FLCTL->rBANK0_MAIN_WEPROT.r) & sector))
+ if (!FlashCtl_verifyMemory((void*) ii, 4096, FLASH_1_PATTERN))
{
- for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
- {
- if (FlashInternal_eraseSector(ii, true))
- {
- break;
- }
- }
+ if (!FlashCtl_eraseSector(ii))
+ goto MassEraseCleanup;
+ }
+ }
- if (jj == MAX_ERASE_TRIES)
- return false;
+ if (!(FLCTL->BANK1_MAIN_WEPROT & sector))
+ {
+ if (!FlashCtl_verifyMemory((void*) (ii + userFlash), 4096,
+ FLASH_1_PATTERN))
+ {
+ if (!FlashCtl_eraseSector(ii + userFlash))
+ goto MassEraseCleanup;
+ }
+ }
+
+ if (sector < FLCTL_BANK0_MAIN_WEPROT_PROT2)
+ {
+ if (!(FLCTL->BANK0_INFO_WEPROT & sector))
+ {
+ if (!FlashCtl_verifyMemory(
+ (void*) (ii + __INFO_FLASH_TECH_START__), 4096,
+ FLASH_1_PATTERN))
+ {
+ if (!FlashCtl_eraseSector(ii + __INFO_FLASH_TECH_START__))
+ goto MassEraseCleanup;
+ }
}
- if (!(FLCTL->rBANK1_MAIN_WEPROT.r & sector))
+ if (!(FLCTL->BANK1_INFO_WEPROT & sector))
{
- for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
+ if (!FlashCtl_verifyMemory((void*) (ii + (0x202000)), 4096,
+ FLASH_1_PATTERN))
{
- if (FlashInternal_eraseSector(ii + userFlash, true))
- {
- break;
- }
+ if (!FlashCtl_eraseSector(ii + (0x202000)))
+ goto MassEraseCleanup;
}
-
- if (jj == MAX_ERASE_TRIES)
- return false;
}
- if (sector < FLCTL_BANK0_MAIN_WEPROT_PROT2)
- {
- if (!(FLCTL->rBANK0_INFO_WEPROT.r & sector))
- {
- for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
- {
- if (FlashInternal_eraseSector(ii + __BSL_MEMORY_START__,
- true))
- {
- break;
- }
- }
-
- if (jj == MAX_ERASE_TRIES)
- return false;
- }
-
- if (!(FLCTL->rBANK1_INFO_WEPROT.r & sector))
- {
-
- for (jj = 1; jj < MAX_ERASE_TRIES; jj++)
- {
-
- if (FlashInternal_eraseSector(
- ii + __BSL_MEMORY_START__ + 0x2000, true))
- {
- break;
- }
- }
-
- if (jj == MAX_ERASE_TRIES)
- return false;
- }
-
- }
}
}
- return true;
+ /* If we got this far, the mass erase happened */
+ res = true;
+
+ MassEraseCleanup:
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
+
+ if(intStatus == 0)
+ Interrupt_enableMaster();
+
+ return res;
}
bool FlashCtl_eraseSector(uint32_t addr)
{
- uint32_t ii;
+ uint_fast8_t memoryType, ii;
+ uint32_t otpOffset = 0;
+ uint32_t intStatus;
+ uint_fast8_t mTries, tlvLength;
+ SysCtl_FlashTLV_Info *flInfo;
+ bool res;
- for(ii=0;ii<MAX_ERASE_TRIES;ii++)
+ /* Saving interrupt context and disabling interrupts for program
+ * operation
+ */
+ intStatus = CPU_primask();
+ Interrupt_disableMaster();
+
+ /* Assuming Failure */
+ res = false;
+
+ memoryType =
+ addr > __MAIN_MEMORY_END__ ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
+
+ /* Parsing the TLV and getting the maximum erase pulses */
+ SysCtl_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo);
+
+ if (tlvLength == 0 || flInfo->maxErasePulses == 0)
{
- if(FlashInternal_eraseSector(addr, true))
- {
- return true;
- }
+ mTries = MAX_ERASE_NO_TLV;
+ } else
+ {
+ mTries = flInfo->maxErasePulses;
}
- return false;
+ /* We can only erase on 4KB boundaries */
+ while (addr & 0xFFF)
+ {
+ addr--;
+ }
+
+ /* Clearing the status */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
+
+ if (memoryType == FLASH_INFO_SPACE)
+ {
+ otpOffset = __INFO_FLASH_TECH_START__;
+ FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
+ & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_1;
+
+ } else
+ {
+ otpOffset = __MAIN_MEMORY_START__;
+ FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
+ & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0;
+ }
+
+ /* Clearing old flags and setting up the erase */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_MODE_OFS) = 0;
+ FLCTL->ERASE_SECTADDR = addr - otpOffset;
+
+ for (ii = 0; ii < mTries; ii++)
+ {
+ /* Clearing the status */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) =
+ 1;
+
+ /* Starting the erase */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT,
+ FLCTL_ERASE_CTLSTAT_START_OFS) = 1;
+
+ while ((FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
+ == FLCTL_ERASE_CTLSTAT_STATUS_1
+ || (FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK)
+ == FLCTL_ERASE_CTLSTAT_STATUS_2)
+ {
+ __no_operation();
+ }
+
+ /* Return false if an address error */
+ if (BITBAND_PERI(FLCTL->ERASE_CTLSTAT,
+ FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS))
+ {
+ goto SectorEraseCleanup;
+ }
+ /* Erase verifying */
+ if (FlashCtl_verifyMemory((void*) addr, 4096, FLASH_1_PATTERN))
+ {
+ res = true;
+ goto SectorEraseCleanup;
+ }
+
+ }
+
+SectorEraseCleanup:
+
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
+
+ if(intStatus == 0)
+ Interrupt_enableMaster();
+
+ return res;
+}
+
+void FlashCtl_initiateSectorErase(uint32_t addr)
+{
+ uint_fast8_t memoryType;
+ uint32_t otpOffset = 0;
+
+ memoryType =
+ addr > __MAIN_MEMORY_END__ ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE;
+
+ /* We can only erase on 4KB boundaries */
+ while (addr & 0xFFF)
+ {
+ addr--;
+ }
+
+ /* Clearing the status */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1;
+
+ if (memoryType == FLASH_INFO_SPACE)
+ {
+ otpOffset = __INFO_FLASH_TECH_START__;
+ FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
+ & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_1;
+
+ } else
+ {
+ otpOffset = __MAIN_MEMORY_START__;
+ FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT
+ & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0;
+ }
+
+ /* Clearing old flags and setting up the erase */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_MODE_OFS) = 0;
+ FLCTL->ERASE_SECTADDR = addr - otpOffset;
+
+ /* Starting the erase */
+ BITBAND_PERI(FLCTL->ERASE_CTLSTAT,
+ FLCTL_ERASE_CTLSTAT_START_OFS) = 1;
+
}
bool FlashCtl_programMemory(void* src, void* dest, uint32_t length)
{
- uint32_t destAddr, srcAddr;
+ uint32_t destAddr, srcAddr, burstLength, intStatus;
bool res;
+ uint_fast8_t mTries, tlvLength;
+ SysCtl_FlashTLV_Info *flInfo;
+
+ /* Saving interrupt context and disabling interrupts for program
+ * operation
+ */
+ intStatus = CPU_primask();
+ Interrupt_disableMaster();
+
+ /* Parsing the TLV and getting the maximum erase pulses */
+ SysCtl_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo);
+
+ if (tlvLength == 0 || flInfo->maxProgramPulses == 0)
+ {
+ mTries = MAX_PROGRAM_NO_TLV;
+ } else
+ {
+ mTries = flInfo->maxProgramPulses;
+ }
/* Casting to integers */
- srcAddr = (uint32_t)src;
- destAddr = (uint32_t)dest;
+ srcAddr = (uint32_t) src;
+ destAddr = (uint32_t) dest;
/* Enabling word programming */
FlashCtl_enableWordProgramming(FLASH_IMMEDIATE_WRITE_MODE);
@@ -590,11 +1041,10 @@
/* Taking care of byte accesses */
while ((destAddr & 0x03) && length > 0)
{
- if(!_FlashCtl_Program8(srcAddr,destAddr))
+ if (!_FlashCtl_Program8(srcAddr, destAddr, mTries))
{
goto FlashProgramCleanUp;
- }
- else
+ } else
{
srcAddr++;
destAddr++;
@@ -605,11 +1055,10 @@
/* Taking care of word accesses */
while ((destAddr & 0x0F) && (length > 3))
{
- if (!_FlashCtl_Program32(srcAddr, destAddr))
+ if (!_FlashCtl_Program32(srcAddr, destAddr, mTries))
{
goto FlashProgramCleanUp;
- }
- else
+ } else
{
srcAddr += 4;
destAddr += 4;
@@ -617,14 +1066,43 @@
}
}
+ /* Taking care of burst programs */
+ while (length > 16)
+ {
+ burstLength = length > 63 ? 64 : length & 0xFFFFFFF0;
+
+ if (!_FlashCtl_ProgramBurst(srcAddr, destAddr, burstLength, mTries))
+ {
+ goto FlashProgramCleanUp;
+ } else
+ {
+ srcAddr += burstLength;
+ destAddr += burstLength;
+ length -= burstLength;
+ }
+ }
+
+ /* Remaining word accesses */
+ while (length > 3)
+ {
+ if (!_FlashCtl_Program32(srcAddr, destAddr, mTries))
+ {
+ goto FlashProgramCleanUp;
+ } else
+ {
+ srcAddr+=4;
+ destAddr+=4;
+ length-=4;
+ }
+ }
+
/* Remaining byte accesses */
while (length > 0)
{
- if(!_FlashCtl_Program8(srcAddr,destAddr))
+ if (!_FlashCtl_Program8(srcAddr, destAddr, mTries))
{
goto FlashProgramCleanUp;
- }
- else
+ } else
{
srcAddr++;
destAddr++;
@@ -635,44 +1113,47 @@
/* If we got this far that means that we succeeded */
res = true;
-FlashProgramCleanUp:
+ FlashProgramCleanUp:
+
+ if(intStatus == 0)
+ Interrupt_enableMaster();
+
FlashCtl_disableWordProgramming();
return res;
}
-
void FlashCtl_setProgramVerification(uint32_t verificationSetting)
{
if ((verificationSetting & FLASH_BURSTPOST))
- BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) =
- 1;
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 1;
if ((verificationSetting & FLASH_BURSTPRE))
- BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) =
- 1;
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 1;
if ((verificationSetting & FLASH_REGPRE))
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 1;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 1;
if ((verificationSetting & FLASH_REGPOST))
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 1;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 1;
}
void FlashCtl_clearProgramVerification(uint32_t verificationSetting)
{
if ((verificationSetting & FLASH_BURSTPOST))
- BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) =
- 0;
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 0;
if ((verificationSetting & FLASH_BURSTPRE))
- BITBAND_PERI(FLCTL->rPRGBRST_CTLSTAT.r, FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) =
- 0;
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 0;
if ((verificationSetting & FLASH_REGPRE))
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 0;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 0;
if ((verificationSetting & FLASH_REGPOST))
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 0;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 0;
}
@@ -680,27 +1161,27 @@
{
if (mode == FLASH_IMMEDIATE_WRITE_MODE)
{
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS) = 0;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS) = 0;
} else if (mode == FLASH_COLLATED_WRITE_MODE)
{
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS) = 1;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS) = 1;
}
}
void FlashCtl_disableWordProgramming(void)
{
- BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 0;
+ BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 0;
}
uint32_t FlashCtl_isWordProgrammingEnabled(void)
{
- if (!BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_ENABLE_OFS))
+ if (!BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS))
{
return 0;
- } else if (BITBAND_PERI(FLCTL->rPRG_CTLSTAT.r, FLCTL_PRG_CTLSTAT_MODE_OFS))
+ } else if (BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS))
return FLASH_COLLATED_WRITE_MODE;
else
return FLASH_IMMEDIATE_WRITE_MODE;
@@ -710,14 +1191,12 @@
{
if (flashBank == FLASH_BANK0)
{
- FLCTL->rBANK0_RDCTL.r =
- (FLCTL->rBANK0_RDCTL.r & ~FLCTL_BANK0_RDCTL_WAIT_M)
- | (waitState << 12);
+ FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL
+ & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | (waitState << FLCTL_BANK0_RDCTL_WAIT_OFS);
} else if (flashBank == FLASH_BANK1)
{
- FLCTL->rBANK1_RDCTL.r =
- (FLCTL->rBANK1_RDCTL.r & ~FLCTL_BANK1_RDCTL_WAIT_M)
- | (waitState << 12);
+ FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL
+ & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | (waitState << FLCTL_BANK1_RDCTL_WAIT_OFS);
} else
{
ASSERT(false);
@@ -728,10 +1207,10 @@
{
if (flashBank == FLASH_BANK0)
{
- return FLCTL->rBANK0_RDCTL.b.bWAIT;
+ return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_WAIT_MASK) >> FLCTL_BANK0_RDCTL_WAIT_OFS;
} else if (flashBank == FLASH_BANK1)
{
- return FLCTL->rBANK1_RDCTL.b.bWAIT;
+ return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_WAIT_MASK) >> FLCTL_BANK1_RDCTL_WAIT_OFS;
} else
{
ASSERT(false);
@@ -741,27 +1220,27 @@
void FlashCtl_enableInterrupt(uint32_t flags)
{
- FLCTL->rIE.r |= flags;
+ FLCTL->IE |= flags;
}
void FlashCtl_disableInterrupt(uint32_t flags)
{
- FLCTL->rIE.r &= ~flags;
+ FLCTL->IE &= ~flags;
}
uint32_t FlashCtl_getInterruptStatus(void)
{
- return FLCTL->rIFG.r;
+ return FLCTL->IFG;
}
uint32_t FlashCtl_getEnabledInterruptStatus(void)
{
- return FlashCtl_getInterruptStatus() & FLCTL->rIE.r;
+ return FlashCtl_getInterruptStatus() & FLCTL->IE;
}
void FlashCtl_clearInterruptFlag(uint32_t flags)
{
- FLCTL->rCLRIFG.r |= flags;
+ FLCTL->CLRIFG |= flags;
}
void FlashCtl_registerInterrupt(void (*intHandler)(void))
@@ -790,3 +1269,301 @@
Interrupt_unregisterInterrupt(INT_FLCTL);
}
+uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr)
+{
+ uint32_t readMode, waitState, bankProgram, bankOneStart;
+
+ /* Changing the waitstate and read mode of whichever bank we are in */
+ /* Finding out which bank we are in */
+ if(addr > SysCtl_getFlashSize())
+ {
+ bankOneStart = __INFO_FLASH_TECH_MIDDLE__;
+ }
+ else
+ {
+ bankOneStart = SysCtl_getFlashSize() / 2;
+ }
+
+ bankProgram =
+ addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
+
+ /* Saving the current wait states and read mode */
+ waitState = FlashCtl_getWaitState(bankProgram);
+ readMode = FlashCtl_getReadMode(bankProgram);
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setWaitState(bankProgram, (2 * waitState) + 1);
+
+ /* Changing to PROGRAM VERIFY mode */
+ FlashCtl_setReadMode(bankProgram, FLASH_PROGRAM_VERIFY_READ_MODE);
+
+ data = ~(~(data) & HWREG8(addr));
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setReadMode(bankProgram, readMode);
+ FlashCtl_setWaitState(bankProgram, waitState);
+
+ return data;
+}
+
+uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr)
+{
+ uint32_t readMode, waitState, bankProgram, bankOneStart;
+
+ /* Changing the waitstate and read mode of whichever bank we are in */
+ /* Finding out which bank we are in */
+ if(addr > SysCtl_getFlashSize())
+ {
+ bankOneStart = __INFO_FLASH_TECH_MIDDLE__;
+ }
+ else
+ {
+ bankOneStart = SysCtl_getFlashSize() / 2;
+ }
+
+ bankProgram =
+ addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1;
+
+ /* Saving the current wait states and read mode */
+ waitState = FlashCtl_getWaitState(bankProgram);
+ readMode = FlashCtl_getReadMode(bankProgram);
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setWaitState(bankProgram, (2 * waitState) + 1);
+
+ /* Changing to PROGRAM VERIFY mode */
+ FlashCtl_setReadMode(bankProgram, FLASH_PROGRAM_VERIFY_READ_MODE);
+
+ data |= ~(HWREG8(addr) | data);
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setReadMode(bankProgram, readMode);
+ FlashCtl_setWaitState(bankProgram, waitState);
+
+ return data;
+}
+
+uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr)
+{
+ uint32_t bankProgramStart, bankProgramEnd, bank1Start;
+ uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
+
+ /* Changing the waitstate and read mode of whichever bank we are in */
+ /* Finding out which bank we are in */
+ if(addr > SysCtl_getFlashSize())
+ {
+ bank1Start = __INFO_FLASH_TECH_MIDDLE__;
+ }
+ else
+ {
+ bank1Start = SysCtl_getFlashSize() / 2;
+ }
+
+ bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+ bankProgramEnd = (addr + 4) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+
+ /* Saving the current wait states and read mode */
+ b0WaitState = FlashCtl_getWaitState(bankProgramStart);
+ b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
+ FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
+ b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
+ FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
+ }
+
+ data = ~(~(data) & HWREG32(addr));
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
+ FlashCtl_setWaitState(bankProgramStart, b0WaitState);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
+ FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
+ }
+
+ return data;
+}
+
+uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr)
+{
+ uint32_t bankProgramStart, bankProgramEnd, bank1Start;
+ uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
+
+ /* Changing the waitstate and read mode of whichever bank we are in */
+ /* Finding out which bank we are in */
+ if(addr > SysCtl_getFlashSize())
+ {
+ bank1Start = __INFO_FLASH_TECH_MIDDLE__;
+ }
+ else
+ {
+ bank1Start = SysCtl_getFlashSize() / 2;
+ }
+
+ bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+ bankProgramEnd = (addr + 4) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+
+ /* Saving the current wait states and read mode */
+ b0WaitState = FlashCtl_getWaitState(bankProgramStart);
+ b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
+ FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
+ b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
+ FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
+ }
+
+ data |= ~(HWREG32(addr) | data);
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
+ FlashCtl_setWaitState(bankProgramStart, b0WaitState);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
+ FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
+ }
+
+ return data;
+}
+
+void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size)
+{
+
+ uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii;
+ uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
+
+ /* Waiting for idle status */
+ while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
+ != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
+ {
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
+ }
+
+ /* Changing the waitstate and read mode of whichever bank we are in */
+ /* Finding out which bank we are in */
+ if(addr > SysCtl_getFlashSize())
+ {
+ bank1Start = __INFO_FLASH_TECH_MIDDLE__;
+ }
+ else
+ {
+ bank1Start = SysCtl_getFlashSize() / 2;
+ }
+
+ bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+ bankProgramEnd = (addr + size) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+
+ /* Saving the current wait states and read mode */
+ b0WaitState = FlashCtl_getWaitState(bankProgramStart);
+ b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
+ FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
+ b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
+ FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
+ }
+
+ /* Going through each BURST program register and masking out for pre
+ * verifcation
+ */
+ size = (size / 4);
+ for (ii = 0; ii < size; ii++)
+ {
+ HWREG32(__getBurstProgramRegs[ii]) |=
+ ~(HWREG32(__getBurstProgramRegs[ii])
+ | HWREG32(addr));
+ addr += 4;
+ }
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
+ FlashCtl_setWaitState(bankProgramStart, b0WaitState);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
+ FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
+ }
+
+}
+void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size)
+{
+ uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii;
+ uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode;
+
+ /* Waiting for idle status */
+ while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK)
+ != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0)
+ {
+ BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT,
+ FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1;
+ }
+
+ /* Changing the waitstate and read mode of whichever bank we are in */
+ /* Finding out which bank we are in */
+ if(addr > SysCtl_getFlashSize())
+ {
+ bank1Start = __INFO_FLASH_TECH_MIDDLE__;
+ }
+ else
+ {
+ bank1Start = SysCtl_getFlashSize() / 2;
+ }
+
+ bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+ bankProgramEnd = (addr + size) < bank1Start ? FLASH_BANK0 : FLASH_BANK1;
+
+ /* Saving the current wait states and read mode */
+ b0WaitState = FlashCtl_getWaitState(bankProgramStart);
+ b0ReadMode = FlashCtl_getReadMode(bankProgramStart);
+ FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ b1WaitState = FlashCtl_getWaitState(bankProgramEnd);
+ b1ReadMode = FlashCtl_getReadMode(bankProgramEnd);
+ FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1);
+ FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE);
+ }
+
+ /* Going through each BURST program register and masking out for post
+ * verifcation if needed
+ */
+ size = (size / 4);
+ for (ii = 0; ii < size; ii++)
+ {
+ HWREG32(__getBurstProgramRegs[ii]) = ~(~(HWREG32(
+ __getBurstProgramRegs[ii])) & HWREG32(addr));
+
+ addr += 4;
+ }
+
+ /* Setting the wait state to account for the mode */
+ FlashCtl_setReadMode(bankProgramStart, b0ReadMode);
+ FlashCtl_setWaitState(bankProgramStart, b0WaitState);
+
+ if (bankProgramStart != bankProgramEnd)
+ {
+ FlashCtl_setReadMode(bankProgramEnd, b1ReadMode);
+ FlashCtl_setWaitState(bankProgramEnd, b1WaitState);
+ }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
index 41d50ae..0c2cc8f 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/flash.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -84,7 +84,7 @@
#define FLASH_MARGIN0B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_9
#define FLASH_MARGIN1B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_10
-#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE 0x70000
+#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7
#define FLASH_BANK0 0x00
#define FLASH_BANK1 0x01
@@ -146,13 +146,8 @@
#define FLASH_COLLATED_WRITE_MODE 0x01
#define FLASH_IMMEDIATE_WRITE_MODE 0x02
-#define FlashInternal_eraseSector \
- ((bool (*)(uint32_t addr, \
- bool verify))ROM_FLASHCTLTABLE[9])
-
-#define FlashInternal_performMassErase \
- ((bool (*)(bool verify))ROM_FLASHCTLTABLE[8])
-
+#define __INFO_FLASH_TECH_START__ 0x00200000
+#define __INFO_FLASH_TECH_MIDDLE__ 0x00202000
//*****************************************************************************
@@ -160,6 +155,32 @@
// Prototypes for the APIs.
//
//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Calculates the flash bank and sector number given an address. Stores the
+//! results into the two pointers given as parameters. The user must provide
+//! a valid memory address (an address in SRAM for example will give an invalid
+//! result).
+//!
+//! \param addr Address to calculate the bank/sector information for
+//!
+//! \param sectorNum The sector number will be stored in here after the function
+//! completes.
+//!
+//! \param sectorNum The bank number will be stored in here after the function
+//! completes.
+//!
+//! \note For simplicity, this API only works with address in MAIN flash memory.
+//! For calculating the sector/bank number of an address in info memory,
+//! please refer to your device datasheet/
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
+ uint32_t *bankNum);
+
//*****************************************************************************
//
//! Enables read buffering on accesses to a specified bank of flash memory
@@ -251,6 +272,11 @@
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
+//! \note Not all devices will contain a dedicated INFO memory. Please check the
+//! device datasheet to see if your device has INFO memory available for use.
+//! For devices without INFO memory, any operation related to the INFO memory
+//! will be ignored by the hardware.
+//!
//! \return true if sector protection disabled false otherwise.
//
//*****************************************************************************
@@ -308,6 +334,11 @@
//! depending on the specific device. Also, for INFO memory space, only sectors
//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
//!
+//! \note Not all devices will contain a dedicated INFO memory. Please check the
+//! device datasheet to see if your device has INFO memory available for use.
+//! For devices without INFO memory, any operation related to the INFO memory
+//! will be ignored by the hardware.
+//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
@@ -364,6 +395,11 @@
//! depending on the specific device. Also, for INFO memory space, only sectors
//! FLASH_SECTOR0 and FLASH_SECTOR1 will exist.
//!
+//! \note Not all devices will contain a dedicated INFO memory. Please check the
+//! device datasheet to see if your device has INFO memory available for use.
+//! For devices without INFO memory, any operation related to the INFO memory
+//! will be ignored by the hardware.
+//!
//! \return true if sector protection enabled false otherwise.
//
//*****************************************************************************
@@ -384,13 +420,25 @@
//! of 32 zeros, or a high pattern (each register will be checked versus a
//! pattern of 32 ones). Valid values are: FLASH_0_PATTERN, FLASH_1_PATTERN
//!
-//! Note that there are no sector/boundary restrictions for this function,
+//! \note There are no sector/boundary restrictions for this function,
//! however it is encouraged to proved a start address aligned on 32-bit
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
-//! Note that this function is blocking and will not exit until operation has
-//! either completed or failed due to an error.
+//! \note This function is blocking and will not exit until operation has
+//! either completed or failed due to an error. Furthermore, given the
+//! complex verification requirements of the flash controller, master
+//! interrupts are disabled throughout execution of this function. The original
+//! interrupt context is saved at the start of execution and restored prior
+//! to exit of the API.
+//!
+//! \note Due to the hardware limitations of the flash controller, this
+//! function cannot verify a memory adress in the same flash bank that it
+//! is executing from. If using the ROM version of this API (by using the
+//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//! in flash then special care needs to be taken to ensure no code execution
+//! or reads happen in the flash bank being programmed while this API is
+//! being executed.
//!
//! \return true if memory verification is successful, false otherwise.
//
@@ -403,8 +451,20 @@
//! Performs a mass erase on all unprotected flash sectors. Protected sectors
//! are ignored.
//!
-//! \note This function is blocking and will not exit until operation has
-//! either completed or failed due to an error.
+//! \note This function is blocking and will not exit until operation has
+//! either completed or failed due to an error. Furthermore, given the
+//! complex verification requirements of the flash controller, master
+//! interrupts are disabled throughout execution of this function. The original
+//! interrupt context is saved at the start of execution and restored prior
+//! to exit of the API.
+//!
+//! \note Due to the hardware limitations of the flash controller, this
+//! function cannot erase a memory adress in the same flash bank that it
+//! is executing from. If using the ROM version of this API (by using the
+//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//! in flash then special care needs to be taken to ensure no code execution
+//! or reads happen in the flash bank being programmed while this API is
+//! being executed.
//!
//! \return true if mass erase completes successfully, false otherwise
//
@@ -413,6 +473,18 @@
//*****************************************************************************
//
+//! Initiates a mass erase and returns control back to the program. This is a
+//! non-blocking function, however it is the user's responsibility to perform
+//! the necessary verification requirements after the interrupt is set to
+//! signify completion.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashCtl_initiateMassErase(void);
+
+//*****************************************************************************
+//
//! Erases a sector of MAIN or INFO flash memory.
//!
//! \param addr The start of the sector to erase. Note that with flash,
@@ -421,8 +493,20 @@
//! this function which is not on a 4KB boundary, the entire sector
//! will still be erased.
//!
-//! Note that this function is blocking and will not exit until operation has
-//! either completed or failed due to an error.
+//! \note This function is blocking and will not exit until operation has
+//! either completed or failed due to an error. Furthermore, given the
+//! complex verification requirements of the flash controller, master
+//! interrupts are disabled throughout execution of this function. The original
+//! interrupt context is saved at the start of execution and restored prior
+//! to exit of the API.
+//!
+//! \note Due to the hardware limitations of the flash controller, this
+//! function cannot erase a memory adress in the same flash bank that it
+//! is executing from. If using the ROM version of this API (by using the
+//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//! in flash then special care needs to be taken to ensure no code execution
+//! or reads happen in the flash bank being programmed while this API is
+//! being executed.
//!
//! \return true if sector erase is successful, false otherwise.
//
@@ -444,8 +528,20 @@
//! boundaries. Providing an unaligned address will result in unaligned data
//! accesses and detriment efficiency.
//!
-//! Note that this function is blocking and will not exit until operation has
-//! either completed or failed due to an error.
+//! \note This function is blocking and will not exit until operation has
+//! either completed or failed due to an error. Furthermore, given the
+//! complex verification requirements of the flash controller, master
+//! interrupts are disabled throughout execution of this function. The original
+//! interrupt context is saved at the start of execution and restored prior
+//! to exit of the API.
+//!
+//! \note Due to the hardware limitations of the flash controller, this
+//! function cannot program a memory adress in the same flash bank that it
+//! is executing from. If using the ROM version of this API (by using the
+//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//! in flash then special care needs to be taken to ensure no code execution
+//! or reads happen in the flash bank being programmed while this API is
+//! being executed.
//!
//! \return Whether or not the program succeeded
//
@@ -794,6 +890,40 @@
//*****************************************************************************
extern void FlashCtl_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Initiates a sector erase of MAIN or INFO flash memory. Note that this
+//! function simply initaites the sector erase, but does no verification
+//! which is required by the flash controller. The user must manually set
+//! and enable interrupts on the flash controller to fire on erase completion
+//! and then use the FlashCtl_verifyMemory function to verify that the sector
+//! was actually erased
+//!
+//! \param addr The start of the sector to erase. Note that with flash,
+//! the minimum allowed size that can be erased is a flash sector
+//! (which is 4KB on the MSP432 family). If an address is provided to
+//! this function which is not on a 4KB boundary, the entire sector
+//! will still be erased.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashCtl_initiateSectorErase(uint32_t addr);
+
+
+/* The following functions are advanced functions that are used by the flash
+ * driver to remask a failed bit in the event of a post or pre verification
+ * failure. They are meant to be advanced functions and should not be used
+ * by the majority of users (unless you are writing your own flash driver).
+ */
+extern uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr);
+extern uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr);
+extern uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr);
+extern uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr);
+extern void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size);
+extern void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size);
+
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
index 176fdd1..aa90a29 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,8 +41,8 @@
//
// Enable the coprocessors used by the floating-point unit.
//
- SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_M | SCB_CPACR_CP10_M))
- | SCB_CPACR_CP11_M | SCB_CPACR_CP10_M);
+ SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK))
+ | SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK);
}
void FPU_disableModule(void)
@@ -50,7 +50,7 @@
//
// Disable the coprocessors used by the floating-point unit.
//
- SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_M | SCB_CPACR_CP11_M)));
+ SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK)));
}
void FPU_enableStacking(void)
@@ -60,7 +60,7 @@
// disable lazy state preservation (meaning that the floating-point state
// is always stacked when floating-point instructions are used).
//
- FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN) | FPU_FPCCR_ASPEN;
+ FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN_Msk) | FPU_FPCCR_ASPEN_Msk;
}
void FPU_enableLazyStacking(void)
@@ -69,7 +69,7 @@
// Enable automatic and lazy state preservation for the floating-point
// unit.
//
- FPU->FPCCR |= FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN;
+ FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
}
void FPU_disableStacking(void)
@@ -78,7 +78,7 @@
// Disable automatic and lazy state preservation for the floating-point
// unit.
//
- FPU->FPCCR &= ~(FPU_FPCCR_ASPEN | FPU_FPCCR_LSPEN);
+ FPU->FPCCR &= ~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk);
}
void FPU_setHalfPrecisionMode(uint32_t mode)
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
index f9698bb..cd4729e 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/fpu.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
index 9ecfb79..b236808 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,6 +41,21 @@
#include <gpio.h>
#include <debug.h>
#include <interrupt.h>
+#include <hw_memmap.h>
+
+/* DriverLib internal GPIO register offset for optimized performace */
+#define OFS_LIB_PAIN ((uint32_t)&P1->IN - (uint32_t)P1)
+#define OFS_LIB_PAOUT ((uint32_t)&P1->OUT - (uint32_t)P1)
+#define OFS_LIB_PADIR ((uint32_t)&P1->DIR - (uint32_t)P1)
+#define OFS_LIB_PAREN ((uint32_t)&P1->REN - (uint32_t)P1)
+#define OFS_LIB_PADS ((uint32_t)&P1->DS - (uint32_t)P1)
+#define OFS_LIB_PASEL0 ((uint32_t)&P1->SEL0 - (uint32_t)P1)
+#define OFS_LIB_PASEL1 ((uint32_t)&P1->SEL1 - (uint32_t)P1)
+#define OFS_LIB_PAIE ((uint32_t)&P1->IE - (uint32_t)P1)
+#define OFS_LIB_PAIES ((uint32_t)&P1->IES - (uint32_t)P1)
+#define OFS_LIB_PAIFG ((uint32_t)&P1->IFG - (uint32_t)P1)
+#define OFS_LIB_P1IE ((uint32_t)&P1->IE - (uint32_t)P1)
+#define OFS_LIB_P2IE ((uint32_t)&P2->IE - (uint32_t)P2)
static const uint32_t GPIO_PORT_TO_INT[] =
{ 0x00,
@@ -51,41 +66,39 @@
INT_PORT5,
INT_PORT6 };
-static const uint32_t GPIO_PORT_TO_BASE[] =
+static uint32_t GPIO_PORT_TO_BASE[] =
{ 0x00,
- 0x40004C00,
- 0x40004C01,
- 0x40004C20,
- 0x40004C21,
- 0x40004C40,
- 0x40004C41,
- 0x40004C60,
- 0x40004C61,
- 0x40004C80,
- 0x40004C81,
- 0x40004D20
+ (uint32_t)P1,
+ (uint32_t)P1+1,
+ (uint32_t)P3,
+ (uint32_t)P3+1,
+ (uint32_t)P5,
+ (uint32_t)P5+1,
+ (uint32_t)P7,
+ (uint32_t)P7+1,
+ (uint32_t)P9,
+ (uint32_t)P9+1,
+ (uint32_t)PJ
};
void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
-
- return;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
}
+
void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
{
-
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAREN) &= ~selectedPins;
}
@@ -95,20 +108,20 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PADIR) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
- HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
- HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
- HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
}
}
@@ -119,20 +132,20 @@
{
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
switch (mode)
{
case GPIO_PRIMARY_MODULE_FUNCTION:
- HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
break;
case GPIO_SECONDARY_MODULE_FUNCTION:
- HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
case GPIO_TERTIARY_MODULE_FUNCTION:
- HWREG16(baseAddress + OFS_PASEL0) |= selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
break;
}
}
@@ -144,7 +157,7 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
}
@@ -154,7 +167,7 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
}
@@ -164,7 +177,7 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAOUT) ^= selectedPins;
}
@@ -174,12 +187,12 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
- HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
}
@@ -189,21 +202,21 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins;
- HWREG16(baseAddress + OFS_PAREN) |= selectedPins;
- HWREG16(baseAddress + OFS_PAOUT) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
}
uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort,
uint_fast16_t selectedPins)
{
- uint16_t inputPinValue;
+ uint_fast16_t inputPinValue;
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins);
+ inputPinValue = HWREG16(baseAddress + OFS_LIB_PAIN) & (selectedPins);
if (inputPinValue > 0)
return GPIO_INPUT_PIN_HIGH;
@@ -216,7 +229,7 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PAIE) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAIE) |= selectedPins;
}
@@ -226,7 +239,7 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAIE) &= ~selectedPins;
}
@@ -236,7 +249,7 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- return HWREG16(baseAddress + OFS_PAIFG) & selectedPins;
+ return HWREG16(baseAddress + OFS_LIB_PAIFG) & selectedPins;
}
@@ -247,7 +260,7 @@
uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
- HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAIFG) &= ~selectedPins;
}
@@ -259,9 +272,9 @@
if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect)
- HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAIES) &= ~selectedPins;
else
- HWREG16(baseAddress + OFS_PAIES) |= selectedPins;
+ HWREG16(baseAddress + OFS_LIB_PAIES) |= selectedPins;
}
uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
@@ -281,15 +294,15 @@
case GPIO_PORT_P5:
case GPIO_PORT_P7:
case GPIO_PORT_P9:
- return (HWREG8(baseAddr + OFS_P1IE) & pendingInts);
+ return (HWREG8(baseAddr + OFS_LIB_P1IE) & pendingInts);
case GPIO_PORT_P2:
case GPIO_PORT_P4:
case GPIO_PORT_P6:
case GPIO_PORT_P8:
case GPIO_PORT_P10:
- return (HWREG8(baseAddr + OFS_P2IE) & pendingInts);
+ return (HWREG8(baseAddr + OFS_LIB_P2IE) & pendingInts);
case GPIO_PORT_PJ:
- return (HWREG16(baseAddr + OFS_PAIE) & pendingInts);
+ return (HWREG16(baseAddr + OFS_LIB_PAIE) & pendingInts);
default:
return 0;
}
@@ -303,7 +316,7 @@
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
- HWREG8(baseAddr + OFS_PADS) |= selectedPins;
+ HWREG8(baseAddr + OFS_LIB_PADS) |= selectedPins;
}
@@ -314,7 +327,7 @@
baseAddr = GPIO_PORT_TO_BASE[selectedPort];
- HWREG8(baseAddr + OFS_PADS) &= ~selectedPins;
+ HWREG8(baseAddr + OFS_LIB_PADS) &= ~selectedPins;
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
index 7a33a49..e5af07b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/gpio.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -68,8 +68,14 @@
#define GPIO_PORT_P8 8
#define GPIO_PORT_P9 9
#define GPIO_PORT_P10 10
-#define GPIO_PORT_PJ 11
+#define GPIO_PORT_PA 1
+#define GPIO_PORT_PB 3
+#define GPIO_PORT_PC 5
+#define GPIO_PORT_PD 7
+#define GPIO_PORT_PE 9
+#define GPIO_PORT_PJ 11
+
#define GPIO_PIN0 (0x0001)
#define GPIO_PIN1 (0x0002)
#define GPIO_PIN2 (0x0004)
@@ -406,8 +412,6 @@
//! - \b GPIO_PIN14
//! - \b GPIO_PIN15
//!
-//! Modified bits of \b PxOUT register.
-//!
//! \return None
//
//*****************************************************************************
@@ -998,7 +1002,11 @@
//*****************************************************************************
extern void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
uint_fast8_t selectedPins);
-
+
+/* Backwards Compatibility Layer */
+#define GPIO_selectInterruptEdge GPIO_interruptEdgeSelect
+#define GPIO_clearInterrupt GPIO_clearInterruptFlag
+
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/hw_memmap.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/hw_memmap.h
new file mode 100644
index 0000000..51b21ba
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/hw_memmap.h
@@ -0,0 +1,87 @@
+/*
+ * -------------------------------------------
+ * MSP432 DriverLib - v3_10_00_09
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __HW_MEMMAP__
+#define __HW_MEMMAP__
+
+#define __DRIVERLIB_MSP432P4XX_FAMILY__
+//*****************************************************************************
+//
+// Include device specific header file
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// SUCCESS and FAILURE for API return value
+//
+//*****************************************************************************
+#define STATUS_SUCCESS 0x01
+#define STATUS_FAIL 0x00
+
+//*****************************************************************************
+//
+// Macros for hardware access
+//
+//*****************************************************************************
+#define HWREG8(x) (*((volatile uint8_t *)(x)))
+#define HWREG16(x) (*((volatile uint16_t *)(x)))
+#define HWREG32(x) (*((volatile uint32_t *)(x)))
+#define HWREG(x) (HWREG16(x))
+#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
+#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
+#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
+#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
+
+/******************************************************************************
+* Device memory map *
+******************************************************************************/
+#define __MAIN_MEMORY_START__ (0x00000000) /**< Main Flash memory start address */
+#define __MAIN_MEMORY_END__ (0x0003FFFF) /**< Main Flash memory end address */
+#define __BSL_MEMORY_START__ (0x00202000) /**< BSL memory start address */
+#define __BSL_MEMORY_END__ (0x00203FFF) /**< BSL memory end address */
+#define __SRAM_START__ (0x20000000) /**< SRAM memory start address */
+#define __SRAM_END__ (0x2000FFFF) /**< SRAM memory end address */
+
+/******************************************************************************
+* Definitions for 8/16/32-bit wide bit band access *
+******************************************************************************/
+#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+
+#endif // #ifndef __HW_MEMMAP__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
index 034d7b6..17a89bf 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,10 +37,11 @@
#include <i2c.h>
#include <interrupt.h>
#include <debug.h>
+#include <hw_memmap.h>
void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config)
{
- uint16_t preScalarValue;
+ uint_fast16_t preScalarValue;
ASSERT(
(EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource)
@@ -49,7 +50,8 @@
ASSERT(
(EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate)
- || (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate));
+ || (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate)
+ || (EUSCI_B_I2C_SET_DATA_RATE_1MBPS == config->dataRate));
ASSERT(
(EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration)
@@ -59,15 +61,16 @@
== config->autoSTOPGeneration));
/* Disable the USCI module and clears the other bits of control register */
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+ 1;
/* Configure Automatic STOP condition generation */
- EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r & ~UCASTP_M)
+ EUSCI_B_CMSIS(moduleInstance)->CTLW1 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW1 & ~EUSCI_B_CTLW1_ASTP_MASK)
| (config->autoSTOPGeneration);
/* Byte Count Threshold */
- EUSCI_B_CMSIS(moduleInstance)->rTBCNT.r = config->byteCounterThreshold;
+ EUSCI_B_CMSIS(moduleInstance)->TBCNT = config->byteCounterThreshold;
/*
* Configure as I2C master mode.
@@ -75,10 +78,11 @@
* UCMODE_3 = I2C mode
* UCSYNC = Synchronous mode
*/
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_M)
- | (config->selectClockSource | UCMST | UCMODE_3 | UCSYNC
- | UCSWRST);
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_B_CTLW0_SSEL_MASK)
+ | (config->selectClockSource | EUSCI_B_CTLW0_MST
+ | EUSCI_B_CTLW0_MODE_3 | EUSCI_B_CTLW0_SYNC
+ | EUSCI_B_CTLW0_SWRST);
/*
* Compute the clock divider that achieves the fastest speed less than or
@@ -88,7 +92,7 @@
*/
preScalarValue = (uint16_t) (config->i2cClk / config->dataRate);
- EUSCI_B_CMSIS(moduleInstance)->rBRW = preScalarValue;
+ EUSCI_B_CMSIS(moduleInstance)->BRW = preScalarValue;
}
void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
@@ -101,35 +105,38 @@
|| (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
/* Disable the USCI module */
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+ 1;
/* Clear USCI master mode */
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCMST))
- | (UCMODE_3 + UCSYNC);
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_MST))
+ | (EUSCI_B_CTLW0_MODE_3 + EUSCI_B_CTLW0_SYNC);
/* Set up the slave address. */
- HWREG16(moduleInstance + OFS_UCB0I2COA0 + slaveAddressOffset) = slaveAddress
- + slaveOwnAddressEnable;
+ HWREG16((uint32_t)&EUSCI_B_CMSIS(moduleInstance)->I2COA0 + slaveAddressOffset) =
+ slaveAddress + slaveOwnAddressEnable;
}
void I2C_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+ 0;
}
void I2C_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+ 1;
;
}
void I2C_setSlaveAddress(uint32_t moduleInstance, uint_fast16_t slaveAddress)
{
/* Set the address of the slave with which the master will communicate */
- EUSCI_B_CMSIS(moduleInstance)->rI2CSA.r = (slaveAddress);
+ EUSCI_B_CMSIS(moduleInstance)->I2CSA = (slaveAddress);
}
void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
@@ -138,8 +145,8 @@
(EUSCI_B_I2C_TRANSMIT_MODE == mode)
|| (EUSCI_B_I2C_RECEIVE_MODE == mode));
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0
& (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
}
@@ -147,88 +154,89 @@
uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
{
//Set USCI in Receive mode
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTR_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TR_OFS) = 0;
//Send start
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= (UCTXSTT + UCTXSTP);
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= (EUSCI_B_CTLW0_TXSTT + EUSCI_B_CTLW0_TXSTP);
//Poll for receive interrupt flag.
- while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
+ while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
;
//Send single byte data.
- return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+ return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData)
{
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = transmitData;
}
uint8_t I2C_slaveGetData(uint32_t moduleInstance)
{
//Read a byte.
- return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+ return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
uint8_t I2C_isBusBusy(uint32_t moduleInstance)
{
//Return the bus busy status.
- return EUSCI_B_CMSIS(moduleInstance)->rSTATW.b.bBBUSY;
+ return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->STATW,
+ EUSCI_B_STATW_BBUSY_OFS);
}
void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
{
//Store current TXIE status
- uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+ uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
- while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
+ while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
;
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
- while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG))
+ while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
;
//Send stop condition.
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTXSTP;
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TXSTP;
//Clear transmit interrupt flag before enabling interrupt again
- EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(UCTXIFG);
+ EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(EUSCI_B_IFG_TXIFG);
//Reinstate transmit interrupt enable
- EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+ EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
}
bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
- uint16_t txieStatus;
+ uint_fast16_t txieStatus;
uint32_t timeout2 = timeout;
ASSERT(timeout > 0);
//Store current TXIE status
- txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+ txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
- while ((!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG)) && --timeout)
+ while ((!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG)) && --timeout)
;
//Check if transfer timed out
@@ -236,10 +244,10 @@
return false;
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
- while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout2)
;
@@ -248,13 +256,13 @@
return false;
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
//Clear transmit interrupt flag before enabling interrupt again
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,UCTXIFG_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,EUSCI_B_IFG_TXIFG0_OFS) = 0;
//Reinstate transmit interrupt enable
- EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+ EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
return true;
}
@@ -262,43 +270,43 @@
void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData)
{
//Store current transmit interrupt enable
- uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+ uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
- while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Reinstate transmit interrupt enable
- EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+ EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
}
bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
uint8_t txData, uint32_t timeout)
{
- uint16_t txieStatus;
+ uint_fast16_t txieStatus;
ASSERT(timeout > 0);
//Store current transmit interrupt enable
- txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE;
+ txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
//Disable transmit interrupt enable
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
//Send start condition.
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT;
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
//Poll for transmit interrupt flag.
- while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout))
;
@@ -307,10 +315,10 @@
return false;
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Reinstate transmit interrupt enable
- EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus;
+ EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
return true;
}
@@ -318,16 +326,16 @@
void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
- if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+ if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
- (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
}
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
}
bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
@@ -336,11 +344,11 @@
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
- if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+ if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
- while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
- UCTXIFG_OFS)) && --timeout)
+ while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+ EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
;
//Check if transfer timed out
@@ -349,7 +357,7 @@
}
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
return true;
}
@@ -357,23 +365,23 @@
void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
{
//If interrupts are not used, poll for flags
- if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+ if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
- (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
}
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
- while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
}
bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
@@ -384,11 +392,11 @@
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
- if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+ if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
- while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
- UCTXIFG_OFS)) && --timeout)
+ while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+ EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
;
//Check if transfer timed out
@@ -397,10 +405,10 @@
}
//Send single byte data.
- EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData;
+ EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
//Poll for transmit interrupt flag.
- while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
&& --timeout2)
;
@@ -409,7 +417,7 @@
return false;
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
return true;
}
@@ -417,16 +425,16 @@
void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
{
//If interrupts are not used, poll for flags
- if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+ if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
while
- (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
;
}
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
}
bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
@@ -435,11 +443,11 @@
ASSERT(timeout > 0);
//If interrupts are not used, poll for flags
- if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
+ if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
{
//Poll for transmit interrupt flag.
- while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
- UCTXIFG_OFS)) && --timeout)
+ while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+ EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
;
//Check if transfer timed out
@@ -448,7 +456,7 @@
}
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
return 0x01;
}
@@ -456,31 +464,33 @@
void I2C_masterReceiveStart(uint32_t moduleInstance)
{
//Set USCI in Receive mode
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCTR)) | UCTXSTT;
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_TR))
+ | EUSCI_B_CTLW0_TXSTT;
}
uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
{
- return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.a.bRXBUF;
+ return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance)
{
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) =
+ 1;
//Wait for Stop to finish
- while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS))
+ while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS))
{
// Wait for RX buffer
- while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG, UCRXIFG_OFS))
+ while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
;
}
/* Capture data from receive buffer after setting stop bit due to
MSP430 I2C critical timing. */
- return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+ return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
}
bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
@@ -491,10 +501,10 @@
ASSERT(timeout > 0);
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
//Wait for Stop to finish
- while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS)
+ while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS)
&& --timeout)
;
@@ -503,7 +513,7 @@
return false;
// Wait for RX buffer
- while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
+ while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
&& --timeout2)
;
@@ -513,7 +523,7 @@
//Capture data from receive buffer after setting stop bit due to
//MSP430 I2C critical timing.
- *txData = (EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF);
+ *txData = (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
return true;
}
@@ -521,58 +531,63 @@
void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance)
{
//Send stop condition.
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
}
uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
{
//Polling RXIFG0 if RXIE is not enabled
- if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCRXIE0_OFS))
+ if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_RXIE0_OFS))
{
- while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,
- UCRXIFG0_OFS))
+ while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+ EUSCI_B_IFG_RXIFG0_OFS))
;
}
//Read a byte.
- return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF;
+ return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK) ;
}
uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
- return moduleInstance + OFS_UCB0RXBUF;
+ return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->RXBUF;
}
uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
- return moduleInstance + OFS_UCB0TXBUF;
+ return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
}
uint8_t I2C_masterIsStopSent(uint32_t moduleInstance)
{
- return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS);
+ return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
+ EUSCI_B_CTLW0_TXSTP_OFS);
}
bool I2C_masterIsStartSent(uint32_t moduleInstance)
{
- return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTT_OFS);
+ return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
+ EUSCI_B_CTLW0_TXSTT_OFS);
}
void I2C_masterSendStart(uint32_t moduleInstance)
{
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTT_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTT_OFS) =
+ 1;
}
void I2C_enableMultiMasterMode(uint32_t moduleInstance)
{
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+ 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 1;
}
void I2C_disableMultiMasterMode(uint32_t moduleInstance)
{
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1;
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCMM_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+ 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 0;
}
void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
@@ -597,7 +612,7 @@
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Enable the interrupt masked bit
- EUSCI_B_CMSIS(moduleInstance)->rIE.r |= mask;
+ EUSCI_B_CMSIS(moduleInstance)->IE |= mask;
}
void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
@@ -622,7 +637,7 @@
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Disable the interrupt masked bit
- EUSCI_B_CMSIS(moduleInstance)->rIE.r &= ~(mask);
+ EUSCI_B_CMSIS(moduleInstance)->IE &= ~(mask);
}
void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
@@ -646,7 +661,7 @@
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Clear the I2C interrupt source.
- EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
+ EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(mask);
}
uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
@@ -670,41 +685,41 @@
+ EUSCI_B_I2C_RECEIVE_INTERRUPT2
+ EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
//Return the interrupt status of the request masked bit.
- return EUSCI_B_CMSIS(moduleInstance)->rIFG.r & mask;
+ return EUSCI_B_CMSIS(moduleInstance)->IFG & mask;
}
uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance)
{
return I2C_getInterruptStatus(moduleInstance,
- EUSCI_B_CMSIS(moduleInstance)->rIE.r);
+ EUSCI_B_CMSIS(moduleInstance)->IE);
}
uint_fast16_t I2C_getMode(uint32_t moduleInstance)
{
//Read the I2C mode.
- return (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & UCTR);
+ return (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & EUSCI_B_CTLW0_TR);
}
void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
- case EUSCI_B0_MODULE:
+ case EUSCI_B0_BASE:
Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB0);
break;
- case EUSCI_B1_MODULE:
+ case EUSCI_B1_BASE:
Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB1);
break;
-#ifdef EUSCI_B2_MODULE
- case EUSCI_B2_MODULE:
+#ifdef EUSCI_B2_BASE
+ case EUSCI_B2_BASE:
Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB2);
break;
#endif
-#ifdef EUSCI_B3_MODULE
- case EUSCI_B3_MODULE:
+#ifdef EUSCI_B3_BASE
+ case EUSCI_B3_BASE:
Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB3);
break;
@@ -718,22 +733,22 @@
{
switch (moduleInstance)
{
- case EUSCI_B0_MODULE:
+ case EUSCI_B0_BASE:
Interrupt_disableInterrupt(INT_EUSCIB0);
Interrupt_unregisterInterrupt(INT_EUSCIB0);
break;
- case EUSCI_B1_MODULE:
+ case EUSCI_B1_BASE:
Interrupt_disableInterrupt(INT_EUSCIB1);
Interrupt_unregisterInterrupt(INT_EUSCIB1);
break;
-#ifdef EUSCI_B2_MODULE
- case EUSCI_B2_MODULE:
+#ifdef EUSCI_B2_BASE
+ case EUSCI_B2_BASE:
Interrupt_disableInterrupt(INT_EUSCIB2);
Interrupt_unregisterInterrupt(INT_EUSCIB2);
break;
#endif
-#ifdef EUSCI_B3_MODULE
- case EUSCI_B3_MODULE:
+#ifdef EUSCI_B3_BASE
+ case EUSCI_B3_BASE:
Interrupt_disableInterrupt(INT_EUSCIB3);
Interrupt_unregisterInterrupt(INT_EUSCIB3);
break;
@@ -742,3 +757,9 @@
ASSERT(false);
}
}
+
+void I2C_slaveSendNAK(uint32_t moduleInstance)
+{
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXNACK_OFS)
+ = 1;
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
index 95ca85d..93c0486 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/i2c.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -60,15 +60,17 @@
#include <msp.h>
#include "eusci.h"
-#define EUSCI_B_I2C_NO_AUTO_STOP UCASTP_0
-#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG UCASTP_1
-#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD UCASTP_2
+#define EUSCI_B_I2C_NO_AUTO_STOP EUSCI_B_CTLW1_ASTP_0
+#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG EUSCI_B_CTLW1_ASTP_1
+#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD \
+ EUSCI_B_CTLW1_ASTP_2
+#define EUSCI_B_I2C_SET_DATA_RATE_1MBPS 1000000
#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS 400000
#define EUSCI_B_I2C_SET_DATA_RATE_100KBPS 100000
-#define EUSCI_B_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK
-#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
+#define EUSCI_B_I2C_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK
+#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK
#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 0x00
#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 0x02
@@ -76,39 +78,39 @@
#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 0x06
#define EUSCI_B_I2C_OWN_ADDRESS_DISABLE 0x00
-#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE UCOAEN
+#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE EUSCI_B_I2COA0_OAEN
-#define EUSCI_B_I2C_TRANSMIT_MODE UCTR
+#define EUSCI_B_I2C_TRANSMIT_MODE EUSCI_B_CTLW0_TR
#define EUSCI_B_I2C_RECEIVE_MODE 0x00
-#define EUSCI_B_I2C_NAK_INTERRUPT UCNACKIE
-#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT UCALIE
-#define EUSCI_B_I2C_STOP_INTERRUPT UCSTPIE
-#define EUSCI_B_I2C_START_INTERRUPT UCSTTIE
-#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 UCTXIE0
-#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 UCTXIE1
-#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 UCTXIE2
-#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 UCTXIE3
-#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 UCRXIE0
-#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 UCRXIE1
-#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 UCRXIE2
-#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 UCRXIE3
-#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT UCBIT9IE
-#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT UCCLTOIE
-#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT UCBCNTIE
+#define EUSCI_B_I2C_NAK_INTERRUPT EUSCI_B_IE_NACKIE
+#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT EUSCI_B_IE_ALIE
+#define EUSCI_B_I2C_STOP_INTERRUPT EUSCI_B_IE_STPIE
+#define EUSCI_B_I2C_START_INTERRUPT EUSCI_B_IE_STTIE
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 EUSCI_B_IE_TXIE0
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 EUSCI_B_IE_TXIE1
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 EUSCI_B_IE_TXIE2
+#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 EUSCI_B_IE_TXIE3
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 EUSCI_B_IE_RXIE0
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 EUSCI_B_IE_RXIE1
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 EUSCI_B_IE_RXIE2
+#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 EUSCI_B_IE_RXIE3
+#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT EUSCI_B_IE_BIT9IE
+#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT EUSCI_B_IE_CLTOIE
+#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT EUSCI_B_IE_BCNTIE
-#define EUSCI_B_I2C_BUS_BUSY UCBBUSY
+#define EUSCI_B_I2C_BUS_BUSY EUSCI_B_STATW_BBUSY
#define EUSCI_B_I2C_BUS_NOT_BUSY 0x00
#define EUSCI_B_I2C_STOP_SEND_COMPLETE 0x00
-#define EUSCI_B_I2C_SENDING_STOP UCTXSTP
+#define EUSCI_B_I2C_SENDING_STOP EUSCI_B_CTLW0_TXSTP
#define EUSCI_B_I2C_START_SEND_COMPLETE 0x00
-#define EUSCI_B_I2C_SENDING_START UCTXSTT
+#define EUSCI_B_I2C_SENDING_START EUSCI_B_CTLW0_TXSTT
//*****************************************************************************
//
-//! \typedef eUSCI_I2C_MasterConfig
+//! ypedef eUSCI_I2C_MasterConfig
//! \brief Type definition for \link _eUSCI_I2C_MasterConfig \endlink structure
//!
//! \struct _eUSCI_I2C_MasterConfig
@@ -132,10 +134,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -154,6 +156,7 @@
//! selectClockSource).
//! \param dataRate set up for selecting data transfer rate.
//! Valid values are
+//! - \b EUSCI_B_I2C_SET_DATA_RATE_1MBPS
//! - \b EUSCI_B_I2C_SET_DATA_RATE_400KBPS
//! - \b EUSCI_B_I2C_SET_DATA_RATE_100KBPS
//! \param byteCounterThreshold sets threshold for automatic STOP or UCSTPIFG
@@ -168,10 +171,6 @@
//! bus speed for the master; however I2C module is still disabled till
//! I2C_enableModule is invoked
//!
-//! If the parameter \e dataRate is EUSCI_B_I2C_SET_DATA_RATE_400KBPS, then the
-//! master block will be set up to transfer data at 400 kbps; otherwise, it will
-//! be set up to transfer data at 100 kbps.
-//!
//! Modified bits are \b UCMST,UCMODE_3,\b UCSYNC of \b UCBxCTL0 register
//! \b UCSSELx, \b UCSWRST, of \b UCBxCTL1 register
//! \b UCBxBR0 and \b UCBxBR1 registers
@@ -187,15 +186,15 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
-//! \param slaveAddress 7-bit slave address
+//! \param slaveAddress 7-bit or 10-bit slave address
//! \param slaveAddressOffset Own address Offset referred to- 'x' value of
//! UCBxI2COAx. Valid values are:
//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0,
@@ -231,10 +230,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -253,10 +252,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -275,15 +274,15 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
//!
-//! \param slaveAddress 7-bit slave address
+//! \param slaveAddress 7-bit or 10-bit slave address
//!
//! This function will set the address that the I2C Master will place on the
//! bus when initiating a transaction.
@@ -301,10 +300,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -328,10 +327,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -353,10 +352,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -378,10 +377,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -401,10 +400,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -426,10 +425,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -456,10 +455,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -488,10 +487,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -518,10 +517,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -549,10 +548,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -577,10 +576,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -607,10 +606,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -637,10 +636,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -668,10 +667,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -696,10 +695,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -725,10 +724,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -750,10 +749,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -775,10 +774,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -802,10 +801,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -833,10 +832,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -857,10 +856,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -885,10 +884,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -908,10 +907,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -931,10 +930,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -954,10 +953,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -979,10 +978,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1003,10 +1002,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1027,10 +1026,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1053,10 +1052,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1079,10 +1078,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1126,10 +1125,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1173,10 +1172,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1203,10 +1202,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1250,7 +1249,7 @@
//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable
//
//*****************************************************************************
-uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask);
+extern uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask);
//*****************************************************************************
//
@@ -1260,10 +1259,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1295,10 +1294,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1327,10 +1326,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! <br>It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -1347,6 +1346,26 @@
//*****************************************************************************
extern void I2C_unregisterInterrupt(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! This function is used by the slave to send a NAK out over the I2C line
+//!
+//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid
+//! parameters vary from part to part, but can include:
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
+//! <br>It is important to note that for eUSCI modules, only "B" modules such as
+//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//! I2C mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void I2C_slaveSendNAK(uint32_t moduleInstance);
+
/* Backwards Compatibility Layer */
#define EUSCI_B_I2C_slaveInit I2C_initSlave
#define EUSCI_B_I2C_enable I2C_enableModule
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
index 84b3d26..41f82eb 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/cmsis_ccs.h
@@ -1,6 +1,6 @@
//*****************************************************************************
//
-// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
+// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -41,12 +41,18 @@
// CMSIS-compatible instruction calls
//*****************************************************************************
+#ifndef __cplusplus
// No Operation
__attribute__( ( always_inline ) ) static inline void __nop(void)
{
__asm(" nop");
}
+__attribute__( ( always_inline ) ) static inline void __NOP(void)
+{
+ __asm(" nop");
+}
+
// Wait For Interrupt
__attribute__( ( always_inline ) ) static inline void __wfi(void)
{
@@ -58,6 +64,7 @@
{
__asm(" wfe");
}
+#endif
// Enable Interrupts
__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
@@ -194,7 +201,7 @@
#define __SMUAD _smuad
#define __SMUADX _smuadx
#define __SMUSD _smusd
-#define __SMUSDX _smusd
+#define __SMUSDX _smusdx
#define __SSAT16 _ssat16
#define __SSUB16 _ssub16
#define __SSUB8 _ssub8
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
index 2c8b088..92db523 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cm4.h
@@ -1,13 +1,10 @@
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
+ * @version V4.20
+ * @date 20. August 2015
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -35,17 +32,21 @@
---------------------------------------------------------------------------*/
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM4_H_GENERIC
#define __CORE_CM4_H_GENERIC
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,107 +69,149 @@
*/
/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x14U) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#elif (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#else
+ #error Unknown compiler
#endif
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
#else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
#endif
#else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
+ #define __FPU_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
#else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
#endif
#else
- #define __FPU_USED 0
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
+ #define __FPU_USED 0U
#endif
#else
- #define __FPU_USED 0
+ #define __FPU_USED 0U
#endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
#endif
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
#endif /* __CORE_CM4_H_GENERIC */
@@ -177,30 +220,34 @@
#ifndef __CORE_CM4_H_DEPENDANT
#define __CORE_CM4_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM4_REV
- #define __CM4_REV 0x0000
+ #define __CM4_REV 0x0000U
#warning "__CM4_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
+ #define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
+ #define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
+ #define __NVIC_PRIO_BITS 4U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
+ #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
@@ -214,12 +261,17 @@
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
+ #define __I volatile /*!< Defines 'read only' permissions */
#else
- #define __I volatile const /*!< Defines 'read only' permissions */
+ #define __I volatile const /*!< Defines 'read only' permissions */
#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M4 */
@@ -252,22 +304,37 @@
{
struct
{
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -275,12 +342,16 @@
{
struct
{
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -288,25 +359,49 @@
{
struct
{
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -315,13 +410,23 @@
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
/*@} end of group CMSIS_CORE */
@@ -335,24 +440,24 @@
*/
typedef struct
{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
@@ -367,209 +472,209 @@
*/
typedef struct
{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
@@ -584,30 +689,30 @@
*/
typedef struct
{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
@@ -622,42 +727,42 @@
*/
typedef struct
{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -672,93 +777,93 @@
*/
typedef struct
{
- __O union
+ __OM union
{
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
@@ -773,137 +878,137 @@
*/
typedef struct
{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
@@ -918,150 +1023,150 @@
*/
typedef struct
{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
/*@}*/ /* end of group CMSIS_TPI */
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@@ -1072,89 +1177,89 @@
*/
typedef struct
{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1U)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@@ -1165,96 +1270,96 @@
*/
typedef struct
{
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
} FPU_Type;
/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/*@} end of group CMSIS_FPU */
#endif
@@ -1270,100 +1375,127 @@
*/
typedef struct
{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+* Mask and shift a bit field value for use in a register bit range.
+*
+* \param[in] field Name of the register bit field.
+* \param[in] value Value of the bit field.
+* \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+* Mask and shift a register value to extract a bit filed value.
+*
+* \param[in] field Name of the register bit field.
+* \param[in] value Value of register.
+* \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
@@ -1388,12 +1520,12 @@
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
-#if (__FPU_PRESENT == 1)
+#if (__FPU_PRESENT == 1U)
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#endif
@@ -1435,13 +1567,13 @@
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
@@ -1454,7 +1586,7 @@
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@@ -1466,8 +1598,7 @@
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1479,7 +1610,7 @@
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1495,7 +1626,7 @@
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1507,7 +1638,7 @@
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1519,7 +1650,7 @@
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1534,7 +1665,7 @@
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1549,10 +1680,14 @@
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
}
@@ -1570,10 +1705,14 @@
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
}
@@ -1582,7 +1721,7 @@
The function encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
@@ -1591,16 +1730,16 @@
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
@@ -1610,24 +1749,24 @@
The function decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
@@ -1637,13 +1776,17 @@
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -1657,7 +1800,7 @@
@{
*/
-#if (__Vendor_SysTickConfig == 0)
+#if (__Vendor_SysTickConfig == 0U)
/** \brief System Tick Configuration
@@ -1676,15 +1819,18 @@
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -1701,7 +1847,7 @@
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** \brief ITM Send Character
@@ -1716,11 +1862,14 @@
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
@@ -1733,10 +1882,12 @@
\return Received character.
\return -1 No character pending.
*/
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
int32_t ch = -1; /* no character available */
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
@@ -1754,19 +1905,25 @@
*/
__STATIC_INLINE int32_t ITM_CheckChar (void) {
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
-#endif /* __CORE_CM4_H_DEPENDANT */
-#endif /* __CMSIS_GENERIC */
+
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
index 139bc3c..0e567c0 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmFunc.h
@@ -1,13 +1,10 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
+ * @version V4.20
+ * @date 02. July 2015
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -35,6 +32,12 @@
---------------------------------------------------------------------------*/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
@@ -45,592 +48,33 @@
@{
*/
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
+ #include <cmsis_armcc.h>
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
+#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
+ #include <cmsis_armcc_V6.h>
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
+ #include <cmsis_gcc.h>
-/** \brief Get Control Register
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
+ #include <cmsis_iar.h>
- This function returns the content of the Control Register.
+#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
+ #include <cmsis_ccs.h>
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+ #include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
-
#endif /* __CORE_CMFUNC_H */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
index 8946c2c..f24f30b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmInstr.h
@@ -1,13 +1,10 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V3.20
- * @date 05. March 2013
- *
- * @note
- *
+ * @version V4.20
+ * @date 02. July 2015
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -35,6 +32,12 @@
---------------------------------------------------------------------------*/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
@@ -45,641 +48,30 @@
@{
*/
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
+ #include <cmsis_armcc.h>
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
+#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
+ #include <cmsis_armcc_V6.h>
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
+ #include <cmsis_gcc.h>
-/** \brief No Operation
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
+ #include <cmsis_iar.h>
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
+#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
+ #include <cmsis_ccs.h>
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() __isb(0xF)
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __RBIT __rbit
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+ #include <cmsis_csm.h>
#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmSimd.h
new file mode 100644
index 0000000..30538ac
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/CMSIS/core_cmSimd.h
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.20
+ * @date 02. July 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------ RealView Compiler -----------------*/
+ #include <cmsis_armcc.h>
+
+#elif (__ARMCC_VERSION >= 6010050) /*------------------ ARM Compiler V6 -------------------*/
+ #include <cmsis_armcc_V6.h>
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ----------------------*/
+ #include <cmsis_gcc.h>
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler ----------------------*/
+ #include <cmsis_iar.h>
+
+#elif defined ( __TMS470__ ) /*------------------ TI CCS Compiler -------------------*/
+ #include <cmsis_ccs.h>
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler ------------------*/
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
index 67ff5b0..05db650 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp.h
@@ -32,7 +32,7 @@
//
// MSP432 Family Generic Include File
//
-// File creation date: 2015-01-02
+// File creation date: 2015-10-26
//
//*****************************************************************************
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
index 9f6e1aa..05db650 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432.h
@@ -32,7 +32,7 @@
//
// MSP432 Family Generic Include File
//
-// File creation date: 2015-01-05
+// File creation date: 2015-10-26
//
//*****************************************************************************
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h
index 7bf3e6d..267fca1 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp432p401r.h
@@ -1,77 +1,105 @@
-//*****************************************************************************
-//
-// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//
-// Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the
-// distribution.
-//
-// Neither the name of Texas Instruments Incorporated nor the names of
-// its contributors may be used to endorse or promote products derived
-// from this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// MSP432P401R Register Definitions
-//
-// This file includes definitions that are compatible with MSP430 code,
-// and additionally CMSIS compliant definitions
-//
-// When using MSP430 definitions the physical registers can be directly
-// accessed, e.g.
-// - ADC14CTL0 |= ADC14SSEL__ACLK;
-//
-// When using CMSIS definitions, the register and bit defines have been
-// reformatted and shortened.
-// - Registers: ModuleName[ModuleInstance]->rRegisterName.r
-// - Bits: ModuleName[ModuleInstance]->rRegisterName.b.bBitName
-// - Alternate Bits: ModuleName[ModuleInstance]->rRegisterName.a.bBitName
-//
-// Writing to CMSIS bit fields can be done through both register level
-// access or bit level access, e.g.
-// - ADC14->rCTL0.r |= ADC14SSEL__ACLK;
-// - ADC14->rCTL0.b.bSSEL = ADC14SSEL__ACLK >> ADC14SSEL_OFS;
-//
-// File creation date: 2015-01-05
-//
-//****************************************************************************
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* MSP432P401R Register Definitions
+*
+* This file includes CMSIS compliant component and register definitions
+*
+* For legacy components the definitions that are compatible with MSP430 code,
+* are included with msp432p401r_classic.h
+*
+* With CMSIS definitions, the register defines have been reformatted:
+* ModuleName[ModuleInstance]->RegisterName
+*
+* Writing to CMSIS bit fields can be done through register level
+* or via bitband area access:
+* - ADC14->CTL0 |= ADC14_CTL0_ENC;
+* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1;
+*
+* File creation date: 2015-10-26
+*
+******************************************************************************/
#ifndef __MSP432P401R_H__
#define __MSP432P401R_H__
-// Use standard integer types with explicit width
+/* Use standard integer types with explicit width */
#include <stdint.h>
-// Remap MSP430 intrinsics to ARM equivalents
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __MSP432_HEADER_VERSION__ 2000
+
+/* Remap MSP432 intrinsics to ARM equivalents */
#include "msp_compatibility.h"
-//*****************************************************************************
-// CMSIS-compatible Interrupt Number Definition
-//*****************************************************************************
+/******************************************************************************
+* include MSP430 legacy definitions to make porting of code from MSP430 *
+* code base easier *
+* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in *
+* your project to omit including the classic defines *
+******************************************************************************/
+#ifndef NO_MSP_CLASSIC_DEFINES
+#include "msp432p401r_classic.h"
+#endif
+
#ifndef __CMSIS_CONFIG__
#define __CMSIS_CONFIG__
+/** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions
+ This file defines all structures and symbols for MSP432P401R:
+ - components and registers
+ - peripheral base address
+ - peripheral ID
+ - Peripheral definitions
+ @{
+*/
+
+/******************************************************************************
+* Processor and Core Peripherals *
+******************************************************************************/
+/** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions
+ Configuration of the Cortex-M4 Processor and Core Peripherals
+ @{
+*/
+
+/******************************************************************************
+* CMSIS-compatible Interrupt Number Definition *
+******************************************************************************/
typedef enum IRQn
{
- // Cortex-M4 Processor Exceptions Numbers
+ /* Cortex-M4 Processor Exceptions Numbers */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
@@ -81,7 +109,7 @@
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
- // Peripheral Exceptions Numbers
+ /* Peripheral Exceptions Numbers */
PSS_IRQn = 0, /* 16 PSS Interrupt */
CS_IRQn = 1, /* 17 CS Interrupt */
PCM_IRQn = 2, /* 18 PCM Interrupt */
@@ -125,17 +153,78 @@
PORT6_IRQn = 40 /* 56 PORT6 Interrupt */
} IRQn_Type;
-//*****************************************************************************
-// CMSIS-compatible configuration of the Cortex-M4 Processor and Core Peripherals
-//*****************************************************************************
-#define __MPU_PRESENT 1 // MPU present or not
-#define __NVIC_PRIO_BITS 3 // Number of Bits used for Prio Levels
-#define __FPU_PRESENT 1 // FPU present or not
+/******************************************************************************
+* Processor and Core Peripheral Section *
+******************************************************************************/
+#define __CM4_REV 0x0001 /* Core revision r0p1 */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /* FPU present or not */
-#endif // __CMSIS_CONFIG__
+/******************************************************************************
+* Available Peripherals *
+******************************************************************************/
+#define __MCU_HAS_ADC14__ /**< Module ADC14 is available */
+#define __MCU_HAS_AES256__ /**< Module AES256 is available */
+#define __MCU_HAS_CAPTIO0__ /**< Module CAPTIO0 is available */
+#define __MCU_HAS_CAPTIO1__ /**< Module CAPTIO1 is available */
+#define __MCU_HAS_COMP_E0__ /**< Module COMP_E0 is available */
+#define __MCU_HAS_COMP_E1__ /**< Module COMP_E1 is available */
+#define __MCU_HAS_CRC32__ /**< Module CRC32 is available */
+#define __MCU_HAS_CS__ /**< Module CS is available */
+#define __MCU_HAS_DIO__ /**< Module DIO is available */
+#define __MCU_HAS_DMA__ /**< Module DMA is available */
+#define __MCU_HAS_EUSCI_A0__ /**< Module EUSCI_A0 is available */
+#define __MCU_HAS_EUSCI_A1__ /**< Module EUSCI_A1 is available */
+#define __MCU_HAS_EUSCI_A2__ /**< Module EUSCI_A2 is available */
+#define __MCU_HAS_EUSCI_A3__ /**< Module EUSCI_A3 is available */
+#define __MCU_HAS_EUSCI_B0__ /**< Module EUSCI_B0 is available */
+#define __MCU_HAS_EUSCI_B1__ /**< Module EUSCI_B1 is available */
+#define __MCU_HAS_EUSCI_B2__ /**< Module EUSCI_B2 is available */
+#define __MCU_HAS_EUSCI_B3__ /**< Module EUSCI_B3 is available */
+#define __MCU_HAS_FLCTL__ /**< Module FLCTL is available */
+#define __MCU_HAS_PCM__ /**< Module PCM is available */
+#define __MCU_HAS_PMAP__ /**< Module PMAP is available */
+#define __MCU_HAS_PSS__ /**< Module PSS is available */
+#define __MCU_HAS_REF_A__ /**< Module REF_A is available */
+#define __MCU_HAS_RSTCTL__ /**< Module RSTCTL is available */
+#define __MCU_HAS_RTC_C__ /**< Module RTC_C is available */
+#define __MCU_HAS_SYSCTL__ /**< Module SYSCTL is available */
+#define __MCU_HAS_TIMER32__ /**< Module TIMER32 is available */
+#define __MCU_HAS_TIMER_A0__ /**< Module TIMER_A0 is available */
+#define __MCU_HAS_TIMER_A1__ /**< Module TIMER_A1 is available */
+#define __MCU_HAS_TIMER_A2__ /**< Module TIMER_A2 is available */
+#define __MCU_HAS_TIMER_A3__ /**< Module TIMER_A3 is available */
+#define __MCU_HAS_TLV__ /**< Module TLV is available */
+#define __MCU_HAS_WDT_A__ /**< Module WDT_A is available */
-// Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File
-#ifdef __TMS470__
+/* Definitions to show that specific ports are available */
+
+#define __MSP432_HAS_PORTA_R__
+#define __MSP432_HAS_PORTB_R__
+#define __MSP432_HAS_PORTC_R__
+#define __MSP432_HAS_PORTD_R__
+#define __MSP432_HAS_PORTE_R__
+#define __MSP432_HAS_PORTJ_R__
+
+#define __MSP432_HAS_PORT1_R__
+#define __MSP432_HAS_PORT2_R__
+#define __MSP432_HAS_PORT3_R__
+#define __MSP432_HAS_PORT4_R__
+#define __MSP432_HAS_PORT5_R__
+#define __MSP432_HAS_PORT6_R__
+#define __MSP432_HAS_PORT7_R__
+#define __MSP432_HAS_PORT8_R__
+#define __MSP432_HAS_PORT9_R__
+#define __MSP432_HAS_PORT10_R__
+
+
+/*@}*/ /* end of group MSP432P401R_CMSIS */
+
+/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */
+#ifdef __TI_ARM__
+/* disable the TI ULP advisor check for the core header file definitions */
#pragma diag_push
#pragma CHECK_ULP("none")
#include "core_cm4.h"
@@ -144,17900 +233,6529 @@
#include "core_cm4.h"
#endif
-//*****************************************************************************
-// Definition of standard bits
-//*****************************************************************************
-#define BIT0 (0x0001u)
-#define BIT1 (0x0002u)
-#define BIT2 (0x0004u)
-#define BIT3 (0x0008u)
-#define BIT4 (0x0010u)
-#define BIT5 (0x0020u)
-#define BIT6 (0x0040u)
-#define BIT7 (0x0080u)
-#define BIT8 (0x0100u)
-#define BIT9 (0x0200u)
-#define BITA (0x0400u)
-#define BITB (0x0800u)
-#define BITC (0x1000u)
-#define BITD (0x2000u)
-#define BITE (0x4000u)
-#define BITF (0x8000u)
-#define BIT(x) (1 << (x))
+/* System Header */
+#include "system_msp432p401r.h"
-//*****************************************************************************
-// Definitions for 8/16/32-bit wide memory access
-//*****************************************************************************
-#define HWREG8(x) (*((volatile uint8_t *)(x)))
-#define HWREG16(x) (*((volatile uint16_t *)(x)))
-#define HWREG32(x) (*((volatile uint32_t *)(x)))
-#define HWREG(x) (HWREG16(x))
-#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
-#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
-#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
-#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
+/******************************************************************************
+* Definition of standard bits *
+******************************************************************************/
+#define BIT0 (uint16_t)(0x0001)
+#define BIT1 (uint16_t)(0x0002)
+#define BIT2 (uint16_t)(0x0004)
+#define BIT3 (uint16_t)(0x0008)
+#define BIT4 (uint16_t)(0x0010)
+#define BIT5 (uint16_t)(0x0020)
+#define BIT6 (uint16_t)(0x0040)
+#define BIT7 (uint16_t)(0x0080)
+#define BIT8 (uint16_t)(0x0100)
+#define BIT9 (uint16_t)(0x0200)
+#define BITA (uint16_t)(0x0400)
+#define BITB (uint16_t)(0x0800)
+#define BITC (uint16_t)(0x1000)
+#define BITD (uint16_t)(0x2000)
+#define BITE (uint16_t)(0x4000)
+#define BITF (uint16_t)(0x8000)
+#define BIT(x) ((uint16_t)1 << (x))
-//*****************************************************************************
-// Definitions for 8/16/32-bit wide bit band access
-//*****************************************************************************
-#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
-#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
-#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
-#define BITBAND_SRAM(x, b) (*((volatile uint8_t *) (0x22000000 + (((uint32_t)(uint32_t *)&x) - 0x20000000)*32 + b*4)))
-#define BITBAND_PERI(x, b) (*((volatile uint8_t *) (0x42000000 + (((uint32_t)(uint32_t *)&x) - 0x40000000)*32 + b*4)))
+/******************************************************************************
+* Device and peripheral memory map *
+******************************************************************************/
+/** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping
+ @{
+*/
-//*****************************************************************************
-// Device memory map
-//*****************************************************************************
-#define __MAIN_MEMORY_START__ (0x00000000) /* Main Flash memory start address */
-#define __MAIN_MEMORY_END__ (0x0003FFFF) /* Main Flash memory end address */
-#define __BSL_MEMORY_START__ (0x00202000) /* BSL memory start address */
-#define __BSL_MEMORY_END__ (0x00203FFF) /* BSL memory end address */
-#define __SRAM_START__ (0x20000000) /* SRAM memory start address */
-#define __SRAM_END__ (0x2000FFFF) /* SRAM memory end address */
+#define FLASH_BASE ((uint32_t)0x00000000) /**< Main Flash memory start address */
+#define SRAM_BASE ((uint32_t)0x20000000) /**< SRAM memory start address */
+#define PERIPH_BASE ((uint32_t)0x40000000) /**< Peripherals start address */
+#define PERIPH_BASE2 ((uint32_t)0xE0000000) /**< Peripherals start address */
-//*****************************************************************************
-// Peripheral memory map
-//*****************************************************************************
-#define __MCU_HAS_ADC14__ /* Module is available */
-#define __MCU_HAS_AES256__ /* Module is available */
-#define __MCU_HAS_CAPTIO0__ /* Module is available */
-#define __MCU_HAS_CAPTIO1__ /* Module is available */
-#define __MCU_HAS_COMP_E0__ /* Module is available */
-#define __MCU_HAS_COMP_E1__ /* Module is available */
-#define __MCU_HAS_CRC32__ /* Module is available */
-#define __MCU_HAS_CS__ /* Module is available */
-#define __MCU_HAS_DIO__ /* Module is available */
-#define __MCU_HAS_DMA__ /* Module is available */
-#define __MCU_HAS_EUSCI_A0__ /* Module is available */
-#define __MCU_HAS_EUSCI_A1__ /* Module is available */
-#define __MCU_HAS_EUSCI_A2__ /* Module is available */
-#define __MCU_HAS_EUSCI_A3__ /* Module is available */
-#define __MCU_HAS_EUSCI_B0__ /* Module is available */
-#define __MCU_HAS_EUSCI_B1__ /* Module is available */
-#define __MCU_HAS_EUSCI_B2__ /* Module is available */
-#define __MCU_HAS_EUSCI_B3__ /* Module is available */
-#define __MCU_HAS_FLCTL__ /* Module is available */
-#define __MCU_HAS_FPB__ /* Module is available */
-#define __MCU_HAS_PCM__ /* Module is available */
-#define __MCU_HAS_PMAP__ /* Module is available */
-#define __MCU_HAS_PSS__ /* Module is available */
-#define __MCU_HAS_REF_A__ /* Module is available */
-#define __MCU_HAS_RSTCTL__ /* Module is available */
-#define __MCU_HAS_RTC_C__ /* Module is available */
-#define __MCU_HAS_SYSCTL__ /* Module is available */
-#define __MCU_HAS_TIMER32__ /* Module is available */
-#define __MCU_HAS_TIMER_A0__ /* Module is available */
-#define __MCU_HAS_TIMER_A1__ /* Module is available */
-#define __MCU_HAS_TIMER_A2__ /* Module is available */
-#define __MCU_HAS_TIMER_A3__ /* Module is available */
-#define __MCU_HAS_TLV__ /* Module is available */
-#define __MCU_HAS_WDT_A__ /* Module is available */
+#define ADC14_BASE (PERIPH_BASE +0x00012000) /**< Base address of module ADC14 registers */
+#define AES256_BASE (PERIPH_BASE +0x00003C00) /**< Base address of module AES256 registers */
+#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /**< Base address of module CAPTIO0 registers */
+#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /**< Base address of module CAPTIO1 registers */
+#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /**< Base address of module COMP_E0 registers */
+#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /**< Base address of module COMP_E1 registers */
+#define CRC32_BASE (PERIPH_BASE +0x00004000) /**< Base address of module CRC32 registers */
+#define CS_BASE (PERIPH_BASE +0x00010400) /**< Base address of module CS registers */
+#define DIO_BASE (PERIPH_BASE +0x00004C00) /**< Base address of module DIO registers */
+#define DMA_BASE (PERIPH_BASE +0x0000E000) /**< Base address of module DMA registers */
+#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /**< Base address of module EUSCI_A0 registers */
+#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /**< Base address of module EUSCI_A0 registers */
+#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /**< Base address of module EUSCI_A1 registers */
+#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /**< Base address of module EUSCI_A1 registers */
+#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /**< Base address of module EUSCI_A2 registers */
+#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /**< Base address of module EUSCI_A2 registers */
+#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /**< Base address of module EUSCI_A3 registers */
+#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /**< Base address of module EUSCI_A3 registers */
+#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /**< Base address of module EUSCI_B0 registers */
+#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /**< Base address of module EUSCI_B0 registers */
+#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /**< Base address of module EUSCI_B1 registers */
+#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /**< Base address of module EUSCI_B1 registers */
+#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /**< Base address of module EUSCI_B2 registers */
+#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /**< Base address of module EUSCI_B2 registers */
+#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /**< Base address of module EUSCI_B3 registers */
+#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /**< Base address of module EUSCI_B3 registers */
+#define FLCTL_BASE (PERIPH_BASE +0x00011000) /**< Base address of module FLCTL registers */
+#define PCM_BASE (PERIPH_BASE +0x00010000) /**< Base address of module PCM registers */
+#define PMAP_BASE (PERIPH_BASE +0x00005000) /**< Base address of module PMAP registers */
+#define PSS_BASE (PERIPH_BASE +0x00010800) /**< Base address of module PSS registers */
+#define REF_A_BASE (PERIPH_BASE +0x00003000) /**< Base address of module REF_A registers */
+#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /**< Base address of module RSTCTL registers */
+#define RTC_C_BASE (PERIPH_BASE +0x00004400) /**< Base address of module RTC_C registers */
+#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /**< Base address of module RTC_C registers */
+#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /**< Base address of module SYSCTL registers */
+#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /**< Base address of module TIMER32 registers */
+#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /**< Base address of module TIMER_A0 registers */
+#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /**< Base address of module TIMER_A1 registers */
+#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /**< Base address of module TIMER_A2 registers */
+#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /**< Base address of module TIMER_A3 registers */
+#define TLV_BASE ((uint32_t)0x00201000) /**< Base address of module TLV registers */
+#define WDT_A_BASE (PERIPH_BASE +0x00004800) /**< Base address of module WDT_A registers */
-#define ADC14_BASE (0x40012000) /* Base address of module registers */
-#define ADC14_MODULE (0x40012000) /* Base address of module registers */
-#define AES256_BASE (0x40003C00) /* Base address of module registers */
-#define AES256_MODULE (0x40003C00) /* Base address of module registers */
-#define CAPTIO0_BASE (0x40005400) /* Base address of module registers */
-#define CAPTIO0_MODULE (0x40005400) /* Base address of module registers */
-#define CAPTIO1_BASE (0x40005800) /* Base address of module registers */
-#define CAPTIO1_MODULE (0x40005800) /* Base address of module registers */
-#define COMP_E0_BASE (0x40003400) /* Base address of module registers */
-#define COMP_E0_MODULE (0x40003400) /* Base address of module registers */
-#define COMP_E1_BASE (0x40003800) /* Base address of module registers */
-#define COMP_E1_MODULE (0x40003800) /* Base address of module registers */
-#define CRC32_BASE (0x40004000) /* Base address of module registers */
-#define CRC32_MODULE (0x40004000) /* Base address of module registers */
-#define CS_BASE (0x40010400) /* Base address of module registers */
-#define CS_MODULE (0x40010400) /* Base address of module registers */
-#define DIO_BASE (0x40004C00) /* Base address of module registers */
-#define DIO_MODULE (0x40004C00) /* Base address of module registers */
-#define DMA_BASE (0x4000E000) /* Base address of module registers */
-#define DMA_MODULE (0x4000E000) /* Base address of module registers */
-#define EUSCI_A0_BASE (0x40001000) /* Base address of module registers */
-#define EUSCI_A0_MODULE (0x40001000) /* Base address of module registers */
-#define EUSCI_A1_BASE (0x40001400) /* Base address of module registers */
-#define EUSCI_A1_MODULE (0x40001400) /* Base address of module registers */
-#define EUSCI_A2_BASE (0x40001800) /* Base address of module registers */
-#define EUSCI_A2_MODULE (0x40001800) /* Base address of module registers */
-#define EUSCI_A3_BASE (0x40001C00) /* Base address of module registers */
-#define EUSCI_A3_MODULE (0x40001C00) /* Base address of module registers */
-#define EUSCI_B0_BASE (0x40002000) /* Base address of module registers */
-#define EUSCI_B0_MODULE (0x40002000) /* Base address of module registers */
-#define EUSCI_B1_BASE (0x40002400) /* Base address of module registers */
-#define EUSCI_B1_MODULE (0x40002400) /* Base address of module registers */
-#define EUSCI_B2_BASE (0x40002800) /* Base address of module registers */
-#define EUSCI_B2_MODULE (0x40002800) /* Base address of module registers */
-#define EUSCI_B3_BASE (0x40002C00) /* Base address of module registers */
-#define EUSCI_B3_MODULE (0x40002C00) /* Base address of module registers */
-#define FLCTL_BASE (0x40011000) /* Base address of module registers */
-#define FLCTL_MODULE (0x40011000) /* Base address of module registers */
-#define FPB_BASE (0xE0002000) /* Base address of module registers */
-#define FPB_MODULE (0xE0002000) /* Base address of module registers */
-#define PCM_BASE (0x40010000) /* Base address of module registers */
-#define PCM_MODULE (0x40010000) /* Base address of module registers */
-#define PMAP_BASE (0x40005000) /* Base address of module registers */
-#define PMAP_MODULE (0x40005000) /* Base address of module registers */
-#define PSS_BASE (0x40010800) /* Base address of module registers */
-#define PSS_MODULE (0x40010800) /* Base address of module registers */
-#define REF_A_BASE (0x40003000) /* Base address of module registers */
-#define REF_A_MODULE (0x40003000) /* Base address of module registers */
-#define RSTCTL_BASE (0xE0042000) /* Base address of module registers */
-#define RSTCTL_MODULE (0xE0042000) /* Base address of module registers */
-#define RTC_C_BASE (0x40004400) /* Base address of module registers */
-#define RTC_C_MODULE (0x40004400) /* Base address of module registers */
-#define SYSCTL_BASE (0xE0043000) /* Base address of module registers */
-#define SYSCTL_MODULE (0xE0043000) /* Base address of module registers */
-#define TIMER32_BASE (0x4000C000) /* Base address of module registers */
-#define TIMER32_MODULE (0x4000C000) /* Base address of module registers */
-#define TIMER_A0_BASE (0x40000000) /* Base address of module registers */
-#define TIMER_A0_MODULE (0x40000000) /* Base address of module registers */
-#define TIMER_A1_BASE (0x40000400) /* Base address of module registers */
-#define TIMER_A1_MODULE (0x40000400) /* Base address of module registers */
-#define TIMER_A2_BASE (0x40000800) /* Base address of module registers */
-#define TIMER_A2_MODULE (0x40000800) /* Base address of module registers */
-#define TIMER_A3_BASE (0x40000C00) /* Base address of module registers */
-#define TIMER_A3_MODULE (0x40000C00) /* Base address of module registers */
-#define TLV_BASE (0x00201000) /* Base address of module registers */
-#define TLV_MODULE (0x00201000) /* Base address of module registers */
-#define WDT_A_BASE (0x40004800) /* Base address of module registers */
-#define WDT_A_MODULE (0x40004800) /* Base address of module registers */
-#define ADC14 ((ADC14_Type *) ADC14_BASE)
-#define AES256 ((AES256_Type *) AES256_BASE)
-#define CAPTIO0 ((CAPTIO0_Type *) CAPTIO0_BASE)
-#define CAPTIO1 ((CAPTIO1_Type *) CAPTIO1_BASE)
-#define COMP_E0 ((COMP_E0_Type *) COMP_E0_BASE)
-#define COMP_E1 ((COMP_E1_Type *) COMP_E1_BASE)
-#define CRC32 ((CRC32_Type *) CRC32_BASE)
-#define CS ((CS_Type *) CS_BASE)
-#define DIO ((DIO_Type *) DIO_BASE)
-#define DMA ((DMA_Type *) DMA_BASE)
-#define EUSCI_A0 ((EUSCI_A0_Type *) EUSCI_A0_BASE)
-#define EUSCI_A1 ((EUSCI_A1_Type *) EUSCI_A1_BASE)
-#define EUSCI_A2 ((EUSCI_A2_Type *) EUSCI_A2_BASE)
-#define EUSCI_A3 ((EUSCI_A3_Type *) EUSCI_A3_BASE)
-#define EUSCI_B0 ((EUSCI_B0_Type *) EUSCI_B0_BASE)
-#define EUSCI_B1 ((EUSCI_B1_Type *) EUSCI_B1_BASE)
-#define EUSCI_B2 ((EUSCI_B2_Type *) EUSCI_B2_BASE)
-#define EUSCI_B3 ((EUSCI_B3_Type *) EUSCI_B3_BASE)
-#define FLCTL ((FLCTL_Type *) FLCTL_BASE)
-#define FPB ((FPB_Type *) FPB_BASE)
-#define PCM ((PCM_Type *) PCM_BASE)
-#define PMAP ((PMAP_Type *) PMAP_BASE)
-#define PSS ((PSS_Type *) PSS_BASE)
-#define REF_A ((REF_A_Type *) REF_A_BASE)
-#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE)
-#define RTC_C ((RTC_C_Type *) RTC_C_BASE)
-#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE)
-#define TIMER32 ((TIMER32_Type *) TIMER32_BASE)
-#define TIMER_A0 ((TIMER_A0_Type *) TIMER_A0_BASE)
-#define TIMER_A1 ((TIMER_A1_Type *) TIMER_A1_BASE)
-#define TIMER_A2 ((TIMER_A2_Type *) TIMER_A2_BASE)
-#define TIMER_A3 ((TIMER_A3_Type *) TIMER_A3_BASE)
-#define TLV ((TLV_Type *) TLV_BASE)
-#define WDT_A ((WDT_A_Type *) WDT_A_BASE)
+/*@}*/ /* end of group MSP432P401R_MemoryMap */
+/******************************************************************************
+* Definitions for bit band access *
+******************************************************************************/
+#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000))
+#define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
-//*****************************************************************************
-// MSP-format peripheral registers
-//*****************************************************************************
+/* SRAM allows 32 bit bit band access */
+#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&x) - SRAM_BASE )*32 + b*4)))
+/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */
+#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&x) - PERIPH_BASE)*32 + b*4)))
-//*****************************************************************************
-// ADC14 Registers
-//*****************************************************************************
-#define ADC14CTL0 (HWREG32(0x40012000)) /* Control 0 Register */
-#define ADC14CTL1 (HWREG32(0x40012004)) /* Control 1 Register */
-#define ADC14LO0 (HWREG32(0x40012008)) /* Window Comparator Low Threshold 0 Register */
-#define ADC14HI0 (HWREG32(0x4001200C)) /* Window Comparator High Threshold 0 Register */
-#define ADC14LO1 (HWREG32(0x40012010)) /* Window Comparator Low Threshold 1 Register */
-#define ADC14HI1 (HWREG32(0x40012014)) /* Window Comparator High Threshold 1 Register */
-#define ADC14MCTL0 (HWREG32(0x40012018)) /* Conversion Memory Control Register */
-#define ADC14MCTL1 (HWREG32(0x4001201C)) /* Conversion Memory Control Register */
-#define ADC14MCTL2 (HWREG32(0x40012020)) /* Conversion Memory Control Register */
-#define ADC14MCTL3 (HWREG32(0x40012024)) /* Conversion Memory Control Register */
-#define ADC14MCTL4 (HWREG32(0x40012028)) /* Conversion Memory Control Register */
-#define ADC14MCTL5 (HWREG32(0x4001202C)) /* Conversion Memory Control Register */
-#define ADC14MCTL6 (HWREG32(0x40012030)) /* Conversion Memory Control Register */
-#define ADC14MCTL7 (HWREG32(0x40012034)) /* Conversion Memory Control Register */
-#define ADC14MCTL8 (HWREG32(0x40012038)) /* Conversion Memory Control Register */
-#define ADC14MCTL9 (HWREG32(0x4001203C)) /* Conversion Memory Control Register */
-#define ADC14MCTL10 (HWREG32(0x40012040)) /* Conversion Memory Control Register */
-#define ADC14MCTL11 (HWREG32(0x40012044)) /* Conversion Memory Control Register */
-#define ADC14MCTL12 (HWREG32(0x40012048)) /* Conversion Memory Control Register */
-#define ADC14MCTL13 (HWREG32(0x4001204C)) /* Conversion Memory Control Register */
-#define ADC14MCTL14 (HWREG32(0x40012050)) /* Conversion Memory Control Register */
-#define ADC14MCTL15 (HWREG32(0x40012054)) /* Conversion Memory Control Register */
-#define ADC14MCTL16 (HWREG32(0x40012058)) /* Conversion Memory Control Register */
-#define ADC14MCTL17 (HWREG32(0x4001205C)) /* Conversion Memory Control Register */
-#define ADC14MCTL18 (HWREG32(0x40012060)) /* Conversion Memory Control Register */
-#define ADC14MCTL19 (HWREG32(0x40012064)) /* Conversion Memory Control Register */
-#define ADC14MCTL20 (HWREG32(0x40012068)) /* Conversion Memory Control Register */
-#define ADC14MCTL21 (HWREG32(0x4001206C)) /* Conversion Memory Control Register */
-#define ADC14MCTL22 (HWREG32(0x40012070)) /* Conversion Memory Control Register */
-#define ADC14MCTL23 (HWREG32(0x40012074)) /* Conversion Memory Control Register */
-#define ADC14MCTL24 (HWREG32(0x40012078)) /* Conversion Memory Control Register */
-#define ADC14MCTL25 (HWREG32(0x4001207C)) /* Conversion Memory Control Register */
-#define ADC14MCTL26 (HWREG32(0x40012080)) /* Conversion Memory Control Register */
-#define ADC14MCTL27 (HWREG32(0x40012084)) /* Conversion Memory Control Register */
-#define ADC14MCTL28 (HWREG32(0x40012088)) /* Conversion Memory Control Register */
-#define ADC14MCTL29 (HWREG32(0x4001208C)) /* Conversion Memory Control Register */
-#define ADC14MCTL30 (HWREG32(0x40012090)) /* Conversion Memory Control Register */
-#define ADC14MCTL31 (HWREG32(0x40012094)) /* Conversion Memory Control Register */
-#define ADC14MEM0 (HWREG32(0x40012098)) /* Conversion Memory Register */
-#define ADC14MEM1 (HWREG32(0x4001209C)) /* Conversion Memory Register */
-#define ADC14MEM2 (HWREG32(0x400120A0)) /* Conversion Memory Register */
-#define ADC14MEM3 (HWREG32(0x400120A4)) /* Conversion Memory Register */
-#define ADC14MEM4 (HWREG32(0x400120A8)) /* Conversion Memory Register */
-#define ADC14MEM5 (HWREG32(0x400120AC)) /* Conversion Memory Register */
-#define ADC14MEM6 (HWREG32(0x400120B0)) /* Conversion Memory Register */
-#define ADC14MEM7 (HWREG32(0x400120B4)) /* Conversion Memory Register */
-#define ADC14MEM8 (HWREG32(0x400120B8)) /* Conversion Memory Register */
-#define ADC14MEM9 (HWREG32(0x400120BC)) /* Conversion Memory Register */
-#define ADC14MEM10 (HWREG32(0x400120C0)) /* Conversion Memory Register */
-#define ADC14MEM11 (HWREG32(0x400120C4)) /* Conversion Memory Register */
-#define ADC14MEM12 (HWREG32(0x400120C8)) /* Conversion Memory Register */
-#define ADC14MEM13 (HWREG32(0x400120CC)) /* Conversion Memory Register */
-#define ADC14MEM14 (HWREG32(0x400120D0)) /* Conversion Memory Register */
-#define ADC14MEM15 (HWREG32(0x400120D4)) /* Conversion Memory Register */
-#define ADC14MEM16 (HWREG32(0x400120D8)) /* Conversion Memory Register */
-#define ADC14MEM17 (HWREG32(0x400120DC)) /* Conversion Memory Register */
-#define ADC14MEM18 (HWREG32(0x400120E0)) /* Conversion Memory Register */
-#define ADC14MEM19 (HWREG32(0x400120E4)) /* Conversion Memory Register */
-#define ADC14MEM20 (HWREG32(0x400120E8)) /* Conversion Memory Register */
-#define ADC14MEM21 (HWREG32(0x400120EC)) /* Conversion Memory Register */
-#define ADC14MEM22 (HWREG32(0x400120F0)) /* Conversion Memory Register */
-#define ADC14MEM23 (HWREG32(0x400120F4)) /* Conversion Memory Register */
-#define ADC14MEM24 (HWREG32(0x400120F8)) /* Conversion Memory Register */
-#define ADC14MEM25 (HWREG32(0x400120FC)) /* Conversion Memory Register */
-#define ADC14MEM26 (HWREG32(0x40012100)) /* Conversion Memory Register */
-#define ADC14MEM27 (HWREG32(0x40012104)) /* Conversion Memory Register */
-#define ADC14MEM28 (HWREG32(0x40012108)) /* Conversion Memory Register */
-#define ADC14MEM29 (HWREG32(0x4001210C)) /* Conversion Memory Register */
-#define ADC14MEM30 (HWREG32(0x40012110)) /* Conversion Memory Register */
-#define ADC14MEM31 (HWREG32(0x40012114)) /* Conversion Memory Register */
-#define ADC14IER0 (HWREG32(0x4001213C)) /* Interrupt Enable 0 Register */
-#define ADC14IER1 (HWREG32(0x40012140)) /* Interrupt Enable 1 Register */
-#define ADC14IFGR0 (HWREG32(0x40012144)) /* Interrupt Flag 0 Register */
-#define ADC14IFGR1 (HWREG32(0x40012148)) /* Interrupt Flag 1 Register */
-#define ADC14CLRIFGR0 (HWREG32(0x4001214C)) /* Clear Interrupt Flag 0 Register */
-#define ADC14CLRIFGR1 (HWREG32(0x40012150)) /* Clear Interrupt Flag 1 Register */
-#define ADC14IV (HWREG32(0x40012154)) /* Interrupt Vector Register */
+/******************************************************************************
+* Peripheral register definitions *
+******************************************************************************/
+/** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals
+ MSP432P401R Device Specific Peripheral registers structures
+ @{
+*/
-/* Register offsets from ADC14_BASE address */
-#define OFS_ADC14CTL0 (0x00000000) /* Control 0 Register */
-#define OFS_ADC14CTL1 (0x00000004) /* Control 1 Register */
-#define OFS_ADC14LO0 (0x00000008) /* Window Comparator Low Threshold 0 Register */
-#define OFS_ADC14HI0 (0x0000000c) /* Window Comparator High Threshold 0 Register */
-#define OFS_ADC14LO1 (0x00000010) /* Window Comparator Low Threshold 1 Register */
-#define OFS_ADC14HI1 (0x00000014) /* Window Comparator High Threshold 1 Register */
-#define OFS_ADC14MCTL0 (0x00000018) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL1 (0x0000001C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL2 (0x00000020) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL3 (0x00000024) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL4 (0x00000028) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL5 (0x0000002C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL6 (0x00000030) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL7 (0x00000034) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL8 (0x00000038) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL9 (0x0000003C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL10 (0x00000040) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL11 (0x00000044) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL12 (0x00000048) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL13 (0x0000004C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL14 (0x00000050) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL15 (0x00000054) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL16 (0x00000058) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL17 (0x0000005C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL18 (0x00000060) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL19 (0x00000064) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL20 (0x00000068) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL21 (0x0000006C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL22 (0x00000070) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL23 (0x00000074) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL24 (0x00000078) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL25 (0x0000007C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL26 (0x00000080) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL27 (0x00000084) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL28 (0x00000088) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL29 (0x0000008C) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL30 (0x00000090) /* Conversion Memory Control Register */
-#define OFS_ADC14MCTL31 (0x00000094) /* Conversion Memory Control Register */
-#define OFS_ADC14MEM0 (0x00000098) /* Conversion Memory Register */
-#define OFS_ADC14MEM1 (0x0000009C) /* Conversion Memory Register */
-#define OFS_ADC14MEM2 (0x000000A0) /* Conversion Memory Register */
-#define OFS_ADC14MEM3 (0x000000A4) /* Conversion Memory Register */
-#define OFS_ADC14MEM4 (0x000000A8) /* Conversion Memory Register */
-#define OFS_ADC14MEM5 (0x000000AC) /* Conversion Memory Register */
-#define OFS_ADC14MEM6 (0x000000B0) /* Conversion Memory Register */
-#define OFS_ADC14MEM7 (0x000000B4) /* Conversion Memory Register */
-#define OFS_ADC14MEM8 (0x000000B8) /* Conversion Memory Register */
-#define OFS_ADC14MEM9 (0x000000BC) /* Conversion Memory Register */
-#define OFS_ADC14MEM10 (0x000000C0) /* Conversion Memory Register */
-#define OFS_ADC14MEM11 (0x000000C4) /* Conversion Memory Register */
-#define OFS_ADC14MEM12 (0x000000C8) /* Conversion Memory Register */
-#define OFS_ADC14MEM13 (0x000000CC) /* Conversion Memory Register */
-#define OFS_ADC14MEM14 (0x000000D0) /* Conversion Memory Register */
-#define OFS_ADC14MEM15 (0x000000D4) /* Conversion Memory Register */
-#define OFS_ADC14MEM16 (0x000000D8) /* Conversion Memory Register */
-#define OFS_ADC14MEM17 (0x000000DC) /* Conversion Memory Register */
-#define OFS_ADC14MEM18 (0x000000E0) /* Conversion Memory Register */
-#define OFS_ADC14MEM19 (0x000000E4) /* Conversion Memory Register */
-#define OFS_ADC14MEM20 (0x000000E8) /* Conversion Memory Register */
-#define OFS_ADC14MEM21 (0x000000EC) /* Conversion Memory Register */
-#define OFS_ADC14MEM22 (0x000000F0) /* Conversion Memory Register */
-#define OFS_ADC14MEM23 (0x000000F4) /* Conversion Memory Register */
-#define OFS_ADC14MEM24 (0x000000F8) /* Conversion Memory Register */
-#define OFS_ADC14MEM25 (0x000000FC) /* Conversion Memory Register */
-#define OFS_ADC14MEM26 (0x00000100) /* Conversion Memory Register */
-#define OFS_ADC14MEM27 (0x00000104) /* Conversion Memory Register */
-#define OFS_ADC14MEM28 (0x00000108) /* Conversion Memory Register */
-#define OFS_ADC14MEM29 (0x0000010C) /* Conversion Memory Register */
-#define OFS_ADC14MEM30 (0x00000110) /* Conversion Memory Register */
-#define OFS_ADC14MEM31 (0x00000114) /* Conversion Memory Register */
-#define OFS_ADC14IER0 (0x0000013c) /* Interrupt Enable 0 Register */
-#define OFS_ADC14IER1 (0x00000140) /* Interrupt Enable 1 Register */
-#define OFS_ADC14IFGR0 (0x00000144) /* Interrupt Flag 0 Register */
-#define OFS_ADC14IFGR1 (0x00000148) /* Interrupt Flag 1 Register */
-#define OFS_ADC14CLRIFGR0 (0x0000014c) /* Clear Interrupt Flag 0 Register */
-#define OFS_ADC14CLRIFGR1 (0x00000150) /* Clear Interrupt Flag 1 Register */
-#define OFS_ADC14IV (0x00000154) /* Interrupt Vector Register */
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
-//*****************************************************************************
-// AES256 Registers
-//*****************************************************************************
-#define AESACTL0 (HWREG16(0x40003C00)) /* AES Accelerator Control Register 0 */
-#define AESACTL1 (HWREG16(0x40003C02)) /* AES Accelerator Control Register 1 */
-#define AESASTAT (HWREG16(0x40003C04)) /* AES Accelerator Status Register */
-#define AESAKEY (HWREG16(0x40003C06)) /* AES Accelerator Key Register */
-#define AESADIN (HWREG16(0x40003C08)) /* AES Accelerator Data In Register */
-#define AESADOUT (HWREG16(0x40003C0A)) /* AES Accelerator Data Out Register */
-#define AESAXDIN (HWREG16(0x40003C0C)) /* AES Accelerator XORed Data In Register */
-#define AESAXIN (HWREG16(0x40003C0E)) /* AES Accelerator XORed Data In Register */
-
-/* Register offsets from AES256_BASE address */
-#define OFS_AESACTL0 (0x0000) /* AES Accelerator Control Register 0 */
-#define OFS_AESACTL1 (0x0002) /* AES Accelerator Control Register 1 */
-#define OFS_AESASTAT (0x0004) /* AES Accelerator Status Register */
-#define OFS_AESAKEY (0x0006) /* AES Accelerator Key Register */
-#define OFS_AESADIN (0x0008) /* AES Accelerator Data In Register */
-#define OFS_AESADOUT (0x000a) /* AES Accelerator Data Out Register */
-#define OFS_AESAXDIN (0x000c) /* AES Accelerator XORed Data In Register */
-#define OFS_AESAXIN (0x000e) /* AES Accelerator XORed Data In Register */
-
-
-//*****************************************************************************
-// CAPTIO0 Registers
-//*****************************************************************************
-#define CAPTIO0CTL (HWREG16(0x4000540E)) /* Capacitive Touch IO x Control Register */
-
-/* Register offsets from CAPTIO0_BASE address */
-#define OFS_CAPTIO0CTL (0x000e) /* Capacitive Touch IO x Control Register */
-
-#define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
-#define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
-
-//*****************************************************************************
-// CAPTIO1 Registers
-//*****************************************************************************
-#define CAPTIO1CTL (HWREG16(0x4000580E)) /* Capacitive Touch IO x Control Register */
-
-/* Register offsets from CAPTIO1_BASE address */
-#define OFS_CAPTIO1CTL (0x000e) /* Capacitive Touch IO x Control Register */
-
-#define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
-#define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
-
-//*****************************************************************************
-// COMP_E0 Registers
-//*****************************************************************************
-#define CE0CTL0 (HWREG16(0x40003400)) /* Comparator Control Register 0 */
-#define CE0CTL1 (HWREG16(0x40003402)) /* Comparator Control Register 1 */
-#define CE0CTL2 (HWREG16(0x40003404)) /* Comparator Control Register 2 */
-#define CE0CTL3 (HWREG16(0x40003406)) /* Comparator Control Register 3 */
-#define CE0INT (HWREG16(0x4000340C)) /* Comparator Interrupt Control Register */
-#define CE0IV (HWREG16(0x4000340E)) /* Comparator Interrupt Vector Word Register */
-
-/* Register offsets from COMP_E0_BASE address */
-#define OFS_CE0CTL0 (0x0000) /* Comparator Control Register 0 */
-#define OFS_CE0CTL1 (0x0002) /* Comparator Control Register 1 */
-#define OFS_CE0CTL2 (0x0004) /* Comparator Control Register 2 */
-#define OFS_CE0CTL3 (0x0006) /* Comparator Control Register 3 */
-#define OFS_CE0INT (0x000c) /* Comparator Interrupt Control Register */
-#define OFS_CE0IV (0x000e) /* Comparator Interrupt Vector Word Register */
-
-
-//*****************************************************************************
-// COMP_E1 Registers
-//*****************************************************************************
-#define CE1CTL0 (HWREG16(0x40003800)) /* Comparator Control Register 0 */
-#define CE1CTL1 (HWREG16(0x40003802)) /* Comparator Control Register 1 */
-#define CE1CTL2 (HWREG16(0x40003804)) /* Comparator Control Register 2 */
-#define CE1CTL3 (HWREG16(0x40003806)) /* Comparator Control Register 3 */
-#define CE1INT (HWREG16(0x4000380C)) /* Comparator Interrupt Control Register */
-#define CE1IV (HWREG16(0x4000380E)) /* Comparator Interrupt Vector Word Register */
-
-/* Register offsets from COMP_E1_BASE address */
-#define OFS_CE1CTL0 (0x0000) /* Comparator Control Register 0 */
-#define OFS_CE1CTL1 (0x0002) /* Comparator Control Register 1 */
-#define OFS_CE1CTL2 (0x0004) /* Comparator Control Register 2 */
-#define OFS_CE1CTL3 (0x0006) /* Comparator Control Register 3 */
-#define OFS_CE1INT (0x000c) /* Comparator Interrupt Control Register */
-#define OFS_CE1IV (0x000e) /* Comparator Interrupt Vector Word Register */
-
-
-//*****************************************************************************
-// COREDEBUG Registers
-//*****************************************************************************
-#define COREDEBUG_DHCSR (HWREG32(0xE000EDF0)) /* Debug Halting Control and Status Register */
-#define COREDEBUG_DCRSR (HWREG32(0xE000EDF4)) /* Deubg Core Register Selector Register */
-#define COREDEBUG_DCRDR (HWREG32(0xE000EDF8)) /* Debug Core Register Data Register */
-#define COREDEBUG_DEMCR (HWREG32(0xE000EDFC)) /* Debug Exception and Monitor Control Register */
-
-/* Register offsets from COREDEBUG_BASE address */
-#define OFS_COREDEBUG_DHCSR (0x00000DF0) /* Debug Halting Control and Status Register */
-#define OFS_COREDEBUG_DCRSR (0x00000DF4) /* Deubg Core Register Selector Register */
-#define OFS_COREDEBUG_DCRDR (0x00000DF8) /* Debug Core Register Data Register */
-#define OFS_COREDEBUG_DEMCR (0x00000DFC) /* Debug Exception and Monitor Control Register */
-
-
-//*****************************************************************************
-// CRC32 Registers
-//*****************************************************************************
-#define CRC32DI (HWREG16(0x40004000)) /* Data Input for CRC32 Signature Computation */
-#define CRC32DIRB (HWREG16(0x40004004)) /* Data In Reverse for CRC32 Computation */
-#define CRC32INIRES_LO (HWREG16(0x40004008)) /* CRC32 Initialization and Result, lower 16 bits */
-#define CRC32INIRES_HI (HWREG16(0x4000400A)) /* CRC32 Initialization and Result, upper 16 bits */
-#define CRC32RESR_LO (HWREG16(0x4000400C)) /* CRC32 Result Reverse, lower 16 bits */
-#define CRC32RESR_HI (HWREG16(0x4000400E)) /* CRC32 Result Reverse, Upper 16 bits */
-#define CRC16DI (HWREG16(0x40004010)) /* Data Input for CRC16 computation */
-#define CRC16DIRB (HWREG16(0x40004014)) /* CRC16 Data In Reverse */
-#define CRC16INIRES (HWREG16(0x40004018)) /* CRC16 Initialization and Result register */
-#define CRC16RESR (HWREG16(0x4000401E)) /* CRC16 Result Reverse */
-
-/* Register offsets from CRC32_BASE address */
-#define OFS_CRC32DI (0x0000) /* Data Input for CRC32 Signature Computation */
-#define OFS_CRC32DIRB (0x0004) /* Data In Reverse for CRC32 Computation */
-#define OFS_CRC32INIRES_LO (0x0008) /* CRC32 Initialization and Result, lower 16 bits */
-#define OFS_CRC32INIRES_HI (0x000a) /* CRC32 Initialization and Result, upper 16 bits */
-#define OFS_CRC32RESR_LO (0x000c) /* CRC32 Result Reverse, lower 16 bits */
-#define OFS_CRC32RESR_HI (0x000e) /* CRC32 Result Reverse, Upper 16 bits */
-#define OFS_CRC16DI (0x0010) /* Data Input for CRC16 computation */
-#define OFS_CRC16DIRB (0x0014) /* CRC16 Data In Reverse */
-#define OFS_CRC16INIRES (0x0018) /* CRC16 Initialization and Result register */
-#define OFS_CRC16RESR (0x001e) /* CRC16 Result Reverse */
-
-
-//*****************************************************************************
-// CS Registers
-//*****************************************************************************
-#define CSKEY (HWREG32(0x40010400)) /* Key Register */
-#define CSCTL0 (HWREG32(0x40010404)) /* Control 0 Register */
-#define CSCTL1 (HWREG32(0x40010408)) /* Control 1 Register */
-#define CSCTL2 (HWREG32(0x4001040C)) /* Control 2 Register */
-#define CSCTL3 (HWREG32(0x40010410)) /* Control 3 Register */
-#define CSCTL4 (HWREG32(0x40010414)) /* Control 4 Register */
-#define CSCTL5 (HWREG32(0x40010418)) /* Control 5 Register */
-#define CSCTL6 (HWREG32(0x4001041C)) /* Control 6 Register */
-#define CSCTL7 (HWREG32(0x40010420)) /* Control 7 Register */
-#define CSCLKEN (HWREG32(0x40010430)) /* Clock Enable Register */
-#define CSSTAT (HWREG32(0x40010434)) /* Status Register */
-#define CSIE (HWREG32(0x40010440)) /* Interrupt Enable Register */
-#define CSIFG (HWREG32(0x40010448)) /* Interrupt Flag Register */
-#define CSCLRIFG (HWREG32(0x40010450)) /* Clear Interrupt Flag Register */
-#define CSSETIFG (HWREG32(0x40010458)) /* Set Interrupt Flag Register */
-#define CSDCOERCAL (HWREG32(0x40010460)) /* DCO external resistor cailbration register */
-
-/* Register offsets from CS_BASE address */
-#define OFS_CSKEY (0x00000000) /* Key Register */
-#define OFS_CSCTL0 (0x00000004) /* Control 0 Register */
-#define OFS_CSCTL1 (0x00000008) /* Control 1 Register */
-#define OFS_CSCTL2 (0x0000000c) /* Control 2 Register */
-#define OFS_CSCTL3 (0x00000010) /* Control 3 Register */
-#define OFS_CSCTL4 (0x00000014) /* Control 4 Register */
-#define OFS_CSCTL5 (0x00000018) /* Control 5 Register */
-#define OFS_CSCTL6 (0x0000001c) /* Control 6 Register */
-#define OFS_CSCTL7 (0x00000020) /* Control 7 Register */
-#define OFS_CSCLKEN (0x00000030) /* Clock Enable Register */
-#define OFS_CSSTAT (0x00000034) /* Status Register */
-#define OFS_CSIE (0x00000040) /* Interrupt Enable Register */
-#define OFS_CSIFG (0x00000048) /* Interrupt Flag Register */
-#define OFS_CSCLRIFG (0x00000050) /* Clear Interrupt Flag Register */
-#define OFS_CSSETIFG (0x00000058) /* Set Interrupt Flag Register */
-#define OFS_CSDCOERCAL (0x00000060) /* DCO external resistor cailbration register */
-
-
-//*****************************************************************************
-// DIO Registers
-//*****************************************************************************
-#define PAIN (HWREG16(0x40004C00)) /* Port A Input */
-#define PAOUT (HWREG16(0x40004C02)) /* Port A Output */
-#define PADIR (HWREG16(0x40004C04)) /* Port A Direction */
-#define PAREN (HWREG16(0x40004C06)) /* Port A Resistor Enable */
-#define PADS (HWREG16(0x40004C08)) /* Port A Drive Strength */
-#define PASEL0 (HWREG16(0x40004C0A)) /* Port A Select 0 */
-#define PASEL1 (HWREG16(0x40004C0C)) /* Port A Select 1 */
-#define P1IV (HWREG16(0x40004C0E)) /* Port 1 Interrupt Vector Register */
-#define PASELC (HWREG16(0x40004C16)) /* Port A Complement Select */
-#define PAIES (HWREG16(0x40004C18)) /* Port A Interrupt Edge Select */
-#define PAIE (HWREG16(0x40004C1A)) /* Port A Interrupt Enable */
-#define PAIFG (HWREG16(0x40004C1C)) /* Port A Interrupt Flag */
-#define P2IV (HWREG16(0x40004C1E)) /* Port 2 Interrupt Vector Register */
-#define PBIN (HWREG16(0x40004C20)) /* Port B Input */
-#define PBOUT (HWREG16(0x40004C22)) /* Port B Output */
-#define PBDIR (HWREG16(0x40004C24)) /* Port B Direction */
-#define PBREN (HWREG16(0x40004C26)) /* Port B Resistor Enable */
-#define PBDS (HWREG16(0x40004C28)) /* Port B Drive Strength */
-#define PBSEL0 (HWREG16(0x40004C2A)) /* Port B Select 0 */
-#define PBSEL1 (HWREG16(0x40004C2C)) /* Port B Select 1 */
-#define P3IV (HWREG16(0x40004C2E)) /* Port 3 Interrupt Vector Register */
-#define PBSELC (HWREG16(0x40004C36)) /* Port B Complement Select */
-#define PBIES (HWREG16(0x40004C38)) /* Port B Interrupt Edge Select */
-#define PBIE (HWREG16(0x40004C3A)) /* Port B Interrupt Enable */
-#define PBIFG (HWREG16(0x40004C3C)) /* Port B Interrupt Flag */
-#define P4IV (HWREG16(0x40004C3E)) /* Port 4 Interrupt Vector Register */
-#define PCIN (HWREG16(0x40004C40)) /* Port C Input */
-#define PCOUT (HWREG16(0x40004C42)) /* Port C Output */
-#define PCDIR (HWREG16(0x40004C44)) /* Port C Direction */
-#define PCREN (HWREG16(0x40004C46)) /* Port C Resistor Enable */
-#define PCDS (HWREG16(0x40004C48)) /* Port C Drive Strength */
-#define PCSEL0 (HWREG16(0x40004C4A)) /* Port C Select 0 */
-#define PCSEL1 (HWREG16(0x40004C4C)) /* Port C Select 1 */
-#define P5IV (HWREG16(0x40004C4E)) /* Port 5 Interrupt Vector Register */
-#define PCSELC (HWREG16(0x40004C56)) /* Port C Complement Select */
-#define PCIES (HWREG16(0x40004C58)) /* Port C Interrupt Edge Select */
-#define PCIE (HWREG16(0x40004C5A)) /* Port C Interrupt Enable */
-#define PCIFG (HWREG16(0x40004C5C)) /* Port C Interrupt Flag */
-#define P6IV (HWREG16(0x40004C5E)) /* Port 6 Interrupt Vector Register */
-#define PDIN (HWREG16(0x40004C60)) /* Port D Input */
-#define PDOUT (HWREG16(0x40004C62)) /* Port D Output */
-#define PDDIR (HWREG16(0x40004C64)) /* Port D Direction */
-#define PDREN (HWREG16(0x40004C66)) /* Port D Resistor Enable */
-#define PDDS (HWREG16(0x40004C68)) /* Port D Drive Strength */
-#define PDSEL0 (HWREG16(0x40004C6A)) /* Port D Select 0 */
-#define PDSEL1 (HWREG16(0x40004C6C)) /* Port D Select 1 */
-#define P7IV (HWREG16(0x40004C6E)) /* Port 7 Interrupt Vector Register */
-#define PDSELC (HWREG16(0x40004C76)) /* Port D Complement Select */
-#define PDIES (HWREG16(0x40004C78)) /* Port D Interrupt Edge Select */
-#define PDIE (HWREG16(0x40004C7A)) /* Port D Interrupt Enable */
-#define PDIFG (HWREG16(0x40004C7C)) /* Port D Interrupt Flag */
-#define P8IV (HWREG16(0x40004C7E)) /* Port 8 Interrupt Vector Register */
-#define PEIN (HWREG16(0x40004C80)) /* Port E Input */
-#define PEOUT (HWREG16(0x40004C82)) /* Port E Output */
-#define PEDIR (HWREG16(0x40004C84)) /* Port E Direction */
-#define PEREN (HWREG16(0x40004C86)) /* Port E Resistor Enable */
-#define PEDS (HWREG16(0x40004C88)) /* Port E Drive Strength */
-#define PESEL0 (HWREG16(0x40004C8A)) /* Port E Select 0 */
-#define PESEL1 (HWREG16(0x40004C8C)) /* Port E Select 1 */
-#define P9IV (HWREG16(0x40004C8E)) /* Port 9 Interrupt Vector Register */
-#define PESELC (HWREG16(0x40004C96)) /* Port E Complement Select */
-#define PEIES (HWREG16(0x40004C98)) /* Port E Interrupt Edge Select */
-#define PEIE (HWREG16(0x40004C9A)) /* Port E Interrupt Enable */
-#define PEIFG (HWREG16(0x40004C9C)) /* Port E Interrupt Flag */
-#define P10IV (HWREG16(0x40004C9E)) /* Port 10 Interrupt Vector Register */
-#define PJIN (HWREG16(0x40004D20)) /* Port J Input */
-#define PJOUT (HWREG16(0x40004D22)) /* Port J Output */
-#define PJDIR (HWREG16(0x40004D24)) /* Port J Direction */
-#define PJREN (HWREG16(0x40004D26)) /* Port J Resistor Enable */
-#define PJDS (HWREG16(0x40004D28)) /* Port J Drive Strength */
-#define PJSEL0 (HWREG16(0x40004D2A)) /* Port J Select 0 */
-#define PJSEL1 (HWREG16(0x40004D2C)) /* Port J Select 1 */
-#define PJSELC (HWREG16(0x40004D36)) /* Port J Complement Select */
-#define P1IN (HWREG8(0x40004C00)) /* Port 1 Input */
-#define P2IN (HWREG8(0x40004C01)) /* Port 2 Input */
-#define P2OUT (HWREG8(0x40004C03)) /* Port 2 Output */
-#define P1OUT (HWREG8(0x40004C02)) /* Port 1 Output */
-#define P1DIR (HWREG8(0x40004C04)) /* Port 1 Direction */
-#define P2DIR (HWREG8(0x40004C05)) /* Port 2 Direction */
-#define P1REN (HWREG8(0x40004C06)) /* Port 1 Resistor Enable */
-#define P2REN (HWREG8(0x40004C07)) /* Port 2 Resistor Enable */
-#define P1DS (HWREG8(0x40004C08)) /* Port 1 Drive Strength */
-#define P2DS (HWREG8(0x40004C09)) /* Port 2 Drive Strength */
-#define P1SEL0 (HWREG8(0x40004C0A)) /* Port 1 Select 0 */
-#define P2SEL0 (HWREG8(0x40004C0B)) /* Port 2 Select 0 */
-#define P1SEL1 (HWREG8(0x40004C0C)) /* Port 1 Select 1 */
-#define P2SEL1 (HWREG8(0x40004C0D)) /* Port 2 Select 1 */
-#define P1SELC (HWREG8(0x40004C16)) /* Port 1 Complement Select */
-#define P2SELC (HWREG8(0x40004C17)) /* Port 2 Complement Select */
-#define P1IES (HWREG8(0x40004C18)) /* Port 1 Interrupt Edge Select */
-#define P2IES (HWREG8(0x40004C19)) /* Port 2 Interrupt Edge Select */
-#define P1IE (HWREG8(0x40004C1A)) /* Port 1 Interrupt Enable */
-#define P2IE (HWREG8(0x40004C1B)) /* Port 2 Interrupt Enable */
-#define P1IFG (HWREG8(0x40004C1C)) /* Port 1 Interrupt Flag */
-#define P2IFG (HWREG8(0x40004C1D)) /* Port 2 Interrupt Flag */
-#define P3IN (HWREG8(0x40004C20)) /* Port 3 Input */
-#define P4IN (HWREG8(0x40004C21)) /* Port 4 Input */
-#define P3OUT (HWREG8(0x40004C22)) /* Port 3 Output */
-#define P4OUT (HWREG8(0x40004C23)) /* Port 4 Output */
-#define P3DIR (HWREG8(0x40004C24)) /* Port 3 Direction */
-#define P4DIR (HWREG8(0x40004C25)) /* Port 4 Direction */
-#define P3REN (HWREG8(0x40004C26)) /* Port 3 Resistor Enable */
-#define P4REN (HWREG8(0x40004C27)) /* Port 4 Resistor Enable */
-#define P3DS (HWREG8(0x40004C28)) /* Port 3 Drive Strength */
-#define P4DS (HWREG8(0x40004C29)) /* Port 4 Drive Strength */
-#define P4SEL0 (HWREG8(0x40004C2B)) /* Port 4 Select 0 */
-#define P3SEL0 (HWREG8(0x40004C2A)) /* Port 3 Select 0 */
-#define P3SEL1 (HWREG8(0x40004C2C)) /* Port 3 Select 1 */
-#define P4SEL1 (HWREG8(0x40004C2D)) /* Port 4 Select 1 */
-#define P3SELC (HWREG8(0x40004C36)) /* Port 3 Complement Select */
-#define P4SELC (HWREG8(0x40004C37)) /* Port 4 Complement Select */
-#define P3IES (HWREG8(0x40004C38)) /* Port 3 Interrupt Edge Select */
-#define P4IES (HWREG8(0x40004C39)) /* Port 4 Interrupt Edge Select */
-#define P3IE (HWREG8(0x40004C3A)) /* Port 3 Interrupt Enable */
-#define P4IE (HWREG8(0x40004C3B)) /* Port 4 Interrupt Enable */
-#define P3IFG (HWREG8(0x40004C3C)) /* Port 3 Interrupt Flag */
-#define P4IFG (HWREG8(0x40004C3D)) /* Port 4 Interrupt Flag */
-#define P5IN (HWREG8(0x40004C40)) /* Port 5 Input */
-#define P6IN (HWREG8(0x40004C41)) /* Port 6 Input */
-#define P5OUT (HWREG8(0x40004C42)) /* Port 5 Output */
-#define P6OUT (HWREG8(0x40004C43)) /* Port 6 Output */
-#define P5DIR (HWREG8(0x40004C44)) /* Port 5 Direction */
-#define P6DIR (HWREG8(0x40004C45)) /* Port 6 Direction */
-#define P5REN (HWREG8(0x40004C46)) /* Port 5 Resistor Enable */
-#define P6REN (HWREG8(0x40004C47)) /* Port 6 Resistor Enable */
-#define P5DS (HWREG8(0x40004C48)) /* Port 5 Drive Strength */
-#define P6DS (HWREG8(0x40004C49)) /* Port 6 Drive Strength */
-#define P5SEL0 (HWREG8(0x40004C4A)) /* Port 5 Select 0 */
-#define P6SEL0 (HWREG8(0x40004C4B)) /* Port 6 Select 0 */
-#define P5SEL1 (HWREG8(0x40004C4C)) /* Port 5 Select 1 */
-#define P6SEL1 (HWREG8(0x40004C4D)) /* Port 6 Select 1 */
-#define P5SELC (HWREG8(0x40004C56)) /* Port 5 Complement Select */
-#define P6SELC (HWREG8(0x40004C57)) /* Port 6 Complement Select */
-#define P5IES (HWREG8(0x40004C58)) /* Port 5 Interrupt Edge Select */
-#define P6IES (HWREG8(0x40004C59)) /* Port 6 Interrupt Edge Select */
-#define P5IE (HWREG8(0x40004C5A)) /* Port 5 Interrupt Enable */
-#define P6IE (HWREG8(0x40004C5B)) /* Port 6 Interrupt Enable */
-#define P5IFG (HWREG8(0x40004C5C)) /* Port 5 Interrupt Flag */
-#define P6IFG (HWREG8(0x40004C5D)) /* Port 6 Interrupt Flag */
-#define P7IN (HWREG8(0x40004C60)) /* Port 7 Input */
-#define P8IN (HWREG8(0x40004C61)) /* Port 8 Input */
-#define P7OUT (HWREG8(0x40004C62)) /* Port 7 Output */
-#define P8OUT (HWREG8(0x40004C63)) /* Port 8 Output */
-#define P7DIR (HWREG8(0x40004C64)) /* Port 7 Direction */
-#define P8DIR (HWREG8(0x40004C65)) /* Port 8 Direction */
-#define P7REN (HWREG8(0x40004C66)) /* Port 7 Resistor Enable */
-#define P8REN (HWREG8(0x40004C67)) /* Port 8 Resistor Enable */
-#define P7DS (HWREG8(0x40004C68)) /* Port 7 Drive Strength */
-#define P8DS (HWREG8(0x40004C69)) /* Port 8 Drive Strength */
-#define P7SEL0 (HWREG8(0x40004C6A)) /* Port 7 Select 0 */
-#define P8SEL0 (HWREG8(0x40004C6B)) /* Port 8 Select 0 */
-#define P7SEL1 (HWREG8(0x40004C6C)) /* Port 7 Select 1 */
-#define P8SEL1 (HWREG8(0x40004C6D)) /* Port 8 Select 1 */
-#define P7SELC (HWREG8(0x40004C76)) /* Port 7 Complement Select */
-#define P8SELC (HWREG8(0x40004C77)) /* Port 8 Complement Select */
-#define P7IES (HWREG8(0x40004C78)) /* Port 7 Interrupt Edge Select */
-#define P8IES (HWREG8(0x40004C79)) /* Port 8 Interrupt Edge Select */
-#define P7IE (HWREG8(0x40004C7A)) /* Port 7 Interrupt Enable */
-#define P8IE (HWREG8(0x40004C7B)) /* Port 8 Interrupt Enable */
-#define P7IFG (HWREG8(0x40004C7C)) /* Port 7 Interrupt Flag */
-#define P8IFG (HWREG8(0x40004C7D)) /* Port 8 Interrupt Flag */
-#define P9IN (HWREG8(0x40004C80)) /* Port 9 Input */
-#define P10IN (HWREG8(0x40004C81)) /* Port 10 Input */
-#define P9OUT (HWREG8(0x40004C82)) /* Port 9 Output */
-#define P10OUT (HWREG8(0x40004C83)) /* Port 10 Output */
-#define P9DIR (HWREG8(0x40004C84)) /* Port 9 Direction */
-#define P10DIR (HWREG8(0x40004C85)) /* Port 10 Direction */
-#define P9REN (HWREG8(0x40004C86)) /* Port 9 Resistor Enable */
-#define P10REN (HWREG8(0x40004C87)) /* Port 10 Resistor Enable */
-#define P9DS (HWREG8(0x40004C88)) /* Port 9 Drive Strength */
-#define P10DS (HWREG8(0x40004C89)) /* Port 10 Drive Strength */
-#define P9SEL0 (HWREG8(0x40004C8A)) /* Port 9 Select 0 */
-#define P10SEL0 (HWREG8(0x40004C8B)) /* Port 10 Select 0 */
-#define P9SEL1 (HWREG8(0x40004C8C)) /* Port 9 Select 1 */
-#define P10SEL1 (HWREG8(0x40004C8D)) /* Port 10 Select 1 */
-#define P9SELC (HWREG8(0x40004C96)) /* Port 9 Complement Select */
-#define P10SELC (HWREG8(0x40004C97)) /* Port 10 Complement Select */
-#define P9IES (HWREG8(0x40004C98)) /* Port 9 Interrupt Edge Select */
-#define P10IES (HWREG8(0x40004C99)) /* Port 10 Interrupt Edge Select */
-#define P9IE (HWREG8(0x40004C9A)) /* Port 9 Interrupt Enable */
-#define P10IE (HWREG8(0x40004C9B)) /* Port 10 Interrupt Enable */
-#define P9IFG (HWREG8(0x40004C9C)) /* Port 9 Interrupt Flag */
-#define P10IFG (HWREG8(0x40004C9D)) /* Port 10 Interrupt Flag */
-
-/* Register offsets from DIO_BASE address */
-#define OFS_PAIN (0x0000) /* Port A Input */
-#define OFS_PAOUT (0x0002) /* Port A Output */
-#define OFS_PADIR (0x0004) /* Port A Direction */
-#define OFS_PAREN (0x0006) /* Port A Resistor Enable */
-#define OFS_PADS (0x0008) /* Port A Drive Strength */
-#define OFS_PASEL0 (0x000a) /* Port A Select 0 */
-#define OFS_PASEL1 (0x000c) /* Port A Select 1 */
-#define OFS_P1IV (0x000e) /* Port 1 Interrupt Vector Register */
-#define OFS_PASELC (0x0016) /* Port A Complement Select */
-#define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */
-#define OFS_PAIE (0x001a) /* Port A Interrupt Enable */
-#define OFS_PAIFG (0x001c) /* Port A Interrupt Flag */
-#define OFS_P2IV (0x001e) /* Port 2 Interrupt Vector Register */
-#define OFS_PBIN (0x0020) /* Port B Input */
-#define OFS_PBOUT (0x0022) /* Port B Output */
-#define OFS_PBDIR (0x0024) /* Port B Direction */
-#define OFS_PBREN (0x0026) /* Port B Resistor Enable */
-#define OFS_PBDS (0x0028) /* Port B Drive Strength */
-#define OFS_PBSEL0 (0x002a) /* Port B Select 0 */
-#define OFS_PBSEL1 (0x002c) /* Port B Select 1 */
-#define OFS_P3IV (0x002e) /* Port 3 Interrupt Vector Register */
-#define OFS_PBSELC (0x0036) /* Port B Complement Select */
-#define OFS_PBIES (0x0038) /* Port B Interrupt Edge Select */
-#define OFS_PBIE (0x003a) /* Port B Interrupt Enable */
-#define OFS_PBIFG (0x003c) /* Port B Interrupt Flag */
-#define OFS_P4IV (0x003e) /* Port 4 Interrupt Vector Register */
-#define OFS_PCIN (0x0040) /* Port C Input */
-#define OFS_PCOUT (0x0042) /* Port C Output */
-#define OFS_PCDIR (0x0044) /* Port C Direction */
-#define OFS_PCREN (0x0046) /* Port C Resistor Enable */
-#define OFS_PCDS (0x0048) /* Port C Drive Strength */
-#define OFS_PCSEL0 (0x004a) /* Port C Select 0 */
-#define OFS_PCSEL1 (0x004c) /* Port C Select 1 */
-#define OFS_P5IV (0x004e) /* Port 5 Interrupt Vector Register */
-#define OFS_PCSELC (0x0056) /* Port C Complement Select */
-#define OFS_PCIES (0x0058) /* Port C Interrupt Edge Select */
-#define OFS_PCIE (0x005a) /* Port C Interrupt Enable */
-#define OFS_PCIFG (0x005c) /* Port C Interrupt Flag */
-#define OFS_P6IV (0x005e) /* Port 6 Interrupt Vector Register */
-#define OFS_PDIN (0x0060) /* Port D Input */
-#define OFS_PDOUT (0x0062) /* Port D Output */
-#define OFS_PDDIR (0x0064) /* Port D Direction */
-#define OFS_PDREN (0x0066) /* Port D Resistor Enable */
-#define OFS_PDDS (0x0068) /* Port D Drive Strength */
-#define OFS_PDSEL0 (0x006a) /* Port D Select 0 */
-#define OFS_PDSEL1 (0x006c) /* Port D Select 1 */
-#define OFS_P7IV (0x006e) /* Port 7 Interrupt Vector Register */
-#define OFS_PDSELC (0x0076) /* Port D Complement Select */
-#define OFS_PDIES (0x0078) /* Port D Interrupt Edge Select */
-#define OFS_PDIE (0x007a) /* Port D Interrupt Enable */
-#define OFS_PDIFG (0x007c) /* Port D Interrupt Flag */
-#define OFS_P8IV (0x007e) /* Port 8 Interrupt Vector Register */
-#define OFS_PEIN (0x0080) /* Port E Input */
-#define OFS_PEOUT (0x0082) /* Port E Output */
-#define OFS_PEDIR (0x0084) /* Port E Direction */
-#define OFS_PEREN (0x0086) /* Port E Resistor Enable */
-#define OFS_PEDS (0x0088) /* Port E Drive Strength */
-#define OFS_PESEL0 (0x008a) /* Port E Select 0 */
-#define OFS_PESEL1 (0x008c) /* Port E Select 1 */
-#define OFS_P9IV (0x008e) /* Port 9 Interrupt Vector Register */
-#define OFS_PESELC (0x0096) /* Port E Complement Select */
-#define OFS_PEIES (0x0098) /* Port E Interrupt Edge Select */
-#define OFS_PEIE (0x009a) /* Port E Interrupt Enable */
-#define OFS_PEIFG (0x009c) /* Port E Interrupt Flag */
-#define OFS_P10IV (0x009e) /* Port 10 Interrupt Vector Register */
-#define OFS_PJIN (0x0120) /* Port J Input */
-#define OFS_PJOUT (0x0122) /* Port J Output */
-#define OFS_PJDIR (0x0124) /* Port J Direction */
-#define OFS_PJREN (0x0126) /* Port J Resistor Enable */
-#define OFS_PJDS (0x0128) /* Port J Drive Strength */
-#define OFS_PJSEL0 (0x012a) /* Port J Select 0 */
-#define OFS_PJSEL1 (0x012c) /* Port J Select 1 */
-#define OFS_PJSELC (0x0136) /* Port J Complement Select */
-#define OFS_P1IN (0x0000) /* Port 1 Input */
-#define OFS_P2IN (0x0000) /* Port 2 Input */
-#define OFS_P2OUT (0x0002) /* Port 2 Output */
-#define OFS_P1OUT (0x0002) /* Port 1 Output */
-#define OFS_P1DIR (0x0004) /* Port 1 Direction */
-#define OFS_P2DIR (0x0004) /* Port 2 Direction */
-#define OFS_P1REN (0x0006) /* Port 1 Resistor Enable */
-#define OFS_P2REN (0x0006) /* Port 2 Resistor Enable */
-#define OFS_P1DS (0x0008) /* Port 1 Drive Strength */
-#define OFS_P2DS (0x0008) /* Port 2 Drive Strength */
-#define OFS_P1SEL0 (0x000a) /* Port 1 Select 0 */
-#define OFS_P2SEL0 (0x000a) /* Port 2 Select 0 */
-#define OFS_P1SEL1 (0x000c) /* Port 1 Select 1 */
-#define OFS_P2SEL1 (0x000c) /* Port 2 Select 1 */
-#define OFS_P1SELC (0x0016) /* Port 1 Complement Select */
-#define OFS_P2SELC (0x0016) /* Port 2 Complement Select */
-#define OFS_P1IES (0x0018) /* Port 1 Interrupt Edge Select */
-#define OFS_P2IES (0x0018) /* Port 2 Interrupt Edge Select */
-#define OFS_P1IE (0x001a) /* Port 1 Interrupt Enable */
-#define OFS_P2IE (0x001a) /* Port 2 Interrupt Enable */
-#define OFS_P1IFG (0x001c) /* Port 1 Interrupt Flag */
-#define OFS_P2IFG (0x001c) /* Port 2 Interrupt Flag */
-#define OFS_P3IN (0x0020) /* Port 3 Input */
-#define OFS_P4IN (0x0020) /* Port 4 Input */
-#define OFS_P3OUT (0x0022) /* Port 3 Output */
-#define OFS_P4OUT (0x0022) /* Port 4 Output */
-#define OFS_P3DIR (0x0024) /* Port 3 Direction */
-#define OFS_P4DIR (0x0024) /* Port 4 Direction */
-#define OFS_P3REN (0x0026) /* Port 3 Resistor Enable */
-#define OFS_P4REN (0x0026) /* Port 4 Resistor Enable */
-#define OFS_P3DS (0x0028) /* Port 3 Drive Strength */
-#define OFS_P4DS (0x0028) /* Port 4 Drive Strength */
-#define OFS_P4SEL0 (0x002a) /* Port 4 Select 0 */
-#define OFS_P3SEL0 (0x002a) /* Port 3 Select 0 */
-#define OFS_P3SEL1 (0x002c) /* Port 3 Select 1 */
-#define OFS_P4SEL1 (0x002c) /* Port 4 Select 1 */
-#define OFS_P3SELC (0x0036) /* Port 3 Complement Select */
-#define OFS_P4SELC (0x0036) /* Port 4 Complement Select */
-#define OFS_P3IES (0x0038) /* Port 3 Interrupt Edge Select */
-#define OFS_P4IES (0x0038) /* Port 4 Interrupt Edge Select */
-#define OFS_P3IE (0x003a) /* Port 3 Interrupt Enable */
-#define OFS_P4IE (0x003a) /* Port 4 Interrupt Enable */
-#define OFS_P3IFG (0x003c) /* Port 3 Interrupt Flag */
-#define OFS_P4IFG (0x003c) /* Port 4 Interrupt Flag */
-#define OFS_P5IN (0x0040) /* Port 5 Input */
-#define OFS_P6IN (0x0040) /* Port 6 Input */
-#define OFS_P5OUT (0x0042) /* Port 5 Output */
-#define OFS_P6OUT (0x0042) /* Port 6 Output */
-#define OFS_P5DIR (0x0044) /* Port 5 Direction */
-#define OFS_P6DIR (0x0044) /* Port 6 Direction */
-#define OFS_P5REN (0x0046) /* Port 5 Resistor Enable */
-#define OFS_P6REN (0x0046) /* Port 6 Resistor Enable */
-#define OFS_P5DS (0x0048) /* Port 5 Drive Strength */
-#define OFS_P6DS (0x0048) /* Port 6 Drive Strength */
-#define OFS_P5SEL0 (0x004a) /* Port 5 Select 0 */
-#define OFS_P6SEL0 (0x004a) /* Port 6 Select 0 */
-#define OFS_P5SEL1 (0x004c) /* Port 5 Select 1 */
-#define OFS_P6SEL1 (0x004c) /* Port 6 Select 1 */
-#define OFS_P5SELC (0x0056) /* Port 5 Complement Select */
-#define OFS_P6SELC (0x0056) /* Port 6 Complement Select */
-#define OFS_P5IES (0x0058) /* Port 5 Interrupt Edge Select */
-#define OFS_P6IES (0x0058) /* Port 6 Interrupt Edge Select */
-#define OFS_P5IE (0x005a) /* Port 5 Interrupt Enable */
-#define OFS_P6IE (0x005a) /* Port 6 Interrupt Enable */
-#define OFS_P5IFG (0x005c) /* Port 5 Interrupt Flag */
-#define OFS_P6IFG (0x005c) /* Port 6 Interrupt Flag */
-#define OFS_P7IN (0x0060) /* Port 7 Input */
-#define OFS_P8IN (0x0060) /* Port 8 Input */
-#define OFS_P7OUT (0x0062) /* Port 7 Output */
-#define OFS_P8OUT (0x0062) /* Port 8 Output */
-#define OFS_P7DIR (0x0064) /* Port 7 Direction */
-#define OFS_P8DIR (0x0064) /* Port 8 Direction */
-#define OFS_P7REN (0x0066) /* Port 7 Resistor Enable */
-#define OFS_P8REN (0x0066) /* Port 8 Resistor Enable */
-#define OFS_P7DS (0x0068) /* Port 7 Drive Strength */
-#define OFS_P8DS (0x0068) /* Port 8 Drive Strength */
-#define OFS_P7SEL0 (0x006a) /* Port 7 Select 0 */
-#define OFS_P8SEL0 (0x006a) /* Port 8 Select 0 */
-#define OFS_P7SEL1 (0x006c) /* Port 7 Select 1 */
-#define OFS_P8SEL1 (0x006c) /* Port 8 Select 1 */
-#define OFS_P7SELC (0x0076) /* Port 7 Complement Select */
-#define OFS_P8SELC (0x0076) /* Port 8 Complement Select */
-#define OFS_P7IES (0x0078) /* Port 7 Interrupt Edge Select */
-#define OFS_P8IES (0x0078) /* Port 8 Interrupt Edge Select */
-#define OFS_P7IE (0x007a) /* Port 7 Interrupt Enable */
-#define OFS_P8IE (0x007a) /* Port 8 Interrupt Enable */
-#define OFS_P7IFG (0x007c) /* Port 7 Interrupt Flag */
-#define OFS_P8IFG (0x007c) /* Port 8 Interrupt Flag */
-#define OFS_P9IN (0x0080) /* Port 9 Input */
-#define OFS_P10IN (0x0080) /* Port 10 Input */
-#define OFS_P9OUT (0x0082) /* Port 9 Output */
-#define OFS_P10OUT (0x0082) /* Port 10 Output */
-#define OFS_P9DIR (0x0084) /* Port 9 Direction */
-#define OFS_P10DIR (0x0084) /* Port 10 Direction */
-#define OFS_P9REN (0x0086) /* Port 9 Resistor Enable */
-#define OFS_P10REN (0x0086) /* Port 10 Resistor Enable */
-#define OFS_P9DS (0x0088) /* Port 9 Drive Strength */
-#define OFS_P10DS (0x0088) /* Port 10 Drive Strength */
-#define OFS_P9SEL0 (0x008a) /* Port 9 Select 0 */
-#define OFS_P10SEL0 (0x008a) /* Port 10 Select 0 */
-#define OFS_P9SEL1 (0x008c) /* Port 9 Select 1 */
-#define OFS_P10SEL1 (0x008c) /* Port 10 Select 1 */
-#define OFS_P9SELC (0x0096) /* Port 9 Complement Select */
-#define OFS_P10SELC (0x0096) /* Port 10 Complement Select */
-#define OFS_P9IES (0x0098) /* Port 9 Interrupt Edge Select */
-#define OFS_P10IES (0x0098) /* Port 10 Interrupt Edge Select */
-#define OFS_P9IE (0x009a) /* Port 9 Interrupt Enable */
-#define OFS_P10IE (0x009a) /* Port 10 Interrupt Enable */
-#define OFS_P9IFG (0x009c) /* Port 9 Interrupt Flag */
-#define OFS_P10IFG (0x009c) /* Port 10 Interrupt Flag */
-
-
-//*****************************************************************************
-// DMA Registers
-//*****************************************************************************
-#define DMA_DEVICE_CFG (HWREG32(0x4000E000)) /* Device Configuration Status */
-#define DMA_SW_CHTRIG (HWREG32(0x4000E004)) /* Software Channel Trigger Register */
-#define DMA_CH0_SRCCFG (HWREG32(0x4000E010)) /* Channel n Source Configuration Register */
-#define DMA_CH1_SRCCFG (HWREG32(0x4000E014)) /* Channel n Source Configuration Register */
-#define DMA_CH2_SRCCFG (HWREG32(0x4000E018)) /* Channel n Source Configuration Register */
-#define DMA_CH3_SRCCFG (HWREG32(0x4000E01C)) /* Channel n Source Configuration Register */
-#define DMA_CH4_SRCCFG (HWREG32(0x4000E020)) /* Channel n Source Configuration Register */
-#define DMA_CH5_SRCCFG (HWREG32(0x4000E024)) /* Channel n Source Configuration Register */
-#define DMA_CH6_SRCCFG (HWREG32(0x4000E028)) /* Channel n Source Configuration Register */
-#define DMA_CH7_SRCCFG (HWREG32(0x4000E02C)) /* Channel n Source Configuration Register */
-#define DMA_CH8_SRCCFG (HWREG32(0x4000E030)) /* Channel n Source Configuration Register */
-#define DMA_CH9_SRCCFG (HWREG32(0x4000E034)) /* Channel n Source Configuration Register */
-#define DMA_CH10_SRCCFG (HWREG32(0x4000E038)) /* Channel n Source Configuration Register */
-#define DMA_CH11_SRCCFG (HWREG32(0x4000E03C)) /* Channel n Source Configuration Register */
-#define DMA_CH12_SRCCFG (HWREG32(0x4000E040)) /* Channel n Source Configuration Register */
-#define DMA_CH13_SRCCFG (HWREG32(0x4000E044)) /* Channel n Source Configuration Register */
-#define DMA_CH14_SRCCFG (HWREG32(0x4000E048)) /* Channel n Source Configuration Register */
-#define DMA_CH15_SRCCFG (HWREG32(0x4000E04C)) /* Channel n Source Configuration Register */
-#define DMA_CH16_SRCCFG (HWREG32(0x4000E050)) /* Channel n Source Configuration Register */
-#define DMA_CH17_SRCCFG (HWREG32(0x4000E054)) /* Channel n Source Configuration Register */
-#define DMA_CH18_SRCCFG (HWREG32(0x4000E058)) /* Channel n Source Configuration Register */
-#define DMA_CH19_SRCCFG (HWREG32(0x4000E05C)) /* Channel n Source Configuration Register */
-#define DMA_CH20_SRCCFG (HWREG32(0x4000E060)) /* Channel n Source Configuration Register */
-#define DMA_CH21_SRCCFG (HWREG32(0x4000E064)) /* Channel n Source Configuration Register */
-#define DMA_CH22_SRCCFG (HWREG32(0x4000E068)) /* Channel n Source Configuration Register */
-#define DMA_CH23_SRCCFG (HWREG32(0x4000E06C)) /* Channel n Source Configuration Register */
-#define DMA_CH24_SRCCFG (HWREG32(0x4000E070)) /* Channel n Source Configuration Register */
-#define DMA_CH25_SRCCFG (HWREG32(0x4000E074)) /* Channel n Source Configuration Register */
-#define DMA_CH26_SRCCFG (HWREG32(0x4000E078)) /* Channel n Source Configuration Register */
-#define DMA_CH27_SRCCFG (HWREG32(0x4000E07C)) /* Channel n Source Configuration Register */
-#define DMA_CH28_SRCCFG (HWREG32(0x4000E080)) /* Channel n Source Configuration Register */
-#define DMA_CH29_SRCCFG (HWREG32(0x4000E084)) /* Channel n Source Configuration Register */
-#define DMA_CH30_SRCCFG (HWREG32(0x4000E088)) /* Channel n Source Configuration Register */
-#define DMA_CH31_SRCCFG (HWREG32(0x4000E08C)) /* Channel n Source Configuration Register */
-#define DMA_INT1_SRCCFG (HWREG32(0x4000E100)) /* Interrupt 1 Source Channel Configuration */
-#define DMA_INT2_SRCCFG (HWREG32(0x4000E104)) /* Interrupt 2 Source Channel Configuration Register */
-#define DMA_INT3_SRCCFG (HWREG32(0x4000E108)) /* Interrupt 3 Source Channel Configuration Register */
-#define DMA_INT0_SRCFLG (HWREG32(0x4000E110)) /* Interrupt 0 Source Channel Flag Register */
-#define DMA_INT0_CLRFLG (HWREG32(0x4000E114)) /* Interrupt 0 Source Channel Clear Flag Register */
-#define DMA_STAT (HWREG32(0x4000F000)) /* Status Register */
-#define DMA_CFG (HWREG32(0x4000F004)) /* Configuration Register */
-#define DMA_CTLBASE (HWREG32(0x4000F008)) /* Channel Control Data Base Pointer Register */
-#define DMA_ATLBASE (HWREG32(0x4000F00C)) /* Channel Alternate Control Data Base Pointer Register */
-#define DMA_WAITSTAT (HWREG32(0x4000F010)) /* Channel Wait on Request Status Register */
-#define DMA_SWREQ (HWREG32(0x4000F014)) /* Channel Software Request Register */
-#define DMA_USEBURSTSET (HWREG32(0x4000F018)) /* Channel Useburst Set Register */
-#define DMA_USEBURSTCLR (HWREG32(0x4000F01C)) /* Channel Useburst Clear Register */
-#define DMA_REQMASKSET (HWREG32(0x4000F020)) /* Channel Request Mask Set Register */
-#define DMA_REQMASKCLR (HWREG32(0x4000F024)) /* Channel Request Mask Clear Register */
-#define DMA_ENASET (HWREG32(0x4000F028)) /* Channel Enable Set Register */
-#define DMA_ENACLR (HWREG32(0x4000F02C)) /* Channel Enable Clear Register */
-#define DMA_ALTSET (HWREG32(0x4000F030)) /* Channel Primary-Alternate Set Register */
-#define DMA_ALTCLR (HWREG32(0x4000F034)) /* Channel Primary-Alternate Clear Register */
-#define DMA_PRIOSET (HWREG32(0x4000F038)) /* Channel Priority Set Register */
-#define DMA_PRIOCLR (HWREG32(0x4000F03C)) /* Channel Priority Clear Register */
-#define DMA_ERRCLR (HWREG32(0x4000F04C)) /* Bus Error Clear Register */
-
-/* Register offsets from DMA_BASE address */
-#define OFS_DMA_DEVICE_CFG (0x00000000) /* Device Configuration Status */
-#define OFS_DMA_SW_CHTRIG (0x00000004) /* Software Channel Trigger Register */
-#define OFS_DMA_CH0_SRCCFG (0x00000010) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH1_SRCCFG (0x00000014) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH2_SRCCFG (0x00000018) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH3_SRCCFG (0x0000001C) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH4_SRCCFG (0x00000020) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH5_SRCCFG (0x00000024) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH6_SRCCFG (0x00000028) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH7_SRCCFG (0x0000002C) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH8_SRCCFG (0x00000030) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH9_SRCCFG (0x00000034) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH10_SRCCFG (0x00000038) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH11_SRCCFG (0x0000003C) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH12_SRCCFG (0x00000040) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH13_SRCCFG (0x00000044) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH14_SRCCFG (0x00000048) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH15_SRCCFG (0x0000004C) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH16_SRCCFG (0x00000050) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH17_SRCCFG (0x00000054) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH18_SRCCFG (0x00000058) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH19_SRCCFG (0x0000005C) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH20_SRCCFG (0x00000060) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH21_SRCCFG (0x00000064) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH22_SRCCFG (0x00000068) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH23_SRCCFG (0x0000006C) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH24_SRCCFG (0x00000070) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH25_SRCCFG (0x00000074) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH26_SRCCFG (0x00000078) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH27_SRCCFG (0x0000007C) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH28_SRCCFG (0x00000080) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH29_SRCCFG (0x00000084) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH30_SRCCFG (0x00000088) /* Channel n Source Configuration Register */
-#define OFS_DMA_CH31_SRCCFG (0x0000008C) /* Channel n Source Configuration Register */
-#define OFS_DMA_INT1_SRCCFG (0x00000100) /* Interrupt 1 Source Channel Configuration */
-#define OFS_DMA_INT2_SRCCFG (0x00000104) /* Interrupt 2 Source Channel Configuration Register */
-#define OFS_DMA_INT3_SRCCFG (0x00000108) /* Interrupt 3 Source Channel Configuration Register */
-#define OFS_DMA_INT0_SRCFLG (0x00000110) /* Interrupt 0 Source Channel Flag Register */
-#define OFS_DMA_INT0_CLRFLG (0x00000114) /* Interrupt 0 Source Channel Clear Flag Register */
-#define OFS_DMA_STAT (0x00001000) /* Status Register */
-#define OFS_DMA_CFG (0x00001004) /* Configuration Register */
-#define OFS_DMA_CTLBASE (0x00001008) /* Channel Control Data Base Pointer Register */
-#define OFS_DMA_ATLBASE (0x0000100c) /* Channel Alternate Control Data Base Pointer Register */
-#define OFS_DMA_WAITSTAT (0x00001010) /* Channel Wait on Request Status Register */
-#define OFS_DMA_SWREQ (0x00001014) /* Channel Software Request Register */
-#define OFS_DMA_USEBURSTSET (0x00001018) /* Channel Useburst Set Register */
-#define OFS_DMA_USEBURSTCLR (0x0000101c) /* Channel Useburst Clear Register */
-#define OFS_DMA_REQMASKSET (0x00001020) /* Channel Request Mask Set Register */
-#define OFS_DMA_REQMASKCLR (0x00001024) /* Channel Request Mask Clear Register */
-#define OFS_DMA_ENASET (0x00001028) /* Channel Enable Set Register */
-#define OFS_DMA_ENACLR (0x0000102c) /* Channel Enable Clear Register */
-#define OFS_DMA_ALTSET (0x00001030) /* Channel Primary-Alternate Set Register */
-#define OFS_DMA_ALTCLR (0x00001034) /* Channel Primary-Alternate Clear Register */
-#define OFS_DMA_PRIOSET (0x00001038) /* Channel Priority Set Register */
-#define OFS_DMA_PRIOCLR (0x0000103c) /* Channel Priority Clear Register */
-#define OFS_DMA_ERRCLR (0x0000104c) /* Bus Error Clear Register */
-
-
-//*****************************************************************************
-// DWT Registers
-//*****************************************************************************
-#define DWT_CTRL (HWREG32(0xE0001000)) /* DWT Control Register */
-#define DWT_CYCCNT (HWREG32(0xE0001004)) /* DWT Current PC Sampler Cycle Count Register */
-#define DWT_CPICNT (HWREG32(0xE0001008)) /* DWT CPI Count Register */
-#define DWT_EXCCNT (HWREG32(0xE000100C)) /* DWT Exception Overhead Count Register */
-#define DWT_SLEEPCNT (HWREG32(0xE0001010)) /* DWT Sleep Count Register */
-#define DWT_LSUCNT (HWREG32(0xE0001014)) /* DWT LSU Count Register */
-#define DWT_FOLDCNT (HWREG32(0xE0001018)) /* DWT Fold Count Register */
-#define DWT_PCSR (HWREG32(0xE000101C)) /* DWT Program Counter Sample Register */
-#define DWT_COMP0 (HWREG32(0xE0001020)) /* DWT Comparator Register 0 */
-#define DWT_MASK0 (HWREG32(0xE0001024)) /* DWT Mask Register 0 */
-#define DWT_FUNCTION0 (HWREG32(0xE0001028)) /* DWT Function Register 0 */
-#define DWT_COMP1 (HWREG32(0xE0001030)) /* DWT Comparator Register 1 */
-#define DWT_MASK1 (HWREG32(0xE0001034)) /* DWT Mask Register 1 */
-#define DWT_FUNCTION1 (HWREG32(0xE0001038)) /* DWT Function Register 1 */
-#define DWT_COMP2 (HWREG32(0xE0001040)) /* DWT Comparator Register 2 */
-#define DWT_MASK2 (HWREG32(0xE0001044)) /* DWT Mask Register 2 */
-#define DWT_FUNCTION2 (HWREG32(0xE0001048)) /* DWT Function Register 2 */
-#define DWT_COMP3 (HWREG32(0xE0001050)) /* DWT Comparator Register 3 */
-#define DWT_MASK3 (HWREG32(0xE0001054)) /* DWT Mask Register 3 */
-#define DWT_FUNCTION3 (HWREG32(0xE0001058)) /* DWT Function Register 3 */
-
-/* Register offsets from DWT_BASE address */
-#define OFS_DWT_CTRL (0x00000000) /* DWT Control Register */
-#define OFS_DWT_CYCCNT (0x00000004) /* DWT Current PC Sampler Cycle Count Register */
-#define OFS_DWT_CPICNT (0x00000008) /* DWT CPI Count Register */
-#define OFS_DWT_EXCCNT (0x0000000C) /* DWT Exception Overhead Count Register */
-#define OFS_DWT_SLEEPCNT (0x00000010) /* DWT Sleep Count Register */
-#define OFS_DWT_LSUCNT (0x00000014) /* DWT LSU Count Register */
-#define OFS_DWT_FOLDCNT (0x00000018) /* DWT Fold Count Register */
-#define OFS_DWT_PCSR (0x0000001C) /* DWT Program Counter Sample Register */
-#define OFS_DWT_COMP0 (0x00000020) /* DWT Comparator Register 0 */
-#define OFS_DWT_MASK0 (0x00000024) /* DWT Mask Register 0 */
-#define OFS_DWT_FUNCTION0 (0x00000028) /* DWT Function Register 0 */
-#define OFS_DWT_COMP1 (0x00000030) /* DWT Comparator Register 1 */
-#define OFS_DWT_MASK1 (0x00000034) /* DWT Mask Register 1 */
-#define OFS_DWT_FUNCTION1 (0x00000038) /* DWT Function Register 1 */
-#define OFS_DWT_COMP2 (0x00000040) /* DWT Comparator Register 2 */
-#define OFS_DWT_MASK2 (0x00000044) /* DWT Mask Register 2 */
-#define OFS_DWT_FUNCTION2 (0x00000048) /* DWT Function Register 2 */
-#define OFS_DWT_COMP3 (0x00000050) /* DWT Comparator Register 3 */
-#define OFS_DWT_MASK3 (0x00000054) /* DWT Mask Register 3 */
-#define OFS_DWT_FUNCTION3 (0x00000058) /* DWT Function Register 3 */
-
-
-//*****************************************************************************
-// EUSCI_A0 Registers
-//*****************************************************************************
-#define UCA0CTLW0 (HWREG16(0x40001000)) /* eUSCI_Ax Control Word Register 0 */
-#define UCA0CTLW0_SPI (HWREG16(0x40001000)) /* */
-#define UCA0CTLW1 (HWREG16(0x40001002)) /* eUSCI_Ax Control Word Register 1 */
-#define UCA0BRW (HWREG16(0x40001006)) /* eUSCI_Ax Baud Rate Control Word Register */
-#define UCA0BRW_SPI (HWREG16(0x40001006)) /* */
-#define UCA0MCTLW (HWREG16(0x40001008)) /* eUSCI_Ax Modulation Control Word Register */
-#define UCA0STATW (HWREG16(0x4000100A)) /* eUSCI_Ax Status Register */
-#define UCA0STATW_SPI (HWREG16(0x4000100A)) /* */
-#define UCA0RXBUF (HWREG16(0x4000100C)) /* eUSCI_Ax Receive Buffer Register */
-#define UCA0RXBUF_SPI (HWREG16(0x4000100C)) /* */
-#define UCA0TXBUF (HWREG16(0x4000100E)) /* eUSCI_Ax Transmit Buffer Register */
-#define UCA0TXBUF_SPI (HWREG16(0x4000100E)) /* */
-#define UCA0ABCTL (HWREG16(0x40001010)) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define UCA0IRCTL (HWREG16(0x40001012)) /* eUSCI_Ax IrDA Control Word Register */
-#define UCA0IE (HWREG16(0x4000101A)) /* eUSCI_Ax Interrupt Enable Register */
-#define UCA0IE_SPI (HWREG16(0x4000101A)) /* */
-#define UCA0IFG (HWREG16(0x4000101C)) /* eUSCI_Ax Interrupt Flag Register */
-#define UCA0IFG_SPI (HWREG16(0x4000101C)) /* */
-#define UCA0IV (HWREG16(0x4000101E)) /* eUSCI_Ax Interrupt Vector Register */
-#define UCA0IV_SPI (HWREG16(0x4000101E)) /* */
-
-/* Register offsets from EUSCI_A0_BASE address */
-#define OFS_UCA0CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
-#define OFS_UCA0CTLW0_SPI (0x0000) /* */
-#define OFS_UCA0CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
-#define OFS_UCA0BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
-#define OFS_UCA0BRW_SPI (0x0006) /* */
-#define OFS_UCA0MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
-#define OFS_UCA0STATW (0x000a) /* eUSCI_Ax Status Register */
-#define OFS_UCA0STATW_SPI (0x000a) /* */
-#define OFS_UCA0RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
-#define OFS_UCA0RXBUF_SPI (0x000c) /* */
-#define OFS_UCA0TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
-#define OFS_UCA0TXBUF_SPI (0x000e) /* */
-#define OFS_UCA0ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define OFS_UCA0IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
-#define OFS_UCA0IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
-#define OFS_UCA0IE_SPI (0x001a) /* */
-#define OFS_UCA0IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
-#define OFS_UCA0IFG_SPI (0x001c) /* */
-#define OFS_UCA0IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
-#define OFS_UCA0IV_SPI (0x001e) /* */
-
-#define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */
-#define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */
-#define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */
-#define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */
-#define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
-#define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */
-
-//*****************************************************************************
-// EUSCI_A1 Registers
-//*****************************************************************************
-#define UCA1CTLW0 (HWREG16(0x40001400)) /* eUSCI_Ax Control Word Register 0 */
-#define UCA1CTLW0_SPI (HWREG16(0x40001400)) /* */
-#define UCA1CTLW1 (HWREG16(0x40001402)) /* eUSCI_Ax Control Word Register 1 */
-#define UCA1BRW (HWREG16(0x40001406)) /* eUSCI_Ax Baud Rate Control Word Register */
-#define UCA1BRW_SPI (HWREG16(0x40001406)) /* */
-#define UCA1MCTLW (HWREG16(0x40001408)) /* eUSCI_Ax Modulation Control Word Register */
-#define UCA1STATW (HWREG16(0x4000140A)) /* eUSCI_Ax Status Register */
-#define UCA1STATW_SPI (HWREG16(0x4000140A)) /* */
-#define UCA1RXBUF (HWREG16(0x4000140C)) /* eUSCI_Ax Receive Buffer Register */
-#define UCA1RXBUF_SPI (HWREG16(0x4000140C)) /* */
-#define UCA1TXBUF (HWREG16(0x4000140E)) /* eUSCI_Ax Transmit Buffer Register */
-#define UCA1TXBUF_SPI (HWREG16(0x4000140E)) /* */
-#define UCA1ABCTL (HWREG16(0x40001410)) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define UCA1IRCTL (HWREG16(0x40001412)) /* eUSCI_Ax IrDA Control Word Register */
-#define UCA1IE (HWREG16(0x4000141A)) /* eUSCI_Ax Interrupt Enable Register */
-#define UCA1IE_SPI (HWREG16(0x4000141A)) /* */
-#define UCA1IFG (HWREG16(0x4000141C)) /* eUSCI_Ax Interrupt Flag Register */
-#define UCA1IFG_SPI (HWREG16(0x4000141C)) /* */
-#define UCA1IV (HWREG16(0x4000141E)) /* eUSCI_Ax Interrupt Vector Register */
-#define UCA1IV_SPI (HWREG16(0x4000141E)) /* */
-
-/* Register offsets from EUSCI_A1_BASE address */
-#define OFS_UCA1CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
-#define OFS_UCA1CTLW0_SPI (0x0000) /* */
-#define OFS_UCA1CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
-#define OFS_UCA1BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
-#define OFS_UCA1BRW_SPI (0x0006) /* */
-#define OFS_UCA1MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
-#define OFS_UCA1STATW (0x000a) /* eUSCI_Ax Status Register */
-#define OFS_UCA1STATW_SPI (0x000a) /* */
-#define OFS_UCA1RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
-#define OFS_UCA1RXBUF_SPI (0x000c) /* */
-#define OFS_UCA1TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
-#define OFS_UCA1TXBUF_SPI (0x000e) /* */
-#define OFS_UCA1ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define OFS_UCA1IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
-#define OFS_UCA1IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
-#define OFS_UCA1IE_SPI (0x001a) /* */
-#define OFS_UCA1IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
-#define OFS_UCA1IFG_SPI (0x001c) /* */
-#define OFS_UCA1IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
-#define OFS_UCA1IV_SPI (0x001e) /* */
-
-#define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */
-#define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */
-#define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */
-#define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */
-#define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
-#define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */
-
-//*****************************************************************************
-// EUSCI_A2 Registers
-//*****************************************************************************
-#define UCA2CTLW0 (HWREG16(0x40001800)) /* eUSCI_Ax Control Word Register 0 */
-#define UCA2CTLW0_SPI (HWREG16(0x40001800)) /* */
-#define UCA2CTLW1 (HWREG16(0x40001802)) /* eUSCI_Ax Control Word Register 1 */
-#define UCA2BRW (HWREG16(0x40001806)) /* eUSCI_Ax Baud Rate Control Word Register */
-#define UCA2BRW_SPI (HWREG16(0x40001806)) /* */
-#define UCA2MCTLW (HWREG16(0x40001808)) /* eUSCI_Ax Modulation Control Word Register */
-#define UCA2STATW (HWREG16(0x4000180A)) /* eUSCI_Ax Status Register */
-#define UCA2STATW_SPI (HWREG16(0x4000180A)) /* */
-#define UCA2RXBUF (HWREG16(0x4000180C)) /* eUSCI_Ax Receive Buffer Register */
-#define UCA2RXBUF_SPI (HWREG16(0x4000180C)) /* */
-#define UCA2TXBUF (HWREG16(0x4000180E)) /* eUSCI_Ax Transmit Buffer Register */
-#define UCA2TXBUF_SPI (HWREG16(0x4000180E)) /* */
-#define UCA2ABCTL (HWREG16(0x40001810)) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define UCA2IRCTL (HWREG16(0x40001812)) /* eUSCI_Ax IrDA Control Word Register */
-#define UCA2IE (HWREG16(0x4000181A)) /* eUSCI_Ax Interrupt Enable Register */
-#define UCA2IE_SPI (HWREG16(0x4000181A)) /* */
-#define UCA2IFG (HWREG16(0x4000181C)) /* eUSCI_Ax Interrupt Flag Register */
-#define UCA2IFG_SPI (HWREG16(0x4000181C)) /* */
-#define UCA2IV (HWREG16(0x4000181E)) /* eUSCI_Ax Interrupt Vector Register */
-#define UCA2IV_SPI (HWREG16(0x4000181E)) /* */
-
-/* Register offsets from EUSCI_A2_BASE address */
-#define OFS_UCA2CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
-#define OFS_UCA2CTLW0_SPI (0x0000) /* */
-#define OFS_UCA2CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
-#define OFS_UCA2BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
-#define OFS_UCA2BRW_SPI (0x0006) /* */
-#define OFS_UCA2MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
-#define OFS_UCA2STATW (0x000a) /* eUSCI_Ax Status Register */
-#define OFS_UCA2STATW_SPI (0x000a) /* */
-#define OFS_UCA2RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
-#define OFS_UCA2RXBUF_SPI (0x000c) /* */
-#define OFS_UCA2TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
-#define OFS_UCA2TXBUF_SPI (0x000e) /* */
-#define OFS_UCA2ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define OFS_UCA2IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
-#define OFS_UCA2IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
-#define OFS_UCA2IE_SPI (0x001a) /* */
-#define OFS_UCA2IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
-#define OFS_UCA2IFG_SPI (0x001c) /* */
-#define OFS_UCA2IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
-#define OFS_UCA2IV_SPI (0x001e) /* */
-
-#define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */
-#define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */
-#define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */
-#define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */
-#define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
-#define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */
-
-//*****************************************************************************
-// EUSCI_A3 Registers
-//*****************************************************************************
-#define UCA3CTLW0 (HWREG16(0x40001C00)) /* eUSCI_Ax Control Word Register 0 */
-#define UCA3CTLW0_SPI (HWREG16(0x40001C00)) /* */
-#define UCA3CTLW1 (HWREG16(0x40001C02)) /* eUSCI_Ax Control Word Register 1 */
-#define UCA3BRW (HWREG16(0x40001C06)) /* eUSCI_Ax Baud Rate Control Word Register */
-#define UCA3BRW_SPI (HWREG16(0x40001C06)) /* */
-#define UCA3MCTLW (HWREG16(0x40001C08)) /* eUSCI_Ax Modulation Control Word Register */
-#define UCA3STATW (HWREG16(0x40001C0A)) /* eUSCI_Ax Status Register */
-#define UCA3STATW_SPI (HWREG16(0x40001C0A)) /* */
-#define UCA3RXBUF (HWREG16(0x40001C0C)) /* eUSCI_Ax Receive Buffer Register */
-#define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) /* */
-#define UCA3TXBUF (HWREG16(0x40001C0E)) /* eUSCI_Ax Transmit Buffer Register */
-#define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) /* */
-#define UCA3ABCTL (HWREG16(0x40001C10)) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define UCA3IRCTL (HWREG16(0x40001C12)) /* eUSCI_Ax IrDA Control Word Register */
-#define UCA3IE (HWREG16(0x40001C1A)) /* eUSCI_Ax Interrupt Enable Register */
-#define UCA3IE_SPI (HWREG16(0x40001C1A)) /* */
-#define UCA3IFG (HWREG16(0x40001C1C)) /* eUSCI_Ax Interrupt Flag Register */
-#define UCA3IFG_SPI (HWREG16(0x40001C1C)) /* */
-#define UCA3IV (HWREG16(0x40001C1E)) /* eUSCI_Ax Interrupt Vector Register */
-#define UCA3IV_SPI (HWREG16(0x40001C1E)) /* */
-
-/* Register offsets from EUSCI_A3_BASE address */
-#define OFS_UCA3CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
-#define OFS_UCA3CTLW0_SPI (0x0000) /* */
-#define OFS_UCA3CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
-#define OFS_UCA3BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
-#define OFS_UCA3BRW_SPI (0x0006) /* */
-#define OFS_UCA3MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
-#define OFS_UCA3STATW (0x000a) /* eUSCI_Ax Status Register */
-#define OFS_UCA3STATW_SPI (0x000a) /* */
-#define OFS_UCA3RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
-#define OFS_UCA3RXBUF_SPI (0x000c) /* */
-#define OFS_UCA3TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
-#define OFS_UCA3TXBUF_SPI (0x000e) /* */
-#define OFS_UCA3ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
-#define OFS_UCA3IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
-#define OFS_UCA3IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
-#define OFS_UCA3IE_SPI (0x001a) /* */
-#define OFS_UCA3IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
-#define OFS_UCA3IFG_SPI (0x001c) /* */
-#define OFS_UCA3IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
-#define OFS_UCA3IV_SPI (0x001e) /* */
-
-#define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */
-#define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */
-#define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */
-#define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */
-#define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
-#define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */
-
-//*****************************************************************************
-// EUSCI_B0 Registers
-//*****************************************************************************
-#define UCB0CTLW0 (HWREG16(0x40002000)) /* eUSCI_Bx Control Word Register 0 */
-#define UCB0CTLW0_SPI (HWREG16(0x40002000)) /* */
-#define UCB0CTLW1 (HWREG16(0x40002002)) /* eUSCI_Bx Control Word Register 1 */
-#define UCB0BRW (HWREG16(0x40002006)) /* eUSCI_Bx Baud Rate Control Word Register */
-#define UCB0BRW_SPI (HWREG16(0x40002006)) /* */
-#define UCB0STATW (HWREG16(0x40002008)) /* eUSCI_Bx Status Register */
-#define UCB0STATW_SPI (HWREG16(0x40002008)) /* */
-#define UCB0TBCNT (HWREG16(0x4000200A)) /* eUSCI_Bx Byte Counter Threshold Register */
-#define UCB0RXBUF (HWREG16(0x4000200C)) /* eUSCI_Bx Receive Buffer Register */
-#define UCB0RXBUF_SPI (HWREG16(0x4000200C)) /* */
-#define UCB0TXBUF (HWREG16(0x4000200E)) /* eUSCI_Bx Transmit Buffer Register */
-#define UCB0TXBUF_SPI (HWREG16(0x4000200E)) /* */
-#define UCB0I2COA0 (HWREG16(0x40002014)) /* eUSCI_Bx I2C Own Address 0 Register */
-#define UCB0I2COA1 (HWREG16(0x40002016)) /* eUSCI_Bx I2C Own Address 1 Register */
-#define UCB0I2COA2 (HWREG16(0x40002018)) /* eUSCI_Bx I2C Own Address 2 Register */
-#define UCB0I2COA3 (HWREG16(0x4000201A)) /* eUSCI_Bx I2C Own Address 3 Register */
-#define UCB0ADDRX (HWREG16(0x4000201C)) /* eUSCI_Bx I2C Received Address Register */
-#define UCB0ADDMASK (HWREG16(0x4000201E)) /* eUSCI_Bx I2C Address Mask Register */
-#define UCB0I2CSA (HWREG16(0x40002020)) /* eUSCI_Bx I2C Slave Address Register */
-#define UCB0IE (HWREG16(0x4000202A)) /* eUSCI_Bx Interrupt Enable Register */
-#define UCB0IE_SPI (HWREG16(0x4000202A)) /* */
-#define UCB0IFG (HWREG16(0x4000202C)) /* eUSCI_Bx Interrupt Flag Register */
-#define UCB0IFG_SPI (HWREG16(0x4000202C)) /* */
-#define UCB0IV (HWREG16(0x4000202E)) /* eUSCI_Bx Interrupt Vector Register */
-#define UCB0IV_SPI (HWREG16(0x4000202E)) /* */
-
-/* Register offsets from EUSCI_B0_BASE address */
-#define OFS_UCB0CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
-#define OFS_UCB0CTLW0_SPI (0x0000) /* */
-#define OFS_UCB0CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
-#define OFS_UCB0BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
-#define OFS_UCB0BRW_SPI (0x0006) /* */
-#define OFS_UCB0STATW (0x0008) /* eUSCI_Bx Status Register */
-#define OFS_UCB0STATW_SPI (0x0008) /* */
-#define OFS_UCB0TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
-#define OFS_UCB0RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
-#define OFS_UCB0RXBUF_SPI (0x000c) /* */
-#define OFS_UCB0TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
-#define OFS_UCB0TXBUF_SPI (0x000e) /* */
-#define OFS_UCB0I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
-#define OFS_UCB0I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
-#define OFS_UCB0I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
-#define OFS_UCB0I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
-#define OFS_UCB0ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
-#define OFS_UCB0ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
-#define OFS_UCB0I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
-#define OFS_UCB0IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
-#define OFS_UCB0IE_SPI (0x002a) /* */
-#define OFS_UCB0IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
-#define OFS_UCB0IFG_SPI (0x002c) /* */
-#define OFS_UCB0IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
-#define OFS_UCB0IV_SPI (0x002e) /* */
-
-#define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */
-#define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */
-#define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */
-#define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */
-#define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */
-#define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */
-
-//*****************************************************************************
-// EUSCI_B1 Registers
-//*****************************************************************************
-#define UCB1CTLW0 (HWREG16(0x40002400)) /* eUSCI_Bx Control Word Register 0 */
-#define UCB1CTLW0_SPI (HWREG16(0x40002400)) /* */
-#define UCB1CTLW1 (HWREG16(0x40002402)) /* eUSCI_Bx Control Word Register 1 */
-#define UCB1BRW (HWREG16(0x40002406)) /* eUSCI_Bx Baud Rate Control Word Register */
-#define UCB1BRW_SPI (HWREG16(0x40002406)) /* */
-#define UCB1STATW (HWREG16(0x40002408)) /* eUSCI_Bx Status Register */
-#define UCB1STATW_SPI (HWREG16(0x40002408)) /* */
-#define UCB1TBCNT (HWREG16(0x4000240A)) /* eUSCI_Bx Byte Counter Threshold Register */
-#define UCB1RXBUF (HWREG16(0x4000240C)) /* eUSCI_Bx Receive Buffer Register */
-#define UCB1RXBUF_SPI (HWREG16(0x4000240C)) /* */
-#define UCB1TXBUF (HWREG16(0x4000240E)) /* eUSCI_Bx Transmit Buffer Register */
-#define UCB1TXBUF_SPI (HWREG16(0x4000240E)) /* */
-#define UCB1I2COA0 (HWREG16(0x40002414)) /* eUSCI_Bx I2C Own Address 0 Register */
-#define UCB1I2COA1 (HWREG16(0x40002416)) /* eUSCI_Bx I2C Own Address 1 Register */
-#define UCB1I2COA2 (HWREG16(0x40002418)) /* eUSCI_Bx I2C Own Address 2 Register */
-#define UCB1I2COA3 (HWREG16(0x4000241A)) /* eUSCI_Bx I2C Own Address 3 Register */
-#define UCB1ADDRX (HWREG16(0x4000241C)) /* eUSCI_Bx I2C Received Address Register */
-#define UCB1ADDMASK (HWREG16(0x4000241E)) /* eUSCI_Bx I2C Address Mask Register */
-#define UCB1I2CSA (HWREG16(0x40002420)) /* eUSCI_Bx I2C Slave Address Register */
-#define UCB1IE (HWREG16(0x4000242A)) /* eUSCI_Bx Interrupt Enable Register */
-#define UCB1IE_SPI (HWREG16(0x4000242A)) /* */
-#define UCB1IFG (HWREG16(0x4000242C)) /* eUSCI_Bx Interrupt Flag Register */
-#define UCB1IFG_SPI (HWREG16(0x4000242C)) /* */
-#define UCB1IV (HWREG16(0x4000242E)) /* eUSCI_Bx Interrupt Vector Register */
-#define UCB1IV_SPI (HWREG16(0x4000242E)) /* */
-
-/* Register offsets from EUSCI_B1_BASE address */
-#define OFS_UCB1CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
-#define OFS_UCB1CTLW0_SPI (0x0000) /* */
-#define OFS_UCB1CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
-#define OFS_UCB1BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
-#define OFS_UCB1BRW_SPI (0x0006) /* */
-#define OFS_UCB1STATW (0x0008) /* eUSCI_Bx Status Register */
-#define OFS_UCB1STATW_SPI (0x0008) /* */
-#define OFS_UCB1TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
-#define OFS_UCB1RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
-#define OFS_UCB1RXBUF_SPI (0x000c) /* */
-#define OFS_UCB1TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
-#define OFS_UCB1TXBUF_SPI (0x000e) /* */
-#define OFS_UCB1I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
-#define OFS_UCB1I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
-#define OFS_UCB1I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
-#define OFS_UCB1I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
-#define OFS_UCB1ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
-#define OFS_UCB1ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
-#define OFS_UCB1I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
-#define OFS_UCB1IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
-#define OFS_UCB1IE_SPI (0x002a) /* */
-#define OFS_UCB1IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
-#define OFS_UCB1IFG_SPI (0x002c) /* */
-#define OFS_UCB1IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
-#define OFS_UCB1IV_SPI (0x002e) /* */
-
-#define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */
-#define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */
-#define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */
-#define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */
-#define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */
-#define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */
-
-//*****************************************************************************
-// EUSCI_B2 Registers
-//*****************************************************************************
-#define UCB2CTLW0 (HWREG16(0x40002800)) /* eUSCI_Bx Control Word Register 0 */
-#define UCB2CTLW0_SPI (HWREG16(0x40002800)) /* */
-#define UCB2CTLW1 (HWREG16(0x40002802)) /* eUSCI_Bx Control Word Register 1 */
-#define UCB2BRW (HWREG16(0x40002806)) /* eUSCI_Bx Baud Rate Control Word Register */
-#define UCB2BRW_SPI (HWREG16(0x40002806)) /* */
-#define UCB2STATW (HWREG16(0x40002808)) /* eUSCI_Bx Status Register */
-#define UCB2STATW_SPI (HWREG16(0x40002808)) /* */
-#define UCB2TBCNT (HWREG16(0x4000280A)) /* eUSCI_Bx Byte Counter Threshold Register */
-#define UCB2RXBUF (HWREG16(0x4000280C)) /* eUSCI_Bx Receive Buffer Register */
-#define UCB2RXBUF_SPI (HWREG16(0x4000280C)) /* */
-#define UCB2TXBUF (HWREG16(0x4000280E)) /* eUSCI_Bx Transmit Buffer Register */
-#define UCB2TXBUF_SPI (HWREG16(0x4000280E)) /* */
-#define UCB2I2COA0 (HWREG16(0x40002814)) /* eUSCI_Bx I2C Own Address 0 Register */
-#define UCB2I2COA1 (HWREG16(0x40002816)) /* eUSCI_Bx I2C Own Address 1 Register */
-#define UCB2I2COA2 (HWREG16(0x40002818)) /* eUSCI_Bx I2C Own Address 2 Register */
-#define UCB2I2COA3 (HWREG16(0x4000281A)) /* eUSCI_Bx I2C Own Address 3 Register */
-#define UCB2ADDRX (HWREG16(0x4000281C)) /* eUSCI_Bx I2C Received Address Register */
-#define UCB2ADDMASK (HWREG16(0x4000281E)) /* eUSCI_Bx I2C Address Mask Register */
-#define UCB2I2CSA (HWREG16(0x40002820)) /* eUSCI_Bx I2C Slave Address Register */
-#define UCB2IE (HWREG16(0x4000282A)) /* eUSCI_Bx Interrupt Enable Register */
-#define UCB2IE_SPI (HWREG16(0x4000282A)) /* */
-#define UCB2IFG (HWREG16(0x4000282C)) /* eUSCI_Bx Interrupt Flag Register */
-#define UCB2IFG_SPI (HWREG16(0x4000282C)) /* */
-#define UCB2IV (HWREG16(0x4000282E)) /* eUSCI_Bx Interrupt Vector Register */
-#define UCB2IV_SPI (HWREG16(0x4000282E)) /* */
-
-/* Register offsets from EUSCI_B2_BASE address */
-#define OFS_UCB2CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
-#define OFS_UCB2CTLW0_SPI (0x0000) /* */
-#define OFS_UCB2CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
-#define OFS_UCB2BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
-#define OFS_UCB2BRW_SPI (0x0006) /* */
-#define OFS_UCB2STATW (0x0008) /* eUSCI_Bx Status Register */
-#define OFS_UCB2STATW_SPI (0x0008) /* */
-#define OFS_UCB2TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
-#define OFS_UCB2RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
-#define OFS_UCB2RXBUF_SPI (0x000c) /* */
-#define OFS_UCB2TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
-#define OFS_UCB2TXBUF_SPI (0x000e) /* */
-#define OFS_UCB2I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
-#define OFS_UCB2I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
-#define OFS_UCB2I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
-#define OFS_UCB2I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
-#define OFS_UCB2ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
-#define OFS_UCB2ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
-#define OFS_UCB2I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
-#define OFS_UCB2IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
-#define OFS_UCB2IE_SPI (0x002a) /* */
-#define OFS_UCB2IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
-#define OFS_UCB2IFG_SPI (0x002c) /* */
-#define OFS_UCB2IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
-#define OFS_UCB2IV_SPI (0x002e) /* */
-
-#define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */
-#define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */
-#define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */
-#define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */
-#define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */
-#define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */
-
-//*****************************************************************************
-// EUSCI_B3 Registers
-//*****************************************************************************
-#define UCB3CTLW0 (HWREG16(0x40002C00)) /* eUSCI_Bx Control Word Register 0 */
-#define UCB3CTLW0_SPI (HWREG16(0x40002C00)) /* */
-#define UCB3CTLW1 (HWREG16(0x40002C02)) /* eUSCI_Bx Control Word Register 1 */
-#define UCB3BRW (HWREG16(0x40002C06)) /* eUSCI_Bx Baud Rate Control Word Register */
-#define UCB3BRW_SPI (HWREG16(0x40002C06)) /* */
-#define UCB3STATW (HWREG16(0x40002C08)) /* eUSCI_Bx Status Register */
-#define UCB3STATW_SPI (HWREG16(0x40002C08)) /* */
-#define UCB3TBCNT (HWREG16(0x40002C0A)) /* eUSCI_Bx Byte Counter Threshold Register */
-#define UCB3RXBUF (HWREG16(0x40002C0C)) /* eUSCI_Bx Receive Buffer Register */
-#define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) /* */
-#define UCB3TXBUF (HWREG16(0x40002C0E)) /* eUSCI_Bx Transmit Buffer Register */
-#define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) /* */
-#define UCB3I2COA0 (HWREG16(0x40002C14)) /* eUSCI_Bx I2C Own Address 0 Register */
-#define UCB3I2COA1 (HWREG16(0x40002C16)) /* eUSCI_Bx I2C Own Address 1 Register */
-#define UCB3I2COA2 (HWREG16(0x40002C18)) /* eUSCI_Bx I2C Own Address 2 Register */
-#define UCB3I2COA3 (HWREG16(0x40002C1A)) /* eUSCI_Bx I2C Own Address 3 Register */
-#define UCB3ADDRX (HWREG16(0x40002C1C)) /* eUSCI_Bx I2C Received Address Register */
-#define UCB3ADDMASK (HWREG16(0x40002C1E)) /* eUSCI_Bx I2C Address Mask Register */
-#define UCB3I2CSA (HWREG16(0x40002C20)) /* eUSCI_Bx I2C Slave Address Register */
-#define UCB3IE (HWREG16(0x40002C2A)) /* eUSCI_Bx Interrupt Enable Register */
-#define UCB3IE_SPI (HWREG16(0x40002C2A)) /* */
-#define UCB3IFG (HWREG16(0x40002C2C)) /* eUSCI_Bx Interrupt Flag Register */
-#define UCB3IFG_SPI (HWREG16(0x40002C2C)) /* */
-#define UCB3IV (HWREG16(0x40002C2E)) /* eUSCI_Bx Interrupt Vector Register */
-#define UCB3IV_SPI (HWREG16(0x40002C2E)) /* */
-
-/* Register offsets from EUSCI_B3_BASE address */
-#define OFS_UCB3CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
-#define OFS_UCB3CTLW0_SPI (0x0000) /* */
-#define OFS_UCB3CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
-#define OFS_UCB3BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
-#define OFS_UCB3BRW_SPI (0x0006) /* */
-#define OFS_UCB3STATW (0x0008) /* eUSCI_Bx Status Register */
-#define OFS_UCB3STATW_SPI (0x0008) /* */
-#define OFS_UCB3TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
-#define OFS_UCB3RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
-#define OFS_UCB3RXBUF_SPI (0x000c) /* */
-#define OFS_UCB3TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
-#define OFS_UCB3TXBUF_SPI (0x000e) /* */
-#define OFS_UCB3I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
-#define OFS_UCB3I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
-#define OFS_UCB3I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
-#define OFS_UCB3I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
-#define OFS_UCB3ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
-#define OFS_UCB3ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
-#define OFS_UCB3I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
-#define OFS_UCB3IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
-#define OFS_UCB3IE_SPI (0x002a) /* */
-#define OFS_UCB3IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
-#define OFS_UCB3IFG_SPI (0x002c) /* */
-#define OFS_UCB3IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
-#define OFS_UCB3IV_SPI (0x002e) /* */
-
-#define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */
-#define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */
-#define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */
-#define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */
-#define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */
-#define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */
-
-//*****************************************************************************
-// FLCTL Registers
-//*****************************************************************************
-#define FLCTL_POWER_STAT (HWREG32(0x40011000)) /* Power Status Register */
-#define FLCTL_BANK0_RDCTL (HWREG32(0x40011010)) /* Bank0 Read Control Register */
-#define FLCTL_BANK1_RDCTL (HWREG32(0x40011014)) /* Bank1 Read Control Register */
-#define FLCTL_RDBRST_CTLSTAT (HWREG32(0x40011020)) /* Read Burst/Compare Control and Status Register */
-#define FLCTL_RDBRST_STARTADDR (HWREG32(0x40011024)) /* Read Burst/Compare Start Address Register */
-#define FLCTL_RDBRST_LEN (HWREG32(0x40011028)) /* Read Burst/Compare Length Register */
-#define FLCTL_RDBRST_FAILADDR (HWREG32(0x4001103C)) /* Read Burst/Compare Fail Address Register */
-#define FLCTL_RDBRST_FAILCNT (HWREG32(0x40011040)) /* Read Burst/Compare Fail Count Register */
-#define FLCTL_PRG_CTLSTAT (HWREG32(0x40011050)) /* Program Control and Status Register */
-#define FLCTL_PRGBRST_CTLSTAT (HWREG32(0x40011054)) /* Program Burst Control and Status Register */
-#define FLCTL_PRGBRST_STARTADDR (HWREG32(0x40011058)) /* Program Burst Start Address Register */
-#define FLCTL_PRGBRST_DATA0_0 (HWREG32(0x40011060)) /* Program Burst Data0 Register0 */
-#define FLCTL_PRGBRST_DATA0_1 (HWREG32(0x40011064)) /* Program Burst Data0 Register1 */
-#define FLCTL_PRGBRST_DATA0_2 (HWREG32(0x40011068)) /* Program Burst Data0 Register2 */
-#define FLCTL_PRGBRST_DATA0_3 (HWREG32(0x4001106C)) /* Program Burst Data0 Register3 */
-#define FLCTL_PRGBRST_DATA1_0 (HWREG32(0x40011070)) /* Program Burst Data1 Register0 */
-#define FLCTL_PRGBRST_DATA1_1 (HWREG32(0x40011074)) /* Program Burst Data1 Register1 */
-#define FLCTL_PRGBRST_DATA1_2 (HWREG32(0x40011078)) /* Program Burst Data1 Register2 */
-#define FLCTL_PRGBRST_DATA1_3 (HWREG32(0x4001107C)) /* Program Burst Data1 Register3 */
-#define FLCTL_PRGBRST_DATA2_0 (HWREG32(0x40011080)) /* Program Burst Data2 Register0 */
-#define FLCTL_PRGBRST_DATA2_1 (HWREG32(0x40011084)) /* Program Burst Data2 Register1 */
-#define FLCTL_PRGBRST_DATA2_2 (HWREG32(0x40011088)) /* Program Burst Data2 Register2 */
-#define FLCTL_PRGBRST_DATA2_3 (HWREG32(0x4001108C)) /* Program Burst Data2 Register3 */
-#define FLCTL_PRGBRST_DATA3_0 (HWREG32(0x40011090)) /* Program Burst Data3 Register0 */
-#define FLCTL_PRGBRST_DATA3_1 (HWREG32(0x40011094)) /* Program Burst Data3 Register1 */
-#define FLCTL_PRGBRST_DATA3_2 (HWREG32(0x40011098)) /* Program Burst Data3 Register2 */
-#define FLCTL_PRGBRST_DATA3_3 (HWREG32(0x4001109C)) /* Program Burst Data3 Register3 */
-#define FLCTL_ERASE_CTLSTAT (HWREG32(0x400110A0)) /* Erase Control and Status Register */
-#define FLCTL_ERASE_SECTADDR (HWREG32(0x400110A4)) /* Erase Sector Address Register */
-#define FLCTL_BANK0_INFO_WEPROT (HWREG32(0x400110B0)) /* Information Memory Bank0 Write/Erase Protection Register */
-#define FLCTL_BANK0_MAIN_WEPROT (HWREG32(0x400110B4)) /* Main Memory Bank0 Write/Erase Protection Register */
-#define FLCTL_BANK1_INFO_WEPROT (HWREG32(0x400110C0)) /* Information Memory Bank1 Write/Erase Protection Register */
-#define FLCTL_BANK1_MAIN_WEPROT (HWREG32(0x400110C4)) /* Main Memory Bank1 Write/Erase Protection Register */
-#define FLCTL_BMRK_CTLSTAT (HWREG32(0x400110D0)) /* Benchmark Control and Status Register */
-#define FLCTL_BMRK_IFETCH (HWREG32(0x400110D4)) /* Benchmark Instruction Fetch Count Register */
-#define FLCTL_BMRK_DREAD (HWREG32(0x400110D8)) /* Benchmark Data Read Count Register */
-#define FLCTL_BMRK_CMP (HWREG32(0x400110DC)) /* Benchmark Count Compare Register */
-#define FLCTL_IFG (HWREG32(0x400110F0)) /* Interrupt Flag Register */
-#define FLCTL_IE (HWREG32(0x400110F4)) /* Interrupt Enable Register */
-#define FLCTL_CLRIFG (HWREG32(0x400110F8)) /* Clear Interrupt Flag Register */
-#define FLCTL_SETIFG (HWREG32(0x400110FC)) /* Set Interrupt Flag Register */
-#define FLCTL_READ_TIMCTL (HWREG32(0x40011100)) /* Read Timing Control Register */
-#define FLCTL_READMARGIN_TIMCTL (HWREG32(0x40011104)) /* Read Margin Timing Control Register */
-#define FLCTL_PRGVER_TIMCTL (HWREG32(0x40011108)) /* Program Verify Timing Control Register */
-#define FLCTL_ERSVER_TIMCTL (HWREG32(0x4001110C)) /* Erase Verify Timing Control Register */
-#define FLCTL_LKGVER_TIMCTL (HWREG32(0x40011110)) /* Leakage Verify Timing Control Register */
-#define FLCTL_PROGRAM_TIMCTL (HWREG32(0x40011114)) /* Program Timing Control Register */
-#define FLCTL_ERASE_TIMCTL (HWREG32(0x40011118)) /* Erase Timing Control Register */
-#define FLCTL_MASSERASE_TIMCTL (HWREG32(0x4001111C)) /* Mass Erase Timing Control Register */
-#define FLCTL_BURSTPRG_TIMCTL (HWREG32(0x40011120)) /* Burst Program Timing Control Register */
-
-/* Register offsets from FLCTL_BASE address */
-#define OFS_FLCTL_POWER_STAT (0x00000000) /* Power Status Register */
-#define OFS_FLCTL_BANK0_RDCTL (0x00000010) /* Bank0 Read Control Register */
-#define OFS_FLCTL_BANK1_RDCTL (0x00000014) /* Bank1 Read Control Register */
-#define OFS_FLCTL_RDBRST_CTLSTAT (0x00000020) /* Read Burst/Compare Control and Status Register */
-#define OFS_FLCTL_RDBRST_STARTADDR (0x00000024) /* Read Burst/Compare Start Address Register */
-#define OFS_FLCTL_RDBRST_LEN (0x00000028) /* Read Burst/Compare Length Register */
-#define OFS_FLCTL_RDBRST_FAILADDR (0x0000003C) /* Read Burst/Compare Fail Address Register */
-#define OFS_FLCTL_RDBRST_FAILCNT (0x00000040) /* Read Burst/Compare Fail Count Register */
-#define OFS_FLCTL_PRG_CTLSTAT (0x00000050) /* Program Control and Status Register */
-#define OFS_FLCTL_PRGBRST_CTLSTAT (0x00000054) /* Program Burst Control and Status Register */
-#define OFS_FLCTL_PRGBRST_STARTADDR (0x00000058) /* Program Burst Start Address Register */
-#define OFS_FLCTL_PRGBRST_DATA0_0 (0x00000060) /* Program Burst Data0 Register0 */
-#define OFS_FLCTL_PRGBRST_DATA0_1 (0x00000064) /* Program Burst Data0 Register1 */
-#define OFS_FLCTL_PRGBRST_DATA0_2 (0x00000068) /* Program Burst Data0 Register2 */
-#define OFS_FLCTL_PRGBRST_DATA0_3 (0x0000006C) /* Program Burst Data0 Register3 */
-#define OFS_FLCTL_PRGBRST_DATA1_0 (0x00000070) /* Program Burst Data1 Register0 */
-#define OFS_FLCTL_PRGBRST_DATA1_1 (0x00000074) /* Program Burst Data1 Register1 */
-#define OFS_FLCTL_PRGBRST_DATA1_2 (0x00000078) /* Program Burst Data1 Register2 */
-#define OFS_FLCTL_PRGBRST_DATA1_3 (0x0000007C) /* Program Burst Data1 Register3 */
-#define OFS_FLCTL_PRGBRST_DATA2_0 (0x00000080) /* Program Burst Data2 Register0 */
-#define OFS_FLCTL_PRGBRST_DATA2_1 (0x00000084) /* Program Burst Data2 Register1 */
-#define OFS_FLCTL_PRGBRST_DATA2_2 (0x00000088) /* Program Burst Data2 Register2 */
-#define OFS_FLCTL_PRGBRST_DATA2_3 (0x0000008C) /* Program Burst Data2 Register3 */
-#define OFS_FLCTL_PRGBRST_DATA3_0 (0x00000090) /* Program Burst Data3 Register0 */
-#define OFS_FLCTL_PRGBRST_DATA3_1 (0x00000094) /* Program Burst Data3 Register1 */
-#define OFS_FLCTL_PRGBRST_DATA3_2 (0x00000098) /* Program Burst Data3 Register2 */
-#define OFS_FLCTL_PRGBRST_DATA3_3 (0x0000009C) /* Program Burst Data3 Register3 */
-#define OFS_FLCTL_ERASE_CTLSTAT (0x000000A0) /* Erase Control and Status Register */
-#define OFS_FLCTL_ERASE_SECTADDR (0x000000A4) /* Erase Sector Address Register */
-#define OFS_FLCTL_BANK0_INFO_WEPROT (0x000000B0) /* Information Memory Bank0 Write/Erase Protection Register */
-#define OFS_FLCTL_BANK0_MAIN_WEPROT (0x000000B4) /* Main Memory Bank0 Write/Erase Protection Register */
-#define OFS_FLCTL_BANK1_INFO_WEPROT (0x000000C0) /* Information Memory Bank1 Write/Erase Protection Register */
-#define OFS_FLCTL_BANK1_MAIN_WEPROT (0x000000C4) /* Main Memory Bank1 Write/Erase Protection Register */
-#define OFS_FLCTL_BMRK_CTLSTAT (0x000000D0) /* Benchmark Control and Status Register */
-#define OFS_FLCTL_BMRK_IFETCH (0x000000D4) /* Benchmark Instruction Fetch Count Register */
-#define OFS_FLCTL_BMRK_DREAD (0x000000D8) /* Benchmark Data Read Count Register */
-#define OFS_FLCTL_BMRK_CMP (0x000000DC) /* Benchmark Count Compare Register */
-#define OFS_FLCTL_IFG (0x000000F0) /* Interrupt Flag Register */
-#define OFS_FLCTL_IE (0x000000F4) /* Interrupt Enable Register */
-#define OFS_FLCTL_CLRIFG (0x000000F8) /* Clear Interrupt Flag Register */
-#define OFS_FLCTL_SETIFG (0x000000FC) /* Set Interrupt Flag Register */
-#define OFS_FLCTL_READ_TIMCTL (0x00000100) /* Read Timing Control Register */
-#define OFS_FLCTL_READMARGIN_TIMCTL (0x00000104) /* Read Margin Timing Control Register */
-#define OFS_FLCTL_PRGVER_TIMCTL (0x00000108) /* Program Verify Timing Control Register */
-#define OFS_FLCTL_ERSVER_TIMCTL (0x0000010C) /* Erase Verify Timing Control Register */
-#define OFS_FLCTL_LKGVER_TIMCTL (0x00000110) /* Leakage Verify Timing Control Register */
-#define OFS_FLCTL_PROGRAM_TIMCTL (0x00000114) /* Program Timing Control Register */
-#define OFS_FLCTL_ERASE_TIMCTL (0x00000118) /* Erase Timing Control Register */
-#define OFS_FLCTL_MASSERASE_TIMCTL (0x0000011C) /* Mass Erase Timing Control Register */
-#define OFS_FLCTL_BURSTPRG_TIMCTL (0x00000120) /* Burst Program Timing Control Register */
-
-
-//*****************************************************************************
-// FPB Registers
-//*****************************************************************************
-#define FPB_FP_CTRL (HWREG32(0xE0002000)) /* Flash Patch Control Register */
-#define FPB_FP_REMAP (HWREG32(0xE0002004)) /* Flash Patch Remap Register */
-#define FPB_FP_COMP0 (HWREG32(0xE0002008)) /* Flash Patch Comparator Registers */
-#define FPB_FP_COMP1 (HWREG32(0xE000200C)) /* Flash Patch Comparator Registers */
-#define FPB_FP_COMP2 (HWREG32(0xE0002010)) /* Flash Patch Comparator Registers */
-#define FPB_FP_COMP3 (HWREG32(0xE0002014)) /* Flash Patch Comparator Registers */
-#define FPB_FP_COMP4 (HWREG32(0xE0002018)) /* Flash Patch Comparator Registers */
-#define FPB_FP_COMP5 (HWREG32(0xE000201C)) /* Flash Patch Comparator Registers */
-#define FPB_FP_COMP6 (HWREG32(0xE0002020)) /* Flash Patch Comparator Registers */
-#define FPB_FP_COMP7 (HWREG32(0xE0002024)) /* Flash Patch Comparator Registers */
-
-/* Register offsets from FPB_BASE address */
-#define OFS_FPB_FP_CTRL (0x00000000) /* Flash Patch Control Register */
-#define OFS_FPB_FP_REMAP (0x00000004) /* Flash Patch Remap Register */
-#define OFS_FPB_FP_COMP0 (0x00000008) /* Flash Patch Comparator Registers */
-#define OFS_FPB_FP_COMP1 (0x0000000C) /* Flash Patch Comparator Registers */
-#define OFS_FPB_FP_COMP2 (0x00000010) /* Flash Patch Comparator Registers */
-#define OFS_FPB_FP_COMP3 (0x00000014) /* Flash Patch Comparator Registers */
-#define OFS_FPB_FP_COMP4 (0x00000018) /* Flash Patch Comparator Registers */
-#define OFS_FPB_FP_COMP5 (0x0000001C) /* Flash Patch Comparator Registers */
-#define OFS_FPB_FP_COMP6 (0x00000020) /* Flash Patch Comparator Registers */
-#define OFS_FPB_FP_COMP7 (0x00000024) /* Flash Patch Comparator Registers */
-
-
-//*****************************************************************************
-// FPU Registers
-//*****************************************************************************
-#define FPU_FPCCR (HWREG32(0xE000EF34)) /* Floating Point Context Control Register */
-#define FPU_FPCAR (HWREG32(0xE000EF38)) /* Floating-Point Context Address Register */
-#define FPU_FPDSCR (HWREG32(0xE000EF3C)) /* Floating Point Default Status Control Register */
-#define FPU_MVFR0 (HWREG32(0xE000EF40)) /* Media and FP Feature Register 0 (MVFR0) */
-#define FPU_MVFR1 (HWREG32(0xE000EF44)) /* Media and FP Feature Register 1 (MVFR1) */
-
-/* Register offsets from FPU_BASE address */
-#define OFS_FPU_FPCCR (0x00000F34) /* Floating Point Context Control Register */
-#define OFS_FPU_FPCAR (0x00000F38) /* Floating-Point Context Address Register */
-#define OFS_FPU_FPDSCR (0x00000F3C) /* Floating Point Default Status Control Register */
-#define OFS_FPU_MVFR0 (0x00000F40) /* Media and FP Feature Register 0 (MVFR0) */
-#define OFS_FPU_MVFR1 (0x00000F44) /* Media and FP Feature Register 1 (MVFR1) */
-
-
-//*****************************************************************************
-// ITM Registers
-//*****************************************************************************
-#define ITM_STIM0 (HWREG32(0xE0000000)) /* ITM Stimulus Port 0 */
-#define ITM_STIM1 (HWREG32(0xE0000004)) /* ITM Stimulus Port 1 */
-#define ITM_STIM2 (HWREG32(0xE0000008)) /* ITM Stimulus Port 2 */
-#define ITM_STIM3 (HWREG32(0xE000000C)) /* ITM Stimulus Port 3 */
-#define ITM_STIM4 (HWREG32(0xE0000010)) /* ITM Stimulus Port 4 */
-#define ITM_STIM5 (HWREG32(0xE0000014)) /* ITM Stimulus Port 5 */
-#define ITM_STIM6 (HWREG32(0xE0000018)) /* ITM Stimulus Port 6 */
-#define ITM_STIM7 (HWREG32(0xE000001C)) /* ITM Stimulus Port 7 */
-#define ITM_STIM8 (HWREG32(0xE0000020)) /* ITM Stimulus Port 8 */
-#define ITM_STIM9 (HWREG32(0xE0000024)) /* ITM Stimulus Port 9 */
-#define ITM_STIM10 (HWREG32(0xE0000028)) /* ITM Stimulus Port 10 */
-#define ITM_STIM11 (HWREG32(0xE000002C)) /* ITM Stimulus Port 11 */
-#define ITM_STIM12 (HWREG32(0xE0000030)) /* ITM Stimulus Port 12 */
-#define ITM_STIM13 (HWREG32(0xE0000034)) /* ITM Stimulus Port 13 */
-#define ITM_STIM14 (HWREG32(0xE0000038)) /* ITM Stimulus Port 14 */
-#define ITM_STIM15 (HWREG32(0xE000003C)) /* ITM Stimulus Port 15 */
-#define ITM_STIM16 (HWREG32(0xE0000040)) /* ITM Stimulus Port 16 */
-#define ITM_STIM17 (HWREG32(0xE0000044)) /* ITM Stimulus Port 17 */
-#define ITM_STIM18 (HWREG32(0xE0000048)) /* ITM Stimulus Port 18 */
-#define ITM_STIM19 (HWREG32(0xE000004C)) /* ITM Stimulus Port 19 */
-#define ITM_STIM20 (HWREG32(0xE0000050)) /* ITM Stimulus Port 20 */
-#define ITM_STIM21 (HWREG32(0xE0000054)) /* ITM Stimulus Port 21 */
-#define ITM_STIM22 (HWREG32(0xE0000058)) /* ITM Stimulus Port 22 */
-#define ITM_STIM23 (HWREG32(0xE000005C)) /* ITM Stimulus Port 23 */
-#define ITM_STIM24 (HWREG32(0xE0000060)) /* ITM Stimulus Port 24 */
-#define ITM_STIM25 (HWREG32(0xE0000064)) /* ITM Stimulus Port 25 */
-#define ITM_STIM26 (HWREG32(0xE0000068)) /* ITM Stimulus Port 26 */
-#define ITM_STIM27 (HWREG32(0xE000006C)) /* ITM Stimulus Port 27 */
-#define ITM_STIM28 (HWREG32(0xE0000070)) /* ITM Stimulus Port 28 */
-#define ITM_STIM29 (HWREG32(0xE0000074)) /* ITM Stimulus Port 29 */
-#define ITM_STIM30 (HWREG32(0xE0000078)) /* ITM Stimulus Port 30 */
-#define ITM_STIM31 (HWREG32(0xE000007C)) /* ITM Stimulus Port 31 */
-#define ITM_TER (HWREG32(0xE0000E00)) /* ITM Trace Enable Register */
-#define ITM_TPR (HWREG32(0xE0000E40)) /* ITM Trace Privilege Register */
-#define ITM_TCR (HWREG32(0xE0000E80)) /* ITM Trace Control Register */
-#define ITM_IWR (HWREG32(0xE0000EF8)) /* ITM Integration Write Register */
-#define ITM_IMCR (HWREG32(0xE0000F00)) /* ITM Integration Mode Control Register */
-#define ITM_LAR (HWREG32(0xE0000FB0)) /* ITM Lock Access Register */
-#define ITM_LSR (HWREG32(0xE0000FB4)) /* ITM Lock Status Register */
-
-/* Register offsets from ITM_BASE address */
-#define OFS_ITM_STIM0 (0x00000000) /* ITM Stimulus Port 0 */
-#define OFS_ITM_STIM1 (0x00000004) /* ITM Stimulus Port 1 */
-#define OFS_ITM_STIM2 (0x00000008) /* ITM Stimulus Port 2 */
-#define OFS_ITM_STIM3 (0x0000000C) /* ITM Stimulus Port 3 */
-#define OFS_ITM_STIM4 (0x00000010) /* ITM Stimulus Port 4 */
-#define OFS_ITM_STIM5 (0x00000014) /* ITM Stimulus Port 5 */
-#define OFS_ITM_STIM6 (0x00000018) /* ITM Stimulus Port 6 */
-#define OFS_ITM_STIM7 (0x0000001C) /* ITM Stimulus Port 7 */
-#define OFS_ITM_STIM8 (0x00000020) /* ITM Stimulus Port 8 */
-#define OFS_ITM_STIM9 (0x00000024) /* ITM Stimulus Port 9 */
-#define OFS_ITM_STIM10 (0x00000028) /* ITM Stimulus Port 10 */
-#define OFS_ITM_STIM11 (0x0000002C) /* ITM Stimulus Port 11 */
-#define OFS_ITM_STIM12 (0x00000030) /* ITM Stimulus Port 12 */
-#define OFS_ITM_STIM13 (0x00000034) /* ITM Stimulus Port 13 */
-#define OFS_ITM_STIM14 (0x00000038) /* ITM Stimulus Port 14 */
-#define OFS_ITM_STIM15 (0x0000003C) /* ITM Stimulus Port 15 */
-#define OFS_ITM_STIM16 (0x00000040) /* ITM Stimulus Port 16 */
-#define OFS_ITM_STIM17 (0x00000044) /* ITM Stimulus Port 17 */
-#define OFS_ITM_STIM18 (0x00000048) /* ITM Stimulus Port 18 */
-#define OFS_ITM_STIM19 (0x0000004C) /* ITM Stimulus Port 19 */
-#define OFS_ITM_STIM20 (0x00000050) /* ITM Stimulus Port 20 */
-#define OFS_ITM_STIM21 (0x00000054) /* ITM Stimulus Port 21 */
-#define OFS_ITM_STIM22 (0x00000058) /* ITM Stimulus Port 22 */
-#define OFS_ITM_STIM23 (0x0000005C) /* ITM Stimulus Port 23 */
-#define OFS_ITM_STIM24 (0x00000060) /* ITM Stimulus Port 24 */
-#define OFS_ITM_STIM25 (0x00000064) /* ITM Stimulus Port 25 */
-#define OFS_ITM_STIM26 (0x00000068) /* ITM Stimulus Port 26 */
-#define OFS_ITM_STIM27 (0x0000006C) /* ITM Stimulus Port 27 */
-#define OFS_ITM_STIM28 (0x00000070) /* ITM Stimulus Port 28 */
-#define OFS_ITM_STIM29 (0x00000074) /* ITM Stimulus Port 29 */
-#define OFS_ITM_STIM30 (0x00000078) /* ITM Stimulus Port 30 */
-#define OFS_ITM_STIM31 (0x0000007C) /* ITM Stimulus Port 31 */
-#define OFS_ITM_TER (0x00000E00) /* ITM Trace Enable Register */
-#define OFS_ITM_TPR (0x00000E40) /* ITM Trace Privilege Register */
-#define OFS_ITM_TCR (0x00000E80) /* ITM Trace Control Register */
-#define OFS_ITM_IWR (0x00000EF8) /* ITM Integration Write Register */
-#define OFS_ITM_IMCR (0x00000F00) /* ITM Integration Mode Control Register */
-#define OFS_ITM_LAR (0x00000FB0) /* ITM Lock Access Register */
-#define OFS_ITM_LSR (0x00000FB4) /* ITM Lock Status Register */
-
-
-//*****************************************************************************
-// MPU Registers
-//*****************************************************************************
-#define MPU_TYPE (HWREG32(0xE000ED90)) /* MPU Type Register */
-#define MPU_CTRL (HWREG32(0xE000ED94)) /* MPU Control Register */
-#define MPU_RNR (HWREG32(0xE000ED98)) /* MPU Region Number Register */
-#define MPU_RBAR (HWREG32(0xE000ED9C)) /* MPU Region Base Address Register */
-#define MPU_RASR (HWREG32(0xE000EDA0)) /* MPU Region Attribute and Size Register */
-#define MPU_RBAR_A1 (HWREG32(0xE000EDA4)) /* MPU Alias 1 Region Base Address register */
-#define MPU_RASR_A1 (HWREG32(0xE000EDA8)) /* MPU Alias 1 Region Attribute and Size register */
-#define MPU_RBAR_A2 (HWREG32(0xE000EDAC)) /* MPU Alias 2 Region Base Address register */
-#define MPU_RASR_A2 (HWREG32(0xE000EDB0)) /* MPU Alias 2 Region Attribute and Size register */
-#define MPU_RBAR_A3 (HWREG32(0xE000EDB4)) /* MPU Alias 3 Region Base Address register */
-#define MPU_RASR_A3 (HWREG32(0xE000EDB8)) /* MPU Alias 3 Region Attribute and Size register */
-
-/* Register offsets from MPU_BASE address */
-#define OFS_MPU_TYPE (0x00000D90) /* MPU Type Register */
-#define OFS_MPU_CTRL (0x00000D94) /* MPU Control Register */
-#define OFS_MPU_RNR (0x00000D98) /* MPU Region Number Register */
-#define OFS_MPU_RBAR (0x00000D9C) /* MPU Region Base Address Register */
-#define OFS_MPU_RASR (0x00000DA0) /* MPU Region Attribute and Size Register */
-#define OFS_MPU_RBAR_A1 (0x00000DA4) /* MPU Alias 1 Region Base Address register */
-#define OFS_MPU_RASR_A1 (0x00000DA8) /* MPU Alias 1 Region Attribute and Size register */
-#define OFS_MPU_RBAR_A2 (0x00000DAC) /* MPU Alias 2 Region Base Address register */
-#define OFS_MPU_RASR_A2 (0x00000DB0) /* MPU Alias 2 Region Attribute and Size register */
-#define OFS_MPU_RBAR_A3 (0x00000DB4) /* MPU Alias 3 Region Base Address register */
-#define OFS_MPU_RASR_A3 (0x00000DB8) /* MPU Alias 3 Region Attribute and Size register */
-
-
-//*****************************************************************************
-// NVIC Registers
-//*****************************************************************************
-#define NVIC_ISER0 (HWREG32(0xE000E100)) /* Irq 0 to 31 Set Enable Register */
-#define NVIC_ISER1 (HWREG32(0xE000E104)) /* Irq 32 to 63 Set Enable Register */
-#define NVIC_ICER0 (HWREG32(0xE000E180)) /* Irq 0 to 31 Clear Enable Register */
-#define NVIC_ICER1 (HWREG32(0xE000E184)) /* Irq 32 to 63 Clear Enable Register */
-#define NVIC_ISPR0 (HWREG32(0xE000E200)) /* Irq 0 to 31 Set Pending Register */
-#define NVIC_ISPR1 (HWREG32(0xE000E204)) /* Irq 32 to 63 Set Pending Register */
-#define NVIC_ICPR0 (HWREG32(0xE000E280)) /* Irq 0 to 31 Clear Pending Register */
-#define NVIC_ICPR1 (HWREG32(0xE000E284)) /* Irq 32 to 63 Clear Pending Register */
-#define NVIC_IABR0 (HWREG32(0xE000E300)) /* Irq 0 to 31 Active Bit Register */
-#define NVIC_IABR1 (HWREG32(0xE000E304)) /* Irq 32 to 63 Active Bit Register */
-#define NVIC_IPR0 (HWREG32(0xE000E400)) /* Irq 0 to 3 Priority Register */
-#define NVIC_IPR1 (HWREG32(0xE000E404)) /* Irq 4 to 7 Priority Register */
-#define NVIC_IPR2 (HWREG32(0xE000E408)) /* Irq 8 to 11 Priority Register */
-#define NVIC_IPR3 (HWREG32(0xE000E40C)) /* Irq 12 to 15 Priority Register */
-#define NVIC_IPR4 (HWREG32(0xE000E410)) /* Irq 16 to 19 Priority Register */
-#define NVIC_IPR5 (HWREG32(0xE000E414)) /* Irq 20 to 23 Priority Register */
-#define NVIC_IPR6 (HWREG32(0xE000E418)) /* Irq 24 to 27 Priority Register */
-#define NVIC_IPR7 (HWREG32(0xE000E41C)) /* Irq 28 to 31 Priority Register */
-#define NVIC_IPR8 (HWREG32(0xE000E420)) /* Irq 32 to 35 Priority Register */
-#define NVIC_IPR9 (HWREG32(0xE000E424)) /* Irq 36 to 39 Priority Register */
-#define NVIC_IPR10 (HWREG32(0xE000E428)) /* Irq 40 to 43 Priority Register */
-#define NVIC_IPR11 (HWREG32(0xE000E42C)) /* Irq 44 to 47 Priority Register */
-#define NVIC_IPR12 (HWREG32(0xE000E430)) /* Irq 48 to 51 Priority Register */
-#define NVIC_IPR13 (HWREG32(0xE000E434)) /* Irq 52 to 55 Priority Register */
-#define NVIC_IPR14 (HWREG32(0xE000E438)) /* Irq 56 to 59 Priority Register */
-#define NVIC_IPR15 (HWREG32(0xE000E43C)) /* Irq 60 to 63 Priority Register */
-#define NVIC_STIR (HWREG32(0xE000EF00)) /* Software Trigger Interrupt Register */
-
-/* Register offsets from NVIC_BASE address */
-#define OFS_NVIC_ISER0 (0x00000100) /* Irq 0 to 31 Set Enable Register */
-#define OFS_NVIC_ISER1 (0x00000104) /* Irq 32 to 63 Set Enable Register */
-#define OFS_NVIC_ICER0 (0x00000180) /* Irq 0 to 31 Clear Enable Register */
-#define OFS_NVIC_ICER1 (0x00000184) /* Irq 32 to 63 Clear Enable Register */
-#define OFS_NVIC_ISPR0 (0x00000200) /* Irq 0 to 31 Set Pending Register */
-#define OFS_NVIC_ISPR1 (0x00000204) /* Irq 32 to 63 Set Pending Register */
-#define OFS_NVIC_ICPR0 (0x00000280) /* Irq 0 to 31 Clear Pending Register */
-#define OFS_NVIC_ICPR1 (0x00000284) /* Irq 32 to 63 Clear Pending Register */
-#define OFS_NVIC_IABR0 (0x00000300) /* Irq 0 to 31 Active Bit Register */
-#define OFS_NVIC_IABR1 (0x00000304) /* Irq 32 to 63 Active Bit Register */
-#define OFS_NVIC_IPR0 (0x00000400) /* Irq 0 to 3 Priority Register */
-#define OFS_NVIC_IPR1 (0x00000404) /* Irq 4 to 7 Priority Register */
-#define OFS_NVIC_IPR2 (0x00000408) /* Irq 8 to 11 Priority Register */
-#define OFS_NVIC_IPR3 (0x0000040C) /* Irq 12 to 15 Priority Register */
-#define OFS_NVIC_IPR4 (0x00000410) /* Irq 16 to 19 Priority Register */
-#define OFS_NVIC_IPR5 (0x00000414) /* Irq 20 to 23 Priority Register */
-#define OFS_NVIC_IPR6 (0x00000418) /* Irq 24 to 27 Priority Register */
-#define OFS_NVIC_IPR7 (0x0000041C) /* Irq 28 to 31 Priority Register */
-#define OFS_NVIC_IPR8 (0x00000420) /* Irq 32 to 35 Priority Register */
-#define OFS_NVIC_IPR9 (0x00000424) /* Irq 36 to 39 Priority Register */
-#define OFS_NVIC_IPR10 (0x00000428) /* Irq 40 to 43 Priority Register */
-#define OFS_NVIC_IPR11 (0x0000042C) /* Irq 44 to 47 Priority Register */
-#define OFS_NVIC_IPR12 (0x00000430) /* Irq 48 to 51 Priority Register */
-#define OFS_NVIC_IPR13 (0x00000434) /* Irq 52 to 55 Priority Register */
-#define OFS_NVIC_IPR14 (0x00000438) /* Irq 56 to 59 Priority Register */
-#define OFS_NVIC_IPR15 (0x0000043C) /* Irq 60 to 63 Priority Register */
-#define OFS_NVIC_STIR (0x00000F00) /* Software Trigger Interrupt Register */
-
-
-//*****************************************************************************
-// PCM Registers
-//*****************************************************************************
-#define PCMCTL0 (HWREG32(0x40010000)) /* Control 0 Register */
-#define PCMCTL1 (HWREG32(0x40010004)) /* Control 1 Register */
-#define PCMIE (HWREG32(0x40010008)) /* Interrupt Enable Register */
-#define PCMIFG (HWREG32(0x4001000C)) /* Interrupt Flag Register */
-#define PCMCLRIFG (HWREG32(0x40010010)) /* Clear Interrupt Flag Register */
-
-/* Register offsets from PCM_BASE address */
-#define OFS_PCMCTL0 (0x00000000) /* Control 0 Register */
-#define OFS_PCMCTL1 (0x00000004) /* Control 1 Register */
-#define OFS_PCMIE (0x00000008) /* Interrupt Enable Register */
-#define OFS_PCMIFG (0x0000000c) /* Interrupt Flag Register */
-#define OFS_PCMCLRIFG (0x00000010) /* Clear Interrupt Flag Register */
-
-
-//*****************************************************************************
-// PMAP Registers
-//*****************************************************************************
-#define PMAPKEYID (HWREG16(0x40005000)) /* Port Mapping Key Register */
-#define PMAPCTL (HWREG16(0x40005002)) /* Port Mapping Control Register */
-#define P1MAP01 (HWREG16(0x40005008)) /* Port mapping register, P1.0 and P1.1 */
-#define P1MAP23 (HWREG16(0x4000500A)) /* Port mapping register, P1.2 and P1.3 */
-#define P1MAP45 (HWREG16(0x4000500C)) /* Port mapping register, P1.4 and P1.5 */
-#define P1MAP67 (HWREG16(0x4000500E)) /* Port mapping register, P1.6 and P1.7 */
-#define P2MAP01 (HWREG16(0x40005010)) /* Port mapping register, P2.0 and P2.1 */
-#define P2MAP23 (HWREG16(0x40005012)) /* Port mapping register, P2.2 and P2.3 */
-#define P2MAP45 (HWREG16(0x40005014)) /* Port mapping register, P2.4 and P2.5 */
-#define P2MAP67 (HWREG16(0x40005016)) /* Port mapping register, P2.6 and P2.7 */
-#define P3MAP01 (HWREG16(0x40005018)) /* Port mapping register, P3.0 and P3.1 */
-#define P3MAP23 (HWREG16(0x4000501A)) /* Port mapping register, P3.2 and P3.3 */
-#define P3MAP45 (HWREG16(0x4000501C)) /* Port mapping register, P3.4 and P3.5 */
-#define P3MAP67 (HWREG16(0x4000501E)) /* Port mapping register, P3.6 and P3.7 */
-#define P4MAP01 (HWREG16(0x40005020)) /* Port mapping register, P4.0 and P4.1 */
-#define P4MAP23 (HWREG16(0x40005022)) /* Port mapping register, P4.2 and P4.3 */
-#define P4MAP45 (HWREG16(0x40005024)) /* Port mapping register, P4.4 and P4.5 */
-#define P4MAP67 (HWREG16(0x40005026)) /* Port mapping register, P4.6 and P4.7 */
-#define P5MAP01 (HWREG16(0x40005028)) /* Port mapping register, P5.0 and P5.1 */
-#define P5MAP23 (HWREG16(0x4000502A)) /* Port mapping register, P5.2 and P5.3 */
-#define P5MAP45 (HWREG16(0x4000502C)) /* Port mapping register, P5.4 and P5.5 */
-#define P5MAP67 (HWREG16(0x4000502E)) /* Port mapping register, P5.6 and P5.7 */
-#define P6MAP01 (HWREG16(0x40005030)) /* Port mapping register, P6.0 and P6.1 */
-#define P6MAP23 (HWREG16(0x40005032)) /* Port mapping register, P6.2 and P6.3 */
-#define P6MAP45 (HWREG16(0x40005034)) /* Port mapping register, P6.4 and P6.5 */
-#define P6MAP67 (HWREG16(0x40005036)) /* Port mapping register, P6.6 and P6.7 */
-#define P7MAP01 (HWREG16(0x40005038)) /* Port mapping register, P7.0 and P7.1 */
-#define P7MAP23 (HWREG16(0x4000503A)) /* Port mapping register, P7.2 and P7.3 */
-#define P7MAP45 (HWREG16(0x4000503C)) /* Port mapping register, P7.4 and P7.5 */
-#define P7MAP67 (HWREG16(0x4000503E)) /* Port mapping register, P7.6 and P7.7 */
-
-/* Register offsets from PMAP_BASE address */
-#define OFS_PMAPKEYID (0x0000) /* Port Mapping Key Register */
-#define OFS_PMAPCTL (0x0002) /* Port Mapping Control Register */
-#define OFS_P1MAP01 (0x0008) /* Port mapping register, P1.0 and P1.1 */
-#define OFS_P1MAP23 (0x000a) /* Port mapping register, P1.2 and P1.3 */
-#define OFS_P1MAP45 (0x000c) /* Port mapping register, P1.4 and P1.5 */
-#define OFS_P1MAP67 (0x000e) /* Port mapping register, P1.6 and P1.7 */
-#define OFS_P2MAP01 (0x0010) /* Port mapping register, P2.0 and P2.1 */
-#define OFS_P2MAP23 (0x0012) /* Port mapping register, P2.2 and P2.3 */
-#define OFS_P2MAP45 (0x0014) /* Port mapping register, P2.4 and P2.5 */
-#define OFS_P2MAP67 (0x0016) /* Port mapping register, P2.6 and P2.7 */
-#define OFS_P3MAP01 (0x0018) /* Port mapping register, P3.0 and P3.1 */
-#define OFS_P3MAP23 (0x001a) /* Port mapping register, P3.2 and P3.3 */
-#define OFS_P3MAP45 (0x001c) /* Port mapping register, P3.4 and P3.5 */
-#define OFS_P3MAP67 (0x001e) /* Port mapping register, P3.6 and P3.7 */
-#define OFS_P4MAP01 (0x0020) /* Port mapping register, P4.0 and P4.1 */
-#define OFS_P4MAP23 (0x0022) /* Port mapping register, P4.2 and P4.3 */
-#define OFS_P4MAP45 (0x0024) /* Port mapping register, P4.4 and P4.5 */
-#define OFS_P4MAP67 (0x0026) /* Port mapping register, P4.6 and P4.7 */
-#define OFS_P5MAP01 (0x0028) /* Port mapping register, P5.0 and P5.1 */
-#define OFS_P5MAP23 (0x002a) /* Port mapping register, P5.2 and P5.3 */
-#define OFS_P5MAP45 (0x002c) /* Port mapping register, P5.4 and P5.5 */
-#define OFS_P5MAP67 (0x002e) /* Port mapping register, P5.6 and P5.7 */
-#define OFS_P6MAP01 (0x0030) /* Port mapping register, P6.0 and P6.1 */
-#define OFS_P6MAP23 (0x0032) /* Port mapping register, P6.2 and P6.3 */
-#define OFS_P6MAP45 (0x0034) /* Port mapping register, P6.4 and P6.5 */
-#define OFS_P6MAP67 (0x0036) /* Port mapping register, P6.6 and P6.7 */
-#define OFS_P7MAP01 (0x0038) /* Port mapping register, P7.0 and P7.1 */
-#define OFS_P7MAP23 (0x003a) /* Port mapping register, P7.2 and P7.3 */
-#define OFS_P7MAP45 (0x003c) /* Port mapping register, P7.4 and P7.5 */
-#define OFS_P7MAP67 (0x003e) /* Port mapping register, P7.6 and P7.7 */
-
-
-//*****************************************************************************
-// PSS Registers
-//*****************************************************************************
-#define PSSKEY (HWREG32(0x40010800)) /* Key Register */
-#define PSSCTL0 (HWREG32(0x40010804)) /* Control 0 Register */
-#define PSSIE (HWREG32(0x40010834)) /* Interrupt Enable Register */
-#define PSSIFG (HWREG32(0x40010838)) /* Interrupt Flag Register */
-#define PSSCLRIFG (HWREG32(0x4001083C)) /* Clear Interrupt Flag Register */
-
-/* Register offsets from PSS_BASE address */
-#define OFS_PSSKEY (0x00000000) /* Key Register */
-#define OFS_PSSCTL0 (0x00000004) /* Control 0 Register */
-#define OFS_PSSIE (0x00000034) /* Interrupt Enable Register */
-#define OFS_PSSIFG (0x00000038) /* Interrupt Flag Register */
-#define OFS_PSSCLRIFG (0x0000003c) /* Clear Interrupt Flag Register */
-
-
-//*****************************************************************************
-// REF_A Registers
-//*****************************************************************************
-#define REFCTL0 (HWREG16(0x40003000)) /* REF Control Register 0 */
-
-/* Register offsets from REF_A_BASE address */
-#define OFS_REFCTL0 (0x0000) /* REF Control Register 0 */
-
-#define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */
-#define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */
-
-//*****************************************************************************
-// RSTCTL Registers
-//*****************************************************************************
-#define RSTCTL_RESET_REQ (HWREG32(0xE0042000)) /* Reset Request Register */
-#define RSTCTL_HARDRESET_CLR (HWREG32(0xE0042008)) /* Hard Reset Status Clear Register */
-#define RSTCTL_HARDRESET_SET (HWREG32(0xE004200C)) /* Hard Reset Status Set Register */
-#define RSTCTL_SOFTRESET_STAT (HWREG32(0xE0042010)) /* Soft Reset Status Register */
-#define RSTCTL_SOFTRESET_CLR (HWREG32(0xE0042014)) /* Soft Reset Status Clear Register */
-#define RSTCTL_SOFTRESET_SET (HWREG32(0xE0042018)) /* Soft Reset Status Set Register */
-#define RSTCTL_PSSRESET_STAT (HWREG32(0xE0042100)) /* PSS Reset Status Register */
-#define RSTCTL_PSSRESET_CLR (HWREG32(0xE0042104)) /* PSS Reset Status Clear Register */
-#define RSTCTL_PCMRESET_STAT (HWREG32(0xE0042108)) /* PCM Reset Status Register */
-#define RSTCTL_PCMRESET_CLR (HWREG32(0xE004210C)) /* PCM Reset Status Clear Register */
-#define RSTCTL_PINRESET_STAT (HWREG32(0xE0042110)) /* Pin Reset Status Register */
-#define RSTCTL_PINRESET_CLR (HWREG32(0xE0042114)) /* Pin Reset Status Clear Register */
-#define RSTCTL_REBOOTRESET_STAT (HWREG32(0xE0042118)) /* Reboot Reset Status Register */
-#define RSTCTL_REBOOTRESET_CLR (HWREG32(0xE004211C)) /* Reboot Reset Status Clear Register */
-
-/* Register offsets from RSTCTL_BASE address */
-#define OFS_RSTCTL_RESET_REQ (0x00000000) /* Reset Request Register */
-#define OFS_RSTCTL_HARDRESET_CLR (0x00000008) /* Hard Reset Status Clear Register */
-#define OFS_RSTCTL_HARDRESET_SET (0x0000000c) /* Hard Reset Status Set Register */
-#define OFS_RSTCTL_SOFTRESET_STAT (0x00000010) /* Soft Reset Status Register */
-#define OFS_RSTCTL_SOFTRESET_CLR (0x00000014) /* Soft Reset Status Clear Register */
-#define OFS_RSTCTL_SOFTRESET_SET (0x00000018) /* Soft Reset Status Set Register */
-#define OFS_RSTCTL_PSSRESET_STAT (0x00000100) /* PSS Reset Status Register */
-#define OFS_RSTCTL_PSSRESET_CLR (0x00000104) /* PSS Reset Status Clear Register */
-#define OFS_RSTCTL_PCMRESET_STAT (0x00000108) /* PCM Reset Status Register */
-#define OFS_RSTCTL_PCMRESET_CLR (0x0000010c) /* PCM Reset Status Clear Register */
-#define OFS_RSTCTL_PINRESET_STAT (0x00000110) /* Pin Reset Status Register */
-#define OFS_RSTCTL_PINRESET_CLR (0x00000114) /* Pin Reset Status Clear Register */
-#define OFS_RSTCTL_REBOOTRESET_STAT (0x00000118) /* Reboot Reset Status Register */
-#define OFS_RSTCTL_REBOOTRESET_CLR (0x0000011c) /* Reboot Reset Status Clear Register */
-
-
-//*****************************************************************************
-// RTC_C Registers
-//*****************************************************************************
-#define RTCCTL0 (HWREG16(0x40004400)) /* RTCCTL0 Register */
-#define RTCCTL13 (HWREG16(0x40004402)) /* RTCCTL13 Register */
-#define RTCOCAL (HWREG16(0x40004404)) /* RTCOCAL Register */
-#define RTCTCMP (HWREG16(0x40004406)) /* RTCTCMP Register */
-#define RTCPS0CTL (HWREG16(0x40004408)) /* Real-Time Clock Prescale Timer 0 Control Register */
-#define RTCPS1CTL (HWREG16(0x4000440A)) /* Real-Time Clock Prescale Timer 1 Control Register */
-#define RTCPS (HWREG16(0x4000440C)) /* Real-Time Clock Prescale Timer Counter Register */
-#define RTCIV (HWREG16(0x4000440E)) /* Real-Time Clock Interrupt Vector Register */
-#define RTCTIM0 (HWREG16(0x40004410)) /* RTCTIM0 Register ? Hexadecimal Format */
-#define RTCTIM0_BCD (HWREG16(0x40004410)) /* */
-#define RTCTIM1 (HWREG16(0x40004412)) /* Real-Time Clock Hour, Day of Week */
-#define RTCTIM1_BCD (HWREG16(0x40004412)) /* */
-#define RTCDATE (HWREG16(0x40004414)) /* RTCDATE - Hexadecimal Format */
-#define RTCDATE_BCD (HWREG16(0x40004414)) /* */
-#define RTCYEAR (HWREG16(0x40004416)) /* RTCYEAR Register ? Hexadecimal Format */
-#define RTCYEAR_BCD (HWREG16(0x40004416)) /* */
-#define RTCAMINHR (HWREG16(0x40004418)) /* RTCMINHR - Hexadecimal Format */
-#define RTCAMINHR_BCD (HWREG16(0x40004418)) /* */
-#define RTCADOWDAY (HWREG16(0x4000441A)) /* RTCADOWDAY - Hexadecimal Format */
-#define RTCADOWDAY_BCD (HWREG16(0x4000441A)) /* */
-#define RTCBIN2BCD (HWREG16(0x4000441C)) /* Binary-to-BCD Conversion Register */
-#define RTCBCD2BIN (HWREG16(0x4000441E)) /* BCD-to-Binary Conversion Register */
-
-/* Register offsets from RTC_C_BASE address */
-#define OFS_RTCCTL0 (0x0000) /* RTCCTL0 Register */
-#define OFS_RTCCTL13 (0x0002) /* RTCCTL13 Register */
-#define OFS_RTCOCAL (0x0004) /* RTCOCAL Register */
-#define OFS_RTCTCMP (0x0006) /* RTCTCMP Register */
-#define OFS_RTCPS0CTL (0x0008) /* Real-Time Clock Prescale Timer 0 Control Register */
-#define OFS_RTCPS1CTL (0x000a) /* Real-Time Clock Prescale Timer 1 Control Register */
-#define OFS_RTCPS (0x000c) /* Real-Time Clock Prescale Timer Counter Register */
-#define OFS_RTCIV (0x000e) /* Real-Time Clock Interrupt Vector Register */
-#define OFS_RTCTIM0 (0x0010) /* RTCTIM0 Register ? Hexadecimal Format */
-#define OFS_RTCTIM0_BCD (0x0010) /* */
-#define OFS_RTCTIM1 (0x0012) /* Real-Time Clock Hour, Day of Week */
-#define OFS_RTCTIM1_BCD (0x0012) /* */
-#define OFS_RTCDATE (0x0014) /* RTCDATE - Hexadecimal Format */
-#define OFS_RTCDATE_BCD (0x0014) /* */
-#define OFS_RTCYEAR (0x0016) /* RTCYEAR Register ? Hexadecimal Format */
-#define OFS_RTCYEAR_BCD (0x0016) /* */
-#define OFS_RTCAMINHR (0x0018) /* RTCMINHR - Hexadecimal Format */
-#define OFS_RTCAMINHR_BCD (0x0018) /* */
-#define OFS_RTCADOWDAY (0x001a) /* RTCADOWDAY - Hexadecimal Format */
-#define OFS_RTCADOWDAY_BCD (0x001a) /* */
-#define OFS_RTCBIN2BCD (0x001c) /* Binary-to-BCD Conversion Register */
-#define OFS_RTCBCD2BIN (0x001e) /* BCD-to-Binary Conversion Register */
-
-#define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */
-#define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */
-#define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */
-#define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */
-#define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */
-#define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */
-#define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */
-#define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */
-#define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */
-#define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */
-#define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
-#define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
-#define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
-#define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
-#define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
-#define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
-#define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
-#define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
-#define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */
-#define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */
-#define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */
-#define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */
-#define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */
-#define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */
-#define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */
-#define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */
-#define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */
-#define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */
-#define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */
-#define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */
-#define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
-#define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
-#define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
-#define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
-#define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
-#define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
-#define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
-#define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
-
-//*****************************************************************************
-// SCB Registers
-//*****************************************************************************
-#define SCB_CPUID (HWREG32(0xE000ED00)) /* CPUID Base Register */
-#define SCB_ICSR (HWREG32(0xE000ED04)) /* Interrupt Control State Register */
-#define SCB_VTOR (HWREG32(0xE000ED08)) /* Vector Table Offset Register */
-#define SCB_AIRCR (HWREG32(0xE000ED0C)) /* Application Interrupt/Reset Control Register */
-#define SCB_SCR (HWREG32(0xE000ED10)) /* System Control Register */
-#define SCB_CCR (HWREG32(0xE000ED14)) /* Configuration Control Register */
-#define SCB_SHPR1 (HWREG32(0xE000ED18)) /* System Handlers 4-7 Priority Register */
-#define SCB_SHPR2 (HWREG32(0xE000ED1C)) /* System Handlers 8-11 Priority Register */
-#define SCB_SHPR3 (HWREG32(0xE000ED20)) /* System Handlers 12-15 Priority Register */
-#define SCB_SHCSR (HWREG32(0xE000ED24)) /* System Handler Control and State Register */
-#define SCB_CFSR (HWREG32(0xE000ED28)) /* Configurable Fault Status Registers */
-#define SCB_HFSR (HWREG32(0xE000ED2C)) /* Hard Fault Status Register */
-#define SCB_DFSR (HWREG32(0xE000ED30)) /* Debug Fault Status Register */
-#define SCB_MMFAR (HWREG32(0xE000ED34)) /* Mem Manage Fault Address Register */
-#define SCB_BFAR (HWREG32(0xE000ED38)) /* Bus Fault Address Register */
-#define SCB_AFSR (HWREG32(0xE000ED3C)) /* Auxiliary Fault Status Register */
-#define SCB_PFR0 (HWREG32(0xE000ED40)) /* Processor Feature register0 */
-#define SCB_PFR1 (HWREG32(0xE000ED44)) /* Processor Feature register1 */
-#define SCB_DFR0 (HWREG32(0xE000ED48)) /* Debug Feature register0 */
-#define SCB_AFR0 (HWREG32(0xE000ED4C)) /* Auxiliary Feature register0 */
-#define SCB_MMFR0 (HWREG32(0xE000ED50)) /* Memory Model Feature register0 */
-#define SCB_MMFR1 (HWREG32(0xE000ED54)) /* Memory Model Feature register1 */
-#define SCB_MMFR2 (HWREG32(0xE000ED58)) /* Memory Model Feature register2 */
-#define SCB_MMFR3 (HWREG32(0xE000ED5C)) /* Memory Model Feature register3 */
-#define SCB_ISAR0 (HWREG32(0xE000ED60)) /* ISA Feature register0 */
-#define SCB_ISAR1 (HWREG32(0xE000ED64)) /* ISA Feature register1 */
-#define SCB_ISAR2 (HWREG32(0xE000ED68)) /* ISA Feature register2 */
-#define SCB_ISAR3 (HWREG32(0xE000ED6C)) /* ISA Feature register3 */
-#define SCB_ISAR4 (HWREG32(0xE000ED70)) /* ISA Feature register4 */
-#define SCB_CPACR (HWREG32(0xE000ED88)) /* Coprocessor Access Control Register */
-
-/* Register offsets from SCB_BASE address */
-#define OFS_SCB_CPUID (0x00000D00) /* CPUID Base Register */
-#define OFS_SCB_ICSR (0x00000D04) /* Interrupt Control State Register */
-#define OFS_SCB_VTOR (0x00000D08) /* Vector Table Offset Register */
-#define OFS_SCB_AIRCR (0x00000D0C) /* Application Interrupt/Reset Control Register */
-#define OFS_SCB_SCR (0x00000D10) /* System Control Register */
-#define OFS_SCB_CCR (0x00000D14) /* Configuration Control Register */
-#define OFS_SCB_SHPR1 (0x00000D18) /* System Handlers 4-7 Priority Register */
-#define OFS_SCB_SHPR2 (0x00000D1C) /* System Handlers 8-11 Priority Register */
-#define OFS_SCB_SHPR3 (0x00000D20) /* System Handlers 12-15 Priority Register */
-#define OFS_SCB_SHCSR (0x00000D24) /* System Handler Control and State Register */
-#define OFS_SCB_CFSR (0x00000D28) /* Configurable Fault Status Registers */
-#define OFS_SCB_HFSR (0x00000D2C) /* Hard Fault Status Register */
-#define OFS_SCB_DFSR (0x00000D30) /* Debug Fault Status Register */
-#define OFS_SCB_MMFAR (0x00000D34) /* Mem Manage Fault Address Register */
-#define OFS_SCB_BFAR (0x00000D38) /* Bus Fault Address Register */
-#define OFS_SCB_AFSR (0x00000D3C) /* Auxiliary Fault Status Register */
-#define OFS_SCB_PFR0 (0x00000D40) /* Processor Feature register0 */
-#define OFS_SCB_PFR1 (0x00000D44) /* Processor Feature register1 */
-#define OFS_SCB_DFR0 (0x00000D48) /* Debug Feature register0 */
-#define OFS_SCB_AFR0 (0x00000D4C) /* Auxiliary Feature register0 */
-#define OFS_SCB_MMFR0 (0x00000D50) /* Memory Model Feature register0 */
-#define OFS_SCB_MMFR1 (0x00000D54) /* Memory Model Feature register1 */
-#define OFS_SCB_MMFR2 (0x00000D58) /* Memory Model Feature register2 */
-#define OFS_SCB_MMFR3 (0x00000D5C) /* Memory Model Feature register3 */
-#define OFS_SCB_ISAR0 (0x00000D60) /* ISA Feature register0 */
-#define OFS_SCB_ISAR1 (0x00000D64) /* ISA Feature register1 */
-#define OFS_SCB_ISAR2 (0x00000D68) /* ISA Feature register2 */
-#define OFS_SCB_ISAR3 (0x00000D6C) /* ISA Feature register3 */
-#define OFS_SCB_ISAR4 (0x00000D70) /* ISA Feature register4 */
-#define OFS_SCB_CPACR (0x00000D88) /* Coprocessor Access Control Register */
-
-
-//*****************************************************************************
-// SCnSCB Registers
-//*****************************************************************************
-#define SCnSCB_ICTR (HWREG32(0xE000E004)) /* Interrupt Control Type Register */
-#define SCnSCB_ACTLR (HWREG32(0xE000E008)) /* Auxiliary Control Register */
-
-/* Register offsets from SCnSCB_BASE address */
-#define OFS_SCnSCB_ICTR (0x00000004) /* Interrupt Control Type Register */
-#define OFS_SCnSCB_ACTLR (0x00000008) /* Auxiliary Control Register */
-
-
-//*****************************************************************************
-// SYSCTL Registers
-//*****************************************************************************
-#define SYSCTL_REBOOT_CTL (HWREG32(0xE0043000)) /* Reboot Control Register */
-#define SYSCTL_NMI_CTLSTAT (HWREG32(0xE0043004)) /* NMI Control and Status Register */
-#define SYSCTL_WDTRESET_CTL (HWREG32(0xE0043008)) /* Watchdog Reset Control Register */
-#define SYSCTL_PERIHALT_CTL (HWREG32(0xE004300C)) /* Peripheral Halt Control Register */
-#define SYSCTL_SRAM_SIZE (HWREG32(0xE0043010)) /* SRAM Size Register */
-#define SYSCTL_SRAM_BANKEN (HWREG32(0xE0043014)) /* SRAM Bank Enable Register */
-#define SYSCTL_SRAM_BANKRET (HWREG32(0xE0043018)) /* SRAM Bank Retention Control Register */
-#define SYSCTL_FLASH_SIZE (HWREG32(0xE0043020)) /* Flash Size Register */
-#define SYSCTL_DIO_GLTFLT_CTL (HWREG32(0xE0043030)) /* Digital I/O Glitch Filter Control Register */
-#define SYSCTL_SECDATA_UNLOCK (HWREG32(0xE0043040)) /* IP Protected Secure Zone Data Access Unlock Register */
-#define SYSCTL_MASTER_UNLOCK (HWREG32(0xE0044000)) /* Master Unlock Register */
-#define SYSCTL_BOOTOVER_REQ0 (HWREG32(0xE0044004)) /* Boot Override Request Register */
-#define SYSCTL_BOOTOVER_REQ1 (HWREG32(0xE0044008)) /* Boot Override Request Register */
-#define SYSCTL_BOOTOVER_ACK (HWREG32(0xE004400C)) /* Boot Override Acknowledge Register */
-#define SYSCTL_RESET_REQ (HWREG32(0xE0044010)) /* Reset Request Register */
-#define SYSCTL_RESET_STATOVER (HWREG32(0xE0044014)) /* Reset Status and Override Register */
-#define SYSCTL_SYSTEM_STAT (HWREG32(0xE0044020)) /* System Status Register */
-
-/* Register offsets from SYSCTL_BASE address */
-#define OFS_SYSCTL_REBOOT_CTL (0x00000000) /* Reboot Control Register */
-#define OFS_SYSCTL_NMI_CTLSTAT (0x00000004) /* NMI Control and Status Register */
-#define OFS_SYSCTL_WDTRESET_CTL (0x00000008) /* Watchdog Reset Control Register */
-#define OFS_SYSCTL_PERIHALT_CTL (0x0000000c) /* Peripheral Halt Control Register */
-#define OFS_SYSCTL_SRAM_SIZE (0x00000010) /* SRAM Size Register */
-#define OFS_SYSCTL_SRAM_BANKEN (0x00000014) /* SRAM Bank Enable Register */
-#define OFS_SYSCTL_SRAM_BANKRET (0x00000018) /* SRAM Bank Retention Control Register */
-#define OFS_SYSCTL_FLASH_SIZE (0x00000020) /* Flash Size Register */
-#define OFS_SYSCTL_DIO_GLTFLT_CTL (0x00000030) /* Digital I/O Glitch Filter Control Register */
-#define OFS_SYSCTL_SECDATA_UNLOCK (0x00000040) /* IP Protected Secure Zone Data Access Unlock Register */
-#define OFS_SYSCTL_MASTER_UNLOCK (0x00001000) /* Master Unlock Register */
-#define OFS_SYSCTL_BOOTOVER_REQ0 (0x00001004) /* Boot Override Request Register */
-#define OFS_SYSCTL_BOOTOVER_REQ1 (0x00001008) /* Boot Override Request Register */
-#define OFS_SYSCTL_BOOTOVER_ACK (0x0000100c) /* Boot Override Acknowledge Register */
-#define OFS_SYSCTL_RESET_REQ (0x00001010) /* Reset Request Register */
-#define OFS_SYSCTL_RESET_STATOVER (0x00001014) /* Reset Status and Override Register */
-#define OFS_SYSCTL_SYSTEM_STAT (0x00001020) /* System Status Register */
-
-
-//*****************************************************************************
-// SYSTICK Registers
-//*****************************************************************************
-#define SYSTICK_STCSR (HWREG32(0xE000E010)) /* SysTick Control and Status Register */
-#define SYSTICK_STRVR (HWREG32(0xE000E014)) /* SysTick Reload Value Register */
-#define SYSTICK_STCVR (HWREG32(0xE000E018)) /* SysTick Current Value Register */
-#define SYSTICK_STCR (HWREG32(0xE000E01C)) /* SysTick Calibration Value Register */
-
-/* Register offsets from SYSTICK_BASE address */
-#define OFS_SYSTICK_STCSR (0x00000010) /* SysTick Control and Status Register */
-#define OFS_SYSTICK_STRVR (0x00000014) /* SysTick Reload Value Register */
-#define OFS_SYSTICK_STCVR (0x00000018) /* SysTick Current Value Register */
-#define OFS_SYSTICK_STCR (0x0000001C) /* SysTick Calibration Value Register */
-
-
-//*****************************************************************************
-// TIMER32 Registers
-//*****************************************************************************
-#define TIMER32_LOAD1 (HWREG32(0x4000C000)) /* Timer 1 Load Register */
-#define TIMER32_VALUE1 (HWREG32(0x4000C004)) /* Timer 1 Current Value Register */
-#define TIMER32_CONTROL1 (HWREG32(0x4000C008)) /* Timer 1 Timer Control Register */
-#define TIMER32_INTCLR1 (HWREG32(0x4000C00C)) /* Timer 1 Interrupt Clear Register */
-#define TIMER32_RIS1 (HWREG32(0x4000C010)) /* Timer 1 Raw Interrupt Status Register */
-#define TIMER32_MIS1 (HWREG32(0x4000C014)) /* Timer 1 Interrupt Status Register */
-#define TIMER32_BGLOAD1 (HWREG32(0x4000C018)) /* Timer 1 Background Load Register */
-#define TIMER32_LOAD2 (HWREG32(0x4000C020)) /* Timer 2 Load Register */
-#define TIMER32_VALUE2 (HWREG32(0x4000C024)) /* Timer 2 Current Value Register */
-#define TIMER32_CONTROL2 (HWREG32(0x4000C028)) /* Timer 2 Timer Control Register */
-#define TIMER32_INTCLR2 (HWREG32(0x4000C02C)) /* Timer 2 Interrupt Clear Register */
-#define TIMER32_RIS2 (HWREG32(0x4000C030)) /* Timer 2 Raw Interrupt Status Register */
-#define TIMER32_MIS2 (HWREG32(0x4000C034)) /* Timer 2 Interrupt Status Register */
-#define TIMER32_BGLOAD2 (HWREG32(0x4000C038)) /* Timer 2 Background Load Register */
-
-/* Register offsets from TIMER32_BASE address */
-#define OFS_TIMER32_LOAD1 (0x00000000) /* Timer 1 Load Register */
-#define OFS_TIMER32_VALUE1 (0x00000004) /* Timer 1 Current Value Register */
-#define OFS_TIMER32_CONTROL1 (0x00000008) /* Timer 1 Timer Control Register */
-#define OFS_TIMER32_INTCLR1 (0x0000000C) /* Timer 1 Interrupt Clear Register */
-#define OFS_TIMER32_RIS1 (0x00000010) /* Timer 1 Raw Interrupt Status Register */
-#define OFS_TIMER32_MIS1 (0x00000014) /* Timer 1 Interrupt Status Register */
-#define OFS_TIMER32_BGLOAD1 (0x00000018) /* Timer 1 Background Load Register */
-#define OFS_TIMER32_LOAD2 (0x00000020) /* Timer 2 Load Register */
-#define OFS_TIMER32_VALUE2 (0x00000024) /* Timer 2 Current Value Register */
-#define OFS_TIMER32_CONTROL2 (0x00000028) /* Timer 2 Timer Control Register */
-#define OFS_TIMER32_INTCLR2 (0x0000002C) /* Timer 2 Interrupt Clear Register */
-#define OFS_TIMER32_RIS2 (0x00000030) /* Timer 2 Raw Interrupt Status Register */
-#define OFS_TIMER32_MIS2 (0x00000034) /* Timer 2 Interrupt Status Register */
-#define OFS_TIMER32_BGLOAD2 (0x00000038) /* Timer 2 Background Load Register */
-
-
-//*****************************************************************************
-// TIMER_A0 Registers
-//*****************************************************************************
-#define TA0CTL (HWREG16(0x40000000)) /* TimerAx Control Register */
-#define TA0CCTL0 (HWREG16(0x40000002)) /* Timer_A Capture/Compare Control Register */
-#define TA0CCTL1 (HWREG16(0x40000004)) /* Timer_A Capture/Compare Control Register */
-#define TA0CCTL2 (HWREG16(0x40000006)) /* Timer_A Capture/Compare Control Register */
-#define TA0CCTL3 (HWREG16(0x40000008)) /* Timer_A Capture/Compare Control Register */
-#define TA0CCTL4 (HWREG16(0x4000000A)) /* Timer_A Capture/Compare Control Register */
-#define TA0CCTL5 (HWREG16(0x4000000C)) /* Timer_A Capture/Compare Control Register */
-#define TA0CCTL6 (HWREG16(0x4000000E)) /* Timer_A Capture/Compare Control Register */
-#define TA0R (HWREG16(0x40000010)) /* TimerA register */
-#define TA0CCR0 (HWREG16(0x40000012)) /* Timer_A Capture/Compare Register */
-#define TA0CCR1 (HWREG16(0x40000014)) /* Timer_A Capture/Compare Register */
-#define TA0CCR2 (HWREG16(0x40000016)) /* Timer_A Capture/Compare Register */
-#define TA0CCR3 (HWREG16(0x40000018)) /* Timer_A Capture/Compare Register */
-#define TA0CCR4 (HWREG16(0x4000001A)) /* Timer_A Capture/Compare Register */
-#define TA0CCR5 (HWREG16(0x4000001C)) /* Timer_A Capture/Compare Register */
-#define TA0CCR6 (HWREG16(0x4000001E)) /* Timer_A Capture/Compare Register */
-#define TA0EX0 (HWREG16(0x40000020)) /* TimerAx Expansion 0 Register */
-#define TA0IV (HWREG16(0x4000002E)) /* TimerAx Interrupt Vector Register */
-
-/* Register offsets from TIMER_A0_BASE address */
-#define OFS_TA0CTL (0x0000) /* TimerAx Control Register */
-#define OFS_TA0CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA0CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA0CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA0CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA0CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA0CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA0CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA0R (0x0010) /* TimerA register */
-#define OFS_TA0CCR0 (0x0012) /* Timer_A Capture/Compare Register */
-#define OFS_TA0CCR1 (0x0014) /* Timer_A Capture/Compare Register */
-#define OFS_TA0CCR2 (0x0016) /* Timer_A Capture/Compare Register */
-#define OFS_TA0CCR3 (0x0018) /* Timer_A Capture/Compare Register */
-#define OFS_TA0CCR4 (0x001A) /* Timer_A Capture/Compare Register */
-#define OFS_TA0CCR5 (0x001C) /* Timer_A Capture/Compare Register */
-#define OFS_TA0CCR6 (0x001E) /* Timer_A Capture/Compare Register */
-#define OFS_TA0EX0 (0x0020) /* TimerAx Expansion 0 Register */
-#define OFS_TA0IV (0x002e) /* TimerAx Interrupt Vector Register */
-
-
-//*****************************************************************************
-// TIMER_A1 Registers
-//*****************************************************************************
-#define TA1CTL (HWREG16(0x40000400)) /* TimerAx Control Register */
-#define TA1CCTL0 (HWREG16(0x40000402)) /* Timer_A Capture/Compare Control Register */
-#define TA1CCTL1 (HWREG16(0x40000404)) /* Timer_A Capture/Compare Control Register */
-#define TA1CCTL2 (HWREG16(0x40000406)) /* Timer_A Capture/Compare Control Register */
-#define TA1CCTL3 (HWREG16(0x40000408)) /* Timer_A Capture/Compare Control Register */
-#define TA1CCTL4 (HWREG16(0x4000040A)) /* Timer_A Capture/Compare Control Register */
-#define TA1CCTL5 (HWREG16(0x4000040C)) /* Timer_A Capture/Compare Control Register */
-#define TA1CCTL6 (HWREG16(0x4000040E)) /* Timer_A Capture/Compare Control Register */
-#define TA1R (HWREG16(0x40000410)) /* TimerA register */
-#define TA1CCR0 (HWREG16(0x40000412)) /* Timer_A Capture/Compare Register */
-#define TA1CCR1 (HWREG16(0x40000414)) /* Timer_A Capture/Compare Register */
-#define TA1CCR2 (HWREG16(0x40000416)) /* Timer_A Capture/Compare Register */
-#define TA1CCR3 (HWREG16(0x40000418)) /* Timer_A Capture/Compare Register */
-#define TA1CCR4 (HWREG16(0x4000041A)) /* Timer_A Capture/Compare Register */
-#define TA1CCR5 (HWREG16(0x4000041C)) /* Timer_A Capture/Compare Register */
-#define TA1CCR6 (HWREG16(0x4000041E)) /* Timer_A Capture/Compare Register */
-#define TA1EX0 (HWREG16(0x40000420)) /* TimerAx Expansion 0 Register */
-#define TA1IV (HWREG16(0x4000042E)) /* TimerAx Interrupt Vector Register */
-
-/* Register offsets from TIMER_A1_BASE address */
-#define OFS_TA1CTL (0x0000) /* TimerAx Control Register */
-#define OFS_TA1CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA1CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA1CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA1CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA1CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA1CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA1CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA1R (0x0010) /* TimerA register */
-#define OFS_TA1CCR0 (0x0012) /* Timer_A Capture/Compare Register */
-#define OFS_TA1CCR1 (0x0014) /* Timer_A Capture/Compare Register */
-#define OFS_TA1CCR2 (0x0016) /* Timer_A Capture/Compare Register */
-#define OFS_TA1CCR3 (0x0018) /* Timer_A Capture/Compare Register */
-#define OFS_TA1CCR4 (0x001A) /* Timer_A Capture/Compare Register */
-#define OFS_TA1CCR5 (0x001C) /* Timer_A Capture/Compare Register */
-#define OFS_TA1CCR6 (0x001E) /* Timer_A Capture/Compare Register */
-#define OFS_TA1EX0 (0x0020) /* TimerAx Expansion 0 Register */
-#define OFS_TA1IV (0x002e) /* TimerAx Interrupt Vector Register */
-
-
-//*****************************************************************************
-// TIMER_A2 Registers
-//*****************************************************************************
-#define TA2CTL (HWREG16(0x40000800)) /* TimerAx Control Register */
-#define TA2CCTL0 (HWREG16(0x40000802)) /* Timer_A Capture/Compare Control Register */
-#define TA2CCTL1 (HWREG16(0x40000804)) /* Timer_A Capture/Compare Control Register */
-#define TA2CCTL2 (HWREG16(0x40000806)) /* Timer_A Capture/Compare Control Register */
-#define TA2CCTL3 (HWREG16(0x40000808)) /* Timer_A Capture/Compare Control Register */
-#define TA2CCTL4 (HWREG16(0x4000080A)) /* Timer_A Capture/Compare Control Register */
-#define TA2CCTL5 (HWREG16(0x4000080C)) /* Timer_A Capture/Compare Control Register */
-#define TA2CCTL6 (HWREG16(0x4000080E)) /* Timer_A Capture/Compare Control Register */
-#define TA2R (HWREG16(0x40000810)) /* TimerA register */
-#define TA2CCR0 (HWREG16(0x40000812)) /* Timer_A Capture/Compare Register */
-#define TA2CCR1 (HWREG16(0x40000814)) /* Timer_A Capture/Compare Register */
-#define TA2CCR2 (HWREG16(0x40000816)) /* Timer_A Capture/Compare Register */
-#define TA2CCR3 (HWREG16(0x40000818)) /* Timer_A Capture/Compare Register */
-#define TA2CCR4 (HWREG16(0x4000081A)) /* Timer_A Capture/Compare Register */
-#define TA2CCR5 (HWREG16(0x4000081C)) /* Timer_A Capture/Compare Register */
-#define TA2CCR6 (HWREG16(0x4000081E)) /* Timer_A Capture/Compare Register */
-#define TA2EX0 (HWREG16(0x40000820)) /* TimerAx Expansion 0 Register */
-#define TA2IV (HWREG16(0x4000082E)) /* TimerAx Interrupt Vector Register */
-
-/* Register offsets from TIMER_A2_BASE address */
-#define OFS_TA2CTL (0x0000) /* TimerAx Control Register */
-#define OFS_TA2CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA2CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA2CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA2CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA2CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA2CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA2CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA2R (0x0010) /* TimerA register */
-#define OFS_TA2CCR0 (0x0012) /* Timer_A Capture/Compare Register */
-#define OFS_TA2CCR1 (0x0014) /* Timer_A Capture/Compare Register */
-#define OFS_TA2CCR2 (0x0016) /* Timer_A Capture/Compare Register */
-#define OFS_TA2CCR3 (0x0018) /* Timer_A Capture/Compare Register */
-#define OFS_TA2CCR4 (0x001A) /* Timer_A Capture/Compare Register */
-#define OFS_TA2CCR5 (0x001C) /* Timer_A Capture/Compare Register */
-#define OFS_TA2CCR6 (0x001E) /* Timer_A Capture/Compare Register */
-#define OFS_TA2EX0 (0x0020) /* TimerAx Expansion 0 Register */
-#define OFS_TA2IV (0x002e) /* TimerAx Interrupt Vector Register */
-
-
-//*****************************************************************************
-// TIMER_A3 Registers
-//*****************************************************************************
-#define TA3CTL (HWREG16(0x40000C00)) /* TimerAx Control Register */
-#define TA3CCTL0 (HWREG16(0x40000C02)) /* Timer_A Capture/Compare Control Register */
-#define TA3CCTL1 (HWREG16(0x40000C04)) /* Timer_A Capture/Compare Control Register */
-#define TA3CCTL2 (HWREG16(0x40000C06)) /* Timer_A Capture/Compare Control Register */
-#define TA3CCTL3 (HWREG16(0x40000C08)) /* Timer_A Capture/Compare Control Register */
-#define TA3CCTL4 (HWREG16(0x40000C0A)) /* Timer_A Capture/Compare Control Register */
-#define TA3CCTL5 (HWREG16(0x40000C0C)) /* Timer_A Capture/Compare Control Register */
-#define TA3CCTL6 (HWREG16(0x40000C0E)) /* Timer_A Capture/Compare Control Register */
-#define TA3R (HWREG16(0x40000C10)) /* TimerA register */
-#define TA3CCR0 (HWREG16(0x40000C12)) /* Timer_A Capture/Compare Register */
-#define TA3CCR1 (HWREG16(0x40000C14)) /* Timer_A Capture/Compare Register */
-#define TA3CCR2 (HWREG16(0x40000C16)) /* Timer_A Capture/Compare Register */
-#define TA3CCR3 (HWREG16(0x40000C18)) /* Timer_A Capture/Compare Register */
-#define TA3CCR4 (HWREG16(0x40000C1A)) /* Timer_A Capture/Compare Register */
-#define TA3CCR5 (HWREG16(0x40000C1C)) /* Timer_A Capture/Compare Register */
-#define TA3CCR6 (HWREG16(0x40000C1E)) /* Timer_A Capture/Compare Register */
-#define TA3EX0 (HWREG16(0x40000C20)) /* TimerAx Expansion 0 Register */
-#define TA3IV (HWREG16(0x40000C2E)) /* TimerAx Interrupt Vector Register */
-
-/* Register offsets from TIMER_A3_BASE address */
-#define OFS_TA3CTL (0x0000) /* TimerAx Control Register */
-#define OFS_TA3CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA3CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA3CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA3CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA3CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA3CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA3CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
-#define OFS_TA3R (0x0010) /* TimerA register */
-#define OFS_TA3CCR0 (0x0012) /* Timer_A Capture/Compare Register */
-#define OFS_TA3CCR1 (0x0014) /* Timer_A Capture/Compare Register */
-#define OFS_TA3CCR2 (0x0016) /* Timer_A Capture/Compare Register */
-#define OFS_TA3CCR3 (0x0018) /* Timer_A Capture/Compare Register */
-#define OFS_TA3CCR4 (0x001A) /* Timer_A Capture/Compare Register */
-#define OFS_TA3CCR5 (0x001C) /* Timer_A Capture/Compare Register */
-#define OFS_TA3CCR6 (0x001E) /* Timer_A Capture/Compare Register */
-#define OFS_TA3EX0 (0x0020) /* TimerAx Expansion 0 Register */
-#define OFS_TA3IV (0x002e) /* TimerAx Interrupt Vector Register */
-
-
-//*****************************************************************************
-// TLV Registers
-//*****************************************************************************
-#define TLV_TLV_CHECKSUM (HWREG32(0x00201000)) /* TLV Checksum */
-#define TLV_DEVICE_INFO_TAG (HWREG32(0x00201004)) /* Device Info Tag */
-#define TLV_DEVICE_INFO_LEN (HWREG32(0x00201008)) /* Device Info Length */
-#define TLV_DEVICE_ID (HWREG32(0x0020100C)) /* Device ID */
-#define TLV_HWREV (HWREG32(0x00201010)) /* HW Revision */
-#define TLV_BCREV (HWREG32(0x00201014)) /* Boot Code Revision */
-#define TLV_ROM_DRVLIB_REV (HWREG32(0x00201018)) /* ROM Driver Library Revision */
-#define TLV_DIE_REC_TAG (HWREG32(0x0020101C)) /* Die Record Tag */
-#define TLV_DIE_REC_LEN (HWREG32(0x00201020)) /* Die Record Length */
-#define TLV_DIE_XPOS (HWREG32(0x00201024)) /* Die X-Position */
-#define TLV_DIE_YPOS (HWREG32(0x00201028)) /* Die Y-Position */
-#define TLV_WAFER_ID (HWREG32(0x0020102C)) /* Wafer ID */
-#define TLV_LOT_ID (HWREG32(0x00201030)) /* Lot ID */
-#define TLV_RESERVED0 (HWREG32(0x00201034)) /* Reserved */
-#define TLV_RESERVED1 (HWREG32(0x00201038)) /* Reserved */
-#define TLV_RESERVED2 (HWREG32(0x0020103C)) /* Reserved */
-#define TLV_TEST_RESULTS (HWREG32(0x00201040)) /* Test Results */
-#define TLV_CS_CAL_TAG (HWREG32(0x00201044)) /* Clock System Calibration Tag */
-#define TLV_CS_CAL_LEN (HWREG32(0x00201048)) /* Clock System Calibration Length */
-#define TLV_DCOIR_FCAL_RSEL04 (HWREG32(0x0020104C)) /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
-#define TLV_DCOIR_FCAL_RSEL5 (HWREG32(0x00201050)) /* DCO IR mode: Frequency calibration for DCORSEL 5 */
-#define TLV_DCOIR_MAXPOSTUNE_RSEL04 (HWREG32(0x00201054)) /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
-#define TLV_DCOIR_MAXNEGTUNE_RSEL04 (HWREG32(0x00201058)) /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
-#define TLV_DCOIR_MAXPOSTUNE_RSEL5 (HWREG32(0x0020105C)) /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
-#define TLV_DCOIR_MAXNEGTUNE_RSEL5 (HWREG32(0x00201060)) /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
-#define TLV_DCOIR_CONSTK_RSEL04 (HWREG32(0x00201064)) /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
-#define TLV_DCOIR_CONSTK_RSEL5 (HWREG32(0x00201068)) /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
-#define TLV_DCOER_FCAL_RSEL04 (HWREG32(0x0020106C)) /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
-#define TLV_DCOER_FCAL_RSEL5 (HWREG32(0x00201070)) /* DCO ER mode: Frequency calibration for DCORSEL 5 */
-#define TLV_DCOER_MAXPOSTUNE_RSEL04 (HWREG32(0x00201074)) /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
-#define TLV_DCOER_MAXNEGTUNE_RSEL04 (HWREG32(0x00201078)) /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
-#define TLV_DCOER_MAXPOSTUNE_RSEL5 (HWREG32(0x0020107C)) /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
-#define TLV_DCOER_MAXNEGTUNE_RSEL5 (HWREG32(0x00201080)) /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
-#define TLV_DCOER_CONSTK_RSEL04 (HWREG32(0x00201084)) /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
-#define TLV_DCOER_CONSTK_RSEL5 (HWREG32(0x00201088)) /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
-#define TLV_ADC14_CAL_TAG (HWREG32(0x0020108C)) /* ADC14 Calibration Tag */
-#define TLV_ADC14_CAL_LEN (HWREG32(0x00201090)) /* ADC14 Calibration Length */
-#define TLV_ADC14_GF_EXTREF30C (HWREG32(0x00201094)) /* ADC14 Gain Factor for External Reference 30°C */
-#define TLV_ADC14_GF_EXTREF85C (HWREG32(0x00201098)) /* ADC14 Gain Factor for External Reference 85°C */
-#define TLV_ADC14_GF_BUF_EXTREF30C (HWREG32(0x0020109C)) /* ADC14 Gain Factor for Buffered External Reference 30°C */
-#define TLV_ADC14_GF_BUF_EXTREF85C (HWREG32(0x002010A0)) /* ADC14 Gain Factor for Buffered External Reference 85°C */
-#define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0 (HWREG32(0x002010A4)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
-#define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0 (HWREG32(0x002010A8)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
-#define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1 (HWREG32(0x002010AC)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
-#define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1 (HWREG32(0x002010B0)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
-#define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0 (HWREG32(0x002010B4)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
-#define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0 (HWREG32(0x002010B8)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
-#define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1 (HWREG32(0x002010BC)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
-#define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1 (HWREG32(0x002010C0)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
-#define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0 (HWREG32(0x002010C4)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
-#define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0 (HWREG32(0x002010C8)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
-#define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1 (HWREG32(0x002010CC)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
-#define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1 (HWREG32(0x002010D0)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
-#define TLV_ADC14_OFFSET_VRSEL_1 (HWREG32(0x002010D4)) /* ADC14 Offset (ADC14VRSEL = 1h) */
-#define TLV_ADC14_OFFSET_VRSEL_E (HWREG32(0x002010D8)) /* ADC14 Offset (ADC14VRSEL = Eh) */
-#define TLV_ADC14_REF1P2V_TS30C (HWREG32(0x002010DC)) /* ADC14 1.2V Reference Temp. Sensor 30°C */
-#define TLV_ADC14_REF1P2V_TS85C (HWREG32(0x002010E0)) /* ADC14 1.2V Reference Temp. Sensor 85°C */
-#define TLV_ADC14_REF1P45V_TS30C (HWREG32(0x002010E4)) /* ADC14 1.45V Reference Temp. Sensor 30°C */
-#define TLV_ADC14_REF1P45V_TS85C (HWREG32(0x002010E8)) /* ADC14 1.45V Reference Temp. Sensor 85°C */
-#define TLV_ADC14_REF2P5V_TS30C (HWREG32(0x002010EC)) /* ADC14 2.5V Reference Temp. Sensor 30°C */
-#define TLV_ADC14_REF2P5V_TS85C (HWREG32(0x002010F0)) /* ADC14 2.5V Reference Temp. Sensor 85°C */
-#define TLV_REF_CAL_TAG (HWREG32(0x002010F4)) /* REF Calibration Tag */
-#define TLV_REF_CAL_LEN (HWREG32(0x002010F8)) /* REF Calibration Length */
-#define TLV_REF_1P2V (HWREG32(0x002010FC)) /* REF 1.2V Reference */
-#define TLV_REF_1P45V (HWREG32(0x00201100)) /* REF 1.45V Reference */
-#define TLV_REF_2P5V (HWREG32(0x00201104)) /* REF 2.5V Reference */
-#define TLV_RANDOM_NUM_TAG (HWREG32(0x00201108)) /* 128-bit Random Number Tag */
-#define TLV_RANDOM_NUM_LEN (HWREG32(0x0020110C)) /* 128-bit Random Number Length */
-#define TLV_RANDOM_NUM_1 (HWREG32(0x00201110)) /* 32-bit Random Number 1 */
-#define TLV_RANDOM_NUM_2 (HWREG32(0x00201114)) /* 32-bit Random Number 2 */
-#define TLV_RANDOM_NUM_3 (HWREG32(0x00201118)) /* 32-bit Random Number 3 */
-#define TLV_RANDOM_NUM_4 (HWREG32(0x0020111C)) /* 32-bit Random Number 4 */
-#define TLV_BSL_CFG_TAG (HWREG32(0x00201120)) /* BSL Configuration Tag */
-#define TLV_BSL_CFG_LEN (HWREG32(0x00201124)) /* BSL Configuration Length */
-#define TLV_BSL_PERIPHIF_SEL (HWREG32(0x00201128)) /* BSL Peripheral Interface Selection */
-#define TLV_BSL_PORTIF_CFG_UART (HWREG32(0x0020112C)) /* BSL Port Interface Configuration for UART */
-#define TLV_BSL_PORTIF_CFG_SPI (HWREG32(0x00201130)) /* BSL Port Interface Configuration for SPI */
-#define TLV_BSL_PORTIF_CFG_I2C (HWREG32(0x00201134)) /* BSL Port Interface Configuration for I2C */
-#define TLV_TLV_END (HWREG32(0x00201138)) /* TLV End Word */
-
-/* Register offsets from TLV_BASE address */
-#define OFS_TLV_TLV_CHECKSUM (0x00000000) /* TLV Checksum */
-#define OFS_TLV_DEVICE_INFO_TAG (0x00000004) /* Device Info Tag */
-#define OFS_TLV_DEVICE_INFO_LEN (0x00000008) /* Device Info Length */
-#define OFS_TLV_DEVICE_ID (0x0000000C) /* Device ID */
-#define OFS_TLV_HWREV (0x00000010) /* HW Revision */
-#define OFS_TLV_BCREV (0x00000014) /* Boot Code Revision */
-#define OFS_TLV_ROM_DRVLIB_REV (0x00000018) /* ROM Driver Library Revision */
-#define OFS_TLV_DIE_REC_TAG (0x0000001C) /* Die Record Tag */
-#define OFS_TLV_DIE_REC_LEN (0x00000020) /* Die Record Length */
-#define OFS_TLV_DIE_XPOS (0x00000024) /* Die X-Position */
-#define OFS_TLV_DIE_YPOS (0x00000028) /* Die Y-Position */
-#define OFS_TLV_WAFER_ID (0x0000002C) /* Wafer ID */
-#define OFS_TLV_LOT_ID (0x00000030) /* Lot ID */
-#define OFS_TLV_RESERVED0 (0x00000034) /* Reserved */
-#define OFS_TLV_RESERVED1 (0x00000038) /* Reserved */
-#define OFS_TLV_RESERVED2 (0x0000003c) /* Reserved */
-#define OFS_TLV_TEST_RESULTS (0x00000040) /* Test Results */
-#define OFS_TLV_CS_CAL_TAG (0x00000044) /* Clock System Calibration Tag */
-#define OFS_TLV_CS_CAL_LEN (0x00000048) /* Clock System Calibration Length */
-#define OFS_TLV_DCOIR_FCAL_RSEL04 (0x0000004c) /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOIR_FCAL_RSEL5 (0x00000050) /* DCO IR mode: Frequency calibration for DCORSEL 5 */
-#define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL04 (0x00000054) /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL04 (0x00000058) /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL5 (0x0000005c) /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
-#define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL5 (0x00000060) /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
-#define OFS_TLV_DCOIR_CONSTK_RSEL04 (0x00000064) /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOIR_CONSTK_RSEL5 (0x00000068) /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
-#define OFS_TLV_DCOER_FCAL_RSEL04 (0x0000006c) /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOER_FCAL_RSEL5 (0x00000070) /* DCO ER mode: Frequency calibration for DCORSEL 5 */
-#define OFS_TLV_DCOER_MAXPOSTUNE_RSEL04 (0x00000074) /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOER_MAXNEGTUNE_RSEL04 (0x00000078) /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOER_MAXPOSTUNE_RSEL5 (0x0000007c) /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
-#define OFS_TLV_DCOER_MAXNEGTUNE_RSEL5 (0x00000080) /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
-#define OFS_TLV_DCOER_CONSTK_RSEL04 (0x00000084) /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
-#define OFS_TLV_DCOER_CONSTK_RSEL5 (0x00000088) /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
-#define OFS_TLV_ADC14_CAL_TAG (0x0000008C) /* ADC14 Calibration Tag */
-#define OFS_TLV_ADC14_CAL_LEN (0x00000090) /* ADC14 Calibration Length */
-#define OFS_TLV_ADC14_GF_EXTREF30C (0x00000094) /* ADC14 Gain Factor for External Reference 30°C */
-#define OFS_TLV_ADC14_GF_EXTREF85C (0x00000098) /* ADC14 Gain Factor for External Reference 85°C */
-#define OFS_TLV_ADC14_GF_BUF_EXTREF30C (0x0000009C) /* ADC14 Gain Factor for Buffered External Reference 30°C */
-#define OFS_TLV_ADC14_GF_BUF_EXTREF85C (0x000000A0) /* ADC14 Gain Factor for Buffered External Reference 85°C */
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0 (0x000000A4) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0 (0x000000A8) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1 (0x000000AC) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
-#define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1 (0x000000B0) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0 (0x000000B4) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0 (0x000000B8) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1 (0x000000BC) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
-#define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1 (0x000000C0) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0 (0x000000C4) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0 (0x000000C8) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1 (0x000000CC) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
-#define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1 (0x000000D0) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
-#define OFS_TLV_ADC14_OFFSET_VRSEL_1 (0x000000D4) /* ADC14 Offset (ADC14VRSEL = 1h) */
-#define OFS_TLV_ADC14_OFFSET_VRSEL_E (0x000000D8) /* ADC14 Offset (ADC14VRSEL = Eh) */
-#define OFS_TLV_ADC14_REF1P2V_TS30C (0x000000DC) /* ADC14 1.2V Reference Temp. Sensor 30°C */
-#define OFS_TLV_ADC14_REF1P2V_TS85C (0x000000E0) /* ADC14 1.2V Reference Temp. Sensor 85°C */
-#define OFS_TLV_ADC14_REF1P45V_TS30C (0x000000E4) /* ADC14 1.45V Reference Temp. Sensor 30°C */
-#define OFS_TLV_ADC14_REF1P45V_TS85C (0x000000E8) /* ADC14 1.45V Reference Temp. Sensor 85°C */
-#define OFS_TLV_ADC14_REF2P5V_TS30C (0x000000EC) /* ADC14 2.5V Reference Temp. Sensor 30°C */
-#define OFS_TLV_ADC14_REF2P5V_TS85C (0x000000F0) /* ADC14 2.5V Reference Temp. Sensor 85°C */
-#define OFS_TLV_REF_CAL_TAG (0x000000F4) /* REF Calibration Tag */
-#define OFS_TLV_REF_CAL_LEN (0x000000F8) /* REF Calibration Length */
-#define OFS_TLV_REF_1P2V (0x000000FC) /* REF 1.2V Reference */
-#define OFS_TLV_REF_1P45V (0x00000100) /* REF 1.45V Reference */
-#define OFS_TLV_REF_2P5V (0x00000104) /* REF 2.5V Reference */
-#define OFS_TLV_RANDOM_NUM_TAG (0x00000108) /* 128-bit Random Number Tag */
-#define OFS_TLV_RANDOM_NUM_LEN (0x0000010C) /* 128-bit Random Number Length */
-#define OFS_TLV_RANDOM_NUM_1 (0x00000110) /* 32-bit Random Number 1 */
-#define OFS_TLV_RANDOM_NUM_2 (0x00000114) /* 32-bit Random Number 2 */
-#define OFS_TLV_RANDOM_NUM_3 (0x00000118) /* 32-bit Random Number 3 */
-#define OFS_TLV_RANDOM_NUM_4 (0x0000011C) /* 32-bit Random Number 4 */
-#define OFS_TLV_BSL_CFG_TAG (0x00000120) /* BSL Configuration Tag */
-#define OFS_TLV_BSL_CFG_LEN (0x00000124) /* BSL Configuration Length */
-#define OFS_TLV_BSL_PERIPHIF_SEL (0x00000128) /* BSL Peripheral Interface Selection */
-#define OFS_TLV_BSL_PORTIF_CFG_UART (0x0000012C) /* BSL Port Interface Configuration for UART */
-#define OFS_TLV_BSL_PORTIF_CFG_SPI (0x00000130) /* BSL Port Interface Configuration for SPI */
-#define OFS_TLV_BSL_PORTIF_CFG_I2C (0x00000134) /* BSL Port Interface Configuration for I2C */
-#define OFS_TLV_TLV_END (0x00000138) /* TLV End Word */
-
-
-//*****************************************************************************
-// WDT_A Registers
-//*****************************************************************************
-#define WDTCTL (HWREG16(0x4000480C)) /* Watchdog Timer Control Register */
-
-/* Register offsets from WDT_A_BASE address */
-#define OFS_WDTCTL (0x000c) /* Watchdog Timer Control Register */
-
-
-//*****************************************************************************
-// CMSIS-format peripheral registers
-//*****************************************************************************
-
-//*****************************************************************************
-// ADC14 Registers
-//*****************************************************************************
+/******************************************************************************
+* ADC14 Registers
+******************************************************************************/
+/** @addtogroup ADC14 MSP432P401R (ADC14)
+ @{
+*/
typedef struct {
- union { /* ADC14CTL0 Register */
- __IO uint32_t r;
- struct { /* ADC14CTL0 Bits */
- __IO uint32_t bSC : 1; /* ADC14 start conversion */
- __IO uint32_t bENC : 1; /* ADC14 enable conversion */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bON : 1; /* ADC14 on */
- __I uint32_t bRESERVED1 : 2; /* Reserved */
- __IO uint32_t bMSC : 1; /* ADC14 multiple sample and conversion */
- __IO uint32_t bSHT0 : 4; /* ADC14 sample-and-hold time */
- __IO uint32_t bSHT1 : 4; /* ADC14 sample-and-hold time */
- __I uint32_t bBUSY : 1; /* ADC14 busy */
- __IO uint32_t bCONSEQ : 2; /* ADC14 conversion sequence mode select */
- __IO uint32_t bSSEL : 3; /* ADC14 clock source select */
- __IO uint32_t bDIV : 3; /* ADC14 clock divider */
- __IO uint32_t bISSH : 1; /* ADC14 invert signal sample-and-hold */
- __IO uint32_t bSHP : 1; /* ADC14 sample-and-hold pulse-mode select */
- __IO uint32_t bSHS : 3; /* ADC14 sample-and-hold source select */
- __IO uint32_t bPDIV : 2; /* ADC14 predivider */
- } b;
- } rCTL0;
- union { /* ADC14CTL1 Register */
- __IO uint32_t r;
- struct { /* ADC14CTL1 Bits */
- __IO uint32_t bPWRMD : 2; /* ADC14 power modes */
- __IO uint32_t bREFBURST : 1; /* ADC14 reference buffer burst */
- __IO uint32_t bDF : 1; /* ADC14 data read-back format */
- __IO uint32_t bRES : 2; /* ADC14 resolution */
- __I uint32_t bRESERVED0 : 10; /* Reserved */
- __IO uint32_t bCSTARTADD : 5; /* ADC14 conversion start address */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bBATMAP : 1; /* Controls 1/2 AVCC ADC input channel selection */
- __IO uint32_t bTCMAP : 1; /* Controls temperature sensor ADC input channel selection */
- __IO uint32_t bCH0MAP : 1; /* Controls internal channel 0 selection to ADC input channel MAX-2 */
- __IO uint32_t bCH1MAP : 1; /* Controls internal channel 1 selection to ADC input channel MAX-3 */
- __IO uint32_t bCH2MAP : 1; /* Controls internal channel 2 selection to ADC input channel MAX-4 */
- __IO uint32_t bCH3MAP : 1; /* Controls internal channel 3 selection to ADC input channel MAX-5 */
- __I uint32_t bRESERVED2 : 4; /* Reserved */
- } b;
- } rCTL1;
- union { /* ADC14LO0 Register */
- __IO uint32_t r;
- struct { /* ADC14LO0 Bits */
- __IO uint32_t bLO0 : 16; /* Low threshold 0 */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rLO0;
- union { /* ADC14HI0 Register */
- __IO uint32_t r;
- struct { /* ADC14HI0 Bits */
- __IO uint32_t bHI0 : 16; /* High threshold 0 */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rHI0;
- union { /* ADC14LO1 Register */
- __IO uint32_t r;
- struct { /* ADC14LO1 Bits */
- __IO uint32_t bLO1 : 16; /* Low threshold 1 */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rLO1;
- union { /* ADC14HI1 Register */
- __IO uint32_t r;
- struct { /* ADC14HI1 Bits */
- __IO uint32_t bHI1 : 16; /* High threshold 1 */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rHI1;
- union { /* ADC14MCTL0 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL0 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL0;
- union { /* ADC14MCTL1 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL1 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL1;
- union { /* ADC14MCTL2 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL2 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL2;
- union { /* ADC14MCTL3 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL3 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL3;
- union { /* ADC14MCTL4 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL4 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL4;
- union { /* ADC14MCTL5 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL5 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL5;
- union { /* ADC14MCTL6 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL6 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL6;
- union { /* ADC14MCTL7 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL7 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL7;
- union { /* ADC14MCTL8 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL8 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL8;
- union { /* ADC14MCTL9 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL9 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL9;
- union { /* ADC14MCTL10 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL10 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL10;
- union { /* ADC14MCTL11 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL11 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL11;
- union { /* ADC14MCTL12 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL12 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL12;
- union { /* ADC14MCTL13 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL13 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL13;
- union { /* ADC14MCTL14 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL14 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL14;
- union { /* ADC14MCTL15 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL15 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL15;
- union { /* ADC14MCTL16 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL16 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL16;
- union { /* ADC14MCTL17 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL17 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL17;
- union { /* ADC14MCTL18 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL18 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL18;
- union { /* ADC14MCTL19 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL19 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL19;
- union { /* ADC14MCTL20 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL20 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL20;
- union { /* ADC14MCTL21 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL21 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL21;
- union { /* ADC14MCTL22 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL22 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL22;
- union { /* ADC14MCTL23 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL23 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL23;
- union { /* ADC14MCTL24 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL24 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL24;
- union { /* ADC14MCTL25 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL25 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL25;
- union { /* ADC14MCTL26 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL26 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL26;
- union { /* ADC14MCTL27 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL27 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL27;
- union { /* ADC14MCTL28 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL28 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL28;
- union { /* ADC14MCTL29 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL29 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL29;
- union { /* ADC14MCTL30 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL30 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL30;
- union { /* ADC14MCTL31 Register */
- __IO uint32_t r;
- struct { /* ADC14MCTL31 Bits */
- __IO uint32_t bINCH : 5; /* Input channel select */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bEOS : 1; /* End of sequence */
- __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bDIF : 1; /* Differential mode */
- __IO uint32_t bWINC : 1; /* Comparator window enable */
- __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rMCTL31;
- union { /* ADC14MEM0 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM0 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM0;
- union { /* ADC14MEM1 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM1 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM1;
- union { /* ADC14MEM2 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM2 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM2;
- union { /* ADC14MEM3 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM3 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM3;
- union { /* ADC14MEM4 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM4 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM4;
- union { /* ADC14MEM5 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM5 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM5;
- union { /* ADC14MEM6 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM6 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM6;
- union { /* ADC14MEM7 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM7 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM7;
- union { /* ADC14MEM8 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM8 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM8;
- union { /* ADC14MEM9 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM9 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM9;
- union { /* ADC14MEM10 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM10 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM10;
- union { /* ADC14MEM11 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM11 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM11;
- union { /* ADC14MEM12 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM12 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM12;
- union { /* ADC14MEM13 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM13 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM13;
- union { /* ADC14MEM14 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM14 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM14;
- union { /* ADC14MEM15 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM15 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM15;
- union { /* ADC14MEM16 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM16 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM16;
- union { /* ADC14MEM17 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM17 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM17;
- union { /* ADC14MEM18 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM18 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM18;
- union { /* ADC14MEM19 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM19 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM19;
- union { /* ADC14MEM20 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM20 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM20;
- union { /* ADC14MEM21 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM21 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM21;
- union { /* ADC14MEM22 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM22 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM22;
- union { /* ADC14MEM23 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM23 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM23;
- union { /* ADC14MEM24 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM24 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM24;
- union { /* ADC14MEM25 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM25 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM25;
- union { /* ADC14MEM26 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM26 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM26;
- union { /* ADC14MEM27 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM27 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM27;
- union { /* ADC14MEM28 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM28 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM28;
- union { /* ADC14MEM29 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM29 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM29;
- union { /* ADC14MEM30 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM30 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM30;
- union { /* ADC14MEM31 Register */
- __IO uint32_t r;
- struct { /* ADC14MEM31 Bits */
- __IO uint32_t bCONVRES : 16; /* Conversion Result */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMEM31;
- uint8_t RESERVED0[36];
- union { /* ADC14IER0 Register */
- __IO uint32_t r;
- struct { /* ADC14IER0 Bits */
- __IO uint32_t bIE0 : 1; /* Interrupt enable */
- __IO uint32_t bIE1 : 1; /* Interrupt enable */
- __IO uint32_t bIE2 : 1; /* Interrupt enable */
- __IO uint32_t bIE3 : 1; /* Interrupt enable */
- __IO uint32_t bIE4 : 1; /* Interrupt enable */
- __IO uint32_t bIE5 : 1; /* Interrupt enable */
- __IO uint32_t bIE6 : 1; /* Interrupt enable */
- __IO uint32_t bIE7 : 1; /* Interrupt enable */
- __IO uint32_t bIE8 : 1; /* Interrupt enable */
- __IO uint32_t bIE9 : 1; /* Interrupt enable */
- __IO uint32_t bIE10 : 1; /* Interrupt enable */
- __IO uint32_t bIE11 : 1; /* Interrupt enable */
- __IO uint32_t bIE12 : 1; /* Interrupt enable */
- __IO uint32_t bIE13 : 1; /* Interrupt enable */
- __IO uint32_t bIE14 : 1; /* Interrupt enable */
- __IO uint32_t bIE15 : 1; /* Interrupt enable */
- __IO uint32_t bIE16 : 1; /* Interrupt enable */
- __IO uint32_t bIE17 : 1; /* Interrupt enable */
- __IO uint32_t bIE18 : 1; /* Interrupt enable */
- __IO uint32_t bIE19 : 1; /* Interrupt enable */
- __IO uint32_t bIE20 : 1; /* Interrupt enable */
- __IO uint32_t bIE21 : 1; /* Interrupt enable */
- __IO uint32_t bIE22 : 1; /* Interrupt enable */
- __IO uint32_t bIE23 : 1; /* Interrupt enable */
- __IO uint32_t bIE24 : 1; /* Interrupt enable */
- __IO uint32_t bIE25 : 1; /* Interrupt enable */
- __IO uint32_t bIE26 : 1; /* Interrupt enable */
- __IO uint32_t bIE27 : 1; /* Interrupt enable */
- __IO uint32_t bIE28 : 1; /* Interrupt enable */
- __IO uint32_t bIE29 : 1; /* Interrupt enable */
- __IO uint32_t bIE30 : 1; /* Interrupt enable */
- __IO uint32_t bIE31 : 1; /* Interrupt enable */
- } b;
- } rIER0;
- union { /* ADC14IER1 Register */
- __IO uint32_t r;
- struct { /* ADC14IER1 Bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bINIE : 1; /* Interrupt enable for ADC14MEMx within comparator window */
- __IO uint32_t bLOIE : 1; /* Interrupt enable for ADC14MEMx below comparator window */
- __IO uint32_t bHIIE : 1; /* Interrupt enable for ADC14MEMx above comparator window */
- __IO uint32_t bOVIE : 1; /* ADC14MEMx overflow-interrupt enable */
- __IO uint32_t bTOVIE : 1; /* ADC14 conversion-time-overflow interrupt enable */
- __IO uint32_t bRDYIE : 1; /* ADC14 local buffered reference ready interrupt enable */
- __I uint32_t bRESERVED1 : 25; /* Reserved */
- } b;
- } rIER1;
- union { /* ADC14IFGR0 Register */
- __I uint32_t r;
- struct { /* ADC14IFGR0 Bits */
- __I uint32_t bIFG0 : 1; /* ADC14MEM0 interrupt flag */
- __I uint32_t bIFG1 : 1; /* ADC14MEM1 interrupt flag */
- __I uint32_t bIFG2 : 1; /* ADC14MEM2 interrupt flag */
- __I uint32_t bIFG3 : 1; /* ADC14MEM3 interrupt flag */
- __I uint32_t bIFG4 : 1; /* ADC14MEM4 interrupt flag */
- __I uint32_t bIFG5 : 1; /* ADC14MEM5 interrupt flag */
- __I uint32_t bIFG6 : 1; /* ADC14MEM6 interrupt flag */
- __I uint32_t bIFG7 : 1; /* ADC14MEM7 interrupt flag */
- __I uint32_t bIFG8 : 1; /* ADC14MEM8 interrupt flag */
- __I uint32_t bIFG9 : 1; /* ADC14MEM9 interrupt flag */
- __I uint32_t bIFG10 : 1; /* ADC14MEM10 interrupt flag */
- __I uint32_t bIFG11 : 1; /* ADC14MEM11 interrupt flag */
- __I uint32_t bIFG12 : 1; /* ADC14MEM12 interrupt flag */
- __I uint32_t bIFG13 : 1; /* ADC14MEM13 interrupt flag */
- __I uint32_t bIFG14 : 1; /* ADC14MEM14 interrupt flag */
- __I uint32_t bIFG15 : 1; /* ADC14MEM15 interrupt flag */
- __I uint32_t bIFG16 : 1; /* ADC14MEM16 interrupt flag */
- __I uint32_t bIFG17 : 1; /* ADC14MEM17 interrupt flag */
- __I uint32_t bIFG18 : 1; /* ADC14MEM18 interrupt flag */
- __I uint32_t bIFG19 : 1; /* ADC14MEM19 interrupt flag */
- __I uint32_t bIFG20 : 1; /* ADC14MEM20 interrupt flag */
- __I uint32_t bIFG21 : 1; /* ADC14MEM21 interrupt flag */
- __I uint32_t bIFG22 : 1; /* ADC14MEM22 interrupt flag */
- __I uint32_t bIFG23 : 1; /* ADC14MEM23 interrupt flag */
- __I uint32_t bIFG24 : 1; /* ADC14MEM24 interrupt flag */
- __I uint32_t bIFG25 : 1; /* ADC14MEM25 interrupt flag */
- __I uint32_t bIFG26 : 1; /* ADC14MEM26 interrupt flag */
- __I uint32_t bIFG27 : 1; /* ADC14MEM27 interrupt flag */
- __I uint32_t bIFG28 : 1; /* ADC14MEM28 interrupt flag */
- __I uint32_t bIFG29 : 1; /* ADC14MEM29 interrupt flag */
- __I uint32_t bIFG30 : 1; /* ADC14MEM30 interrupt flag */
- __I uint32_t bIFG31 : 1; /* ADC14MEM31 interrupt flag */
- } b;
- } rIFGR0;
- union { /* ADC14IFGR1 Register */
- __I uint32_t r;
- struct { /* ADC14IFGR1 Bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __I uint32_t bINIFG : 1; /* Interrupt flag for ADC14MEMx within comparator window */
- __I uint32_t bLOIFG : 1; /* Interrupt flag for ADC14MEMx below comparator window */
- __I uint32_t bHIIFG : 1; /* Interrupt flag for ADC14MEMx above comparator window */
- __I uint32_t bOVIFG : 1; /* ADC14MEMx overflow interrupt flag */
- __I uint32_t bTOVIFG : 1; /* ADC14 conversion time overflow interrupt flag */
- __I uint32_t bRDYIFG : 1; /* ADC14 local buffered reference ready interrupt flag */
- __I uint32_t bRESERVED1 : 25; /* Reserved */
- } b;
- } rIFGR1;
- union { /* ADC14CLRIFGR0 Register */
- __O uint32_t r;
- struct { /* ADC14CLRIFGR0 Bits */
- __O uint32_t bCLRIFG0 : 1; /* clear ADC14IFG0 */
- __O uint32_t bCLRIFG1 : 1; /* clear ADC14IFG1 */
- __O uint32_t bCLRIFG2 : 1; /* clear ADC14IFG2 */
- __O uint32_t bCLRIFG3 : 1; /* clear ADC14IFG3 */
- __O uint32_t bCLRIFG4 : 1; /* clear ADC14IFG4 */
- __O uint32_t bCLRIFG5 : 1; /* clear ADC14IFG5 */
- __O uint32_t bCLRIFG6 : 1; /* clear ADC14IFG6 */
- __O uint32_t bCLRIFG7 : 1; /* clear ADC14IFG7 */
- __O uint32_t bCLRIFG8 : 1; /* clear ADC14IFG8 */
- __O uint32_t bCLRIFG9 : 1; /* clear ADC14IFG9 */
- __O uint32_t bCLRIFG10 : 1; /* clear ADC14IFG10 */
- __O uint32_t bCLRIFG11 : 1; /* clear ADC14IFG11 */
- __O uint32_t bCLRIFG12 : 1; /* clear ADC14IFG12 */
- __O uint32_t bCLRIFG13 : 1; /* clear ADC14IFG13 */
- __O uint32_t bCLRIFG14 : 1; /* clear ADC14IFG14 */
- __O uint32_t bCLRIFG15 : 1; /* clear ADC14IFG15 */
- __O uint32_t bCLRIFG16 : 1; /* clear ADC14IFG16 */
- __O uint32_t bCLRIFG17 : 1; /* clear ADC14IFG17 */
- __O uint32_t bCLRIFG18 : 1; /* clear ADC14IFG18 */
- __O uint32_t bCLRIFG19 : 1; /* clear ADC14IFG19 */
- __O uint32_t bCLRIFG20 : 1; /* clear ADC14IFG20 */
- __O uint32_t bCLRIFG21 : 1; /* clear ADC14IFG21 */
- __O uint32_t bCLRIFG22 : 1; /* clear ADC14IFG22 */
- __O uint32_t bCLRIFG23 : 1; /* clear ADC14IFG23 */
- __O uint32_t bCLRIFG24 : 1; /* clear ADC14IFG24 */
- __O uint32_t bCLRIFG25 : 1; /* clear ADC14IFG25 */
- __O uint32_t bCLRIFG26 : 1; /* clear ADC14IFG26 */
- __O uint32_t bCLRIFG27 : 1; /* clear ADC14IFG27 */
- __O uint32_t bCLRIFG28 : 1; /* clear ADC14IFG28 */
- __O uint32_t bCLRIFG29 : 1; /* clear ADC14IFG29 */
- __O uint32_t bCLRIFG30 : 1; /* clear ADC14IFG30 */
- __O uint32_t bCLRIFG31 : 1; /* clear ADC14IFG31 */
- } b;
- } rCLRIFGR0;
- union { /* ADC14CLRIFGR1 Register */
- __IO uint32_t r;
- struct { /* ADC14CLRIFGR1 Bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __O uint32_t bCLRINIFG : 1; /* clear ADC14INIFG */
- __O uint32_t bCLRLOIFG : 1; /* clear ADC14LOIFG */
- __O uint32_t bCLRHIIFG : 1; /* clear ADC14HIIFG */
- __O uint32_t bCLROVIFG : 1; /* clear ADC14OVIFG */
- __O uint32_t bCLRTOVIFG : 1; /* clear ADC14TOVIFG */
- __O uint32_t bCLRRDYIFG : 1; /* clear ADC14RDYIFG */
- __I uint32_t bRESERVED1 : 25; /* Reserved */
- } b;
- } rCLRIFGR1;
- __IO uint32_t rIV; /* Interrupt Vector Register */
+ __IO uint32_t CTL0; /**< Control 0 Register */
+ __IO uint32_t CTL1; /**< Control 1 Register */
+ __IO uint32_t LO0; /**< Window Comparator Low Threshold 0 Register */
+ __IO uint32_t HI0; /**< Window Comparator High Threshold 0 Register */
+ __IO uint32_t LO1; /**< Window Comparator Low Threshold 1 Register */
+ __IO uint32_t HI1; /**< Window Comparator High Threshold 1 Register */
+ __IO uint32_t MCTL[32]; /**< Conversion Memory Control Register */
+ __IO uint32_t MEM[32]; /**< Conversion Memory Register */
+ uint32_t RESERVED0[9];
+ __IO uint32_t IER0; /**< Interrupt Enable 0 Register */
+ __IO uint32_t IER1; /**< Interrupt Enable 1 Register */
+ __I uint32_t IFGR0; /**< Interrupt Flag 0 Register */
+ __I uint32_t IFGR1; /**< Interrupt Flag 1 Register */
+ __O uint32_t CLRIFGR0; /**< Clear Interrupt Flag 0 Register */
+ __IO uint32_t CLRIFGR1; /**< Clear Interrupt Flag 1 Register */
+ __IO uint32_t IV; /**< Interrupt Vector Register */
} ADC14_Type;
+/*@}*/ /* end of group ADC14 */
-//*****************************************************************************
-// AES256 Registers
-//*****************************************************************************
+
+/******************************************************************************
+* AES256 Registers
+******************************************************************************/
+/** @addtogroup AES256 MSP432P401R (AES256)
+ @{
+*/
typedef struct {
- union { /* AESACTL0 Register */
- __IO uint16_t r;
- struct { /* AESACTL0 Bits */
- __IO uint16_t bOP : 2; /* AES operation */
- __IO uint16_t bKL : 2; /* AES key length */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bCM : 2; /* AES cipher mode select */
- __IO uint16_t bSWRST : 1; /* AES software reset */
- __IO uint16_t bRDYIFG : 1; /* AES ready interrupt flag */
- __I uint16_t bRESERVED1 : 2; /* Reserved */
- __IO uint16_t bERRFG : 1; /* AES error flag */
- __IO uint16_t bRDYIE : 1; /* AES ready interrupt enable */
- __I uint16_t bRESERVED2 : 2; /* Reserved */
- __IO uint16_t bCMEN : 1; /* AES cipher mode enable */
- } b;
- } rCTL0;
- union { /* AESACTL1 Register */
- __IO uint16_t r;
- struct { /* AESACTL1 Bits */
- __IO uint16_t bBLKCNT : 8; /* Cipher Block Counter */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- } rCTL1;
- union { /* AESASTAT Register */
- __IO uint16_t r;
- struct { /* AESASTAT Bits */
- __IO uint16_t bBUSY : 1; /* AES accelerator module busy */
- __IO uint16_t bKEYWR : 1; /* All 16 bytes written to AESAKEY */
- __IO uint16_t bDINWR : 1; /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
- __I uint16_t bDOUTRD : 1; /* All 16 bytes read from AESADOUT */
- __I uint16_t bKEYCNT : 4; /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
- __I uint16_t bDINCNT : 4; /* Bytes written via AESADIN, AESAXDIN or AESAXIN */
- __I uint16_t bDOUTCNT : 4; /* Bytes read via AESADOUT */
- } b;
- } rSTAT;
- union { /* AESAKEY Register */
- __O uint16_t r;
- struct { /* AESAKEY Bits */
- __O uint16_t bKEY0 : 8; /* AES key byte n when AESAKEY is written as half-word */
- __O uint16_t bKEY1 : 8; /* AES key byte n+1 when AESAKEY is written as half-word */
- } b;
- } rKEY;
- union { /* AESADIN Register */
- __O uint16_t r;
- struct { /* AESADIN Bits */
- __O uint16_t bDIN0 : 8; /* AES data in byte n when AESADIN is written as half-word */
- __O uint16_t bDIN1 : 8; /* AES data in byte n+1 when AESADIN is written as half-word */
- } b;
- } rDIN;
- union { /* AESADOUT Register */
- __O uint16_t r;
- struct { /* AESADOUT Bits */
- __O uint16_t bDOUT0 : 8; /* AES data out byte n when AESADOUT is read as half-word */
- __O uint16_t bDOUT1 : 8; /* AES data out byte n+1 when AESADOUT is read as half-word */
- } b;
- } rDOUT;
- union { /* AESAXDIN Register */
- __O uint16_t r;
- struct { /* AESAXDIN Bits */
- __O uint16_t bXDIN0 : 8; /* AES data in byte n when AESAXDIN is written as half-word */
- __O uint16_t bXDIN1 : 8; /* AES data in byte n+1 when AESAXDIN is written as half-word */
- } b;
- } rXDIN;
- union { /* AESAXIN Register */
- __O uint16_t r;
- struct { /* AESAXIN Bits */
- __O uint16_t bXIN0 : 8; /* AES data in byte n when AESAXIN is written as half-word */
- __O uint16_t bXIN1 : 8; /* AES data in byte n+1 when AESAXIN is written as half-word */
- } b;
- } rXIN;
+ __IO uint16_t CTL0; /**< AES Accelerator Control Register 0 */
+ __IO uint16_t CTL1; /**< AES Accelerator Control Register 1 */
+ __IO uint16_t STAT; /**< AES Accelerator Status Register */
+ __O uint16_t KEY; /**< AES Accelerator Key Register */
+ __O uint16_t DIN; /**< AES Accelerator Data In Register */
+ __O uint16_t DOUT; /**< AES Accelerator Data Out Register */
+ __O uint16_t XDIN; /**< AES Accelerator XORed Data In Register */
+ __O uint16_t XIN; /**< AES Accelerator XORed Data In Register */
} AES256_Type;
+/*@}*/ /* end of group AES256 */
-//*****************************************************************************
-// CAPTIO0 Registers
-//*****************************************************************************
+
+/******************************************************************************
+* CAPTIO Registers
+******************************************************************************/
+/** @addtogroup CAPTIO MSP432P401R (CAPTIO)
+ @{
+*/
typedef struct {
- uint8_t RESERVED0[14];
- union { /* CAPTIO0CTL Register */
- __IO uint16_t r;
- struct { /* CAPTIO0CTL Bits */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bPISEL : 3; /* Capacitive Touch IO pin select */
- __IO uint16_t bPOSEL : 4; /* Capacitive Touch IO port select */
- __IO uint16_t bEN : 1; /* Capacitive Touch IO enable */
- __I uint16_t bSTATE : 1; /* Capacitive Touch IO state */
- __I uint16_t bRESERVED1 : 6; /* Reserved */
- } b;
- } rCTL;
-} CAPTIO0_Type;
+ uint16_t RESERVED0[7];
+ __IO uint16_t CTL; /**< Capacitive Touch IO x Control Register */
+} CAPTIO_Type;
+
+/*@}*/ /* end of group CAPTIO */
-//*****************************************************************************
-// CAPTIO1 Registers
-//*****************************************************************************
+/******************************************************************************
+* COMP_E Registers
+******************************************************************************/
+/** @addtogroup COMP_E MSP432P401R (COMP_E)
+ @{
+*/
typedef struct {
- uint8_t RESERVED0[14];
- union { /* CAPTIO1CTL Register */
- __IO uint16_t r;
- struct { /* CAPTIO1CTL Bits */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bPISEL : 3; /* Capacitive Touch IO pin select */
- __IO uint16_t bPOSEL : 4; /* Capacitive Touch IO port select */
- __IO uint16_t bEN : 1; /* Capacitive Touch IO enable */
- __I uint16_t bSTATE : 1; /* Capacitive Touch IO state */
- __I uint16_t bRESERVED1 : 6; /* Reserved */
- } b;
- } rCTL;
-} CAPTIO1_Type;
+ __IO uint16_t CTL0; /**< Comparator Control Register 0 */
+ __IO uint16_t CTL1; /**< Comparator Control Register 1 */
+ __IO uint16_t CTL2; /**< Comparator Control Register 2 */
+ __IO uint16_t CTL3; /**< Comparator Control Register 3 */
+ uint16_t RESERVED0[2];
+ __IO uint16_t INT; /**< Comparator Interrupt Control Register */
+ __I uint16_t IV; /**< Comparator Interrupt Vector Word Register */
+} COMP_E_Type;
+
+/*@}*/ /* end of group COMP_E */
-//*****************************************************************************
-// COMP_E0 Registers
-//*****************************************************************************
+/******************************************************************************
+* CRC32 Registers
+******************************************************************************/
+/** @addtogroup CRC32 MSP432P401R (CRC32)
+ @{
+*/
typedef struct {
- union { /* CE0CTL0 Register */
- __IO uint16_t r;
- struct { /* CE0CTL0 Bits */
- __IO uint16_t bIPSEL : 4; /* Channel input selected for the V+ terminal */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bIPEN : 1; /* Channel input enable for the V+ terminal */
- __IO uint16_t bIMSEL : 4; /* Channel input selected for the - terminal */
- __I uint16_t bRESERVED1 : 3; /* Reserved */
- __IO uint16_t bIMEN : 1; /* Channel input enable for the - terminal */
- } b;
- } rCTL0;
- union { /* CE0CTL1 Register */
- __IO uint16_t r;
- struct { /* CE0CTL1 Bits */
- __IO uint16_t bOUT : 1; /* Comparator output value */
- __IO uint16_t bOUTPOL : 1; /* Comparator output polarity */
- __IO uint16_t bF : 1; /* Comparator output filter */
- __IO uint16_t bIES : 1; /* Interrupt edge select for CEIIFG and CEIFG */
- __IO uint16_t bSHORT : 1; /* Input short */
- __IO uint16_t bEX : 1; /* Exchange */
- __IO uint16_t bFDLY : 2; /* Filter delay */
- __IO uint16_t bPWRMD : 2; /* Power Mode */
- __IO uint16_t bON : 1; /* Comparator On */
- __IO uint16_t bMRVL : 1; /* This bit is valid of CEMRVS is set to 1 */
- __IO uint16_t bMRVS : 1; /* */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- } b;
- } rCTL1;
- union { /* CE0CTL2 Register */
- __IO uint16_t r;
- struct { /* CE0CTL2 Bits */
- __IO uint16_t bREF0 : 5; /* Reference resistor tap 0 */
- __IO uint16_t bRSEL : 1; /* Reference select */
- __IO uint16_t bRS : 2; /* Reference source */
- __IO uint16_t bREF1 : 5; /* Reference resistor tap 1 */
- __IO uint16_t bREFL : 2; /* Reference voltage level */
- __IO uint16_t bREFACC : 1; /* Reference accuracy */
- } b;
- } rCTL2;
- union { /* CE0CTL3 Register */
- __IO uint16_t r;
- struct { /* CE0CTL3 Bits */
- __IO uint16_t bPD0 : 1; /* Port disable */
- __IO uint16_t bPD1 : 1; /* Port disable */
- __IO uint16_t bPD2 : 1; /* Port disable */
- __IO uint16_t bPD3 : 1; /* Port disable */
- __IO uint16_t bPD4 : 1; /* Port disable */
- __IO uint16_t bPD5 : 1; /* Port disable */
- __IO uint16_t bPD6 : 1; /* Port disable */
- __IO uint16_t bPD7 : 1; /* Port disable */
- __IO uint16_t bPD8 : 1; /* Port disable */
- __IO uint16_t bPD9 : 1; /* Port disable */
- __IO uint16_t bPD10 : 1; /* Port disable */
- __IO uint16_t bPD11 : 1; /* Port disable */
- __IO uint16_t bPD12 : 1; /* Port disable */
- __IO uint16_t bPD13 : 1; /* Port disable */
- __IO uint16_t bPD14 : 1; /* Port disable */
- __IO uint16_t bPD15 : 1; /* Port disable */
- } b;
- } rCTL3;
- uint8_t RESERVED0[4];
- union { /* CE0INT Register */
- __IO uint16_t r;
- struct { /* CE0INT Bits */
- __IO uint16_t bIFG : 1; /* Comparator output interrupt flag */
- __IO uint16_t bIIFG : 1; /* Comparator output inverted interrupt flag */
- __I uint16_t bRESERVED0 : 2; /* Reserved */
- __IO uint16_t bRDYIFG : 1; /* Comparator ready interrupt flag */
- __I uint16_t bRESERVED1 : 3; /* Reserved */
- __IO uint16_t bIE : 1; /* Comparator output interrupt enable */
- __IO uint16_t bIIE : 1; /* Comparator output interrupt enable inverted polarity */
- __I uint16_t bRESERVED2 : 2; /* Reserved */
- __IO uint16_t bRDYIE : 1; /* Comparator ready interrupt enable */
- __I uint16_t bRESERVED3 : 3; /* Reserved */
- } b;
- } rINT;
- __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */
-} COMP_E0_Type;
-
-
-//*****************************************************************************
-// COMP_E1 Registers
-//*****************************************************************************
-typedef struct {
- union { /* CE1CTL0 Register */
- __IO uint16_t r;
- struct { /* CE1CTL0 Bits */
- __IO uint16_t bIPSEL : 4; /* Channel input selected for the V+ terminal */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bIPEN : 1; /* Channel input enable for the V+ terminal */
- __IO uint16_t bIMSEL : 4; /* Channel input selected for the - terminal */
- __I uint16_t bRESERVED1 : 3; /* Reserved */
- __IO uint16_t bIMEN : 1; /* Channel input enable for the - terminal */
- } b;
- } rCTL0;
- union { /* CE1CTL1 Register */
- __IO uint16_t r;
- struct { /* CE1CTL1 Bits */
- __IO uint16_t bOUT : 1; /* Comparator output value */
- __IO uint16_t bOUTPOL : 1; /* Comparator output polarity */
- __IO uint16_t bF : 1; /* Comparator output filter */
- __IO uint16_t bIES : 1; /* Interrupt edge select for CEIIFG and CEIFG */
- __IO uint16_t bSHORT : 1; /* Input short */
- __IO uint16_t bEX : 1; /* Exchange */
- __IO uint16_t bFDLY : 2; /* Filter delay */
- __IO uint16_t bPWRMD : 2; /* Power Mode */
- __IO uint16_t bON : 1; /* Comparator On */
- __IO uint16_t bMRVL : 1; /* This bit is valid of CEMRVS is set to 1 */
- __IO uint16_t bMRVS : 1; /* */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- } b;
- } rCTL1;
- union { /* CE1CTL2 Register */
- __IO uint16_t r;
- struct { /* CE1CTL2 Bits */
- __IO uint16_t bREF0 : 5; /* Reference resistor tap 0 */
- __IO uint16_t bRSEL : 1; /* Reference select */
- __IO uint16_t bRS : 2; /* Reference source */
- __IO uint16_t bREF1 : 5; /* Reference resistor tap 1 */
- __IO uint16_t bREFL : 2; /* Reference voltage level */
- __IO uint16_t bREFACC : 1; /* Reference accuracy */
- } b;
- } rCTL2;
- union { /* CE1CTL3 Register */
- __IO uint16_t r;
- struct { /* CE1CTL3 Bits */
- __IO uint16_t bPD0 : 1; /* Port disable */
- __IO uint16_t bPD1 : 1; /* Port disable */
- __IO uint16_t bPD2 : 1; /* Port disable */
- __IO uint16_t bPD3 : 1; /* Port disable */
- __IO uint16_t bPD4 : 1; /* Port disable */
- __IO uint16_t bPD5 : 1; /* Port disable */
- __IO uint16_t bPD6 : 1; /* Port disable */
- __IO uint16_t bPD7 : 1; /* Port disable */
- __IO uint16_t bPD8 : 1; /* Port disable */
- __IO uint16_t bPD9 : 1; /* Port disable */
- __IO uint16_t bPD10 : 1; /* Port disable */
- __IO uint16_t bPD11 : 1; /* Port disable */
- __IO uint16_t bPD12 : 1; /* Port disable */
- __IO uint16_t bPD13 : 1; /* Port disable */
- __IO uint16_t bPD14 : 1; /* Port disable */
- __IO uint16_t bPD15 : 1; /* Port disable */
- } b;
- } rCTL3;
- uint8_t RESERVED0[4];
- union { /* CE1INT Register */
- __IO uint16_t r;
- struct { /* CE1INT Bits */
- __IO uint16_t bIFG : 1; /* Comparator output interrupt flag */
- __IO uint16_t bIIFG : 1; /* Comparator output inverted interrupt flag */
- __I uint16_t bRESERVED0 : 2; /* Reserved */
- __IO uint16_t bRDYIFG : 1; /* Comparator ready interrupt flag */
- __I uint16_t bRESERVED1 : 3; /* Reserved */
- __IO uint16_t bIE : 1; /* Comparator output interrupt enable */
- __IO uint16_t bIIE : 1; /* Comparator output interrupt enable inverted polarity */
- __I uint16_t bRESERVED2 : 2; /* Reserved */
- __IO uint16_t bRDYIE : 1; /* Comparator ready interrupt enable */
- __I uint16_t bRESERVED3 : 3; /* Reserved */
- } b;
- } rINT;
- __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */
-} COMP_E1_Type;
-
-
-//*****************************************************************************
-// CRC32 Registers
-//*****************************************************************************
-typedef struct {
- __IO uint16_t rCRC32DI; /* Data Input for CRC32 Signature Computation */
- uint8_t RESERVED0[2];
- __IO uint16_t rCRC32DIRB; /* Data In Reverse for CRC32 Computation */
- uint8_t RESERVED1[2];
- __IO uint16_t rCRC32INIRES_LO; /* CRC32 Initialization and Result, lower 16 bits */
- __IO uint16_t rCRC32INIRES_HI; /* CRC32 Initialization and Result, upper 16 bits */
- __IO uint16_t rCRC32RESR_LO; /* CRC32 Result Reverse, lower 16 bits */
- __IO uint16_t rCRC32RESR_HI; /* CRC32 Result Reverse, Upper 16 bits */
- __IO uint16_t rCRC16DI; /* Data Input for CRC16 computation */
- uint8_t RESERVED2[2];
- __IO uint16_t rCRC16DIRB; /* CRC16 Data In Reverse */
- uint8_t RESERVED3[2];
- __IO uint16_t rCRC16INIRES; /* CRC16 Initialization and Result register */
- uint8_t RESERVED4[4];
- __IO uint16_t rCRC16RESR; /* CRC16 Result Reverse */
+ __IO uint16_t DI32; /**< Data Input for CRC32 Signature Computation */
+ uint16_t RESERVED0;
+ __IO uint16_t DIRB32; /**< Data In Reverse for CRC32 Computation */
+ uint16_t RESERVED1;
+ __IO uint16_t INIRES32_LO; /**< CRC32 Initialization and Result, lower 16 bits */
+ __IO uint16_t INIRES32_HI; /**< CRC32 Initialization and Result, upper 16 bits */
+ __IO uint16_t RESR32_LO; /**< CRC32 Result Reverse, lower 16 bits */
+ __IO uint16_t RESR32_HI; /**< CRC32 Result Reverse, Upper 16 bits */
+ __IO uint16_t DI16; /**< Data Input for CRC16 computation */
+ uint16_t RESERVED2;
+ __IO uint16_t DIRB16; /**< CRC16 Data In Reverse */
+ uint16_t RESERVED3;
+ __IO uint16_t INIRES16; /**< CRC16 Initialization and Result register */
+ uint16_t RESERVED4[2];
+ __IO uint16_t RESR16; /**< CRC16 Result Reverse */
} CRC32_Type;
+/*@}*/ /* end of group CRC32 */
-//*****************************************************************************
-// CS Registers
-//*****************************************************************************
+
+/******************************************************************************
+* CS Registers
+******************************************************************************/
+/** @addtogroup CS MSP432P401R (CS)
+ @{
+*/
typedef struct {
- union { /* CSKEY Register */
- __IO uint32_t r;
- struct { /* CSKEY Bits */
- __IO uint32_t bKEY : 16; /* Write xxxx_695Ah to unlock */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rKEY;
- union { /* CSCTL0 Register */
- __IO uint32_t r;
- struct { /* CSCTL0 Bits */
- __IO uint32_t bDCOTUNE : 13; /* DCO frequency tuning select */
- __I uint32_t bRESERVED0 : 3; /* Reserved */
- __IO uint32_t bDCORSEL : 3; /* DCO frequency range select */
- __I uint32_t bRESERVED1 : 3; /* Reserved */
- __IO uint32_t bDCORES : 1; /* Enables the DCO external resistor mode */
- __IO uint32_t bDCOEN : 1; /* Enables the DCO oscillator */
- __IO uint32_t bDIS_DCO_DELAY_CNT : 1; /* */
- __I uint32_t bRESERVED2 : 7; /* Reserved */
- } b;
- } rCTL0;
- union { /* CSCTL1 Register */
- __IO uint32_t r;
- struct { /* CSCTL1 Bits */
- __IO uint32_t bSELM : 3; /* Selects the MCLK source */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bSELS : 3; /* Selects the SMCLK and HSMCLK source */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bSELA : 3; /* Selects the ACLK source */
- __I uint32_t bRESERVED2 : 1; /* Reserved */
- __IO uint32_t bSELB : 1; /* Selects the BCLK source */
- __I uint32_t bRESERVED3 : 3; /* Reserved */
- __IO uint32_t bDIVM : 3; /* MCLK source divider */
- __I uint32_t bRESERVED4 : 1; /* Reserved */
- __IO uint32_t bDIVHS : 3; /* HSMCLK source divider */
- __I uint32_t bRESERVED5 : 1; /* Reserved */
- __IO uint32_t bDIVA : 3; /* ACLK source divider */
- __I uint32_t bRESERVED6 : 1; /* Reserved */
- __IO uint32_t bDIVS : 3; /* SMCLK source divider */
- __I uint32_t bRESERVED7 : 1; /* Reserved */
- } b;
- } rCTL1;
- union { /* CSCTL2 Register */
- __IO uint32_t r;
- struct { /* CSCTL2 Bits */
- __IO uint32_t bLFXTDRIVE : 3; /* LFXT oscillator current can be adjusted to its drive needs */
- __IO uint32_t bRESERVED0 : 4; /* Reserved */
- __IO uint32_t bLFXTAGCOFF : 1; /* Disables the automatic gain control of the LFXT crystal */
- __IO uint32_t bLFXT_EN : 1; /* Turns on the LFXT oscillator regardless if used as a clock resource */
- __IO uint32_t bLFXTBYPASS : 1; /* LFXT bypass select */
- __I uint32_t bRESERVED1 : 6; /* Reserved */
- __IO uint32_t bHFXTDRIVE : 1; /* HFXT oscillator drive selection */
- __IO uint32_t bRESERVED5 : 2; /* Reserved */
- __I uint32_t bRESERVED2 : 1; /* Reserved */
- __IO uint32_t bHFXTFREQ : 3; /* HFXT frequency selection */
- __I uint32_t bRESERVED3 : 1; /* Reserved */
- __IO uint32_t bHFXT_EN : 1; /* Turns on the HFXT oscillator regardless if used as a clock resource */
- __IO uint32_t bHFXTBYPASS : 1; /* HFXT bypass select */
- __I uint32_t bRESERVED4 : 6; /* Reserved */
- } b;
- } rCTL2;
- union { /* CSCTL3 Register */
- __IO uint32_t r;
- struct { /* CSCTL3 Bits */
- __IO uint32_t bFCNTLF : 2; /* Start flag counter for LFXT */
- __O uint32_t bRFCNTLF : 1; /* Reset start fault counter for LFXT */
- __IO uint32_t bFCNTLF_EN : 1; /* Enable start fault counter for LFXT */
- __IO uint32_t bFCNTHF : 2; /* Start flag counter for HFXT */
- __O uint32_t bRFCNTHF : 1; /* Reset start fault counter for HFXT */
- __IO uint32_t bFCNTHF_EN : 1; /* Enable start fault counter for HFXT */
- __IO uint32_t bFCNTHF2 : 2; /* Start flag counter for HFXT2 */
- __O uint32_t bRFCNTHF2 : 1; /* Reset start fault counter for HFXT2 */
- __IO uint32_t bFCNTHF2_EN : 1; /* Enable start fault counter for HFXT2 */
- __I uint32_t bRESERVED0 : 20; /* Reserved */
- } b;
- } rCTL3;
- union { /* CSCTL4 Register */
- __IO uint32_t r;
- struct { /* CSCTL4 Bits */
- __IO uint32_t bHFXT2DRIVE : 3; /* HFXT2 oscillator current can be adjusted to its drive needs */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bHFXT2FREQ : 3; /* HFXT2 frequency selection */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bHFXT2_EN : 1; /* Turns on the HFXT2 oscillator */
- __IO uint32_t bHFXT2BYPASS : 1; /* HFXT2 bypass select */
- __I uint32_t bRESERVED2 : 22; /* Reserved */
- } b;
- } rCTL4;
- union { /* CSCTL5 Register */
- __IO uint32_t r;
- struct { /* CSCTL5 Bits */
- __IO uint32_t bREFCNTSEL : 3; /* Reference counter source select */
- __IO uint32_t bREFCNTPS : 3; /* Reference clock prescaler */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __O uint32_t bCALSTART : 1; /* Start clock calibration counters */
- __IO uint32_t bPERCNTSEL : 3; /* Period counter source select */
- __I uint32_t bRESERVED1 : 21; /* Reserved */
- } b;
- } rCTL5;
- union { /* CSCTL6 Register */
- __IO uint32_t r;
- struct { /* CSCTL6 Bits */
- __I uint32_t bPERCNT : 16; /* Calibration period counter */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rCTL6;
- union { /* CSCTL7 Register */
- __IO uint32_t r;
- struct { /* CSCTL7 Bits */
- __IO uint32_t bREFCNT : 16; /* Calibration reference period counter */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rCTL7;
- uint8_t RESERVED0[12];
- union { /* CSCLKEN Register */
- __IO uint32_t r;
- struct { /* CSCLKEN Bits */
- __IO uint32_t bACLK_EN : 1; /* ACLK system clock conditional request enable */
- __IO uint32_t bMCLK_EN : 1; /* MCLK system clock conditional request enable */
- __IO uint32_t bHSMCLK_EN : 1; /* HSMCLK system clock conditional request enable */
- __IO uint32_t bSMCLK_EN : 1; /* SMCLK system clock conditional request enable */
- __I uint32_t bRESERVED0 : 4; /* Reserved */
- __IO uint32_t bVLO_EN : 1; /* Turns on the VLO oscillator */
- __IO uint32_t bREFO_EN : 1; /* Turns on the REFO oscillator */
- __IO uint32_t bMODOSC_EN : 1; /* Turns on the MODOSC oscillator */
- __I uint32_t bRESERVED1 : 4; /* Reserved */
- __IO uint32_t bREFOFSEL : 1; /* Selects REFO nominal frequency */
- __I uint32_t bRESERVED2 : 16; /* Reserved */
- } b;
- } rCLKEN;
- union { /* CSSTAT Register */
- __I uint32_t r;
- struct { /* CSSTAT Bits */
- __I uint32_t bDCO_ON : 1; /* DCO status */
- __I uint32_t bDCOBIAS_ON : 1; /* DCO bias status */
- __I uint32_t bHFXT_ON : 1; /* HFXT status */
- __I uint32_t bHFXT2_ON : 1; /* HFXT2 status */
- __I uint32_t bMODOSC_ON : 1; /* MODOSC status */
- __I uint32_t bVLO_ON : 1; /* VLO status */
- __I uint32_t bLFXT_ON : 1; /* LFXT status */
- __I uint32_t bREFO_ON : 1; /* REFO status */
- __I uint32_t bRESERVED0 : 8; /* Reserved */
- __I uint32_t bACLK_ON : 1; /* ACLK system clock status */
- __I uint32_t bMCLK_ON : 1; /* MCLK system clock status */
- __I uint32_t bHSMCLK_ON : 1; /* HSMCLK system clock status */
- __I uint32_t bSMCLK_ON : 1; /* SMCLK system clock status */
- __I uint32_t bMODCLK_ON : 1; /* MODCLK system clock status */
- __I uint32_t bVLOCLK_ON : 1; /* VLOCLK system clock status */
- __I uint32_t bLFXTCLK_ON : 1; /* LFXTCLK system clock status */
- __I uint32_t bREFOCLK_ON : 1; /* REFOCLK system clock status */
- __I uint32_t bACLK_READY : 1; /* ACLK Ready status */
- __I uint32_t bMCLK_READY : 1; /* MCLK Ready status */
- __I uint32_t bHSMCLK_READY : 1; /* HSMCLK Ready status */
- __I uint32_t bSMCLK_READY : 1; /* SMCLK Ready status */
- __I uint32_t bBCLK_READY : 1; /* BCLK Ready status */
- __I uint32_t bRESERVED1 : 3; /* Reserved */
- } b;
- } rSTAT;
- uint8_t RESERVED1[8];
- union { /* CSIE Register */
- __IO uint32_t r;
- struct { /* CSIE Bits */
- __IO uint32_t bLFXTIE : 1; /* LFXT oscillator fault flag interrupt enable */
- __IO uint32_t bHFXTIE : 1; /* HFXT oscillator fault flag interrupt enable */
- __IO uint32_t bHFXT2IE : 1; /* HFXT2 oscillator fault flag interrupt enable */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bDCOMINIE : 1; /* DCO minimum fault flag interrupt enable */
- __IO uint32_t bDCOMAXIE : 1; /* DCO maximum fault flag interrupt enable */
- __IO uint32_t bDCORIE : 1; /* DCO external resistor fault flag interrupt enable */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bFCNTLFIE : 1; /* Start fault counter interrupt enable LFXT */
- __IO uint32_t bFCNTHFIE : 1; /* Start fault counter interrupt enable HFXT */
- __IO uint32_t bFCNTHF2IE : 1; /* Start fault counter interrupt enable HFXT2 */
- __I uint32_t bRESERVED2 : 1; /* Reserved */
- __IO uint32_t bPLLOOLIE : 1; /* PLL out-of-lock interrupt enable */
- __IO uint32_t bPLLLOSIE : 1; /* PLL loss-of-signal interrupt enable */
- __IO uint32_t bPLLOORIE : 1; /* PLL out-of-range interrupt enable */
- __IO uint32_t bCALIE : 1; /* REFCNT period counter interrupt enable */
- __I uint32_t bRESERVED3 : 16; /* Reserved */
- } b;
- } rIE;
- uint8_t RESERVED2[4];
- union { /* CSIFG Register */
- __I uint32_t r;
- struct { /* CSIFG Bits */
- __I uint32_t bLFXTIFG : 1; /* LFXT oscillator fault flag */
- __I uint32_t bHFXTIFG : 1; /* HFXT oscillator fault flag */
- __I uint32_t bHFXT2IFG : 1; /* HFXT2 oscillator fault flag */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __I uint32_t bDCOMINIFG : 1; /* DCO minimum fault flag */
- __I uint32_t bDCOMAXIFG : 1; /* DCO maximum fault flag */
- __I uint32_t bDCORIFG : 1; /* DCO external resistor fault flag */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __I uint32_t bFCNTLFIFG : 1; /* Start fault counter interrupt flag LFXT */
- __I uint32_t bFCNTHFIFG : 1; /* Start fault counter interrupt flag HFXT */
- __I uint32_t bRESERVED2 : 1; /* Reserved */
- __I uint32_t bFCNTHF2IFG : 1; /* Start fault counter interrupt flag HFXT2 */
- __I uint32_t bPLLOOLIFG : 1; /* PLL out-of-lock interrupt flag */
- __I uint32_t bPLLLOSIFG : 1; /* PLL loss-of-signal interrupt flag */
- __I uint32_t bPLLOORIFG : 1; /* PLL out-of-range interrupt flag */
- __I uint32_t bCALIFG : 1; /* REFCNT period counter expired */
- __I uint32_t bRESERVED3 : 16; /* Reserved */
- } b;
- } rIFG;
- uint8_t RESERVED3[4];
- union { /* CSCLRIFG Register */
- __IO uint32_t r;
- struct { /* CSCLRIFG Bits */
- __O uint32_t bCLR_LFXTIFG : 1; /* Clear LFXT oscillator fault interrupt flag */
- __O uint32_t bCLR_HFXTIFG : 1; /* Clear HFXT oscillator fault interrupt flag */
- __O uint32_t bCLR_HFXT2IFG : 1; /* Clear HFXT2 oscillator fault interrupt flag */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __O uint32_t bCLR_DCOMINIFG : 1; /* Clear DCO minimum fault interrupt flag */
- __O uint32_t bCLR_DCOMAXIFG : 1; /* Clear DCO maximum fault interrupt flag */
- __O uint32_t bCLR_DCORIFG : 1; /* Clear DCO external resistor fault interrupt flag */
- __O uint32_t bCLR_CALIFG : 1; /* REFCNT period counter clear interrupt flag */
- __O uint32_t bCLR_FCNTLFIFG : 1; /* Start fault counter clear interrupt flag LFXT */
- __O uint32_t bCLR_FCNTHFIFG : 1; /* Start fault counter clear interrupt flag HFXT */
- __O uint32_t bCLR_FCNTHF2IFG : 1; /* Start fault counter clear interrupt flag HFXT2 */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __O uint32_t bCLR_PLLOOLIFG : 1; /* PLL out-of-lock clear interrupt flag */
- __O uint32_t bCLR_PLLLOSIFG : 1; /* PLL loss-of-signal clear interrupt flag */
- __O uint32_t bCLR_PLLOORIFG : 1; /* PLL out-of-range clear interrupt flag */
- __I uint32_t bRESERVED2 : 17; /* Reserved */
- } b;
- } rCLRIFG;
- uint8_t RESERVED4[4];
- union { /* CSSETIFG Register */
- __IO uint32_t r;
- struct { /* CSSETIFG Bits */
- __O uint32_t bSET_LFXTIFG : 1; /* Set LFXT oscillator fault interrupt flag */
- __O uint32_t bSET_HFXTIFG : 1; /* Set HFXT oscillator fault interrupt flag */
- __O uint32_t bSET_HFXT2IFG : 1; /* Set HFXT2 oscillator fault interrupt flag */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __O uint32_t bSET_DCOMINIFG : 1; /* Set DCO minimum fault interrupt flag */
- __O uint32_t bSET_DCOMAXIFG : 1; /* Set DCO maximum fault interrupt flag */
- __O uint32_t bSET_DCORIFG : 1; /* Set DCO external resistor fault interrupt flag */
- __O uint32_t bSET_CALIFG : 1; /* REFCNT period counter set interrupt flag */
- __O uint32_t bSET_FCNTLFIFG : 1; /* Start fault counter set interrupt flag LFXT */
- __O uint32_t bSET_FCNTHFIFG : 1; /* Start fault counter set interrupt flag HFXT */
- __O uint32_t bSET_FCNTHF2IFG : 1; /* Start fault counter set interrupt flag HFXT2 */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __O uint32_t bSET_PLLOOLIFG : 1; /* PLL out-of-lock set interrupt flag */
- __O uint32_t bSET_PLLLOSIFG : 1; /* PLL loss-of-signal set interrupt flag */
- __O uint32_t bSET_PLLOORIFG : 1; /* PLL out-of-range set interrupt flag */
- __I uint32_t bRESERVED2 : 17; /* Reserved */
- } b;
- } rSETIFG;
- uint8_t RESERVED5[4];
- union { /* CSDCOERCAL Register */
- __IO uint32_t r;
- struct { /* CSDCOERCAL Bits */
- __IO uint32_t bDCO_TCTRIM : 2; /* DCO Temperature compensation Trim */
- __I uint32_t bRESERVED0 : 14; /* Reserved */
- __IO uint32_t bDCO_FTRIM : 11; /* DCO frequency trim */
- __I uint32_t bRESERVED1 : 5; /* Reserved */
- } b;
- } rDCOERCAL;
+ __IO uint32_t KEY; /**< Key Register */
+ __IO uint32_t CTL0; /**< Control 0 Register */
+ __IO uint32_t CTL1; /**< Control 1 Register */
+ __IO uint32_t CTL2; /**< Control 2 Register */
+ __IO uint32_t CTL3; /**< Control 3 Register */
+ __IO uint32_t CTL4; /**< Control 4 Register */
+ __IO uint32_t CTL5; /**< Control 5 Register */
+ __IO uint32_t CTL6; /**< Control 6 Register */
+ __IO uint32_t CTL7; /**< Control 7 Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t CLKEN; /**< Clock Enable Register */
+ __I uint32_t STAT; /**< Status Register */
+ uint32_t RESERVED1[2];
+ __IO uint32_t IE; /**< Interrupt Enable Register */
+ uint32_t RESERVED2;
+ __I uint32_t IFG; /**< Interrupt Flag Register */
+ uint32_t RESERVED3;
+ __O uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
+ uint32_t RESERVED4;
+ __O uint32_t SETIFG; /**< Set Interrupt Flag Register */
+ uint32_t RESERVED5;
+ __IO uint32_t DCOERCAL0; /**< DCO External Resistor Cailbration 0 Register */
+ __IO uint32_t DCOERCAL1; /**< DCO External Resistor Calibration 1 Register */
} CS_Type;
+/*@}*/ /* end of group CS */
-//*****************************************************************************
-// DIO Registers
-//*****************************************************************************
+/******************************************************************************
+* DIO Registers
+******************************************************************************/
+/** @addtogroup DIO MSP432P401R (DIO)
+ @{
+*/
typedef struct {
- union { /* PAIN Register */
- __I uint16_t r;
- struct { /* PAIN Bits */
- __I uint16_t bP1IN : 8; /* Port 1 Input */
- __I uint16_t bP2IN : 8; /* Port 2 Input */
- } b;
- } rPAIN;
- union { /* PAOUT Register */
- __IO uint16_t r;
- struct { /* PAOUT Bits */
- __IO uint16_t bP1OUT : 8; /* Port 1 Output */
- __IO uint16_t bP2OUT : 8; /* Port 2 Output */
- } b;
- } rPAOUT;
- union { /* PADIR Register */
- __IO uint16_t r;
- struct { /* PADIR Bits */
- __IO uint16_t bP1DIR : 8; /* Port 1 Direction */
- __IO uint16_t bP2DIR : 8; /* Port 2 Direction */
- } b;
- } rPADIR;
- union { /* PAREN Register */
- __IO uint16_t r;
- struct { /* PAREN Bits */
- __IO uint16_t bP1REN : 8; /* Port 1 Resistor Enable */
- __IO uint16_t bP2REN : 8; /* Port 2 Resistor Enable */
- } b;
- } rPAREN;
- union { /* PADS Register */
- __IO uint16_t r;
- struct { /* PADS Bits */
- __IO uint16_t bP1DS : 8; /* Port 1 Drive Strength */
- __IO uint16_t bP2DS : 8; /* Port 2 Drive Strength */
- } b;
- } rPADS;
- union { /* PASEL0 Register */
- __IO uint16_t r;
- struct { /* PASEL0 Bits */
- __IO uint16_t bP1SEL0 : 8; /* Port 1 Select 0 */
- __IO uint16_t bP2SEL0 : 8; /* Port 2 Select 0 */
- } b;
- } rPASEL0;
- union { /* PASEL1 Register */
- __IO uint16_t r;
- struct { /* PASEL1 Bits */
- __IO uint16_t bP1SEL1 : 8; /* Port 1 Select 1 */
- __IO uint16_t bP2SEL1 : 8; /* Port 2 Select 1 */
- } b;
- } rPASEL1;
- union { /* P1IV Register */
- __I uint16_t r;
- struct { /* P1IV Bits */
- __I uint16_t bP1IV : 5; /* Port 1 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP1IV;
- uint8_t RESERVED0[6];
- union { /* PASELC Register */
- __IO uint16_t r;
- struct { /* PASELC Bits */
- __IO uint16_t bP1SELC : 8; /* Port 1 Complement Select */
- __IO uint16_t bP2SELC : 8; /* Port 2 Complement Select */
- } b;
- } rPASELC;
- union { /* PAIES Register */
- __IO uint16_t r;
- struct { /* PAIES Bits */
- __IO uint16_t bP1IES : 8; /* Port 1 Interrupt Edge Select */
- __IO uint16_t bP2IES : 8; /* Port 2 Interrupt Edge Select */
- } b;
- } rPAIES;
- union { /* PAIE Register */
- __IO uint16_t r;
- struct { /* PAIE Bits */
- __IO uint16_t bP1IE : 8; /* Port 1 Interrupt Enable */
- __IO uint16_t bP2IE : 8; /* Port 2 Interrupt Enable */
- } b;
- } rPAIE;
- union { /* PAIFG Register */
- __IO uint16_t r;
- struct { /* PAIFG Bits */
- __IO uint16_t bP1IFG : 8; /* Port 1 Interrupt Flag */
- __IO uint16_t bP2IFG : 8; /* Port 2 Interrupt Flag */
- } b;
- } rPAIFG;
- union { /* P2IV Register */
- __I uint16_t r;
- struct { /* P2IV Bits */
- __I uint16_t bP2IV : 5; /* Port 2 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP2IV;
- union { /* PBIN Register */
- __I uint16_t r;
- struct { /* PBIN Bits */
- __I uint16_t bP3IN : 8; /* Port 3 Input */
- __I uint16_t bP4IN : 8; /* Port 4 Input */
- } b;
- } rPBIN;
- union { /* PBOUT Register */
- __IO uint16_t r;
- struct { /* PBOUT Bits */
- __IO uint16_t bP3OUT : 8; /* Port 3 Output */
- __IO uint16_t bP4OUT : 8; /* Port 4 Output */
- } b;
- } rPBOUT;
- union { /* PBDIR Register */
- __IO uint16_t r;
- struct { /* PBDIR Bits */
- __IO uint16_t bP3DIR : 8; /* Port 3 Direction */
- __IO uint16_t bP4DIR : 8; /* Port 4 Direction */
- } b;
- } rPBDIR;
- union { /* PBREN Register */
- __IO uint16_t r;
- struct { /* PBREN Bits */
- __IO uint16_t bP3REN : 8; /* Port 3 Resistor Enable */
- __IO uint16_t bP4REN : 8; /* Port 4 Resistor Enable */
- } b;
- } rPBREN;
- union { /* PBDS Register */
- __IO uint16_t r;
- struct { /* PBDS Bits */
- __IO uint16_t bP3DS : 8; /* Port 3 Drive Strength */
- __IO uint16_t bP4DS : 8; /* Port 4 Drive Strength */
- } b;
- } rPBDS;
- union { /* PBSEL0 Register */
- __IO uint16_t r;
- struct { /* PBSEL0 Bits */
- __IO uint16_t bP3SEL0 : 8; /* Port 3 Select 0 */
- __IO uint16_t bP4SEL0 : 8; /* Port 4 Select 0 */
- } b;
- } rPBSEL0;
- union { /* PBSEL1 Register */
- __IO uint16_t r;
- struct { /* PBSEL1 Bits */
- __IO uint16_t bP3SEL1 : 8; /* Port 3 Select 1 */
- __IO uint16_t bP4SEL1 : 8; /* Port 4 Select 1 */
- } b;
- } rPBSEL1;
- union { /* P3IV Register */
- __I uint16_t r;
- struct { /* P3IV Bits */
- __I uint16_t bP3IV : 5; /* Port 3 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP3IV;
- uint8_t RESERVED1[6];
- union { /* PBSELC Register */
- __IO uint16_t r;
- struct { /* PBSELC Bits */
- __IO uint16_t bP3SELC : 8; /* Port 3 Complement Select */
- __IO uint16_t bP4SELC : 8; /* Port 4 Complement Select */
- } b;
- } rPBSELC;
- union { /* PBIES Register */
- __IO uint16_t r;
- struct { /* PBIES Bits */
- __IO uint16_t bP3IES : 8; /* Port 3 Interrupt Edge Select */
- __IO uint16_t bP4IES : 8; /* Port 4 Interrupt Edge Select */
- } b;
- } rPBIES;
- union { /* PBIE Register */
- __IO uint16_t r;
- struct { /* PBIE Bits */
- __IO uint16_t bP3IE : 8; /* Port 3 Interrupt Enable */
- __IO uint16_t bP4IE : 8; /* Port 4 Interrupt Enable */
- } b;
- } rPBIE;
- union { /* PBIFG Register */
- __IO uint16_t r;
- struct { /* PBIFG Bits */
- __IO uint16_t bP3IFG : 8; /* Port 3 Interrupt Flag */
- __IO uint16_t bP4IFG : 8; /* Port 4 Interrupt Flag */
- } b;
- } rPBIFG;
- union { /* P4IV Register */
- __I uint16_t r;
- struct { /* P4IV Bits */
- __I uint16_t bP4IV : 5; /* Port 4 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP4IV;
- union { /* PCIN Register */
- __I uint16_t r;
- struct { /* PCIN Bits */
- __I uint16_t bP5IN : 8; /* Port 5 Input */
- __I uint16_t bP6IN : 8; /* Port 6 Input */
- } b;
- } rPCIN;
- union { /* PCOUT Register */
- __IO uint16_t r;
- struct { /* PCOUT Bits */
- __IO uint16_t bP5OUT : 8; /* Port 5 Output */
- __IO uint16_t bP6OUT : 8; /* Port 6 Output */
- } b;
- } rPCOUT;
- union { /* PCDIR Register */
- __IO uint16_t r;
- struct { /* PCDIR Bits */
- __IO uint16_t bP5DIR : 8; /* Port 5 Direction */
- __IO uint16_t bP6DIR : 8; /* Port 6 Direction */
- } b;
- } rPCDIR;
- union { /* PCREN Register */
- __IO uint16_t r;
- struct { /* PCREN Bits */
- __IO uint16_t bP5REN : 8; /* Port 5 Resistor Enable */
- __IO uint16_t bP6REN : 8; /* Port 6 Resistor Enable */
- } b;
- } rPCREN;
- union { /* PCDS Register */
- __IO uint16_t r;
- struct { /* PCDS Bits */
- __IO uint16_t bP5DS : 8; /* Port 5 Drive Strength */
- __IO uint16_t bP6DS : 8; /* Port 6 Drive Strength */
- } b;
- } rPCDS;
- union { /* PCSEL0 Register */
- __IO uint16_t r;
- struct { /* PCSEL0 Bits */
- __IO uint16_t bP5SEL0 : 8; /* Port 5 Select 0 */
- __IO uint16_t bP6SEL0 : 8; /* Port 6 Select 0 */
- } b;
- } rPCSEL0;
- union { /* PCSEL1 Register */
- __IO uint16_t r;
- struct { /* PCSEL1 Bits */
- __IO uint16_t bP5SEL1 : 8; /* Port 5 Select 1 */
- __IO uint16_t bP6SEL1 : 8; /* Port 6 Select 1 */
- } b;
- } rPCSEL1;
- union { /* P5IV Register */
- __I uint16_t r;
- struct { /* P5IV Bits */
- __I uint16_t bP5IV : 5; /* Port 5 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP5IV;
- uint8_t RESERVED2[6];
- union { /* PCSELC Register */
- __IO uint16_t r;
- struct { /* PCSELC Bits */
- __IO uint16_t bP5SELC : 8; /* Port 5 Complement Select */
- __IO uint16_t bP6SELC : 8; /* Port 6 Complement Select */
- } b;
- } rPCSELC;
- union { /* PCIES Register */
- __IO uint16_t r;
- struct { /* PCIES Bits */
- __IO uint16_t bP5IES : 8; /* Port 5 Interrupt Edge Select */
- __IO uint16_t bP6IES : 8; /* Port 6 Interrupt Edge Select */
- } b;
- } rPCIES;
- union { /* PCIE Register */
- __IO uint16_t r;
- struct { /* PCIE Bits */
- __IO uint16_t bP5IE : 8; /* Port 5 Interrupt Enable */
- __IO uint16_t bP6IE : 8; /* Port 6 Interrupt Enable */
- } b;
- } rPCIE;
- union { /* PCIFG Register */
- __IO uint16_t r;
- struct { /* PCIFG Bits */
- __IO uint16_t bP5IFG : 8; /* Port 5 Interrupt Flag */
- __IO uint16_t bP6IFG : 8; /* Port 6 Interrupt Flag */
- } b;
- } rPCIFG;
- union { /* P6IV Register */
- __I uint16_t r;
- struct { /* P6IV Bits */
- __I uint16_t bP6IV : 5; /* Port 6 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP6IV;
- union { /* PDIN Register */
- __I uint16_t r;
- struct { /* PDIN Bits */
- __I uint16_t bP7IN : 8; /* Port 7 Input */
- __I uint16_t bP8IN : 8; /* Port 8 Input */
- } b;
- } rPDIN;
- union { /* PDOUT Register */
- __IO uint16_t r;
- struct { /* PDOUT Bits */
- __IO uint16_t bP7OUT : 8; /* Port 7 Output */
- __IO uint16_t bP8OUT : 8; /* Port 8 Output */
- } b;
- } rPDOUT;
- union { /* PDDIR Register */
- __IO uint16_t r;
- struct { /* PDDIR Bits */
- __IO uint16_t bP7DIR : 8; /* Port 7 Direction */
- __IO uint16_t bP8DIR : 8; /* Port 8 Direction */
- } b;
- } rPDDIR;
- union { /* PDREN Register */
- __IO uint16_t r;
- struct { /* PDREN Bits */
- __IO uint16_t bP7REN : 8; /* Port 7 Resistor Enable */
- __IO uint16_t bP8REN : 8; /* Port 8 Resistor Enable */
- } b;
- } rPDREN;
- union { /* PDDS Register */
- __IO uint16_t r;
- struct { /* PDDS Bits */
- __IO uint16_t bP7DS : 8; /* Port 7 Drive Strength */
- __IO uint16_t bP8DS : 8; /* Port 8 Drive Strength */
- } b;
- } rPDDS;
- union { /* PDSEL0 Register */
- __IO uint16_t r;
- struct { /* PDSEL0 Bits */
- __IO uint16_t bP7SEL0 : 8; /* Port 7 Select 0 */
- __IO uint16_t bP8SEL0 : 8; /* Port 8 Select 0 */
- } b;
- } rPDSEL0;
- union { /* PDSEL1 Register */
- __IO uint16_t r;
- struct { /* PDSEL1 Bits */
- __IO uint16_t bP7SEL1 : 8; /* Port 7 Select 1 */
- __IO uint16_t bP8SEL1 : 8; /* Port 8 Select 1 */
- } b;
- } rPDSEL1;
- union { /* P7IV Register */
- __I uint16_t r;
- struct { /* P7IV Bits */
- __I uint16_t bP7IV : 5; /* Port 7 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP7IV;
- uint8_t RESERVED3[6];
- union { /* PDSELC Register */
- __IO uint16_t r;
- struct { /* PDSELC Bits */
- __IO uint16_t bP7SELC : 8; /* Port 7 Complement Select */
- __IO uint16_t bP8SELC : 8; /* Port 8 Complement Select */
- } b;
- } rPDSELC;
- union { /* PDIES Register */
- __IO uint16_t r;
- struct { /* PDIES Bits */
- __IO uint16_t bP7IES : 8; /* Port 7 Interrupt Edge Select */
- __IO uint16_t bP8IES : 8; /* Port 8 Interrupt Edge Select */
- } b;
- } rPDIES;
- union { /* PDIE Register */
- __IO uint16_t r;
- struct { /* PDIE Bits */
- __IO uint16_t bP7IE : 8; /* Port 7 Interrupt Enable */
- __IO uint16_t bP8IE : 8; /* Port 8 Interrupt Enable */
- } b;
- } rPDIE;
- union { /* PDIFG Register */
- __IO uint16_t r;
- struct { /* PDIFG Bits */
- __IO uint16_t bP7IFG : 8; /* Port 7 Interrupt Flag */
- __IO uint16_t bP8IFG : 8; /* Port 8 Interrupt Flag */
- } b;
- } rPDIFG;
- union { /* P8IV Register */
- __I uint16_t r;
- struct { /* P8IV Bits */
- __I uint16_t bP8IV : 5; /* Port 8 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP8IV;
- union { /* PEIN Register */
- __I uint16_t r;
- struct { /* PEIN Bits */
- __I uint16_t bP9IN : 8; /* Port 9 Input */
- __I uint16_t bP10IN : 8; /* Port 10 Input */
- } b;
- } rPEIN;
- union { /* PEOUT Register */
- __IO uint16_t r;
- struct { /* PEOUT Bits */
- __IO uint16_t bP9OUT : 8; /* Port 9 Output */
- __IO uint16_t bP10OUT : 8; /* Port 10 Output */
- } b;
- } rPEOUT;
- union { /* PEDIR Register */
- __IO uint16_t r;
- struct { /* PEDIR Bits */
- __IO uint16_t bP9DIR : 8; /* Port 9 Direction */
- __IO uint16_t bP10DIR : 8; /* Port 10 Direction */
- } b;
- } rPEDIR;
- union { /* PEREN Register */
- __IO uint16_t r;
- struct { /* PEREN Bits */
- __IO uint16_t bP9REN : 8; /* Port 9 Resistor Enable */
- __IO uint16_t bP10REN : 8; /* Port 10 Resistor Enable */
- } b;
- } rPEREN;
- union { /* PEDS Register */
- __IO uint16_t r;
- struct { /* PEDS Bits */
- __IO uint16_t bP9DS : 8; /* Port 9 Drive Strength */
- __IO uint16_t bP10DS : 8; /* Port 10 Drive Strength */
- } b;
- } rPEDS;
- union { /* PESEL0 Register */
- __IO uint16_t r;
- struct { /* PESEL0 Bits */
- __IO uint16_t bP9SEL0 : 8; /* Port 9 Select 0 */
- __IO uint16_t bP10SEL0 : 8; /* Port 10 Select 0 */
- } b;
- } rPESEL0;
- union { /* PESEL1 Register */
- __IO uint16_t r;
- struct { /* PESEL1 Bits */
- __IO uint16_t bP9SEL1 : 8; /* Port 9 Select 1 */
- __IO uint16_t bP10SEL1 : 8; /* Port 10 Select 1 */
- } b;
- } rPESEL1;
- union { /* P9IV Register */
- __I uint16_t r;
- struct { /* P9IV Bits */
- __I uint16_t bP9IV : 5; /* Port 9 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP9IV;
- uint8_t RESERVED4[6];
- union { /* PESELC Register */
- __IO uint16_t r;
- struct { /* PESELC Bits */
- __IO uint16_t bP9SELC : 8; /* Port 9 Complement Select */
- __IO uint16_t bP10SELC : 8; /* Port 10 Complement Select */
- } b;
- } rPESELC;
- union { /* PEIES Register */
- __IO uint16_t r;
- struct { /* PEIES Bits */
- __IO uint16_t bP9IES : 8; /* Port 9 Interrupt Edge Select */
- __IO uint16_t bP10IES : 8; /* Port 10 Interrupt Edge Select */
- } b;
- } rPEIES;
- union { /* PEIE Register */
- __IO uint16_t r;
- struct { /* PEIE Bits */
- __IO uint16_t bP9IE : 8; /* Port 9 Interrupt Enable */
- __IO uint16_t bP10IE : 8; /* Port 10 Interrupt Enable */
- } b;
- } rPEIE;
- union { /* PEIFG Register */
- __IO uint16_t r;
- struct { /* PEIFG Bits */
- __IO uint16_t bP9IFG : 8; /* Port 9 Interrupt Flag */
- __IO uint16_t bP10IFG : 8; /* Port 10 Interrupt Flag */
- } b;
- } rPEIFG;
- union { /* P10IV Register */
- __I uint16_t r;
- struct { /* P10IV Bits */
- __I uint16_t bP10IV : 5; /* Port 10 interrupt vector value */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rP10IV;
- uint8_t RESERVED5[128];
- __I uint16_t rPJIN; /* Port J Input */
- __IO uint16_t rPJOUT; /* Port J Output */
- __IO uint16_t rPJDIR; /* Port J Direction */
- __IO uint16_t rPJREN; /* Port J Resistor Enable */
- __IO uint16_t rPJDS; /* Port J Drive Strength */
- __IO uint16_t rPJSEL0; /* Port J Select 0 */
- __IO uint16_t rPJSEL1; /* Port J Select 1 */
- uint8_t RESERVED6[8];
- __IO uint16_t rPJSELC; /* Port J Complement Select */
-} DIO_Type;
+ union {
+ __I uint16_t IN; /**< Port Pair Input */
+ struct {
+ __I uint8_t IN_L; /**< Low Port Input */
+ __I uint8_t IN_H; /**< High Port Input */
+ };
+ };
+ union {
+ __IO uint16_t OUT; /**< Port Pair Output */
+ struct {
+ __IO uint8_t OUT_L; /**< Low Port Output */
+ __IO uint8_t OUT_H; /**< High Port Output */
+ };
+ };
+ union {
+ __IO uint16_t DIR; /**< Port Pair Direction */
+ struct {
+ __IO uint8_t DIR_L; /**< Low Port Direction */
+ __IO uint8_t DIR_H; /**< High Port Direction */
+ };
+ };
+ union {
+ __IO uint16_t REN; /**< Port Pair Resistor Enable */
+ struct {
+ __IO uint8_t REN_L; /**< Low Port Resistor Enable */
+ __IO uint8_t REN_H; /**< High Port Resistor Enable */
+ };
+ };
+ union {
+ __IO uint16_t DS; /**< Port Pair Drive Strength */
+ struct {
+ __IO uint8_t DS_L; /**< Low Port Drive Strength */
+ __IO uint8_t DS_H; /**< High Port Drive Strength */
+ };
+ };
+ union {
+ __IO uint16_t SEL0; /**< Port Pair Select 0 */
+ struct {
+ __IO uint8_t SEL0_L; /**< Low Port Select 0 */
+ __IO uint8_t SEL0_H; /**< High Port Select 0 */
+ };
+ };
+ union {
+ __IO uint16_t SEL1; /**< Port Pair Select 1 */
+ struct {
+ __IO uint8_t SEL1_L; /**< Low Port Select 1 */
+ __IO uint8_t SEL1_H; /**< High Port Select 1 */
+ };
+ };
+ __I uint16_t IV_L; /**< Low Port Interrupt Vector Value */
+ uint16_t RESERVED0[3];
+ union {
+ __IO uint16_t SELC; /**< Port Pair Complement Select */
+ struct {
+ __IO uint8_t SELC_L; /**< Low Port Complement Select */
+ __IO uint8_t SELC_H; /**< High Port Complement Select */
+ };
+ };
+ union {
+ __IO uint16_t IES; /**< Port Pair Interrupt Edge Select */
+ struct {
+ __IO uint8_t IES_L; /**< Low Port Interrupt Edge Select */
+ __IO uint8_t IES_H; /**< High Port Interrupt Edge Select */
+ };
+ };
+ union {
+ __IO uint16_t IE; /**< Port Pair Interrupt Enable */
+ struct {
+ __IO uint8_t IE_L; /**< Low Port Interrupt Enable */
+ __IO uint8_t IE_H; /**< High Port Interrupt Enable */
+ };
+ };
+ union {
+ __IO uint16_t IFG; /**< Port Pair Interrupt Flag */
+ struct {
+ __IO uint8_t IFG_L; /**< Low Port Interrupt Flag */
+ __IO uint8_t IFG_H; /**< High Port Interrupt Flag */
+ };
+ };
+ __I uint16_t IV_H; /**< High Port Interrupt Vector Value */
+} DIO_PORT_Interruptable_Type;
-
-//*****************************************************************************
-// DMA Registers
-//*****************************************************************************
typedef struct {
- union { /* DMA_DEVICE_CFG Register */
- __I uint32_t r;
- struct { /* DMA_DEVICE_CFG Bits */
- __I uint32_t bNUM_DMA_CHANNELS : 8; /* Number of DMA channels available */
- __I uint32_t bNUM_SRC_PER_CHANNEL : 8; /* Number of DMA sources per channel */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rDEVICE_CFG;
- union { /* DMA_SW_CHTRIG Register */
- __IO uint32_t r;
- struct { /* DMA_SW_CHTRIG Bits */
- __IO uint32_t bCH0 : 1; /* Write 1, triggers DMA_CHANNEL0 */
- __IO uint32_t bCH1 : 1; /* Write 1, triggers DMA_CHANNEL1 */
- __IO uint32_t bCH2 : 1; /* Write 1, triggers DMA_CHANNEL2 */
- __IO uint32_t bCH3 : 1; /* Write 1, triggers DMA_CHANNEL3 */
- __IO uint32_t bCH4 : 1; /* Write 1, triggers DMA_CHANNEL4 */
- __IO uint32_t bCH5 : 1; /* Write 1, triggers DMA_CHANNEL5 */
- __IO uint32_t bCH6 : 1; /* Write 1, triggers DMA_CHANNEL6 */
- __IO uint32_t bCH7 : 1; /* Write 1, triggers DMA_CHANNEL7 */
- __IO uint32_t bCH8 : 1; /* Write 1, triggers DMA_CHANNEL8 */
- __IO uint32_t bCH9 : 1; /* Write 1, triggers DMA_CHANNEL9 */
- __IO uint32_t bCH10 : 1; /* Write 1, triggers DMA_CHANNEL10 */
- __IO uint32_t bCH11 : 1; /* Write 1, triggers DMA_CHANNEL11 */
- __IO uint32_t bCH12 : 1; /* Write 1, triggers DMA_CHANNEL12 */
- __IO uint32_t bCH13 : 1; /* Write 1, triggers DMA_CHANNEL13 */
- __IO uint32_t bCH14 : 1; /* Write 1, triggers DMA_CHANNEL14 */
- __IO uint32_t bCH15 : 1; /* Write 1, triggers DMA_CHANNEL15 */
- __IO uint32_t bCH16 : 1; /* Write 1, triggers DMA_CHANNEL16 */
- __IO uint32_t bCH17 : 1; /* Write 1, triggers DMA_CHANNEL17 */
- __IO uint32_t bCH18 : 1; /* Write 1, triggers DMA_CHANNEL18 */
- __IO uint32_t bCH19 : 1; /* Write 1, triggers DMA_CHANNEL19 */
- __IO uint32_t bCH20 : 1; /* Write 1, triggers DMA_CHANNEL20 */
- __IO uint32_t bCH21 : 1; /* Write 1, triggers DMA_CHANNEL21 */
- __IO uint32_t bCH22 : 1; /* Write 1, triggers DMA_CHANNEL22 */
- __IO uint32_t bCH23 : 1; /* Write 1, triggers DMA_CHANNEL23 */
- __IO uint32_t bCH24 : 1; /* Write 1, triggers DMA_CHANNEL24 */
- __IO uint32_t bCH25 : 1; /* Write 1, triggers DMA_CHANNEL25 */
- __IO uint32_t bCH26 : 1; /* Write 1, triggers DMA_CHANNEL26 */
- __IO uint32_t bCH27 : 1; /* Write 1, triggers DMA_CHANNEL27 */
- __IO uint32_t bCH28 : 1; /* Write 1, triggers DMA_CHANNEL28 */
- __IO uint32_t bCH29 : 1; /* Write 1, triggers DMA_CHANNEL29 */
- __IO uint32_t bCH30 : 1; /* Write 1, triggers DMA_CHANNEL30 */
- __IO uint32_t bCH31 : 1; /* Write 1, triggers DMA_CHANNEL31 */
- } b;
- } rSW_CHTRIG;
- uint8_t RESERVED0[8];
- union { /* DMA_CH0_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH0_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH0_SRCCFG;
- union { /* DMA_CH1_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH1_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH1_SRCCFG;
- union { /* DMA_CH2_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH2_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH2_SRCCFG;
- union { /* DMA_CH3_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH3_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH3_SRCCFG;
- union { /* DMA_CH4_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH4_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH4_SRCCFG;
- union { /* DMA_CH5_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH5_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH5_SRCCFG;
- union { /* DMA_CH6_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH6_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH6_SRCCFG;
- union { /* DMA_CH7_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH7_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH7_SRCCFG;
- union { /* DMA_CH8_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH8_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH8_SRCCFG;
- union { /* DMA_CH9_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH9_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH9_SRCCFG;
- union { /* DMA_CH10_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH10_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH10_SRCCFG;
- union { /* DMA_CH11_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH11_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH11_SRCCFG;
- union { /* DMA_CH12_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH12_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH12_SRCCFG;
- union { /* DMA_CH13_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH13_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH13_SRCCFG;
- union { /* DMA_CH14_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH14_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH14_SRCCFG;
- union { /* DMA_CH15_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH15_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH15_SRCCFG;
- union { /* DMA_CH16_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH16_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH16_SRCCFG;
- union { /* DMA_CH17_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH17_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH17_SRCCFG;
- union { /* DMA_CH18_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH18_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH18_SRCCFG;
- union { /* DMA_CH19_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH19_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH19_SRCCFG;
- union { /* DMA_CH20_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH20_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH20_SRCCFG;
- union { /* DMA_CH21_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH21_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH21_SRCCFG;
- union { /* DMA_CH22_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH22_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH22_SRCCFG;
- union { /* DMA_CH23_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH23_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH23_SRCCFG;
- union { /* DMA_CH24_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH24_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH24_SRCCFG;
- union { /* DMA_CH25_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH25_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH25_SRCCFG;
- union { /* DMA_CH26_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH26_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH26_SRCCFG;
- union { /* DMA_CH27_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH27_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH27_SRCCFG;
- union { /* DMA_CH28_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH28_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH28_SRCCFG;
- union { /* DMA_CH29_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH29_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH29_SRCCFG;
- union { /* DMA_CH30_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH30_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH30_SRCCFG;
- union { /* DMA_CH31_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_CH31_SRCCFG Bits */
- __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rCH31_SRCCFG;
- uint8_t RESERVED1[112];
- union { /* DMA_INT1_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_INT1_SRCCFG Bits */
- __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */
- __IO uint32_t bEN : 1; /* Enables DMA_INT1 mapping */
- __I uint32_t bRESERVED0 : 26; /* Reserved */
- } b;
- } rINT1_SRCCFG;
- union { /* DMA_INT2_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_INT2_SRCCFG Bits */
- __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */
- __IO uint32_t bEN : 1; /* Enables DMA_INT2 mapping */
- __I uint32_t bRESERVED0 : 26; /* Reserved */
- } b;
- } rINT2_SRCCFG;
- union { /* DMA_INT3_SRCCFG Register */
- __IO uint32_t r;
- struct { /* DMA_INT3_SRCCFG Bits */
- __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */
- __IO uint32_t bEN : 1; /* Enables DMA_INT3 mapping */
- __I uint32_t bRESERVED0 : 26; /* Reserved */
- } b;
- } rINT3_SRCCFG;
- uint8_t RESERVED2[4];
- union { /* DMA_INT0_SRCFLG Register */
- __I uint32_t r;
- struct { /* DMA_INT0_SRCFLG Bits */
- __I uint32_t bCH0 : 1; /* Channel 0 was the source of DMA_INT0 */
- __I uint32_t bCH1 : 1; /* Channel 1 was the source of DMA_INT0 */
- __I uint32_t bCH2 : 1; /* Channel 2 was the source of DMA_INT0 */
- __I uint32_t bCH3 : 1; /* Channel 3 was the source of DMA_INT0 */
- __I uint32_t bCH4 : 1; /* Channel 4 was the source of DMA_INT0 */
- __I uint32_t bCH5 : 1; /* Channel 5 was the source of DMA_INT0 */
- __I uint32_t bCH6 : 1; /* Channel 6 was the source of DMA_INT0 */
- __I uint32_t bCH7 : 1; /* Channel 7 was the source of DMA_INT0 */
- __I uint32_t bCH8 : 1; /* Channel 8 was the source of DMA_INT0 */
- __I uint32_t bCH9 : 1; /* Channel 9 was the source of DMA_INT0 */
- __I uint32_t bCH10 : 1; /* Channel 10 was the source of DMA_INT0 */
- __I uint32_t bCH11 : 1; /* Channel 11 was the source of DMA_INT0 */
- __I uint32_t bCH12 : 1; /* Channel 12 was the source of DMA_INT0 */
- __I uint32_t bCH13 : 1; /* Channel 13 was the source of DMA_INT0 */
- __I uint32_t bCH14 : 1; /* Channel 14 was the source of DMA_INT0 */
- __I uint32_t bCH15 : 1; /* Channel 15 was the source of DMA_INT0 */
- __I uint32_t bCH16 : 1; /* Channel 16 was the source of DMA_INT0 */
- __I uint32_t bCH17 : 1; /* Channel 17 was the source of DMA_INT0 */
- __I uint32_t bCH18 : 1; /* Channel 18 was the source of DMA_INT0 */
- __I uint32_t bCH19 : 1; /* Channel 19 was the source of DMA_INT0 */
- __I uint32_t bCH20 : 1; /* Channel 20 was the source of DMA_INT0 */
- __I uint32_t bCH21 : 1; /* Channel 21 was the source of DMA_INT0 */
- __I uint32_t bCH22 : 1; /* Channel 22 was the source of DMA_INT0 */
- __I uint32_t bCH23 : 1; /* Channel 23 was the source of DMA_INT0 */
- __I uint32_t bCH24 : 1; /* Channel 24 was the source of DMA_INT0 */
- __I uint32_t bCH25 : 1; /* Channel 25 was the source of DMA_INT0 */
- __I uint32_t bCH26 : 1; /* Channel 26 was the source of DMA_INT0 */
- __I uint32_t bCH27 : 1; /* Channel 27 was the source of DMA_INT0 */
- __I uint32_t bCH28 : 1; /* Channel 28 was the source of DMA_INT0 */
- __I uint32_t bCH29 : 1; /* Channel 29 was the source of DMA_INT0 */
- __I uint32_t bCH30 : 1; /* Channel 30 was the source of DMA_INT0 */
- __I uint32_t bCH31 : 1; /* Channel 31 was the source of DMA_INT0 */
- } b;
- } rINT0_SRCFLG;
- union { /* DMA_INT0_CLRFLG Register */
- __O uint32_t r;
- struct { /* DMA_INT0_CLRFLG Bits */
- __O uint32_t bCH0 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH1 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH2 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH3 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH4 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH5 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH6 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH7 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH8 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH9 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH10 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH11 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH12 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH13 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH14 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH15 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH16 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH17 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH18 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH19 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH20 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH21 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH22 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH23 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH24 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH25 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH26 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH27 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH28 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH29 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH30 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- __O uint32_t bCH31 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
- } b;
- } rINT0_CLRFLG;
- uint8_t RESERVED3[3816];
- union { /* DMA_STAT Register */
- __I uint32_t r;
- struct { /* DMA_STAT Bits */
- __I uint32_t bMASTEN : 1; /* */
- __I uint32_t bRESERVED0 : 3; /* Reserved */
- __I uint32_t b : 4; /* */
- __I uint32_t bRESERVED1 : 8; /* Reserved */
- __I uint32_t bRESERVED2 : 7; /* Reserved */
- } b;
- } rSTAT;
- union { /* DMA_CFG Register */
- __O uint32_t r;
- struct { /* DMA_CFG Bits */
- __O uint32_t b : 1; /* */
- __O uint32_t bRESERVED0 : 4; /* Reserved */
- __O uint32_t bRESERVED1 : 24; /* Reserved */
- } b;
- } rCFG;
- union { /* DMA_CTLBASE Register */
- __IO uint32_t r;
- struct { /* DMA_CTLBASE Bits */
- __I uint32_t bRESERVED0 : 5; /* Reserved */
- __IO uint32_t b : 27; /* */
- } b;
- } rCTLBASE;
- __I uint32_t rATLBASE; /* Channel Alternate Control Data Base Pointer Register */
- __I uint32_t rWAITSTAT; /* Channel Wait on Request Status Register */
- __O uint32_t rSWREQ; /* Channel Software Request Register */
- __IO uint32_t rUSEBURSTSET; /* Channel Useburst Set Register */
- __O uint32_t rUSEBURSTCLR; /* Channel Useburst Clear Register */
- __IO uint32_t rREQMASKSET; /* Channel Request Mask Set Register */
- __O uint32_t rREQMASKCLR; /* Channel Request Mask Clear Register */
- __IO uint32_t rENASET; /* Channel Enable Set Register */
- __O uint32_t rENACLR; /* Channel Enable Clear Register */
- __IO uint32_t rALTSET; /* Channel Primary-Alternate Set Register */
- __O uint32_t rALTCLR; /* Channel Primary-Alternate Clear Register */
- __IO uint32_t rPRIOSET; /* Channel Priority Set Register */
- __O uint32_t rPRIOCLR; /* Channel Priority Clear Register */
- uint8_t RESERVED4[12];
- union { /* DMA_ERRCLR Register */
- __IO uint32_t r;
- struct { /* DMA_ERRCLR Bits */
- __IO uint32_t b : 1; /* */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rERRCLR;
-} DMA_Type;
+ union {
+ __I uint16_t IN; /**< Port Pair Input */
+ struct {
+ __I uint8_t IN_L; /**< Low Port Input */
+ __I uint8_t IN_H; /**< High Port Input */
+ };
+ };
+ union {
+ __IO uint16_t OUT; /**< Port Pair Output */
+ struct {
+ __IO uint8_t OUT_L; /**< Low Port Output */
+ __IO uint8_t OUT_H; /**< High Port Output */
+ };
+ };
+ union {
+ __IO uint16_t DIR; /**< Port Pair Direction */
+ struct {
+ __IO uint8_t DIR_L; /**< Low Port Direction */
+ __IO uint8_t DIR_H; /**< High Port Direction */
+ };
+ };
+ union {
+ __IO uint16_t REN; /**< Port Pair Resistor Enable */
+ struct {
+ __IO uint8_t REN_L; /**< Low Port Resistor Enable */
+ __IO uint8_t REN_H; /**< High Port Resistor Enable */
+ };
+ };
+ union {
+ __IO uint16_t DS; /**< Port Pair Drive Strength */
+ struct {
+ __IO uint8_t DS_L; /**< Low Port Drive Strength */
+ __IO uint8_t DS_H; /**< High Port Drive Strength */
+ };
+ };
+ union {
+ __IO uint16_t SEL0; /**< Port Pair Select 0 */
+ struct {
+ __IO uint8_t SEL0_L; /**< Low Port Select 0 */
+ __IO uint8_t SEL0_H; /**< High Port Select 0 */
+ };
+ };
+ union {
+ __IO uint16_t SEL1; /**< Port Pair Select 1 */
+ struct {
+ __IO uint8_t SEL1_L; /**< Low Port Select 1 */
+ __IO uint8_t SEL1_H; /**< High Port Select 1 */
+ };
+ };
+ uint16_t RESERVED0[4];
+ union {
+ __IO uint16_t SELC; /**< Port Pair Complement Select */
+ struct {
+ __IO uint8_t SELC_L; /**< Low Port Complement Select */
+ __IO uint8_t SELC_H; /**< High Port Complement Select */
+ };
+ };
+} DIO_PORT_Not_Interruptable_Type;
-//*****************************************************************************
-// EUSCI_A0 Registers
-//*****************************************************************************
typedef struct {
- union { /* UCA0CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCA0CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXBRK : 1; /* Transmit break */
- __IO uint16_t bTXADDR : 1; /* Transmit address */
- __IO uint16_t bDORM : 1; /* Dormant */
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */
- __IO uint16_t bSPB : 1; /* Stop bit select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bPAR : 1; /* Parity select */
- __IO uint16_t bPEN : 1; /* Parity enable */
- } b;
- struct { /* UCA0CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCA0CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCA0CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __I uint16_t bRESERVED0 : 14; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
- union { /* UCA0MCTLW Register */
- __IO uint16_t r;
- struct { /* UCA0MCTLW Bits */
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bBRF : 4; /* First modulation stage select */
- __IO uint16_t bBRS : 8; /* Second modulation stage select */
- } b;
- } rMCTLW;
- union { /* UCA0STATW Register */
- __IO uint16_t r;
- struct { /* UCA0STATW Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
- __IO uint16_t bRXERR : 1; /* Receive error flag */
- __IO uint16_t bBRK : 1; /* Break detect flag */
- __IO uint16_t bPE : 1; /* */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA0STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCA0RXBUF Register */
- __I uint16_t r;
- struct { /* UCA0RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA0RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCA0TXBUF Register */
- __IO uint16_t r;
- struct { /* UCA0TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA0TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- union { /* UCA0ABCTL Register */
- __IO uint16_t r;
- struct { /* UCA0ABCTL Bits */
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bBTOE : 1; /* Break time out error */
- __IO uint16_t bSTOE : 1; /* Synch field time out error */
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
- __I uint16_t bRESERVED1 : 10; /* Reserved */
- } b;
- } rABCTL;
- union { /* UCA0IRCTL Register */
- __IO uint16_t r;
- struct { /* UCA0IRCTL Bits */
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */
- } b;
- } rIRCTL;
- uint8_t RESERVED1[6];
- union { /* UCA0IE Register */
- __IO uint16_t r;
- struct { /* UCA0IE Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA0IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCA0IFG Register */
- __IO uint16_t r;
- struct { /* UCA0IFG Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA0IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
-} EUSCI_A0_Type;
+ __I uint8_t IN; /**< Port Input */
+ uint8_t RESERVED0;
+ __IO uint8_t OUT; /**< Port Output */
+ uint8_t RESERVED1;
+ __IO uint8_t DIR; /**< Port Direction */
+ uint8_t RESERVED2;
+ __IO uint8_t REN; /**< Port Resistor Enable */
+ uint8_t RESERVED3;
+ __IO uint8_t DS; /**< Port Drive Strength */
+ uint8_t RESERVED4;
+ __IO uint8_t SEL0; /**< Port Select 0 */
+ uint8_t RESERVED5;
+ __IO uint8_t SEL1; /**< Port Select 1 */
+ uint8_t RESERVED6;
+ __I uint16_t IV; /**< Port Interrupt Vector Value */
+ uint8_t RESERVED7[6];
+ __IO uint8_t SELC; /**< Port Complement Select */
+ uint8_t RESERVED8;
+ __IO uint8_t IES; /**< Port Interrupt Edge Select */
+ uint8_t RESERVED9;
+ __IO uint8_t IE; /**< Port Interrupt Enable */
+ uint8_t RESERVED10;
+ __IO uint8_t IFG; /**< Port Interrupt Flag */
+} DIO_PORT_Odd_Interruptable_Type;
-
-//*****************************************************************************
-// EUSCI_A1 Registers
-//*****************************************************************************
typedef struct {
- union { /* UCA1CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCA1CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXBRK : 1; /* Transmit break */
- __IO uint16_t bTXADDR : 1; /* Transmit address */
- __IO uint16_t bDORM : 1; /* Dormant */
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */
- __IO uint16_t bSPB : 1; /* Stop bit select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bPAR : 1; /* Parity select */
- __IO uint16_t bPEN : 1; /* Parity enable */
- } b;
- struct { /* UCA1CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCA1CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCA1CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __I uint16_t bRESERVED0 : 14; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
- union { /* UCA1MCTLW Register */
- __IO uint16_t r;
- struct { /* UCA1MCTLW Bits */
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bBRF : 4; /* First modulation stage select */
- __IO uint16_t bBRS : 8; /* Second modulation stage select */
- } b;
- } rMCTLW;
- union { /* UCA1STATW Register */
- __IO uint16_t r;
- struct { /* UCA1STATW Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
- __IO uint16_t bRXERR : 1; /* Receive error flag */
- __IO uint16_t bBRK : 1; /* Break detect flag */
- __IO uint16_t bPE : 1; /* */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA1STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCA1RXBUF Register */
- __I uint16_t r;
- struct { /* UCA1RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA1RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCA1TXBUF Register */
- __IO uint16_t r;
- struct { /* UCA1TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA1TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- union { /* UCA1ABCTL Register */
- __IO uint16_t r;
- struct { /* UCA1ABCTL Bits */
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bBTOE : 1; /* Break time out error */
- __IO uint16_t bSTOE : 1; /* Synch field time out error */
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
- __I uint16_t bRESERVED1 : 10; /* Reserved */
- } b;
- } rABCTL;
- union { /* UCA1IRCTL Register */
- __IO uint16_t r;
- struct { /* UCA1IRCTL Bits */
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */
- } b;
- } rIRCTL;
- uint8_t RESERVED1[6];
- union { /* UCA1IE Register */
- __IO uint16_t r;
- struct { /* UCA1IE Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA1IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCA1IFG Register */
- __IO uint16_t r;
- struct { /* UCA1IFG Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA1IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
-} EUSCI_A1_Type;
+ uint8_t RESERVED0;
+ __I uint8_t IN; /**< Port Input */
+ uint8_t RESERVED1;
+ __IO uint8_t OUT; /**< Port Output */
+ uint8_t RESERVED2;
+ __IO uint8_t DIR; /**< Port Direction */
+ uint8_t RESERVED3;
+ __IO uint8_t REN; /**< Port Resistor Enable */
+ uint8_t RESERVED4;
+ __IO uint8_t DS; /**< Port Drive Strength */
+ uint8_t RESERVED5;
+ __IO uint8_t SEL0; /**< Port Select 0 */
+ uint8_t RESERVED6;
+ __IO uint8_t SEL1; /**< Port Select 1 */
+ uint8_t RESERVED7[9];
+ __IO uint8_t SELC; /**< Port Complement Select */
+ uint8_t RESERVED8;
+ __IO uint8_t IES; /**< Port Interrupt Edge Select */
+ uint8_t RESERVED9;
+ __IO uint8_t IE; /**< Port Interrupt Enable */
+ uint8_t RESERVED10;
+ __IO uint8_t IFG; /**< Port Interrupt Flag */
+ __I uint16_t IV; /**< Port Interrupt Vector Value */
+} DIO_PORT_Even_Interruptable_Type;
+
+/*@}*/ /* end of group MSP432P401R_DIO */
-//*****************************************************************************
-// EUSCI_A2 Registers
-//*****************************************************************************
+/******************************************************************************
+* DMA Registers
+******************************************************************************/
+/** @addtogroup DMA MSP432P401R (DMA)
+ @{
+*/
typedef struct {
- union { /* UCA2CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCA2CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXBRK : 1; /* Transmit break */
- __IO uint16_t bTXADDR : 1; /* Transmit address */
- __IO uint16_t bDORM : 1; /* Dormant */
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */
- __IO uint16_t bSPB : 1; /* Stop bit select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bPAR : 1; /* Parity select */
- __IO uint16_t bPEN : 1; /* Parity enable */
- } b;
- struct { /* UCA2CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCA2CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCA2CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __I uint16_t bRESERVED0 : 14; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
- union { /* UCA2MCTLW Register */
- __IO uint16_t r;
- struct { /* UCA2MCTLW Bits */
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bBRF : 4; /* First modulation stage select */
- __IO uint16_t bBRS : 8; /* Second modulation stage select */
- } b;
- } rMCTLW;
- union { /* UCA2STATW Register */
- __IO uint16_t r;
- struct { /* UCA2STATW Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
- __IO uint16_t bRXERR : 1; /* Receive error flag */
- __IO uint16_t bBRK : 1; /* Break detect flag */
- __IO uint16_t bPE : 1; /* */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA2STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCA2RXBUF Register */
- __I uint16_t r;
- struct { /* UCA2RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA2RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCA2TXBUF Register */
- __IO uint16_t r;
- struct { /* UCA2TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA2TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- union { /* UCA2ABCTL Register */
- __IO uint16_t r;
- struct { /* UCA2ABCTL Bits */
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bBTOE : 1; /* Break time out error */
- __IO uint16_t bSTOE : 1; /* Synch field time out error */
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
- __I uint16_t bRESERVED1 : 10; /* Reserved */
- } b;
- } rABCTL;
- union { /* UCA2IRCTL Register */
- __IO uint16_t r;
- struct { /* UCA2IRCTL Bits */
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */
- } b;
- } rIRCTL;
- uint8_t RESERVED1[6];
- union { /* UCA2IE Register */
- __IO uint16_t r;
- struct { /* UCA2IE Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA2IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCA2IFG Register */
- __IO uint16_t r;
- struct { /* UCA2IFG Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA2IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
-} EUSCI_A2_Type;
+ __I uint32_t DEVICE_CFG; /**< Device Configuration Status */
+ __IO uint32_t SW_CHTRIG; /**< Software Channel Trigger Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t CH_SRCCFG[32]; /**< Channel n Source Configuration Register */
+ uint32_t RESERVED1[28];
+ __IO uint32_t INT1_SRCCFG; /**< Interrupt 1 Source Channel Configuration */
+ __IO uint32_t INT2_SRCCFG; /**< Interrupt 2 Source Channel Configuration Register */
+ __IO uint32_t INT3_SRCCFG; /**< Interrupt 3 Source Channel Configuration Register */
+ uint32_t RESERVED2;
+ __I uint32_t INT0_SRCFLG; /**< Interrupt 0 Source Channel Flag Register */
+ __O uint32_t INT0_CLRFLG; /**< Interrupt 0 Source Channel Clear Flag Register */
+} DMA_Channel_Type;
-
-//*****************************************************************************
-// EUSCI_A3 Registers
-//*****************************************************************************
typedef struct {
- union { /* UCA3CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCA3CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXBRK : 1; /* Transmit break */
- __IO uint16_t bTXADDR : 1; /* Transmit address */
- __IO uint16_t bDORM : 1; /* Dormant */
- __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
- __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_A mode */
- __IO uint16_t bSPB : 1; /* Stop bit select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bPAR : 1; /* Parity select */
- __IO uint16_t bPEN : 1; /* Parity enable */
- } b;
- struct { /* UCA3CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCA3CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCA3CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __I uint16_t bRESERVED0 : 14; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
- union { /* UCA3MCTLW Register */
- __IO uint16_t r;
- struct { /* UCA3MCTLW Bits */
- __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bBRF : 4; /* First modulation stage select */
- __IO uint16_t bBRS : 8; /* Second modulation stage select */
- } b;
- } rMCTLW;
- union { /* UCA3STATW Register */
- __IO uint16_t r;
- struct { /* UCA3STATW Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
- __IO uint16_t bRXERR : 1; /* Receive error flag */
- __IO uint16_t bBRK : 1; /* Break detect flag */
- __IO uint16_t bPE : 1; /* */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA3STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_A busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCA3RXBUF Register */
- __I uint16_t r;
- struct { /* UCA3RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA3RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCA3TXBUF Register */
- __IO uint16_t r;
- struct { /* UCA3TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCA3TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- union { /* UCA3ABCTL Register */
- __IO uint16_t r;
- struct { /* UCA3ABCTL Bits */
- __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bBTOE : 1; /* Break time out error */
- __IO uint16_t bSTOE : 1; /* Synch field time out error */
- __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
- __I uint16_t bRESERVED1 : 10; /* Reserved */
- } b;
- } rABCTL;
- union { /* UCA3IRCTL Register */
- __IO uint16_t r;
- struct { /* UCA3IRCTL Bits */
- __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
- __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
- __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
- __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
- __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
- __IO uint16_t bIRRXFL : 4; /* Receive filter length */
- } b;
- } rIRCTL;
- uint8_t RESERVED1[6];
- union { /* UCA3IE Register */
- __IO uint16_t r;
- struct { /* UCA3IE Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
- __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA3IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCA3IFG Register */
- __IO uint16_t r;
- struct { /* UCA3IFG Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
- __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
- __I uint16_t bRESERVED0 : 12; /* Reserved */
- } b;
- struct { /* UCA3IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
-} EUSCI_A3_Type;
+ __I uint32_t STAT; /**< Status Register */
+ __O uint32_t CFG; /**< Configuration Register */
+ __IO uint32_t CTLBASE; /**< Channel Control Data Base Pointer Register */
+ __I uint32_t ATLBASE; /**< Channel Alternate Control Data Base Pointer Register */
+ __I uint32_t WAITSTAT; /**< Channel Wait on Request Status Register */
+ __O uint32_t SWREQ; /**< Channel Software Request Register */
+ __IO uint32_t USEBURSTSET; /**< Channel Useburst Set Register */
+ __O uint32_t USEBURSTCLR; /**< Channel Useburst Clear Register */
+ __IO uint32_t REQMASKSET; /**< Channel Request Mask Set Register */
+ __O uint32_t REQMASKCLR; /**< Channel Request Mask Clear Register */
+ __IO uint32_t ENASET; /**< Channel Enable Set Register */
+ __O uint32_t ENACLR; /**< Channel Enable Clear Register */
+ __IO uint32_t ALTSET; /**< Channel Primary-Alternate Set Register */
+ __O uint32_t ALTCLR; /**< Channel Primary-Alternate Clear Register */
+ __IO uint32_t PRIOSET; /**< Channel Priority Set Register */
+ __O uint32_t PRIOCLR; /**< Channel Priority Clear Register */
+ uint32_t RESERVED4[3];
+ __IO uint32_t ERRCLR; /**< Bus Error Clear Register */
+} DMA_Control_Type;
+
+/*@}*/ /* end of group DMA */
-//*****************************************************************************
-// EUSCI_B0 Registers
-//*****************************************************************************
+/******************************************************************************
+* EUSCI_A Registers
+******************************************************************************/
+/** @addtogroup EUSCI_A MSP432P401R (EUSCI_A)
+ @{
+*/
typedef struct {
- union { /* UCB0CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCB0CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
- __IO uint16_t bTR : 1; /* Transmitter/receiver */
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMM : 1; /* Multi-master environment select */
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
- __IO uint16_t bA10 : 1; /* Own addressing mode select */
- } b;
- struct { /* UCB0CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCB0CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCB0CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
- __I uint16_t bRESERVED0 : 7; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
- union { /* UCB0STATW Register */
- __IO uint16_t r;
- struct { /* UCB0STATW Bits */
- __I uint16_t bRESERVED1 : 4; /* Reserved */
- __I uint16_t bBBUSY : 1; /* Bus busy */
- __I uint16_t bGC : 1; /* General call address received */
- __I uint16_t bSCLLOW : 1; /* SCL low */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */
- } b;
- struct { /* UCB0STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCB0TBCNT Register */
- __IO uint16_t r;
- struct { /* UCB0TBCNT Bits */
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- } rTBCNT;
- union { /* UCB0RXBUF Register */
- __I uint16_t r;
- struct { /* UCB0RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB0RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCB0TXBUF Register */
- __IO uint16_t r;
- struct { /* UCB0TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB0TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- uint8_t RESERVED1[4];
- union { /* UCB0I2COA0 Register */
- __IO uint16_t r;
- struct { /* UCB0I2COA0 Bits */
- __IO uint16_t bI2COA0 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 4; /* Reserved */
- __IO uint16_t bGCEN : 1; /* General call response enable */
- } b;
- } rI2COA0;
- union { /* UCB0I2COA1 Register */
- __IO uint16_t r;
- struct { /* UCB0I2COA1 Bits */
- __IO uint16_t bI2COA1 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA1;
- union { /* UCB0I2COA2 Register */
- __IO uint16_t r;
- struct { /* UCB0I2COA2 Bits */
- __IO uint16_t bI2COA2 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA2;
- union { /* UCB0I2COA3 Register */
- __IO uint16_t r;
- struct { /* UCB0I2COA3 Bits */
- __IO uint16_t bI2COA3 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA3;
- union { /* UCB0ADDRX Register */
- __I uint16_t r;
- struct { /* UCB0ADDRX Bits */
- __I uint16_t bADDRX : 10; /* Received Address Register */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDRX;
- union { /* UCB0ADDMASK Register */
- __IO uint16_t r;
- struct { /* UCB0ADDMASK Bits */
- __IO uint16_t bADDMASK : 10; /* */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDMASK;
- union { /* UCB0I2CSA Register */
- __IO uint16_t r;
- struct { /* UCB0I2CSA Bits */
- __IO uint16_t bI2CSA : 10; /* I2C slave address */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rI2CSA;
- uint8_t RESERVED2[8];
- union { /* UCB0IE Register */
- __IO uint16_t r;
- struct { /* UCB0IE Bits */
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB0IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCB0IFG Register */
- __IO uint16_t r;
- struct { /* UCB0IFG Bits */
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB0IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
-} EUSCI_B0_Type;
+ __IO uint16_t CTLW0; /**< eUSCI_Ax Control Word Register 0 */
+ __IO uint16_t CTLW1; /**< eUSCI_Ax Control Word Register 1 */
+ uint16_t RESERVED0;
+ __IO uint16_t BRW; /**< eUSCI_Ax Baud Rate Control Word Register */
+ __IO uint16_t MCTLW; /**< eUSCI_Ax Modulation Control Word Register */
+ __IO uint16_t STATW; /**< eUSCI_Ax Status Register */
+ __I uint16_t RXBUF; /**< eUSCI_Ax Receive Buffer Register */
+ __IO uint16_t TXBUF; /**< eUSCI_Ax Transmit Buffer Register */
+ __IO uint16_t ABCTL; /**< eUSCI_Ax Auto Baud Rate Control Register */
+ __IO uint16_t IRCTL; /**< eUSCI_Ax IrDA Control Word Register */
+ uint16_t RESERVED1[3];
+ __IO uint16_t IE; /**< eUSCI_Ax Interrupt Enable Register */
+ __IO uint16_t IFG; /**< eUSCI_Ax Interrupt Flag Register */
+ __I uint16_t IV; /**< eUSCI_Ax Interrupt Vector Register */
+} EUSCI_A_Type;
+/*@}*/ /* end of group EUSCI_A */
-//*****************************************************************************
-// EUSCI_B1 Registers
-//*****************************************************************************
+/** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI)
+ @{
+*/
typedef struct {
- union { /* UCB1CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCB1CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
- __IO uint16_t bTR : 1; /* Transmitter/receiver */
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMM : 1; /* Multi-master environment select */
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
- __IO uint16_t bA10 : 1; /* Own addressing mode select */
- } b;
- struct { /* UCB1CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCB1CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCB1CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
- __I uint16_t bRESERVED0 : 7; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
- union { /* UCB1STATW Register */
- __IO uint16_t r;
- struct { /* UCB1STATW Bits */
- __I uint16_t bRESERVED1 : 4; /* Reserved */
- __I uint16_t bBBUSY : 1; /* Bus busy */
- __I uint16_t bGC : 1; /* General call address received */
- __I uint16_t bSCLLOW : 1; /* SCL low */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */
- } b;
- struct { /* UCB1STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCB1TBCNT Register */
- __IO uint16_t r;
- struct { /* UCB1TBCNT Bits */
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- } rTBCNT;
- union { /* UCB1RXBUF Register */
- __I uint16_t r;
- struct { /* UCB1RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB1RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCB1TXBUF Register */
- __IO uint16_t r;
- struct { /* UCB1TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB1TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- uint8_t RESERVED1[4];
- union { /* UCB1I2COA0 Register */
- __IO uint16_t r;
- struct { /* UCB1I2COA0 Bits */
- __IO uint16_t bI2COA0 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 4; /* Reserved */
- __IO uint16_t bGCEN : 1; /* General call response enable */
- } b;
- } rI2COA0;
- union { /* UCB1I2COA1 Register */
- __IO uint16_t r;
- struct { /* UCB1I2COA1 Bits */
- __IO uint16_t bI2COA1 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA1;
- union { /* UCB1I2COA2 Register */
- __IO uint16_t r;
- struct { /* UCB1I2COA2 Bits */
- __IO uint16_t bI2COA2 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA2;
- union { /* UCB1I2COA3 Register */
- __IO uint16_t r;
- struct { /* UCB1I2COA3 Bits */
- __IO uint16_t bI2COA3 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA3;
- union { /* UCB1ADDRX Register */
- __I uint16_t r;
- struct { /* UCB1ADDRX Bits */
- __I uint16_t bADDRX : 10; /* Received Address Register */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDRX;
- union { /* UCB1ADDMASK Register */
- __IO uint16_t r;
- struct { /* UCB1ADDMASK Bits */
- __IO uint16_t bADDMASK : 10; /* */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDMASK;
- union { /* UCB1I2CSA Register */
- __IO uint16_t r;
- struct { /* UCB1I2CSA Bits */
- __IO uint16_t bI2CSA : 10; /* I2C slave address */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rI2CSA;
- uint8_t RESERVED2[8];
- union { /* UCB1IE Register */
- __IO uint16_t r;
- struct { /* UCB1IE Bits */
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB1IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCB1IFG Register */
- __IO uint16_t r;
- struct { /* UCB1IFG Bits */
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB1IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
-} EUSCI_B1_Type;
+ __IO uint16_t CTLW0; /**< eUSCI_Ax Control Word Register 0 */
+ uint16_t RESERVED0[2];
+ __IO uint16_t BRW; /**< eUSCI_Ax Bit Rate Control Register 1 */
+ uint16_t RESERVED1;
+ __IO uint16_t STATW;
+ __I uint16_t RXBUF; /**< eUSCI_Ax Receive Buffer Register */
+ __IO uint16_t TXBUF; /**< eUSCI_Ax Transmit Buffer Register */
+ uint16_t RESERVED2[5];
+ __IO uint16_t IE; /**< eUSCI_Ax Interrupt Enable Register */
+ __IO uint16_t IFG; /**< eUSCI_Ax Interrupt Flag Register */
+ __I uint16_t IV; /**< eUSCI_Ax Interrupt Vector Register */
+} EUSCI_A_SPI_Type;
+
+/*@}*/ /* end of group EUSCI_A_SPI */
-//*****************************************************************************
-// EUSCI_B2 Registers
-//*****************************************************************************
+/******************************************************************************
+* EUSCI_B Registers
+******************************************************************************/
+/** @addtogroup EUSCI_B MSP432P401R (EUSCI_B)
+ @{
+*/
typedef struct {
- union { /* UCB2CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCB2CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
- __IO uint16_t bTR : 1; /* Transmitter/receiver */
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMM : 1; /* Multi-master environment select */
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
- __IO uint16_t bA10 : 1; /* Own addressing mode select */
- } b;
- struct { /* UCB2CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCB2CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCB2CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
- __I uint16_t bRESERVED0 : 7; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
- union { /* UCB2STATW Register */
- __IO uint16_t r;
- struct { /* UCB2STATW Bits */
- __I uint16_t bRESERVED1 : 4; /* Reserved */
- __I uint16_t bBBUSY : 1; /* Bus busy */
- __I uint16_t bGC : 1; /* General call address received */
- __I uint16_t bSCLLOW : 1; /* SCL low */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */
- } b;
- struct { /* UCB2STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCB2TBCNT Register */
- __IO uint16_t r;
- struct { /* UCB2TBCNT Bits */
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- } rTBCNT;
- union { /* UCB2RXBUF Register */
- __I uint16_t r;
- struct { /* UCB2RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB2RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCB2TXBUF Register */
- __IO uint16_t r;
- struct { /* UCB2TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB2TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- uint8_t RESERVED1[4];
- union { /* UCB2I2COA0 Register */
- __IO uint16_t r;
- struct { /* UCB2I2COA0 Bits */
- __IO uint16_t bI2COA0 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 4; /* Reserved */
- __IO uint16_t bGCEN : 1; /* General call response enable */
- } b;
- } rI2COA0;
- union { /* UCB2I2COA1 Register */
- __IO uint16_t r;
- struct { /* UCB2I2COA1 Bits */
- __IO uint16_t bI2COA1 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA1;
- union { /* UCB2I2COA2 Register */
- __IO uint16_t r;
- struct { /* UCB2I2COA2 Bits */
- __IO uint16_t bI2COA2 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA2;
- union { /* UCB2I2COA3 Register */
- __IO uint16_t r;
- struct { /* UCB2I2COA3 Bits */
- __IO uint16_t bI2COA3 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA3;
- union { /* UCB2ADDRX Register */
- __I uint16_t r;
- struct { /* UCB2ADDRX Bits */
- __I uint16_t bADDRX : 10; /* Received Address Register */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDRX;
- union { /* UCB2ADDMASK Register */
- __IO uint16_t r;
- struct { /* UCB2ADDMASK Bits */
- __IO uint16_t bADDMASK : 10; /* */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDMASK;
- union { /* UCB2I2CSA Register */
- __IO uint16_t r;
- struct { /* UCB2I2CSA Bits */
- __IO uint16_t bI2CSA : 10; /* I2C slave address */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rI2CSA;
- uint8_t RESERVED2[8];
- union { /* UCB2IE Register */
- __IO uint16_t r;
- struct { /* UCB2IE Bits */
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB2IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCB2IFG Register */
- __IO uint16_t r;
- struct { /* UCB2IFG Bits */
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB2IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
-} EUSCI_B2_Type;
+ __IO uint16_t CTLW0; /**< eUSCI_Bx Control Word Register 0 */
+ __IO uint16_t CTLW1; /**< eUSCI_Bx Control Word Register 1 */
+ uint16_t RESERVED0;
+ __IO uint16_t BRW; /**< eUSCI_Bx Baud Rate Control Word Register */
+ __IO uint16_t STATW; /**< eUSCI_Bx Status Register */
+ __IO uint16_t TBCNT; /**< eUSCI_Bx Byte Counter Threshold Register */
+ __I uint16_t RXBUF; /**< eUSCI_Bx Receive Buffer Register */
+ __IO uint16_t TXBUF; /**< eUSCI_Bx Transmit Buffer Register */
+ uint16_t RESERVED1[2];
+ __IO uint16_t I2COA0; /**< eUSCI_Bx I2C Own Address 0 Register */
+ __IO uint16_t I2COA1; /**< eUSCI_Bx I2C Own Address 1 Register */
+ __IO uint16_t I2COA2; /**< eUSCI_Bx I2C Own Address 2 Register */
+ __IO uint16_t I2COA3; /**< eUSCI_Bx I2C Own Address 3 Register */
+ __I uint16_t ADDRX; /**< eUSCI_Bx I2C Received Address Register */
+ __IO uint16_t ADDMASK; /**< eUSCI_Bx I2C Address Mask Register */
+ __IO uint16_t I2CSA; /**< eUSCI_Bx I2C Slave Address Register */
+ uint16_t RESERVED2[4];
+ __IO uint16_t IE; /**< eUSCI_Bx Interrupt Enable Register */
+ __IO uint16_t IFG; /**< eUSCI_Bx Interrupt Flag Register */
+ __I uint16_t IV; /**< eUSCI_Bx Interrupt Vector Register */
+} EUSCI_B_Type;
+/*@}*/ /* end of group EUSCI_B */
-//*****************************************************************************
-// EUSCI_B3 Registers
-//*****************************************************************************
+/** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI)
+ @{
+*/
typedef struct {
- union { /* UCB3CTLW0 Register */
- __IO uint16_t r;
- struct { /* UCB3CTLW0 Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
- __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
- __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
- __IO uint16_t bTR : 1; /* Transmitter/receiver */
- __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI_B mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMM : 1; /* Multi-master environment select */
- __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
- __IO uint16_t bA10 : 1; /* Own addressing mode select */
- } b;
- struct { /* UCB3CTLW0_SPI Bits */
- __IO uint16_t bSWRST : 1; /* Software reset enable */
- __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
- __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
- __IO uint16_t bMODE : 2; /* eUSCI mode */
- __IO uint16_t bMST : 1; /* Master mode select */
- __IO uint16_t b7BIT : 1; /* Character length */
- __IO uint16_t bMSB : 1; /* MSB first select */
- __IO uint16_t bCKPL : 1; /* Clock polarity select */
- __IO uint16_t bCKPH : 1; /* Clock phase select */
- } a;
- } rCTLW0;
- union { /* UCB3CTLW1 Register */
- __IO uint16_t r;
- struct { /* UCB3CTLW1 Bits */
- __IO uint16_t bGLIT : 2; /* Deglitch time */
- __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
- __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
- __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
- __IO uint16_t bCLTO : 2; /* Clock low timeout select */
- __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
- __I uint16_t bRESERVED0 : 7; /* Reserved */
- } b;
- } rCTLW1;
- uint8_t RESERVED0[2];
- __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
- union { /* UCB3STATW Register */
- __IO uint16_t r;
- struct { /* UCB3STATW Bits */
- __I uint16_t bRESERVED1 : 4; /* Reserved */
- __I uint16_t bBBUSY : 1; /* Bus busy */
- __I uint16_t bGC : 1; /* General call address received */
- __I uint16_t bSCLLOW : 1; /* SCL low */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __I uint16_t bBCNT : 8; /* Hardware byte counter value */
- } b;
- struct { /* UCB3STATW_SPI Bits */
- __I uint16_t bBUSY : 1; /* eUSCI_B busy */
- __IO uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bOE : 1; /* Overrun error flag */
- __IO uint16_t bFE : 1; /* Framing error flag */
- __IO uint16_t bLISTEN : 1; /* Listen enable */
- } a;
- } rSTATW;
- union { /* UCB3TBCNT Register */
- __IO uint16_t r;
- struct { /* UCB3TBCNT Bits */
- __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- } rTBCNT;
- union { /* UCB3RXBUF Register */
- __I uint16_t r;
- struct { /* UCB3RXBUF Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB3RXBUF_SPI Bits */
- __I uint16_t bRXBUF : 8; /* Receive data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rRXBUF;
- union { /* UCB3TXBUF Register */
- __IO uint16_t r;
- struct { /* UCB3TXBUF Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED0 : 8; /* Reserved */
- } b;
- struct { /* UCB3TXBUF_SPI Bits */
- __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
- __I uint16_t bRESERVED : 8; /* Reserved */
- } a;
- } rTXBUF;
- uint8_t RESERVED1[4];
- union { /* UCB3I2COA0 Register */
- __IO uint16_t r;
- struct { /* UCB3I2COA0 Bits */
- __IO uint16_t bI2COA0 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 4; /* Reserved */
- __IO uint16_t bGCEN : 1; /* General call response enable */
- } b;
- } rI2COA0;
- union { /* UCB3I2COA1 Register */
- __IO uint16_t r;
- struct { /* UCB3I2COA1 Bits */
- __IO uint16_t bI2COA1 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA1;
- union { /* UCB3I2COA2 Register */
- __IO uint16_t r;
- struct { /* UCB3I2COA2 Bits */
- __IO uint16_t bI2COA2 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA2;
- union { /* UCB3I2COA3 Register */
- __IO uint16_t r;
- struct { /* UCB3I2COA3 Bits */
- __IO uint16_t bI2COA3 : 10; /* I2C own address */
- __IO uint16_t bOAEN : 1; /* Own Address enable register */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- } b;
- } rI2COA3;
- union { /* UCB3ADDRX Register */
- __I uint16_t r;
- struct { /* UCB3ADDRX Bits */
- __I uint16_t bADDRX : 10; /* Received Address Register */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDRX;
- union { /* UCB3ADDMASK Register */
- __IO uint16_t r;
- struct { /* UCB3ADDMASK Bits */
- __IO uint16_t bADDMASK : 10; /* */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rADDMASK;
- union { /* UCB3I2CSA Register */
- __IO uint16_t r;
- struct { /* UCB3I2CSA Bits */
- __IO uint16_t bI2CSA : 10; /* I2C slave address */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rI2CSA;
- uint8_t RESERVED2[8];
- union { /* UCB3IE Register */
- __IO uint16_t r;
- struct { /* UCB3IE Bits */
- __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
- __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
- __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
- __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
- __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
- __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
- __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
- __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
- __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
- __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
- __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
- __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
- __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
- __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
- __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB3IE_SPI Bits */
- __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
- __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIE;
- union { /* UCB3IFG Register */
- __IO uint16_t r;
- struct { /* UCB3IFG Bits */
- __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
- __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
- __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
- __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
- __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
- __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
- __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
- __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
- __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
- __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
- __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
- __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
- __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
- __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
- __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- } b;
- struct { /* UCB3IFG_SPI Bits */
- __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
- __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
- __I uint16_t bRESERVED : 14; /* Reserved */
- } a;
- } rIFG;
- __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
-} EUSCI_B3_Type;
+ __IO uint16_t CTLW0; /**< eUSCI_Bx Control Word Register 0 */
+ uint16_t RESERVED0[2];
+ __IO uint16_t BRW; /**< eUSCI_Bx Bit Rate Control Register 1 */
+ __IO uint16_t STATW;
+ uint16_t RESERVED1;
+ __I uint16_t RXBUF; /**< eUSCI_Bx Receive Buffer Register */
+ __IO uint16_t TXBUF; /**< eUSCI_Bx Transmit Buffer Register */
+ uint16_t RESERVED2[13];
+ __IO uint16_t IE; /**< eUSCI_Bx Interrupt Enable Register */
+ __IO uint16_t IFG; /**< eUSCI_Bx Interrupt Flag Register */
+ __I uint16_t IV; /**< eUSCI_Bx Interrupt Vector Register */
+} EUSCI_B_SPI_Type;
+
+/*@}*/ /* end of group EUSCI_B_SPI */
-//*****************************************************************************
-// FLCTL Registers
-//*****************************************************************************
+/******************************************************************************
+* FLCTL Registers
+******************************************************************************/
+/** @addtogroup FLCTL MSP432P401R (FLCTL)
+ @{
+*/
typedef struct {
- union { /* FLCTL_POWER_STAT Register */
- __I uint32_t r;
- struct { /* FLCTL_POWER_STAT Bits */
- __I uint32_t bPSTAT : 3; /* */
- __I uint32_t bLDOSTAT : 1; /* PSS FLDO GOOD status */
- __I uint32_t bVREFSTAT : 1; /* PSS VREF stable status */
- __I uint32_t bIREFSTAT : 1; /* PSS IREF stable status */
- __I uint32_t bTRIMSTAT : 1; /* PSS trim done status */
- __I uint32_t bRD_2T : 1; /* Indicates if Flash is being accessed in 2T mode */
- __I uint32_t bRESERVED0 : 24; /* Reserved */
- } b;
- } rPOWER_STAT;
- uint8_t RESERVED0[12];
- union { /* FLCTL_BANK0_RDCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_BANK0_RDCTL Bits */
- __IO uint32_t bRD_MODE : 4; /* Flash read mode control setting for Bank 0 */
- __IO uint32_t bBUFI : 1; /* Enables read buffering feature for instruction fetches to this Bank */
- __IO uint32_t bBUFD : 1; /* Enables read buffering feature for data reads to this Bank */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bRESERVED2 : 1; /* Reserved */
- __IO uint32_t bRESERVED3 : 1; /* Reserved */
- __IO uint32_t bRESERVED4 : 1; /* Reserved */
- __IO uint32_t bWAIT : 4; /* Number of wait states for read */
- __I uint32_t bRD_MODE_STATUS : 4; /* Read mode */
- __I uint32_t bRESERVED5 : 12; /* Reserved */
- } b;
- } rBANK0_RDCTL;
- union { /* FLCTL_BANK1_RDCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_BANK1_RDCTL Bits */
- __IO uint32_t bRD_MODE : 4; /* Flash read mode control setting for Bank 0 */
- __IO uint32_t bBUFI : 1; /* Enables read buffering feature for instruction fetches to this Bank */
- __IO uint32_t bBUFD : 1; /* Enables read buffering feature for data reads to this Bank */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bRESERVED2 : 1; /* Reserved */
- __IO uint32_t bRESERVED3 : 1; /* Reserved */
- __IO uint32_t bRESERVED4 : 1; /* Reserved */
- __IO uint32_t bWAIT : 4; /* Number of wait states for read */
- __I uint32_t bRD_MODE_STATUS : 4; /* Read mode */
- __I uint32_t bRESERVED5 : 12; /* Reserved */
- } b;
- } rBANK1_RDCTL;
- uint8_t RESERVED1[8];
- union { /* FLCTL_RDBRST_CTLSTAT Register */
- __IO uint32_t r;
- struct { /* FLCTL_RDBRST_CTLSTAT Bits */
- __O uint32_t bSTART : 1; /* Start of burst/compare operation */
- __IO uint32_t bMEM_TYPE : 2; /* Type of memory that burst is carried out on */
- __IO uint32_t bSTOP_FAIL : 1; /* Terminate burst/compare operation */
- __IO uint32_t bDATA_CMP : 1; /* Data pattern used for comparison against memory read data */
- __IO uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bTEST_EN : 1; /* Enable comparison against test data compare registers */
- __I uint32_t bRESERVED1 : 9; /* Reserved */
- __I uint32_t bBRST_STAT : 2; /* Status of Burst/Compare operation */
- __I uint32_t bCMP_ERR : 1; /* Burst/Compare Operation encountered atleast one data */
- __I uint32_t bADDR_ERR : 1; /* Burst/Compare Operation was terminated due to access to */
- __I uint32_t bRESERVED2 : 3; /* Reserved */
- __O uint32_t bCLR_STAT : 1; /* Clear status bits 19-16 of this register */
- __I uint32_t bRESERVED3 : 8; /* Reserved */
- } b;
- } rRDBRST_CTLSTAT;
- union { /* FLCTL_RDBRST_STARTADDR Register */
- __IO uint32_t r;
- struct { /* FLCTL_RDBRST_STARTADDR Bits */
- __IO uint32_t bSTART_ADDRESS : 21; /* Start Address of Burst Operation */
- __I uint32_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rRDBRST_STARTADDR;
- union { /* FLCTL_RDBRST_LEN Register */
- __IO uint32_t r;
- struct { /* FLCTL_RDBRST_LEN Bits */
- __IO uint32_t bBURST_LENGTH : 21; /* Length of Burst Operation */
- __I uint32_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rRDBRST_LEN;
- uint8_t RESERVED2[16];
- union { /* FLCTL_RDBRST_FAILADDR Register */
- __IO uint32_t r;
- struct { /* FLCTL_RDBRST_FAILADDR Bits */
- __IO uint32_t bFAIL_ADDRESS : 21; /* Reflects address of last failed compare */
- __I uint32_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rRDBRST_FAILADDR;
- union { /* FLCTL_RDBRST_FAILCNT Register */
- __IO uint32_t r;
- struct { /* FLCTL_RDBRST_FAILCNT Bits */
- __IO uint32_t bFAIL_COUNT : 17; /* Number of failures encountered in burst operation */
- __I uint32_t bRESERVED0 : 15; /* Reserved */
- } b;
- } rRDBRST_FAILCNT;
- uint8_t RESERVED3[12];
- union { /* FLCTL_PRG_CTLSTAT Register */
- __IO uint32_t r;
- struct { /* FLCTL_PRG_CTLSTAT Bits */
- __IO uint32_t bENABLE : 1; /* Master control for all word program operations */
- __IO uint32_t bMODE : 1; /* Write mode */
- __IO uint32_t bVER_PRE : 1; /* Controls automatic pre program verify operations */
- __IO uint32_t bVER_PST : 1; /* Controls automatic post program verify operations */
- __I uint32_t bRESERVED0 : 12; /* Reserved */
- __I uint32_t bSTATUS : 2; /* Status of program operations in the Flash memory */
- __I uint32_t bBNK_ACT : 1; /* Bank active */
- __I uint32_t bRESERVED1 : 13; /* Reserved */
- } b;
- } rPRG_CTLSTAT;
- union { /* FLCTL_PRGBRST_CTLSTAT Register */
- __IO uint32_t r;
- struct { /* FLCTL_PRGBRST_CTLSTAT Bits */
- __O uint32_t bSTART : 1; /* Trigger start of burst program operation */
- __IO uint32_t bTYPE : 2; /* Type of memory that burst program is carried out on */
- __IO uint32_t bLEN : 3; /* Length of burst */
- __IO uint32_t bAUTO_PRE : 1; /* Auto-Verify operation before the Burst Program */
- __IO uint32_t bAUTO_PST : 1; /* Auto-Verify operation after the Burst Program */
- __I uint32_t bRESERVED0 : 8; /* Reserved */
- __I uint32_t bBURST_STATUS : 3; /* Status of a Burst Operation */
- __I uint32_t bPRE_ERR : 1; /* Burst Operation encountered preprogram auto-verify errors */
- __I uint32_t bPST_ERR : 1; /* Burst Operation encountered postprogram auto-verify errors */
- __I uint32_t bADDR_ERR : 1; /* Burst Operation was terminated due to attempted program of reserved memory */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __O uint32_t bCLR_STAT : 1; /* Clear status bits 21-16 of this register */
- __I uint32_t bRESERVED2 : 8; /* Reserved */
- } b;
- } rPRGBRST_CTLSTAT;
- union { /* FLCTL_PRGBRST_STARTADDR Register */
- __IO uint32_t r;
- struct { /* FLCTL_PRGBRST_STARTADDR Bits */
- __IO uint32_t bSTART_ADDRESS : 22; /* Start Address of Program Burst Operation */
- __I uint32_t bRESERVED0 : 10; /* Reserved */
- } b;
- } rPRGBRST_STARTADDR;
- uint8_t RESERVED4[4];
- __IO uint32_t rPRGBRST_DATA0_0; /* Program Burst Data0 Register0 */
- __IO uint32_t rPRGBRST_DATA0_1; /* Program Burst Data0 Register1 */
- __IO uint32_t rPRGBRST_DATA0_2; /* Program Burst Data0 Register2 */
- __IO uint32_t rPRGBRST_DATA0_3; /* Program Burst Data0 Register3 */
- __IO uint32_t rPRGBRST_DATA1_0; /* Program Burst Data1 Register0 */
- __IO uint32_t rPRGBRST_DATA1_1; /* Program Burst Data1 Register1 */
- __IO uint32_t rPRGBRST_DATA1_2; /* Program Burst Data1 Register2 */
- __IO uint32_t rPRGBRST_DATA1_3; /* Program Burst Data1 Register3 */
- __IO uint32_t rPRGBRST_DATA2_0; /* Program Burst Data2 Register0 */
- __IO uint32_t rPRGBRST_DATA2_1; /* Program Burst Data2 Register1 */
- __IO uint32_t rPRGBRST_DATA2_2; /* Program Burst Data2 Register2 */
- __IO uint32_t rPRGBRST_DATA2_3; /* Program Burst Data2 Register3 */
- __IO uint32_t rPRGBRST_DATA3_0; /* Program Burst Data3 Register0 */
- __IO uint32_t rPRGBRST_DATA3_1; /* Program Burst Data3 Register1 */
- __IO uint32_t rPRGBRST_DATA3_2; /* Program Burst Data3 Register2 */
- __IO uint32_t rPRGBRST_DATA3_3; /* Program Burst Data3 Register3 */
- union { /* FLCTL_ERASE_CTLSTAT Register */
- __IO uint32_t r;
- struct { /* FLCTL_ERASE_CTLSTAT Bits */
- __O uint32_t bSTART : 1; /* Start of Erase operation */
- __IO uint32_t bMODE : 1; /* Erase mode selected by application */
- __IO uint32_t bTYPE : 2; /* Type of memory that erase operation is carried out on */
- __I uint32_t bRESERVED0 : 12; /* Reserved */
- __I uint32_t bSTATUS : 2; /* Status of erase operations in the Flash memory */
- __I uint32_t bADDR_ERR : 1; /* Erase Operation was terminated due to attempted erase of reserved memory address */
- __O uint32_t bCLR_STAT : 1; /* Clear status bits 18-16 of this register */
- __I uint32_t bRESERVED1 : 12; /* Reserved */
- } b;
- } rERASE_CTLSTAT;
- union { /* FLCTL_ERASE_SECTADDR Register */
- __IO uint32_t r;
- struct { /* FLCTL_ERASE_SECTADDR Bits */
- __IO uint32_t bSECT_ADDRESS : 22; /* Address of Sector being Erased */
- __I uint32_t bRESERVED0 : 10; /* Reserved */
- } b;
- } rERASE_SECTADDR;
- uint8_t RESERVED5[8];
- union { /* FLCTL_BANK0_INFO_WEPROT Register */
- __IO uint32_t r;
- struct { /* FLCTL_BANK0_INFO_WEPROT Bits */
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase */
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase */
- __I uint32_t bRESERVED0 : 30; /* Reserved */
- } b;
- } rBANK0_INFO_WEPROT;
- union { /* FLCTL_BANK0_MAIN_WEPROT Register */
- __IO uint32_t r;
- struct { /* FLCTL_BANK0_MAIN_WEPROT Bits */
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase */
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase */
- __IO uint32_t bPROT2 : 1; /* Protects Sector 2 from program or erase */
- __IO uint32_t bPROT3 : 1; /* Protects Sector 3 from program or erase */
- __IO uint32_t bPROT4 : 1; /* Protects Sector 4 from program or erase */
- __IO uint32_t bPROT5 : 1; /* Protects Sector 5 from program or erase */
- __IO uint32_t bPROT6 : 1; /* Protects Sector 6 from program or erase */
- __IO uint32_t bPROT7 : 1; /* Protects Sector 7 from program or erase */
- __IO uint32_t bPROT8 : 1; /* Protects Sector 8 from program or erase */
- __IO uint32_t bPROT9 : 1; /* Protects Sector 9 from program or erase */
- __IO uint32_t bPROT10 : 1; /* Protects Sector 10 from program or erase */
- __IO uint32_t bPROT11 : 1; /* Protects Sector 11 from program or erase */
- __IO uint32_t bPROT12 : 1; /* Protects Sector 12 from program or erase */
- __IO uint32_t bPROT13 : 1; /* Protects Sector 13 from program or erase */
- __IO uint32_t bPROT14 : 1; /* Protects Sector 14 from program or erase */
- __IO uint32_t bPROT15 : 1; /* Protects Sector 15 from program or erase */
- __IO uint32_t bPROT16 : 1; /* Protects Sector 16 from program or erase */
- __IO uint32_t bPROT17 : 1; /* Protects Sector 17 from program or erase */
- __IO uint32_t bPROT18 : 1; /* Protects Sector 18 from program or erase */
- __IO uint32_t bPROT19 : 1; /* Protects Sector 19 from program or erase */
- __IO uint32_t bPROT20 : 1; /* Protects Sector 20 from program or erase */
- __IO uint32_t bPROT21 : 1; /* Protects Sector 21 from program or erase */
- __IO uint32_t bPROT22 : 1; /* Protects Sector 22 from program or erase */
- __IO uint32_t bPROT23 : 1; /* Protects Sector 23 from program or erase */
- __IO uint32_t bPROT24 : 1; /* Protects Sector 24 from program or erase */
- __IO uint32_t bPROT25 : 1; /* Protects Sector 25 from program or erase */
- __IO uint32_t bPROT26 : 1; /* Protects Sector 26 from program or erase */
- __IO uint32_t bPROT27 : 1; /* Protects Sector 27 from program or erase */
- __IO uint32_t bPROT28 : 1; /* Protects Sector 28 from program or erase */
- __IO uint32_t bPROT29 : 1; /* Protects Sector 29 from program or erase */
- __IO uint32_t bPROT30 : 1; /* Protects Sector 30 from program or erase */
- __IO uint32_t bPROT31 : 1; /* Protects Sector 31 from program or erase */
- } b;
- } rBANK0_MAIN_WEPROT;
- uint8_t RESERVED6[8];
- union { /* FLCTL_BANK1_INFO_WEPROT Register */
- __IO uint32_t r;
- struct { /* FLCTL_BANK1_INFO_WEPROT Bits */
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase operations */
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase operations */
- __I uint32_t bRESERVED0 : 30; /* Reserved */
- } b;
- } rBANK1_INFO_WEPROT;
- union { /* FLCTL_BANK1_MAIN_WEPROT Register */
- __IO uint32_t r;
- struct { /* FLCTL_BANK1_MAIN_WEPROT Bits */
- __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase operations */
- __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase operations */
- __IO uint32_t bPROT2 : 1; /* Protects Sector 2 from program or erase operations */
- __IO uint32_t bPROT3 : 1; /* Protects Sector 3 from program or erase operations */
- __IO uint32_t bPROT4 : 1; /* Protects Sector 4 from program or erase operations */
- __IO uint32_t bPROT5 : 1; /* Protects Sector 5 from program or erase operations */
- __IO uint32_t bPROT6 : 1; /* Protects Sector 6 from program or erase operations */
- __IO uint32_t bPROT7 : 1; /* Protects Sector 7 from program or erase operations */
- __IO uint32_t bPROT8 : 1; /* Protects Sector 8 from program or erase operations */
- __IO uint32_t bPROT9 : 1; /* Protects Sector 9 from program or erase operations */
- __IO uint32_t bPROT10 : 1; /* Protects Sector 10 from program or erase operations */
- __IO uint32_t bPROT11 : 1; /* Protects Sector 11 from program or erase operations */
- __IO uint32_t bPROT12 : 1; /* Protects Sector 12 from program or erase operations */
- __IO uint32_t bPROT13 : 1; /* Protects Sector 13 from program or erase operations */
- __IO uint32_t bPROT14 : 1; /* Protects Sector 14 from program or erase operations */
- __IO uint32_t bPROT15 : 1; /* Protects Sector 15 from program or erase operations */
- __IO uint32_t bPROT16 : 1; /* Protects Sector 16 from program or erase operations */
- __IO uint32_t bPROT17 : 1; /* Protects Sector 17 from program or erase operations */
- __IO uint32_t bPROT18 : 1; /* Protects Sector 18 from program or erase operations */
- __IO uint32_t bPROT19 : 1; /* Protects Sector 19 from program or erase operations */
- __IO uint32_t bPROT20 : 1; /* Protects Sector 20 from program or erase operations */
- __IO uint32_t bPROT21 : 1; /* Protects Sector 21 from program or erase operations */
- __IO uint32_t bPROT22 : 1; /* Protects Sector 22 from program or erase operations */
- __IO uint32_t bPROT23 : 1; /* Protects Sector 23 from program or erase operations */
- __IO uint32_t bPROT24 : 1; /* Protects Sector 24 from program or erase operations */
- __IO uint32_t bPROT25 : 1; /* Protects Sector 25 from program or erase operations */
- __IO uint32_t bPROT26 : 1; /* Protects Sector 26 from program or erase operations */
- __IO uint32_t bPROT27 : 1; /* Protects Sector 27 from program or erase operations */
- __IO uint32_t bPROT28 : 1; /* Protects Sector 28 from program or erase operations */
- __IO uint32_t bPROT29 : 1; /* Protects Sector 29 from program or erase operations */
- __IO uint32_t bPROT30 : 1; /* Protects Sector 30 from program or erase operations */
- __IO uint32_t bPROT31 : 1; /* Protects Sector 31 from program or erase operations */
- } b;
- } rBANK1_MAIN_WEPROT;
- uint8_t RESERVED7[8];
- union { /* FLCTL_BMRK_CTLSTAT Register */
- __IO uint32_t r;
- struct { /* FLCTL_BMRK_CTLSTAT Bits */
- __IO uint32_t bI_BMRK : 1; /* */
- __IO uint32_t bD_BMRK : 1; /* */
- __IO uint32_t bCMP_EN : 1; /* */
- __IO uint32_t bCMP_SEL : 1; /* */
- __I uint32_t bRESERVED0 : 28; /* Reserved */
- } b;
- } rBMRK_CTLSTAT;
- __IO uint32_t rBMRK_IFETCH; /* Benchmark Instruction Fetch Count Register */
- __IO uint32_t rBMRK_DREAD; /* Benchmark Data Read Count Register */
- __IO uint32_t rBMRK_CMP; /* Benchmark Count Compare Register */
- uint8_t RESERVED8[16];
- union { /* FLCTL_IFG Register */
- __IO uint32_t r;
- struct { /* FLCTL_IFG Bits */
- __I uint32_t bRDBRST : 1; /* */
- __I uint32_t bAVPRE : 1; /* */
- __I uint32_t bAVPST : 1; /* */
- __I uint32_t bPRG : 1; /* */
- __I uint32_t bPRGB : 1; /* */
- __I uint32_t bERASE : 1; /* */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __I uint32_t bRESERVED1 : 1; /* Reserved */
- __I uint32_t bBMRK : 1; /* */
- __I uint32_t bPRG_ERR : 1; /* */
- __I uint32_t bRESERVED2 : 22; /* Reserved */
- } b;
- } rIFG;
- union { /* FLCTL_IE Register */
- __IO uint32_t r;
- struct { /* FLCTL_IE Bits */
- __IO uint32_t bRDBRST : 1; /* */
- __IO uint32_t bAVPRE : 1; /* */
- __IO uint32_t bAVPST : 1; /* */
- __IO uint32_t bPRG : 1; /* */
- __IO uint32_t bPRGB : 1; /* */
- __IO uint32_t bERASE : 1; /* */
- __IO uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bRESERVED1 : 1; /* Reserved */
- __IO uint32_t bBMRK : 1; /* */
- __IO uint32_t bPRG_ERR : 1; /* */
- __I uint32_t bRESERVED2 : 22; /* Reserved */
- } b;
- } rIE;
- union { /* FLCTL_CLRIFG Register */
- __IO uint32_t r;
- struct { /* FLCTL_CLRIFG Bits */
- __O uint32_t bRDBRST : 1; /* */
- __O uint32_t bAVPRE : 1; /* */
- __O uint32_t bAVPST : 1; /* */
- __O uint32_t bPRG : 1; /* */
- __O uint32_t bPRGB : 1; /* */
- __O uint32_t bERASE : 1; /* */
- __O uint32_t bRESERVED0 : 1; /* Reserved */
- __O uint32_t bRESERVED1 : 1; /* Reserved */
- __O uint32_t bBMRK : 1; /* */
- __O uint32_t bPRG_ERR : 1; /* */
- __I uint32_t bRESERVED2 : 22; /* Reserved */
- } b;
- } rCLRIFG;
- union { /* FLCTL_SETIFG Register */
- __IO uint32_t r;
- struct { /* FLCTL_SETIFG Bits */
- __O uint32_t bRDBRST : 1; /* */
- __O uint32_t bAVPRE : 1; /* */
- __O uint32_t bAVPST : 1; /* */
- __O uint32_t bPRG : 1; /* */
- __O uint32_t bPRGB : 1; /* */
- __O uint32_t bERASE : 1; /* */
- __O uint32_t bRESERVED0 : 1; /* Reserved */
- __O uint32_t bRESERVED1 : 1; /* Reserved */
- __O uint32_t bBMRK : 1; /* */
- __O uint32_t bPRG_ERR : 1; /* */
- __I uint32_t bRESERVED2 : 22; /* Reserved */
- } b;
- } rSETIFG;
- union { /* FLCTL_READ_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_READ_TIMCTL Bits */
- __IO uint32_t bSETUP : 8; /* */
- __IO uint32_t bHOLD : 4; /* */
- __IO uint32_t bIREF_BOOST1 : 4; /* */
- __IO uint32_t bSETUP_LONG : 8; /* */
- __I uint32_t bRESERVED0 : 8; /* Reserved */
- } b;
- } rREAD_TIMCTL;
- union { /* FLCTL_READMARGIN_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_READMARGIN_TIMCTL Bits */
- __IO uint32_t bSETUP : 8; /* */
- __IO uint32_t bHOLD : 4; /* */
- __I uint32_t bRESERVED0 : 4; /* Reserved */
- __I uint32_t bRESERVED1 : 16; /* Reserved */
- } b;
- } rREADMARGIN_TIMCTL;
- union { /* FLCTL_PRGVER_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_PRGVER_TIMCTL Bits */
- __IO uint32_t bSETUP : 8; /* */
- __IO uint32_t bACTIVE : 4; /* */
- __IO uint32_t bHOLD : 4; /* */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rPRGVER_TIMCTL;
- union { /* FLCTL_ERSVER_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_ERSVER_TIMCTL Bits */
- __IO uint32_t bSETUP : 8; /* */
- __IO uint32_t bHOLD : 4; /* */
- __I uint32_t bRESERVED0 : 4; /* Reserved */
- __I uint32_t bRESERVED1 : 16; /* Reserved */
- } b;
- } rERSVER_TIMCTL;
- union { /* FLCTL_LKGVER_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_LKGVER_TIMCTL Bits */
- __IO uint32_t bSETUP : 8; /* */
- __IO uint32_t bHOLD : 4; /* */
- __I uint32_t bRESERVED0 : 4; /* Reserved */
- __I uint32_t bRESERVED1 : 16; /* Reserved */
- } b;
- } rLKGVER_TIMCTL;
- union { /* FLCTL_PROGRAM_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_PROGRAM_TIMCTL Bits */
- __IO uint32_t bSETUP : 8; /* */
- __IO uint32_t bACTIVE : 20; /* */
- __IO uint32_t bHOLD : 4; /* */
- } b;
- } rPROGRAM_TIMCTL;
- union { /* FLCTL_ERASE_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_ERASE_TIMCTL Bits */
- __IO uint32_t bSETUP : 8; /* */
- __IO uint32_t bACTIVE : 20; /* */
- __IO uint32_t bHOLD : 4; /* */
- } b;
- } rERASE_TIMCTL;
- union { /* FLCTL_MASSERASE_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_MASSERASE_TIMCTL Bits */
- __IO uint32_t bBOOST_ACTIVE : 8; /* */
- __IO uint32_t bBOOST_HOLD : 8; /* */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMASSERASE_TIMCTL;
- union { /* FLCTL_BURSTPRG_TIMCTL Register */
- __IO uint32_t r;
- struct { /* FLCTL_BURSTPRG_TIMCTL Bits */
- __I uint32_t bRESERVED0 : 8; /* Reserved */
- __IO uint32_t bACTIVE : 20; /* */
- __I uint32_t bRESERVED1 : 4; /* Reserved */
- } b;
- } rBURSTPRG_TIMCTL;
+ __I uint32_t POWER_STAT; /**< Power Status Register */
+ uint32_t RESERVED0[3];
+ __IO uint32_t BANK0_RDCTL; /**< Bank0 Read Control Register */
+ __IO uint32_t BANK1_RDCTL; /**< Bank1 Read Control Register */
+ uint32_t RESERVED1[2];
+ __IO uint32_t RDBRST_CTLSTAT; /**< Read Burst/Compare Control and Status Register */
+ __IO uint32_t RDBRST_STARTADDR; /**< Read Burst/Compare Start Address Register */
+ __IO uint32_t RDBRST_LEN; /**< Read Burst/Compare Length Register */
+ uint32_t RESERVED2[4];
+ __IO uint32_t RDBRST_FAILADDR; /**< Read Burst/Compare Fail Address Register */
+ __IO uint32_t RDBRST_FAILCNT; /**< Read Burst/Compare Fail Count Register */
+ uint32_t RESERVED3[3];
+ __IO uint32_t PRG_CTLSTAT; /**< Program Control and Status Register */
+ __IO uint32_t PRGBRST_CTLSTAT; /**< Program Burst Control and Status Register */
+ __IO uint32_t PRGBRST_STARTADDR; /**< Program Burst Start Address Register */
+ uint32_t RESERVED4;
+ __IO uint32_t PRGBRST_DATA0_0; /**< Program Burst Data0 Register0 */
+ __IO uint32_t PRGBRST_DATA0_1; /**< Program Burst Data0 Register1 */
+ __IO uint32_t PRGBRST_DATA0_2; /**< Program Burst Data0 Register2 */
+ __IO uint32_t PRGBRST_DATA0_3; /**< Program Burst Data0 Register3 */
+ __IO uint32_t PRGBRST_DATA1_0; /**< Program Burst Data1 Register0 */
+ __IO uint32_t PRGBRST_DATA1_1; /**< Program Burst Data1 Register1 */
+ __IO uint32_t PRGBRST_DATA1_2; /**< Program Burst Data1 Register2 */
+ __IO uint32_t PRGBRST_DATA1_3; /**< Program Burst Data1 Register3 */
+ __IO uint32_t PRGBRST_DATA2_0; /**< Program Burst Data2 Register0 */
+ __IO uint32_t PRGBRST_DATA2_1; /**< Program Burst Data2 Register1 */
+ __IO uint32_t PRGBRST_DATA2_2; /**< Program Burst Data2 Register2 */
+ __IO uint32_t PRGBRST_DATA2_3; /**< Program Burst Data2 Register3 */
+ __IO uint32_t PRGBRST_DATA3_0; /**< Program Burst Data3 Register0 */
+ __IO uint32_t PRGBRST_DATA3_1; /**< Program Burst Data3 Register1 */
+ __IO uint32_t PRGBRST_DATA3_2; /**< Program Burst Data3 Register2 */
+ __IO uint32_t PRGBRST_DATA3_3; /**< Program Burst Data3 Register3 */
+ __IO uint32_t ERASE_CTLSTAT; /**< Erase Control and Status Register */
+ __IO uint32_t ERASE_SECTADDR; /**< Erase Sector Address Register */
+ uint32_t RESERVED5[2];
+ __IO uint32_t BANK0_INFO_WEPROT; /**< Information Memory Bank0 Write/Erase Protection Register */
+ __IO uint32_t BANK0_MAIN_WEPROT; /**< Main Memory Bank0 Write/Erase Protection Register */
+ uint32_t RESERVED6[2];
+ __IO uint32_t BANK1_INFO_WEPROT; /**< Information Memory Bank1 Write/Erase Protection Register */
+ __IO uint32_t BANK1_MAIN_WEPROT; /**< Main Memory Bank1 Write/Erase Protection Register */
+ uint32_t RESERVED7[2];
+ __IO uint32_t BMRK_CTLSTAT; /**< Benchmark Control and Status Register */
+ __IO uint32_t BMRK_IFETCH; /**< Benchmark Instruction Fetch Count Register */
+ __IO uint32_t BMRK_DREAD; /**< Benchmark Data Read Count Register */
+ __IO uint32_t BMRK_CMP; /**< Benchmark Count Compare Register */
+ uint32_t RESERVED8[4];
+ __IO uint32_t IFG; /**< Interrupt Flag Register */
+ __IO uint32_t IE; /**< Interrupt Enable Register */
+ __IO uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
+ __IO uint32_t SETIFG; /**< Set Interrupt Flag Register */
+ __I uint32_t READ_TIMCTL; /**< Read Timing Control Register */
+ __I uint32_t READMARGIN_TIMCTL; /**< Read Margin Timing Control Register */
+ __I uint32_t PRGVER_TIMCTL; /**< Program Verify Timing Control Register */
+ __I uint32_t ERSVER_TIMCTL; /**< Erase Verify Timing Control Register */
+ __I uint32_t LKGVER_TIMCTL; /**< Leakage Verify Timing Control Register */
+ __I uint32_t PROGRAM_TIMCTL; /**< Program Timing Control Register */
+ __I uint32_t ERASE_TIMCTL; /**< Erase Timing Control Register */
+ __I uint32_t MASSERASE_TIMCTL; /**< Mass Erase Timing Control Register */
+ __I uint32_t BURSTPRG_TIMCTL; /**< Burst Program Timing Control Register */
} FLCTL_Type;
+/*@}*/ /* end of group FLCTL */
-//*****************************************************************************
-// PCM Registers
-//*****************************************************************************
+
+/******************************************************************************
+* PCM Registers
+******************************************************************************/
+/** @addtogroup PCM MSP432P401R (PCM)
+ @{
+*/
typedef struct {
- union { /* PCMCTL0 Register */
- __IO uint32_t r;
- struct { /* PCMCTL0 Bits */
- __IO uint32_t bAMR : 4; /* Active Mode Request */
- __IO uint32_t bLPMR : 4; /* Low Power Mode Request */
- __I uint32_t bCPM : 6; /* Current Power Mode */
- __I uint32_t bRESERVED0 : 2; /* Reserved */
- __IO uint32_t bKEY : 16; /* PCM key */
- } b;
- } rCTL0;
- union { /* PCMCTL1 Register */
- __IO uint32_t r;
- struct { /* PCMCTL1 Bits */
- __IO uint32_t bLOCKLPM5 : 1; /* Lock LPM5 */
- __IO uint32_t bLOCKBKUP : 1; /* Lock Backup */
- __IO uint32_t bFORCE_LPM_ENTRY : 1; /* Force LPM entry */
- __I uint32_t bRESERVED0 : 5; /* Reserved */
- __IO uint32_t bPMR_BUSY : 1; /* Power mode request busy flag */
- __I uint32_t bRESERVED1 : 7; /* Reserved */
- __IO uint32_t bKEY : 16; /* PCM key */
- } b;
- } rCTL1;
- union { /* PCMIE Register */
- __IO uint32_t r;
- struct { /* PCMIE Bits */
- __IO uint32_t bLPM_INVALID_TR_IE : 1; /* LPM invalid transition interrupt enable */
- __IO uint32_t bLPM_INVALID_CLK_IE : 1; /* LPM invalid clock interrupt enable */
- __IO uint32_t bAM_INVALID_TR_IE : 1; /* Active mode invalid transition interrupt enable */
- __I uint32_t bRESERVED0 : 3; /* Reserved */
- __IO uint32_t bDCDC_ERROR_IE : 1; /* DC-DC error interrupt enable */
- __I uint32_t bRESERVED1 : 25; /* Reserved */
- } b;
- } rIE;
- union { /* PCMIFG Register */
- __I uint32_t r;
- struct { /* PCMIFG Bits */
- __I uint32_t bLPM_INVALID_TR_IFG : 1; /* LPM invalid transition flag */
- __I uint32_t bLPM_INVALID_CLK_IFG : 1; /* LPM invalid clock flag */
- __I uint32_t bAM_INVALID_TR_IFG : 1; /* Active mode invalid transition flag */
- __I uint32_t bRESERVED0 : 3; /* Reserved */
- __I uint32_t bDCDC_ERROR_IFG : 1; /* DC-DC error flag */
- __I uint32_t bRESERVED1 : 25; /* Reserved */
- } b;
- } rIFG;
- union { /* PCMCLRIFG Register */
- __O uint32_t r;
- struct { /* PCMCLRIFG Bits */
- __O uint32_t bCLR_LPM_INVALID_TR_IFG : 1; /* Clear LPM invalid transition flag */
- __O uint32_t bCLR_LPM_INVALID_CLK_IFG : 1; /* Clear LPM invalid clock flag */
- __O uint32_t bCLR_AM_INVALID_TR_IFG : 1; /* Clear active mode invalid transition flag */
- __O uint32_t bRESERVED0 : 3; /* Reserved */
- __O uint32_t bCLR_DCDC_ERROR_IFG : 1; /* Clear DC-DC error flag */
- __O uint32_t bRESERVED1 : 25; /* Reserved */
- } b;
- } rCLRIFG;
+ __IO uint32_t CTL0; /**< Control 0 Register */
+ __IO uint32_t CTL1; /**< Control 1 Register */
+ __IO uint32_t IE; /**< Interrupt Enable Register */
+ __I uint32_t IFG; /**< Interrupt Flag Register */
+ __O uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
} PCM_Type;
+/*@}*/ /* end of group PCM */
-//*****************************************************************************
-// PMAP Registers
-//*****************************************************************************
+/******************************************************************************
+* PMAP Registers
+******************************************************************************/
+/** @addtogroup PMAP MSP432P401R (PMAP)
+ @{
+*/
typedef struct {
- __IO uint16_t rKEYID; /* Port Mapping Key Register */
- union { /* PMAPCTL Register */
- __IO uint16_t r;
- struct { /* PMAPCTL Bits */
- __I uint16_t bLOCKED : 1; /* Port mapping lock bit */
- __IO uint16_t bPRECFG : 1; /* Port mapping reconfiguration control bit */
- __I uint16_t bRESERVED0 : 14; /* Reserved */
- } b;
- } rCTL;
- uint8_t RESERVED0[4];
- __IO uint16_t rP1MAP01; /* Port mapping register, P1.0 and P1.1 */
- __IO uint16_t rP1MAP23; /* Port mapping register, P1.2 and P1.3 */
- __IO uint16_t rP1MAP45; /* Port mapping register, P1.4 and P1.5 */
- __IO uint16_t rP1MAP67; /* Port mapping register, P1.6 and P1.7 */
- __IO uint16_t rP2MAP01; /* Port mapping register, P2.0 and P2.1 */
- __IO uint16_t rP2MAP23; /* Port mapping register, P2.2 and P2.3 */
- __IO uint16_t rP2MAP45; /* Port mapping register, P2.4 and P2.5 */
- __IO uint16_t rP2MAP67; /* Port mapping register, P2.6 and P2.7 */
- __IO uint16_t rP3MAP01; /* Port mapping register, P3.0 and P3.1 */
- __IO uint16_t rP3MAP23; /* Port mapping register, P3.2 and P3.3 */
- __IO uint16_t rP3MAP45; /* Port mapping register, P3.4 and P3.5 */
- __IO uint16_t rP3MAP67; /* Port mapping register, P3.6 and P3.7 */
- __IO uint16_t rP4MAP01; /* Port mapping register, P4.0 and P4.1 */
- __IO uint16_t rP4MAP23; /* Port mapping register, P4.2 and P4.3 */
- __IO uint16_t rP4MAP45; /* Port mapping register, P4.4 and P4.5 */
- __IO uint16_t rP4MAP67; /* Port mapping register, P4.6 and P4.7 */
- __IO uint16_t rP5MAP01; /* Port mapping register, P5.0 and P5.1 */
- __IO uint16_t rP5MAP23; /* Port mapping register, P5.2 and P5.3 */
- __IO uint16_t rP5MAP45; /* Port mapping register, P5.4 and P5.5 */
- __IO uint16_t rP5MAP67; /* Port mapping register, P5.6 and P5.7 */
- __IO uint16_t rP6MAP01; /* Port mapping register, P6.0 and P6.1 */
- __IO uint16_t rP6MAP23; /* Port mapping register, P6.2 and P6.3 */
- __IO uint16_t rP6MAP45; /* Port mapping register, P6.4 and P6.5 */
- __IO uint16_t rP6MAP67; /* Port mapping register, P6.6 and P6.7 */
- __IO uint16_t rP7MAP01; /* Port mapping register, P7.0 and P7.1 */
- __IO uint16_t rP7MAP23; /* Port mapping register, P7.2 and P7.3 */
- __IO uint16_t rP7MAP45; /* Port mapping register, P7.4 and P7.5 */
- __IO uint16_t rP7MAP67; /* Port mapping register, P7.6 and P7.7 */
-} PMAP_Type;
+ __IO uint16_t KEYID;
+ __IO uint16_t CTL;
+} PMAP_COMMON_Type;
-
-//*****************************************************************************
-// PSS Registers
-//*****************************************************************************
typedef struct {
- union { /* PSSKEY Register */
- __IO uint32_t r;
- struct { /* PSSKEY Bits */
- __IO uint32_t bKEY : 16; /* PSS control key */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rKEY;
- union { /* PSSCTL0 Register */
- __IO uint32_t r;
- struct { /* PSSCTL0 Bits */
- __IO uint32_t bSVSMHOFF : 1; /* SVSM high-side off */
- __IO uint32_t bSVSMHLP : 1; /* SVSM high-side low power normal performance mode */
- __IO uint32_t bSVSMHS : 1; /* Supply supervisor or monitor selection for the high-side */
- __IO uint32_t bSVSMHTH : 3; /* SVSM high-side reset voltage level */
- __IO uint32_t bSVMHOE : 1; /* SVSM high-side output enable */
- __IO uint32_t bSVMHOUTPOLAL : 1; /* SVMHOUT pin polarity active low */
- __IO uint32_t bSVSLOFF : 1; /* SVS low-side off */
- __IO uint32_t bSVSLLP : 1; /* SVS low-side low power normal performance mode */
- __IO uint32_t bDCDC_FORCE : 1; /* Disables automatic supply voltage detection */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bVCORETRAN : 2; /* Controls VCORE Level Transition time */
- __I uint32_t bRESERVED1 : 18; /* Reserved */
- } b;
- } rCTL0;
- union { /* PSSCTL1 Register */
- __IO uint32_t r;
- struct { /* PSSCTL1 Bits */
- __IO uint32_t bDOCMON : 1; /* Turns the DOCM module on or off */
- __IO uint32_t bDOCMSAMP : 1; /* DOCM sample current */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bDOCMCM : 6; /* Controls current mirrors in DOCM for conversion */
- __I uint32_t bRESERVED1 : 23; /* Reserved */
- } b;
- } rCTL1;
- union { /* PSSCTL2 Register */
- __I uint32_t r;
- struct { /* PSSCTL2 Bits */
- __I uint32_t bDOCMOUT : 6; /* DOCM comparator output */
- __I uint32_t bRESERVED0 : 26; /* Reserved */
- } b;
- } rCTL2;
- uint8_t RESERVED0[36];
- union { /* PSSIE Register */
- __IO uint32_t r;
- struct { /* PSSIE Bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bSVSMHIE : 1; /* High-side SVSM interrupt enable */
- __I uint32_t bRESERVED1 : 30; /* Reserved */
- } b;
- } rIE;
- union { /* PSSIFG Register */
- __I uint32_t r;
- struct { /* PSSIFG Bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __I uint32_t bSVSMHIFG : 1; /* High-side SVSM interrupt flag */
- __I uint32_t bRESERVED1 : 30; /* Reserved */
- } b;
- } rIFG;
- union { /* PSSCLRIFG Register */
- __IO uint32_t r;
- struct { /* PSSCLRIFG Bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __O uint32_t bCLRSVSMHIFG : 1; /* SVSMH clear interrupt flag */
- __I uint32_t bRESERVED1 : 30; /* Reserved */
- } b;
- } rCLRIFG;
+ union {
+ __IO uint16_t PMAP_REGISTER[4];
+ struct {
+ __IO uint8_t PMAP_REGISTER0;
+ __IO uint8_t PMAP_REGISTER1;
+ __IO uint8_t PMAP_REGISTER2;
+ __IO uint8_t PMAP_REGISTER3;
+ __IO uint8_t PMAP_REGISTER4;
+ __IO uint8_t PMAP_REGISTER5;
+ __IO uint8_t PMAP_REGISTER6;
+ __IO uint8_t PMAP_REGISTER7;
+ };
+ };
+} PMAP_REGISTER_Type;
+
+/*@}*/ /* end of group PMAP */
+
+
+/******************************************************************************
+* PSS Registers
+******************************************************************************/
+/** @addtogroup PSS MSP432P401R (PSS)
+ @{
+*/
+typedef struct {
+ __IO uint32_t KEY; /**< Key Register */
+ __IO uint32_t CTL0; /**< Control 0 Register */
+ uint32_t RESERVED0[11];
+ __IO uint32_t IE; /**< Interrupt Enable Register */
+ __I uint32_t IFG; /**< Interrupt Flag Register */
+ __IO uint32_t CLRIFG; /**< Clear Interrupt Flag Register */
} PSS_Type;
+/*@}*/ /* end of group PSS */
-//*****************************************************************************
-// REF_A Registers
-//*****************************************************************************
+
+/******************************************************************************
+* REF_A Registers
+******************************************************************************/
+/** @addtogroup REF_A MSP432P401R (REF_A)
+ @{
+*/
typedef struct {
- union { /* REFCTL0 Register */
- __IO uint16_t r;
- struct { /* REFCTL0 Bits */
- __IO uint16_t bON : 1; /* Reference enable */
- __IO uint16_t bOUT : 1; /* Reference output buffer */
- __IO uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bTCOFF : 1; /* Temperature sensor disabled */
- __IO uint16_t bVSEL : 2; /* Reference voltage level select */
- __IO uint16_t bGENOT : 1; /* Reference generator one-time trigger */
- __IO uint16_t bBGOT : 1; /* Bandgap and bandgap buffer one-time trigger */
- __I uint16_t bGENACT : 1; /* Reference generator active */
- __I uint16_t bBGACT : 1; /* Reference bandgap active */
- __I uint16_t bGENBUSY : 1; /* Reference generator busy */
- __I uint16_t bBGMODE : 1; /* Bandgap mode */
- __I uint16_t bGENRDY : 1; /* Variable reference voltage ready status */
- __I uint16_t bBGRDY : 1; /* Buffered bandgap voltage ready status */
- __I uint16_t bRESERVED1 : 2; /* Reserved */
- } b;
- } rCTL0;
+ __IO uint16_t CTL0; /**< REF Control Register 0 */
} REF_A_Type;
+/*@}*/ /* end of group REF_A */
-//*****************************************************************************
-// RSTCTL Registers
-//*****************************************************************************
+
+/******************************************************************************
+* RSTCTL Registers
+******************************************************************************/
+/** @addtogroup RSTCTL MSP432P401R (RSTCTL)
+ @{
+*/
typedef struct {
- union { /* RSTCTL_RESET_REQ Register */
- __IO uint32_t r;
- struct { /* RSTCTL_RESET_REQ Bits */
- __O uint32_t bSOFT_REQ : 1; /* Soft Reset request */
- __O uint32_t bHARD_REQ : 1; /* Hard Reset request */
- __I uint32_t bRESERVED0 : 6; /* Reserved */
- __O uint32_t bRSTKEY : 8; /* Write key to unlock reset request bits */
- __I uint32_t bRESERVED1 : 16; /* Reserved */
- } b;
- } rRESET_REQ;
- union { /* RSTCTL_HARDRESET_STAT Register */
- __I uint32_t r;
- struct { /* RSTCTL_HARDRESET_STAT Bits */
- __I uint32_t bSRC0 : 1; /* Indicates that SRC0 was the source of the Hard Reset */
- __I uint32_t bSRC1 : 1; /* Indicates that SRC1 was the source of the Hard Reset */
- __I uint32_t bSRC2 : 1; /* Indicates that SRC2 was the source of the Hard Reset */
- __I uint32_t bSRC3 : 1; /* Indicates that SRC3 was the source of the Hard Reset */
- __I uint32_t bSRC4 : 1; /* Indicates that SRC4 was the source of the Hard Reset */
- __I uint32_t bSRC5 : 1; /* Indicates that SRC5 was the source of the Hard Reset */
- __I uint32_t bSRC6 : 1; /* Indicates that SRC6 was the source of the Hard Reset */
- __I uint32_t bSRC7 : 1; /* Indicates that SRC7 was the source of the Hard Reset */
- __I uint32_t bSRC8 : 1; /* Indicates that SRC8 was the source of the Hard Reset */
- __I uint32_t bSRC9 : 1; /* Indicates that SRC9 was the source of the Hard Reset */
- __I uint32_t bSRC10 : 1; /* Indicates that SRC10 was the source of the Hard Reset */
- __I uint32_t bSRC11 : 1; /* Indicates that SRC11 was the source of the Hard Reset */
- __I uint32_t bSRC12 : 1; /* Indicates that SRC12 was the source of the Hard Reset */
- __I uint32_t bSRC13 : 1; /* Indicates that SRC13 was the source of the Hard Reset */
- __I uint32_t bSRC14 : 1; /* Indicates that SRC14 was the source of the Hard Reset */
- __I uint32_t bSRC15 : 1; /* Indicates that SRC15 was the source of the Hard Reset */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rHARDRESET_STAT;
- union { /* RSTCTL_HARDRESET_CLR Register */
- __IO uint32_t r;
- struct { /* RSTCTL_HARDRESET_CLR Bits */
- __O uint32_t bSRC0 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC1 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC2 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC3 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC4 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC5 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC6 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC7 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC8 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC9 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC10 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC11 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC12 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC13 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC14 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
- __O uint32_t bSRC15 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rHARDRESET_CLR;
- union { /* RSTCTL_HARDRESET_SET Register */
- __IO uint32_t r;
- struct { /* RSTCTL_HARDRESET_SET Bits */
- __O uint32_t bSRC0 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC1 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC2 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC3 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC4 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC5 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC6 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC7 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC8 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC9 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC10 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC11 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC12 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC13 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC14 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __O uint32_t bSRC15 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rHARDRESET_SET;
- union { /* RSTCTL_SOFTRESET_STAT Register */
- __I uint32_t r;
- struct { /* RSTCTL_SOFTRESET_STAT Bits */
- __I uint32_t bSRC0 : 1; /* If 1, indicates that SRC0 was the source of the Soft Reset */
- __I uint32_t bSRC1 : 1; /* If 1, indicates that SRC1 was the source of the Soft Reset */
- __I uint32_t bSRC2 : 1; /* If 1, indicates that SRC2 was the source of the Soft Reset */
- __I uint32_t bSRC3 : 1; /* If 1, indicates that SRC3 was the source of the Soft Reset */
- __I uint32_t bSRC4 : 1; /* If 1, indicates that SRC4 was the source of the Soft Reset */
- __I uint32_t bSRC5 : 1; /* If 1, indicates that SRC5 was the source of the Soft Reset */
- __I uint32_t bSRC6 : 1; /* If 1, indicates that SRC6 was the source of the Soft Reset */
- __I uint32_t bSRC7 : 1; /* If 1, indicates that SRC7 was the source of the Soft Reset */
- __I uint32_t bSRC8 : 1; /* If 1, indicates that SRC8 was the source of the Soft Reset */
- __I uint32_t bSRC9 : 1; /* If 1, indicates that SRC9 was the source of the Soft Reset */
- __I uint32_t bSRC10 : 1; /* If 1, indicates that SRC10 was the source of the Soft Reset */
- __I uint32_t bSRC11 : 1; /* If 1, indicates that SRC11 was the source of the Soft Reset */
- __I uint32_t bSRC12 : 1; /* If 1, indicates that SRC12 was the source of the Soft Reset */
- __I uint32_t bSRC13 : 1; /* If 1, indicates that SRC13 was the source of the Soft Reset */
- __I uint32_t bSRC14 : 1; /* If 1, indicates that SRC14 was the source of the Soft Reset */
- __I uint32_t bSRC15 : 1; /* If 1, indicates that SRC15 was the source of the Soft Reset */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rSOFTRESET_STAT;
- union { /* RSTCTL_SOFTRESET_CLR Register */
- __IO uint32_t r;
- struct { /* RSTCTL_SOFTRESET_CLR Bits */
- __O uint32_t bSRC0 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC1 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC2 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC3 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC4 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC5 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC6 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC7 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC8 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC9 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC10 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC11 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC12 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC13 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC14 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __O uint32_t bSRC15 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rSOFTRESET_CLR;
- union { /* RSTCTL_SOFTRESET_SET Register */
- __IO uint32_t r;
- struct { /* RSTCTL_SOFTRESET_SET Bits */
- __O uint32_t bSRC0 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC1 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC2 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC3 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC4 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC5 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC6 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC7 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC8 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC9 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC10 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC11 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC12 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC13 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC14 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __O uint32_t bSRC15 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rSOFTRESET_SET;
- uint8_t RESERVED0[228];
- union { /* RSTCTL_PSSRESET_STAT Register */
- __I uint32_t r;
- struct { /* RSTCTL_PSSRESET_STAT Bits */
- __I uint32_t bSVSL : 1; /* Indicates if POR was caused by an SVSL trip condition in the PSS */
- __I uint32_t bSVSMH : 1; /* Indicates if POR was caused by an SVSMH trip condition int the PSS */
- __I uint32_t bBGREF : 1; /* Indicates if POR was caused by a BGREF not okay condition in the PSS */
- __I uint32_t bVCCDET : 1; /* Indicates if POR was caused by a VCCDET trip condition in the PSS */
- __I uint32_t bRESERVED0 : 28; /* Reserved */
- } b;
- } rPSSRESET_STAT;
- union { /* RSTCTL_PSSRESET_CLR Register */
- __IO uint32_t r;
- struct { /* RSTCTL_PSSRESET_CLR Bits */
- __O uint32_t bCLR : 1; /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rPSSRESET_CLR;
- union { /* RSTCTL_PCMRESET_STAT Register */
- __I uint32_t r;
- struct { /* RSTCTL_PCMRESET_STAT Bits */
- __I uint32_t bLPM35 : 1; /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */
- __I uint32_t bLPM45 : 1; /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */
- __I uint32_t bRESERVED0 : 30; /* Reserved */
- } b;
- } rPCMRESET_STAT;
- union { /* RSTCTL_PCMRESET_CLR Register */
- __IO uint32_t r;
- struct { /* RSTCTL_PCMRESET_CLR Bits */
- __O uint32_t bCLR : 1; /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rPCMRESET_CLR;
- union { /* RSTCTL_PINRESET_STAT Register */
- __I uint32_t r;
- struct { /* RSTCTL_PINRESET_STAT Bits */
- __I uint32_t bRSTNMI : 1; /* POR was caused by RSTn/NMI pin based reset event */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rPINRESET_STAT;
- union { /* RSTCTL_PINRESET_CLR Register */
- __IO uint32_t r;
- struct { /* RSTCTL_PINRESET_CLR Bits */
- __O uint32_t bCLR : 1; /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rPINRESET_CLR;
- union { /* RSTCTL_REBOOTRESET_STAT Register */
- __I uint32_t r;
- struct { /* RSTCTL_REBOOTRESET_STAT Bits */
- __I uint32_t bREBOOT : 1; /* Indicates if Reboot reset was caused by the SYSCTL module. */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rREBOOTRESET_STAT;
- union { /* RSTCTL_REBOOTRESET_CLR Register */
- __IO uint32_t r;
- struct { /* RSTCTL_REBOOTRESET_CLR Bits */
- __O uint32_t bCLR : 1; /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rREBOOTRESET_CLR;
+ __IO uint32_t RESET_REQ; /**< Reset Request Register */
+ __I uint32_t HARDRESET_STAT; /**< Hard Reset Status Register */
+ __IO uint32_t HARDRESET_CLR; /**< Hard Reset Status Clear Register */
+ __IO uint32_t HARDRESET_SET; /**< Hard Reset Status Set Register */
+ __I uint32_t SOFTRESET_STAT; /**< Soft Reset Status Register */
+ __IO uint32_t SOFTRESET_CLR; /**< Soft Reset Status Clear Register */
+ __IO uint32_t SOFTRESET_SET; /**< Soft Reset Status Set Register */
+ uint32_t RESERVED0[57];
+ __I uint32_t PSSRESET_STAT; /**< PSS Reset Status Register */
+ __IO uint32_t PSSRESET_CLR; /**< PSS Reset Status Clear Register */
+ __I uint32_t PCMRESET_STAT; /**< PCM Reset Status Register */
+ __IO uint32_t PCMRESET_CLR; /**< PCM Reset Status Clear Register */
+ __I uint32_t PINRESET_STAT; /**< Pin Reset Status Register */
+ __IO uint32_t PINRESET_CLR; /**< Pin Reset Status Clear Register */
+ __I uint32_t REBOOTRESET_STAT; /**< Reboot Reset Status Register */
+ __IO uint32_t REBOOTRESET_CLR; /**< Reboot Reset Status Clear Register */
+ __I uint32_t CSRESET_STAT; /**< CS Reset Status Register */
+ __IO uint32_t CSRESET_CLR; /**< CS Reset Status Clear Register */
} RSTCTL_Type;
+/*@}*/ /* end of group RSTCTL */
-//*****************************************************************************
-// RTC_C Registers
-//*****************************************************************************
+
+/******************************************************************************
+* RTC_C Registers
+******************************************************************************/
+/** @addtogroup RTC_C MSP432P401R (RTC_C)
+ @{
+*/
typedef struct {
- union { /* RTCCTL0 Register */
- __IO uint16_t r;
- struct { /* RTCCTL0 Bits */
- __IO uint16_t bRDYIFG : 1; /* Real-time clock ready interrupt flag */
- __IO uint16_t bAIFG : 1; /* Real-time clock alarm interrupt flag */
- __IO uint16_t bTEVIFG : 1; /* Real-time clock time event interrupt flag */
- __IO uint16_t bOFIFG : 1; /* 32-kHz crystal oscillator fault interrupt flag */
- __IO uint16_t bRDYIE : 1; /* Real-time clock ready interrupt enable */
- __IO uint16_t bAIE : 1; /* Real-time clock alarm interrupt enable */
- __IO uint16_t bTEVIE : 1; /* Real-time clock time event interrupt enable */
- __IO uint16_t bOFIE : 1; /* 32-kHz crystal oscillator fault interrupt enable */
- __IO uint16_t bKEY : 8; /* Real-time clock key */
- } b;
- } rCTL0;
- union { /* RTCCTL13 Register */
- __IO uint16_t r;
- struct { /* RTCCTL13 Bits */
- __IO uint16_t bTEV : 2; /* Real-time clock time event */
- __IO uint16_t bSSEL : 2; /* Real-time clock source select */
- __I uint16_t bRDY : 1; /* Real-time clock ready */
- __I uint16_t bMODE : 1; /* */
- __IO uint16_t bHOLD : 1; /* Real-time clock hold */
- __IO uint16_t bBCD : 1; /* Real-time clock BCD select */
- __IO uint16_t bCALF : 2; /* Real-time clock calibration frequency */
- __I uint16_t bRESERVED0 : 6; /* Reserved */
- } b;
- } rCTL13;
- union { /* RTCOCAL Register */
- __IO uint16_t r;
- struct { /* RTCOCAL Bits */
- __IO uint16_t bOCAL : 8; /* Real-time clock offset error calibration */
- __I uint16_t bRESERVED0 : 7; /* Reserved */
- __IO uint16_t bOCALS : 1; /* Real-time clock offset error calibration sign */
- } b;
- } rOCAL;
- union { /* RTCTCMP Register */
- __IO uint16_t r;
- struct { /* RTCTCMP Bits */
- __IO uint16_t bTCMP : 8; /* Real-time clock temperature compensation */
- __I uint16_t bRESERVED0 : 5; /* Reserved */
- __I uint16_t bTCOK : 1; /* Real-time clock temperature compensation write OK */
- __I uint16_t bTCRDY : 1; /* Real-time clock temperature compensation ready */
- __IO uint16_t bTCMPS : 1; /* Real-time clock temperature compensation sign */
- } b;
- } rTCMP;
- union { /* RTCPS0CTL Register */
- __IO uint16_t r;
- struct { /* RTCPS0CTL Bits */
- __IO uint16_t bRT0PSIFG : 1; /* Prescale timer 0 interrupt flag */
- __IO uint16_t bRT0PSIE : 1; /* Prescale timer 0 interrupt enable */
- __IO uint16_t bRT0IP : 3; /* Prescale timer 0 interrupt interval */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rPS0CTL;
- union { /* RTCPS1CTL Register */
- __IO uint16_t r;
- struct { /* RTCPS1CTL Bits */
- __IO uint16_t bRT1PSIFG : 1; /* Prescale timer 1 interrupt flag */
- __IO uint16_t bRT1PSIE : 1; /* Prescale timer 1 interrupt enable */
- __IO uint16_t bRT1IP : 3; /* Prescale timer 1 interrupt interval */
- __I uint16_t bRESERVED0 : 11; /* Reserved */
- } b;
- } rPS1CTL;
- union { /* RTCPS Register */
- __IO uint16_t r;
- struct { /* RTCPS Bits */
- __IO uint16_t bRT0PS : 8; /* Prescale timer 0 counter value */
- __IO uint16_t bRT1PS : 8; /* Prescale timer 1 counter value */
- } b;
- } rPS;
- __I uint16_t rIV; /* Real-Time Clock Interrupt Vector Register */
- union { /* RTCTIM0 Register */
- __IO uint16_t r;
- struct { /* RTCTIM0 Bits */
- __IO uint16_t bSEC : 6; /* Seconds (0 to 59) */
- __I uint16_t bRESERVED0 : 2; /* Reserved */
- __IO uint16_t bMIN : 6; /* Minutes (0 to 59) */
- __I uint16_t bRESERVED1 : 2; /* Reserved */
- } b;
- struct { /* RTCTIM0_BCD Bits */
- __IO uint16_t bSEC_LD : 4; /* Seconds ? low digit (0 to 9) */
- __IO uint16_t bSEC_HD : 3; /* Seconds ? high digit (0 to 5) */
- __I uint16_t bRESERVED : 1; /* Reserved */
- __IO uint16_t bMIN_LD : 4; /* Minutes ? low digit (0 to 9) */
- __IO uint16_t bMIN_HD : 3; /* Minutes ? high digit (0 to 5) */
- } a;
- } rTIM0;
- union { /* RTCTIM1 Register */
- __IO uint16_t r;
- struct { /* RTCTIM1 Bits */
- __IO uint16_t bHOUR : 5; /* Hours (0 to 23) */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
- __I uint16_t bRESERVED1 : 5; /* Reserved */
- } b;
- struct { /* RTCTIM1_BCD Bits */
- __IO uint16_t bHOUR_LD : 4; /* Hours ? low digit (0 to 9) */
- __IO uint16_t bHOUR_HD : 2; /* Hours ? high digit (0 to 2) */
- __I uint16_t bRESERVED : 2; /* Reserved */
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
- } a;
- } rTIM1;
- union { /* RTCDATE Register */
- __IO uint16_t r;
- struct { /* RTCDATE Bits */
- __IO uint16_t bDAY : 5; /* Day of month (1 to 28, 29, 30, 31) */
- __I uint16_t bRESERVED0 : 3; /* Reserved */
- __IO uint16_t bMON : 4; /* Month (1 to 12) */
- __I uint16_t bRESERVED1 : 4; /* Reserved */
- } b;
- struct { /* RTCDATE_BCD Bits */
- __IO uint16_t bDAY_LD : 4; /* Day of month ? low digit (0 to 9) */
- __IO uint16_t bDAY_HD : 2; /* Day of month ? high digit (0 to 3) */
- __I uint16_t bRESERVED : 2; /* Reserved */
- __IO uint16_t bMON_LD : 4; /* Month ? low digit (0 to 9) */
- __IO uint16_t bMON_HD : 1; /* Month ? high digit (0 or 1) */
- } a;
- } rDATE;
- union { /* RTCYEAR Register */
- __IO uint16_t r;
- struct { /* RTCYEAR Bits */
- __IO uint16_t bYEAR_LB : 8; /* Year ? low byte. Valid values for Year are 0 to 4095. */
- __IO uint16_t bYEAR_HB : 4; /* Year ? high byte. Valid values for Year are 0 to 4095. */
- __I uint16_t bRESERVED0 : 4; /* Reserved */
- } b;
- struct { /* RTCYEAR_BCD Bits */
- __IO uint16_t bYEAR : 4; /* Year ? lowest digit (0 to 9) */
- __IO uint16_t bDEC : 4; /* Decade (0 to 9) */
- __IO uint16_t bCENT_LD : 4; /* Century ? low digit (0 to 9) */
- __IO uint16_t bCENT_HD : 3; /* Century ? high digit (0 to 4) */
- __I uint16_t bRESERVED : 1; /* Reserved */
- } a;
- } rYEAR;
- union { /* RTCAMINHR Register */
- __IO uint16_t r;
- struct { /* RTCAMINHR Bits */
- __IO uint16_t bMIN : 6; /* Minutes (0 to 59) */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMINAE : 1; /* Alarm enable */
- __IO uint16_t bHOUR : 5; /* Hours (0 to 23) */
- __I uint16_t bRESERVED1 : 2; /* Reserved */
- __IO uint16_t bHOURAE : 1; /* Alarm enable */
- } b;
- struct { /* RTCAMINHR_BCD Bits */
- __IO uint16_t bMIN_LD : 4; /* Minutes ? low digit (0 to 9) */
- __IO uint16_t bMIN_HD : 3; /* Minutes ? high digit (0 to 5) */
- __IO uint16_t b : 1; /* Alarm enable */
- __IO uint16_t bHOUR_LD : 4; /* Hours ? low digit (0 to 9) */
- __IO uint16_t bHOUR_HD : 2; /* Hours ? high digit (0 to 2) */
- __I uint16_t bRESERVED : 1; /* Reserved */
- __IO uint16_t bHOURAE : 1; /* Alarm enable */
- } a;
- } rAMINHR;
- union { /* RTCADOWDAY Register */
- __IO uint16_t r;
- struct { /* RTCADOWDAY Bits */
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
- __I uint16_t bRESERVED0 : 4; /* Reserved */
- __IO uint16_t bDOWAE : 1; /* Alarm enable */
- __IO uint16_t bDAY : 5; /* Day of month (1 to 28, 29, 30, 31) */
- __I uint16_t bRESERVED1 : 2; /* Reserved */
- __IO uint16_t bDAYAE : 1; /* Alarm enable */
- } b;
- struct { /* RTCADOWDAY_BCD Bits */
- __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
- __I uint16_t bRESERVED : 4; /* Reserved */
- __IO uint16_t bDOWAE : 1; /* Alarm enable */
- __IO uint16_t bDAY_LD : 4; /* Day of month ? low digit (0 to 9) */
- __IO uint16_t bDAY_HD : 2; /* Day of month ? high digit (0 to 3) */
- __IO uint16_t bDAYAE : 1; /* Alarm enable */
- } a;
- } rADOWDAY;
- __IO uint16_t rBIN2BCD; /* Binary-to-BCD Conversion Register */
- __IO uint16_t rBCD2BIN; /* BCD-to-Binary Conversion Register */
+ __IO uint16_t CTL0; /**< RTCCTL0 Register */
+ __IO uint16_t CTL13; /**< RTCCTL13 Register */
+ __IO uint16_t OCAL; /**< RTCOCAL Register */
+ __IO uint16_t TCMP; /**< RTCTCMP Register */
+ __IO uint16_t PS0CTL; /**< Real-Time Clock Prescale Timer 0 Control Register */
+ __IO uint16_t PS1CTL; /**< Real-Time Clock Prescale Timer 1 Control Register */
+ __IO uint16_t PS; /**< Real-Time Clock Prescale Timer Counter Register */
+ __I uint16_t IV; /**< Real-Time Clock Interrupt Vector Register */
+ __IO uint16_t TIM0; /**< RTCTIM0 Register ? Hexadecimal Format */
+ __IO uint16_t TIM1; /**< Real-Time Clock Hour, Day of Week */
+ __IO uint16_t DATE; /**< RTCDATE - Hexadecimal Format */
+ __IO uint16_t YEAR; /**< RTCYEAR Register ? Hexadecimal Format */
+ __IO uint16_t AMINHR; /**< RTCMINHR - Hexadecimal Format */
+ __IO uint16_t ADOWDAY; /**< RTCADOWDAY - Hexadecimal Format */
+ __IO uint16_t BIN2BCD; /**< Binary-to-BCD Conversion Register */
+ __IO uint16_t BCD2BIN; /**< BCD-to-Binary Conversion Register */
} RTC_C_Type;
+/*@}*/ /* end of group RTC_C */
-//*****************************************************************************
-// SYSCTL Registers
-//*****************************************************************************
+/** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD)
+ @{
+*/
typedef struct {
- union { /* SYS_REBOOT_CTL Register */
- __IO uint32_t r;
- struct { /* SYS_REBOOT_CTL Bits */
- __IO uint32_t bREBOOT : 1; /* Write 1 initiates a Reboot of the device */
- __I uint32_t bRESERVED0 : 7; /* Reserved */
- __O uint32_t bWKEY : 8; /* Key to enable writes to bit 0 */
- __I uint32_t bRESERVED1 : 16; /* Reserved */
- } b;
- } rREBOOT_CTL;
- union { /* SYS_NMI_CTLSTAT Register */
- __IO uint32_t r;
- struct { /* SYS_NMI_CTLSTAT Bits */
- __IO uint32_t bCS_SRC : 1; /* CS interrupt as a source of NMI */
- __IO uint32_t bPSS_SRC : 1; /* PSS interrupt as a source of NMI */
- __IO uint32_t bPCM_SRC : 1; /* PCM interrupt as a source of NMI */
- __IO uint32_t bPIN_SRC : 1; /* */
- __I uint32_t bRESERVED0 : 12; /* Reserved */
- __I uint32_t bCS_FLG : 1; /* CS interrupt was the source of NMI */
- __I uint32_t bPSS_FLG : 1; /* PSS interrupt was the source of NMI */
- __I uint32_t bPCM_FLG : 1; /* PCM interrupt was the source of NMI */
- __IO uint32_t bPIN_FLG : 1; /* RSTn/NMI pin was the source of NMI */
- __I uint32_t bRESERVED1 : 12; /* Reserved */
- } b;
- } rNMI_CTLSTAT;
- union { /* SYS_WDTRESET_CTL Register */
- __IO uint32_t r;
- struct { /* SYS_WDTRESET_CTL Bits */
- __IO uint32_t bTIMEOUT : 1; /* WDT timeout reset type */
- __IO uint32_t bVIOLATION : 1; /* WDT password violation reset type */
- __I uint32_t bRESERVED0 : 30; /* Reserved */
- } b;
- } rWDTRESET_CTL;
- union { /* SYS_PERIHALT_CTL Register */
- __IO uint32_t r;
- struct { /* SYS_PERIHALT_CTL Bits */
- __IO uint32_t bT16_0 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bT16_1 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bT16_2 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bT16_3 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bT32_0 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUA0 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUA1 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUA2 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUA3 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUB0 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUB1 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUB2 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bEUB3 : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bADC : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bWDT : 1; /* Freezes IP operation when CPU is halted */
- __IO uint32_t bDMA : 1; /* Freezes IP operation when CPU is halted */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rPERIHALT_CTL;
- __I uint32_t rSRAM_SIZE; /* SRAM Size Register */
- union { /* SYS_SRAM_BANKEN Register */
- __IO uint32_t r;
- struct { /* SYS_SRAM_BANKEN Bits */
- __I uint32_t bBNK0_EN : 1; /* SRAM Bank0 enable */
- __IO uint32_t bBNK1_EN : 1; /* SRAM Bank1 enable */
- __IO uint32_t bBNK2_EN : 1; /* SRAM Bank1 enable */
- __IO uint32_t bBNK3_EN : 1; /* SRAM Bank1 enable */
- __IO uint32_t bBNK4_EN : 1; /* SRAM Bank1 enable */
- __IO uint32_t bBNK5_EN : 1; /* SRAM Bank1 enable */
- __IO uint32_t bBNK6_EN : 1; /* SRAM Bank1 enable */
- __IO uint32_t bBNK7_EN : 1; /* SRAM Bank1 enable */
- __I uint32_t bRESERVED0 : 8; /* Reserved */
- __I uint32_t bSRAM_RDY : 1; /* SRAM ready */
- __I uint32_t bRESERVED1 : 15; /* Reserved */
- } b;
- } rSRAM_BANKEN;
- union { /* SYS_SRAM_BANKRET Register */
- __IO uint32_t r;
- struct { /* SYS_SRAM_BANKRET Bits */
- __I uint32_t bBNK0_RET : 1; /* Bank0 retention */
- __IO uint32_t bBNK1_RET : 1; /* Bank1 retention */
- __IO uint32_t bBNK2_RET : 1; /* Bank2 retention */
- __IO uint32_t bBNK3_RET : 1; /* Bank3 retention */
- __IO uint32_t bBNK4_RET : 1; /* Bank4 retention */
- __IO uint32_t bBNK5_RET : 1; /* Bank5 retention */
- __IO uint32_t bBNK6_RET : 1; /* Bank6 retention */
- __IO uint32_t bBNK7_RET : 1; /* Bank7 retention */
- __I uint32_t bRESERVED0 : 8; /* Reserved */
- __I uint32_t bSRAM_RDY : 1; /* SRAM ready */
- __I uint32_t bRESERVED1 : 15; /* Reserved */
- } b;
- } rSRAM_BANKRET;
- uint8_t RESERVED0[4];
- __I uint32_t rFLASH_SIZE; /* Flash Size Register */
- uint8_t RESERVED1[12];
- union { /* SYS_DIO_GLTFLT_CTL Register */
- __IO uint32_t r;
- struct { /* SYS_DIO_GLTFLT_CTL Bits */
- __IO uint32_t bGLTCH_EN : 1; /* Glitch filter enable */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rDIO_GLTFLT_CTL;
- uint8_t RESERVED2[12];
- union { /* SYS_SECDATA_UNLOCK Register */
- __IO uint32_t r;
- struct { /* SYS_SECDATA_UNLOCK Bits */
- __IO uint32_t bUNLKEY : 16; /* Unlock key */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rSECDATA_UNLOCK;
- uint8_t RESERVED3[4028];
- union { /* SYS_MASTER_UNLOCK Register */
- __IO uint32_t r;
- struct { /* SYS_MASTER_UNLOCK Bits */
- __IO uint32_t bUNLKEY : 16; /* Unlock Key */
- __I uint32_t bRESERVED0 : 16; /* Reserved */
- } b;
- } rMASTER_UNLOCK;
- __IO uint32_t rBOOTOVER_REQ0; /* Boot Override Request Register */
- __IO uint32_t rBOOTOVER_REQ1; /* Boot Override Request Register */
- __IO uint32_t rBOOTOVER_ACK; /* Boot Override Acknowledge Register */
- union { /* SYS_RESET_REQ Register */
- __IO uint32_t r;
- struct { /* SYS_RESET_REQ Bits */
- __O uint32_t bPOR : 1; /* Generate POR */
- __O uint32_t bREBOOT : 1; /* Generate Reboot_Reset */
- __I uint32_t bRESERVED0 : 6; /* Reserved */
- __O uint32_t bWKEY : 8; /* Write key */
- __I uint32_t bRESERVED1 : 16; /* Reserved */
- } b;
- } rRESET_REQ;
- union { /* SYS_RESET_STATOVER Register */
- __IO uint32_t r;
- struct { /* SYS_RESET_STATOVER Bits */
- __I uint32_t bSOFT : 1; /* Indicates if SOFT Reset is active */
- __I uint32_t bHARD : 1; /* Indicates if HARD Reset is active */
- __I uint32_t bREBOOT : 1; /* Indicates if Reboot Reset is active */
- __I uint32_t bRESERVED0 : 5; /* Reserved */
- __IO uint32_t bSOFT_OVER : 1; /* SOFT_Reset overwrite request */
- __IO uint32_t bHARD_OVER : 1; /* HARD_Reset overwrite request */
- __IO uint32_t bRBT_OVER : 1; /* Reboot Reset overwrite request */
- __I uint32_t bRESERVED1 : 21; /* Reserved */
- } b;
- } rRESET_STATOVER;
- uint8_t RESERVED4[8];
- union { /* SYS_SYSTEM_STAT Register */
- __I uint32_t r;
- struct { /* SYS_SYSTEM_STAT Bits */
- __I uint32_t bRESERVED0 : 3; /* Reserved */
- __I uint32_t bDBG_SEC_ACT : 1; /* Debug Security active */
- __I uint32_t bJTAG_SWD_LOCK_ACT : 1; /* Indicates if JTAG and SWD Lock is active */
- __I uint32_t bIP_PROT_ACT : 1; /* Indicates if IP protection is active */
- __I uint32_t bRESERVED1 : 26; /* Reserved */
- } b;
- } rSYSTEM_STAT;
+ uint16_t RESERVED0[8];
+ __IO uint16_t TIM0; /**< RTCTIM0 Register ? BCD Format */
+ __IO uint16_t TIM1; /**< RTCTIM1 Register ? BCD Format */
+ __IO uint16_t DATE; /**< Real-Time Clock Date - BCD Format */
+ __IO uint16_t YEAR; /**< RTCYEAR Register ? BCD Format */
+ __IO uint16_t AMINHR; /**< RTCMINHR - BCD Format */
+ __IO uint16_t ADOWDAY; /**< RTCADOWDAY - BCD Format */
+} RTC_C_BCD_Type;
+
+/*@}*/ /* end of group RTC_C_BCD */
+
+
+/******************************************************************************
+* SYSCTL Registers
+******************************************************************************/
+/** @addtogroup SYSCTL MSP432P401R (SYSCTL)
+ @{
+*/
+typedef struct {
+ __IO uint32_t REBOOT_CTL; /**< Reboot Control Register */
+ __IO uint32_t NMI_CTLSTAT; /**< NMI Control and Status Register */
+ __IO uint32_t WDTRESET_CTL; /**< Watchdog Reset Control Register */
+ __IO uint32_t PERIHALT_CTL; /**< Peripheral Halt Control Register */
+ __I uint32_t SRAM_SIZE; /**< SRAM Size Register */
+ __IO uint32_t SRAM_BANKEN; /**< SRAM Bank Enable Register */
+ __IO uint32_t SRAM_BANKRET; /**< SRAM Bank Retention Control Register */
+ uint32_t RESERVED0;
+ __I uint32_t FLASH_SIZE; /**< Flash Size Register */
+ uint32_t RESERVED1[3];
+ __IO uint32_t DIO_GLTFLT_CTL; /**< Digital I/O Glitch Filter Control Register */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SECDATA_UNLOCK; /**< IP Protected Secure Zone Data Access Unlock Register */
+ uint32_t RESERVED3[175];
+ __IO uint32_t CSYS_MASTER_UNLOCK; /**< Master Unlock Register */
+ __IO uint32_t BOOT_CTL; /**< Boot Control Register */
+ uint32_t RESERVED4[2];
+ __IO uint32_t SEC_CTL; /**< Security Control Register */
+ uint32_t RESERVED5[3];
+ __IO uint32_t SEC_STARTADDR0; /**< Security Zone 0 Start Address Register */
+ __IO uint32_t SEC_STARTADDR1; /**< Security Zone 1 Start Address Register */
+ __IO uint32_t SEC_STARTADDR2; /**< Security Zone 2 Start Address Register */
+ __IO uint32_t SEC_STARTADDR3; /**< Security Zone 3 Start Address Register */
+ __IO uint32_t SEC_SIZE0; /**< Security Zone 0 Size Register */
+ __IO uint32_t SEC_SIZE1; /**< Security Zone 1 Size Register */
+ __IO uint32_t SEC_SIZE2; /**< Security Zone 2 Size Register */
+ __IO uint32_t SEC_SIZE3; /**< Security Zone 3 Size Register */
+ __IO uint32_t ETW_CTL; /**< ETW Control Register */
+ __IO uint32_t FLASH_SIZECFG; /**< Flash Size Configuration Register */
+ __IO uint32_t SRAM_SIZECFG; /**< SRAM Size Configuration Register */
+ __IO uint32_t SRAM_NUMBANK; /**< SRAM NUM BANK Configuration Register */
+ __IO uint32_t TIMER_CFG; /**< Timer Configuration Register */
+ __IO uint32_t EUSCI_CFG; /**< eUSCI Configuration Register */
+ __IO uint32_t ADC_CFG; /**< ADC Configuration Register */
+ __IO uint32_t XTAL_CFG; /**< Crystal Oscillator Configuration Register */
+ __IO uint32_t BOC_CFG; /**< Bond Out Configuration Register */
} SYSCTL_Type;
-
-//*****************************************************************************
-// TIMER32 Registers
-//*****************************************************************************
typedef struct {
- __IO uint32_t rLOAD1; /* Timer 1 Load Register */
- __I uint32_t rVALUE1; /* Timer 1 Current Value Register */
- union { /* T32CONTROL1 Register */
- __IO uint32_t r;
- struct { /* T32CONTROL1 Bits */
- __IO uint32_t bONESHOT : 1; /* Selects one-shot or wrapping counter mode */
- __IO uint32_t bSIZE : 1; /* Selects 16 or 32 bit counter operation */
- __IO uint32_t bPRESCALE : 2; /* Prescale bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bIE : 1; /* Interrupt enable bit */
- __IO uint32_t bMODE : 1; /* Mode bit */
- __IO uint32_t bENABLE : 1; /* */
- __I uint32_t bRESERVED1 : 24; /* Reserved */
- } b;
- } rCONTROL1;
- __O uint32_t rINTCLR1; /* Timer 1 Interrupt Clear Register */
- union { /* T32RIS1 Register */
- __I uint32_t r;
- struct { /* T32RIS1 Bits */
- __I uint32_t bRAW_IFG : 1; /* Raw interrupt status */
- __I uint32_t b : 31; /* */
- } b;
- } rRIS1;
- union { /* T32MIS1 Register */
- __I uint32_t r;
- struct { /* T32MIS1 Bits */
- __I uint32_t b : 1; /* Enabled interrupt status */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rMIS1;
- __IO uint32_t rBGLOAD1; /* Timer 1 Background Load Register */
- uint8_t RESERVED0[4];
- __IO uint32_t rLOAD2; /* Timer 2 Load Register */
- __I uint32_t rVALUE2; /* Timer 2 Current Value Register */
- union { /* T32CONTROL2 Register */
- __IO uint32_t r;
- struct { /* T32CONTROL2 Bits */
- __IO uint32_t bONESHOT : 1; /* Selects one-shot or wrapping counter mode */
- __IO uint32_t bSIZE : 1; /* Selects 16 or 32 bit counter operation */
- __IO uint32_t bPRESCALE : 2; /* Prescale bits */
- __I uint32_t bRESERVED0 : 1; /* Reserved */
- __IO uint32_t bIE : 1; /* Interrupt enable bit */
- __IO uint32_t bMODE : 1; /* Mode bit */
- __IO uint32_t bENABLE : 1; /* */
- __I uint32_t bRESERVED1 : 24; /* Reserved */
- } b;
- } rCONTROL2;
- __O uint32_t rINTCLR2; /* Timer 2 Interrupt Clear Register */
- union { /* T32RIS2 Register */
- __I uint32_t r;
- struct { /* T32RIS2 Bits */
- __I uint32_t bRAW_IFG : 1; /* Raw interrupt status */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rRIS2;
- union { /* T32MIS2 Register */
- __I uint32_t r;
- struct { /* T32MIS2 Bits */
- __I uint32_t bIFG : 1; /* Enabled interrupt status */
- __I uint32_t bRESERVED0 : 31; /* Reserved */
- } b;
- } rMIS2;
- __IO uint32_t rBGLOAD2; /* Timer 2 Background Load Register */
- uint8_t RESERVED1[3780];
- union { /* T32ITCR Register */
- __IO uint32_t r;
- struct { /* T32ITCR Bits */
- __IO uint32_t bTEST_EN : 1; /* Test mode */
- __I uint32_t b : 31; /* */
- } b;
- } rITCR;
- union { /* T32ITOP Register */
- __IO uint32_t r;
- struct { /* T32ITOP Bits */
- __O uint32_t bTIMINT1_VAL : 1; /* Value output on TIMINT1 */
- __O uint32_t bTIMINT2_VAL : 1; /* Value output on TIMINT2 */
- __I uint32_t bRESERVED0 : 30; /* Reserved */
- } b;
- } rITOP;
-} TIMER32_Type;
+ __IO uint32_t MASTER_UNLOCK; /**< Master Unlock Register */
+ __IO uint32_t BOOTOVER_REQ[2]; /**< Boot Override Request Register */
+ __IO uint32_t BOOTOVER_ACK; /**< Boot Override Acknowledge Register */
+ __IO uint32_t RESET_REQ; /**< Reset Request Register */
+ __IO uint32_t RESET_STATOVER; /**< Reset Status and Override Register */
+ uint32_t RESERVED7[2];
+ __I uint32_t SYSTEM_STAT; /**< System Status Register */
+} SYSCTL_Boot_Type;
+
+/*@}*/ /* end of group SYSCTL */
-//*****************************************************************************
-// TIMER_A0 Registers
-//*****************************************************************************
+/******************************************************************************
+* Timer32 Registers
+******************************************************************************/
+/** @addtogroup Timer32 MSP432P401R (Timer32)
+ @{
+*/
typedef struct {
- union { /* TA0CTL Register */
- __IO uint16_t r;
- struct { /* TA0CTL Bits */
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */
- __IO uint16_t bCLR : 1; /* TimerA clear */
- __IO uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMC : 2; /* Mode control */
- __IO uint16_t bID : 2; /* Input divider */
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */
- __IO uint16_t bRESERVED1 : 6; /* Reserved */
- } b;
- } rCTL;
- union { /* TA0CCTL0 Register */
- __IO uint16_t r;
- struct { /* TA0CCTL0 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL0;
- union { /* TA0CCTL1 Register */
- __IO uint16_t r;
- struct { /* TA0CCTL1 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL1;
- union { /* TA0CCTL2 Register */
- __IO uint16_t r;
- struct { /* TA0CCTL2 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL2;
- union { /* TA0CCTL3 Register */
- __IO uint16_t r;
- struct { /* TA0CCTL3 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL3;
- union { /* TA0CCTL4 Register */
- __IO uint16_t r;
- struct { /* TA0CCTL4 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL4;
- union { /* TA0CCTL5 Register */
- __IO uint16_t r;
- struct { /* TA0CCTL5 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL5;
- union { /* TA0CCTL6 Register */
- __IO uint16_t r;
- struct { /* TA0CCTL6 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL6;
- __IO uint16_t rR; /* TimerA register */
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
- union { /* TA0EX0 Register */
- __IO uint16_t r;
- struct { /* TA0EX0 Bits */
- __IO uint16_t bIDEX : 3; /* Input divider expansion */
- __I uint16_t bRESERVED0 : 13; /* Reserved */
- } b;
- } rEX0;
- uint8_t RESERVED0[12];
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
-} TIMER_A0_Type;
+ __IO uint32_t LOAD; /**< Timer 1 Load Register */
+ __I uint32_t VALUE; /**< Timer 1 Current Value Register */
+ __IO uint32_t CONTROL; /**< Timer 1 Timer Control Register */
+ __O uint32_t INTCLR; /**< Timer 1 Interrupt Clear Register */
+ __I uint32_t RIS; /**< Timer 1 Raw Interrupt Status Register */
+ __I uint32_t MIS; /**< Timer 1 Interrupt Status Register */
+ __IO uint32_t BGLOAD; /**< Timer 1 Background Load Register */
+} Timer32_Type;
+
+/*@}*/ /* end of group Timer32 */
-//*****************************************************************************
-// TIMER_A1 Registers
-//*****************************************************************************
+/******************************************************************************
+* Timer_A Registers
+******************************************************************************/
+/** @addtogroup Timer_A MSP432P401R (Timer_A)
+ @{
+*/
typedef struct {
- union { /* TA1CTL Register */
- __IO uint16_t r;
- struct { /* TA1CTL Bits */
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */
- __IO uint16_t bCLR : 1; /* TimerA clear */
- __IO uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMC : 2; /* Mode control */
- __IO uint16_t bID : 2; /* Input divider */
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */
- __IO uint16_t bRESERVED1 : 6; /* Reserved */
- } b;
- } rCTL;
- union { /* TA1CCTL0 Register */
- __IO uint16_t r;
- struct { /* TA1CCTL0 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL0;
- union { /* TA1CCTL1 Register */
- __IO uint16_t r;
- struct { /* TA1CCTL1 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL1;
- union { /* TA1CCTL2 Register */
- __IO uint16_t r;
- struct { /* TA1CCTL2 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL2;
- union { /* TA1CCTL3 Register */
- __IO uint16_t r;
- struct { /* TA1CCTL3 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL3;
- union { /* TA1CCTL4 Register */
- __IO uint16_t r;
- struct { /* TA1CCTL4 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL4;
- union { /* TA1CCTL5 Register */
- __IO uint16_t r;
- struct { /* TA1CCTL5 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL5;
- union { /* TA1CCTL6 Register */
- __IO uint16_t r;
- struct { /* TA1CCTL6 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL6;
- __IO uint16_t rR; /* TimerA register */
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
- union { /* TA1EX0 Register */
- __IO uint16_t r;
- struct { /* TA1EX0 Bits */
- __IO uint16_t bIDEX : 3; /* Input divider expansion */
- __I uint16_t bRESERVED0 : 13; /* Reserved */
- } b;
- } rEX0;
- uint8_t RESERVED0[12];
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
-} TIMER_A1_Type;
+ __IO uint16_t CTL; /**< TimerAx Control Register */
+ __IO uint16_t CCTL[7]; /**< Timer_A Capture/Compare Control Register */
+ __IO uint16_t R; /**< TimerA register */
+ __IO uint16_t CCR[7]; /**< Timer_A Capture/Compare Register */
+ __IO uint16_t EX0; /**< TimerAx Expansion 0 Register */
+ uint16_t RESERVED0[6];
+ __I uint16_t IV; /**< TimerAx Interrupt Vector Register */
+} Timer_A_Type;
+
+/*@}*/ /* end of group Timer_A */
-//*****************************************************************************
-// TIMER_A2 Registers
-//*****************************************************************************
+/******************************************************************************
+* TLV Registers
+******************************************************************************/
+/** @addtogroup TLV MSP432P401R (TLV)
+ @{
+*/
typedef struct {
- union { /* TA2CTL Register */
- __IO uint16_t r;
- struct { /* TA2CTL Bits */
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */
- __IO uint16_t bCLR : 1; /* TimerA clear */
- __IO uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMC : 2; /* Mode control */
- __IO uint16_t bID : 2; /* Input divider */
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */
- __IO uint16_t bRESERVED1 : 6; /* Reserved */
- } b;
- } rCTL;
- union { /* TA2CCTL0 Register */
- __IO uint16_t r;
- struct { /* TA2CCTL0 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL0;
- union { /* TA2CCTL1 Register */
- __IO uint16_t r;
- struct { /* TA2CCTL1 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL1;
- union { /* TA2CCTL2 Register */
- __IO uint16_t r;
- struct { /* TA2CCTL2 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL2;
- union { /* TA2CCTL3 Register */
- __IO uint16_t r;
- struct { /* TA2CCTL3 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL3;
- union { /* TA2CCTL4 Register */
- __IO uint16_t r;
- struct { /* TA2CCTL4 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL4;
- union { /* TA2CCTL5 Register */
- __IO uint16_t r;
- struct { /* TA2CCTL5 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL5;
- union { /* TA2CCTL6 Register */
- __IO uint16_t r;
- struct { /* TA2CCTL6 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL6;
- __IO uint16_t rR; /* TimerA register */
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
- union { /* TA2EX0 Register */
- __IO uint16_t r;
- struct { /* TA2EX0 Bits */
- __IO uint16_t bIDEX : 3; /* Input divider expansion */
- __I uint16_t bRESERVED0 : 13; /* Reserved */
- } b;
- } rEX0;
- uint8_t RESERVED0[12];
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
-} TIMER_A2_Type;
-
-
-//*****************************************************************************
-// TIMER_A3 Registers
-//*****************************************************************************
-typedef struct {
- union { /* TA3CTL Register */
- __IO uint16_t r;
- struct { /* TA3CTL Bits */
- __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
- __IO uint16_t bIE : 1; /* TimerA interrupt enable */
- __IO uint16_t bCLR : 1; /* TimerA clear */
- __IO uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bMC : 2; /* Mode control */
- __IO uint16_t bID : 2; /* Input divider */
- __IO uint16_t bSSEL : 2; /* TimerA clock source select */
- __IO uint16_t bRESERVED1 : 6; /* Reserved */
- } b;
- } rCTL;
- union { /* TA3CCTL0 Register */
- __IO uint16_t r;
- struct { /* TA3CCTL0 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL0;
- union { /* TA3CCTL1 Register */
- __IO uint16_t r;
- struct { /* TA3CCTL1 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL1;
- union { /* TA3CCTL2 Register */
- __IO uint16_t r;
- struct { /* TA3CCTL2 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL2;
- union { /* TA3CCTL3 Register */
- __IO uint16_t r;
- struct { /* TA3CCTL3 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL3;
- union { /* TA3CCTL4 Register */
- __IO uint16_t r;
- struct { /* TA3CCTL4 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL4;
- union { /* TA3CCTL5 Register */
- __IO uint16_t r;
- struct { /* TA3CCTL5 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL5;
- union { /* TA3CCTL6 Register */
- __IO uint16_t r;
- struct { /* TA3CCTL6 Bits */
- __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
- __IO uint16_t bCOV : 1; /* Capture overflow */
- __IO uint16_t bOUT : 1; /* Output */
- __I uint16_t bCCI : 1; /* Capture/compare input */
- __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
- __IO uint16_t bOUTMOD : 3; /* Output mode */
- __IO uint16_t bCAP : 1; /* Capture mode */
- __I uint16_t bRESERVED0 : 1; /* Reserved */
- __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
- __IO uint16_t bSCS : 1; /* Synchronize capture source */
- __IO uint16_t bCCIS : 2; /* Capture/compare input select */
- __IO uint16_t bCM : 2; /* Capture mode */
- } b;
- } rCCTL6;
- __IO uint16_t rR; /* TimerA register */
- __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
- __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
- union { /* TA3EX0 Register */
- __IO uint16_t r;
- struct { /* TA3EX0 Bits */
- __IO uint16_t bIDEX : 3; /* Input divider expansion */
- __I uint16_t bRESERVED0 : 13; /* Reserved */
- } b;
- } rEX0;
- uint8_t RESERVED0[12];
- __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
-} TIMER_A3_Type;
-
-
-//*****************************************************************************
-// TLV Registers
-//*****************************************************************************
-typedef struct {
- __IO uint32_t rTLV_CHECKSUM; /* TLV Checksum */
- __IO uint32_t rDEVICE_INFO_TAG; /* Device Info Tag */
- __IO uint32_t rDEVICE_INFO_LEN; /* Device Info Length */
- __IO uint32_t rDEVICE_ID; /* Device ID */
- __IO uint32_t rHWREV; /* HW Revision */
- __IO uint32_t rBCREV; /* Boot Code Revision */
- __IO uint32_t rROM_DRVLIB_REV; /* ROM Driver Library Revision */
- __IO uint32_t rDIE_REC_TAG; /* Die Record Tag */
- __IO uint32_t rDIE_REC_LEN; /* Die Record Length */
- __IO uint32_t rDIE_XPOS; /* Die X-Position */
- __IO uint32_t rDIE_YPOS; /* Die Y-Position */
- __IO uint32_t rWAFER_ID; /* Wafer ID */
- __IO uint32_t rLOT_ID; /* Lot ID */
- __IO uint32_t rRESERVED0; /* Reserved */
- __IO uint32_t rRESERVED1; /* Reserved */
- __IO uint32_t rRESERVED2; /* Reserved */
- __IO uint32_t rTEST_RESULTS; /* Test Results */
- __IO uint32_t rCS_CAL_TAG; /* Clock System Calibration Tag */
- __IO uint32_t rCS_CAL_LEN; /* Clock System Calibration Length */
- __IO uint32_t rDCOIR_FCAL_RSEL04; /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
- __IO uint32_t rDCOIR_FCAL_RSEL5; /* DCO IR mode: Frequency calibration for DCORSEL 5 */
- __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL04; /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
- __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL04; /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
- __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL5; /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
- __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL5; /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
- __IO uint32_t rDCOIR_CONSTK_RSEL04; /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
- __IO uint32_t rDCOIR_CONSTK_RSEL5; /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
- __IO uint32_t rDCOER_FCAL_RSEL04; /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
- __IO uint32_t rDCOER_FCAL_RSEL5; /* DCO ER mode: Frequency calibration for DCORSEL 5 */
- __IO uint32_t rDCOER_MAXPOSTUNE_RSEL04; /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
- __IO uint32_t rDCOER_MAXNEGTUNE_RSEL04; /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
- __IO uint32_t rDCOER_MAXPOSTUNE_RSEL5; /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
- __IO uint32_t rDCOER_MAXNEGTUNE_RSEL5; /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
- __IO uint32_t rDCOER_CONSTK_RSEL04; /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
- __IO uint32_t rDCOER_CONSTK_RSEL5; /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
- __IO uint32_t rADC14_CAL_TAG; /* ADC14 Calibration Tag */
- __IO uint32_t rADC14_CAL_LEN; /* ADC14 Calibration Length */
- __IO uint32_t rADC14_GF_EXTREF30C; /* ADC14 Gain Factor for External Reference 30°C */
- __IO uint32_t rADC14_GF_EXTREF85C; /* ADC14 Gain Factor for External Reference 85°C */
- __IO uint32_t rADC14_GF_BUF_EXTREF30C; /* ADC14 Gain Factor for Buffered External Reference 30°C */
- __IO uint32_t rADC14_GF_BUF_EXTREF85C; /* ADC14 Gain Factor for Buffered External Reference 85°C */
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
- __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
- __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
- __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
- __IO uint32_t rADC14_OFFSET_VRSEL_1; /* ADC14 Offset (ADC14VRSEL = 1h) */
- __IO uint32_t rADC14_OFFSET_VRSEL_E; /* ADC14 Offset (ADC14VRSEL = Eh) */
- __IO uint32_t rADC14_REF1P2V_TS30C; /* ADC14 1.2V Reference Temp. Sensor 30°C */
- __IO uint32_t rADC14_REF1P2V_TS85C; /* ADC14 1.2V Reference Temp. Sensor 85°C */
- __IO uint32_t rADC14_REF1P45V_TS30C; /* ADC14 1.45V Reference Temp. Sensor 30°C */
- __IO uint32_t rADC14_REF1P45V_TS85C; /* ADC14 1.45V Reference Temp. Sensor 85°C */
- __IO uint32_t rADC14_REF2P5V_TS30C; /* ADC14 2.5V Reference Temp. Sensor 30°C */
- __IO uint32_t rADC14_REF2P5V_TS85C; /* ADC14 2.5V Reference Temp. Sensor 85°C */
- __IO uint32_t rREF_CAL_TAG; /* REF Calibration Tag */
- __IO uint32_t rREF_CAL_LEN; /* REF Calibration Length */
- __IO uint32_t rREF_1P2V; /* REF 1.2V Reference */
- __IO uint32_t rREF_1P45V; /* REF 1.45V Reference */
- __IO uint32_t rREF_2P5V; /* REF 2.5V Reference */
- __IO uint32_t rRANDOM_NUM_TAG; /* 128-bit Random Number Tag */
- __IO uint32_t rRANDOM_NUM_LEN; /* 128-bit Random Number Length */
- __IO uint32_t rRANDOM_NUM_1; /* 32-bit Random Number 1 */
- __IO uint32_t rRANDOM_NUM_2; /* 32-bit Random Number 2 */
- __IO uint32_t rRANDOM_NUM_3; /* 32-bit Random Number 3 */
- __IO uint32_t rRANDOM_NUM_4; /* 32-bit Random Number 4 */
- __IO uint32_t rBSL_CFG_TAG; /* BSL Configuration Tag */
- __IO uint32_t rBSL_CFG_LEN; /* BSL Configuration Length */
- __IO uint32_t rBSL_PERIPHIF_SEL; /* BSL Peripheral Interface Selection */
- __IO uint32_t rBSL_PORTIF_CFG_UART; /* BSL Port Interface Configuration for UART */
- __IO uint32_t rBSL_PORTIF_CFG_SPI; /* BSL Port Interface Configuration for SPI */
- __IO uint32_t rBSL_PORTIF_CFG_I2C; /* BSL Port Interface Configuration for I2C */
- __IO uint32_t rTLV_END; /* TLV End Word */
+ __I uint32_t TLV_CHECKSUM; /**< TLV Checksum */
+ __I uint32_t DEVICE_INFO_TAG; /**< Device Info Tag */
+ __I uint32_t DEVICE_INFO_LEN; /**< Device Info Length */
+ __I uint32_t DEVICE_ID; /**< Device ID */
+ __I uint32_t HWREV; /**< HW Revision */
+ __I uint32_t BCREV; /**< Boot Code Revision */
+ __I uint32_t ROM_DRVLIB_REV; /**< ROM Driver Library Revision */
+ __I uint32_t DIE_REC_TAG; /**< Die Record Tag */
+ __I uint32_t DIE_REC_LEN; /**< Die Record Length */
+ __I uint32_t DIE_XPOS; /**< Die X-Position */
+ __I uint32_t DIE_YPOS; /**< Die Y-Position */
+ __I uint32_t WAFER_ID; /**< Wafer ID */
+ __I uint32_t LOT_ID; /**< Lot ID */
+ __I uint32_t RESERVED0; /**< Reserved */
+ __I uint32_t RESERVED1; /**< Reserved */
+ __I uint32_t RESERVED2; /**< Reserved */
+ __I uint32_t TEST_RESULTS; /**< Test Results */
+ __I uint32_t CS_CAL_TAG; /**< Clock System Calibration Tag */
+ __I uint32_t CS_CAL_LEN; /**< Clock System Calibration Length */
+ __I uint32_t DCOIR_FCAL_RSEL04; /**< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
+ __I uint32_t DCOIR_FCAL_RSEL5; /**< DCO IR mode: Frequency calibration for DCORSEL 5 */
+ __I uint32_t DCOIR_MAXPOSTUNE_RSEL04; /**< DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
+ __I uint32_t DCOIR_MAXNEGTUNE_RSEL04; /**< DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
+ __I uint32_t DCOIR_MAXPOSTUNE_RSEL5; /**< DCO IR mode: Max Positive Tune for DCORSEL 5 */
+ __I uint32_t DCOIR_MAXNEGTUNE_RSEL5; /**< DCO IR mode: Max Negative Tune for DCORSEL 5 */
+ __I uint32_t DCOIR_CONSTK_RSEL04; /**< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
+ __I uint32_t DCOIR_CONSTK_RSEL5; /**< DCO IR mode: DCO Constant (K) for DCORSEL 5 */
+ __I uint32_t DCOER_FCAL_RSEL04; /**< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
+ __I uint32_t DCOER_FCAL_RSEL5; /**< DCO ER mode: Frequency calibration for DCORSEL 5 */
+ __I uint32_t DCOER_MAXPOSTUNE_RSEL04; /**< DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
+ __I uint32_t DCOER_MAXNEGTUNE_RSEL04; /**< DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
+ __I uint32_t DCOER_MAXPOSTUNE_RSEL5; /**< DCO ER mode: Max Positive Tune for DCORSEL 5 */
+ __I uint32_t DCOER_MAXNEGTUNE_RSEL5; /**< DCO ER mode: Max Negative Tune for DCORSEL 5 */
+ __I uint32_t DCOER_CONSTK_RSEL04; /**< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
+ __I uint32_t DCOER_CONSTK_RSEL5; /**< DCO ER mode: DCO Constant (K) for DCORSEL 5 */
+ __I uint32_t ADC14_CAL_TAG; /**< ADC14 Calibration Tag */
+ __I uint32_t ADC14_CAL_LEN; /**< ADC14 Calibration Length */
+ __I uint32_t ADC14_GF_EXTREF30C; /**< ADC14 Gain Factor for External Reference 30°C */
+ __I uint32_t ADC14_GF_EXTREF85C; /**< ADC14 Gain Factor for External Reference 85°C */
+ __I uint32_t ADC14_GF_BUF_EXTREF30C; /**< ADC14 Gain Factor for Buffered External Reference 30°C */
+ __I uint32_t ADC14_GF_BUF_EXTREF85C; /**< ADC14 Gain Factor for Buffered External Reference 85°C */
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
+ __I uint32_t ADC14_GF_BUF1P2V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
+ __I uint32_t ADC14_GF_BUF1P45V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF30C_REFOUT0; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF85C_REFOUT0; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF30C_REFOUT1; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
+ __I uint32_t ADC14_GF_BUF2P5V_INTREF85C_REFOUT1; /**< ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
+ __I uint32_t ADC14_OFFSET_VRSEL_1; /**< ADC14 Offset (ADC14VRSEL = 1h) */
+ __I uint32_t ADC14_OFFSET_VRSEL_E; /**< ADC14 Offset (ADC14VRSEL = Eh) */
+ __I uint32_t ADC14_REF1P2V_TS30C; /**< ADC14 1.2V Reference Temp. Sensor 30°C */
+ __I uint32_t ADC14_REF1P2V_TS85C; /**< ADC14 1.2V Reference Temp. Sensor 85°C */
+ __I uint32_t ADC14_REF1P45V_TS30C; /**< ADC14 1.45V Reference Temp. Sensor 30°C */
+ __I uint32_t ADC14_REF1P45V_TS85C; /**< ADC14 1.45V Reference Temp. Sensor 85°C */
+ __I uint32_t ADC14_REF2P5V_TS30C; /**< ADC14 2.5V Reference Temp. Sensor 30°C */
+ __I uint32_t ADC14_REF2P5V_TS85C; /**< ADC14 2.5V Reference Temp. Sensor 85°C */
+ __I uint32_t REF_CAL_TAG; /**< REF Calibration Tag */
+ __I uint32_t REF_CAL_LEN; /**< REF Calibration Length */
+ __I uint32_t REF_1P2V; /**< REF 1.2V Reference */
+ __I uint32_t REF_1P45V; /**< REF 1.45V Reference */
+ __I uint32_t REF_2P5V; /**< REF 2.5V Reference */
+ __I uint32_t FLASH_INFO_TAG; /**< Flash Info Tag */
+ __I uint32_t FLASH_INFO_LEN; /**< Flash Info Length */
+ __I uint32_t FLASH_MAX_PROG_PULSES; /**< Flash Maximum Programming Pulses */
+ __I uint32_t FLASH_MAX_ERASE_PULSES; /**< Flash Maximum Erase Pulses */
+ __I uint32_t RANDOM_NUM_TAG; /**< 128-bit Random Number Tag */
+ __I uint32_t RANDOM_NUM_LEN; /**< 128-bit Random Number Length */
+ __I uint32_t RANDOM_NUM_1; /**< 32-bit Random Number 1 */
+ __I uint32_t RANDOM_NUM_2; /**< 32-bit Random Number 2 */
+ __I uint32_t RANDOM_NUM_3; /**< 32-bit Random Number 3 */
+ __I uint32_t RANDOM_NUM_4; /**< 32-bit Random Number 4 */
+ __I uint32_t BSL_CFG_TAG; /**< BSL Configuration Tag */
+ __I uint32_t BSL_CFG_LEN; /**< BSL Configuration Length */
+ __I uint32_t BSL_PERIPHIF_SEL; /**< BSL Peripheral Interface Selection */
+ __I uint32_t BSL_PORTIF_CFG_UART; /**< BSL Port Interface Configuration for UART */
+ __I uint32_t BSL_PORTIF_CFG_SPI; /**< BSL Port Interface Configuration for SPI */
+ __I uint32_t BSL_PORTIF_CFG_I2C; /**< BSL Port Interface Configuration for I2C */
+ __I uint32_t TLV_END; /**< TLV End Word */
} TLV_Type;
+/*@}*/ /* end of group TLV */
-//*****************************************************************************
-// WDT_A Registers
-//*****************************************************************************
+
+/******************************************************************************
+* WDT_A Registers
+******************************************************************************/
+/** @addtogroup WDT_A MSP432P401R (WDT_A)
+ @{
+*/
typedef struct {
- uint8_t RESERVED0[12];
- union { /* WDTCTL Register */
- __IO uint16_t r;
- struct { /* WDTCTL Bits */
- __IO uint16_t bIS : 3; /* Watchdog timer interval select */
- __O uint16_t bCNTCL : 1; /* Watchdog timer counter clear */
- __IO uint16_t bTMSEL : 1; /* Watchdog timer mode select */
- __IO uint16_t bSSEL : 2; /* Watchdog timer clock source select */
- __IO uint16_t bHOLD : 1; /* Watchdog timer hold */
- __IO uint16_t bPW : 8; /* Watchdog timer password */
- } b;
- } rCTL;
+ uint16_t RESERVED0[6];
+ __IO uint16_t CTL; /**< Watchdog Timer Control Register */
} WDT_A_Type;
-
-//*****************************************************************************
-// Peripheral register control bits
-//*****************************************************************************
-
-//*****************************************************************************
-// ADC14 Bits
-//*****************************************************************************
-/* ADC14CTL0[ADC14SC] Bits */
-#define ADC14SC_OFS ( 0) /* ADC14SC Offset */
-#define ADC14SC (0x00000001) /* ADC14 start conversion */
-/* ADC14CTL0[ADC14ENC] Bits */
-#define ADC14ENC_OFS ( 1) /* ADC14ENC Offset */
-#define ADC14ENC (0x00000002) /* ADC14 enable conversion */
-/* ADC14CTL0[ADC14ON] Bits */
-#define ADC14ON_OFS ( 4) /* ADC14ON Offset */
-#define ADC14ON (0x00000010) /* ADC14 on */
-/* ADC14CTL0[ADC14MSC] Bits */
-#define ADC14MSC_OFS ( 7) /* ADC14MSC Offset */
-#define ADC14MSC (0x00000080) /* ADC14 multiple sample and conversion */
-/* ADC14CTL0[ADC14SHT0] Bits */
-#define ADC14SHT0_OFS ( 8) /* ADC14SHT0 Offset */
-#define ADC14SHT0_M (0x00000f00) /* ADC14 sample-and-hold time */
-#define ADC14SHT00 (0x00000100) /* ADC14 sample-and-hold time */
-#define ADC14SHT01 (0x00000200) /* ADC14 sample-and-hold time */
-#define ADC14SHT02 (0x00000400) /* ADC14 sample-and-hold time */
-#define ADC14SHT03 (0x00000800) /* ADC14 sample-and-hold time */
-#define ADC14SHT0_0 (0x00000000) /* 4 */
-#define ADC14SHT0_1 (0x00000100) /* 8 */
-#define ADC14SHT0_2 (0x00000200) /* 16 */
-#define ADC14SHT0_3 (0x00000300) /* 32 */
-#define ADC14SHT0_4 (0x00000400) /* 64 */
-#define ADC14SHT0_5 (0x00000500) /* 96 */
-#define ADC14SHT0_6 (0x00000600) /* 128 */
-#define ADC14SHT0_7 (0x00000700) /* 192 */
-#define ADC14SHT0__4 (0x00000000) /* 4 */
-#define ADC14SHT0__8 (0x00000100) /* 8 */
-#define ADC14SHT0__16 (0x00000200) /* 16 */
-#define ADC14SHT0__32 (0x00000300) /* 32 */
-#define ADC14SHT0__64 (0x00000400) /* 64 */
-#define ADC14SHT0__96 (0x00000500) /* 96 */
-#define ADC14SHT0__128 (0x00000600) /* 128 */
-#define ADC14SHT0__192 (0x00000700) /* 192 */
-/* ADC14CTL0[ADC14SHT1] Bits */
-#define ADC14SHT1_OFS (12) /* ADC14SHT1 Offset */
-#define ADC14SHT1_M (0x0000f000) /* ADC14 sample-and-hold time */
-#define ADC14SHT10 (0x00001000) /* ADC14 sample-and-hold time */
-#define ADC14SHT11 (0x00002000) /* ADC14 sample-and-hold time */
-#define ADC14SHT12 (0x00004000) /* ADC14 sample-and-hold time */
-#define ADC14SHT13 (0x00008000) /* ADC14 sample-and-hold time */
-#define ADC14SHT1_0 (0x00000000) /* 4 */
-#define ADC14SHT1_1 (0x00001000) /* 8 */
-#define ADC14SHT1_2 (0x00002000) /* 16 */
-#define ADC14SHT1_3 (0x00003000) /* 32 */
-#define ADC14SHT1_4 (0x00004000) /* 64 */
-#define ADC14SHT1_5 (0x00005000) /* 96 */
-#define ADC14SHT1_6 (0x00006000) /* 128 */
-#define ADC14SHT1_7 (0x00007000) /* 192 */
-#define ADC14SHT1__4 (0x00000000) /* 4 */
-#define ADC14SHT1__8 (0x00001000) /* 8 */
-#define ADC14SHT1__16 (0x00002000) /* 16 */
-#define ADC14SHT1__32 (0x00003000) /* 32 */
-#define ADC14SHT1__64 (0x00004000) /* 64 */
-#define ADC14SHT1__96 (0x00005000) /* 96 */
-#define ADC14SHT1__128 (0x00006000) /* 128 */
-#define ADC14SHT1__192 (0x00007000) /* 192 */
-/* ADC14CTL0[ADC14BUSY] Bits */
-#define ADC14BUSY_OFS (16) /* ADC14BUSY Offset */
-#define ADC14BUSY (0x00010000) /* ADC14 busy */
-/* ADC14CTL0[ADC14CONSEQ] Bits */
-#define ADC14CONSEQ_OFS (17) /* ADC14CONSEQ Offset */
-#define ADC14CONSEQ_M (0x00060000) /* ADC14 conversion sequence mode select */
-#define ADC14CONSEQ0 (0x00020000) /* ADC14 conversion sequence mode select */
-#define ADC14CONSEQ1 (0x00040000) /* ADC14 conversion sequence mode select */
-#define ADC14CONSEQ_0 (0x00000000) /* Single-channel, single-conversion */
-#define ADC14CONSEQ_1 (0x00020000) /* Sequence-of-channels */
-#define ADC14CONSEQ_2 (0x00040000) /* Repeat-single-channel */
-#define ADC14CONSEQ_3 (0x00060000) /* Repeat-sequence-of-channels */
-/* ADC14CTL0[ADC14SSEL] Bits */
-#define ADC14SSEL_OFS (19) /* ADC14SSEL Offset */
-#define ADC14SSEL_M (0x00380000) /* ADC14 clock source select */
-#define ADC14SSEL0 (0x00080000) /* ADC14 clock source select */
-#define ADC14SSEL1 (0x00100000) /* ADC14 clock source select */
-#define ADC14SSEL2 (0x00200000) /* ADC14 clock source select */
-#define ADC14SSEL_0 (0x00000000) /* MODCLK */
-#define ADC14SSEL_1 (0x00080000) /* SYSCLK */
-#define ADC14SSEL_2 (0x00100000) /* ACLK */
-#define ADC14SSEL_3 (0x00180000) /* MCLK */
-#define ADC14SSEL_4 (0x00200000) /* SMCLK */
-#define ADC14SSEL_5 (0x00280000) /* HSMCLK */
-#define ADC14SSEL__MODCLK (0x00000000) /* MODCLK */
-#define ADC14SSEL__SYSCLK (0x00080000) /* SYSCLK */
-#define ADC14SSEL__ACLK (0x00100000) /* ACLK */
-#define ADC14SSEL__MCLK (0x00180000) /* MCLK */
-#define ADC14SSEL__SMCLK (0x00200000) /* SMCLK */
-#define ADC14SSEL__HSMCLK (0x00280000) /* HSMCLK */
-/* ADC14CTL0[ADC14DIV] Bits */
-#define ADC14DIV_OFS (22) /* ADC14DIV Offset */
-#define ADC14DIV_M (0x01c00000) /* ADC14 clock divider */
-#define ADC14DIV0 (0x00400000) /* ADC14 clock divider */
-#define ADC14DIV1 (0x00800000) /* ADC14 clock divider */
-#define ADC14DIV2 (0x01000000) /* ADC14 clock divider */
-#define ADC14DIV_0 (0x00000000) /* /1 */
-#define ADC14DIV_1 (0x00400000) /* /2 */
-#define ADC14DIV_2 (0x00800000) /* /3 */
-#define ADC14DIV_3 (0x00c00000) /* /4 */
-#define ADC14DIV_4 (0x01000000) /* /5 */
-#define ADC14DIV_5 (0x01400000) /* /6 */
-#define ADC14DIV_6 (0x01800000) /* /7 */
-#define ADC14DIV_7 (0x01c00000) /* /8 */
-#define ADC14DIV__1 (0x00000000) /* /1 */
-#define ADC14DIV__2 (0x00400000) /* /2 */
-#define ADC14DIV__3 (0x00800000) /* /3 */
-#define ADC14DIV__4 (0x00c00000) /* /4 */
-#define ADC14DIV__5 (0x01000000) /* /5 */
-#define ADC14DIV__6 (0x01400000) /* /6 */
-#define ADC14DIV__7 (0x01800000) /* /7 */
-#define ADC14DIV__8 (0x01c00000) /* /8 */
-/* ADC14CTL0[ADC14ISSH] Bits */
-#define ADC14ISSH_OFS (25) /* ADC14ISSH Offset */
-#define ADC14ISSH (0x02000000) /* ADC14 invert signal sample-and-hold */
-/* ADC14CTL0[ADC14SHP] Bits */
-#define ADC14SHP_OFS (26) /* ADC14SHP Offset */
-#define ADC14SHP (0x04000000) /* ADC14 sample-and-hold pulse-mode select */
-/* ADC14CTL0[ADC14SHS] Bits */
-#define ADC14SHS_OFS (27) /* ADC14SHS Offset */
-#define ADC14SHS_M (0x38000000) /* ADC14 sample-and-hold source select */
-#define ADC14SHS0 (0x08000000) /* ADC14 sample-and-hold source select */
-#define ADC14SHS1 (0x10000000) /* ADC14 sample-and-hold source select */
-#define ADC14SHS2 (0x20000000) /* ADC14 sample-and-hold source select */
-#define ADC14SHS_0 (0x00000000) /* ADC14SC bit */
-#define ADC14SHS_1 (0x08000000) /* See device-specific data sheet for source */
-#define ADC14SHS_2 (0x10000000) /* See device-specific data sheet for source */
-#define ADC14SHS_3 (0x18000000) /* See device-specific data sheet for source */
-#define ADC14SHS_4 (0x20000000) /* See device-specific data sheet for source */
-#define ADC14SHS_5 (0x28000000) /* See device-specific data sheet for source */
-#define ADC14SHS_6 (0x30000000) /* See device-specific data sheet for source */
-#define ADC14SHS_7 (0x38000000) /* See device-specific data sheet for source */
-/* ADC14CTL0[ADC14PDIV] Bits */
-#define ADC14PDIV_OFS (30) /* ADC14PDIV Offset */
-#define ADC14PDIV_M (0xc0000000) /* ADC14 predivider */
-#define ADC14PDIV0 (0x40000000) /* ADC14 predivider */
-#define ADC14PDIV1 (0x80000000) /* ADC14 predivider */
-#define ADC14PDIV_0 (0x00000000) /* Predivide by 1 */
-#define ADC14PDIV_1 (0x40000000) /* Predivide by 4 */
-#define ADC14PDIV_2 (0x80000000) /* Predivide by 32 */
-#define ADC14PDIV_3 (0xc0000000) /* Predivide by 64 */
-#define ADC14PDIV__1 (0x00000000) /* Predivide by 1 */
-#define ADC14PDIV__4 (0x40000000) /* Predivide by 4 */
-#define ADC14PDIV__32 (0x80000000) /* Predivide by 32 */
-#define ADC14PDIV__64 (0xc0000000) /* Predivide by 64 */
-/* ADC14CTL1[ADC14PWRMD] Bits */
-#define ADC14PWRMD_OFS ( 0) /* ADC14PWRMD Offset */
-#define ADC14PWRMD_M (0x00000003) /* ADC14 power modes */
-#define ADC14PWRMD0 (0x00000001) /* ADC14 power modes */
-#define ADC14PWRMD1 (0x00000002) /* ADC14 power modes */
-#define ADC14PWRMD_0 (0x00000000) /* Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps. */
-#define ADC14PWRMD_2 (0x00000002) /* Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps. */
-/* ADC14CTL1[ADC14REFBURST] Bits */
-#define ADC14REFBURST_OFS ( 2) /* ADC14REFBURST Offset */
-#define ADC14REFBURST (0x00000004) /* ADC14 reference buffer burst */
-/* ADC14CTL1[ADC14DF] Bits */
-#define ADC14DF_OFS ( 3) /* ADC14DF Offset */
-#define ADC14DF (0x00000008) /* ADC14 data read-back format */
-/* ADC14CTL1[ADC14RES] Bits */
-#define ADC14RES_OFS ( 4) /* ADC14RES Offset */
-#define ADC14RES_M (0x00000030) /* ADC14 resolution */
-#define ADC14RES0 (0x00000010) /* ADC14 resolution */
-#define ADC14RES1 (0x00000020) /* ADC14 resolution */
-#define ADC14RES_0 (0x00000000) /* 8 bit (9 clock cycle conversion time) */
-#define ADC14RES_1 (0x00000010) /* 10 bit (11 clock cycle conversion time) */
-#define ADC14RES_2 (0x00000020) /* 12 bit (14 clock cycle conversion time) */
-#define ADC14RES_3 (0x00000030) /* 14 bit (16 clock cycle conversion time) */
-#define ADC14RES__8BIT (0x00000000) /* 8 bit (9 clock cycle conversion time) */
-#define ADC14RES__10BIT (0x00000010) /* 10 bit (11 clock cycle conversion time) */
-#define ADC14RES__12BIT (0x00000020) /* 12 bit (14 clock cycle conversion time) */
-#define ADC14RES__14BIT (0x00000030) /* 14 bit (16 clock cycle conversion time) */
-/* ADC14CTL1[ADC14CSTARTADD] Bits */
-#define ADC14CSTARTADD_OFS (16) /* ADC14CSTARTADD Offset */
-#define ADC14CSTARTADD_M (0x001f0000) /* ADC14 conversion start address */
-/* ADC14CTL1[ADC14BATMAP] Bits */
-#define ADC14BATMAP_OFS (22) /* ADC14BATMAP Offset */
-#define ADC14BATMAP (0x00400000) /* Controls 1/2 AVCC ADC input channel selection */
-/* ADC14CTL1[ADC14TCMAP] Bits */
-#define ADC14TCMAP_OFS (23) /* ADC14TCMAP Offset */
-#define ADC14TCMAP (0x00800000) /* Controls temperature sensor ADC input channel selection */
-/* ADC14CTL1[ADC14CH0MAP] Bits */
-#define ADC14CH0MAP_OFS (24) /* ADC14CH0MAP Offset */
-#define ADC14CH0MAP (0x01000000) /* Controls internal channel 0 selection to ADC input channel MAX-2 */
-/* ADC14CTL1[ADC14CH1MAP] Bits */
-#define ADC14CH1MAP_OFS (25) /* ADC14CH1MAP Offset */
-#define ADC14CH1MAP (0x02000000) /* Controls internal channel 1 selection to ADC input channel MAX-3 */
-/* ADC14CTL1[ADC14CH2MAP] Bits */
-#define ADC14CH2MAP_OFS (26) /* ADC14CH2MAP Offset */
-#define ADC14CH2MAP (0x04000000) /* Controls internal channel 2 selection to ADC input channel MAX-4 */
-/* ADC14CTL1[ADC14CH3MAP] Bits */
-#define ADC14CH3MAP_OFS (27) /* ADC14CH3MAP Offset */
-#define ADC14CH3MAP (0x08000000) /* Controls internal channel 3 selection to ADC input channel MAX-5 */
-/* ADC14LO0[ADC14LO0] Bits */
-#define ADC14LO0_OFS ( 0) /* ADC14LO0 Offset */
-#define ADC14LO0_M (0x0000ffff) /* Low threshold 0 */
-/* ADC14HI0[ADC14HI0] Bits */
-#define ADC14HI0_OFS ( 0) /* ADC14HI0 Offset */
-#define ADC14HI0_M (0x0000ffff) /* High threshold 0 */
-/* ADC14LO1[ADC14LO1] Bits */
-#define ADC14LO1_OFS ( 0) /* ADC14LO1 Offset */
-#define ADC14LO1_M (0x0000ffff) /* Low threshold 1 */
-/* ADC14HI1[ADC14HI1] Bits */
-#define ADC14HI1_OFS ( 0) /* ADC14HI1 Offset */
-#define ADC14HI1_M (0x0000ffff) /* High threshold 1 */
-/* ADC14MCTL[ADC14INCH] Bits */
-#define ADC14INCH_OFS ( 0) /* ADC14INCH Offset */
-#define ADC14INCH_M (0x0000001f) /* Input channel select */
-#define ADC14INCH0 (0x00000001) /* Input channel select */
-#define ADC14INCH1 (0x00000002) /* Input channel select */
-#define ADC14INCH2 (0x00000004) /* Input channel select */
-#define ADC14INCH3 (0x00000008) /* Input channel select */
-#define ADC14INCH4 (0x00000010) /* Input channel select */
-#define ADC14INCH_0 (0x00000000) /* If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
-#define ADC14INCH_1 (0x00000001) /* If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
-#define ADC14INCH_2 (0x00000002) /* If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
-#define ADC14INCH_3 (0x00000003) /* If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
-#define ADC14INCH_4 (0x00000004) /* If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
-#define ADC14INCH_5 (0x00000005) /* If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
-#define ADC14INCH_6 (0x00000006) /* If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
-#define ADC14INCH_7 (0x00000007) /* If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
-#define ADC14INCH_8 (0x00000008) /* If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
-#define ADC14INCH_9 (0x00000009) /* If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
-#define ADC14INCH_10 (0x0000000a) /* If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
-#define ADC14INCH_11 (0x0000000b) /* If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
-#define ADC14INCH_12 (0x0000000c) /* If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
-#define ADC14INCH_13 (0x0000000d) /* If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
-#define ADC14INCH_14 (0x0000000e) /* If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
-#define ADC14INCH_15 (0x0000000f) /* If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
-#define ADC14INCH_16 (0x00000010) /* If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
-#define ADC14INCH_17 (0x00000011) /* If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
-#define ADC14INCH_18 (0x00000012) /* If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
-#define ADC14INCH_19 (0x00000013) /* If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
-#define ADC14INCH_20 (0x00000014) /* If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
-#define ADC14INCH_21 (0x00000015) /* If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
-#define ADC14INCH_22 (0x00000016) /* If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
-#define ADC14INCH_23 (0x00000017) /* If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
-#define ADC14INCH_24 (0x00000018) /* If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
-#define ADC14INCH_25 (0x00000019) /* If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
-#define ADC14INCH_26 (0x0000001a) /* If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
-#define ADC14INCH_27 (0x0000001b) /* If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
-#define ADC14INCH_28 (0x0000001c) /* If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
-#define ADC14INCH_29 (0x0000001d) /* If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
-#define ADC14INCH_30 (0x0000001e) /* If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
-#define ADC14INCH_31 (0x0000001f) /* If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
-/* ADC14MCTL[ADC14EOS] Bits */
-#define ADC14EOS_OFS ( 7) /* ADC14EOS Offset */
-#define ADC14EOS (0x00000080) /* End of sequence */
-/* ADC14MCTL[ADC14VRSEL] Bits */
-#define ADC14VRSEL_OFS ( 8) /* ADC14VRSEL Offset */
-#define ADC14VRSEL_M (0x00000f00) /* Selects combinations of V(R+) and V(R-) sources */
-#define ADC14VRSEL0 (0x00000100) /* Selects combinations of V(R+) and V(R-) sources */
-#define ADC14VRSEL1 (0x00000200) /* Selects combinations of V(R+) and V(R-) sources */
-#define ADC14VRSEL2 (0x00000400) /* Selects combinations of V(R+) and V(R-) sources */
-#define ADC14VRSEL3 (0x00000800) /* Selects combinations of V(R+) and V(R-) sources */
-#define ADC14VRSEL_0 (0x00000000) /* V(R+) = AVCC, V(R-) = AVSS */
-#define ADC14VRSEL_1 (0x00000100) /* V(R+) = VREF buffered, V(R-) = AVSS */
-#define ADC14VRSEL_14 (0x00000e00) /* V(R+) = VeREF+, V(R-) = VeREF- */
-#define ADC14VRSEL_15 (0x00000f00) /* V(R+) = VeREF+ buffered, V(R-) = VeREF */
-/* ADC14MCTL[ADC14DIF] Bits */
-#define ADC14DIF_OFS (13) /* ADC14DIF Offset */
-#define ADC14DIF (0x00002000) /* Differential mode */
-/* ADC14MCTL[ADC14WINC] Bits */
-#define ADC14WINC_OFS (14) /* ADC14WINC Offset */
-#define ADC14WINC (0x00004000) /* Comparator window enable */
-/* ADC14MCTL[ADC14WINCTH] Bits */
-#define ADC14WINCTH_OFS (15) /* ADC14WINCTH Offset */
-#define ADC14WINCTH (0x00008000) /* Window comparator threshold register selection */
-/* ADC14MEM[CONVERSION_RESULTS] Bits */
-#define CONVERSION_RESULTS_OFS ( 0) /* Conversion_Results Offset */
-#define CONVERSION_RESULTS_M (0x0000ffff) /* Conversion Result */
-/* ADC14IER0[ADC14IE0] Bits */
-#define ADC14IE0_OFS ( 0) /* ADC14IE0 Offset */
-#define ADC14IE0 (0x00000001) /* Interrupt enable */
-/* ADC14IER0[ADC14IE1] Bits */
-#define ADC14IE1_OFS ( 1) /* ADC14IE1 Offset */
-#define ADC14IE1 (0x00000002) /* Interrupt enable */
-/* ADC14IER0[ADC14IE2] Bits */
-#define ADC14IE2_OFS ( 2) /* ADC14IE2 Offset */
-#define ADC14IE2 (0x00000004) /* Interrupt enable */
-/* ADC14IER0[ADC14IE3] Bits */
-#define ADC14IE3_OFS ( 3) /* ADC14IE3 Offset */
-#define ADC14IE3 (0x00000008) /* Interrupt enable */
-/* ADC14IER0[ADC14IE4] Bits */
-#define ADC14IE4_OFS ( 4) /* ADC14IE4 Offset */
-#define ADC14IE4 (0x00000010) /* Interrupt enable */
-/* ADC14IER0[ADC14IE5] Bits */
-#define ADC14IE5_OFS ( 5) /* ADC14IE5 Offset */
-#define ADC14IE5 (0x00000020) /* Interrupt enable */
-/* ADC14IER0[ADC14IE6] Bits */
-#define ADC14IE6_OFS ( 6) /* ADC14IE6 Offset */
-#define ADC14IE6 (0x00000040) /* Interrupt enable */
-/* ADC14IER0[ADC14IE7] Bits */
-#define ADC14IE7_OFS ( 7) /* ADC14IE7 Offset */
-#define ADC14IE7 (0x00000080) /* Interrupt enable */
-/* ADC14IER0[ADC14IE8] Bits */
-#define ADC14IE8_OFS ( 8) /* ADC14IE8 Offset */
-#define ADC14IE8 (0x00000100) /* Interrupt enable */
-/* ADC14IER0[ADC14IE9] Bits */
-#define ADC14IE9_OFS ( 9) /* ADC14IE9 Offset */
-#define ADC14IE9 (0x00000200) /* Interrupt enable */
-/* ADC14IER0[ADC14IE10] Bits */
-#define ADC14IE10_OFS (10) /* ADC14IE10 Offset */
-#define ADC14IE10 (0x00000400) /* Interrupt enable */
-/* ADC14IER0[ADC14IE11] Bits */
-#define ADC14IE11_OFS (11) /* ADC14IE11 Offset */
-#define ADC14IE11 (0x00000800) /* Interrupt enable */
-/* ADC14IER0[ADC14IE12] Bits */
-#define ADC14IE12_OFS (12) /* ADC14IE12 Offset */
-#define ADC14IE12 (0x00001000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE13] Bits */
-#define ADC14IE13_OFS (13) /* ADC14IE13 Offset */
-#define ADC14IE13 (0x00002000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE14] Bits */
-#define ADC14IE14_OFS (14) /* ADC14IE14 Offset */
-#define ADC14IE14 (0x00004000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE15] Bits */
-#define ADC14IE15_OFS (15) /* ADC14IE15 Offset */
-#define ADC14IE15 (0x00008000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE16] Bits */
-#define ADC14IE16_OFS (16) /* ADC14IE16 Offset */
-#define ADC14IE16 (0x00010000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE17] Bits */
-#define ADC14IE17_OFS (17) /* ADC14IE17 Offset */
-#define ADC14IE17 (0x00020000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE19] Bits */
-#define ADC14IE19_OFS (19) /* ADC14IE19 Offset */
-#define ADC14IE19 (0x00080000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE18] Bits */
-#define ADC14IE18_OFS (18) /* ADC14IE18 Offset */
-#define ADC14IE18 (0x00040000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE20] Bits */
-#define ADC14IE20_OFS (20) /* ADC14IE20 Offset */
-#define ADC14IE20 (0x00100000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE21] Bits */
-#define ADC14IE21_OFS (21) /* ADC14IE21 Offset */
-#define ADC14IE21 (0x00200000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE22] Bits */
-#define ADC14IE22_OFS (22) /* ADC14IE22 Offset */
-#define ADC14IE22 (0x00400000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE23] Bits */
-#define ADC14IE23_OFS (23) /* ADC14IE23 Offset */
-#define ADC14IE23 (0x00800000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE24] Bits */
-#define ADC14IE24_OFS (24) /* ADC14IE24 Offset */
-#define ADC14IE24 (0x01000000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE25] Bits */
-#define ADC14IE25_OFS (25) /* ADC14IE25 Offset */
-#define ADC14IE25 (0x02000000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE26] Bits */
-#define ADC14IE26_OFS (26) /* ADC14IE26 Offset */
-#define ADC14IE26 (0x04000000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE27] Bits */
-#define ADC14IE27_OFS (27) /* ADC14IE27 Offset */
-#define ADC14IE27 (0x08000000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE28] Bits */
-#define ADC14IE28_OFS (28) /* ADC14IE28 Offset */
-#define ADC14IE28 (0x10000000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE29] Bits */
-#define ADC14IE29_OFS (29) /* ADC14IE29 Offset */
-#define ADC14IE29 (0x20000000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE30] Bits */
-#define ADC14IE30_OFS (30) /* ADC14IE30 Offset */
-#define ADC14IE30 (0x40000000) /* Interrupt enable */
-/* ADC14IER0[ADC14IE31] Bits */
-#define ADC14IE31_OFS (31) /* ADC14IE31 Offset */
-#define ADC14IE31 (0x80000000) /* Interrupt enable */
-/* ADC14IER1[ADC14INIE] Bits */
-#define ADC14INIE_OFS ( 1) /* ADC14INIE Offset */
-#define ADC14INIE (0x00000002) /* Interrupt enable for ADC14MEMx within comparator window */
-/* ADC14IER1[ADC14LOIE] Bits */
-#define ADC14LOIE_OFS ( 2) /* ADC14LOIE Offset */
-#define ADC14LOIE (0x00000004) /* Interrupt enable for ADC14MEMx below comparator window */
-/* ADC14IER1[ADC14HIIE] Bits */
-#define ADC14HIIE_OFS ( 3) /* ADC14HIIE Offset */
-#define ADC14HIIE (0x00000008) /* Interrupt enable for ADC14MEMx above comparator window */
-/* ADC14IER1[ADC14OVIE] Bits */
-#define ADC14OVIE_OFS ( 4) /* ADC14OVIE Offset */
-#define ADC14OVIE (0x00000010) /* ADC14MEMx overflow-interrupt enable */
-/* ADC14IER1[ADC14TOVIE] Bits */
-#define ADC14TOVIE_OFS ( 5) /* ADC14TOVIE Offset */
-#define ADC14TOVIE (0x00000020) /* ADC14 conversion-time-overflow interrupt enable */
-/* ADC14IER1[ADC14RDYIE] Bits */
-#define ADC14RDYIE_OFS ( 6) /* ADC14RDYIE Offset */
-#define ADC14RDYIE (0x00000040) /* ADC14 local buffered reference ready interrupt enable */
-/* ADC14IFGR0[ADC14IFG0] Bits */
-#define ADC14IFG0_OFS ( 0) /* ADC14IFG0 Offset */
-#define ADC14IFG0 (0x00000001) /* ADC14MEM0 interrupt flag */
-/* ADC14IFGR0[ADC14IFG1] Bits */
-#define ADC14IFG1_OFS ( 1) /* ADC14IFG1 Offset */
-#define ADC14IFG1 (0x00000002) /* ADC14MEM1 interrupt flag */
-/* ADC14IFGR0[ADC14IFG2] Bits */
-#define ADC14IFG2_OFS ( 2) /* ADC14IFG2 Offset */
-#define ADC14IFG2 (0x00000004) /* ADC14MEM2 interrupt flag */
-/* ADC14IFGR0[ADC14IFG3] Bits */
-#define ADC14IFG3_OFS ( 3) /* ADC14IFG3 Offset */
-#define ADC14IFG3 (0x00000008) /* ADC14MEM3 interrupt flag */
-/* ADC14IFGR0[ADC14IFG4] Bits */
-#define ADC14IFG4_OFS ( 4) /* ADC14IFG4 Offset */
-#define ADC14IFG4 (0x00000010) /* ADC14MEM4 interrupt flag */
-/* ADC14IFGR0[ADC14IFG5] Bits */
-#define ADC14IFG5_OFS ( 5) /* ADC14IFG5 Offset */
-#define ADC14IFG5 (0x00000020) /* ADC14MEM5 interrupt flag */
-/* ADC14IFGR0[ADC14IFG6] Bits */
-#define ADC14IFG6_OFS ( 6) /* ADC14IFG6 Offset */
-#define ADC14IFG6 (0x00000040) /* ADC14MEM6 interrupt flag */
-/* ADC14IFGR0[ADC14IFG7] Bits */
-#define ADC14IFG7_OFS ( 7) /* ADC14IFG7 Offset */
-#define ADC14IFG7 (0x00000080) /* ADC14MEM7 interrupt flag */
-/* ADC14IFGR0[ADC14IFG8] Bits */
-#define ADC14IFG8_OFS ( 8) /* ADC14IFG8 Offset */
-#define ADC14IFG8 (0x00000100) /* ADC14MEM8 interrupt flag */
-/* ADC14IFGR0[ADC14IFG9] Bits */
-#define ADC14IFG9_OFS ( 9) /* ADC14IFG9 Offset */
-#define ADC14IFG9 (0x00000200) /* ADC14MEM9 interrupt flag */
-/* ADC14IFGR0[ADC14IFG10] Bits */
-#define ADC14IFG10_OFS (10) /* ADC14IFG10 Offset */
-#define ADC14IFG10 (0x00000400) /* ADC14MEM10 interrupt flag */
-/* ADC14IFGR0[ADC14IFG11] Bits */
-#define ADC14IFG11_OFS (11) /* ADC14IFG11 Offset */
-#define ADC14IFG11 (0x00000800) /* ADC14MEM11 interrupt flag */
-/* ADC14IFGR0[ADC14IFG12] Bits */
-#define ADC14IFG12_OFS (12) /* ADC14IFG12 Offset */
-#define ADC14IFG12 (0x00001000) /* ADC14MEM12 interrupt flag */
-/* ADC14IFGR0[ADC14IFG13] Bits */
-#define ADC14IFG13_OFS (13) /* ADC14IFG13 Offset */
-#define ADC14IFG13 (0x00002000) /* ADC14MEM13 interrupt flag */
-/* ADC14IFGR0[ADC14IFG14] Bits */
-#define ADC14IFG14_OFS (14) /* ADC14IFG14 Offset */
-#define ADC14IFG14 (0x00004000) /* ADC14MEM14 interrupt flag */
-/* ADC14IFGR0[ADC14IFG15] Bits */
-#define ADC14IFG15_OFS (15) /* ADC14IFG15 Offset */
-#define ADC14IFG15 (0x00008000) /* ADC14MEM15 interrupt flag */
-/* ADC14IFGR0[ADC14IFG16] Bits */
-#define ADC14IFG16_OFS (16) /* ADC14IFG16 Offset */
-#define ADC14IFG16 (0x00010000) /* ADC14MEM16 interrupt flag */
-/* ADC14IFGR0[ADC14IFG17] Bits */
-#define ADC14IFG17_OFS (17) /* ADC14IFG17 Offset */
-#define ADC14IFG17 (0x00020000) /* ADC14MEM17 interrupt flag */
-/* ADC14IFGR0[ADC14IFG18] Bits */
-#define ADC14IFG18_OFS (18) /* ADC14IFG18 Offset */
-#define ADC14IFG18 (0x00040000) /* ADC14MEM18 interrupt flag */
-/* ADC14IFGR0[ADC14IFG19] Bits */
-#define ADC14IFG19_OFS (19) /* ADC14IFG19 Offset */
-#define ADC14IFG19 (0x00080000) /* ADC14MEM19 interrupt flag */
-/* ADC14IFGR0[ADC14IFG20] Bits */
-#define ADC14IFG20_OFS (20) /* ADC14IFG20 Offset */
-#define ADC14IFG20 (0x00100000) /* ADC14MEM20 interrupt flag */
-/* ADC14IFGR0[ADC14IFG21] Bits */
-#define ADC14IFG21_OFS (21) /* ADC14IFG21 Offset */
-#define ADC14IFG21 (0x00200000) /* ADC14MEM21 interrupt flag */
-/* ADC14IFGR0[ADC14IFG22] Bits */
-#define ADC14IFG22_OFS (22) /* ADC14IFG22 Offset */
-#define ADC14IFG22 (0x00400000) /* ADC14MEM22 interrupt flag */
-/* ADC14IFGR0[ADC14IFG23] Bits */
-#define ADC14IFG23_OFS (23) /* ADC14IFG23 Offset */
-#define ADC14IFG23 (0x00800000) /* ADC14MEM23 interrupt flag */
-/* ADC14IFGR0[ADC14IFG24] Bits */
-#define ADC14IFG24_OFS (24) /* ADC14IFG24 Offset */
-#define ADC14IFG24 (0x01000000) /* ADC14MEM24 interrupt flag */
-/* ADC14IFGR0[ADC14IFG25] Bits */
-#define ADC14IFG25_OFS (25) /* ADC14IFG25 Offset */
-#define ADC14IFG25 (0x02000000) /* ADC14MEM25 interrupt flag */
-/* ADC14IFGR0[ADC14IFG26] Bits */
-#define ADC14IFG26_OFS (26) /* ADC14IFG26 Offset */
-#define ADC14IFG26 (0x04000000) /* ADC14MEM26 interrupt flag */
-/* ADC14IFGR0[ADC14IFG27] Bits */
-#define ADC14IFG27_OFS (27) /* ADC14IFG27 Offset */
-#define ADC14IFG27 (0x08000000) /* ADC14MEM27 interrupt flag */
-/* ADC14IFGR0[ADC14IFG28] Bits */
-#define ADC14IFG28_OFS (28) /* ADC14IFG28 Offset */
-#define ADC14IFG28 (0x10000000) /* ADC14MEM28 interrupt flag */
-/* ADC14IFGR0[ADC14IFG29] Bits */
-#define ADC14IFG29_OFS (29) /* ADC14IFG29 Offset */
-#define ADC14IFG29 (0x20000000) /* ADC14MEM29 interrupt flag */
-/* ADC14IFGR0[ADC14IFG30] Bits */
-#define ADC14IFG30_OFS (30) /* ADC14IFG30 Offset */
-#define ADC14IFG30 (0x40000000) /* ADC14MEM30 interrupt flag */
-/* ADC14IFGR0[ADC14IFG31] Bits */
-#define ADC14IFG31_OFS (31) /* ADC14IFG31 Offset */
-#define ADC14IFG31 (0x80000000) /* ADC14MEM31 interrupt flag */
-/* ADC14IFGR1[ADC14INIFG] Bits */
-#define ADC14INIFG_OFS ( 1) /* ADC14INIFG Offset */
-#define ADC14INIFG (0x00000002) /* Interrupt flag for ADC14MEMx within comparator window */
-/* ADC14IFGR1[ADC14LOIFG] Bits */
-#define ADC14LOIFG_OFS ( 2) /* ADC14LOIFG Offset */
-#define ADC14LOIFG (0x00000004) /* Interrupt flag for ADC14MEMx below comparator window */
-/* ADC14IFGR1[ADC14HIIFG] Bits */
-#define ADC14HIIFG_OFS ( 3) /* ADC14HIIFG Offset */
-#define ADC14HIIFG (0x00000008) /* Interrupt flag for ADC14MEMx above comparator window */
-/* ADC14IFGR1[ADC14OVIFG] Bits */
-#define ADC14OVIFG_OFS ( 4) /* ADC14OVIFG Offset */
-#define ADC14OVIFG (0x00000010) /* ADC14MEMx overflow interrupt flag */
-/* ADC14IFGR1[ADC14TOVIFG] Bits */
-#define ADC14TOVIFG_OFS ( 5) /* ADC14TOVIFG Offset */
-#define ADC14TOVIFG (0x00000020) /* ADC14 conversion time overflow interrupt flag */
-/* ADC14IFGR1[ADC14RDYIFG] Bits */
-#define ADC14RDYIFG_OFS ( 6) /* ADC14RDYIFG Offset */
-#define ADC14RDYIFG (0x00000040) /* ADC14 local buffered reference ready interrupt flag */
-/* ADC14CLRIFGR0[CLRADC14IFG0] Bits */
-#define CLRADC14IFG0_OFS ( 0) /* CLRADC14IFG0 Offset */
-#define CLRADC14IFG0 (0x00000001) /* clear ADC14IFG0 */
-/* ADC14CLRIFGR0[CLRADC14IFG1] Bits */
-#define CLRADC14IFG1_OFS ( 1) /* CLRADC14IFG1 Offset */
-#define CLRADC14IFG1 (0x00000002) /* clear ADC14IFG1 */
-/* ADC14CLRIFGR0[CLRADC14IFG2] Bits */
-#define CLRADC14IFG2_OFS ( 2) /* CLRADC14IFG2 Offset */
-#define CLRADC14IFG2 (0x00000004) /* clear ADC14IFG2 */
-/* ADC14CLRIFGR0[CLRADC14IFG3] Bits */
-#define CLRADC14IFG3_OFS ( 3) /* CLRADC14IFG3 Offset */
-#define CLRADC14IFG3 (0x00000008) /* clear ADC14IFG3 */
-/* ADC14CLRIFGR0[CLRADC14IFG4] Bits */
-#define CLRADC14IFG4_OFS ( 4) /* CLRADC14IFG4 Offset */
-#define CLRADC14IFG4 (0x00000010) /* clear ADC14IFG4 */
-/* ADC14CLRIFGR0[CLRADC14IFG5] Bits */
-#define CLRADC14IFG5_OFS ( 5) /* CLRADC14IFG5 Offset */
-#define CLRADC14IFG5 (0x00000020) /* clear ADC14IFG5 */
-/* ADC14CLRIFGR0[CLRADC14IFG6] Bits */
-#define CLRADC14IFG6_OFS ( 6) /* CLRADC14IFG6 Offset */
-#define CLRADC14IFG6 (0x00000040) /* clear ADC14IFG6 */
-/* ADC14CLRIFGR0[CLRADC14IFG7] Bits */
-#define CLRADC14IFG7_OFS ( 7) /* CLRADC14IFG7 Offset */
-#define CLRADC14IFG7 (0x00000080) /* clear ADC14IFG7 */
-/* ADC14CLRIFGR0[CLRADC14IFG8] Bits */
-#define CLRADC14IFG8_OFS ( 8) /* CLRADC14IFG8 Offset */
-#define CLRADC14IFG8 (0x00000100) /* clear ADC14IFG8 */
-/* ADC14CLRIFGR0[CLRADC14IFG9] Bits */
-#define CLRADC14IFG9_OFS ( 9) /* CLRADC14IFG9 Offset */
-#define CLRADC14IFG9 (0x00000200) /* clear ADC14IFG9 */
-/* ADC14CLRIFGR0[CLRADC14IFG10] Bits */
-#define CLRADC14IFG10_OFS (10) /* CLRADC14IFG10 Offset */
-#define CLRADC14IFG10 (0x00000400) /* clear ADC14IFG10 */
-/* ADC14CLRIFGR0[CLRADC14IFG11] Bits */
-#define CLRADC14IFG11_OFS (11) /* CLRADC14IFG11 Offset */
-#define CLRADC14IFG11 (0x00000800) /* clear ADC14IFG11 */
-/* ADC14CLRIFGR0[CLRADC14IFG12] Bits */
-#define CLRADC14IFG12_OFS (12) /* CLRADC14IFG12 Offset */
-#define CLRADC14IFG12 (0x00001000) /* clear ADC14IFG12 */
-/* ADC14CLRIFGR0[CLRADC14IFG13] Bits */
-#define CLRADC14IFG13_OFS (13) /* CLRADC14IFG13 Offset */
-#define CLRADC14IFG13 (0x00002000) /* clear ADC14IFG13 */
-/* ADC14CLRIFGR0[CLRADC14IFG14] Bits */
-#define CLRADC14IFG14_OFS (14) /* CLRADC14IFG14 Offset */
-#define CLRADC14IFG14 (0x00004000) /* clear ADC14IFG14 */
-/* ADC14CLRIFGR0[CLRADC14IFG15] Bits */
-#define CLRADC14IFG15_OFS (15) /* CLRADC14IFG15 Offset */
-#define CLRADC14IFG15 (0x00008000) /* clear ADC14IFG15 */
-/* ADC14CLRIFGR0[CLRADC14IFG16] Bits */
-#define CLRADC14IFG16_OFS (16) /* CLRADC14IFG16 Offset */
-#define CLRADC14IFG16 (0x00010000) /* clear ADC14IFG16 */
-/* ADC14CLRIFGR0[CLRADC14IFG17] Bits */
-#define CLRADC14IFG17_OFS (17) /* CLRADC14IFG17 Offset */
-#define CLRADC14IFG17 (0x00020000) /* clear ADC14IFG17 */
-/* ADC14CLRIFGR0[CLRADC14IFG18] Bits */
-#define CLRADC14IFG18_OFS (18) /* CLRADC14IFG18 Offset */
-#define CLRADC14IFG18 (0x00040000) /* clear ADC14IFG18 */
-/* ADC14CLRIFGR0[CLRADC14IFG19] Bits */
-#define CLRADC14IFG19_OFS (19) /* CLRADC14IFG19 Offset */
-#define CLRADC14IFG19 (0x00080000) /* clear ADC14IFG19 */
-/* ADC14CLRIFGR0[CLRADC14IFG20] Bits */
-#define CLRADC14IFG20_OFS (20) /* CLRADC14IFG20 Offset */
-#define CLRADC14IFG20 (0x00100000) /* clear ADC14IFG20 */
-/* ADC14CLRIFGR0[CLRADC14IFG21] Bits */
-#define CLRADC14IFG21_OFS (21) /* CLRADC14IFG21 Offset */
-#define CLRADC14IFG21 (0x00200000) /* clear ADC14IFG21 */
-/* ADC14CLRIFGR0[CLRADC14IFG22] Bits */
-#define CLRADC14IFG22_OFS (22) /* CLRADC14IFG22 Offset */
-#define CLRADC14IFG22 (0x00400000) /* clear ADC14IFG22 */
-/* ADC14CLRIFGR0[CLRADC14IFG23] Bits */
-#define CLRADC14IFG23_OFS (23) /* CLRADC14IFG23 Offset */
-#define CLRADC14IFG23 (0x00800000) /* clear ADC14IFG23 */
-/* ADC14CLRIFGR0[CLRADC14IFG24] Bits */
-#define CLRADC14IFG24_OFS (24) /* CLRADC14IFG24 Offset */
-#define CLRADC14IFG24 (0x01000000) /* clear ADC14IFG24 */
-/* ADC14CLRIFGR0[CLRADC14IFG25] Bits */
-#define CLRADC14IFG25_OFS (25) /* CLRADC14IFG25 Offset */
-#define CLRADC14IFG25 (0x02000000) /* clear ADC14IFG25 */
-/* ADC14CLRIFGR0[CLRADC14IFG26] Bits */
-#define CLRADC14IFG26_OFS (26) /* CLRADC14IFG26 Offset */
-#define CLRADC14IFG26 (0x04000000) /* clear ADC14IFG26 */
-/* ADC14CLRIFGR0[CLRADC14IFG27] Bits */
-#define CLRADC14IFG27_OFS (27) /* CLRADC14IFG27 Offset */
-#define CLRADC14IFG27 (0x08000000) /* clear ADC14IFG27 */
-/* ADC14CLRIFGR0[CLRADC14IFG28] Bits */
-#define CLRADC14IFG28_OFS (28) /* CLRADC14IFG28 Offset */
-#define CLRADC14IFG28 (0x10000000) /* clear ADC14IFG28 */
-/* ADC14CLRIFGR0[CLRADC14IFG29] Bits */
-#define CLRADC14IFG29_OFS (29) /* CLRADC14IFG29 Offset */
-#define CLRADC14IFG29 (0x20000000) /* clear ADC14IFG29 */
-/* ADC14CLRIFGR0[CLRADC14IFG30] Bits */
-#define CLRADC14IFG30_OFS (30) /* CLRADC14IFG30 Offset */
-#define CLRADC14IFG30 (0x40000000) /* clear ADC14IFG30 */
-/* ADC14CLRIFGR0[CLRADC14IFG31] Bits */
-#define CLRADC14IFG31_OFS (31) /* CLRADC14IFG31 Offset */
-#define CLRADC14IFG31 (0x80000000) /* clear ADC14IFG31 */
-/* ADC14CLRIFGR1[CLRADC14INIFG] Bits */
-#define CLRADC14INIFG_OFS ( 1) /* CLRADC14INIFG Offset */
-#define CLRADC14INIFG (0x00000002) /* clear ADC14INIFG */
-/* ADC14CLRIFGR1[CLRADC14LOIFG] Bits */
-#define CLRADC14LOIFG_OFS ( 2) /* CLRADC14LOIFG Offset */
-#define CLRADC14LOIFG (0x00000004) /* clear ADC14LOIFG */
-/* ADC14CLRIFGR1[CLRADC14HIIFG] Bits */
-#define CLRADC14HIIFG_OFS ( 3) /* CLRADC14HIIFG Offset */
-#define CLRADC14HIIFG (0x00000008) /* clear ADC14HIIFG */
-/* ADC14CLRIFGR1[CLRADC14OVIFG] Bits */
-#define CLRADC14OVIFG_OFS ( 4) /* CLRADC14OVIFG Offset */
-#define CLRADC14OVIFG (0x00000010) /* clear ADC14OVIFG */
-/* ADC14CLRIFGR1[CLRADC14TOVIFG] Bits */
-#define CLRADC14TOVIFG_OFS ( 5) /* CLRADC14TOVIFG Offset */
-#define CLRADC14TOVIFG (0x00000020) /* clear ADC14TOVIFG */
-/* ADC14CLRIFGR1[CLRADC14RDYIFG] Bits */
-#define CLRADC14RDYIFG_OFS ( 6) /* CLRADC14RDYIFG Offset */
-#define CLRADC14RDYIFG (0x00000040) /* clear ADC14RDYIFG */
+/*@}*/ /* end of group WDT_A */
-//*****************************************************************************
-// AES256 Bits
-//*****************************************************************************
-/* AESACTL0[AESOP] Bits */
-#define AESOP0 (0x0001) /* AESOP Bit 0 */
-#define AESOP1 (0x0002) /* AESOP Bit 1 */
-/* AESACTL0[AESOP] Bits */
-#define AESOP_OFS ( 0) /* AESOPx Offset */
-#define AESOP_M (0x0003) /* AES operation */
-//#define AESOP0 (0x0001) /* AES operation */
-//#define AESOP1 (0x0002) /* AES operation */
-#define AESOP_0 (0x0000) /* Encryption */
-#define AESOP_1 (0x0001) /* Decryption. The provided key is the same key used for encryption */
-#define AESOP_2 (0x0002) /* Generate first round key required for decryption */
-#define AESOP_3 (0x0003) /* Decryption. The provided key is the first round key required for decryption */
-/* AESACTL0[AESKL] Bits */
-#define AESKL0 (0x0004) /* AESKL Bit 0 */
-#define AESKL1 (0x0008) /* AESKL Bit 1 */
-/* AESACTL0[AESKL] Bits */
-#define AESKL_OFS ( 2) /* AESKLx Offset */
-#define AESKL_M (0x000c) /* AES key length */
-//#define AESKL0 (0x0004) /* AES key length */
-//#define AESKL1 (0x0008) /* AES key length */
-#define AESKL_0 (0x0000) /* AES128. The key size is 128 bit */
-#define AESKL_1 (0x0004) /* AES192. The key size is 192 bit. */
-#define AESKL_2 (0x0008) /* AES256. The key size is 256 bit */
-#define AESKL__128BIT (0x0000) /* AES128. The key size is 128 bit */
-#define AESKL__192BIT (0x0004) /* AES192. The key size is 192 bit. */
-#define AESKL__256BIT (0x0008) /* AES256. The key size is 256 bit */
-/* AESACTL0[AESCM] Bits */
-#define AESCM0 (0x0020) /* AESCM Bit 0 */
-#define AESCM1 (0x0040) /* AESCM Bit 1 */
-/* AESACTL0[AESCM] Bits */
-#define AESCM_OFS ( 5) /* AESCMx Offset */
-#define AESCM_M (0x0060) /* AES cipher mode select */
-//#define AESCM0 (0x0020) /* AES cipher mode select */
-//#define AESCM1 (0x0040) /* AES cipher mode select */
-#define AESCM_0 (0x0000) /* ECB */
-#define AESCM_1 (0x0020) /* CBC */
-#define AESCM_2 (0x0040) /* OFB */
-#define AESCM_3 (0x0060) /* CFB */
-#define AESCM__ECB (0x0000) /* ECB */
-#define AESCM__CBC (0x0020) /* CBC */
-#define AESCM__OFB (0x0040) /* OFB */
-#define AESCM__CFB (0x0060) /* CFB */
-/* AESACTL0[AESSWRST] Bits */
-#define AESSWRST_OFS ( 7) /* AESSWRST Offset */
-#define AESSWRST (0x0080) /* AES software reset */
-/* AESACTL0[AESRDYIFG] Bits */
-#define AESRDYIFG_OFS ( 8) /* AESRDYIFG Offset */
-#define AESRDYIFG (0x0100) /* AES ready interrupt flag */
-/* AESACTL0[AESERRFG] Bits */
-#define AESERRFG_OFS (11) /* AESERRFG Offset */
-#define AESERRFG (0x0800) /* AES error flag */
-/* AESACTL0[AESRDYIE] Bits */
-#define AESRDYIE_OFS (12) /* AESRDYIE Offset */
-#define AESRDYIE (0x1000) /* AES ready interrupt enable */
-/* AESACTL0[AESCMEN] Bits */
-#define AESCMEN_OFS (15) /* AESCMEN Offset */
-#define AESCMEN (0x8000) /* AES cipher mode enable */
-/* AESACTL1[AESBLKCNT] Bits */
-#define AESBLKCNT0 (0x0001) /* AESBLKCNT Bit 0 */
-#define AESBLKCNT1 (0x0002) /* AESBLKCNT Bit 1 */
-#define AESBLKCNT2 (0x0004) /* AESBLKCNT Bit 2 */
-#define AESBLKCNT3 (0x0008) /* AESBLKCNT Bit 3 */
-#define AESBLKCNT4 (0x0010) /* AESBLKCNT Bit 4 */
-#define AESBLKCNT5 (0x0020) /* AESBLKCNT Bit 5 */
-#define AESBLKCNT6 (0x0040) /* AESBLKCNT Bit 6 */
-#define AESBLKCNT7 (0x0080) /* AESBLKCNT Bit 7 */
-/* AESACTL1[AESBLKCNT] Bits */
-#define AESBLKCNT_OFS ( 0) /* AESBLKCNTx Offset */
-#define AESBLKCNT_M (0x00ff) /* Cipher Block Counter */
-/* AESASTAT[AESBUSY] Bits */
-#define AESBUSY_OFS ( 0) /* AESBUSY Offset */
-#define AESBUSY (0x0001) /* AES accelerator module busy */
-/* AESASTAT[AESKEYWR] Bits */
-#define AESKEYWR_OFS ( 1) /* AESKEYWR Offset */
-#define AESKEYWR (0x0002) /* All 16 bytes written to AESAKEY */
-/* AESASTAT[AESDINWR] Bits */
-#define AESDINWR_OFS ( 2) /* AESDINWR Offset */
-#define AESDINWR (0x0004) /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
-/* AESASTAT[AESDOUTRD] Bits */
-#define AESDOUTRD_OFS ( 3) /* AESDOUTRD Offset */
-#define AESDOUTRD (0x0008) /* All 16 bytes read from AESADOUT */
-/* AESASTAT[AESKEYCNT] Bits */
-#define AESKEYCNT0 (0x0010) /* AESKEYCNT Bit 0 */
-#define AESKEYCNT1 (0x0020) /* AESKEYCNT Bit 1 */
-#define AESKEYCNT2 (0x0040) /* AESKEYCNT Bit 2 */
-#define AESKEYCNT3 (0x0080) /* AESKEYCNT Bit 3 */
-/* AESASTAT[AESKEYCNT] Bits */
-#define AESKEYCNT_OFS ( 4) /* AESKEYCNTx Offset */
-#define AESKEYCNT_M (0x00f0) /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
-/* AESASTAT[AESDINCNT] Bits */
-#define AESDINCNT0 (0x0100) /* AESDINCNT Bit 0 */
-#define AESDINCNT1 (0x0200) /* AESDINCNT Bit 1 */
-#define AESDINCNT2 (0x0400) /* AESDINCNT Bit 2 */
-#define AESDINCNT3 (0x0800) /* AESDINCNT Bit 3 */
-/* AESASTAT[AESDINCNT] Bits */
-#define AESDINCNT_OFS ( 8) /* AESDINCNTx Offset */
-#define AESDINCNT_M (0x0f00) /* Bytes written via AESADIN, AESAXDIN or AESAXIN */
-/* AESASTAT[AESDOUTCNT] Bits */
-#define AESDOUTCNT0 (0x1000) /* AESDOUTCNT Bit 0 */
-#define AESDOUTCNT1 (0x2000) /* AESDOUTCNT Bit 1 */
-#define AESDOUTCNT2 (0x4000) /* AESDOUTCNT Bit 2 */
-#define AESDOUTCNT3 (0x8000) /* AESDOUTCNT Bit 3 */
-/* AESASTAT[AESDOUTCNT] Bits */
-#define AESDOUTCNT_OFS (12) /* AESDOUTCNTx Offset */
-#define AESDOUTCNT_M (0xf000) /* Bytes read via AESADOUT */
-/* AESAKEY[AESKEY0] Bits */
-#define AESKEY00 (0x0001) /* AESKEY0 Bit 0 */
-#define AESKEY01 (0x0002) /* AESKEY0 Bit 1 */
-#define AESKEY02 (0x0004) /* AESKEY0 Bit 2 */
-#define AESKEY03 (0x0008) /* AESKEY0 Bit 3 */
-#define AESKEY04 (0x0010) /* AESKEY0 Bit 4 */
-#define AESKEY05 (0x0020) /* AESKEY0 Bit 5 */
-#define AESKEY06 (0x0040) /* AESKEY0 Bit 6 */
-#define AESKEY07 (0x0080) /* AESKEY0 Bit 7 */
-/* AESAKEY[AESKEY0] Bits */
-#define AESKEY0_OFS ( 0) /* AESKEY0x Offset */
-#define AESKEY0_M (0x00ff) /* AES key byte n when AESAKEY is written as half-word */
-/* AESAKEY[AESKEY1] Bits */
-#define AESKEY10 (0x0100) /* AESKEY1 Bit 0 */
-#define AESKEY11 (0x0200) /* AESKEY1 Bit 1 */
-#define AESKEY12 (0x0400) /* AESKEY1 Bit 2 */
-#define AESKEY13 (0x0800) /* AESKEY1 Bit 3 */
-#define AESKEY14 (0x1000) /* AESKEY1 Bit 4 */
-#define AESKEY15 (0x2000) /* AESKEY1 Bit 5 */
-#define AESKEY16 (0x4000) /* AESKEY1 Bit 6 */
-#define AESKEY17 (0x8000) /* AESKEY1 Bit 7 */
-/* AESAKEY[AESKEY1] Bits */
-#define AESKEY1_OFS ( 8) /* AESKEY1x Offset */
-#define AESKEY1_M (0xff00) /* AES key byte n+1 when AESAKEY is written as half-word */
-/* AESADIN[AESDIN0] Bits */
-#define AESDIN00 (0x0001) /* AESDIN0 Bit 0 */
-#define AESDIN01 (0x0002) /* AESDIN0 Bit 1 */
-#define AESDIN02 (0x0004) /* AESDIN0 Bit 2 */
-#define AESDIN03 (0x0008) /* AESDIN0 Bit 3 */
-#define AESDIN04 (0x0010) /* AESDIN0 Bit 4 */
-#define AESDIN05 (0x0020) /* AESDIN0 Bit 5 */
-#define AESDIN06 (0x0040) /* AESDIN0 Bit 6 */
-#define AESDIN07 (0x0080) /* AESDIN0 Bit 7 */
-/* AESADIN[AESDIN0] Bits */
-#define AESDIN0_OFS ( 0) /* AESDIN0x Offset */
-#define AESDIN0_M (0x00ff) /* AES data in byte n when AESADIN is written as half-word */
-/* AESADIN[AESDIN1] Bits */
-#define AESDIN10 (0x0100) /* AESDIN1 Bit 0 */
-#define AESDIN11 (0x0200) /* AESDIN1 Bit 1 */
-#define AESDIN12 (0x0400) /* AESDIN1 Bit 2 */
-#define AESDIN13 (0x0800) /* AESDIN1 Bit 3 */
-#define AESDIN14 (0x1000) /* AESDIN1 Bit 4 */
-#define AESDIN15 (0x2000) /* AESDIN1 Bit 5 */
-#define AESDIN16 (0x4000) /* AESDIN1 Bit 6 */
-#define AESDIN17 (0x8000) /* AESDIN1 Bit 7 */
-/* AESADIN[AESDIN1] Bits */
-#define AESDIN1_OFS ( 8) /* AESDIN1x Offset */
-#define AESDIN1_M (0xff00) /* AES data in byte n+1 when AESADIN is written as half-word */
-/* AESADOUT[AESDOUT0] Bits */
-#define AESDOUT00 (0x0001) /* AESDOUT0 Bit 0 */
-#define AESDOUT01 (0x0002) /* AESDOUT0 Bit 1 */
-#define AESDOUT02 (0x0004) /* AESDOUT0 Bit 2 */
-#define AESDOUT03 (0x0008) /* AESDOUT0 Bit 3 */
-#define AESDOUT04 (0x0010) /* AESDOUT0 Bit 4 */
-#define AESDOUT05 (0x0020) /* AESDOUT0 Bit 5 */
-#define AESDOUT06 (0x0040) /* AESDOUT0 Bit 6 */
-#define AESDOUT07 (0x0080) /* AESDOUT0 Bit 7 */
-/* AESADOUT[AESDOUT0] Bits */
-#define AESDOUT0_OFS ( 0) /* AESDOUT0x Offset */
-#define AESDOUT0_M (0x00ff) /* AES data out byte n when AESADOUT is read as half-word */
-/* AESADOUT[AESDOUT1] Bits */
-#define AESDOUT10 (0x0100) /* AESDOUT1 Bit 0 */
-#define AESDOUT11 (0x0200) /* AESDOUT1 Bit 1 */
-#define AESDOUT12 (0x0400) /* AESDOUT1 Bit 2 */
-#define AESDOUT13 (0x0800) /* AESDOUT1 Bit 3 */
-#define AESDOUT14 (0x1000) /* AESDOUT1 Bit 4 */
-#define AESDOUT15 (0x2000) /* AESDOUT1 Bit 5 */
-#define AESDOUT16 (0x4000) /* AESDOUT1 Bit 6 */
-#define AESDOUT17 (0x8000) /* AESDOUT1 Bit 7 */
-/* AESADOUT[AESDOUT1] Bits */
-#define AESDOUT1_OFS ( 8) /* AESDOUT1x Offset */
-#define AESDOUT1_M (0xff00) /* AES data out byte n+1 when AESADOUT is read as half-word */
-/* AESAXDIN[AESXDIN0] Bits */
-#define AESXDIN00 (0x0001) /* AESXDIN0 Bit 0 */
-#define AESXDIN01 (0x0002) /* AESXDIN0 Bit 1 */
-#define AESXDIN02 (0x0004) /* AESXDIN0 Bit 2 */
-#define AESXDIN03 (0x0008) /* AESXDIN0 Bit 3 */
-#define AESXDIN04 (0x0010) /* AESXDIN0 Bit 4 */
-#define AESXDIN05 (0x0020) /* AESXDIN0 Bit 5 */
-#define AESXDIN06 (0x0040) /* AESXDIN0 Bit 6 */
-#define AESXDIN07 (0x0080) /* AESXDIN0 Bit 7 */
-/* AESAXDIN[AESXDIN0] Bits */
-#define AESXDIN0_OFS ( 0) /* AESXDIN0x Offset */
-#define AESXDIN0_M (0x00ff) /* AES data in byte n when AESAXDIN is written as half-word */
-/* AESAXDIN[AESXDIN1] Bits */
-#define AESXDIN10 (0x0100) /* AESXDIN1 Bit 0 */
-#define AESXDIN11 (0x0200) /* AESXDIN1 Bit 1 */
-#define AESXDIN12 (0x0400) /* AESXDIN1 Bit 2 */
-#define AESXDIN13 (0x0800) /* AESXDIN1 Bit 3 */
-#define AESXDIN14 (0x1000) /* AESXDIN1 Bit 4 */
-#define AESXDIN15 (0x2000) /* AESXDIN1 Bit 5 */
-#define AESXDIN16 (0x4000) /* AESXDIN1 Bit 6 */
-#define AESXDIN17 (0x8000) /* AESXDIN1 Bit 7 */
-/* AESAXDIN[AESXDIN1] Bits */
-#define AESXDIN1_OFS ( 8) /* AESXDIN1x Offset */
-#define AESXDIN1_M (0xff00) /* AES data in byte n+1 when AESAXDIN is written as half-word */
-/* AESAXIN[AESXIN0] Bits */
-#define AESXIN00 (0x0001) /* AESXIN0 Bit 0 */
-#define AESXIN01 (0x0002) /* AESXIN0 Bit 1 */
-#define AESXIN02 (0x0004) /* AESXIN0 Bit 2 */
-#define AESXIN03 (0x0008) /* AESXIN0 Bit 3 */
-#define AESXIN04 (0x0010) /* AESXIN0 Bit 4 */
-#define AESXIN05 (0x0020) /* AESXIN0 Bit 5 */
-#define AESXIN06 (0x0040) /* AESXIN0 Bit 6 */
-#define AESXIN07 (0x0080) /* AESXIN0 Bit 7 */
-/* AESAXIN[AESXIN0] Bits */
-#define AESXIN0_OFS ( 0) /* AESXIN0x Offset */
-#define AESXIN0_M (0x00ff) /* AES data in byte n when AESAXIN is written as half-word */
-/* AESAXIN[AESXIN1] Bits */
-#define AESXIN10 (0x0100) /* AESXIN1 Bit 0 */
-#define AESXIN11 (0x0200) /* AESXIN1 Bit 1 */
-#define AESXIN12 (0x0400) /* AESXIN1 Bit 2 */
-#define AESXIN13 (0x0800) /* AESXIN1 Bit 3 */
-#define AESXIN14 (0x1000) /* AESXIN1 Bit 4 */
-#define AESXIN15 (0x2000) /* AESXIN1 Bit 5 */
-#define AESXIN16 (0x4000) /* AESXIN1 Bit 6 */
-#define AESXIN17 (0x8000) /* AESXIN1 Bit 7 */
-/* AESAXIN[AESXIN1] Bits */
-#define AESXIN1_OFS ( 8) /* AESXIN1x Offset */
-#define AESXIN1_M (0xff00) /* AES data in byte n+1 when AESAXIN is written as half-word */
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group MSP432P401R_Peripherals */
+
+/******************************************************************************
+* Peripheral declaration *
+******************************************************************************/
+/** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration
+ @{
+*/
+
+#define ADC14 ((ADC14_Type *) ADC14_BASE)
+#define AES256 ((AES256_Type *) AES256_BASE)
+#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE)
+#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE)
+#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE)
+#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE)
+#define CRC32 ((CRC32_Type *) CRC32_BASE)
+#define CS ((CS_Type *) CS_BASE)
+#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000))
+#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020))
+#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040))
+#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060))
+#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080))
+#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120))
+#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000))
+#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000))
+#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020))
+#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020))
+#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040))
+#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040))
+#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060))
+#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060))
+#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080))
+#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080))
+#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE)
+#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000))
+#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE)
+#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE)
+#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE)
+#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE)
+#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE)
+#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE)
+#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE)
+#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE)
+#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE)
+#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE)
+#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE)
+#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE)
+#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE)
+#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE)
+#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE)
+#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE)
+#define FLCTL ((FLCTL_Type *) FLCTL_BASE)
+#define PCM ((PCM_Type *) PCM_BASE)
+#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE)
+#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008))
+#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010))
+#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018))
+#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020))
+#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028))
+#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030))
+#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038))
+#define PSS ((PSS_Type *) PSS_BASE)
+#define REF_A ((REF_A_Type *) REF_A_BASE)
+#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE)
+#define RTC_C ((RTC_C_Type *) RTC_C_BASE)
+#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE)
+#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE)
+#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000))
+#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE)
+#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020))
+#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE)
+#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE)
+#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE)
+#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE)
+#define TLV ((TLV_Type *) TLV_BASE)
+#define WDT_A ((WDT_A_Type *) WDT_A_BASE)
-//*****************************************************************************
-// CAPTIO0 Bits
-//*****************************************************************************
-/* CAPTIO0CTL[CAPTIOPISEL] Bits */
-#define CAPTIOPISEL0 (0x0002) /* CAPTIOPISEL Bit 0 */
-#define CAPTIOPISEL1 (0x0004) /* CAPTIOPISEL Bit 1 */
-#define CAPTIOPISEL2 (0x0008) /* CAPTIOPISEL Bit 2 */
-/* CAPTIO0CTL[CAPTIOPISEL] Bits */
-#define CAPTIOPISEL_OFS ( 1) /* CAPTIOPISELx Offset */
-#define CAPTIOPISEL_M (0x000e) /* Capacitive Touch IO pin select */
-//#define CAPTIOPISEL0 (0x0002) /* Capacitive Touch IO pin select */
-//#define CAPTIOPISEL1 (0x0004) /* Capacitive Touch IO pin select */
-//#define CAPTIOPISEL2 (0x0008) /* Capacitive Touch IO pin select */
-#define CAPTIOPISEL_0 (0x0000) /* Px.0 */
-#define CAPTIOPISEL_1 (0x0002) /* Px.1 */
-#define CAPTIOPISEL_2 (0x0004) /* Px.2 */
-#define CAPTIOPISEL_3 (0x0006) /* Px.3 */
-#define CAPTIOPISEL_4 (0x0008) /* Px.4 */
-#define CAPTIOPISEL_5 (0x000a) /* Px.5 */
-#define CAPTIOPISEL_6 (0x000c) /* Px.6 */
-#define CAPTIOPISEL_7 (0x000e) /* Px.7 */
-/* CAPTIO0CTL[CAPTIOPOSEL] Bits */
-#define CAPTIOPOSEL0 (0x0010) /* CAPTIOPOSEL Bit 0 */
-#define CAPTIOPOSEL1 (0x0020) /* CAPTIOPOSEL Bit 1 */
-#define CAPTIOPOSEL2 (0x0040) /* CAPTIOPOSEL Bit 2 */
-#define CAPTIOPOSEL3 (0x0080) /* CAPTIOPOSEL Bit 3 */
-/* CAPTIO0CTL[CAPTIOPOSEL] Bits */
-#define CAPTIOPOSEL_OFS ( 4) /* CAPTIOPOSELx Offset */
-#define CAPTIOPOSEL_M (0x00f0) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL0 (0x0010) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL1 (0x0020) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL2 (0x0040) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL3 (0x0080) /* Capacitive Touch IO port select */
-#define CAPTIOPOSEL_0 (0x0000) /* Px = PJ */
-#define CAPTIOPOSEL_1 (0x0010) /* Px = P1 */
-#define CAPTIOPOSEL_2 (0x0020) /* Px = P2 */
-#define CAPTIOPOSEL_3 (0x0030) /* Px = P3 */
-#define CAPTIOPOSEL_4 (0x0040) /* Px = P4 */
-#define CAPTIOPOSEL_5 (0x0050) /* Px = P5 */
-#define CAPTIOPOSEL_6 (0x0060) /* Px = P6 */
-#define CAPTIOPOSEL_7 (0x0070) /* Px = P7 */
-#define CAPTIOPOSEL_8 (0x0080) /* Px = P8 */
-#define CAPTIOPOSEL_9 (0x0090) /* Px = P9 */
-#define CAPTIOPOSEL_10 (0x00a0) /* Px = P10 */
-#define CAPTIOPOSEL_11 (0x00b0) /* Px = P11 */
-#define CAPTIOPOSEL_12 (0x00c0) /* Px = P12 */
-#define CAPTIOPOSEL_13 (0x00d0) /* Px = P13 */
-#define CAPTIOPOSEL_14 (0x00e0) /* Px = P14 */
-#define CAPTIOPOSEL_15 (0x00f0) /* Px = P15 */
-#define CAPTIOPOSEL__PJ (0x0000) /* Px = PJ */
-#define CAPTIOPOSEL__P1 (0x0010) /* Px = P1 */
-#define CAPTIOPOSEL__P2 (0x0020) /* Px = P2 */
-#define CAPTIOPOSEL__P3 (0x0030) /* Px = P3 */
-#define CAPTIOPOSEL__P4 (0x0040) /* Px = P4 */
-#define CAPTIOPOSEL__P5 (0x0050) /* Px = P5 */
-#define CAPTIOPOSEL__P6 (0x0060) /* Px = P6 */
-#define CAPTIOPOSEL__P7 (0x0070) /* Px = P7 */
-#define CAPTIOPOSEL__P8 (0x0080) /* Px = P8 */
-#define CAPTIOPOSEL__P9 (0x0090) /* Px = P9 */
-#define CAPTIOPOSEL__P10 (0x00a0) /* Px = P10 */
-#define CAPTIOPOSEL__P11 (0x00b0) /* Px = P11 */
-#define CAPTIOPOSEL__P12 (0x00c0) /* Px = P12 */
-#define CAPTIOPOSEL__P13 (0x00d0) /* Px = P13 */
-#define CAPTIOPOSEL__P14 (0x00e0) /* Px = P14 */
-#define CAPTIOPOSEL__P15 (0x00f0) /* Px = P15 */
-/* CAPTIO0CTL[CAPTIOEN] Bits */
-#define CAPTIOEN_OFS ( 8) /* CAPTIOEN Offset */
-#define CAPTIOEN (0x0100) /* Capacitive Touch IO enable */
-/* CAPTIO0CTL[CAPTIOSTATE] Bits */
-#define CAPTIOSTATE_OFS ( 9) /* CAPTIOSTATE Offset */
-#define CAPTIOSTATE (0x0200) /* Capacitive Touch IO state */
+/*@}*/ /* end of group MSP432P401R_PeripheralDecl */
+
+/*@}*/ /* end of group MSP432P401R_Definitions */
+
+#endif /* __CMSIS_CONFIG__ */
+
+/******************************************************************************
+* Peripheral register control bits *
+******************************************************************************/
+
+/******************************************************************************
+* ADC14 Bits
+******************************************************************************/
+/* ADC14_CTL0[SC] Bits */
+#define ADC14_CTL0_SC_OFS ( 0) /**< ADC14SC Bit Offset */
+#define ADC14_CTL0_SC ((uint32_t)0x00000001) /**< ADC14 start conversion */
+/* ADC14_CTL0[ENC] Bits */
+#define ADC14_CTL0_ENC_OFS ( 1) /**< ADC14ENC Bit Offset */
+#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /**< ADC14 enable conversion */
+/* ADC14_CTL0[ON] Bits */
+#define ADC14_CTL0_ON_OFS ( 4) /**< ADC14ON Bit Offset */
+#define ADC14_CTL0_ON ((uint32_t)0x00000010) /**< ADC14 on */
+/* ADC14_CTL0[MSC] Bits */
+#define ADC14_CTL0_MSC_OFS ( 7) /**< ADC14MSC Bit Offset */
+#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /**< ADC14 multiple sample and conversion */
+/* ADC14_CTL0[SHT0] Bits */
+#define ADC14_CTL0_SHT0_OFS ( 8) /**< ADC14SHT0 Bit Offset */
+#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /**< ADC14SHT0 Bit Mask */
+#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /**< SHT0 Bit 0 */
+#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /**< SHT0 Bit 1 */
+#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /**< SHT0 Bit 2 */
+#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /**< SHT0 Bit 3 */
+#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /**< 4 */
+#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /**< 8 */
+#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /**< 16 */
+#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /**< 32 */
+#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /**< 64 */
+#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /**< 96 */
+#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /**< 128 */
+#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /**< 192 */
+#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /**< 4 */
+#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /**< 8 */
+#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /**< 16 */
+#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /**< 32 */
+#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /**< 64 */
+#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /**< 96 */
+#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /**< 128 */
+#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /**< 192 */
+/* ADC14_CTL0[SHT1] Bits */
+#define ADC14_CTL0_SHT1_OFS (12) /**< ADC14SHT1 Bit Offset */
+#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /**< ADC14SHT1 Bit Mask */
+#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /**< SHT1 Bit 0 */
+#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /**< SHT1 Bit 1 */
+#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /**< SHT1 Bit 2 */
+#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /**< SHT1 Bit 3 */
+#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /**< 4 */
+#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /**< 8 */
+#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /**< 16 */
+#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /**< 32 */
+#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /**< 64 */
+#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /**< 96 */
+#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /**< 128 */
+#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /**< 192 */
+#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /**< 4 */
+#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /**< 8 */
+#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /**< 16 */
+#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /**< 32 */
+#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /**< 64 */
+#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /**< 96 */
+#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /**< 128 */
+#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /**< 192 */
+/* ADC14_CTL0[BUSY] Bits */
+#define ADC14_CTL0_BUSY_OFS (16) /**< ADC14BUSY Bit Offset */
+#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /**< ADC14 busy */
+/* ADC14_CTL0[CONSEQ] Bits */
+#define ADC14_CTL0_CONSEQ_OFS (17) /**< ADC14CONSEQ Bit Offset */
+#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /**< ADC14CONSEQ Bit Mask */
+#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /**< CONSEQ Bit 0 */
+#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /**< CONSEQ Bit 1 */
+#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /**< Single-channel, single-conversion */
+#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /**< Sequence-of-channels */
+#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /**< Repeat-single-channel */
+#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /**< Repeat-sequence-of-channels */
+/* ADC14_CTL0[SSEL] Bits */
+#define ADC14_CTL0_SSEL_OFS (19) /**< ADC14SSEL Bit Offset */
+#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /**< ADC14SSEL Bit Mask */
+#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /**< SSEL Bit 0 */
+#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /**< SSEL Bit 1 */
+#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /**< SSEL Bit 2 */
+#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /**< MODCLK */
+#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /**< SYSCLK */
+#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /**< ACLK */
+#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /**< MCLK */
+#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /**< SMCLK */
+#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /**< HSMCLK */
+#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /**< MODCLK */
+#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /**< SYSCLK */
+#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /**< ACLK */
+#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /**< MCLK */
+#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /**< SMCLK */
+#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /**< HSMCLK */
+/* ADC14_CTL0[DIV] Bits */
+#define ADC14_CTL0_DIV_OFS (22) /**< ADC14DIV Bit Offset */
+#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /**< ADC14DIV Bit Mask */
+#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /**< DIV Bit 0 */
+#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /**< DIV Bit 1 */
+#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /**< DIV Bit 2 */
+#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /**< /1 */
+#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /**< /2 */
+#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /**< /3 */
+#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /**< /4 */
+#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /**< /5 */
+#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /**< /6 */
+#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /**< /7 */
+#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /**< /8 */
+#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /**< /1 */
+#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /**< /2 */
+#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /**< /3 */
+#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /**< /4 */
+#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /**< /5 */
+#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /**< /6 */
+#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /**< /7 */
+#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /**< /8 */
+/* ADC14_CTL0[ISSH] Bits */
+#define ADC14_CTL0_ISSH_OFS (25) /**< ADC14ISSH Bit Offset */
+#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /**< ADC14 invert signal sample-and-hold */
+/* ADC14_CTL0[SHP] Bits */
+#define ADC14_CTL0_SHP_OFS (26) /**< ADC14SHP Bit Offset */
+#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /**< ADC14 sample-and-hold pulse-mode select */
+/* ADC14_CTL0[SHS] Bits */
+#define ADC14_CTL0_SHS_OFS (27) /**< ADC14SHS Bit Offset */
+#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /**< ADC14SHS Bit Mask */
+#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /**< SHS Bit 0 */
+#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /**< SHS Bit 1 */
+#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /**< SHS Bit 2 */
+#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /**< ADC14SC bit */
+#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /**< See device-specific data sheet for source */
+#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /**< See device-specific data sheet for source */
+#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /**< See device-specific data sheet for source */
+#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /**< See device-specific data sheet for source */
+#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /**< See device-specific data sheet for source */
+#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /**< See device-specific data sheet for source */
+#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /**< See device-specific data sheet for source */
+/* ADC14_CTL0[PDIV] Bits */
+#define ADC14_CTL0_PDIV_OFS (30) /**< ADC14PDIV Bit Offset */
+#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /**< ADC14PDIV Bit Mask */
+#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /**< PDIV Bit 0 */
+#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /**< PDIV Bit 1 */
+#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /**< Predivide by 1 */
+#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /**< Predivide by 4 */
+#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /**< Predivide by 32 */
+#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /**< Predivide by 64 */
+#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /**< Predivide by 1 */
+#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /**< Predivide by 4 */
+#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /**< Predivide by 32 */
+#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /**< Predivide by 64 */
+/* ADC14_CTL1[PWRMD] Bits */
+#define ADC14_CTL1_PWRMD_OFS ( 0) /**< ADC14PWRMD Bit Offset */
+#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /**< ADC14PWRMD Bit Mask */
+#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /**< PWRMD Bit 0 */
+#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /**< PWRMD Bit 1 */
+#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /**< Regular power mode for use with any resolution setting. Sample rate can be up */
+ /* to 1 Msps. */
+#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /**< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate */
+ /* must not exceed 200 ksps. */
+/* ADC14_CTL1[REFBURST] Bits */
+#define ADC14_CTL1_REFBURST_OFS ( 2) /**< ADC14REFBURST Bit Offset */
+#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /**< ADC14 reference buffer burst */
+/* ADC14_CTL1[DF] Bits */
+#define ADC14_CTL1_DF_OFS ( 3) /**< ADC14DF Bit Offset */
+#define ADC14_CTL1_DF ((uint32_t)0x00000008) /**< ADC14 data read-back format */
+/* ADC14_CTL1[RES] Bits */
+#define ADC14_CTL1_RES_OFS ( 4) /**< ADC14RES Bit Offset */
+#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /**< ADC14RES Bit Mask */
+#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /**< RES Bit 0 */
+#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /**< RES Bit 1 */
+#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /**< 8 bit (9 clock cycle conversion time) */
+#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /**< 10 bit (11 clock cycle conversion time) */
+#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /**< 12 bit (14 clock cycle conversion time) */
+#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /**< 14 bit (16 clock cycle conversion time) */
+#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /**< 8 bit (9 clock cycle conversion time) */
+#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /**< 10 bit (11 clock cycle conversion time) */
+#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /**< 12 bit (14 clock cycle conversion time) */
+#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /**< 14 bit (16 clock cycle conversion time) */
+/* ADC14_CTL1[CSTARTADD] Bits */
+#define ADC14_CTL1_CSTARTADD_OFS (16) /**< ADC14CSTARTADD Bit Offset */
+#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /**< ADC14CSTARTADD Bit Mask */
+/* ADC14_CTL1[BATMAP] Bits */
+#define ADC14_CTL1_BATMAP_OFS (22) /**< ADC14BATMAP Bit Offset */
+#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /**< Controls 1/2 AVCC ADC input channel selection */
+/* ADC14_CTL1[TCMAP] Bits */
+#define ADC14_CTL1_TCMAP_OFS (23) /**< ADC14TCMAP Bit Offset */
+#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /**< Controls temperature sensor ADC input channel selection */
+/* ADC14_CTL1[CH0MAP] Bits */
+#define ADC14_CTL1_CH0MAP_OFS (24) /**< ADC14CH0MAP Bit Offset */
+#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /**< Controls internal channel 0 selection to ADC input channel MAX-2 */
+/* ADC14_CTL1[CH1MAP] Bits */
+#define ADC14_CTL1_CH1MAP_OFS (25) /**< ADC14CH1MAP Bit Offset */
+#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /**< Controls internal channel 1 selection to ADC input channel MAX-3 */
+/* ADC14_CTL1[CH2MAP] Bits */
+#define ADC14_CTL1_CH2MAP_OFS (26) /**< ADC14CH2MAP Bit Offset */
+#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /**< Controls internal channel 2 selection to ADC input channel MAX-4 */
+/* ADC14_CTL1[CH3MAP] Bits */
+#define ADC14_CTL1_CH3MAP_OFS (27) /**< ADC14CH3MAP Bit Offset */
+#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /**< Controls internal channel 3 selection to ADC input channel MAX-5 */
+/* ADC14_LO0[LO0] Bits */
+#define ADC14_LO0_LO0_OFS ( 0) /**< ADC14LO0 Bit Offset */
+#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /**< ADC14LO0 Bit Mask */
+/* ADC14_HI0[HI0] Bits */
+#define ADC14_HI0_HI0_OFS ( 0) /**< ADC14HI0 Bit Offset */
+#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /**< ADC14HI0 Bit Mask */
+/* ADC14_LO1[LO1] Bits */
+#define ADC14_LO1_LO1_OFS ( 0) /**< ADC14LO1 Bit Offset */
+#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /**< ADC14LO1 Bit Mask */
+/* ADC14_HI1[HI1] Bits */
+#define ADC14_HI1_HI1_OFS ( 0) /**< ADC14HI1 Bit Offset */
+#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /**< ADC14HI1 Bit Mask */
+/* ADC14_MCTLN[INCH] Bits */
+#define ADC14_MCTLN_INCH_OFS ( 0) /**< ADC14INCH Bit Offset */
+#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /**< ADC14INCH Bit Mask */
+#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /**< INCH Bit 0 */
+#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /**< INCH Bit 1 */
+#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /**< INCH Bit 2 */
+#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /**< INCH Bit 3 */
+#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /**< INCH Bit 4 */
+#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /**< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
+#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /**< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
+#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /**< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
+#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /**< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
+#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /**< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
+#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /**< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
+#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /**< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
+#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /**< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
+#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /**< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
+#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /**< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
+#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /**< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
+#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /**< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
+#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /**< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
+#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /**< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
+#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /**< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
+#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /**< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
+#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /**< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
+#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /**< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
+#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /**< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
+#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /**< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
+#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /**< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
+#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /**< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
+#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /**< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
+#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /**< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
+#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /**< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
+#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /**< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
+#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /**< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
+#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /**< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
+#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /**< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
+#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /**< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
+#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /**< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
+#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /**< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
+/* ADC14_MCTLN[EOS] Bits */
+#define ADC14_MCTLN_EOS_OFS ( 7) /**< ADC14EOS Bit Offset */
+#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /**< End of sequence */
+/* ADC14_MCTLN[VRSEL] Bits */
+#define ADC14_MCTLN_VRSEL_OFS ( 8) /**< ADC14VRSEL Bit Offset */
+#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /**< ADC14VRSEL Bit Mask */
+#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /**< VRSEL Bit 0 */
+#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /**< VRSEL Bit 1 */
+#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /**< VRSEL Bit 2 */
+#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /**< VRSEL Bit 3 */
+#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /**< V(R+) = AVCC, V(R-) = AVSS */
+#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /**< V(R+) = VREF buffered, V(R-) = AVSS */
+#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /**< V(R+) = VeREF+, V(R-) = VeREF- */
+#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /**< V(R+) = VeREF+ buffered, V(R-) = VeREF */
+/* ADC14_MCTLN[DIF] Bits */
+#define ADC14_MCTLN_DIF_OFS (13) /**< ADC14DIF Bit Offset */
+#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /**< Differential mode */
+/* ADC14_MCTLN[WINC] Bits */
+#define ADC14_MCTLN_WINC_OFS (14) /**< ADC14WINC Bit Offset */
+#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /**< Comparator window enable */
+/* ADC14_MCTLN[WINCTH] Bits */
+#define ADC14_MCTLN_WINCTH_OFS (15) /**< ADC14WINCTH Bit Offset */
+#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /**< Window comparator threshold register selection */
+/* ADC14_MEMN[CONVRES] Bits */
+#define ADC14_MEMN_CONVRES_OFS ( 0) /**< Conversion_Results Bit Offset */
+#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /**< Conversion_Results Bit Mask */
+/* ADC14_IER0[IE0] Bits */
+#define ADC14_IER0_IE0_OFS ( 0) /**< ADC14IE0 Bit Offset */
+#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /**< Interrupt enable */
+/* ADC14_IER0[IE1] Bits */
+#define ADC14_IER0_IE1_OFS ( 1) /**< ADC14IE1 Bit Offset */
+#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /**< Interrupt enable */
+/* ADC14_IER0[IE2] Bits */
+#define ADC14_IER0_IE2_OFS ( 2) /**< ADC14IE2 Bit Offset */
+#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /**< Interrupt enable */
+/* ADC14_IER0[IE3] Bits */
+#define ADC14_IER0_IE3_OFS ( 3) /**< ADC14IE3 Bit Offset */
+#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /**< Interrupt enable */
+/* ADC14_IER0[IE4] Bits */
+#define ADC14_IER0_IE4_OFS ( 4) /**< ADC14IE4 Bit Offset */
+#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /**< Interrupt enable */
+/* ADC14_IER0[IE5] Bits */
+#define ADC14_IER0_IE5_OFS ( 5) /**< ADC14IE5 Bit Offset */
+#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /**< Interrupt enable */
+/* ADC14_IER0[IE6] Bits */
+#define ADC14_IER0_IE6_OFS ( 6) /**< ADC14IE6 Bit Offset */
+#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /**< Interrupt enable */
+/* ADC14_IER0[IE7] Bits */
+#define ADC14_IER0_IE7_OFS ( 7) /**< ADC14IE7 Bit Offset */
+#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /**< Interrupt enable */
+/* ADC14_IER0[IE8] Bits */
+#define ADC14_IER0_IE8_OFS ( 8) /**< ADC14IE8 Bit Offset */
+#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /**< Interrupt enable */
+/* ADC14_IER0[IE9] Bits */
+#define ADC14_IER0_IE9_OFS ( 9) /**< ADC14IE9 Bit Offset */
+#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /**< Interrupt enable */
+/* ADC14_IER0[IE10] Bits */
+#define ADC14_IER0_IE10_OFS (10) /**< ADC14IE10 Bit Offset */
+#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /**< Interrupt enable */
+/* ADC14_IER0[IE11] Bits */
+#define ADC14_IER0_IE11_OFS (11) /**< ADC14IE11 Bit Offset */
+#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /**< Interrupt enable */
+/* ADC14_IER0[IE12] Bits */
+#define ADC14_IER0_IE12_OFS (12) /**< ADC14IE12 Bit Offset */
+#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /**< Interrupt enable */
+/* ADC14_IER0[IE13] Bits */
+#define ADC14_IER0_IE13_OFS (13) /**< ADC14IE13 Bit Offset */
+#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /**< Interrupt enable */
+/* ADC14_IER0[IE14] Bits */
+#define ADC14_IER0_IE14_OFS (14) /**< ADC14IE14 Bit Offset */
+#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /**< Interrupt enable */
+/* ADC14_IER0[IE15] Bits */
+#define ADC14_IER0_IE15_OFS (15) /**< ADC14IE15 Bit Offset */
+#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /**< Interrupt enable */
+/* ADC14_IER0[IE16] Bits */
+#define ADC14_IER0_IE16_OFS (16) /**< ADC14IE16 Bit Offset */
+#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /**< Interrupt enable */
+/* ADC14_IER0[IE17] Bits */
+#define ADC14_IER0_IE17_OFS (17) /**< ADC14IE17 Bit Offset */
+#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /**< Interrupt enable */
+/* ADC14_IER0[IE19] Bits */
+#define ADC14_IER0_IE19_OFS (19) /**< ADC14IE19 Bit Offset */
+#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /**< Interrupt enable */
+/* ADC14_IER0[IE18] Bits */
+#define ADC14_IER0_IE18_OFS (18) /**< ADC14IE18 Bit Offset */
+#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /**< Interrupt enable */
+/* ADC14_IER0[IE20] Bits */
+#define ADC14_IER0_IE20_OFS (20) /**< ADC14IE20 Bit Offset */
+#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /**< Interrupt enable */
+/* ADC14_IER0[IE21] Bits */
+#define ADC14_IER0_IE21_OFS (21) /**< ADC14IE21 Bit Offset */
+#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /**< Interrupt enable */
+/* ADC14_IER0[IE22] Bits */
+#define ADC14_IER0_IE22_OFS (22) /**< ADC14IE22 Bit Offset */
+#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /**< Interrupt enable */
+/* ADC14_IER0[IE23] Bits */
+#define ADC14_IER0_IE23_OFS (23) /**< ADC14IE23 Bit Offset */
+#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /**< Interrupt enable */
+/* ADC14_IER0[IE24] Bits */
+#define ADC14_IER0_IE24_OFS (24) /**< ADC14IE24 Bit Offset */
+#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /**< Interrupt enable */
+/* ADC14_IER0[IE25] Bits */
+#define ADC14_IER0_IE25_OFS (25) /**< ADC14IE25 Bit Offset */
+#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /**< Interrupt enable */
+/* ADC14_IER0[IE26] Bits */
+#define ADC14_IER0_IE26_OFS (26) /**< ADC14IE26 Bit Offset */
+#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /**< Interrupt enable */
+/* ADC14_IER0[IE27] Bits */
+#define ADC14_IER0_IE27_OFS (27) /**< ADC14IE27 Bit Offset */
+#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /**< Interrupt enable */
+/* ADC14_IER0[IE28] Bits */
+#define ADC14_IER0_IE28_OFS (28) /**< ADC14IE28 Bit Offset */
+#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /**< Interrupt enable */
+/* ADC14_IER0[IE29] Bits */
+#define ADC14_IER0_IE29_OFS (29) /**< ADC14IE29 Bit Offset */
+#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /**< Interrupt enable */
+/* ADC14_IER0[IE30] Bits */
+#define ADC14_IER0_IE30_OFS (30) /**< ADC14IE30 Bit Offset */
+#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /**< Interrupt enable */
+/* ADC14_IER0[IE31] Bits */
+#define ADC14_IER0_IE31_OFS (31) /**< ADC14IE31 Bit Offset */
+#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /**< Interrupt enable */
+/* ADC14_IER1[INIE] Bits */
+#define ADC14_IER1_INIE_OFS ( 1) /**< ADC14INIE Bit Offset */
+#define ADC14_IER1_INIE ((uint32_t)0x00000002) /**< Interrupt enable for ADC14MEMx within comparator window */
+/* ADC14_IER1[LOIE] Bits */
+#define ADC14_IER1_LOIE_OFS ( 2) /**< ADC14LOIE Bit Offset */
+#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /**< Interrupt enable for ADC14MEMx below comparator window */
+/* ADC14_IER1[HIIE] Bits */
+#define ADC14_IER1_HIIE_OFS ( 3) /**< ADC14HIIE Bit Offset */
+#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /**< Interrupt enable for ADC14MEMx above comparator window */
+/* ADC14_IER1[OVIE] Bits */
+#define ADC14_IER1_OVIE_OFS ( 4) /**< ADC14OVIE Bit Offset */
+#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /**< ADC14MEMx overflow-interrupt enable */
+/* ADC14_IER1[TOVIE] Bits */
+#define ADC14_IER1_TOVIE_OFS ( 5) /**< ADC14TOVIE Bit Offset */
+#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /**< ADC14 conversion-time-overflow interrupt enable */
+/* ADC14_IER1[RDYIE] Bits */
+#define ADC14_IER1_RDYIE_OFS ( 6) /**< ADC14RDYIE Bit Offset */
+#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /**< ADC14 local buffered reference ready interrupt enable */
+/* ADC14_IFGR0[IFG0] Bits */
+#define ADC14_IFGR0_IFG0_OFS ( 0) /**< ADC14IFG0 Bit Offset */
+#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /**< ADC14MEM0 interrupt flag */
+/* ADC14_IFGR0[IFG1] Bits */
+#define ADC14_IFGR0_IFG1_OFS ( 1) /**< ADC14IFG1 Bit Offset */
+#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /**< ADC14MEM1 interrupt flag */
+/* ADC14_IFGR0[IFG2] Bits */
+#define ADC14_IFGR0_IFG2_OFS ( 2) /**< ADC14IFG2 Bit Offset */
+#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /**< ADC14MEM2 interrupt flag */
+/* ADC14_IFGR0[IFG3] Bits */
+#define ADC14_IFGR0_IFG3_OFS ( 3) /**< ADC14IFG3 Bit Offset */
+#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /**< ADC14MEM3 interrupt flag */
+/* ADC14_IFGR0[IFG4] Bits */
+#define ADC14_IFGR0_IFG4_OFS ( 4) /**< ADC14IFG4 Bit Offset */
+#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /**< ADC14MEM4 interrupt flag */
+/* ADC14_IFGR0[IFG5] Bits */
+#define ADC14_IFGR0_IFG5_OFS ( 5) /**< ADC14IFG5 Bit Offset */
+#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /**< ADC14MEM5 interrupt flag */
+/* ADC14_IFGR0[IFG6] Bits */
+#define ADC14_IFGR0_IFG6_OFS ( 6) /**< ADC14IFG6 Bit Offset */
+#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /**< ADC14MEM6 interrupt flag */
+/* ADC14_IFGR0[IFG7] Bits */
+#define ADC14_IFGR0_IFG7_OFS ( 7) /**< ADC14IFG7 Bit Offset */
+#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /**< ADC14MEM7 interrupt flag */
+/* ADC14_IFGR0[IFG8] Bits */
+#define ADC14_IFGR0_IFG8_OFS ( 8) /**< ADC14IFG8 Bit Offset */
+#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /**< ADC14MEM8 interrupt flag */
+/* ADC14_IFGR0[IFG9] Bits */
+#define ADC14_IFGR0_IFG9_OFS ( 9) /**< ADC14IFG9 Bit Offset */
+#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /**< ADC14MEM9 interrupt flag */
+/* ADC14_IFGR0[IFG10] Bits */
+#define ADC14_IFGR0_IFG10_OFS (10) /**< ADC14IFG10 Bit Offset */
+#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /**< ADC14MEM10 interrupt flag */
+/* ADC14_IFGR0[IFG11] Bits */
+#define ADC14_IFGR0_IFG11_OFS (11) /**< ADC14IFG11 Bit Offset */
+#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /**< ADC14MEM11 interrupt flag */
+/* ADC14_IFGR0[IFG12] Bits */
+#define ADC14_IFGR0_IFG12_OFS (12) /**< ADC14IFG12 Bit Offset */
+#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /**< ADC14MEM12 interrupt flag */
+/* ADC14_IFGR0[IFG13] Bits */
+#define ADC14_IFGR0_IFG13_OFS (13) /**< ADC14IFG13 Bit Offset */
+#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /**< ADC14MEM13 interrupt flag */
+/* ADC14_IFGR0[IFG14] Bits */
+#define ADC14_IFGR0_IFG14_OFS (14) /**< ADC14IFG14 Bit Offset */
+#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /**< ADC14MEM14 interrupt flag */
+/* ADC14_IFGR0[IFG15] Bits */
+#define ADC14_IFGR0_IFG15_OFS (15) /**< ADC14IFG15 Bit Offset */
+#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /**< ADC14MEM15 interrupt flag */
+/* ADC14_IFGR0[IFG16] Bits */
+#define ADC14_IFGR0_IFG16_OFS (16) /**< ADC14IFG16 Bit Offset */
+#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /**< ADC14MEM16 interrupt flag */
+/* ADC14_IFGR0[IFG17] Bits */
+#define ADC14_IFGR0_IFG17_OFS (17) /**< ADC14IFG17 Bit Offset */
+#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /**< ADC14MEM17 interrupt flag */
+/* ADC14_IFGR0[IFG18] Bits */
+#define ADC14_IFGR0_IFG18_OFS (18) /**< ADC14IFG18 Bit Offset */
+#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /**< ADC14MEM18 interrupt flag */
+/* ADC14_IFGR0[IFG19] Bits */
+#define ADC14_IFGR0_IFG19_OFS (19) /**< ADC14IFG19 Bit Offset */
+#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /**< ADC14MEM19 interrupt flag */
+/* ADC14_IFGR0[IFG20] Bits */
+#define ADC14_IFGR0_IFG20_OFS (20) /**< ADC14IFG20 Bit Offset */
+#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /**< ADC14MEM20 interrupt flag */
+/* ADC14_IFGR0[IFG21] Bits */
+#define ADC14_IFGR0_IFG21_OFS (21) /**< ADC14IFG21 Bit Offset */
+#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /**< ADC14MEM21 interrupt flag */
+/* ADC14_IFGR0[IFG22] Bits */
+#define ADC14_IFGR0_IFG22_OFS (22) /**< ADC14IFG22 Bit Offset */
+#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /**< ADC14MEM22 interrupt flag */
+/* ADC14_IFGR0[IFG23] Bits */
+#define ADC14_IFGR0_IFG23_OFS (23) /**< ADC14IFG23 Bit Offset */
+#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /**< ADC14MEM23 interrupt flag */
+/* ADC14_IFGR0[IFG24] Bits */
+#define ADC14_IFGR0_IFG24_OFS (24) /**< ADC14IFG24 Bit Offset */
+#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /**< ADC14MEM24 interrupt flag */
+/* ADC14_IFGR0[IFG25] Bits */
+#define ADC14_IFGR0_IFG25_OFS (25) /**< ADC14IFG25 Bit Offset */
+#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /**< ADC14MEM25 interrupt flag */
+/* ADC14_IFGR0[IFG26] Bits */
+#define ADC14_IFGR0_IFG26_OFS (26) /**< ADC14IFG26 Bit Offset */
+#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /**< ADC14MEM26 interrupt flag */
+/* ADC14_IFGR0[IFG27] Bits */
+#define ADC14_IFGR0_IFG27_OFS (27) /**< ADC14IFG27 Bit Offset */
+#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /**< ADC14MEM27 interrupt flag */
+/* ADC14_IFGR0[IFG28] Bits */
+#define ADC14_IFGR0_IFG28_OFS (28) /**< ADC14IFG28 Bit Offset */
+#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /**< ADC14MEM28 interrupt flag */
+/* ADC14_IFGR0[IFG29] Bits */
+#define ADC14_IFGR0_IFG29_OFS (29) /**< ADC14IFG29 Bit Offset */
+#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /**< ADC14MEM29 interrupt flag */
+/* ADC14_IFGR0[IFG30] Bits */
+#define ADC14_IFGR0_IFG30_OFS (30) /**< ADC14IFG30 Bit Offset */
+#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /**< ADC14MEM30 interrupt flag */
+/* ADC14_IFGR0[IFG31] Bits */
+#define ADC14_IFGR0_IFG31_OFS (31) /**< ADC14IFG31 Bit Offset */
+#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /**< ADC14MEM31 interrupt flag */
+/* ADC14_IFGR1[INIFG] Bits */
+#define ADC14_IFGR1_INIFG_OFS ( 1) /**< ADC14INIFG Bit Offset */
+#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /**< Interrupt flag for ADC14MEMx within comparator window */
+/* ADC14_IFGR1[LOIFG] Bits */
+#define ADC14_IFGR1_LOIFG_OFS ( 2) /**< ADC14LOIFG Bit Offset */
+#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /**< Interrupt flag for ADC14MEMx below comparator window */
+/* ADC14_IFGR1[HIIFG] Bits */
+#define ADC14_IFGR1_HIIFG_OFS ( 3) /**< ADC14HIIFG Bit Offset */
+#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /**< Interrupt flag for ADC14MEMx above comparator window */
+/* ADC14_IFGR1[OVIFG] Bits */
+#define ADC14_IFGR1_OVIFG_OFS ( 4) /**< ADC14OVIFG Bit Offset */
+#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /**< ADC14MEMx overflow interrupt flag */
+/* ADC14_IFGR1[TOVIFG] Bits */
+#define ADC14_IFGR1_TOVIFG_OFS ( 5) /**< ADC14TOVIFG Bit Offset */
+#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /**< ADC14 conversion time overflow interrupt flag */
+/* ADC14_IFGR1[RDYIFG] Bits */
+#define ADC14_IFGR1_RDYIFG_OFS ( 6) /**< ADC14RDYIFG Bit Offset */
+#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /**< ADC14 local buffered reference ready interrupt flag */
+/* ADC14_CLRIFGR0[CLRIFG0] Bits */
+#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /**< CLRADC14IFG0 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /**< clear ADC14IFG0 */
+/* ADC14_CLRIFGR0[CLRIFG1] Bits */
+#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /**< CLRADC14IFG1 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /**< clear ADC14IFG1 */
+/* ADC14_CLRIFGR0[CLRIFG2] Bits */
+#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /**< CLRADC14IFG2 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /**< clear ADC14IFG2 */
+/* ADC14_CLRIFGR0[CLRIFG3] Bits */
+#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /**< CLRADC14IFG3 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /**< clear ADC14IFG3 */
+/* ADC14_CLRIFGR0[CLRIFG4] Bits */
+#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /**< CLRADC14IFG4 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /**< clear ADC14IFG4 */
+/* ADC14_CLRIFGR0[CLRIFG5] Bits */
+#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /**< CLRADC14IFG5 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /**< clear ADC14IFG5 */
+/* ADC14_CLRIFGR0[CLRIFG6] Bits */
+#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /**< CLRADC14IFG6 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /**< clear ADC14IFG6 */
+/* ADC14_CLRIFGR0[CLRIFG7] Bits */
+#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /**< CLRADC14IFG7 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /**< clear ADC14IFG7 */
+/* ADC14_CLRIFGR0[CLRIFG8] Bits */
+#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /**< CLRADC14IFG8 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /**< clear ADC14IFG8 */
+/* ADC14_CLRIFGR0[CLRIFG9] Bits */
+#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /**< CLRADC14IFG9 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /**< clear ADC14IFG9 */
+/* ADC14_CLRIFGR0[CLRIFG10] Bits */
+#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /**< CLRADC14IFG10 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /**< clear ADC14IFG10 */
+/* ADC14_CLRIFGR0[CLRIFG11] Bits */
+#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /**< CLRADC14IFG11 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /**< clear ADC14IFG11 */
+/* ADC14_CLRIFGR0[CLRIFG12] Bits */
+#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /**< CLRADC14IFG12 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /**< clear ADC14IFG12 */
+/* ADC14_CLRIFGR0[CLRIFG13] Bits */
+#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /**< CLRADC14IFG13 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /**< clear ADC14IFG13 */
+/* ADC14_CLRIFGR0[CLRIFG14] Bits */
+#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /**< CLRADC14IFG14 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /**< clear ADC14IFG14 */
+/* ADC14_CLRIFGR0[CLRIFG15] Bits */
+#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /**< CLRADC14IFG15 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /**< clear ADC14IFG15 */
+/* ADC14_CLRIFGR0[CLRIFG16] Bits */
+#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /**< CLRADC14IFG16 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /**< clear ADC14IFG16 */
+/* ADC14_CLRIFGR0[CLRIFG17] Bits */
+#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /**< CLRADC14IFG17 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /**< clear ADC14IFG17 */
+/* ADC14_CLRIFGR0[CLRIFG18] Bits */
+#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /**< CLRADC14IFG18 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /**< clear ADC14IFG18 */
+/* ADC14_CLRIFGR0[CLRIFG19] Bits */
+#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /**< CLRADC14IFG19 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /**< clear ADC14IFG19 */
+/* ADC14_CLRIFGR0[CLRIFG20] Bits */
+#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /**< CLRADC14IFG20 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /**< clear ADC14IFG20 */
+/* ADC14_CLRIFGR0[CLRIFG21] Bits */
+#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /**< CLRADC14IFG21 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /**< clear ADC14IFG21 */
+/* ADC14_CLRIFGR0[CLRIFG22] Bits */
+#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /**< CLRADC14IFG22 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /**< clear ADC14IFG22 */
+/* ADC14_CLRIFGR0[CLRIFG23] Bits */
+#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /**< CLRADC14IFG23 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /**< clear ADC14IFG23 */
+/* ADC14_CLRIFGR0[CLRIFG24] Bits */
+#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /**< CLRADC14IFG24 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /**< clear ADC14IFG24 */
+/* ADC14_CLRIFGR0[CLRIFG25] Bits */
+#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /**< CLRADC14IFG25 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /**< clear ADC14IFG25 */
+/* ADC14_CLRIFGR0[CLRIFG26] Bits */
+#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /**< CLRADC14IFG26 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /**< clear ADC14IFG26 */
+/* ADC14_CLRIFGR0[CLRIFG27] Bits */
+#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /**< CLRADC14IFG27 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /**< clear ADC14IFG27 */
+/* ADC14_CLRIFGR0[CLRIFG28] Bits */
+#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /**< CLRADC14IFG28 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /**< clear ADC14IFG28 */
+/* ADC14_CLRIFGR0[CLRIFG29] Bits */
+#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /**< CLRADC14IFG29 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /**< clear ADC14IFG29 */
+/* ADC14_CLRIFGR0[CLRIFG30] Bits */
+#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /**< CLRADC14IFG30 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /**< clear ADC14IFG30 */
+/* ADC14_CLRIFGR0[CLRIFG31] Bits */
+#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /**< CLRADC14IFG31 Bit Offset */
+#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /**< clear ADC14IFG31 */
+/* ADC14_CLRIFGR1[CLRINIFG] Bits */
+#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /**< CLRADC14INIFG Bit Offset */
+#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /**< clear ADC14INIFG */
+/* ADC14_CLRIFGR1[CLRLOIFG] Bits */
+#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /**< CLRADC14LOIFG Bit Offset */
+#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /**< clear ADC14LOIFG */
+/* ADC14_CLRIFGR1[CLRHIIFG] Bits */
+#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /**< CLRADC14HIIFG Bit Offset */
+#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /**< clear ADC14HIIFG */
+/* ADC14_CLRIFGR1[CLROVIFG] Bits */
+#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /**< CLRADC14OVIFG Bit Offset */
+#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /**< clear ADC14OVIFG */
+/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */
+#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /**< CLRADC14TOVIFG Bit Offset */
+#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /**< clear ADC14TOVIFG */
+/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */
+#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /**< CLRADC14RDYIFG Bit Offset */
+#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /**< clear ADC14RDYIFG */
-//*****************************************************************************
-// CAPTIO1 Bits
-//*****************************************************************************
-/* CAPTIO1CTL[CAPTIOPISEL] Bits */
-//#define CAPTIOPISEL0 (0x0002) /* CAPTIOPISEL Bit 0 */
-//#define CAPTIOPISEL1 (0x0004) /* CAPTIOPISEL Bit 1 */
-//#define CAPTIOPISEL2 (0x0008) /* CAPTIOPISEL Bit 2 */
-/* CAPTIO1CTL[CAPTIOPISEL] Bits */
-//#define CAPTIOPISEL_OFS ( 1) /* CAPTIOPISELx Offset */
-//#define CAPTIOPISEL_M (0x000e) /* Capacitive Touch IO pin select */
-//#define CAPTIOPISEL0 (0x0002) /* Capacitive Touch IO pin select */
-//#define CAPTIOPISEL1 (0x0004) /* Capacitive Touch IO pin select */
-//#define CAPTIOPISEL2 (0x0008) /* Capacitive Touch IO pin select */
-//#define CAPTIOPISEL_0 (0x0000) /* Px.0 */
-//#define CAPTIOPISEL_1 (0x0002) /* Px.1 */
-//#define CAPTIOPISEL_2 (0x0004) /* Px.2 */
-//#define CAPTIOPISEL_3 (0x0006) /* Px.3 */
-//#define CAPTIOPISEL_4 (0x0008) /* Px.4 */
-//#define CAPTIOPISEL_5 (0x000a) /* Px.5 */
-//#define CAPTIOPISEL_6 (0x000c) /* Px.6 */
-//#define CAPTIOPISEL_7 (0x000e) /* Px.7 */
-/* CAPTIO1CTL[CAPTIOPOSEL] Bits */
-//#define CAPTIOPOSEL0 (0x0010) /* CAPTIOPOSEL Bit 0 */
-//#define CAPTIOPOSEL1 (0x0020) /* CAPTIOPOSEL Bit 1 */
-//#define CAPTIOPOSEL2 (0x0040) /* CAPTIOPOSEL Bit 2 */
-//#define CAPTIOPOSEL3 (0x0080) /* CAPTIOPOSEL Bit 3 */
-/* CAPTIO1CTL[CAPTIOPOSEL] Bits */
-//#define CAPTIOPOSEL_OFS ( 4) /* CAPTIOPOSELx Offset */
-//#define CAPTIOPOSEL_M (0x00f0) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL0 (0x0010) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL1 (0x0020) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL2 (0x0040) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL3 (0x0080) /* Capacitive Touch IO port select */
-//#define CAPTIOPOSEL_0 (0x0000) /* Px = PJ */
-//#define CAPTIOPOSEL_1 (0x0010) /* Px = P1 */
-//#define CAPTIOPOSEL_2 (0x0020) /* Px = P2 */
-//#define CAPTIOPOSEL_3 (0x0030) /* Px = P3 */
-//#define CAPTIOPOSEL_4 (0x0040) /* Px = P4 */
-//#define CAPTIOPOSEL_5 (0x0050) /* Px = P5 */
-//#define CAPTIOPOSEL_6 (0x0060) /* Px = P6 */
-//#define CAPTIOPOSEL_7 (0x0070) /* Px = P7 */
-//#define CAPTIOPOSEL_8 (0x0080) /* Px = P8 */
-//#define CAPTIOPOSEL_9 (0x0090) /* Px = P9 */
-//#define CAPTIOPOSEL_10 (0x00a0) /* Px = P10 */
-//#define CAPTIOPOSEL_11 (0x00b0) /* Px = P11 */
-//#define CAPTIOPOSEL_12 (0x00c0) /* Px = P12 */
-//#define CAPTIOPOSEL_13 (0x00d0) /* Px = P13 */
-//#define CAPTIOPOSEL_14 (0x00e0) /* Px = P14 */
-//#define CAPTIOPOSEL_15 (0x00f0) /* Px = P15 */
-//#define CAPTIOPOSEL__PJ (0x0000) /* Px = PJ */
-//#define CAPTIOPOSEL__P1 (0x0010) /* Px = P1 */
-//#define CAPTIOPOSEL__P2 (0x0020) /* Px = P2 */
-//#define CAPTIOPOSEL__P3 (0x0030) /* Px = P3 */
-//#define CAPTIOPOSEL__P4 (0x0040) /* Px = P4 */
-//#define CAPTIOPOSEL__P5 (0x0050) /* Px = P5 */
-//#define CAPTIOPOSEL__P6 (0x0060) /* Px = P6 */
-//#define CAPTIOPOSEL__P7 (0x0070) /* Px = P7 */
-//#define CAPTIOPOSEL__P8 (0x0080) /* Px = P8 */
-//#define CAPTIOPOSEL__P9 (0x0090) /* Px = P9 */
-//#define CAPTIOPOSEL__P10 (0x00a0) /* Px = P10 */
-//#define CAPTIOPOSEL__P11 (0x00b0) /* Px = P11 */
-//#define CAPTIOPOSEL__P12 (0x00c0) /* Px = P12 */
-//#define CAPTIOPOSEL__P13 (0x00d0) /* Px = P13 */
-//#define CAPTIOPOSEL__P14 (0x00e0) /* Px = P14 */
-//#define CAPTIOPOSEL__P15 (0x00f0) /* Px = P15 */
-/* CAPTIO1CTL[CAPTIOEN] Bits */
-//#define CAPTIOEN_OFS ( 8) /* CAPTIOEN Offset */
-//#define CAPTIOEN (0x0100) /* Capacitive Touch IO enable */
-/* CAPTIO1CTL[CAPTIOSTATE] Bits */
-//#define CAPTIOSTATE_OFS ( 9) /* CAPTIOSTATE Offset */
-//#define CAPTIOSTATE (0x0200) /* Capacitive Touch IO state */
+/******************************************************************************
+* AES256 Bits
+******************************************************************************/
+/* AES256_CTL0[OP] Bits */
+#define AES256_CTL0_OP_OFS ( 0) /**< AESOPx Bit Offset */
+#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /**< AESOPx Bit Mask */
+#define AES256_CTL0_OP0 ((uint16_t)0x0001) /**< OP Bit 0 */
+#define AES256_CTL0_OP1 ((uint16_t)0x0002) /**< OP Bit 1 */
+#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /**< Encryption */
+#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /**< Decryption. The provided key is the same key used for encryption */
+#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /**< Generate first round key required for decryption */
+#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /**< Decryption. The provided key is the first round key required for decryption */
+/* AES256_CTL0[KL] Bits */
+#define AES256_CTL0_KL_OFS ( 2) /**< AESKLx Bit Offset */
+#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /**< AESKLx Bit Mask */
+#define AES256_CTL0_KL0 ((uint16_t)0x0004) /**< KL Bit 0 */
+#define AES256_CTL0_KL1 ((uint16_t)0x0008) /**< KL Bit 1 */
+#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /**< AES128. The key size is 128 bit */
+#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /**< AES192. The key size is 192 bit. */
+#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /**< AES256. The key size is 256 bit */
+#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /**< AES128. The key size is 128 bit */
+#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /**< AES192. The key size is 192 bit. */
+#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /**< AES256. The key size is 256 bit */
+/* AES256_CTL0[CM] Bits */
+#define AES256_CTL0_CM_OFS ( 5) /**< AESCMx Bit Offset */
+#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /**< AESCMx Bit Mask */
+#define AES256_CTL0_CM0 ((uint16_t)0x0020) /**< CM Bit 0 */
+#define AES256_CTL0_CM1 ((uint16_t)0x0040) /**< CM Bit 1 */
+#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /**< ECB */
+#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /**< CBC */
+#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /**< OFB */
+#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /**< CFB */
+#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /**< ECB */
+#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /**< CBC */
+#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /**< OFB */
+#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /**< CFB */
+/* AES256_CTL0[SWRST] Bits */
+#define AES256_CTL0_SWRST_OFS ( 7) /**< AESSWRST Bit Offset */
+#define AES256_CTL0_SWRST ((uint16_t)0x0080) /**< AES software reset */
+/* AES256_CTL0[RDYIFG] Bits */
+#define AES256_CTL0_RDYIFG_OFS ( 8) /**< AESRDYIFG Bit Offset */
+#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /**< AES ready interrupt flag */
+/* AES256_CTL0[ERRFG] Bits */
+#define AES256_CTL0_ERRFG_OFS (11) /**< AESERRFG Bit Offset */
+#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /**< AES error flag */
+/* AES256_CTL0[RDYIE] Bits */
+#define AES256_CTL0_RDYIE_OFS (12) /**< AESRDYIE Bit Offset */
+#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /**< AES ready interrupt enable */
+/* AES256_CTL0[CMEN] Bits */
+#define AES256_CTL0_CMEN_OFS (15) /**< AESCMEN Bit Offset */
+#define AES256_CTL0_CMEN ((uint16_t)0x8000) /**< AES cipher mode enable */
+/* AES256_CTL1[BLKCNT] Bits */
+#define AES256_CTL1_BLKCNT_OFS ( 0) /**< AESBLKCNTx Bit Offset */
+#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /**< AESBLKCNTx Bit Mask */
+#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /**< BLKCNT Bit 0 */
+#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /**< BLKCNT Bit 1 */
+#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /**< BLKCNT Bit 2 */
+#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /**< BLKCNT Bit 3 */
+#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /**< BLKCNT Bit 4 */
+#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /**< BLKCNT Bit 5 */
+#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /**< BLKCNT Bit 6 */
+#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /**< BLKCNT Bit 7 */
+/* AES256_STAT[BUSY] Bits */
+#define AES256_STAT_BUSY_OFS ( 0) /**< AESBUSY Bit Offset */
+#define AES256_STAT_BUSY ((uint16_t)0x0001) /**< AES accelerator module busy */
+/* AES256_STAT[KEYWR] Bits */
+#define AES256_STAT_KEYWR_OFS ( 1) /**< AESKEYWR Bit Offset */
+#define AES256_STAT_KEYWR ((uint16_t)0x0002) /**< All 16 bytes written to AESAKEY */
+/* AES256_STAT[DINWR] Bits */
+#define AES256_STAT_DINWR_OFS ( 2) /**< AESDINWR Bit Offset */
+#define AES256_STAT_DINWR ((uint16_t)0x0004) /**< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
+/* AES256_STAT[DOUTRD] Bits */
+#define AES256_STAT_DOUTRD_OFS ( 3) /**< AESDOUTRD Bit Offset */
+#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /**< All 16 bytes read from AESADOUT */
+/* AES256_STAT[KEYCNT] Bits */
+#define AES256_STAT_KEYCNT_OFS ( 4) /**< AESKEYCNTx Bit Offset */
+#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /**< AESKEYCNTx Bit Mask */
+#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /**< KEYCNT Bit 0 */
+#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /**< KEYCNT Bit 1 */
+#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /**< KEYCNT Bit 2 */
+#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /**< KEYCNT Bit 3 */
+/* AES256_STAT[DINCNT] Bits */
+#define AES256_STAT_DINCNT_OFS ( 8) /**< AESDINCNTx Bit Offset */
+#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /**< AESDINCNTx Bit Mask */
+#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /**< DINCNT Bit 0 */
+#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /**< DINCNT Bit 1 */
+#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /**< DINCNT Bit 2 */
+#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /**< DINCNT Bit 3 */
+/* AES256_STAT[DOUTCNT] Bits */
+#define AES256_STAT_DOUTCNT_OFS (12) /**< AESDOUTCNTx Bit Offset */
+#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /**< AESDOUTCNTx Bit Mask */
+#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /**< DOUTCNT Bit 0 */
+#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /**< DOUTCNT Bit 1 */
+#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /**< DOUTCNT Bit 2 */
+#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /**< DOUTCNT Bit 3 */
+/* AES256_KEY[KEY0] Bits */
+#define AES256_KEY_KEY0_OFS ( 0) /**< AESKEY0x Bit Offset */
+#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /**< AESKEY0x Bit Mask */
+#define AES256_KEY_KEY00 ((uint16_t)0x0001) /**< KEY0 Bit 0 */
+#define AES256_KEY_KEY01 ((uint16_t)0x0002) /**< KEY0 Bit 1 */
+#define AES256_KEY_KEY02 ((uint16_t)0x0004) /**< KEY0 Bit 2 */
+#define AES256_KEY_KEY03 ((uint16_t)0x0008) /**< KEY0 Bit 3 */
+#define AES256_KEY_KEY04 ((uint16_t)0x0010) /**< KEY0 Bit 4 */
+#define AES256_KEY_KEY05 ((uint16_t)0x0020) /**< KEY0 Bit 5 */
+#define AES256_KEY_KEY06 ((uint16_t)0x0040) /**< KEY0 Bit 6 */
+#define AES256_KEY_KEY07 ((uint16_t)0x0080) /**< KEY0 Bit 7 */
+/* AES256_KEY[KEY1] Bits */
+#define AES256_KEY_KEY1_OFS ( 8) /**< AESKEY1x Bit Offset */
+#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /**< AESKEY1x Bit Mask */
+#define AES256_KEY_KEY10 ((uint16_t)0x0100) /**< KEY1 Bit 0 */
+#define AES256_KEY_KEY11 ((uint16_t)0x0200) /**< KEY1 Bit 1 */
+#define AES256_KEY_KEY12 ((uint16_t)0x0400) /**< KEY1 Bit 2 */
+#define AES256_KEY_KEY13 ((uint16_t)0x0800) /**< KEY1 Bit 3 */
+#define AES256_KEY_KEY14 ((uint16_t)0x1000) /**< KEY1 Bit 4 */
+#define AES256_KEY_KEY15 ((uint16_t)0x2000) /**< KEY1 Bit 5 */
+#define AES256_KEY_KEY16 ((uint16_t)0x4000) /**< KEY1 Bit 6 */
+#define AES256_KEY_KEY17 ((uint16_t)0x8000) /**< KEY1 Bit 7 */
+/* AES256_DIN[DIN0] Bits */
+#define AES256_DIN_DIN0_OFS ( 0) /**< AESDIN0x Bit Offset */
+#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /**< AESDIN0x Bit Mask */
+#define AES256_DIN_DIN00 ((uint16_t)0x0001) /**< DIN0 Bit 0 */
+#define AES256_DIN_DIN01 ((uint16_t)0x0002) /**< DIN0 Bit 1 */
+#define AES256_DIN_DIN02 ((uint16_t)0x0004) /**< DIN0 Bit 2 */
+#define AES256_DIN_DIN03 ((uint16_t)0x0008) /**< DIN0 Bit 3 */
+#define AES256_DIN_DIN04 ((uint16_t)0x0010) /**< DIN0 Bit 4 */
+#define AES256_DIN_DIN05 ((uint16_t)0x0020) /**< DIN0 Bit 5 */
+#define AES256_DIN_DIN06 ((uint16_t)0x0040) /**< DIN0 Bit 6 */
+#define AES256_DIN_DIN07 ((uint16_t)0x0080) /**< DIN0 Bit 7 */
+/* AES256_DIN[DIN1] Bits */
+#define AES256_DIN_DIN1_OFS ( 8) /**< AESDIN1x Bit Offset */
+#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /**< AESDIN1x Bit Mask */
+#define AES256_DIN_DIN10 ((uint16_t)0x0100) /**< DIN1 Bit 0 */
+#define AES256_DIN_DIN11 ((uint16_t)0x0200) /**< DIN1 Bit 1 */
+#define AES256_DIN_DIN12 ((uint16_t)0x0400) /**< DIN1 Bit 2 */
+#define AES256_DIN_DIN13 ((uint16_t)0x0800) /**< DIN1 Bit 3 */
+#define AES256_DIN_DIN14 ((uint16_t)0x1000) /**< DIN1 Bit 4 */
+#define AES256_DIN_DIN15 ((uint16_t)0x2000) /**< DIN1 Bit 5 */
+#define AES256_DIN_DIN16 ((uint16_t)0x4000) /**< DIN1 Bit 6 */
+#define AES256_DIN_DIN17 ((uint16_t)0x8000) /**< DIN1 Bit 7 */
+/* AES256_DOUT[DOUT0] Bits */
+#define AES256_DOUT_DOUT0_OFS ( 0) /**< AESDOUT0x Bit Offset */
+#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /**< AESDOUT0x Bit Mask */
+#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /**< DOUT0 Bit 0 */
+#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /**< DOUT0 Bit 1 */
+#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /**< DOUT0 Bit 2 */
+#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /**< DOUT0 Bit 3 */
+#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /**< DOUT0 Bit 4 */
+#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /**< DOUT0 Bit 5 */
+#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /**< DOUT0 Bit 6 */
+#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /**< DOUT0 Bit 7 */
+/* AES256_DOUT[DOUT1] Bits */
+#define AES256_DOUT_DOUT1_OFS ( 8) /**< AESDOUT1x Bit Offset */
+#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /**< AESDOUT1x Bit Mask */
+#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /**< DOUT1 Bit 0 */
+#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /**< DOUT1 Bit 1 */
+#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /**< DOUT1 Bit 2 */
+#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /**< DOUT1 Bit 3 */
+#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /**< DOUT1 Bit 4 */
+#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /**< DOUT1 Bit 5 */
+#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /**< DOUT1 Bit 6 */
+#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /**< DOUT1 Bit 7 */
+/* AES256_XDIN[XDIN0] Bits */
+#define AES256_XDIN_XDIN0_OFS ( 0) /**< AESXDIN0x Bit Offset */
+#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /**< AESXDIN0x Bit Mask */
+#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /**< XDIN0 Bit 0 */
+#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /**< XDIN0 Bit 1 */
+#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /**< XDIN0 Bit 2 */
+#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /**< XDIN0 Bit 3 */
+#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /**< XDIN0 Bit 4 */
+#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /**< XDIN0 Bit 5 */
+#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /**< XDIN0 Bit 6 */
+#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /**< XDIN0 Bit 7 */
+/* AES256_XDIN[XDIN1] Bits */
+#define AES256_XDIN_XDIN1_OFS ( 8) /**< AESXDIN1x Bit Offset */
+#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /**< AESXDIN1x Bit Mask */
+#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /**< XDIN1 Bit 0 */
+#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /**< XDIN1 Bit 1 */
+#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /**< XDIN1 Bit 2 */
+#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /**< XDIN1 Bit 3 */
+#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /**< XDIN1 Bit 4 */
+#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /**< XDIN1 Bit 5 */
+#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /**< XDIN1 Bit 6 */
+#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /**< XDIN1 Bit 7 */
+/* AES256_XIN[XIN0] Bits */
+#define AES256_XIN_XIN0_OFS ( 0) /**< AESXIN0x Bit Offset */
+#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /**< AESXIN0x Bit Mask */
+#define AES256_XIN_XIN00 ((uint16_t)0x0001) /**< XIN0 Bit 0 */
+#define AES256_XIN_XIN01 ((uint16_t)0x0002) /**< XIN0 Bit 1 */
+#define AES256_XIN_XIN02 ((uint16_t)0x0004) /**< XIN0 Bit 2 */
+#define AES256_XIN_XIN03 ((uint16_t)0x0008) /**< XIN0 Bit 3 */
+#define AES256_XIN_XIN04 ((uint16_t)0x0010) /**< XIN0 Bit 4 */
+#define AES256_XIN_XIN05 ((uint16_t)0x0020) /**< XIN0 Bit 5 */
+#define AES256_XIN_XIN06 ((uint16_t)0x0040) /**< XIN0 Bit 6 */
+#define AES256_XIN_XIN07 ((uint16_t)0x0080) /**< XIN0 Bit 7 */
+/* AES256_XIN[XIN1] Bits */
+#define AES256_XIN_XIN1_OFS ( 8) /**< AESXIN1x Bit Offset */
+#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /**< AESXIN1x Bit Mask */
+#define AES256_XIN_XIN10 ((uint16_t)0x0100) /**< XIN1 Bit 0 */
+#define AES256_XIN_XIN11 ((uint16_t)0x0200) /**< XIN1 Bit 1 */
+#define AES256_XIN_XIN12 ((uint16_t)0x0400) /**< XIN1 Bit 2 */
+#define AES256_XIN_XIN13 ((uint16_t)0x0800) /**< XIN1 Bit 3 */
+#define AES256_XIN_XIN14 ((uint16_t)0x1000) /**< XIN1 Bit 4 */
+#define AES256_XIN_XIN15 ((uint16_t)0x2000) /**< XIN1 Bit 5 */
+#define AES256_XIN_XIN16 ((uint16_t)0x4000) /**< XIN1 Bit 6 */
+#define AES256_XIN_XIN17 ((uint16_t)0x8000) /**< XIN1 Bit 7 */
-//*****************************************************************************
-// COMP_E0 Bits
-//*****************************************************************************
-/* CE0CTL0[CEIPSEL] Bits */
-#define CEIPSEL_OFS ( 0) /* CEIPSEL Offset */
-#define CEIPSEL_M (0x000f) /* Channel input selected for the V+ terminal */
-#define CEIPSEL0 (0x0001) /* Channel input selected for the V+ terminal */
-#define CEIPSEL1 (0x0002) /* Channel input selected for the V+ terminal */
-#define CEIPSEL2 (0x0004) /* Channel input selected for the V+ terminal */
-#define CEIPSEL3 (0x0008) /* Channel input selected for the V+ terminal */
-#define CEIPSEL_0 (0x0000) /* Channel 0 selected */
-#define CEIPSEL_1 (0x0001) /* Channel 1 selected */
-#define CEIPSEL_2 (0x0002) /* Channel 2 selected */
-#define CEIPSEL_3 (0x0003) /* Channel 3 selected */
-#define CEIPSEL_4 (0x0004) /* Channel 4 selected */
-#define CEIPSEL_5 (0x0005) /* Channel 5 selected */
-#define CEIPSEL_6 (0x0006) /* Channel 6 selected */
-#define CEIPSEL_7 (0x0007) /* Channel 7 selected */
-#define CEIPSEL_8 (0x0008) /* Channel 8 selected */
-#define CEIPSEL_9 (0x0009) /* Channel 9 selected */
-#define CEIPSEL_10 (0x000a) /* Channel 10 selected */
-#define CEIPSEL_11 (0x000b) /* Channel 11 selected */
-#define CEIPSEL_12 (0x000c) /* Channel 12 selected */
-#define CEIPSEL_13 (0x000d) /* Channel 13 selected */
-#define CEIPSEL_14 (0x000e) /* Channel 14 selected */
-#define CEIPSEL_15 (0x000f) /* Channel 15 selected */
-/* CE0CTL0[CEIPEN] Bits */
-#define CEIPEN_OFS ( 7) /* CEIPEN Offset */
-#define CEIPEN (0x0080) /* Channel input enable for the V+ terminal */
-/* CE0CTL0[CEIMSEL] Bits */
-#define CEIMSEL_OFS ( 8) /* CEIMSEL Offset */
-#define CEIMSEL_M (0x0f00) /* Channel input selected for the - terminal */
-#define CEIMSEL0 (0x0100) /* Channel input selected for the - terminal */
-#define CEIMSEL1 (0x0200) /* Channel input selected for the - terminal */
-#define CEIMSEL2 (0x0400) /* Channel input selected for the - terminal */
-#define CEIMSEL3 (0x0800) /* Channel input selected for the - terminal */
-#define CEIMSEL_0 (0x0000) /* Channel 0 selected */
-#define CEIMSEL_1 (0x0100) /* Channel 1 selected */
-#define CEIMSEL_2 (0x0200) /* Channel 2 selected */
-#define CEIMSEL_3 (0x0300) /* Channel 3 selected */
-#define CEIMSEL_4 (0x0400) /* Channel 4 selected */
-#define CEIMSEL_5 (0x0500) /* Channel 5 selected */
-#define CEIMSEL_6 (0x0600) /* Channel 6 selected */
-#define CEIMSEL_7 (0x0700) /* Channel 7 selected */
-#define CEIMSEL_8 (0x0800) /* Channel 8 selected */
-#define CEIMSEL_9 (0x0900) /* Channel 9 selected */
-#define CEIMSEL_10 (0x0a00) /* Channel 10 selected */
-#define CEIMSEL_11 (0x0b00) /* Channel 11 selected */
-#define CEIMSEL_12 (0x0c00) /* Channel 12 selected */
-#define CEIMSEL_13 (0x0d00) /* Channel 13 selected */
-#define CEIMSEL_14 (0x0e00) /* Channel 14 selected */
-#define CEIMSEL_15 (0x0f00) /* Channel 15 selected */
-/* CE0CTL0[CEIMEN] Bits */
-#define CEIMEN_OFS (15) /* CEIMEN Offset */
-#define CEIMEN (0x8000) /* Channel input enable for the - terminal */
-/* CE0CTL1[CEOUT] Bits */
-#define CEOUT_OFS ( 0) /* CEOUT Offset */
-#define CEOUT (0x0001) /* Comparator output value */
-/* CE0CTL1[CEOUTPOL] Bits */
-#define CEOUTPOL_OFS ( 1) /* CEOUTPOL Offset */
-#define CEOUTPOL (0x0002) /* Comparator output polarity */
-/* CE0CTL1[CEF] Bits */
-#define CEF_OFS ( 2) /* CEF Offset */
-#define CEF (0x0004) /* Comparator output filter */
-/* CE0CTL1[CEIES] Bits */
-#define CEIES_OFS ( 3) /* CEIES Offset */
-#define CEIES (0x0008) /* Interrupt edge select for CEIIFG and CEIFG */
-/* CE0CTL1[CESHORT] Bits */
-#define CESHORT_OFS ( 4) /* CESHORT Offset */
-#define CESHORT (0x0010) /* Input short */
-/* CE0CTL1[CEEX] Bits */
-#define CEEX_OFS ( 5) /* CEEX Offset */
-#define CEEX (0x0020) /* Exchange */
-/* CE0CTL1[CEFDLY] Bits */
-#define CEFDLY_OFS ( 6) /* CEFDLY Offset */
-#define CEFDLY_M (0x00c0) /* Filter delay */
-#define CEFDLY0 (0x0040) /* Filter delay */
-#define CEFDLY1 (0x0080) /* Filter delay */
-#define CEFDLY_0 (0x0000) /* Typical filter delay of TBD (450) ns */
-#define CEFDLY_1 (0x0040) /* Typical filter delay of TBD (900) ns */
-#define CEFDLY_2 (0x0080) /* Typical filter delay of TBD (1800) ns */
-#define CEFDLY_3 (0x00c0) /* Typical filter delay of TBD (3600) ns */
-/* CE0CTL1[CEPWRMD] Bits */
-#define CEPWRMD_OFS ( 8) /* CEPWRMD Offset */
-#define CEPWRMD_M (0x0300) /* Power Mode */
-#define CEPWRMD0 (0x0100) /* Power Mode */
-#define CEPWRMD1 (0x0200) /* Power Mode */
-#define CEPWRMD_0 (0x0000) /* High-speed mode */
-#define CEPWRMD_1 (0x0100) /* Normal mode */
-#define CEPWRMD_2 (0x0200) /* Ultra-low power mode */
-/* CE0CTL1[CEON] Bits */
-#define CEON_OFS (10) /* CEON Offset */
-#define CEON (0x0400) /* Comparator On */
-/* CE0CTL1[CEMRVL] Bits */
-#define CEMRVL_OFS (11) /* CEMRVL Offset */
-#define CEMRVL (0x0800) /* This bit is valid of CEMRVS is set to 1 */
-/* CE0CTL1[CEMRVS] Bits */
-#define CEMRVS_OFS (12) /* CEMRVS Offset */
-#define CEMRVS (0x1000) /* */
-/* CE0CTL2[CEREF0] Bits */
-#define CEREF0_OFS ( 0) /* CEREF0 Offset */
-#define CEREF0_M (0x001f) /* Reference resistor tap 0 */
-/* CE0CTL2[CERSEL] Bits */
-#define CERSEL_OFS ( 5) /* CERSEL Offset */
-#define CERSEL (0x0020) /* Reference select */
-/* CE0CTL2[CERS] Bits */
-#define CERS_OFS ( 6) /* CERS Offset */
-#define CERS_M (0x00c0) /* Reference source */
-#define CERS0 (0x0040) /* Reference source */
-#define CERS1 (0x0080) /* Reference source */
-#define CERS_0 (0x0000) /* No current is drawn by the reference circuitry */
-#define CERS_1 (0x0040) /* VCC applied to the resistor ladder */
-#define CERS_2 (0x0080) /* Shared reference voltage applied to the resistor ladder */
-#define CERS_3 (0x00c0) /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */
-/* CE0CTL2[CEREF1] Bits */
-#define CEREF1_OFS ( 8) /* CEREF1 Offset */
-#define CEREF1_M (0x1f00) /* Reference resistor tap 1 */
-/* CE0CTL2[CEREFL] Bits */
-#define CEREFL_OFS (13) /* CEREFL Offset */
-#define CEREFL_M (0x6000) /* Reference voltage level */
-#define CEREFL0 (0x2000) /* Reference voltage level */
-#define CEREFL1 (0x4000) /* Reference voltage level */
-#define CEREFL_0 (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
-#define CEREFL_1 (0x2000) /* 1.2 V is selected as shared reference voltage input */
-#define CEREFL_2 (0x4000) /* 2.0 V is selected as shared reference voltage input */
-#define CEREFL_3 (0x6000) /* 2.5 V is selected as shared reference voltage input */
-#define CEREFL__OFF (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
-#define CEREFL__1P2V (0x2000) /* 1.2 V is selected as shared reference voltage input */
-#define CEREFL__2P0V (0x4000) /* 2.0 V is selected as shared reference voltage input */
-#define CEREFL__2P5V (0x6000) /* 2.5 V is selected as shared reference voltage input */
-/* CE0CTL2[CEREFACC] Bits */
-#define CEREFACC_OFS (15) /* CEREFACC Offset */
-#define CEREFACC (0x8000) /* Reference accuracy */
-/* CE0CTL3[CEPD0] Bits */
-#define CEPD0_OFS ( 0) /* CEPD0 Offset */
-#define CEPD0 (0x0001) /* Port disable */
-/* CE0CTL3[CEPD1] Bits */
-#define CEPD1_OFS ( 1) /* CEPD1 Offset */
-#define CEPD1 (0x0002) /* Port disable */
-/* CE0CTL3[CEPD2] Bits */
-#define CEPD2_OFS ( 2) /* CEPD2 Offset */
-#define CEPD2 (0x0004) /* Port disable */
-/* CE0CTL3[CEPD3] Bits */
-#define CEPD3_OFS ( 3) /* CEPD3 Offset */
-#define CEPD3 (0x0008) /* Port disable */
-/* CE0CTL3[CEPD4] Bits */
-#define CEPD4_OFS ( 4) /* CEPD4 Offset */
-#define CEPD4 (0x0010) /* Port disable */
-/* CE0CTL3[CEPD5] Bits */
-#define CEPD5_OFS ( 5) /* CEPD5 Offset */
-#define CEPD5 (0x0020) /* Port disable */
-/* CE0CTL3[CEPD6] Bits */
-#define CEPD6_OFS ( 6) /* CEPD6 Offset */
-#define CEPD6 (0x0040) /* Port disable */
-/* CE0CTL3[CEPD7] Bits */
-#define CEPD7_OFS ( 7) /* CEPD7 Offset */
-#define CEPD7 (0x0080) /* Port disable */
-/* CE0CTL3[CEPD8] Bits */
-#define CEPD8_OFS ( 8) /* CEPD8 Offset */
-#define CEPD8 (0x0100) /* Port disable */
-/* CE0CTL3[CEPD9] Bits */
-#define CEPD9_OFS ( 9) /* CEPD9 Offset */
-#define CEPD9 (0x0200) /* Port disable */
-/* CE0CTL3[CEPD10] Bits */
-#define CEPD10_OFS (10) /* CEPD10 Offset */
-#define CEPD10 (0x0400) /* Port disable */
-/* CE0CTL3[CEPD11] Bits */
-#define CEPD11_OFS (11) /* CEPD11 Offset */
-#define CEPD11 (0x0800) /* Port disable */
-/* CE0CTL3[CEPD12] Bits */
-#define CEPD12_OFS (12) /* CEPD12 Offset */
-#define CEPD12 (0x1000) /* Port disable */
-/* CE0CTL3[CEPD13] Bits */
-#define CEPD13_OFS (13) /* CEPD13 Offset */
-#define CEPD13 (0x2000) /* Port disable */
-/* CE0CTL3[CEPD14] Bits */
-#define CEPD14_OFS (14) /* CEPD14 Offset */
-#define CEPD14 (0x4000) /* Port disable */
-/* CE0CTL3[CEPD15] Bits */
-#define CEPD15_OFS (15) /* CEPD15 Offset */
-#define CEPD15 (0x8000) /* Port disable */
-/* CE0INT[CEIFG] Bits */
-#define CEIFG_OFS ( 0) /* CEIFG Offset */
-#define CEIFG (0x0001) /* Comparator output interrupt flag */
-/* CE0INT[CEIIFG] Bits */
-#define CEIIFG_OFS ( 1) /* CEIIFG Offset */
-#define CEIIFG (0x0002) /* Comparator output inverted interrupt flag */
-/* CE0INT[CERDYIFG] Bits */
-#define CERDYIFG_OFS ( 4) /* CERDYIFG Offset */
-#define CERDYIFG (0x0010) /* Comparator ready interrupt flag */
-/* CE0INT[CEIE] Bits */
-#define CEIE_OFS ( 8) /* CEIE Offset */
-#define CEIE (0x0100) /* Comparator output interrupt enable */
-/* CE0INT[CEIIE] Bits */
-#define CEIIE_OFS ( 9) /* CEIIE Offset */
-#define CEIIE (0x0200) /* Comparator output interrupt enable inverted polarity */
-/* CE0INT[CERDYIE] Bits */
-#define CERDYIE_OFS (12) /* CERDYIE Offset */
-#define CERDYIE (0x1000) /* Comparator ready interrupt enable */
+/******************************************************************************
+* CAPTIO Bits
+******************************************************************************/
+/* CAPTIO_CTL[PISEL] Bits */
+#define CAPTIO_CTL_PISEL_OFS ( 1) /**< CAPTIOPISELx Bit Offset */
+#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /**< CAPTIOPISELx Bit Mask */
+#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /**< PISEL Bit 0 */
+#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /**< PISEL Bit 1 */
+#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /**< PISEL Bit 2 */
+#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /**< Px.0 */
+#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /**< Px.1 */
+#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /**< Px.2 */
+#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /**< Px.3 */
+#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /**< Px.4 */
+#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /**< Px.5 */
+#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /**< Px.6 */
+#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /**< Px.7 */
+/* CAPTIO_CTL[POSEL] Bits */
+#define CAPTIO_CTL_POSEL_OFS ( 4) /**< CAPTIOPOSELx Bit Offset */
+#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /**< CAPTIOPOSELx Bit Mask */
+#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /**< POSEL Bit 0 */
+#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /**< POSEL Bit 1 */
+#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /**< POSEL Bit 2 */
+#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /**< POSEL Bit 3 */
+#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /**< Px = PJ */
+#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /**< Px = P1 */
+#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /**< Px = P2 */
+#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /**< Px = P3 */
+#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /**< Px = P4 */
+#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /**< Px = P5 */
+#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /**< Px = P6 */
+#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /**< Px = P7 */
+#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /**< Px = P8 */
+#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /**< Px = P9 */
+#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /**< Px = P10 */
+#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /**< Px = P11 */
+#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /**< Px = P12 */
+#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /**< Px = P13 */
+#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /**< Px = P14 */
+#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /**< Px = P15 */
+#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /**< Px = PJ */
+#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /**< Px = P1 */
+#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /**< Px = P2 */
+#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /**< Px = P3 */
+#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /**< Px = P4 */
+#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /**< Px = P5 */
+#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /**< Px = P6 */
+#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /**< Px = P7 */
+#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /**< Px = P8 */
+#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /**< Px = P9 */
+#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /**< Px = P10 */
+#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /**< Px = P11 */
+#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /**< Px = P12 */
+#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /**< Px = P13 */
+#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /**< Px = P14 */
+#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /**< Px = P15 */
+/* CAPTIO_CTL[EN] Bits */
+#define CAPTIO_CTL_EN_OFS ( 8) /**< CAPTIOEN Bit Offset */
+#define CAPTIO_CTL_EN ((uint16_t)0x0100) /**< Capacitive Touch IO enable */
+/* CAPTIO_CTL[STATE] Bits */
+#define CAPTIO_CTL_STATE_OFS ( 9) /**< CAPTIOSTATE Bit Offset */
+#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /**< Capacitive Touch IO state */
-//*****************************************************************************
-// COMP_E1 Bits
-//*****************************************************************************
-/* CE1CTL0[CEIPSEL] Bits */
-//#define CEIPSEL_OFS ( 0) /* CEIPSEL Offset */
-//#define CEIPSEL_M (0x000f) /* Channel input selected for the V+ terminal */
-//#define CEIPSEL0 (0x0001) /* Channel input selected for the V+ terminal */
-//#define CEIPSEL1 (0x0002) /* Channel input selected for the V+ terminal */
-//#define CEIPSEL2 (0x0004) /* Channel input selected for the V+ terminal */
-//#define CEIPSEL3 (0x0008) /* Channel input selected for the V+ terminal */
-//#define CEIPSEL_0 (0x0000) /* Channel 0 selected */
-//#define CEIPSEL_1 (0x0001) /* Channel 1 selected */
-//#define CEIPSEL_2 (0x0002) /* Channel 2 selected */
-//#define CEIPSEL_3 (0x0003) /* Channel 3 selected */
-//#define CEIPSEL_4 (0x0004) /* Channel 4 selected */
-//#define CEIPSEL_5 (0x0005) /* Channel 5 selected */
-//#define CEIPSEL_6 (0x0006) /* Channel 6 selected */
-//#define CEIPSEL_7 (0x0007) /* Channel 7 selected */
-//#define CEIPSEL_8 (0x0008) /* Channel 8 selected */
-//#define CEIPSEL_9 (0x0009) /* Channel 9 selected */
-//#define CEIPSEL_10 (0x000a) /* Channel 10 selected */
-//#define CEIPSEL_11 (0x000b) /* Channel 11 selected */
-//#define CEIPSEL_12 (0x000c) /* Channel 12 selected */
-//#define CEIPSEL_13 (0x000d) /* Channel 13 selected */
-//#define CEIPSEL_14 (0x000e) /* Channel 14 selected */
-//#define CEIPSEL_15 (0x000f) /* Channel 15 selected */
-/* CE1CTL0[CEIPEN] Bits */
-//#define CEIPEN_OFS ( 7) /* CEIPEN Offset */
-//#define CEIPEN (0x0080) /* Channel input enable for the V+ terminal */
-/* CE1CTL0[CEIMSEL] Bits */
-//#define CEIMSEL_OFS ( 8) /* CEIMSEL Offset */
-//#define CEIMSEL_M (0x0f00) /* Channel input selected for the - terminal */
-//#define CEIMSEL0 (0x0100) /* Channel input selected for the - terminal */
-//#define CEIMSEL1 (0x0200) /* Channel input selected for the - terminal */
-//#define CEIMSEL2 (0x0400) /* Channel input selected for the - terminal */
-//#define CEIMSEL3 (0x0800) /* Channel input selected for the - terminal */
-//#define CEIMSEL_0 (0x0000) /* Channel 0 selected */
-//#define CEIMSEL_1 (0x0100) /* Channel 1 selected */
-//#define CEIMSEL_2 (0x0200) /* Channel 2 selected */
-//#define CEIMSEL_3 (0x0300) /* Channel 3 selected */
-//#define CEIMSEL_4 (0x0400) /* Channel 4 selected */
-//#define CEIMSEL_5 (0x0500) /* Channel 5 selected */
-//#define CEIMSEL_6 (0x0600) /* Channel 6 selected */
-//#define CEIMSEL_7 (0x0700) /* Channel 7 selected */
-//#define CEIMSEL_8 (0x0800) /* Channel 8 selected */
-//#define CEIMSEL_9 (0x0900) /* Channel 9 selected */
-//#define CEIMSEL_10 (0x0a00) /* Channel 10 selected */
-//#define CEIMSEL_11 (0x0b00) /* Channel 11 selected */
-//#define CEIMSEL_12 (0x0c00) /* Channel 12 selected */
-//#define CEIMSEL_13 (0x0d00) /* Channel 13 selected */
-//#define CEIMSEL_14 (0x0e00) /* Channel 14 selected */
-//#define CEIMSEL_15 (0x0f00) /* Channel 15 selected */
-/* CE1CTL0[CEIMEN] Bits */
-//#define CEIMEN_OFS (15) /* CEIMEN Offset */
-//#define CEIMEN (0x8000) /* Channel input enable for the - terminal */
-/* CE1CTL1[CEOUT] Bits */
-//#define CEOUT_OFS ( 0) /* CEOUT Offset */
-//#define CEOUT (0x0001) /* Comparator output value */
-/* CE1CTL1[CEOUTPOL] Bits */
-//#define CEOUTPOL_OFS ( 1) /* CEOUTPOL Offset */
-//#define CEOUTPOL (0x0002) /* Comparator output polarity */
-/* CE1CTL1[CEF] Bits */
-//#define CEF_OFS ( 2) /* CEF Offset */
-//#define CEF (0x0004) /* Comparator output filter */
-/* CE1CTL1[CEIES] Bits */
-//#define CEIES_OFS ( 3) /* CEIES Offset */
-//#define CEIES (0x0008) /* Interrupt edge select for CEIIFG and CEIFG */
-/* CE1CTL1[CESHORT] Bits */
-//#define CESHORT_OFS ( 4) /* CESHORT Offset */
-//#define CESHORT (0x0010) /* Input short */
-/* CE1CTL1[CEEX] Bits */
-//#define CEEX_OFS ( 5) /* CEEX Offset */
-//#define CEEX (0x0020) /* Exchange */
-/* CE1CTL1[CEFDLY] Bits */
-//#define CEFDLY_OFS ( 6) /* CEFDLY Offset */
-//#define CEFDLY_M (0x00c0) /* Filter delay */
-//#define CEFDLY0 (0x0040) /* Filter delay */
-//#define CEFDLY1 (0x0080) /* Filter delay */
-//#define CEFDLY_0 (0x0000) /* Typical filter delay of TBD (450) ns */
-//#define CEFDLY_1 (0x0040) /* Typical filter delay of TBD (900) ns */
-//#define CEFDLY_2 (0x0080) /* Typical filter delay of TBD (1800) ns */
-//#define CEFDLY_3 (0x00c0) /* Typical filter delay of TBD (3600) ns */
-/* CE1CTL1[CEPWRMD] Bits */
-//#define CEPWRMD_OFS ( 8) /* CEPWRMD Offset */
-//#define CEPWRMD_M (0x0300) /* Power Mode */
-//#define CEPWRMD0 (0x0100) /* Power Mode */
-//#define CEPWRMD1 (0x0200) /* Power Mode */
-//#define CEPWRMD_0 (0x0000) /* High-speed mode */
-//#define CEPWRMD_1 (0x0100) /* Normal mode */
-//#define CEPWRMD_2 (0x0200) /* Ultra-low power mode */
-/* CE1CTL1[CEON] Bits */
-//#define CEON_OFS (10) /* CEON Offset */
-//#define CEON (0x0400) /* Comparator On */
-/* CE1CTL1[CEMRVL] Bits */
-//#define CEMRVL_OFS (11) /* CEMRVL Offset */
-//#define CEMRVL (0x0800) /* This bit is valid of CEMRVS is set to 1 */
-/* CE1CTL1[CEMRVS] Bits */
-//#define CEMRVS_OFS (12) /* CEMRVS Offset */
-//#define CEMRVS (0x1000) /* */
-/* CE1CTL2[CEREF0] Bits */
-//#define CEREF0_OFS ( 0) /* CEREF0 Offset */
-//#define CEREF0_M (0x001f) /* Reference resistor tap 0 */
-/* CE1CTL2[CERSEL] Bits */
-//#define CERSEL_OFS ( 5) /* CERSEL Offset */
-//#define CERSEL (0x0020) /* Reference select */
-/* CE1CTL2[CERS] Bits */
-//#define CERS_OFS ( 6) /* CERS Offset */
-//#define CERS_M (0x00c0) /* Reference source */
-//#define CERS0 (0x0040) /* Reference source */
-//#define CERS1 (0x0080) /* Reference source */
-//#define CERS_0 (0x0000) /* No current is drawn by the reference circuitry */
-//#define CERS_1 (0x0040) /* VCC applied to the resistor ladder */
-//#define CERS_2 (0x0080) /* Shared reference voltage applied to the resistor ladder */
-//#define CERS_3 (0x00c0) /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */
-/* CE1CTL2[CEREF1] Bits */
-//#define CEREF1_OFS ( 8) /* CEREF1 Offset */
-//#define CEREF1_M (0x1f00) /* Reference resistor tap 1 */
-/* CE1CTL2[CEREFL] Bits */
-//#define CEREFL_OFS (13) /* CEREFL Offset */
-//#define CEREFL_M (0x6000) /* Reference voltage level */
-//#define CEREFL0 (0x2000) /* Reference voltage level */
-//#define CEREFL1 (0x4000) /* Reference voltage level */
-//#define CEREFL_0 (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
-//#define CEREFL_1 (0x2000) /* 1.2 V is selected as shared reference voltage input */
-//#define CEREFL_2 (0x4000) /* 2.0 V is selected as shared reference voltage input */
-//#define CEREFL_3 (0x6000) /* 2.5 V is selected as shared reference voltage input */
-//#define CEREFL__OFF (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
-//#define CEREFL__1P2V (0x2000) /* 1.2 V is selected as shared reference voltage input */
-//#define CEREFL__2P0V (0x4000) /* 2.0 V is selected as shared reference voltage input */
-//#define CEREFL__2P5V (0x6000) /* 2.5 V is selected as shared reference voltage input */
-/* CE1CTL2[CEREFACC] Bits */
-//#define CEREFACC_OFS (15) /* CEREFACC Offset */
-//#define CEREFACC (0x8000) /* Reference accuracy */
-/* CE1CTL3[CEPD0] Bits */
-//#define CEPD0_OFS ( 0) /* CEPD0 Offset */
-//#define CEPD0 (0x0001) /* Port disable */
-/* CE1CTL3[CEPD1] Bits */
-//#define CEPD1_OFS ( 1) /* CEPD1 Offset */
-//#define CEPD1 (0x0002) /* Port disable */
-/* CE1CTL3[CEPD2] Bits */
-//#define CEPD2_OFS ( 2) /* CEPD2 Offset */
-//#define CEPD2 (0x0004) /* Port disable */
-/* CE1CTL3[CEPD3] Bits */
-//#define CEPD3_OFS ( 3) /* CEPD3 Offset */
-//#define CEPD3 (0x0008) /* Port disable */
-/* CE1CTL3[CEPD4] Bits */
-//#define CEPD4_OFS ( 4) /* CEPD4 Offset */
-//#define CEPD4 (0x0010) /* Port disable */
-/* CE1CTL3[CEPD5] Bits */
-//#define CEPD5_OFS ( 5) /* CEPD5 Offset */
-//#define CEPD5 (0x0020) /* Port disable */
-/* CE1CTL3[CEPD6] Bits */
-//#define CEPD6_OFS ( 6) /* CEPD6 Offset */
-//#define CEPD6 (0x0040) /* Port disable */
-/* CE1CTL3[CEPD7] Bits */
-//#define CEPD7_OFS ( 7) /* CEPD7 Offset */
-//#define CEPD7 (0x0080) /* Port disable */
-/* CE1CTL3[CEPD8] Bits */
-//#define CEPD8_OFS ( 8) /* CEPD8 Offset */
-//#define CEPD8 (0x0100) /* Port disable */
-/* CE1CTL3[CEPD9] Bits */
-//#define CEPD9_OFS ( 9) /* CEPD9 Offset */
-//#define CEPD9 (0x0200) /* Port disable */
-/* CE1CTL3[CEPD10] Bits */
-//#define CEPD10_OFS (10) /* CEPD10 Offset */
-//#define CEPD10 (0x0400) /* Port disable */
-/* CE1CTL3[CEPD11] Bits */
-//#define CEPD11_OFS (11) /* CEPD11 Offset */
-//#define CEPD11 (0x0800) /* Port disable */
-/* CE1CTL3[CEPD12] Bits */
-//#define CEPD12_OFS (12) /* CEPD12 Offset */
-//#define CEPD12 (0x1000) /* Port disable */
-/* CE1CTL3[CEPD13] Bits */
-//#define CEPD13_OFS (13) /* CEPD13 Offset */
-//#define CEPD13 (0x2000) /* Port disable */
-/* CE1CTL3[CEPD14] Bits */
-//#define CEPD14_OFS (14) /* CEPD14 Offset */
-//#define CEPD14 (0x4000) /* Port disable */
-/* CE1CTL3[CEPD15] Bits */
-//#define CEPD15_OFS (15) /* CEPD15 Offset */
-//#define CEPD15 (0x8000) /* Port disable */
-/* CE1INT[CEIFG] Bits */
-//#define CEIFG_OFS ( 0) /* CEIFG Offset */
-//#define CEIFG (0x0001) /* Comparator output interrupt flag */
-/* CE1INT[CEIIFG] Bits */
-//#define CEIIFG_OFS ( 1) /* CEIIFG Offset */
-//#define CEIIFG (0x0002) /* Comparator output inverted interrupt flag */
-/* CE1INT[CERDYIFG] Bits */
-//#define CERDYIFG_OFS ( 4) /* CERDYIFG Offset */
-//#define CERDYIFG (0x0010) /* Comparator ready interrupt flag */
-/* CE1INT[CEIE] Bits */
-//#define CEIE_OFS ( 8) /* CEIE Offset */
-//#define CEIE (0x0100) /* Comparator output interrupt enable */
-/* CE1INT[CEIIE] Bits */
-//#define CEIIE_OFS ( 9) /* CEIIE Offset */
-//#define CEIIE (0x0200) /* Comparator output interrupt enable inverted polarity */
-/* CE1INT[CERDYIE] Bits */
-//#define CERDYIE_OFS (12) /* CERDYIE Offset */
-//#define CERDYIE (0x1000) /* Comparator ready interrupt enable */
+/******************************************************************************
+* COMP_E Bits
+******************************************************************************/
+/* COMP_E_CTL0[IPSEL] Bits */
+#define COMP_E_CTL0_IPSEL_OFS ( 0) /**< CEIPSEL Bit Offset */
+#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /**< CEIPSEL Bit Mask */
+#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /**< IPSEL Bit 0 */
+#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /**< IPSEL Bit 1 */
+#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /**< IPSEL Bit 2 */
+#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /**< IPSEL Bit 3 */
+#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /**< Channel 0 selected */
+#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /**< Channel 1 selected */
+#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /**< Channel 2 selected */
+#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /**< Channel 3 selected */
+#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /**< Channel 4 selected */
+#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /**< Channel 5 selected */
+#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /**< Channel 6 selected */
+#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /**< Channel 7 selected */
+#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /**< Channel 8 selected */
+#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /**< Channel 9 selected */
+#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /**< Channel 10 selected */
+#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /**< Channel 11 selected */
+#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /**< Channel 12 selected */
+#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /**< Channel 13 selected */
+#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /**< Channel 14 selected */
+#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /**< Channel 15 selected */
+/* COMP_E_CTL0[IPEN] Bits */
+#define COMP_E_CTL0_IPEN_OFS ( 7) /**< CEIPEN Bit Offset */
+#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /**< Channel input enable for the V+ terminal */
+/* COMP_E_CTL0[IMSEL] Bits */
+#define COMP_E_CTL0_IMSEL_OFS ( 8) /**< CEIMSEL Bit Offset */
+#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /**< CEIMSEL Bit Mask */
+#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /**< IMSEL Bit 0 */
+#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /**< IMSEL Bit 1 */
+#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /**< IMSEL Bit 2 */
+#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /**< IMSEL Bit 3 */
+#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /**< Channel 0 selected */
+#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /**< Channel 1 selected */
+#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /**< Channel 2 selected */
+#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /**< Channel 3 selected */
+#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /**< Channel 4 selected */
+#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /**< Channel 5 selected */
+#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /**< Channel 6 selected */
+#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /**< Channel 7 selected */
+#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /**< Channel 8 selected */
+#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /**< Channel 9 selected */
+#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /**< Channel 10 selected */
+#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /**< Channel 11 selected */
+#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /**< Channel 12 selected */
+#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /**< Channel 13 selected */
+#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /**< Channel 14 selected */
+#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /**< Channel 15 selected */
+/* COMP_E_CTL0[IMEN] Bits */
+#define COMP_E_CTL0_IMEN_OFS (15) /**< CEIMEN Bit Offset */
+#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /**< Channel input enable for the - terminal */
+/* COMP_E_CTL1[OUT] Bits */
+#define COMP_E_CTL1_OUT_OFS ( 0) /**< CEOUT Bit Offset */
+#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /**< Comparator output value */
+/* COMP_E_CTL1[OUTPOL] Bits */
+#define COMP_E_CTL1_OUTPOL_OFS ( 1) /**< CEOUTPOL Bit Offset */
+#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /**< Comparator output polarity */
+/* COMP_E_CTL1[F] Bits */
+#define COMP_E_CTL1_F_OFS ( 2) /**< CEF Bit Offset */
+#define COMP_E_CTL1_F ((uint16_t)0x0004) /**< Comparator output filter */
+/* COMP_E_CTL1[IES] Bits */
+#define COMP_E_CTL1_IES_OFS ( 3) /**< CEIES Bit Offset */
+#define COMP_E_CTL1_IES ((uint16_t)0x0008) /**< Interrupt edge select for CEIIFG and CEIFG */
+/* COMP_E_CTL1[SHORT] Bits */
+#define COMP_E_CTL1_SHORT_OFS ( 4) /**< CESHORT Bit Offset */
+#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /**< Input short */
+/* COMP_E_CTL1[EX] Bits */
+#define COMP_E_CTL1_EX_OFS ( 5) /**< CEEX Bit Offset */
+#define COMP_E_CTL1_EX ((uint16_t)0x0020) /**< Exchange */
+/* COMP_E_CTL1[FDLY] Bits */
+#define COMP_E_CTL1_FDLY_OFS ( 6) /**< CEFDLY Bit Offset */
+#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /**< CEFDLY Bit Mask */
+#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /**< FDLY Bit 0 */
+#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /**< FDLY Bit 1 */
+#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /**< Typical filter delay of TBD (450) ns */
+#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /**< Typical filter delay of TBD (900) ns */
+#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /**< Typical filter delay of TBD (1800) ns */
+#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /**< Typical filter delay of TBD (3600) ns */
+/* COMP_E_CTL1[PWRMD] Bits */
+#define COMP_E_CTL1_PWRMD_OFS ( 8) /**< CEPWRMD Bit Offset */
+#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /**< CEPWRMD Bit Mask */
+#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /**< PWRMD Bit 0 */
+#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /**< PWRMD Bit 1 */
+#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /**< High-speed mode */
+#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /**< Normal mode */
+#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /**< Ultra-low power mode */
+/* COMP_E_CTL1[ON] Bits */
+#define COMP_E_CTL1_ON_OFS (10) /**< CEON Bit Offset */
+#define COMP_E_CTL1_ON ((uint16_t)0x0400) /**< Comparator On */
+/* COMP_E_CTL1[MRVL] Bits */
+#define COMP_E_CTL1_MRVL_OFS (11) /**< CEMRVL Bit Offset */
+#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /**< This bit is valid of CEMRVS is set to 1 */
+/* COMP_E_CTL1[MRVS] Bits */
+#define COMP_E_CTL1_MRVS_OFS (12) /**< CEMRVS Bit Offset */
+#define COMP_E_CTL1_MRVS ((uint16_t)0x1000)
+/* COMP_E_CTL2[REF0] Bits */
+#define COMP_E_CTL2_REF0_OFS ( 0) /**< CEREF0 Bit Offset */
+#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /**< CEREF0 Bit Mask */
+/* COMP_E_CTL2[RSEL] Bits */
+#define COMP_E_CTL2_RSEL_OFS ( 5) /**< CERSEL Bit Offset */
+#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /**< Reference select */
+/* COMP_E_CTL2[RS] Bits */
+#define COMP_E_CTL2_RS_OFS ( 6) /**< CERS Bit Offset */
+#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /**< CERS Bit Mask */
+#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /**< RS Bit 0 */
+#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /**< RS Bit 1 */
+#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /**< No current is drawn by the reference circuitry */
+#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /**< VCC applied to the resistor ladder */
+#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /**< Shared reference voltage applied to the resistor ladder */
+#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /**< Shared reference voltage supplied to V(CREF). Resistor ladder is off */
+/* COMP_E_CTL2[REF1] Bits */
+#define COMP_E_CTL2_REF1_OFS ( 8) /**< CEREF1 Bit Offset */
+#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /**< CEREF1 Bit Mask */
+/* COMP_E_CTL2[REFL] Bits */
+#define COMP_E_CTL2_REFL_OFS (13) /**< CEREFL Bit Offset */
+#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /**< CEREFL Bit Mask */
+#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /**< REFL Bit 0 */
+#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /**< REFL Bit 1 */
+#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /**< Reference amplifier is disabled. No reference voltage is requested */
+#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /**< 1.2 V is selected as shared reference voltage input */
+#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /**< 2.0 V is selected as shared reference voltage input */
+#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /**< 2.5 V is selected as shared reference voltage input */
+#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /**< Reference amplifier is disabled. No reference voltage is requested */
+#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /**< 1.2 V is selected as shared reference voltage input */
+#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /**< 2.0 V is selected as shared reference voltage input */
+#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /**< 2.5 V is selected as shared reference voltage input */
+/* COMP_E_CTL2[REFACC] Bits */
+#define COMP_E_CTL2_REFACC_OFS (15) /**< CEREFACC Bit Offset */
+#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /**< Reference accuracy */
+/* COMP_E_CTL3[PD0] Bits */
+#define COMP_E_CTL3_PD0_OFS ( 0) /**< CEPD0 Bit Offset */
+#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /**< Port disable */
+/* COMP_E_CTL3[PD1] Bits */
+#define COMP_E_CTL3_PD1_OFS ( 1) /**< CEPD1 Bit Offset */
+#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /**< Port disable */
+/* COMP_E_CTL3[PD2] Bits */
+#define COMP_E_CTL3_PD2_OFS ( 2) /**< CEPD2 Bit Offset */
+#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /**< Port disable */
+/* COMP_E_CTL3[PD3] Bits */
+#define COMP_E_CTL3_PD3_OFS ( 3) /**< CEPD3 Bit Offset */
+#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /**< Port disable */
+/* COMP_E_CTL3[PD4] Bits */
+#define COMP_E_CTL3_PD4_OFS ( 4) /**< CEPD4 Bit Offset */
+#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /**< Port disable */
+/* COMP_E_CTL3[PD5] Bits */
+#define COMP_E_CTL3_PD5_OFS ( 5) /**< CEPD5 Bit Offset */
+#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /**< Port disable */
+/* COMP_E_CTL3[PD6] Bits */
+#define COMP_E_CTL3_PD6_OFS ( 6) /**< CEPD6 Bit Offset */
+#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /**< Port disable */
+/* COMP_E_CTL3[PD7] Bits */
+#define COMP_E_CTL3_PD7_OFS ( 7) /**< CEPD7 Bit Offset */
+#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /**< Port disable */
+/* COMP_E_CTL3[PD8] Bits */
+#define COMP_E_CTL3_PD8_OFS ( 8) /**< CEPD8 Bit Offset */
+#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /**< Port disable */
+/* COMP_E_CTL3[PD9] Bits */
+#define COMP_E_CTL3_PD9_OFS ( 9) /**< CEPD9 Bit Offset */
+#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /**< Port disable */
+/* COMP_E_CTL3[PD10] Bits */
+#define COMP_E_CTL3_PD10_OFS (10) /**< CEPD10 Bit Offset */
+#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /**< Port disable */
+/* COMP_E_CTL3[PD11] Bits */
+#define COMP_E_CTL3_PD11_OFS (11) /**< CEPD11 Bit Offset */
+#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /**< Port disable */
+/* COMP_E_CTL3[PD12] Bits */
+#define COMP_E_CTL3_PD12_OFS (12) /**< CEPD12 Bit Offset */
+#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /**< Port disable */
+/* COMP_E_CTL3[PD13] Bits */
+#define COMP_E_CTL3_PD13_OFS (13) /**< CEPD13 Bit Offset */
+#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /**< Port disable */
+/* COMP_E_CTL3[PD14] Bits */
+#define COMP_E_CTL3_PD14_OFS (14) /**< CEPD14 Bit Offset */
+#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /**< Port disable */
+/* COMP_E_CTL3[PD15] Bits */
+#define COMP_E_CTL3_PD15_OFS (15) /**< CEPD15 Bit Offset */
+#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /**< Port disable */
+/* COMP_E_INT[IFG] Bits */
+#define COMP_E_INT_IFG_OFS ( 0) /**< CEIFG Bit Offset */
+#define COMP_E_INT_IFG ((uint16_t)0x0001) /**< Comparator output interrupt flag */
+/* COMP_E_INT[IIFG] Bits */
+#define COMP_E_INT_IIFG_OFS ( 1) /**< CEIIFG Bit Offset */
+#define COMP_E_INT_IIFG ((uint16_t)0x0002) /**< Comparator output inverted interrupt flag */
+/* COMP_E_INT[RDYIFG] Bits */
+#define COMP_E_INT_RDYIFG_OFS ( 4) /**< CERDYIFG Bit Offset */
+#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /**< Comparator ready interrupt flag */
+/* COMP_E_INT[IE] Bits */
+#define COMP_E_INT_IE_OFS ( 8) /**< CEIE Bit Offset */
+#define COMP_E_INT_IE ((uint16_t)0x0100) /**< Comparator output interrupt enable */
+/* COMP_E_INT[IIE] Bits */
+#define COMP_E_INT_IIE_OFS ( 9) /**< CEIIE Bit Offset */
+#define COMP_E_INT_IIE ((uint16_t)0x0200) /**< Comparator output interrupt enable inverted polarity */
+/* COMP_E_INT[RDYIE] Bits */
+#define COMP_E_INT_RDYIE_OFS (12) /**< CERDYIE Bit Offset */
+#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /**< Comparator ready interrupt enable */
-//*****************************************************************************
-// COREDEBUG Bits
-//*****************************************************************************
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_DEBUGEN] Bits */
-#define COREDEBUG_DHCSR_C_DEBUGEN_OFS ( 0) /* C_DEBUGEN Offset */
-#define COREDEBUG_DHCSR_C_DEBUGEN (0x00000001) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_HALT] Bits */
-#define COREDEBUG_DHCSR_C_HALT_OFS ( 1) /* C_HALT Offset */
-#define COREDEBUG_DHCSR_C_HALT (0x00000002) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_STEP] Bits */
-#define COREDEBUG_DHCSR_C_STEP_OFS ( 2) /* C_STEP Offset */
-#define COREDEBUG_DHCSR_C_STEP (0x00000004) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_MASKINTS] Bits */
-#define COREDEBUG_DHCSR_C_MASKINTS_OFS ( 3) /* C_MASKINTS Offset */
-#define COREDEBUG_DHCSR_C_MASKINTS (0x00000008) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_SNAPSTALL] Bits */
-#define COREDEBUG_DHCSR_C_SNAPSTALL_OFS ( 5) /* C_SNAPSTALL Offset */
-#define COREDEBUG_DHCSR_C_SNAPSTALL (0x00000020) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_REGRDY] Bits */
-#define COREDEBUG_DHCSR_S_REGRDY_OFS (16) /* S_REGRDY Offset */
-#define COREDEBUG_DHCSR_S_REGRDY (0x00010000) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_HALT] Bits */
-#define COREDEBUG_DHCSR_S_HALT_OFS (17) /* S_HALT Offset */
-#define COREDEBUG_DHCSR_S_HALT (0x00020000) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_SLEEP] Bits */
-#define COREDEBUG_DHCSR_S_SLEEP_OFS (18) /* S_SLEEP Offset */
-#define COREDEBUG_DHCSR_S_SLEEP (0x00040000) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_LOCKUP] Bits */
-#define COREDEBUG_DHCSR_S_LOCKUP_OFS (19) /* S_LOCKUP Offset */
-#define COREDEBUG_DHCSR_S_LOCKUP (0x00080000) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RETIRE_ST] Bits */
-#define COREDEBUG_DHCSR_S_RETIRE_ST_OFS (24) /* S_RETIRE_ST Offset */
-#define COREDEBUG_DHCSR_S_RETIRE_ST (0x01000000) /* */
-/* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RESET_ST] Bits */
-#define COREDEBUG_DHCSR_S_RESET_ST_OFS (25) /* S_RESET_ST Offset */
-#define COREDEBUG_DHCSR_S_RESET_ST (0x02000000) /* */
-/* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGSEL] Bits */
-#define COREDEBUG_DCRSR_REGSEL_OFS ( 0) /* REGSEL Offset */
-#define COREDEBUG_DCRSR_REGSEL_M (0x0000001f) /* */
-#define COREDEBUG_DCRSR_REGSEL0 (0x00000001) /* */
-#define COREDEBUG_DCRSR_REGSEL1 (0x00000002) /* */
-#define COREDEBUG_DCRSR_REGSEL2 (0x00000004) /* */
-#define COREDEBUG_DCRSR_REGSEL3 (0x00000008) /* */
-#define COREDEBUG_DCRSR_REGSEL4 (0x00000010) /* */
-#define COREDEBUG_DCRSR_REGSEL_0 (0x00000000) /* R11 */
-//#define COREDEBUG_DCRSR_REGSEL_0 (0x00000000) /* R0 */
-#define COREDEBUG_DCRSR_REGSEL_1 (0x00000001) /* R1 */
-#define COREDEBUG_DCRSR_REGSEL_2 (0x00000002) /* R2 */
-#define COREDEBUG_DCRSR_REGSEL_3 (0x00000003) /* R3 */
-#define COREDEBUG_DCRSR_REGSEL_4 (0x00000004) /* R4 */
-#define COREDEBUG_DCRSR_REGSEL_5 (0x00000005) /* R5 */
-#define COREDEBUG_DCRSR_REGSEL_6 (0x00000006) /* R6 */
-#define COREDEBUG_DCRSR_REGSEL_7 (0x00000007) /* R7 */
-#define COREDEBUG_DCRSR_REGSEL_8 (0x00000008) /* R8 */
-#define COREDEBUG_DCRSR_REGSEL_9 (0x00000009) /* R9 */
-#define COREDEBUG_DCRSR_REGSEL_10 (0x0000000a) /* R10 */
-#define COREDEBUG_DCRSR_REGSEL_12 (0x0000000c) /* R12 */
-#define COREDEBUG_DCRSR_REGSEL_13 (0x0000000d) /* Current SP */
-#define COREDEBUG_DCRSR_REGSEL_14 (0x0000000e) /* LR */
-#define COREDEBUG_DCRSR_REGSEL_15 (0x0000000f) /* DebugReturnAddress */
-#define COREDEBUG_DCRSR_REGSEL_16 (0x00000010) /* xPSR/flags, execution state information, and exception number */
-#define COREDEBUG_DCRSR_REGSEL_17 (0x00000011) /* MSP (Main SP) */
-#define COREDEBUG_DCRSR_REGSEL_18 (0x00000012) /* PSP (Process SP) */
-#define COREDEBUG_DCRSR_REGSEL_20 (0x00000014) /* CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0] */
-/* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGWNR] Bits */
-#define COREDEBUG_DCRSR_REGWNR_OFS (16) /* REGWNR Offset */
-#define COREDEBUG_DCRSR_REGWNR (0x00010000) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CORERESET] Bits */
-#define COREDEBUG_DEMCR_VC_CORERESET_OFS ( 0) /* VC_CORERESET Offset */
-#define COREDEBUG_DEMCR_VC_CORERESET (0x00000001) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_MMERR] Bits */
-#define COREDEBUG_DEMCR_VC_MMERR_OFS ( 4) /* VC_MMERR Offset */
-#define COREDEBUG_DEMCR_VC_MMERR (0x00000010) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_NOCPERR] Bits */
-#define COREDEBUG_DEMCR_VC_NOCPERR_OFS ( 5) /* VC_NOCPERR Offset */
-#define COREDEBUG_DEMCR_VC_NOCPERR (0x00000020) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CHKERR] Bits */
-#define COREDEBUG_DEMCR_VC_CHKERR_OFS ( 6) /* VC_CHKERR Offset */
-#define COREDEBUG_DEMCR_VC_CHKERR (0x00000040) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_STATERR] Bits */
-#define COREDEBUG_DEMCR_VC_STATERR_OFS ( 7) /* VC_STATERR Offset */
-#define COREDEBUG_DEMCR_VC_STATERR (0x00000080) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_BUSERR] Bits */
-#define COREDEBUG_DEMCR_VC_BUSERR_OFS ( 8) /* VC_BUSERR Offset */
-#define COREDEBUG_DEMCR_VC_BUSERR (0x00000100) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_INTERR] Bits */
-#define COREDEBUG_DEMCR_VC_INTERR_OFS ( 9) /* VC_INTERR Offset */
-#define COREDEBUG_DEMCR_VC_INTERR (0x00000200) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_HARDERR] Bits */
-#define COREDEBUG_DEMCR_VC_HARDERR_OFS (10) /* VC_HARDERR Offset */
-#define COREDEBUG_DEMCR_VC_HARDERR (0x00000400) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_EN] Bits */
-#define COREDEBUG_DEMCR_MON_EN_OFS (16) /* MON_EN Offset */
-#define COREDEBUG_DEMCR_MON_EN (0x00010000) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_PEND] Bits */
-#define COREDEBUG_DEMCR_MON_PEND_OFS (17) /* MON_PEND Offset */
-#define COREDEBUG_DEMCR_MON_PEND (0x00020000) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_STEP] Bits */
-#define COREDEBUG_DEMCR_MON_STEP_OFS (18) /* MON_STEP Offset */
-#define COREDEBUG_DEMCR_MON_STEP (0x00040000) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_REQ] Bits */
-#define COREDEBUG_DEMCR_MON_REQ_OFS (19) /* MON_REQ Offset */
-#define COREDEBUG_DEMCR_MON_REQ (0x00080000) /* */
-/* COREDEBUG_DEMCR[COREDEBUG_DEMCR_TRCENA] Bits */
-#define COREDEBUG_DEMCR_TRCENA_OFS (24) /* TRCENA Offset */
-#define COREDEBUG_DEMCR_TRCENA (0x01000000) /* */
+/******************************************************************************
+* COREDEBUG Bits
+******************************************************************************/
-//*****************************************************************************
-// CRC32 Bits
-//*****************************************************************************
+/******************************************************************************
+* CRC32 Bits
+******************************************************************************/
-//*****************************************************************************
-// CS Bits
-//*****************************************************************************
-/* CSKEY[CSKEY] Bits */
-#define CSKEY_OFS ( 0) /* CSKEY Offset */
-#define CSKEY_M (0x0000ffff) /* Write xxxx_695Ah to unlock */
-/* CSCTL0[DCOTUNE] Bits */
-#define DCOTUNE_OFS ( 0) /* DCOTUNE Offset */
-#define DCOTUNE_M (0x00001fff) /* DCO frequency tuning select */
-/* CSCTL0[DCORSEL] Bits */
-#define DCORSEL_OFS (16) /* DCORSEL Offset */
-#define DCORSEL_M (0x00070000) /* DCO frequency range select */
-#define DCORSEL0 (0x00010000) /* DCO frequency range select */
-#define DCORSEL1 (0x00020000) /* DCO frequency range select */
-#define DCORSEL2 (0x00040000) /* DCO frequency range select */
-#define DCORSEL_0 (0x00000000) /* Nominal DCO Frequency Range (MHz): 1 to 2 */
-#define DCORSEL_1 (0x00010000) /* Nominal DCO Frequency Range (MHz): 2 to 4 */
-#define DCORSEL_2 (0x00020000) /* Nominal DCO Frequency Range (MHz): 4 to 8 */
-#define DCORSEL_3 (0x00030000) /* Nominal DCO Frequency Range (MHz): 8 to 16 */
-#define DCORSEL_4 (0x00040000) /* Nominal DCO Frequency Range (MHz): 16 to 32 */
-#define DCORSEL_5 (0x00050000) /* Nominal DCO Frequency Range (MHz): 32 to 64 */
-/* CSCTL0[DCORES] Bits */
-#define DCORES_OFS (22) /* DCORES Offset */
-#define DCORES (0x00400000) /* Enables the DCO external resistor mode */
-/* CSCTL0[DCOEN] Bits */
-#define DCOEN_OFS (23) /* DCOEN Offset */
-#define DCOEN (0x00800000) /* Enables the DCO oscillator */
-/* CSCTL0[DIS_DCO_DELAY_CNT] Bits */
-#define DIS_DCO_DELAY_CNT_OFS (24) /* DIS_DCO_DELAY_CNT Offset */
-#define DIS_DCO_DELAY_CNT (0x01000000) /* */
-/* CSCTL1[SELM] Bits */
-#define SELM_OFS ( 0) /* SELM Offset */
-#define SELM_M (0x00000007) /* Selects the MCLK source */
-#define SELM0 (0x00000001) /* Selects the MCLK source */
-#define SELM1 (0x00000002) /* Selects the MCLK source */
-#define SELM2 (0x00000004) /* Selects the MCLK source */
-#define SELM_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */
-#define SELM_1 (0x00000001) /* */
-#define SELM_2 (0x00000002) /* */
-#define SELM_3 (0x00000003) /* */
-#define SELM_4 (0x00000004) /* */
-#define SELM_5 (0x00000005) /* when HFXT available, otherwise DCOCLK */
-#define SELM_6 (0x00000006) /* when HFXT2 available, otherwise DCOCLK */
-#define SELM__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */
-#define SELM__VLOCLK (0x00000001) /* */
-#define SELM__REFOCLK (0x00000002) /* */
-#define SELM__DCOCLK (0x00000003) /* */
-#define SELM__MODOSC (0x00000004) /* */
-#define SELM__HFXTCLK (0x00000005) /* when HFXT available, otherwise DCOCLK */
-#define SELM__HFXT2CLK (0x00000006) /* when HFXT2 available, otherwise DCOCLK */
-#define SELM_7 (0x00000007) /* for future use. Defaults to DCOCLK. Not recommended for use to ensure future compatibilities. */
-/* CSCTL1[SELS] Bits */
-#define SELS_OFS ( 4) /* SELS Offset */
-#define SELS_M (0x00000070) /* Selects the SMCLK and HSMCLK source */
-#define SELS0 (0x00000010) /* Selects the SMCLK and HSMCLK source */
-#define SELS1 (0x00000020) /* Selects the SMCLK and HSMCLK source */
-#define SELS2 (0x00000040) /* Selects the SMCLK and HSMCLK source */
-#define SELS_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */
-#define SELS_1 (0x00000010) /* */
-#define SELS_2 (0x00000020) /* */
-#define SELS_3 (0x00000030) /* */
-#define SELS_4 (0x00000040) /* */
-#define SELS_5 (0x00000050) /* when HFXT available, otherwise DCOCLK */
-#define SELS_6 (0x00000060) /* when HFXT2 available, otherwise DCOCLK */
-#define SELS__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */
-#define SELS__VLOCLK (0x00000010) /* */
-#define SELS__REFOCLK (0x00000020) /* */
-#define SELS__DCOCLK (0x00000030) /* */
-#define SELS__MODOSC (0x00000040) /* */
-#define SELS__HFXTCLK (0x00000050) /* when HFXT available, otherwise DCOCLK */
-#define SELS__HFXT2CLK (0x00000060) /* when HFXT2 available, otherwise DCOCLK */
-#define SELS_7 (0x00000070) /* for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities. */
-/* CSCTL1[SELA] Bits */
-#define SELA_OFS ( 8) /* SELA Offset */
-#define SELA_M (0x00000700) /* Selects the ACLK source */
-#define SELA0 (0x00000100) /* Selects the ACLK source */
-#define SELA1 (0x00000200) /* Selects the ACLK source */
-#define SELA2 (0x00000400) /* Selects the ACLK source */
-#define SELA_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */
-#define SELA_1 (0x00000100) /* */
-#define SELA_2 (0x00000200) /* */
-#define SELA__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */
-#define SELA__VLOCLK (0x00000100) /* */
-#define SELA__REFOCLK (0x00000200) /* */
-#define SELA_3 (0x00000300) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
-#define SELA_4 (0x00000400) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
-#define SELA_5 (0x00000500) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
-#define SELA_6 (0x00000600) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
-#define SELA_7 (0x00000700) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
-/* CSCTL1[SELB] Bits */
-#define SELB_OFS (12) /* SELB Offset */
-#define SELB (0x00001000) /* Selects the BCLK source */
-/* CSCTL1[DIVM] Bits */
-#define DIVM_OFS (16) /* DIVM Offset */
-#define DIVM_M (0x00070000) /* MCLK source divider */
-#define DIVM0 (0x00010000) /* MCLK source divider */
-#define DIVM1 (0x00020000) /* MCLK source divider */
-#define DIVM2 (0x00040000) /* MCLK source divider */
-#define DIVM_0 (0x00000000) /* f(MCLK)/1 */
-#define DIVM_1 (0x00010000) /* f(MCLK)/2 */
-#define DIVM_2 (0x00020000) /* f(MCLK)/4 */
-#define DIVM_3 (0x00030000) /* f(MCLK)/8 */
-#define DIVM_4 (0x00040000) /* f(MCLK)/16 */
-#define DIVM_5 (0x00050000) /* f(MCLK)/32 */
-#define DIVM_6 (0x00060000) /* f(MCLK)/64 */
-#define DIVM_7 (0x00070000) /* f(MCLK)/128 */
-#define DIVM__1 (0x00000000) /* f(MCLK)/1 */
-#define DIVM__2 (0x00010000) /* f(MCLK)/2 */
-#define DIVM__4 (0x00020000) /* f(MCLK)/4 */
-#define DIVM__8 (0x00030000) /* f(MCLK)/8 */
-#define DIVM__16 (0x00040000) /* f(MCLK)/16 */
-#define DIVM__32 (0x00050000) /* f(MCLK)/32 */
-#define DIVM__64 (0x00060000) /* f(MCLK)/64 */
-#define DIVM__128 (0x00070000) /* f(MCLK)/128 */
-/* CSCTL1[DIVHS] Bits */
-#define DIVHS_OFS (20) /* DIVHS Offset */
-#define DIVHS_M (0x00700000) /* HSMCLK source divider */
-#define DIVHS0 (0x00100000) /* HSMCLK source divider */
-#define DIVHS1 (0x00200000) /* HSMCLK source divider */
-#define DIVHS2 (0x00400000) /* HSMCLK source divider */
-#define DIVHS_0 (0x00000000) /* f(HSMCLK)/1 */
-#define DIVHS_1 (0x00100000) /* f(HSMCLK)/2 */
-#define DIVHS_2 (0x00200000) /* f(HSMCLK)/4 */
-#define DIVHS_3 (0x00300000) /* f(HSMCLK)/8 */
-#define DIVHS_4 (0x00400000) /* f(HSMCLK)/16 */
-#define DIVHS_5 (0x00500000) /* f(HSMCLK)/32 */
-#define DIVHS_6 (0x00600000) /* f(HSMCLK)/64 */
-#define DIVHS_7 (0x00700000) /* f(HSMCLK)/128 */
-#define DIVHS__1 (0x00000000) /* f(HSMCLK)/1 */
-#define DIVHS__2 (0x00100000) /* f(HSMCLK)/2 */
-#define DIVHS__4 (0x00200000) /* f(HSMCLK)/4 */
-#define DIVHS__8 (0x00300000) /* f(HSMCLK)/8 */
-#define DIVHS__16 (0x00400000) /* f(HSMCLK)/16 */
-#define DIVHS__32 (0x00500000) /* f(HSMCLK)/32 */
-#define DIVHS__64 (0x00600000) /* f(HSMCLK)/64 */
-#define DIVHS__128 (0x00700000) /* f(HSMCLK)/128 */
-/* CSCTL1[DIVA] Bits */
-#define DIVA_OFS (24) /* DIVA Offset */
-#define DIVA_M (0x07000000) /* ACLK source divider */
-#define DIVA0 (0x01000000) /* ACLK source divider */
-#define DIVA1 (0x02000000) /* ACLK source divider */
-#define DIVA2 (0x04000000) /* ACLK source divider */
-#define DIVA_0 (0x00000000) /* f(ACLK)/1 */
-#define DIVA_1 (0x01000000) /* f(ACLK)/2 */
-#define DIVA_2 (0x02000000) /* f(ACLK)/4 */
-#define DIVA_3 (0x03000000) /* f(ACLK)/8 */
-#define DIVA_4 (0x04000000) /* f(ACLK)/16 */
-#define DIVA_5 (0x05000000) /* f(ACLK)/32 */
-#define DIVA_6 (0x06000000) /* f(ACLK)/64 */
-#define DIVA_7 (0x07000000) /* f(ACLK)/128 */
-#define DIVA__1 (0x00000000) /* f(ACLK)/1 */
-#define DIVA__2 (0x01000000) /* f(ACLK)/2 */
-#define DIVA__4 (0x02000000) /* f(ACLK)/4 */
-#define DIVA__8 (0x03000000) /* f(ACLK)/8 */
-#define DIVA__16 (0x04000000) /* f(ACLK)/16 */
-#define DIVA__32 (0x05000000) /* f(ACLK)/32 */
-#define DIVA__64 (0x06000000) /* f(ACLK)/64 */
-#define DIVA__128 (0x07000000) /* f(ACLK)/128 */
-/* CSCTL1[DIVS] Bits */
-#define DIVS_OFS (28) /* DIVS Offset */
-#define DIVS_M (0x70000000) /* SMCLK source divider */
-#define DIVS0 (0x10000000) /* SMCLK source divider */
-#define DIVS1 (0x20000000) /* SMCLK source divider */
-#define DIVS2 (0x40000000) /* SMCLK source divider */
-#define DIVS_0 (0x00000000) /* f(SMCLK)/1 */
-#define DIVS_1 (0x10000000) /* f(SMCLK)/2 */
-#define DIVS_2 (0x20000000) /* f(SMCLK)/4 */
-#define DIVS_3 (0x30000000) /* f(SMCLK)/8 */
-#define DIVS_4 (0x40000000) /* f(SMCLK)/16 */
-#define DIVS_5 (0x50000000) /* f(SMCLK)/32 */
-#define DIVS_6 (0x60000000) /* f(SMCLK)/64 */
-#define DIVS_7 (0x70000000) /* f(SMCLK)/128 */
-#define DIVS__1 (0x00000000) /* f(SMCLK)/1 */
-#define DIVS__2 (0x10000000) /* f(SMCLK)/2 */
-#define DIVS__4 (0x20000000) /* f(SMCLK)/4 */
-#define DIVS__8 (0x30000000) /* f(SMCLK)/8 */
-#define DIVS__16 (0x40000000) /* f(SMCLK)/16 */
-#define DIVS__32 (0x50000000) /* f(SMCLK)/32 */
-#define DIVS__64 (0x60000000) /* f(SMCLK)/64 */
-#define DIVS__128 (0x70000000) /* f(SMCLK)/128 */
-/* CSCTL2[LFXTDRIVE] Bits */
-#define LFXTDRIVE_OFS ( 0) /* LFXTDRIVE Offset */
-#define LFXTDRIVE_M (0x00000007) /* LFXT oscillator current can be adjusted to its drive needs */
-#define LFXTDRIVE0 (0x00000001) /* LFXT oscillator current can be adjusted to its drive needs */
-#define LFXTDRIVE1 (0x00000002) /* LFXT oscillator current can be adjusted to its drive needs */
-#define LFXTDRIVE2 (0x00000004) /* LFXT oscillator current can be adjusted to its drive needs */
-#define LFXTDRIVE_0 (0x00000000) /* Lowest current consumption. */
-#define LFXTDRIVE_1 (0x00000001) /* Increased drive strength LFXT oscillator. */
-#define LFXTDRIVE_2 (0x00000002) /* Increased drive strength LFXT oscillator. */
-#define LFXTDRIVE_3 (0x00000003) /* Increased drive strength LFXT oscillator. */
-#define LFXTDRIVE_4 (0x00000004) /* Increased drive strength LFXT oscillator. */
-#define LFXTDRIVE_5 (0x00000005) /* Increased drive strength LFXT oscillator. */
-#define LFXTDRIVE_6 (0x00000006) /* Increased drive strength LFXT oscillator. */
-#define LFXTDRIVE_7 (0x00000007) /* Maximum drive strength LFXT oscillator. */
-/* CSCTL2[LFXTAGCOFF] Bits */
-#define LFXTAGCOFF_OFS ( 7) /* LFXTAGCOFF Offset */
-#define LFXTAGCOFF (0x00000080) /* Disables the automatic gain control of the LFXT crystal */
-/* CSCTL2[LFXT_EN] Bits */
-#define LFXT_EN_OFS ( 8) /* LFXT_EN Offset */
-#define LFXT_EN (0x00000100) /* Turns on the LFXT oscillator regardless if used as a clock resource */
-/* CSCTL2[LFXTBYPASS] Bits */
-#define LFXTBYPASS_OFS ( 9) /* LFXTBYPASS Offset */
-#define LFXTBYPASS (0x00000200) /* LFXT bypass select */
-/* CSCTL2[HFXTDRIVE] Bits */
-#define HFXTDRIVE_OFS (16) /* HFXTDRIVE Offset */
-#define HFXTDRIVE (0x00010000) /* HFXT oscillator drive selection */
-/* CSCTL2[HFXTFREQ] Bits */
-#define HFXTFREQ_OFS (20) /* HFXTFREQ Offset */
-#define HFXTFREQ_M (0x00700000) /* HFXT frequency selection */
-#define HFXTFREQ0 (0x00100000) /* HFXT frequency selection */
-#define HFXTFREQ1 (0x00200000) /* HFXT frequency selection */
-#define HFXTFREQ2 (0x00400000) /* HFXT frequency selection */
-#define HFXTFREQ_0 (0x00000000) /* 1 MHz to 4 MHz */
-#define HFXTFREQ_1 (0x00100000) /* >4 MHz to 8 MHz */
-#define HFXTFREQ_2 (0x00200000) /* >8 MHz to 16 MHz */
-#define HFXTFREQ_3 (0x00300000) /* >16 MHz to 24 MHz */
-#define HFXTFREQ_4 (0x00400000) /* >24 MHz to 32 MHz */
-#define HFXTFREQ_5 (0x00500000) /* >32 MHz to 40 MHz */
-#define HFXTFREQ_6 (0x00600000) /* >40 MHz to 48 MHz */
-/* CSCTL2[HFXT_EN] Bits */
-#define HFXT_EN_OFS (24) /* HFXT_EN Offset */
-#define HFXT_EN (0x01000000) /* Turns on the HFXT oscillator regardless if used as a clock resource */
-/* CSCTL2[HFXTBYPASS] Bits */
-#define HFXTBYPASS_OFS (25) /* HFXTBYPASS Offset */
-#define HFXTBYPASS (0x02000000) /* HFXT bypass select */
-/* CSCTL3[FCNTLF] Bits */
-#define FCNTLF_OFS ( 0) /* FCNTLF Offset */
-#define FCNTLF_M (0x00000003) /* Start flag counter for LFXT */
-#define FCNTLF0 (0x00000001) /* Start flag counter for LFXT */
-#define FCNTLF1 (0x00000002) /* Start flag counter for LFXT */
-#define FCNTLF_0 (0x00000000) /* 4096 cycles */
-#define FCNTLF_1 (0x00000001) /* 8192 cycles */
-#define FCNTLF_2 (0x00000002) /* 16384 cycles */
-#define FCNTLF_3 (0x00000003) /* 32768 cycles */
-#define FCNTLF__4096 (0x00000000) /* 4096 cycles */
-#define FCNTLF__8192 (0x00000001) /* 8192 cycles */
-#define FCNTLF__16384 (0x00000002) /* 16384 cycles */
-#define FCNTLF__32768 (0x00000003) /* 32768 cycles */
-/* CSCTL3[RFCNTLF] Bits */
-#define RFCNTLF_OFS ( 2) /* RFCNTLF Offset */
-#define RFCNTLF (0x00000004) /* Reset start fault counter for LFXT */
-/* CSCTL3[FCNTLF_EN] Bits */
-#define FCNTLF_EN_OFS ( 3) /* FCNTLF_EN Offset */
-#define FCNTLF_EN (0x00000008) /* Enable start fault counter for LFXT */
-/* CSCTL3[FCNTHF] Bits */
-#define FCNTHF_OFS ( 4) /* FCNTHF Offset */
-#define FCNTHF_M (0x00000030) /* Start flag counter for HFXT */
-#define FCNTHF0 (0x00000010) /* Start flag counter for HFXT */
-#define FCNTHF1 (0x00000020) /* Start flag counter for HFXT */
-#define FCNTHF_0 (0x00000000) /* 2048 cycles */
-#define FCNTHF_1 (0x00000010) /* 4096 cycles */
-#define FCNTHF_2 (0x00000020) /* 8192 cycles */
-#define FCNTHF_3 (0x00000030) /* 16384 cycles */
-#define FCNTHF__2048 (0x00000000) /* 2048 cycles */
-#define FCNTHF__4096 (0x00000010) /* 4096 cycles */
-#define FCNTHF__8192 (0x00000020) /* 8192 cycles */
-#define FCNTHF__16384 (0x00000030) /* 16384 cycles */
-/* CSCTL3[RFCNTHF] Bits */
-#define RFCNTHF_OFS ( 6) /* RFCNTHF Offset */
-#define RFCNTHF (0x00000040) /* Reset start fault counter for HFXT */
-/* CSCTL3[FCNTHF_EN] Bits */
-#define FCNTHF_EN_OFS ( 7) /* FCNTHF_EN Offset */
-#define FCNTHF_EN (0x00000080) /* Enable start fault counter for HFXT */
-/* CSCTL3[FCNTHF2] Bits */
-#define FCNTHF2_OFS ( 8) /* FCNTHF2 Offset */
-#define FCNTHF2_M (0x00000300) /* Start flag counter for HFXT2 */
-#define FCNTHF20 (0x00000100) /* Start flag counter for HFXT2 */
-#define FCNTHF21 (0x00000200) /* Start flag counter for HFXT2 */
-#define FCNTHF2_0 (0x00000000) /* 2048 cycles */
-#define FCNTHF2_1 (0x00000100) /* 4096 cycles */
-#define FCNTHF2_2 (0x00000200) /* 8192 cycles */
-#define FCNTHF2_3 (0x00000300) /* 16384 cycles */
-#define FCNTHF2__2048 (0x00000000) /* 2048 cycles */
-#define FCNTHF2__4096 (0x00000100) /* 4096 cycles */
-#define FCNTHF2__8192 (0x00000200) /* 8192 cycles */
-#define FCNTHF2__16384 (0x00000300) /* 16384 cycles */
-/* CSCTL3[RFCNTHF2] Bits */
-#define RFCNTHF2_OFS (10) /* RFCNTHF2 Offset */
-#define RFCNTHF2 (0x00000400) /* Reset start fault counter for HFXT2 */
-/* CSCTL3[FCNTHF2_EN] Bits */
-#define FCNTHF2_EN_OFS (11) /* FCNTHF2_EN Offset */
-#define FCNTHF2_EN (0x00000800) /* Enable start fault counter for HFXT2 */
-/* CSCTL4[HFXT2DRIVE] Bits */
-#define HFXT2DRIVE_OFS ( 0) /* HFXT2DRIVE Offset */
-#define HFXT2DRIVE_M (0x00000007) /* HFXT2 oscillator current can be adjusted to its drive needs */
-#define HFXT2DRIVE0 (0x00000001) /* HFXT2 oscillator current can be adjusted to its drive needs */
-#define HFXT2DRIVE1 (0x00000002) /* HFXT2 oscillator current can be adjusted to its drive needs */
-#define HFXT2DRIVE2 (0x00000004) /* HFXT2 oscillator current can be adjusted to its drive needs */
-#define HFXT2DRIVE_0 (0x00000000) /* Lowest current consumption */
-#define HFXT2DRIVE_1 (0x00000001) /* Increased drive strength HFXT2 oscillator */
-#define HFXT2DRIVE_2 (0x00000002) /* Increased drive strength HFXT2 oscillator */
-#define HFXT2DRIVE_3 (0x00000003) /* Increased drive strength HFXT2 oscillator */
-#define HFXT2DRIVE_4 (0x00000004) /* Increased drive strength HFXT2 oscillator */
-#define HFXT2DRIVE_5 (0x00000005) /* Increased drive strength HFXT2 oscillator */
-#define HFXT2DRIVE_6 (0x00000006) /* Increased drive strength HFXT2 oscillator */
-#define HFXT2DRIVE_7 (0x00000007) /* Maximum drive strength HFXT2 oscillator */
-/* CSCTL4[HFXT2FREQ] Bits */
-#define HFXT2FREQ_OFS ( 4) /* HFXT2FREQ Offset */
-#define HFXT2FREQ_M (0x00000070) /* HFXT2 frequency selection */
-/* CSCTL4[HFXT2_EN] Bits */
-#define HFXT2_EN_OFS ( 8) /* HFXT2_EN Offset */
-#define HFXT2_EN (0x00000100) /* Turns on the HFXT2 oscillator */
-/* CSCTL4[HFXT2BYPASS] Bits */
-#define HFXT2BYPASS_OFS ( 9) /* HFXT2BYPASS Offset */
-#define HFXT2BYPASS (0x00000200) /* HFXT2 bypass select */
-/* CSCTL5[REFCNTSEL] Bits */
-#define REFCNTSEL_OFS ( 0) /* REFCNTSEL Offset */
-#define REFCNTSEL_M (0x00000007) /* Reference counter source select */
-/* CSCTL5[REFCNTPS] Bits */
-#define REFCNTPS_OFS ( 3) /* REFCNTPS Offset */
-#define REFCNTPS_M (0x00000038) /* Reference clock prescaler */
-/* CSCTL5[CALSTART] Bits */
-#define CALSTART_OFS ( 7) /* CALSTART Offset */
-#define CALSTART (0x00000080) /* Start clock calibration counters */
-/* CSCTL5[PERCNTSEL] Bits */
-#define PERCNTSEL_OFS ( 8) /* PERCNTSEL Offset */
-#define PERCNTSEL_M (0x00000700) /* Period counter source select */
-/* CSCTL6[PERCNT] Bits */
-#define PERCNT_OFS ( 0) /* PERCNT Offset */
-#define PERCNT_M (0x0000ffff) /* Calibration period counter */
-/* CSCTL7[REFCNT] Bits */
-#define REFCNT_OFS ( 0) /* REFCNT Offset */
-#define REFCNT_M (0x0000ffff) /* Calibration reference period counter */
-/* CSCLKEN[ACLK_EN] Bits */
-#define ACLK_EN_OFS ( 0) /* ACLK_EN Offset */
-#define ACLK_EN (0x00000001) /* ACLK system clock conditional request enable */
-/* CSCLKEN[MCLK_EN] Bits */
-#define MCLK_EN_OFS ( 1) /* MCLK_EN Offset */
-#define MCLK_EN (0x00000002) /* MCLK system clock conditional request enable */
-/* CSCLKEN[HSMCLK_EN] Bits */
-#define HSMCLK_EN_OFS ( 2) /* HSMCLK_EN Offset */
-#define HSMCLK_EN (0x00000004) /* HSMCLK system clock conditional request enable */
-/* CSCLKEN[SMCLK_EN] Bits */
-#define SMCLK_EN_OFS ( 3) /* SMCLK_EN Offset */
-#define SMCLK_EN (0x00000008) /* SMCLK system clock conditional request enable */
-/* CSCLKEN[VLO_EN] Bits */
-#define VLO_EN_OFS ( 8) /* VLO_EN Offset */
-#define VLO_EN (0x00000100) /* Turns on the VLO oscillator */
-/* CSCLKEN[REFO_EN] Bits */
-#define REFO_EN_OFS ( 9) /* REFO_EN Offset */
-#define REFO_EN (0x00000200) /* Turns on the REFO oscillator */
-/* CSCLKEN[MODOSC_EN] Bits */
-#define MODOSC_EN_OFS (10) /* MODOSC_EN Offset */
-#define MODOSC_EN (0x00000400) /* Turns on the MODOSC oscillator */
-/* CSCLKEN[REFOFSEL] Bits */
-#define REFOFSEL_OFS (15) /* REFOFSEL Offset */
-#define REFOFSEL (0x00008000) /* Selects REFO nominal frequency */
-/* CSSTAT[DCO_ON] Bits */
-#define DCO_ON_OFS ( 0) /* DCO_ON Offset */
-#define DCO_ON (0x00000001) /* DCO status */
-/* CSSTAT[DCOBIAS_ON] Bits */
-#define DCOBIAS_ON_OFS ( 1) /* DCOBIAS_ON Offset */
-#define DCOBIAS_ON (0x00000002) /* DCO bias status */
-/* CSSTAT[HFXT_ON] Bits */
-#define HFXT_ON_OFS ( 2) /* HFXT_ON Offset */
-#define HFXT_ON (0x00000004) /* HFXT status */
-/* CSSTAT[HFXT2_ON] Bits */
-#define HFXT2_ON_OFS ( 3) /* HFXT2_ON Offset */
-#define HFXT2_ON (0x00000008) /* HFXT2 status */
-/* CSSTAT[MODOSC_ON] Bits */
-#define MODOSC_ON_OFS ( 4) /* MODOSC_ON Offset */
-#define MODOSC_ON (0x00000010) /* MODOSC status */
-/* CSSTAT[VLO_ON] Bits */
-#define VLO_ON_OFS ( 5) /* VLO_ON Offset */
-#define VLO_ON (0x00000020) /* VLO status */
-/* CSSTAT[LFXT_ON] Bits */
-#define LFXT_ON_OFS ( 6) /* LFXT_ON Offset */
-#define LFXT_ON (0x00000040) /* LFXT status */
-/* CSSTAT[REFO_ON] Bits */
-#define REFO_ON_OFS ( 7) /* REFO_ON Offset */
-#define REFO_ON (0x00000080) /* REFO status */
-/* CSSTAT[ACLK_ON] Bits */
-#define ACLK_ON_OFS (16) /* ACLK_ON Offset */
-#define ACLK_ON (0x00010000) /* ACLK system clock status */
-/* CSSTAT[MCLK_ON] Bits */
-#define MCLK_ON_OFS (17) /* MCLK_ON Offset */
-#define MCLK_ON (0x00020000) /* MCLK system clock status */
-/* CSSTAT[HSMCLK_ON] Bits */
-#define HSMCLK_ON_OFS (18) /* HSMCLK_ON Offset */
-#define HSMCLK_ON (0x00040000) /* HSMCLK system clock status */
-/* CSSTAT[SMCLK_ON] Bits */
-#define SMCLK_ON_OFS (19) /* SMCLK_ON Offset */
-#define SMCLK_ON (0x00080000) /* SMCLK system clock status */
-/* CSSTAT[MODCLK_ON] Bits */
-#define MODCLK_ON_OFS (20) /* MODCLK_ON Offset */
-#define MODCLK_ON (0x00100000) /* MODCLK system clock status */
-/* CSSTAT[VLOCLK_ON] Bits */
-#define VLOCLK_ON_OFS (21) /* VLOCLK_ON Offset */
-#define VLOCLK_ON (0x00200000) /* VLOCLK system clock status */
-/* CSSTAT[LFXTCLK_ON] Bits */
-#define LFXTCLK_ON_OFS (22) /* LFXTCLK_ON Offset */
-#define LFXTCLK_ON (0x00400000) /* LFXTCLK system clock status */
-/* CSSTAT[REFOCLK_ON] Bits */
-#define REFOCLK_ON_OFS (23) /* REFOCLK_ON Offset */
-#define REFOCLK_ON (0x00800000) /* REFOCLK system clock status */
-/* CSSTAT[ACLK_READY] Bits */
-#define ACLK_READY_OFS (24) /* ACLK_READY Offset */
-#define ACLK_READY (0x01000000) /* ACLK Ready status */
-/* CSSTAT[MCLK_READY] Bits */
-#define MCLK_READY_OFS (25) /* MCLK_READY Offset */
-#define MCLK_READY (0x02000000) /* MCLK Ready status */
-/* CSSTAT[HSMCLK_READY] Bits */
-#define HSMCLK_READY_OFS (26) /* HSMCLK_READY Offset */
-#define HSMCLK_READY (0x04000000) /* HSMCLK Ready status */
-/* CSSTAT[SMCLK_READY] Bits */
-#define SMCLK_READY_OFS (27) /* SMCLK_READY Offset */
-#define SMCLK_READY (0x08000000) /* SMCLK Ready status */
-/* CSSTAT[BCLK_READY] Bits */
-#define BCLK_READY_OFS (28) /* BCLK_READY Offset */
-#define BCLK_READY (0x10000000) /* BCLK Ready status */
-/* CSIE[LFXTIE] Bits */
-#define LFXTIE_OFS ( 0) /* LFXTIE Offset */
-#define LFXTIE (0x00000001) /* LFXT oscillator fault flag interrupt enable */
-/* CSIE[HFXTIE] Bits */
-#define HFXTIE_OFS ( 1) /* HFXTIE Offset */
-#define HFXTIE (0x00000002) /* HFXT oscillator fault flag interrupt enable */
-/* CSIE[HFXT2IE] Bits */
-#define HFXT2IE_OFS ( 2) /* HFXT2IE Offset */
-#define HFXT2IE (0x00000004) /* HFXT2 oscillator fault flag interrupt enable */
-/* CSIE[DCOMINIE] Bits */
-#define DCOMINIE_OFS ( 4) /* DCOMINIE Offset */
-#define DCOMINIE (0x00000010) /* DCO minimum fault flag interrupt enable */
-/* CSIE[DCOMAXIE] Bits */
-#define DCOMAXIE_OFS ( 5) /* DCOMAXIE Offset */
-#define DCOMAXIE (0x00000020) /* DCO maximum fault flag interrupt enable */
-/* CSIE[DCORIE] Bits */
-#define DCORIE_OFS ( 6) /* DCORIE Offset */
-#define DCORIE (0x00000040) /* DCO external resistor fault flag interrupt enable */
-/* CSIE[FCNTLFIE] Bits */
-#define FCNTLFIE_OFS ( 8) /* FCNTLFIE Offset */
-#define FCNTLFIE (0x00000100) /* Start fault counter interrupt enable LFXT */
-/* CSIE[FCNTHFIE] Bits */
-#define FCNTHFIE_OFS ( 9) /* FCNTHFIE Offset */
-#define FCNTHFIE (0x00000200) /* Start fault counter interrupt enable HFXT */
-/* CSIE[FCNTHF2IE] Bits */
-#define FCNTHF2IE_OFS (10) /* FCNTHF2IE Offset */
-#define FCNTHF2IE (0x00000400) /* Start fault counter interrupt enable HFXT2 */
-/* CSIE[PLLOOLIE] Bits */
-#define PLLOOLIE_OFS (12) /* PLLOOLIE Offset */
-#define PLLOOLIE (0x00001000) /* PLL out-of-lock interrupt enable */
-/* CSIE[PLLLOSIE] Bits */
-#define PLLLOSIE_OFS (13) /* PLLLOSIE Offset */
-#define PLLLOSIE (0x00002000) /* PLL loss-of-signal interrupt enable */
-/* CSIE[PLLOORIE] Bits */
-#define PLLOORIE_OFS (14) /* PLLOORIE Offset */
-#define PLLOORIE (0x00004000) /* PLL out-of-range interrupt enable */
-/* CSIE[CALIE] Bits */
-#define CALIE_OFS (15) /* CALIE Offset */
-#define CALIE (0x00008000) /* REFCNT period counter interrupt enable */
-/* CSIFG[LFXTIFG] Bits */
-#define LFXTIFG_OFS ( 0) /* LFXTIFG Offset */
-#define LFXTIFG (0x00000001) /* LFXT oscillator fault flag */
-/* CSIFG[HFXTIFG] Bits */
-#define HFXTIFG_OFS ( 1) /* HFXTIFG Offset */
-#define HFXTIFG (0x00000002) /* HFXT oscillator fault flag */
-/* CSIFG[HFXT2IFG] Bits */
-#define HFXT2IFG_OFS ( 2) /* HFXT2IFG Offset */
-#define HFXT2IFG (0x00000004) /* HFXT2 oscillator fault flag */
-/* CSIFG[DCOMINIFG] Bits */
-#define DCOMINIFG_OFS ( 4) /* DCOMINIFG Offset */
-#define DCOMINIFG (0x00000010) /* DCO minimum fault flag */
-/* CSIFG[DCOMAXIFG] Bits */
-#define DCOMAXIFG_OFS ( 5) /* DCOMAXIFG Offset */
-#define DCOMAXIFG (0x00000020) /* DCO maximum fault flag */
-/* CSIFG[DCORIFG] Bits */
-#define DCORIFG_OFS ( 6) /* DCORIFG Offset */
-#define DCORIFG (0x00000040) /* DCO external resistor fault flag */
-/* CSIFG[FCNTLFIFG] Bits */
-#define FCNTLFIFG_OFS ( 8) /* FCNTLFIFG Offset */
-#define FCNTLFIFG (0x00000100) /* Start fault counter interrupt flag LFXT */
-/* CSIFG[FCNTHFIFG] Bits */
-#define FCNTHFIFG_OFS ( 9) /* FCNTHFIFG Offset */
-#define FCNTHFIFG (0x00000200) /* Start fault counter interrupt flag HFXT */
-/* CSIFG[FCNTHF2IFG] Bits */
-#define FCNTHF2IFG_OFS (11) /* FCNTHF2IFG Offset */
-#define FCNTHF2IFG (0x00000800) /* Start fault counter interrupt flag HFXT2 */
-/* CSIFG[PLLOOLIFG] Bits */
-#define PLLOOLIFG_OFS (12) /* PLLOOLIFG Offset */
-#define PLLOOLIFG (0x00001000) /* PLL out-of-lock interrupt flag */
-/* CSIFG[PLLLOSIFG] Bits */
-#define PLLLOSIFG_OFS (13) /* PLLLOSIFG Offset */
-#define PLLLOSIFG (0x00002000) /* PLL loss-of-signal interrupt flag */
-/* CSIFG[PLLOORIFG] Bits */
-#define PLLOORIFG_OFS (14) /* PLLOORIFG Offset */
-#define PLLOORIFG (0x00004000) /* PLL out-of-range interrupt flag */
-/* CSIFG[CALIFG] Bits */
-#define CALIFG_OFS (15) /* CALIFG Offset */
-#define CALIFG (0x00008000) /* REFCNT period counter expired */
-/* CSCLRIFG[CLR_LFXTIFG] Bits */
-#define CLR_LFXTIFG_OFS ( 0) /* CLR_LFXTIFG Offset */
-#define CLR_LFXTIFG (0x00000001) /* Clear LFXT oscillator fault interrupt flag */
-/* CSCLRIFG[CLR_HFXTIFG] Bits */
-#define CLR_HFXTIFG_OFS ( 1) /* CLR_HFXTIFG Offset */
-#define CLR_HFXTIFG (0x00000002) /* Clear HFXT oscillator fault interrupt flag */
-/* CSCLRIFG[CLR_HFXT2IFG] Bits */
-#define CLR_HFXT2IFG_OFS ( 2) /* CLR_HFXT2IFG Offset */
-#define CLR_HFXT2IFG (0x00000004) /* Clear HFXT2 oscillator fault interrupt flag */
-/* CSCLRIFG[CLR_DCOMAXIFG] Bits */
-#define CLR_DCOMAXIFG_OFS ( 5) /* CLR_DCOMAXIFG Offset */
-#define CLR_DCOMAXIFG (0x00000020) /* Clear DCO maximum fault interrupt flag */
-/* CSCLRIFG[CLR_DCORIFG] Bits */
-#define CLR_DCORIFG_OFS ( 6) /* CLR_DCORIFG Offset */
-#define CLR_DCORIFG (0x00000040) /* Clear DCO external resistor fault interrupt flag */
-/* CSCLRIFG[CLR_CALIFG] Bits */
-#define CLR_CALIFG_OFS ( 7) /* CLR_CALIFG Offset */
-#define CLR_CALIFG (0x00000080) /* REFCNT period counter clear interrupt flag */
-/* CSCLRIFG[CLR_DCOMINIFG] Bits */
-#define CLR_DCOMINIFG_OFS ( 4) /* CLR_DCOMINIFG Offset */
-#define CLR_DCOMINIFG (0x00000010) /* Clear DCO minimum fault interrupt flag */
-/* CSCLRIFG[CLR_FCNTLFIFG] Bits */
-#define CLR_FCNTLFIFG_OFS ( 8) /* CLR_FCNTLFIFG Offset */
-#define CLR_FCNTLFIFG (0x00000100) /* Start fault counter clear interrupt flag LFXT */
-/* CSCLRIFG[CLR_FCNTHFIFG] Bits */
-#define CLR_FCNTHFIFG_OFS ( 9) /* CLR_FCNTHFIFG Offset */
-#define CLR_FCNTHFIFG (0x00000200) /* Start fault counter clear interrupt flag HFXT */
-/* CSCLRIFG[CLR_FCNTHF2IFG] Bits */
-#define CLR_FCNTHF2IFG_OFS (10) /* CLR_FCNTHF2IFG Offset */
-#define CLR_FCNTHF2IFG (0x00000400) /* Start fault counter clear interrupt flag HFXT2 */
-/* CSCLRIFG[CLR_PLLOOLIFG] Bits */
-#define CLR_PLLOOLIFG_OFS (12) /* CLR_PLLOOLIFG Offset */
-#define CLR_PLLOOLIFG (0x00001000) /* PLL out-of-lock clear interrupt flag */
-/* CSCLRIFG[CLR_PLLLOSIFG] Bits */
-#define CLR_PLLLOSIFG_OFS (13) /* CLR_PLLLOSIFG Offset */
-#define CLR_PLLLOSIFG (0x00002000) /* PLL loss-of-signal clear interrupt flag */
-/* CSCLRIFG[CLR_PLLOORIFG] Bits */
-#define CLR_PLLOORIFG_OFS (14) /* CLR_PLLOORIFG Offset */
-#define CLR_PLLOORIFG (0x00004000) /* PLL out-of-range clear interrupt flag */
-/* CSSETIFG[SET_LFXTIFG] Bits */
-#define SET_LFXTIFG_OFS ( 0) /* SET_LFXTIFG Offset */
-#define SET_LFXTIFG (0x00000001) /* Set LFXT oscillator fault interrupt flag */
-/* CSSETIFG[SET_HFXTIFG] Bits */
-#define SET_HFXTIFG_OFS ( 1) /* SET_HFXTIFG Offset */
-#define SET_HFXTIFG (0x00000002) /* Set HFXT oscillator fault interrupt flag */
-/* CSSETIFG[SET_HFXT2IFG] Bits */
-#define SET_HFXT2IFG_OFS ( 2) /* SET_HFXT2IFG Offset */
-#define SET_HFXT2IFG (0x00000004) /* Set HFXT2 oscillator fault interrupt flag */
-/* CSSETIFG[SET_DCOMINIFG] Bits */
-#define SET_DCOMINIFG_OFS ( 4) /* SET_DCOMINIFG Offset */
-#define SET_DCOMINIFG (0x00000010) /* Set DCO minimum fault interrupt flag */
-/* CSSETIFG[SET_DCOMAXIFG] Bits */
-#define SET_DCOMAXIFG_OFS ( 5) /* SET_DCOMAXIFG Offset */
-#define SET_DCOMAXIFG (0x00000020) /* Set DCO maximum fault interrupt flag */
-/* CSSETIFG[SET_DCORIFG] Bits */
-#define SET_DCORIFG_OFS ( 6) /* SET_DCORIFG Offset */
-#define SET_DCORIFG (0x00000040) /* Set DCO external resistor fault interrupt flag */
-/* CSSETIFG[SET_CALIFG] Bits */
-#define SET_CALIFG_OFS ( 7) /* SET_CALIFG Offset */
-#define SET_CALIFG (0x00000080) /* REFCNT period counter set interrupt flag */
-/* CSSETIFG[SET_FCNTHFIFG] Bits */
-#define SET_FCNTHFIFG_OFS ( 9) /* SET_FCNTHFIFG Offset */
-#define SET_FCNTHFIFG (0x00000200) /* Start fault counter set interrupt flag HFXT */
-/* CSSETIFG[SET_FCNTHF2IFG] Bits */
-#define SET_FCNTHF2IFG_OFS (10) /* SET_FCNTHF2IFG Offset */
-#define SET_FCNTHF2IFG (0x00000400) /* Start fault counter set interrupt flag HFXT2 */
-/* CSSETIFG[SET_FCNTLFIFG] Bits */
-#define SET_FCNTLFIFG_OFS ( 8) /* SET_FCNTLFIFG Offset */
-#define SET_FCNTLFIFG (0x00000100) /* Start fault counter set interrupt flag LFXT */
-/* CSSETIFG[SET_PLLOOLIFG] Bits */
-#define SET_PLLOOLIFG_OFS (12) /* SET_PLLOOLIFG Offset */
-#define SET_PLLOOLIFG (0x00001000) /* PLL out-of-lock set interrupt flag */
-/* CSSETIFG[SET_PLLLOSIFG] Bits */
-#define SET_PLLLOSIFG_OFS (13) /* SET_PLLLOSIFG Offset */
-#define SET_PLLLOSIFG (0x00002000) /* PLL loss-of-signal set interrupt flag */
-/* CSSETIFG[SET_PLLOORIFG] Bits */
-#define SET_PLLOORIFG_OFS (14) /* SET_PLLOORIFG Offset */
-#define SET_PLLOORIFG (0x00004000) /* PLL out-of-range set interrupt flag */
-/* CSDCOERCAL[DCO_TCTRIM] Bits */
-#define DCO_TCTRIM_OFS ( 0) /* DCO_TCTRIM Offset */
-#define DCO_TCTRIM_M (0x00000003) /* DCO Temperature compensation Trim */
-/* CSDCOERCAL[DCO_FTRIM] Bits */
-#define DCO_FTRIM_OFS (16) /* DCO_FTRIM Offset */
-#define DCO_FTRIM_M (0x07ff0000) /* DCO frequency trim */
+/******************************************************************************
+* CS Bits
+******************************************************************************/
+/* CS_KEY[KEY] Bits */
+#define CS_KEY_KEY_OFS ( 0) /**< CSKEY Bit Offset */
+#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /**< CSKEY Bit Mask */
+/* CS_CTL0[DCOTUNE] Bits */
+#define CS_CTL0_DCOTUNE_OFS ( 0) /**< DCOTUNE Bit Offset */
+#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /**< DCOTUNE Bit Mask */
+/* CS_CTL0[DCORSEL] Bits */
+#define CS_CTL0_DCORSEL_OFS (16) /**< DCORSEL Bit Offset */
+#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /**< DCORSEL Bit Mask */
+#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /**< DCORSEL Bit 0 */
+#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /**< DCORSEL Bit 1 */
+#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /**< DCORSEL Bit 2 */
+#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /**< Nominal DCO Frequency Range (MHz): 1 to 2 */
+#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /**< Nominal DCO Frequency Range (MHz): 2 to 4 */
+#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /**< Nominal DCO Frequency Range (MHz): 4 to 8 */
+#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /**< Nominal DCO Frequency Range (MHz): 8 to 16 */
+#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /**< Nominal DCO Frequency Range (MHz): 16 to 32 */
+#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /**< Nominal DCO Frequency Range (MHz): 32 to 64 */
+/* CS_CTL0[DCORES] Bits */
+#define CS_CTL0_DCORES_OFS (22) /**< DCORES Bit Offset */
+#define CS_CTL0_DCORES ((uint32_t)0x00400000) /**< Enables the DCO external resistor mode */
+/* CS_CTL0[DCOEN] Bits */
+#define CS_CTL0_DCOEN_OFS (23) /**< DCOEN Bit Offset */
+#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /**< Enables the DCO oscillator */
+/* CS_CTL1[SELM] Bits */
+#define CS_CTL1_SELM_OFS ( 0) /**< SELM Bit Offset */
+#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /**< SELM Bit Mask */
+#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /**< SELM Bit 0 */
+#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /**< SELM Bit 1 */
+#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /**< SELM Bit 2 */
+#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
+#define CS_CTL1_SELM_1 ((uint32_t)0x00000001)
+#define CS_CTL1_SELM_2 ((uint32_t)0x00000002)
+#define CS_CTL1_SELM_3 ((uint32_t)0x00000003)
+#define CS_CTL1_SELM_4 ((uint32_t)0x00000004)
+#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /**< when HFXT available, otherwise DCOCLK */
+#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /**< when HFXT2 available, otherwise DCOCLK */
+#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
+#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001)
+#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002)
+#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003)
+#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004)
+#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /**< when HFXT available, otherwise DCOCLK */
+#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /**< when HFXT2 available, otherwise DCOCLK */
+#define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /**< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */
+ /* compatibilities. */
+/* CS_CTL1[SELS] Bits */
+#define CS_CTL1_SELS_OFS ( 4) /**< SELS Bit Offset */
+#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /**< SELS Bit Mask */
+#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /**< SELS Bit 0 */
+#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /**< SELS Bit 1 */
+#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /**< SELS Bit 2 */
+#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
+#define CS_CTL1_SELS_1 ((uint32_t)0x00000010)
+#define CS_CTL1_SELS_2 ((uint32_t)0x00000020)
+#define CS_CTL1_SELS_3 ((uint32_t)0x00000030)
+#define CS_CTL1_SELS_4 ((uint32_t)0x00000040)
+#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /**< when HFXT available, otherwise DCOCLK */
+#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /**< when HFXT2 available, otherwise DCOCLK */
+#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
+#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010)
+#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020)
+#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030)
+#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040)
+#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /**< when HFXT available, otherwise DCOCLK */
+#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /**< when HFXT2 available, otherwise DCOCLK */
+#define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /**< for furture use. Defaults to DCOCLK. Do not use to ensure future */
+ /* compatibilities. */
+/* CS_CTL1[SELA] Bits */
+#define CS_CTL1_SELA_OFS ( 8) /**< SELA Bit Offset */
+#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /**< SELA Bit Mask */
+#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /**< SELA Bit 0 */
+#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /**< SELA Bit 1 */
+#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /**< SELA Bit 2 */
+#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
+#define CS_CTL1_SELA_1 ((uint32_t)0x00000100)
+#define CS_CTL1_SELA_2 ((uint32_t)0x00000200)
+#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /**< when LFXT available, otherwise REFOCLK */
+#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100)
+#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200)
+#define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
+ /* compatibilities. */
+#define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
+ /* compatibilities. */
+#define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
+ /* compatibilities. */
+#define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
+ /* compatibilities. */
+#define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /**< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */
+ /* compatibilities. */
+/* CS_CTL1[SELB] Bits */
+#define CS_CTL1_SELB_OFS (12) /**< SELB Bit Offset */
+#define CS_CTL1_SELB ((uint32_t)0x00001000) /**< Selects the BCLK source */
+/* CS_CTL1[DIVM] Bits */
+#define CS_CTL1_DIVM_OFS (16) /**< DIVM Bit Offset */
+#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /**< DIVM Bit Mask */
+#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /**< DIVM Bit 0 */
+#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /**< DIVM Bit 1 */
+#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /**< DIVM Bit 2 */
+#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /**< f(MCLK)/1 */
+#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /**< f(MCLK)/2 */
+#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /**< f(MCLK)/4 */
+#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /**< f(MCLK)/8 */
+#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /**< f(MCLK)/16 */
+#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /**< f(MCLK)/32 */
+#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /**< f(MCLK)/64 */
+#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /**< f(MCLK)/128 */
+#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /**< f(MCLK)/1 */
+#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /**< f(MCLK)/2 */
+#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /**< f(MCLK)/4 */
+#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /**< f(MCLK)/8 */
+#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /**< f(MCLK)/16 */
+#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /**< f(MCLK)/32 */
+#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /**< f(MCLK)/64 */
+#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /**< f(MCLK)/128 */
+/* CS_CTL1[DIVHS] Bits */
+#define CS_CTL1_DIVHS_OFS (20) /**< DIVHS Bit Offset */
+#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /**< DIVHS Bit Mask */
+#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /**< DIVHS Bit 0 */
+#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /**< DIVHS Bit 1 */
+#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /**< DIVHS Bit 2 */
+#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /**< f(HSMCLK)/1 */
+#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /**< f(HSMCLK)/2 */
+#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /**< f(HSMCLK)/4 */
+#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /**< f(HSMCLK)/8 */
+#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /**< f(HSMCLK)/16 */
+#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /**< f(HSMCLK)/32 */
+#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /**< f(HSMCLK)/64 */
+#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /**< f(HSMCLK)/128 */
+#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /**< f(HSMCLK)/1 */
+#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /**< f(HSMCLK)/2 */
+#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /**< f(HSMCLK)/4 */
+#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /**< f(HSMCLK)/8 */
+#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /**< f(HSMCLK)/16 */
+#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /**< f(HSMCLK)/32 */
+#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /**< f(HSMCLK)/64 */
+#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /**< f(HSMCLK)/128 */
+/* CS_CTL1[DIVA] Bits */
+#define CS_CTL1_DIVA_OFS (24) /**< DIVA Bit Offset */
+#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /**< DIVA Bit Mask */
+#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /**< DIVA Bit 0 */
+#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /**< DIVA Bit 1 */
+#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /**< DIVA Bit 2 */
+#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /**< f(ACLK)/1 */
+#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /**< f(ACLK)/2 */
+#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /**< f(ACLK)/4 */
+#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /**< f(ACLK)/8 */
+#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /**< f(ACLK)/16 */
+#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /**< f(ACLK)/32 */
+#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /**< f(ACLK)/64 */
+#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /**< f(ACLK)/128 */
+#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /**< f(ACLK)/1 */
+#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /**< f(ACLK)/2 */
+#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /**< f(ACLK)/4 */
+#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /**< f(ACLK)/8 */
+#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /**< f(ACLK)/16 */
+#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /**< f(ACLK)/32 */
+#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /**< f(ACLK)/64 */
+#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /**< f(ACLK)/128 */
+/* CS_CTL1[DIVS] Bits */
+#define CS_CTL1_DIVS_OFS (28) /**< DIVS Bit Offset */
+#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /**< DIVS Bit Mask */
+#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /**< DIVS Bit 0 */
+#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /**< DIVS Bit 1 */
+#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /**< DIVS Bit 2 */
+#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /**< f(SMCLK)/1 */
+#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /**< f(SMCLK)/2 */
+#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /**< f(SMCLK)/4 */
+#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /**< f(SMCLK)/8 */
+#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /**< f(SMCLK)/16 */
+#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /**< f(SMCLK)/32 */
+#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /**< f(SMCLK)/64 */
+#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /**< f(SMCLK)/128 */
+#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /**< f(SMCLK)/1 */
+#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /**< f(SMCLK)/2 */
+#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /**< f(SMCLK)/4 */
+#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /**< f(SMCLK)/8 */
+#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /**< f(SMCLK)/16 */
+#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /**< f(SMCLK)/32 */
+#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /**< f(SMCLK)/64 */
+#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /**< f(SMCLK)/128 */
+/* CS_CTL2[LFXTDRIVE] Bits */
+#define CS_CTL2_LFXTDRIVE_OFS ( 0) /**< LFXTDRIVE Bit Offset */
+#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /**< LFXTDRIVE Bit Mask */
+#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /**< LFXTDRIVE Bit 0 */
+#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /**< LFXTDRIVE Bit 1 */
+#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /**< Lowest drive strength and current consumption LFXT oscillator. */
+#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /**< Increased drive strength LFXT oscillator. */
+#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /**< Increased drive strength LFXT oscillator. */
+#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /**< Maximum drive strength and maximum current consumption LFXT oscillator. */
+/* CS_CTL2[LFXTAGCOFF] Bits */
+#define CS_CTL2_LFXTAGCOFF_OFS ( 7) /**< LFXTAGCOFF Bit Offset */
+#define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /**< Disables the automatic gain control of the LFXT crystal */
+/* CS_CTL2[LFXT_EN] Bits */
+#define CS_CTL2_LFXT_EN_OFS ( 8) /**< LFXT_EN Bit Offset */
+#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /**< Turns on the LFXT oscillator regardless if used as a clock resource */
+/* CS_CTL2[LFXTBYPASS] Bits */
+#define CS_CTL2_LFXTBYPASS_OFS ( 9) /**< LFXTBYPASS Bit Offset */
+#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /**< LFXT bypass select */
+/* CS_CTL2[HFXTDRIVE] Bits */
+#define CS_CTL2_HFXTDRIVE_OFS (16) /**< HFXTDRIVE Bit Offset */
+#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /**< HFXT oscillator drive selection */
+/* CS_CTL2[HFXTFREQ] Bits */
+#define CS_CTL2_HFXTFREQ_OFS (20) /**< HFXTFREQ Bit Offset */
+#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /**< HFXTFREQ Bit Mask */
+#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /**< HFXTFREQ Bit 0 */
+#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /**< HFXTFREQ Bit 1 */
+#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /**< HFXTFREQ Bit 2 */
+#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /**< 1 MHz to 4 MHz */
+#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /**< >4 MHz to 8 MHz */
+#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /**< >8 MHz to 16 MHz */
+#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /**< >16 MHz to 24 MHz */
+#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /**< >24 MHz to 32 MHz */
+#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /**< >32 MHz to 40 MHz */
+#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /**< >40 MHz to 48 MHz */
+#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /**< Reserved for future use. */
+/* CS_CTL2[HFXT_EN] Bits */
+#define CS_CTL2_HFXT_EN_OFS (24) /**< HFXT_EN Bit Offset */
+#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /**< Turns on the HFXT oscillator regardless if used as a clock resource */
+/* CS_CTL2[HFXTBYPASS] Bits */
+#define CS_CTL2_HFXTBYPASS_OFS (25) /**< HFXTBYPASS Bit Offset */
+#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /**< HFXT bypass select */
+/* CS_CTL3[FCNTLF] Bits */
+#define CS_CTL3_FCNTLF_OFS ( 0) /**< FCNTLF Bit Offset */
+#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /**< FCNTLF Bit Mask */
+#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /**< FCNTLF Bit 0 */
+#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /**< FCNTLF Bit 1 */
+#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /**< 4096 cycles */
+#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /**< 8192 cycles */
+#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /**< 16384 cycles */
+#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /**< 32768 cycles */
+#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /**< 4096 cycles */
+#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /**< 8192 cycles */
+#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /**< 16384 cycles */
+#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /**< 32768 cycles */
+/* CS_CTL3[RFCNTLF] Bits */
+#define CS_CTL3_RFCNTLF_OFS ( 2) /**< RFCNTLF Bit Offset */
+#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /**< Reset start fault counter for LFXT */
+/* CS_CTL3[FCNTLF_EN] Bits */
+#define CS_CTL3_FCNTLF_EN_OFS ( 3) /**< FCNTLF_EN Bit Offset */
+#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /**< Enable start fault counter for LFXT */
+/* CS_CTL3[FCNTHF] Bits */
+#define CS_CTL3_FCNTHF_OFS ( 4) /**< FCNTHF Bit Offset */
+#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /**< FCNTHF Bit Mask */
+#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /**< FCNTHF Bit 0 */
+#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /**< FCNTHF Bit 1 */
+#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /**< 2048 cycles */
+#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /**< 4096 cycles */
+#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /**< 8192 cycles */
+#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /**< 16384 cycles */
+#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /**< 2048 cycles */
+#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /**< 4096 cycles */
+#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /**< 8192 cycles */
+#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /**< 16384 cycles */
+/* CS_CTL3[RFCNTHF] Bits */
+#define CS_CTL3_RFCNTHF_OFS ( 6) /**< RFCNTHF Bit Offset */
+#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /**< Reset start fault counter for HFXT */
+/* CS_CTL3[FCNTHF_EN] Bits */
+#define CS_CTL3_FCNTHF_EN_OFS ( 7) /**< FCNTHF_EN Bit Offset */
+#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /**< Enable start fault counter for HFXT */
+/* CS_CTL3[FCNTHF2] Bits */
+#define CS_CTL3_FCNTHF2_OFS ( 8) /**< FCNTHF2 Bit Offset */
+#define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /**< FCNTHF2 Bit Mask */
+#define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /**< FCNTHF2 Bit 0 */
+#define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /**< FCNTHF2 Bit 1 */
+#define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /**< 2048 cycles */
+#define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /**< 4096 cycles */
+#define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /**< 8192 cycles */
+#define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /**< 16384 cycles */
+#define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /**< 2048 cycles */
+#define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /**< 4096 cycles */
+#define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /**< 8192 cycles */
+#define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /**< 16384 cycles */
+/* CS_CTL3[RFCNTHF2] Bits */
+#define CS_CTL3_RFCNTHF2_OFS (10) /**< RFCNTHF2 Bit Offset */
+#define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /**< Reset start fault counter for HFXT2 */
+/* CS_CTL3[FCNTHF2_EN] Bits */
+#define CS_CTL3_FCNTHF2_EN_OFS (11) /**< FCNTHF2_EN Bit Offset */
+#define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /**< Enable start fault counter for HFXT2 */
+/* CS_CTL4[HFXT2DRIVE] Bits */
+#define CS_CTL4_HFXT2DRIVE_OFS ( 0) /**< HFXT2DRIVE Bit Offset */
+#define CS_CTL4_HFXT2DRIVE ((uint32_t)0x00000001) /**< HFXT2 oscillator current can be adjusted to its drive needs */
+/* CS_CTL4[HFXT2FREQ] Bits */
+#define CS_CTL4_HFXT2FREQ_OFS ( 4) /**< HFXT2FREQ Bit Offset */
+#define CS_CTL4_HFXT2FREQ_MASK ((uint32_t)0x00000070) /**< HFXT2FREQ Bit Mask */
+#define CS_CTL4_HFXT2FREQ0 ((uint32_t)0x00000010) /**< HFXT2FREQ Bit 0 */
+#define CS_CTL4_HFXT2FREQ1 ((uint32_t)0x00000020) /**< HFXT2FREQ Bit 1 */
+#define CS_CTL4_HFXT2FREQ2 ((uint32_t)0x00000040) /**< HFXT2FREQ Bit 2 */
+#define CS_CTL4_HFXT2FREQ_0 ((uint32_t)0x00000000) /**< 1 MHz to 4 MHz */
+#define CS_CTL4_HFXT2FREQ_1 ((uint32_t)0x00000010) /**< >4 MHz to 8 MHz */
+#define CS_CTL4_HFXT2FREQ_2 ((uint32_t)0x00000020) /**< >8 MHz to 16 MHz */
+#define CS_CTL4_HFXT2FREQ_3 ((uint32_t)0x00000030) /**< >16 MHz to 24 MHz */
+#define CS_CTL4_HFXT2FREQ_4 ((uint32_t)0x00000040) /**< >24 MHz to 32 MHz */
+#define CS_CTL4_HFXT2FREQ_5 ((uint32_t)0x00000050) /**< >32 MHz to 40 MHz */
+#define CS_CTL4_HFXT2FREQ_6 ((uint32_t)0x00000060) /**< >40 MHz to 48 MHz */
+#define CS_CTL4_HFXT2FREQ_7 ((uint32_t)0x00000070) /**< Reserved for future use. */
+/* CS_CTL4[HFXT2_EN] Bits */
+#define CS_CTL4_HFXT2_EN_OFS ( 8) /**< HFXT2_EN Bit Offset */
+#define CS_CTL4_HFXT2_EN ((uint32_t)0x00000100) /**< Turns on the HFXT2 oscillator */
+/* CS_CTL4[HFXT2BYPASS] Bits */
+#define CS_CTL4_HFXT2BYPASS_OFS ( 9) /**< HFXT2BYPASS Bit Offset */
+#define CS_CTL4_HFXT2BYPASS ((uint32_t)0x00000200) /**< HFXT2 bypass select */
+/* CS_CTL5[REFCNTSEL] Bits */
+#define CS_CTL5_REFCNTSEL_OFS ( 0) /**< REFCNTSEL Bit Offset */
+#define CS_CTL5_REFCNTSEL_MASK ((uint32_t)0x00000007) /**< REFCNTSEL Bit Mask */
+/* CS_CTL5[REFCNTPS] Bits */
+#define CS_CTL5_REFCNTPS_OFS ( 3) /**< REFCNTPS Bit Offset */
+#define CS_CTL5_REFCNTPS_MASK ((uint32_t)0x00000038) /**< REFCNTPS Bit Mask */
+/* CS_CTL5[CALSTART] Bits */
+#define CS_CTL5_CALSTART_OFS ( 7) /**< CALSTART Bit Offset */
+#define CS_CTL5_CALSTART ((uint32_t)0x00000080) /**< Start clock calibration counters */
+/* CS_CTL5[PERCNTSEL] Bits */
+#define CS_CTL5_PERCNTSEL_OFS ( 8) /**< PERCNTSEL Bit Offset */
+#define CS_CTL5_PERCNTSEL_MASK ((uint32_t)0x00000700) /**< PERCNTSEL Bit Mask */
+/* CS_CTL6[PERCNT] Bits */
+#define CS_CTL6_PERCNT_OFS ( 0) /**< PERCNT Bit Offset */
+#define CS_CTL6_PERCNT_MASK ((uint32_t)0x0000FFFF) /**< PERCNT Bit Mask */
+/* CS_CTL7[REFCNT] Bits */
+#define CS_CTL7_REFCNT_OFS ( 0) /**< REFCNT Bit Offset */
+#define CS_CTL7_REFCNT_MASK ((uint32_t)0x0000FFFF) /**< REFCNT Bit Mask */
+/* CS_CLKEN[ACLK_EN] Bits */
+#define CS_CLKEN_ACLK_EN_OFS ( 0) /**< ACLK_EN Bit Offset */
+#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /**< ACLK system clock conditional request enable */
+/* CS_CLKEN[MCLK_EN] Bits */
+#define CS_CLKEN_MCLK_EN_OFS ( 1) /**< MCLK_EN Bit Offset */
+#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /**< MCLK system clock conditional request enable */
+/* CS_CLKEN[HSMCLK_EN] Bits */
+#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /**< HSMCLK_EN Bit Offset */
+#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /**< HSMCLK system clock conditional request enable */
+/* CS_CLKEN[SMCLK_EN] Bits */
+#define CS_CLKEN_SMCLK_EN_OFS ( 3) /**< SMCLK_EN Bit Offset */
+#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /**< SMCLK system clock conditional request enable */
+/* CS_CLKEN[VLO_EN] Bits */
+#define CS_CLKEN_VLO_EN_OFS ( 8) /**< VLO_EN Bit Offset */
+#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /**< Turns on the VLO oscillator */
+/* CS_CLKEN[REFO_EN] Bits */
+#define CS_CLKEN_REFO_EN_OFS ( 9) /**< REFO_EN Bit Offset */
+#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /**< Turns on the REFO oscillator */
+/* CS_CLKEN[MODOSC_EN] Bits */
+#define CS_CLKEN_MODOSC_EN_OFS (10) /**< MODOSC_EN Bit Offset */
+#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /**< Turns on the MODOSC oscillator */
+/* CS_CLKEN[REFOFSEL] Bits */
+#define CS_CLKEN_REFOFSEL_OFS (15) /**< REFOFSEL Bit Offset */
+#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /**< Selects REFO nominal frequency */
+/* CS_STAT[DCO_ON] Bits */
+#define CS_STAT_DCO_ON_OFS ( 0) /**< DCO_ON Bit Offset */
+#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /**< DCO status */
+/* CS_STAT[DCOBIAS_ON] Bits */
+#define CS_STAT_DCOBIAS_ON_OFS ( 1) /**< DCOBIAS_ON Bit Offset */
+#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /**< DCO bias status */
+/* CS_STAT[HFXT_ON] Bits */
+#define CS_STAT_HFXT_ON_OFS ( 2) /**< HFXT_ON Bit Offset */
+#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /**< HFXT status */
+/* CS_STAT[HFXT2_ON] Bits */
+#define CS_STAT_HFXT2_ON_OFS ( 3) /**< HFXT2_ON Bit Offset */
+#define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /**< HFXT2 status */
+/* CS_STAT[MODOSC_ON] Bits */
+#define CS_STAT_MODOSC_ON_OFS ( 4) /**< MODOSC_ON Bit Offset */
+#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /**< MODOSC status */
+/* CS_STAT[VLO_ON] Bits */
+#define CS_STAT_VLO_ON_OFS ( 5) /**< VLO_ON Bit Offset */
+#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /**< VLO status */
+/* CS_STAT[LFXT_ON] Bits */
+#define CS_STAT_LFXT_ON_OFS ( 6) /**< LFXT_ON Bit Offset */
+#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /**< LFXT status */
+/* CS_STAT[REFO_ON] Bits */
+#define CS_STAT_REFO_ON_OFS ( 7) /**< REFO_ON Bit Offset */
+#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /**< REFO status */
+/* CS_STAT[ACLK_ON] Bits */
+#define CS_STAT_ACLK_ON_OFS (16) /**< ACLK_ON Bit Offset */
+#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /**< ACLK system clock status */
+/* CS_STAT[MCLK_ON] Bits */
+#define CS_STAT_MCLK_ON_OFS (17) /**< MCLK_ON Bit Offset */
+#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /**< MCLK system clock status */
+/* CS_STAT[HSMCLK_ON] Bits */
+#define CS_STAT_HSMCLK_ON_OFS (18) /**< HSMCLK_ON Bit Offset */
+#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /**< HSMCLK system clock status */
+/* CS_STAT[SMCLK_ON] Bits */
+#define CS_STAT_SMCLK_ON_OFS (19) /**< SMCLK_ON Bit Offset */
+#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /**< SMCLK system clock status */
+/* CS_STAT[MODCLK_ON] Bits */
+#define CS_STAT_MODCLK_ON_OFS (20) /**< MODCLK_ON Bit Offset */
+#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /**< MODCLK system clock status */
+/* CS_STAT[VLOCLK_ON] Bits */
+#define CS_STAT_VLOCLK_ON_OFS (21) /**< VLOCLK_ON Bit Offset */
+#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /**< VLOCLK system clock status */
+/* CS_STAT[LFXTCLK_ON] Bits */
+#define CS_STAT_LFXTCLK_ON_OFS (22) /**< LFXTCLK_ON Bit Offset */
+#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /**< LFXTCLK system clock status */
+/* CS_STAT[REFOCLK_ON] Bits */
+#define CS_STAT_REFOCLK_ON_OFS (23) /**< REFOCLK_ON Bit Offset */
+#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /**< REFOCLK system clock status */
+/* CS_STAT[ACLK_READY] Bits */
+#define CS_STAT_ACLK_READY_OFS (24) /**< ACLK_READY Bit Offset */
+#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /**< ACLK Ready status */
+/* CS_STAT[MCLK_READY] Bits */
+#define CS_STAT_MCLK_READY_OFS (25) /**< MCLK_READY Bit Offset */
+#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /**< MCLK Ready status */
+/* CS_STAT[HSMCLK_READY] Bits */
+#define CS_STAT_HSMCLK_READY_OFS (26) /**< HSMCLK_READY Bit Offset */
+#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /**< HSMCLK Ready status */
+/* CS_STAT[SMCLK_READY] Bits */
+#define CS_STAT_SMCLK_READY_OFS (27) /**< SMCLK_READY Bit Offset */
+#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /**< SMCLK Ready status */
+/* CS_STAT[BCLK_READY] Bits */
+#define CS_STAT_BCLK_READY_OFS (28) /**< BCLK_READY Bit Offset */
+#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /**< BCLK Ready status */
+/* CS_IE[LFXTIE] Bits */
+#define CS_IE_LFXTIE_OFS ( 0) /**< LFXTIE Bit Offset */
+#define CS_IE_LFXTIE ((uint32_t)0x00000001) /**< LFXT oscillator fault flag interrupt enable */
+/* CS_IE[HFXTIE] Bits */
+#define CS_IE_HFXTIE_OFS ( 1) /**< HFXTIE Bit Offset */
+#define CS_IE_HFXTIE ((uint32_t)0x00000002) /**< HFXT oscillator fault flag interrupt enable */
+/* CS_IE[HFXT2IE] Bits */
+#define CS_IE_HFXT2IE_OFS ( 2) /**< HFXT2IE Bit Offset */
+#define CS_IE_HFXT2IE ((uint32_t)0x00000004) /**< HFXT2 oscillator fault flag interrupt enable */
+/* CS_IE[DCOR_OPNIE] Bits */
+#define CS_IE_DCOR_OPNIE_OFS ( 6) /**< DCOR_OPNIE Bit Offset */
+#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /**< DCO external resistor open circuit fault flag interrupt enable. */
+/* CS_IE[FCNTLFIE] Bits */
+#define CS_IE_FCNTLFIE_OFS ( 8) /**< FCNTLFIE Bit Offset */
+#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /**< Start fault counter interrupt enable LFXT */
+/* CS_IE[FCNTHFIE] Bits */
+#define CS_IE_FCNTHFIE_OFS ( 9) /**< FCNTHFIE Bit Offset */
+#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /**< Start fault counter interrupt enable HFXT */
+/* CS_IE[FCNTHF2IE] Bits */
+#define CS_IE_FCNTHF2IE_OFS (10) /**< FCNTHF2IE Bit Offset */
+#define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /**< Start fault counter interrupt enable HFXT2 */
+/* CS_IE[PLLOOLIE] Bits */
+#define CS_IE_PLLOOLIE_OFS (12) /**< PLLOOLIE Bit Offset */
+#define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /**< PLL out-of-lock interrupt enable */
+/* CS_IE[PLLLOSIE] Bits */
+#define CS_IE_PLLLOSIE_OFS (13) /**< PLLLOSIE Bit Offset */
+#define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /**< PLL loss-of-signal interrupt enable */
+/* CS_IE[PLLOORIE] Bits */
+#define CS_IE_PLLOORIE_OFS (14) /**< PLLOORIE Bit Offset */
+#define CS_IE_PLLOORIE ((uint32_t)0x00004000) /**< PLL out-of-range interrupt enable */
+/* CS_IE[CALIE] Bits */
+#define CS_IE_CALIE_OFS (15) /**< CALIE Bit Offset */
+#define CS_IE_CALIE ((uint32_t)0x00008000) /**< REFCNT period counter interrupt enable */
+/* CS_IFG[LFXTIFG] Bits */
+#define CS_IFG_LFXTIFG_OFS ( 0) /**< LFXTIFG Bit Offset */
+#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /**< LFXT oscillator fault flag */
+/* CS_IFG[HFXTIFG] Bits */
+#define CS_IFG_HFXTIFG_OFS ( 1) /**< HFXTIFG Bit Offset */
+#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /**< HFXT oscillator fault flag */
+/* CS_IFG[HFXT2IFG] Bits */
+#define CS_IFG_HFXT2IFG_OFS ( 2) /**< HFXT2IFG Bit Offset */
+#define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /**< HFXT2 oscillator fault flag */
+/* CS_IFG[DCOR_SHTIFG] Bits */
+#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /**< DCOR_SHTIFG Bit Offset */
+#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /**< DCO external resistor short circuit fault flag. */
+/* CS_IFG[DCOR_OPNIFG] Bits */
+#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /**< DCOR_OPNIFG Bit Offset */
+#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /**< DCO external resistor open circuit fault flag. */
+/* CS_IFG[FCNTLFIFG] Bits */
+#define CS_IFG_FCNTLFIFG_OFS ( 8) /**< FCNTLFIFG Bit Offset */
+#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter interrupt flag LFXT */
+/* CS_IFG[FCNTHFIFG] Bits */
+#define CS_IFG_FCNTHFIFG_OFS ( 9) /**< FCNTHFIFG Bit Offset */
+#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter interrupt flag HFXT */
+/* CS_IFG[FCNTHF2IFG] Bits */
+#define CS_IFG_FCNTHF2IFG_OFS (11) /**< FCNTHF2IFG Bit Offset */
+#define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /**< Start fault counter interrupt flag HFXT2 */
+/* CS_IFG[PLLOOLIFG] Bits */
+#define CS_IFG_PLLOOLIFG_OFS (12) /**< PLLOOLIFG Bit Offset */
+#define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock interrupt flag */
+/* CS_IFG[PLLLOSIFG] Bits */
+#define CS_IFG_PLLLOSIFG_OFS (13) /**< PLLLOSIFG Bit Offset */
+#define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal interrupt flag */
+/* CS_IFG[PLLOORIFG] Bits */
+#define CS_IFG_PLLOORIFG_OFS (14) /**< PLLOORIFG Bit Offset */
+#define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range interrupt flag */
+/* CS_IFG[CALIFG] Bits */
+#define CS_IFG_CALIFG_OFS (15) /**< CALIFG Bit Offset */
+#define CS_IFG_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter expired */
+/* CS_CLRIFG[CLR_LFXTIFG] Bits */
+#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /**< CLR_LFXTIFG Bit Offset */
+#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /**< Clear LFXT oscillator fault interrupt flag */
+/* CS_CLRIFG[CLR_HFXTIFG] Bits */
+#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /**< CLR_HFXTIFG Bit Offset */
+#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /**< Clear HFXT oscillator fault interrupt flag */
+/* CS_CLRIFG[CLR_HFXT2IFG] Bits */
+#define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /**< CLR_HFXT2IFG Bit Offset */
+#define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /**< Clear HFXT2 oscillator fault interrupt flag */
+/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */
+#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /**< CLR_DCOR_OPNIFG Bit Offset */
+#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /**< Clear DCO external resistor open circuit fault interrupt flag. */
+/* CS_CLRIFG[CLR_CALIFG] Bits */
+#define CS_CLRIFG_CLR_CALIFG_OFS (15) /**< CLR_CALIFG Bit Offset */
+#define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter clear interrupt flag */
+/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */
+#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /**< CLR_FCNTLFIFG Bit Offset */
+#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter clear interrupt flag LFXT */
+/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */
+#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /**< CLR_FCNTHFIFG Bit Offset */
+#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter clear interrupt flag HFXT */
+/* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */
+#define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /**< CLR_FCNTHF2IFG Bit Offset */
+#define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /**< Start fault counter clear interrupt flag HFXT2 */
+/* CS_CLRIFG[CLR_PLLOOLIFG] Bits */
+#define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /**< CLR_PLLOOLIFG Bit Offset */
+#define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock clear interrupt flag */
+/* CS_CLRIFG[CLR_PLLLOSIFG] Bits */
+#define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /**< CLR_PLLLOSIFG Bit Offset */
+#define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal clear interrupt flag */
+/* CS_CLRIFG[CLR_PLLOORIFG] Bits */
+#define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /**< CLR_PLLOORIFG Bit Offset */
+#define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range clear interrupt flag */
+/* CS_SETIFG[SET_LFXTIFG] Bits */
+#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /**< SET_LFXTIFG Bit Offset */
+#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /**< Set LFXT oscillator fault interrupt flag */
+/* CS_SETIFG[SET_HFXTIFG] Bits */
+#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /**< SET_HFXTIFG Bit Offset */
+#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /**< Set HFXT oscillator fault interrupt flag */
+/* CS_SETIFG[SET_HFXT2IFG] Bits */
+#define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /**< SET_HFXT2IFG Bit Offset */
+#define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /**< Set HFXT2 oscillator fault interrupt flag */
+/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */
+#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /**< SET_DCOR_OPNIFG Bit Offset */
+#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /**< Set DCO external resistor open circuit fault interrupt flag. */
+/* CS_SETIFG[SET_CALIFG] Bits */
+#define CS_SETIFG_SET_CALIFG_OFS (15) /**< SET_CALIFG Bit Offset */
+#define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /**< REFCNT period counter set interrupt flag */
+/* CS_SETIFG[SET_FCNTHFIFG] Bits */
+#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /**< SET_FCNTHFIFG Bit Offset */
+#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /**< Start fault counter set interrupt flag HFXT */
+/* CS_SETIFG[SET_FCNTHF2IFG] Bits */
+#define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /**< SET_FCNTHF2IFG Bit Offset */
+#define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /**< Start fault counter set interrupt flag HFXT2 */
+/* CS_SETIFG[SET_FCNTLFIFG] Bits */
+#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /**< SET_FCNTLFIFG Bit Offset */
+#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /**< Start fault counter set interrupt flag LFXT */
+/* CS_SETIFG[SET_PLLOOLIFG] Bits */
+#define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /**< SET_PLLOOLIFG Bit Offset */
+#define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /**< PLL out-of-lock set interrupt flag */
+/* CS_SETIFG[SET_PLLLOSIFG] Bits */
+#define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /**< SET_PLLLOSIFG Bit Offset */
+#define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /**< PLL loss-of-signal set interrupt flag */
+/* CS_SETIFG[SET_PLLOORIFG] Bits */
+#define CS_SETIFG_SET_PLLOORIFG_OFS (14) /**< SET_PLLOORIFG Bit Offset */
+#define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /**< PLL out-of-range set interrupt flag */
+/* CS_DCOERCAL0[DCO_TCCAL] Bits */
+#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /**< DCO_TCCAL Bit Offset */
+#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /**< DCO_TCCAL Bit Mask */
+/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */
+#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /**< DCO_FCAL_RSEL04 Bit Offset */
+#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /**< DCO_FCAL_RSEL04 Bit Mask */
+/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */
+#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /**< DCO_FCAL_RSEL5 Bit Offset */
+#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /**< DCO_FCAL_RSEL5 Bit Mask */
/* Pre-defined bitfield values */
-#define CSKEY_VAL (0x0000695A) /* CS control key value */
+#define CS_KEY_VAL ((uint32_t)0x0000695A) /* CS control key value */
+
+/******************************************************************************
+* DIO Bits
+******************************************************************************/
+/* DIO_IV[IV] Bits */
+#define DIO_PORT_IV_OFS ( 0) /**< DIO Port IV Bit Offset */
+#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /**< DIO Port IV Bit Mask */
+#define DIO_PORT_IV0 ((uint16_t)0x0001) /**< DIO Port IV Bit 0 */
+#define DIO_PORT_IV1 ((uint16_t)0x0002) /**< DIO Port IV Bit 1 */
+#define DIO_PORT_IV2 ((uint16_t)0x0004) /**< DIO Port IV Bit 2 */
+#define DIO_PORT_IV3 ((uint16_t)0x0008) /**< DIO Port IV Bit 3 */
+#define DIO_PORT_IV4 ((uint16_t)0x0010) /**< DIO Port IV Bit 4 */
+#define DIO_PORT_IV_0 ((uint16_t)0x0000) /**< No interrupt pending */
+#define DIO_PORT_IV_2 ((uint16_t)0x0002) /**< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */
+ /* Priority: Highest */
+#define DIO_PORT_IV_4 ((uint16_t)0x0004) /**< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
+#define DIO_PORT_IV_6 ((uint16_t)0x0006) /**< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
+#define DIO_PORT_IV_8 ((uint16_t)0x0008) /**< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
+#define DIO_PORT_IV_10 ((uint16_t)0x000A) /**< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
+#define DIO_PORT_IV_12 ((uint16_t)0x000C) /**< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
+#define DIO_PORT_IV_14 ((uint16_t)0x000E) /**< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
+#define DIO_PORT_IV_16 ((uint16_t)0x0010) /**< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */
+ /* Priority: Lowest */
+#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /**< No interrupt pending */
+#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /**< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */
+ /* Priority: Highest */
+#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /**< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
+#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /**< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
+#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /**< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
+#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /**< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
+#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /**< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
+#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /**< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
+#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /**< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */
+ /* Priority: Lowest */
-//*****************************************************************************
-// DIO Bits
-//*****************************************************************************
-/* PAIN[P1IN] Bits */
-#define P1IN_OFS ( 0) /* P1IN Offset */
-#define P1IN_M (0x00ff) /* Port 1 Input */
-/* PAIN[P2IN] Bits */
-#define P2IN_OFS ( 8) /* P2IN Offset */
-#define P2IN_M (0xff00) /* Port 2 Input */
-/* PAOUT[P2OUT] Bits */
-#define P2OUT_OFS ( 8) /* P2OUT Offset */
-#define P2OUT_M (0xff00) /* Port 2 Output */
-/* PAOUT[P1OUT] Bits */
-#define P1OUT_OFS ( 0) /* P1OUT Offset */
-#define P1OUT_M (0x00ff) /* Port 1 Output */
-/* PADIR[P1DIR] Bits */
-#define P1DIR_OFS ( 0) /* P1DIR Offset */
-#define P1DIR_M (0x00ff) /* Port 1 Direction */
-/* PADIR[P2DIR] Bits */
-#define P2DIR_OFS ( 8) /* P2DIR Offset */
-#define P2DIR_M (0xff00) /* Port 2 Direction */
-/* PAREN[P1REN] Bits */
-#define P1REN_OFS ( 0) /* P1REN Offset */
-#define P1REN_M (0x00ff) /* Port 1 Resistor Enable */
-/* PAREN[P2REN] Bits */
-#define P2REN_OFS ( 8) /* P2REN Offset */
-#define P2REN_M (0xff00) /* Port 2 Resistor Enable */
-/* PADS[P1DS] Bits */
-#define P1DS_OFS ( 0) /* P1DS Offset */
-#define P1DS_M (0x00ff) /* Port 1 Drive Strength */
-/* PADS[P2DS] Bits */
-#define P2DS_OFS ( 8) /* P2DS Offset */
-#define P2DS_M (0xff00) /* Port 2 Drive Strength */
-/* PASEL0[P1SEL0] Bits */
-#define P1SEL0_OFS ( 0) /* P1SEL0 Offset */
-#define P1SEL0_M (0x00ff) /* Port 1 Select 0 */
-/* PASEL0[P2SEL0] Bits */
-#define P2SEL0_OFS ( 8) /* P2SEL0 Offset */
-#define P2SEL0_M (0xff00) /* Port 2 Select 0 */
-/* PASEL1[P1SEL1] Bits */
-#define P1SEL1_OFS ( 0) /* P1SEL1 Offset */
-#define P1SEL1_M (0x00ff) /* Port 1 Select 1 */
-/* PASEL1[P2SEL1] Bits */
-#define P2SEL1_OFS ( 8) /* P2SEL1 Offset */
-#define P2SEL1_M (0xff00) /* Port 2 Select 1 */
-/* P1IV[P1IV] Bits */
-#define P1IV_OFS ( 0) /* P1IV Offset */
-#define P1IV_M (0x001f) /* Port 1 interrupt vector value */
-#define P1IV0 (0x0001) /* Port 1 interrupt vector value */
-#define P1IV1 (0x0002) /* Port 1 interrupt vector value */
-#define P1IV2 (0x0004) /* Port 1 interrupt vector value */
-#define P1IV3 (0x0008) /* Port 1 interrupt vector value */
-#define P1IV4 (0x0010) /* Port 1 interrupt vector value */
-#define P1IV_0 (0x0000) /* No interrupt pending */
-#define P1IV_2 (0x0002) /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
-#define P1IV_4 (0x0004) /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
-#define P1IV_6 (0x0006) /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
-#define P1IV_8 (0x0008) /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
-#define P1IV_10 (0x000a) /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
-#define P1IV_12 (0x000c) /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
-#define P1IV_14 (0x000e) /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
-#define P1IV_16 (0x0010) /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
-#define P1IV__NONE (0x0000) /* No interrupt pending */
-#define P1IV__P1IFG0 (0x0002) /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
-#define P1IV__P1IFG1 (0x0004) /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
-#define P1IV__P1IFG2 (0x0006) /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
-#define P1IV__P1IFG3 (0x0008) /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
-#define P1IV__P1IFG4 (0x000a) /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
-#define P1IV__P1IFG5 (0x000c) /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
-#define P1IV__P1IFG6 (0x000e) /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
-#define P1IV__P1IFG7 (0x0010) /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
-/* PASELC[P1SELC] Bits */
-#define P1SELC_OFS ( 0) /* P1SELC Offset */
-#define P1SELC_M (0x00ff) /* Port 1 Complement Select */
-/* PASELC[P2SELC] Bits */
-#define P2SELC_OFS ( 8) /* P2SELC Offset */
-#define P2SELC_M (0xff00) /* Port 2 Complement Select */
-/* PAIES[P1IES] Bits */
-#define P1IES_OFS ( 0) /* P1IES Offset */
-#define P1IES_M (0x00ff) /* Port 1 Interrupt Edge Select */
-/* PAIES[P2IES] Bits */
-#define P2IES_OFS ( 8) /* P2IES Offset */
-#define P2IES_M (0xff00) /* Port 2 Interrupt Edge Select */
-/* PAIE[P1IE] Bits */
-#define P1IE_OFS ( 0) /* P1IE Offset */
-#define P1IE_M (0x00ff) /* Port 1 Interrupt Enable */
-/* PAIE[P2IE] Bits */
-#define P2IE_OFS ( 8) /* P2IE Offset */
-#define P2IE_M (0xff00) /* Port 2 Interrupt Enable */
-/* PAIFG[P1IFG] Bits */
-#define P1IFG_OFS ( 0) /* P1IFG Offset */
-#define P1IFG_M (0x00ff) /* Port 1 Interrupt Flag */
-/* PAIFG[P2IFG] Bits */
-#define P2IFG_OFS ( 8) /* P2IFG Offset */
-#define P2IFG_M (0xff00) /* Port 2 Interrupt Flag */
-/* P2IV[P2IV] Bits */
-#define P2IV_OFS ( 0) /* P2IV Offset */
-#define P2IV_M (0x001f) /* Port 2 interrupt vector value */
-#define P2IV0 (0x0001) /* Port 2 interrupt vector value */
-#define P2IV1 (0x0002) /* Port 2 interrupt vector value */
-#define P2IV2 (0x0004) /* Port 2 interrupt vector value */
-#define P2IV3 (0x0008) /* Port 2 interrupt vector value */
-#define P2IV4 (0x0010) /* Port 2 interrupt vector value */
-#define P2IV_0 (0x0000) /* No interrupt pending */
-#define P2IV_2 (0x0002) /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
-#define P2IV_4 (0x0004) /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
-#define P2IV_6 (0x0006) /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
-#define P2IV_8 (0x0008) /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
-#define P2IV_10 (0x000a) /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
-#define P2IV_12 (0x000c) /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
-#define P2IV_14 (0x000e) /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
-#define P2IV_16 (0x0010) /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
-#define P2IV__NONE (0x0000) /* No interrupt pending */
-#define P2IV__P2IFG0 (0x0002) /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
-#define P2IV__P2IFG1 (0x0004) /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
-#define P2IV__P2IFG2 (0x0006) /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
-#define P2IV__P2IFG3 (0x0008) /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
-#define P2IV__P2IFG4 (0x000a) /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
-#define P2IV__P2IFG5 (0x000c) /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
-#define P2IV__P2IFG6 (0x000e) /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
-#define P2IV__P2IFG7 (0x0010) /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
-/* PBIN[P3IN] Bits */
-#define P3IN_OFS ( 0) /* P3IN Offset */
-#define P3IN_M (0x00ff) /* Port 3 Input */
-/* PBIN[P4IN] Bits */
-#define P4IN_OFS ( 8) /* P4IN Offset */
-#define P4IN_M (0xff00) /* Port 4 Input */
-/* PBOUT[P3OUT] Bits */
-#define P3OUT_OFS ( 0) /* P3OUT Offset */
-#define P3OUT_M (0x00ff) /* Port 3 Output */
-/* PBOUT[P4OUT] Bits */
-#define P4OUT_OFS ( 8) /* P4OUT Offset */
-#define P4OUT_M (0xff00) /* Port 4 Output */
-/* PBDIR[P3DIR] Bits */
-#define P3DIR_OFS ( 0) /* P3DIR Offset */
-#define P3DIR_M (0x00ff) /* Port 3 Direction */
-/* PBDIR[P4DIR] Bits */
-#define P4DIR_OFS ( 8) /* P4DIR Offset */
-#define P4DIR_M (0xff00) /* Port 4 Direction */
-/* PBREN[P3REN] Bits */
-#define P3REN_OFS ( 0) /* P3REN Offset */
-#define P3REN_M (0x00ff) /* Port 3 Resistor Enable */
-/* PBREN[P4REN] Bits */
-#define P4REN_OFS ( 8) /* P4REN Offset */
-#define P4REN_M (0xff00) /* Port 4 Resistor Enable */
-/* PBDS[P3DS] Bits */
-#define P3DS_OFS ( 0) /* P3DS Offset */
-#define P3DS_M (0x00ff) /* Port 3 Drive Strength */
-/* PBDS[P4DS] Bits */
-#define P4DS_OFS ( 8) /* P4DS Offset */
-#define P4DS_M (0xff00) /* Port 4 Drive Strength */
-/* PBSEL0[P4SEL0] Bits */
-#define P4SEL0_OFS ( 8) /* P4SEL0 Offset */
-#define P4SEL0_M (0xff00) /* Port 4 Select 0 */
-/* PBSEL0[P3SEL0] Bits */
-#define P3SEL0_OFS ( 0) /* P3SEL0 Offset */
-#define P3SEL0_M (0x00ff) /* Port 3 Select 0 */
-/* PBSEL1[P3SEL1] Bits */
-#define P3SEL1_OFS ( 0) /* P3SEL1 Offset */
-#define P3SEL1_M (0x00ff) /* Port 3 Select 1 */
-/* PBSEL1[P4SEL1] Bits */
-#define P4SEL1_OFS ( 8) /* P4SEL1 Offset */
-#define P4SEL1_M (0xff00) /* Port 4 Select 1 */
-/* P3IV[P3IV] Bits */
-#define P3IV_OFS ( 0) /* P3IV Offset */
-#define P3IV_M (0x001f) /* Port 3 interrupt vector value */
-#define P3IV0 (0x0001) /* Port 3 interrupt vector value */
-#define P3IV1 (0x0002) /* Port 3 interrupt vector value */
-#define P3IV2 (0x0004) /* Port 3 interrupt vector value */
-#define P3IV3 (0x0008) /* Port 3 interrupt vector value */
-#define P3IV4 (0x0010) /* Port 3 interrupt vector value */
-#define P3IV_0 (0x0000) /* No interrupt pending */
-#define P3IV_2 (0x0002) /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
-#define P3IV_4 (0x0004) /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
-#define P3IV_6 (0x0006) /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
-#define P3IV_8 (0x0008) /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
-#define P3IV_10 (0x000a) /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
-#define P3IV_12 (0x000c) /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
-#define P3IV_14 (0x000e) /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
-#define P3IV_16 (0x0010) /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
-#define P3IV__NONE (0x0000) /* No interrupt pending */
-#define P3IV__P3IFG0 (0x0002) /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
-#define P3IV__P3IFG1 (0x0004) /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
-#define P3IV__P3IFG2 (0x0006) /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
-#define P3IV__P3IFG3 (0x0008) /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
-#define P3IV__P3IFG4 (0x000a) /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
-#define P3IV__P3IFG5 (0x000c) /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
-#define P3IV__P3IFG6 (0x000e) /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
-#define P3IV__P3IFG7 (0x0010) /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
-/* PBSELC[P3SELC] Bits */
-#define P3SELC_OFS ( 0) /* P3SELC Offset */
-#define P3SELC_M (0x00ff) /* Port 3 Complement Select */
-/* PBSELC[P4SELC] Bits */
-#define P4SELC_OFS ( 8) /* P4SELC Offset */
-#define P4SELC_M (0xff00) /* Port 4 Complement Select */
-/* PBIES[P3IES] Bits */
-#define P3IES_OFS ( 0) /* P3IES Offset */
-#define P3IES_M (0x00ff) /* Port 3 Interrupt Edge Select */
-/* PBIES[P4IES] Bits */
-#define P4IES_OFS ( 8) /* P4IES Offset */
-#define P4IES_M (0xff00) /* Port 4 Interrupt Edge Select */
-/* PBIE[P3IE] Bits */
-#define P3IE_OFS ( 0) /* P3IE Offset */
-#define P3IE_M (0x00ff) /* Port 3 Interrupt Enable */
-/* PBIE[P4IE] Bits */
-#define P4IE_OFS ( 8) /* P4IE Offset */
-#define P4IE_M (0xff00) /* Port 4 Interrupt Enable */
-/* PBIFG[P3IFG] Bits */
-#define P3IFG_OFS ( 0) /* P3IFG Offset */
-#define P3IFG_M (0x00ff) /* Port 3 Interrupt Flag */
-/* PBIFG[P4IFG] Bits */
-#define P4IFG_OFS ( 8) /* P4IFG Offset */
-#define P4IFG_M (0xff00) /* Port 4 Interrupt Flag */
-/* P4IV[P4IV] Bits */
-#define P4IV_OFS ( 0) /* P4IV Offset */
-#define P4IV_M (0x001f) /* Port 4 interrupt vector value */
-#define P4IV0 (0x0001) /* Port 4 interrupt vector value */
-#define P4IV1 (0x0002) /* Port 4 interrupt vector value */
-#define P4IV2 (0x0004) /* Port 4 interrupt vector value */
-#define P4IV3 (0x0008) /* Port 4 interrupt vector value */
-#define P4IV4 (0x0010) /* Port 4 interrupt vector value */
-#define P4IV_0 (0x0000) /* No interrupt pending */
-#define P4IV_2 (0x0002) /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
-#define P4IV_4 (0x0004) /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
-#define P4IV_6 (0x0006) /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
-#define P4IV_8 (0x0008) /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
-#define P4IV_10 (0x000a) /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
-#define P4IV_12 (0x000c) /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
-#define P4IV_14 (0x000e) /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
-#define P4IV_16 (0x0010) /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
-#define P4IV__NONE (0x0000) /* No interrupt pending */
-#define P4IV__P4IFG0 (0x0002) /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
-#define P4IV__P4IFG1 (0x0004) /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
-#define P4IV__P4IFG2 (0x0006) /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
-#define P4IV__P4IFG3 (0x0008) /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
-#define P4IV__P4IFG4 (0x000a) /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
-#define P4IV__P4IFG5 (0x000c) /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
-#define P4IV__P4IFG6 (0x000e) /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
-#define P4IV__P4IFG7 (0x0010) /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
-/* PCIN[P5IN] Bits */
-#define P5IN_OFS ( 0) /* P5IN Offset */
-#define P5IN_M (0x00ff) /* Port 5 Input */
-/* PCIN[P6IN] Bits */
-#define P6IN_OFS ( 8) /* P6IN Offset */
-#define P6IN_M (0xff00) /* Port 6 Input */
-/* PCOUT[P5OUT] Bits */
-#define P5OUT_OFS ( 0) /* P5OUT Offset */
-#define P5OUT_M (0x00ff) /* Port 5 Output */
-/* PCOUT[P6OUT] Bits */
-#define P6OUT_OFS ( 8) /* P6OUT Offset */
-#define P6OUT_M (0xff00) /* Port 6 Output */
-/* PCDIR[P5DIR] Bits */
-#define P5DIR_OFS ( 0) /* P5DIR Offset */
-#define P5DIR_M (0x00ff) /* Port 5 Direction */
-/* PCDIR[P6DIR] Bits */
-#define P6DIR_OFS ( 8) /* P6DIR Offset */
-#define P6DIR_M (0xff00) /* Port 6 Direction */
-/* PCREN[P5REN] Bits */
-#define P5REN_OFS ( 0) /* P5REN Offset */
-#define P5REN_M (0x00ff) /* Port 5 Resistor Enable */
-/* PCREN[P6REN] Bits */
-#define P6REN_OFS ( 8) /* P6REN Offset */
-#define P6REN_M (0xff00) /* Port 6 Resistor Enable */
-/* PCDS[P5DS] Bits */
-#define P5DS_OFS ( 0) /* P5DS Offset */
-#define P5DS_M (0x00ff) /* Port 5 Drive Strength */
-/* PCDS[P6DS] Bits */
-#define P6DS_OFS ( 8) /* P6DS Offset */
-#define P6DS_M (0xff00) /* Port 6 Drive Strength */
-/* PCSEL0[P5SEL0] Bits */
-#define P5SEL0_OFS ( 0) /* P5SEL0 Offset */
-#define P5SEL0_M (0x00ff) /* Port 5 Select 0 */
-/* PCSEL0[P6SEL0] Bits */
-#define P6SEL0_OFS ( 8) /* P6SEL0 Offset */
-#define P6SEL0_M (0xff00) /* Port 6 Select 0 */
-/* PCSEL1[P5SEL1] Bits */
-#define P5SEL1_OFS ( 0) /* P5SEL1 Offset */
-#define P5SEL1_M (0x00ff) /* Port 5 Select 1 */
-/* PCSEL1[P6SEL1] Bits */
-#define P6SEL1_OFS ( 8) /* P6SEL1 Offset */
-#define P6SEL1_M (0xff00) /* Port 6 Select 1 */
-/* P5IV[P5IV] Bits */
-#define P5IV_OFS ( 0) /* P5IV Offset */
-#define P5IV_M (0x001f) /* Port 5 interrupt vector value */
-#define P5IV0 (0x0001) /* Port 5 interrupt vector value */
-#define P5IV1 (0x0002) /* Port 5 interrupt vector value */
-#define P5IV2 (0x0004) /* Port 5 interrupt vector value */
-#define P5IV3 (0x0008) /* Port 5 interrupt vector value */
-#define P5IV4 (0x0010) /* Port 5 interrupt vector value */
-#define P5IV_0 (0x0000) /* No interrupt pending */
-#define P5IV_2 (0x0002) /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
-#define P5IV_4 (0x0004) /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
-#define P5IV_6 (0x0006) /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
-#define P5IV_8 (0x0008) /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
-#define P5IV_10 (0x000a) /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
-#define P5IV_12 (0x000c) /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
-#define P5IV_14 (0x000e) /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
-#define P5IV_16 (0x0010) /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
-#define P5IV__NONE (0x0000) /* No interrupt pending */
-#define P5IV__P5IFG0 (0x0002) /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
-#define P5IV__P5IFG1 (0x0004) /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
-#define P5IV__P5IFG2 (0x0006) /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
-#define P5IV__P5IFG3 (0x0008) /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
-#define P5IV__P5IFG4 (0x000a) /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
-#define P5IV__P5IFG5 (0x000c) /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
-#define P5IV__P5IFG6 (0x000e) /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
-#define P5IV__P5IFG7 (0x0010) /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
-/* PCSELC[P5SELC] Bits */
-#define P5SELC_OFS ( 0) /* P5SELC Offset */
-#define P5SELC_M (0x00ff) /* Port 5 Complement Select */
-/* PCSELC[P6SELC] Bits */
-#define P6SELC_OFS ( 8) /* P6SELC Offset */
-#define P6SELC_M (0xff00) /* Port 6 Complement Select */
-/* PCIES[P5IES] Bits */
-#define P5IES_OFS ( 0) /* P5IES Offset */
-#define P5IES_M (0x00ff) /* Port 5 Interrupt Edge Select */
-/* PCIES[P6IES] Bits */
-#define P6IES_OFS ( 8) /* P6IES Offset */
-#define P6IES_M (0xff00) /* Port 6 Interrupt Edge Select */
-/* PCIE[P5IE] Bits */
-#define P5IE_OFS ( 0) /* P5IE Offset */
-#define P5IE_M (0x00ff) /* Port 5 Interrupt Enable */
-/* PCIE[P6IE] Bits */
-#define P6IE_OFS ( 8) /* P6IE Offset */
-#define P6IE_M (0xff00) /* Port 6 Interrupt Enable */
-/* PCIFG[P5IFG] Bits */
-#define P5IFG_OFS ( 0) /* P5IFG Offset */
-#define P5IFG_M (0x00ff) /* Port 5 Interrupt Flag */
-/* PCIFG[P6IFG] Bits */
-#define P6IFG_OFS ( 8) /* P6IFG Offset */
-#define P6IFG_M (0xff00) /* Port 6 Interrupt Flag */
-/* P6IV[P6IV] Bits */
-#define P6IV_OFS ( 0) /* P6IV Offset */
-#define P6IV_M (0x001f) /* Port 6 interrupt vector value */
-#define P6IV0 (0x0001) /* Port 6 interrupt vector value */
-#define P6IV1 (0x0002) /* Port 6 interrupt vector value */
-#define P6IV2 (0x0004) /* Port 6 interrupt vector value */
-#define P6IV3 (0x0008) /* Port 6 interrupt vector value */
-#define P6IV4 (0x0010) /* Port 6 interrupt vector value */
-#define P6IV_0 (0x0000) /* No interrupt pending */
-#define P6IV_2 (0x0002) /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
-#define P6IV_4 (0x0004) /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
-#define P6IV_6 (0x0006) /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
-#define P6IV_8 (0x0008) /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
-#define P6IV_10 (0x000a) /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
-#define P6IV_12 (0x000c) /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
-#define P6IV_14 (0x000e) /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
-#define P6IV_16 (0x0010) /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
-#define P6IV__NONE (0x0000) /* No interrupt pending */
-#define P6IV__P6IFG0 (0x0002) /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
-#define P6IV__P6IFG1 (0x0004) /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
-#define P6IV__P6IFG2 (0x0006) /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
-#define P6IV__P6IFG3 (0x0008) /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
-#define P6IV__P6IFG4 (0x000a) /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
-#define P6IV__P6IFG5 (0x000c) /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
-#define P6IV__P6IFG6 (0x000e) /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
-#define P6IV__P6IFG7 (0x0010) /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
-/* PDIN[P7IN] Bits */
-#define P7IN_OFS ( 0) /* P7IN Offset */
-#define P7IN_M (0x00ff) /* Port 7 Input */
-/* PDIN[P8IN] Bits */
-#define P8IN_OFS ( 8) /* P8IN Offset */
-#define P8IN_M (0xff00) /* Port 8 Input */
-/* PDOUT[P7OUT] Bits */
-#define P7OUT_OFS ( 0) /* P7OUT Offset */
-#define P7OUT_M (0x00ff) /* Port 7 Output */
-/* PDOUT[P8OUT] Bits */
-#define P8OUT_OFS ( 8) /* P8OUT Offset */
-#define P8OUT_M (0xff00) /* Port 8 Output */
-/* PDDIR[P7DIR] Bits */
-#define P7DIR_OFS ( 0) /* P7DIR Offset */
-#define P7DIR_M (0x00ff) /* Port 7 Direction */
-/* PDDIR[P8DIR] Bits */
-#define P8DIR_OFS ( 8) /* P8DIR Offset */
-#define P8DIR_M (0xff00) /* Port 8 Direction */
-/* PDREN[P7REN] Bits */
-#define P7REN_OFS ( 0) /* P7REN Offset */
-#define P7REN_M (0x00ff) /* Port 7 Resistor Enable */
-/* PDREN[P8REN] Bits */
-#define P8REN_OFS ( 8) /* P8REN Offset */
-#define P8REN_M (0xff00) /* Port 8 Resistor Enable */
-/* PDDS[P7DS] Bits */
-#define P7DS_OFS ( 0) /* P7DS Offset */
-#define P7DS_M (0x00ff) /* Port 7 Drive Strength */
-/* PDDS[P8DS] Bits */
-#define P8DS_OFS ( 8) /* P8DS Offset */
-#define P8DS_M (0xff00) /* Port 8 Drive Strength */
-/* PDSEL0[P7SEL0] Bits */
-#define P7SEL0_OFS ( 0) /* P7SEL0 Offset */
-#define P7SEL0_M (0x00ff) /* Port 7 Select 0 */
-/* PDSEL0[P8SEL0] Bits */
-#define P8SEL0_OFS ( 8) /* P8SEL0 Offset */
-#define P8SEL0_M (0xff00) /* Port 8 Select 0 */
-/* PDSEL1[P7SEL1] Bits */
-#define P7SEL1_OFS ( 0) /* P7SEL1 Offset */
-#define P7SEL1_M (0x00ff) /* Port 7 Select 1 */
-/* PDSEL1[P8SEL1] Bits */
-#define P8SEL1_OFS ( 8) /* P8SEL1 Offset */
-#define P8SEL1_M (0xff00) /* Port 8 Select 1 */
-/* P7IV[P7IV] Bits */
-#define P7IV_OFS ( 0) /* P7IV Offset */
-#define P7IV_M (0x001f) /* Port 7 interrupt vector value */
-#define P7IV0 (0x0001) /* Port 7 interrupt vector value */
-#define P7IV1 (0x0002) /* Port 7 interrupt vector value */
-#define P7IV2 (0x0004) /* Port 7 interrupt vector value */
-#define P7IV3 (0x0008) /* Port 7 interrupt vector value */
-#define P7IV4 (0x0010) /* Port 7 interrupt vector value */
-#define P7IV_0 (0x0000) /* No interrupt pending */
-#define P7IV_2 (0x0002) /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
-#define P7IV_4 (0x0004) /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
-#define P7IV_6 (0x0006) /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
-#define P7IV_8 (0x0008) /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
-#define P7IV_10 (0x000a) /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
-#define P7IV_12 (0x000c) /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
-#define P7IV_14 (0x000e) /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
-#define P7IV_16 (0x0010) /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
-#define P7IV__NONE (0x0000) /* No interrupt pending */
-#define P7IV__P7IFG0 (0x0002) /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
-#define P7IV__P7IFG1 (0x0004) /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
-#define P7IV__P7IFG2 (0x0006) /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
-#define P7IV__P7IFG3 (0x0008) /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
-#define P7IV__P7IFG4 (0x000a) /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
-#define P7IV__P7IFG5 (0x000c) /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
-#define P7IV__P7IFG6 (0x000e) /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
-#define P7IV__P7IFG7 (0x0010) /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
-/* PDSELC[P7SELC] Bits */
-#define P7SELC_OFS ( 0) /* P7SELC Offset */
-#define P7SELC_M (0x00ff) /* Port 7 Complement Select */
-/* PDSELC[P8SELC] Bits */
-#define P8SELC_OFS ( 8) /* P8SELC Offset */
-#define P8SELC_M (0xff00) /* Port 8 Complement Select */
-/* PDIES[P7IES] Bits */
-#define P7IES_OFS ( 0) /* P7IES Offset */
-#define P7IES_M (0x00ff) /* Port 7 Interrupt Edge Select */
-/* PDIES[P8IES] Bits */
-#define P8IES_OFS ( 8) /* P8IES Offset */
-#define P8IES_M (0xff00) /* Port 8 Interrupt Edge Select */
-/* PDIE[P7IE] Bits */
-#define P7IE_OFS ( 0) /* P7IE Offset */
-#define P7IE_M (0x00ff) /* Port 7 Interrupt Enable */
-/* PDIE[P8IE] Bits */
-#define P8IE_OFS ( 8) /* P8IE Offset */
-#define P8IE_M (0xff00) /* Port 8 Interrupt Enable */
-/* PDIFG[P7IFG] Bits */
-#define P7IFG_OFS ( 0) /* P7IFG Offset */
-#define P7IFG_M (0x00ff) /* Port 7 Interrupt Flag */
-/* PDIFG[P8IFG] Bits */
-#define P8IFG_OFS ( 8) /* P8IFG Offset */
-#define P8IFG_M (0xff00) /* Port 8 Interrupt Flag */
-/* P8IV[P8IV] Bits */
-#define P8IV_OFS ( 0) /* P8IV Offset */
-#define P8IV_M (0x001f) /* Port 8 interrupt vector value */
-#define P8IV0 (0x0001) /* Port 8 interrupt vector value */
-#define P8IV1 (0x0002) /* Port 8 interrupt vector value */
-#define P8IV2 (0x0004) /* Port 8 interrupt vector value */
-#define P8IV3 (0x0008) /* Port 8 interrupt vector value */
-#define P8IV4 (0x0010) /* Port 8 interrupt vector value */
-#define P8IV_0 (0x0000) /* No interrupt pending */
-#define P8IV_2 (0x0002) /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
-#define P8IV_4 (0x0004) /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
-#define P8IV_6 (0x0006) /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
-#define P8IV_8 (0x0008) /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
-#define P8IV_10 (0x000a) /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
-#define P8IV_12 (0x000c) /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
-#define P8IV_14 (0x000e) /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
-#define P8IV_16 (0x0010) /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
-#define P8IV__NONE (0x0000) /* No interrupt pending */
-#define P8IV__P8IFG0 (0x0002) /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
-#define P8IV__P8IFG1 (0x0004) /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
-#define P8IV__P8IFG2 (0x0006) /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
-#define P8IV__P8IFG3 (0x0008) /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
-#define P8IV__P8IFG4 (0x000a) /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
-#define P8IV__P8IFG5 (0x000c) /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
-#define P8IV__P8IFG6 (0x000e) /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
-#define P8IV__P8IFG7 (0x0010) /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
-/* PEIN[P9IN] Bits */
-#define P9IN_OFS ( 0) /* P9IN Offset */
-#define P9IN_M (0x00ff) /* Port 9 Input */
-/* PEIN[P10IN] Bits */
-#define P10IN_OFS ( 8) /* P10IN Offset */
-#define P10IN_M (0xff00) /* Port 10 Input */
-/* PEOUT[P9OUT] Bits */
-#define P9OUT_OFS ( 0) /* P9OUT Offset */
-#define P9OUT_M (0x00ff) /* Port 9 Output */
-/* PEOUT[P10OUT] Bits */
-#define P10OUT_OFS ( 8) /* P10OUT Offset */
-#define P10OUT_M (0xff00) /* Port 10 Output */
-/* PEDIR[P9DIR] Bits */
-#define P9DIR_OFS ( 0) /* P9DIR Offset */
-#define P9DIR_M (0x00ff) /* Port 9 Direction */
-/* PEDIR[P10DIR] Bits */
-#define P10DIR_OFS ( 8) /* P10DIR Offset */
-#define P10DIR_M (0xff00) /* Port 10 Direction */
-/* PEREN[P9REN] Bits */
-#define P9REN_OFS ( 0) /* P9REN Offset */
-#define P9REN_M (0x00ff) /* Port 9 Resistor Enable */
-/* PEREN[P10REN] Bits */
-#define P10REN_OFS ( 8) /* P10REN Offset */
-#define P10REN_M (0xff00) /* Port 10 Resistor Enable */
-/* PEDS[P9DS] Bits */
-#define P9DS_OFS ( 0) /* P9DS Offset */
-#define P9DS_M (0x00ff) /* Port 9 Drive Strength */
-/* PEDS[P10DS] Bits */
-#define P10DS_OFS ( 8) /* P10DS Offset */
-#define P10DS_M (0xff00) /* Port 10 Drive Strength */
-/* PESEL0[P9SEL0] Bits */
-#define P9SEL0_OFS ( 0) /* P9SEL0 Offset */
-#define P9SEL0_M (0x00ff) /* Port 9 Select 0 */
-/* PESEL0[P10SEL0] Bits */
-#define P10SEL0_OFS ( 8) /* P10SEL0 Offset */
-#define P10SEL0_M (0xff00) /* Port 10 Select 0 */
-/* PESEL1[P9SEL1] Bits */
-#define P9SEL1_OFS ( 0) /* P9SEL1 Offset */
-#define P9SEL1_M (0x00ff) /* Port 9 Select 1 */
-/* PESEL1[P10SEL1] Bits */
-#define P10SEL1_OFS ( 8) /* P10SEL1 Offset */
-#define P10SEL1_M (0xff00) /* Port 10 Select 1 */
-/* P9IV[P9IV] Bits */
-#define P9IV_OFS ( 0) /* P9IV Offset */
-#define P9IV_M (0x001f) /* Port 9 interrupt vector value */
-#define P9IV0 (0x0001) /* Port 9 interrupt vector value */
-#define P9IV1 (0x0002) /* Port 9 interrupt vector value */
-#define P9IV2 (0x0004) /* Port 9 interrupt vector value */
-#define P9IV3 (0x0008) /* Port 9 interrupt vector value */
-#define P9IV4 (0x0010) /* Port 9 interrupt vector value */
-#define P9IV_0 (0x0000) /* No interrupt pending */
-#define P9IV_2 (0x0002) /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
-#define P9IV_4 (0x0004) /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
-#define P9IV_6 (0x0006) /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
-#define P9IV_8 (0x0008) /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
-#define P9IV_10 (0x000a) /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
-#define P9IV_12 (0x000c) /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
-#define P9IV_14 (0x000e) /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
-#define P9IV_16 (0x0010) /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
-#define P9IV__NONE (0x0000) /* No interrupt pending */
-#define P9IV__P9IFG0 (0x0002) /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
-#define P9IV__P9IFG1 (0x0004) /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
-#define P9IV__P9IFG2 (0x0006) /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
-#define P9IV__P9IFG3 (0x0008) /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
-#define P9IV__P9IFG4 (0x000a) /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
-#define P9IV__P9IFG5 (0x000c) /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
-#define P9IV__P9IFG6 (0x000e) /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
-#define P9IV__P9IFG7 (0x0010) /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
-/* PESELC[P9SELC] Bits */
-#define P9SELC_OFS ( 0) /* P9SELC Offset */
-#define P9SELC_M (0x00ff) /* Port 9 Complement Select */
-/* PESELC[P10SELC] Bits */
-#define P10SELC_OFS ( 8) /* P10SELC Offset */
-#define P10SELC_M (0xff00) /* Port 10 Complement Select */
-/* PEIES[P9IES] Bits */
-#define P9IES_OFS ( 0) /* P9IES Offset */
-#define P9IES_M (0x00ff) /* Port 9 Interrupt Edge Select */
-/* PEIES[P10IES] Bits */
-#define P10IES_OFS ( 8) /* P10IES Offset */
-#define P10IES_M (0xff00) /* Port 10 Interrupt Edge Select */
-/* PEIE[P9IE] Bits */
-#define P9IE_OFS ( 0) /* P9IE Offset */
-#define P9IE_M (0x00ff) /* Port 9 Interrupt Enable */
-/* PEIE[P10IE] Bits */
-#define P10IE_OFS ( 8) /* P10IE Offset */
-#define P10IE_M (0xff00) /* Port 10 Interrupt Enable */
-/* PEIFG[P9IFG] Bits */
-#define P9IFG_OFS ( 0) /* P9IFG Offset */
-#define P9IFG_M (0x00ff) /* Port 9 Interrupt Flag */
-/* PEIFG[P10IFG] Bits */
-#define P10IFG_OFS ( 8) /* P10IFG Offset */
-#define P10IFG_M (0xff00) /* Port 10 Interrupt Flag */
-/* P10IV[P10IV] Bits */
-#define P10IV_OFS ( 0) /* P10IV Offset */
-#define P10IV_M (0x001f) /* Port 10 interrupt vector value */
-#define P10IV0 (0x0001) /* Port 10 interrupt vector value */
-#define P10IV1 (0x0002) /* Port 10 interrupt vector value */
-#define P10IV2 (0x0004) /* Port 10 interrupt vector value */
-#define P10IV3 (0x0008) /* Port 10 interrupt vector value */
-#define P10IV4 (0x0010) /* Port 10 interrupt vector value */
-#define P10IV_0 (0x0000) /* No interrupt pending */
-#define P10IV_2 (0x0002) /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
-#define P10IV_4 (0x0004) /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
-#define P10IV_6 (0x0006) /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
-#define P10IV_8 (0x0008) /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
-#define P10IV_10 (0x000a) /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
-#define P10IV_12 (0x000c) /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
-#define P10IV_14 (0x000e) /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
-#define P10IV_16 (0x0010) /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
-#define P10IV__NONE (0x0000) /* No interrupt pending */
-#define P10IV__P10IFG0 (0x0002) /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
-#define P10IV__P10IFG1 (0x0004) /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
-#define P10IV__P10IFG2 (0x0006) /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
-#define P10IV__P10IFG3 (0x0008) /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
-#define P10IV__P10IFG4 (0x000a) /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
-#define P10IV__P10IFG5 (0x000c) /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
-#define P10IV__P10IFG6 (0x000e) /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
-#define P10IV__P10IFG7 (0x0010) /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
-
-
-//*****************************************************************************
-// DMA Bits
-//*****************************************************************************
-/* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_DMA_CHANNELS] Bits */
-#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /* NUM_DMA_CHANNELS Offset */
-#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_M (0x000000ff) /* Number of DMA channels available */
-/* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL] Bits */
-#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /* NUM_SRC_PER_CHANNEL Offset */
-#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_M (0x0000ff00) /* Number of DMA sources per channel */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH0] Bits */
-#define DMA_SW_CHTRIG_CH0_OFS ( 0) /* CH0 Offset */
-#define DMA_SW_CHTRIG_CH0 (0x00000001) /* Write 1, triggers DMA_CHANNEL0 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH1] Bits */
-#define DMA_SW_CHTRIG_CH1_OFS ( 1) /* CH1 Offset */
-#define DMA_SW_CHTRIG_CH1 (0x00000002) /* Write 1, triggers DMA_CHANNEL1 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH2] Bits */
-#define DMA_SW_CHTRIG_CH2_OFS ( 2) /* CH2 Offset */
-#define DMA_SW_CHTRIG_CH2 (0x00000004) /* Write 1, triggers DMA_CHANNEL2 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH3] Bits */
-#define DMA_SW_CHTRIG_CH3_OFS ( 3) /* CH3 Offset */
-#define DMA_SW_CHTRIG_CH3 (0x00000008) /* Write 1, triggers DMA_CHANNEL3 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH4] Bits */
-#define DMA_SW_CHTRIG_CH4_OFS ( 4) /* CH4 Offset */
-#define DMA_SW_CHTRIG_CH4 (0x00000010) /* Write 1, triggers DMA_CHANNEL4 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH5] Bits */
-#define DMA_SW_CHTRIG_CH5_OFS ( 5) /* CH5 Offset */
-#define DMA_SW_CHTRIG_CH5 (0x00000020) /* Write 1, triggers DMA_CHANNEL5 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH6] Bits */
-#define DMA_SW_CHTRIG_CH6_OFS ( 6) /* CH6 Offset */
-#define DMA_SW_CHTRIG_CH6 (0x00000040) /* Write 1, triggers DMA_CHANNEL6 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH7] Bits */
-#define DMA_SW_CHTRIG_CH7_OFS ( 7) /* CH7 Offset */
-#define DMA_SW_CHTRIG_CH7 (0x00000080) /* Write 1, triggers DMA_CHANNEL7 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH8] Bits */
-#define DMA_SW_CHTRIG_CH8_OFS ( 8) /* CH8 Offset */
-#define DMA_SW_CHTRIG_CH8 (0x00000100) /* Write 1, triggers DMA_CHANNEL8 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH9] Bits */
-#define DMA_SW_CHTRIG_CH9_OFS ( 9) /* CH9 Offset */
-#define DMA_SW_CHTRIG_CH9 (0x00000200) /* Write 1, triggers DMA_CHANNEL9 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH10] Bits */
-#define DMA_SW_CHTRIG_CH10_OFS (10) /* CH10 Offset */
-#define DMA_SW_CHTRIG_CH10 (0x00000400) /* Write 1, triggers DMA_CHANNEL10 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH11] Bits */
-#define DMA_SW_CHTRIG_CH11_OFS (11) /* CH11 Offset */
-#define DMA_SW_CHTRIG_CH11 (0x00000800) /* Write 1, triggers DMA_CHANNEL11 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH12] Bits */
-#define DMA_SW_CHTRIG_CH12_OFS (12) /* CH12 Offset */
-#define DMA_SW_CHTRIG_CH12 (0x00001000) /* Write 1, triggers DMA_CHANNEL12 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH13] Bits */
-#define DMA_SW_CHTRIG_CH13_OFS (13) /* CH13 Offset */
-#define DMA_SW_CHTRIG_CH13 (0x00002000) /* Write 1, triggers DMA_CHANNEL13 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH14] Bits */
-#define DMA_SW_CHTRIG_CH14_OFS (14) /* CH14 Offset */
-#define DMA_SW_CHTRIG_CH14 (0x00004000) /* Write 1, triggers DMA_CHANNEL14 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH15] Bits */
-#define DMA_SW_CHTRIG_CH15_OFS (15) /* CH15 Offset */
-#define DMA_SW_CHTRIG_CH15 (0x00008000) /* Write 1, triggers DMA_CHANNEL15 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH16] Bits */
-#define DMA_SW_CHTRIG_CH16_OFS (16) /* CH16 Offset */
-#define DMA_SW_CHTRIG_CH16 (0x00010000) /* Write 1, triggers DMA_CHANNEL16 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH17] Bits */
-#define DMA_SW_CHTRIG_CH17_OFS (17) /* CH17 Offset */
-#define DMA_SW_CHTRIG_CH17 (0x00020000) /* Write 1, triggers DMA_CHANNEL17 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH18] Bits */
-#define DMA_SW_CHTRIG_CH18_OFS (18) /* CH18 Offset */
-#define DMA_SW_CHTRIG_CH18 (0x00040000) /* Write 1, triggers DMA_CHANNEL18 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH19] Bits */
-#define DMA_SW_CHTRIG_CH19_OFS (19) /* CH19 Offset */
-#define DMA_SW_CHTRIG_CH19 (0x00080000) /* Write 1, triggers DMA_CHANNEL19 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH20] Bits */
-#define DMA_SW_CHTRIG_CH20_OFS (20) /* CH20 Offset */
-#define DMA_SW_CHTRIG_CH20 (0x00100000) /* Write 1, triggers DMA_CHANNEL20 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH21] Bits */
-#define DMA_SW_CHTRIG_CH21_OFS (21) /* CH21 Offset */
-#define DMA_SW_CHTRIG_CH21 (0x00200000) /* Write 1, triggers DMA_CHANNEL21 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH22] Bits */
-#define DMA_SW_CHTRIG_CH22_OFS (22) /* CH22 Offset */
-#define DMA_SW_CHTRIG_CH22 (0x00400000) /* Write 1, triggers DMA_CHANNEL22 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH23] Bits */
-#define DMA_SW_CHTRIG_CH23_OFS (23) /* CH23 Offset */
-#define DMA_SW_CHTRIG_CH23 (0x00800000) /* Write 1, triggers DMA_CHANNEL23 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH24] Bits */
-#define DMA_SW_CHTRIG_CH24_OFS (24) /* CH24 Offset */
-#define DMA_SW_CHTRIG_CH24 (0x01000000) /* Write 1, triggers DMA_CHANNEL24 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH25] Bits */
-#define DMA_SW_CHTRIG_CH25_OFS (25) /* CH25 Offset */
-#define DMA_SW_CHTRIG_CH25 (0x02000000) /* Write 1, triggers DMA_CHANNEL25 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH26] Bits */
-#define DMA_SW_CHTRIG_CH26_OFS (26) /* CH26 Offset */
-#define DMA_SW_CHTRIG_CH26 (0x04000000) /* Write 1, triggers DMA_CHANNEL26 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH27] Bits */
-#define DMA_SW_CHTRIG_CH27_OFS (27) /* CH27 Offset */
-#define DMA_SW_CHTRIG_CH27 (0x08000000) /* Write 1, triggers DMA_CHANNEL27 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH28] Bits */
-#define DMA_SW_CHTRIG_CH28_OFS (28) /* CH28 Offset */
-#define DMA_SW_CHTRIG_CH28 (0x10000000) /* Write 1, triggers DMA_CHANNEL28 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH29] Bits */
-#define DMA_SW_CHTRIG_CH29_OFS (29) /* CH29 Offset */
-#define DMA_SW_CHTRIG_CH29 (0x20000000) /* Write 1, triggers DMA_CHANNEL29 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH30] Bits */
-#define DMA_SW_CHTRIG_CH30_OFS (30) /* CH30 Offset */
-#define DMA_SW_CHTRIG_CH30 (0x40000000) /* Write 1, triggers DMA_CHANNEL30 */
-/* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH31] Bits */
-#define DMA_SW_CHTRIG_CH31_OFS (31) /* CH31 Offset */
-#define DMA_SW_CHTRIG_CH31 (0x80000000) /* Write 1, triggers DMA_CHANNEL31 */
-/* DMA_CH_SRCCFG[DMA_CHN_SRCCFG_DMA_SRC] Bits */
-#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /* DMA_SRC Offset */
-#define DMA_CHN_SRCCFG_DMA_SRC_M (0x000000ff) /* Device level DMA source mapping to channel input */
-/* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_INT_SRC] Bits */
-#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */
-#define DMA_INT1_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */
-/* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_EN] Bits */
-#define DMA_INT1_SRCCFG_EN_OFS ( 5) /* EN Offset */
-#define DMA_INT1_SRCCFG_EN (0x00000020) /* Enables DMA_INT1 mapping */
-/* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_INT_SRC] Bits */
-#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */
-#define DMA_INT2_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */
-/* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_EN] Bits */
-#define DMA_INT2_SRCCFG_EN_OFS ( 5) /* EN Offset */
-#define DMA_INT2_SRCCFG_EN (0x00000020) /* Enables DMA_INT2 mapping */
-/* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_INT_SRC] Bits */
-#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */
-#define DMA_INT3_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */
-/* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_EN] Bits */
-#define DMA_INT3_SRCCFG_EN_OFS ( 5) /* EN Offset */
-#define DMA_INT3_SRCCFG_EN (0x00000020) /* Enables DMA_INT3 mapping */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH0] Bits */
-#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /* CH0 Offset */
-#define DMA_INT0_SRCFLG_CH0 (0x00000001) /* Channel 0 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH1] Bits */
-#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /* CH1 Offset */
-#define DMA_INT0_SRCFLG_CH1 (0x00000002) /* Channel 1 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH2] Bits */
-#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /* CH2 Offset */
-#define DMA_INT0_SRCFLG_CH2 (0x00000004) /* Channel 2 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH3] Bits */
-#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /* CH3 Offset */
-#define DMA_INT0_SRCFLG_CH3 (0x00000008) /* Channel 3 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH4] Bits */
-#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /* CH4 Offset */
-#define DMA_INT0_SRCFLG_CH4 (0x00000010) /* Channel 4 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH5] Bits */
-#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /* CH5 Offset */
-#define DMA_INT0_SRCFLG_CH5 (0x00000020) /* Channel 5 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH6] Bits */
-#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /* CH6 Offset */
-#define DMA_INT0_SRCFLG_CH6 (0x00000040) /* Channel 6 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH7] Bits */
-#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /* CH7 Offset */
-#define DMA_INT0_SRCFLG_CH7 (0x00000080) /* Channel 7 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH8] Bits */
-#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /* CH8 Offset */
-#define DMA_INT0_SRCFLG_CH8 (0x00000100) /* Channel 8 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH9] Bits */
-#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /* CH9 Offset */
-#define DMA_INT0_SRCFLG_CH9 (0x00000200) /* Channel 9 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH10] Bits */
-#define DMA_INT0_SRCFLG_CH10_OFS (10) /* CH10 Offset */
-#define DMA_INT0_SRCFLG_CH10 (0x00000400) /* Channel 10 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH11] Bits */
-#define DMA_INT0_SRCFLG_CH11_OFS (11) /* CH11 Offset */
-#define DMA_INT0_SRCFLG_CH11 (0x00000800) /* Channel 11 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH12] Bits */
-#define DMA_INT0_SRCFLG_CH12_OFS (12) /* CH12 Offset */
-#define DMA_INT0_SRCFLG_CH12 (0x00001000) /* Channel 12 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH13] Bits */
-#define DMA_INT0_SRCFLG_CH13_OFS (13) /* CH13 Offset */
-#define DMA_INT0_SRCFLG_CH13 (0x00002000) /* Channel 13 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH14] Bits */
-#define DMA_INT0_SRCFLG_CH14_OFS (14) /* CH14 Offset */
-#define DMA_INT0_SRCFLG_CH14 (0x00004000) /* Channel 14 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH15] Bits */
-#define DMA_INT0_SRCFLG_CH15_OFS (15) /* CH15 Offset */
-#define DMA_INT0_SRCFLG_CH15 (0x00008000) /* Channel 15 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH16] Bits */
-#define DMA_INT0_SRCFLG_CH16_OFS (16) /* CH16 Offset */
-#define DMA_INT0_SRCFLG_CH16 (0x00010000) /* Channel 16 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH17] Bits */
-#define DMA_INT0_SRCFLG_CH17_OFS (17) /* CH17 Offset */
-#define DMA_INT0_SRCFLG_CH17 (0x00020000) /* Channel 17 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH18] Bits */
-#define DMA_INT0_SRCFLG_CH18_OFS (18) /* CH18 Offset */
-#define DMA_INT0_SRCFLG_CH18 (0x00040000) /* Channel 18 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH19] Bits */
-#define DMA_INT0_SRCFLG_CH19_OFS (19) /* CH19 Offset */
-#define DMA_INT0_SRCFLG_CH19 (0x00080000) /* Channel 19 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH20] Bits */
-#define DMA_INT0_SRCFLG_CH20_OFS (20) /* CH20 Offset */
-#define DMA_INT0_SRCFLG_CH20 (0x00100000) /* Channel 20 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH21] Bits */
-#define DMA_INT0_SRCFLG_CH21_OFS (21) /* CH21 Offset */
-#define DMA_INT0_SRCFLG_CH21 (0x00200000) /* Channel 21 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH22] Bits */
-#define DMA_INT0_SRCFLG_CH22_OFS (22) /* CH22 Offset */
-#define DMA_INT0_SRCFLG_CH22 (0x00400000) /* Channel 22 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH23] Bits */
-#define DMA_INT0_SRCFLG_CH23_OFS (23) /* CH23 Offset */
-#define DMA_INT0_SRCFLG_CH23 (0x00800000) /* Channel 23 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH24] Bits */
-#define DMA_INT0_SRCFLG_CH24_OFS (24) /* CH24 Offset */
-#define DMA_INT0_SRCFLG_CH24 (0x01000000) /* Channel 24 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH25] Bits */
-#define DMA_INT0_SRCFLG_CH25_OFS (25) /* CH25 Offset */
-#define DMA_INT0_SRCFLG_CH25 (0x02000000) /* Channel 25 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH26] Bits */
-#define DMA_INT0_SRCFLG_CH26_OFS (26) /* CH26 Offset */
-#define DMA_INT0_SRCFLG_CH26 (0x04000000) /* Channel 26 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH27] Bits */
-#define DMA_INT0_SRCFLG_CH27_OFS (27) /* CH27 Offset */
-#define DMA_INT0_SRCFLG_CH27 (0x08000000) /* Channel 27 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH28] Bits */
-#define DMA_INT0_SRCFLG_CH28_OFS (28) /* CH28 Offset */
-#define DMA_INT0_SRCFLG_CH28 (0x10000000) /* Channel 28 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH29] Bits */
-#define DMA_INT0_SRCFLG_CH29_OFS (29) /* CH29 Offset */
-#define DMA_INT0_SRCFLG_CH29 (0x20000000) /* Channel 29 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH30] Bits */
-#define DMA_INT0_SRCFLG_CH30_OFS (30) /* CH30 Offset */
-#define DMA_INT0_SRCFLG_CH30 (0x40000000) /* Channel 30 was the source of DMA_INT0 */
-/* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH31] Bits */
-#define DMA_INT0_SRCFLG_CH31_OFS (31) /* CH31 Offset */
-#define DMA_INT0_SRCFLG_CH31 (0x80000000) /* Channel 31 was the source of DMA_INT0 */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH0] Bits */
-#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /* CH0 Offset */
-#define DMA_INT0_CLRFLG_CH0 (0x00000001) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH1] Bits */
-#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /* CH1 Offset */
-#define DMA_INT0_CLRFLG_CH1 (0x00000002) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH2] Bits */
-#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /* CH2 Offset */
-#define DMA_INT0_CLRFLG_CH2 (0x00000004) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH3] Bits */
-#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /* CH3 Offset */
-#define DMA_INT0_CLRFLG_CH3 (0x00000008) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH4] Bits */
-#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /* CH4 Offset */
-#define DMA_INT0_CLRFLG_CH4 (0x00000010) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH5] Bits */
-#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /* CH5 Offset */
-#define DMA_INT0_CLRFLG_CH5 (0x00000020) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH6] Bits */
-#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /* CH6 Offset */
-#define DMA_INT0_CLRFLG_CH6 (0x00000040) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH7] Bits */
-#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /* CH7 Offset */
-#define DMA_INT0_CLRFLG_CH7 (0x00000080) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH8] Bits */
-#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /* CH8 Offset */
-#define DMA_INT0_CLRFLG_CH8 (0x00000100) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH9] Bits */
-#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /* CH9 Offset */
-#define DMA_INT0_CLRFLG_CH9 (0x00000200) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH10] Bits */
-#define DMA_INT0_CLRFLG_CH10_OFS (10) /* CH10 Offset */
-#define DMA_INT0_CLRFLG_CH10 (0x00000400) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH11] Bits */
-#define DMA_INT0_CLRFLG_CH11_OFS (11) /* CH11 Offset */
-#define DMA_INT0_CLRFLG_CH11 (0x00000800) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH12] Bits */
-#define DMA_INT0_CLRFLG_CH12_OFS (12) /* CH12 Offset */
-#define DMA_INT0_CLRFLG_CH12 (0x00001000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH13] Bits */
-#define DMA_INT0_CLRFLG_CH13_OFS (13) /* CH13 Offset */
-#define DMA_INT0_CLRFLG_CH13 (0x00002000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH14] Bits */
-#define DMA_INT0_CLRFLG_CH14_OFS (14) /* CH14 Offset */
-#define DMA_INT0_CLRFLG_CH14 (0x00004000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH15] Bits */
-#define DMA_INT0_CLRFLG_CH15_OFS (15) /* CH15 Offset */
-#define DMA_INT0_CLRFLG_CH15 (0x00008000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH16] Bits */
-#define DMA_INT0_CLRFLG_CH16_OFS (16) /* CH16 Offset */
-#define DMA_INT0_CLRFLG_CH16 (0x00010000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH17] Bits */
-#define DMA_INT0_CLRFLG_CH17_OFS (17) /* CH17 Offset */
-#define DMA_INT0_CLRFLG_CH17 (0x00020000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH18] Bits */
-#define DMA_INT0_CLRFLG_CH18_OFS (18) /* CH18 Offset */
-#define DMA_INT0_CLRFLG_CH18 (0x00040000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH19] Bits */
-#define DMA_INT0_CLRFLG_CH19_OFS (19) /* CH19 Offset */
-#define DMA_INT0_CLRFLG_CH19 (0x00080000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH20] Bits */
-#define DMA_INT0_CLRFLG_CH20_OFS (20) /* CH20 Offset */
-#define DMA_INT0_CLRFLG_CH20 (0x00100000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH21] Bits */
-#define DMA_INT0_CLRFLG_CH21_OFS (21) /* CH21 Offset */
-#define DMA_INT0_CLRFLG_CH21 (0x00200000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH22] Bits */
-#define DMA_INT0_CLRFLG_CH22_OFS (22) /* CH22 Offset */
-#define DMA_INT0_CLRFLG_CH22 (0x00400000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH23] Bits */
-#define DMA_INT0_CLRFLG_CH23_OFS (23) /* CH23 Offset */
-#define DMA_INT0_CLRFLG_CH23 (0x00800000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH24] Bits */
-#define DMA_INT0_CLRFLG_CH24_OFS (24) /* CH24 Offset */
-#define DMA_INT0_CLRFLG_CH24 (0x01000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH25] Bits */
-#define DMA_INT0_CLRFLG_CH25_OFS (25) /* CH25 Offset */
-#define DMA_INT0_CLRFLG_CH25 (0x02000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH26] Bits */
-#define DMA_INT0_CLRFLG_CH26_OFS (26) /* CH26 Offset */
-#define DMA_INT0_CLRFLG_CH26 (0x04000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH27] Bits */
-#define DMA_INT0_CLRFLG_CH27_OFS (27) /* CH27 Offset */
-#define DMA_INT0_CLRFLG_CH27 (0x08000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH28] Bits */
-#define DMA_INT0_CLRFLG_CH28_OFS (28) /* CH28 Offset */
-#define DMA_INT0_CLRFLG_CH28 (0x10000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH29] Bits */
-#define DMA_INT0_CLRFLG_CH29_OFS (29) /* CH29 Offset */
-#define DMA_INT0_CLRFLG_CH29 (0x20000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH30] Bits */
-#define DMA_INT0_CLRFLG_CH30_OFS (30) /* CH30 Offset */
-#define DMA_INT0_CLRFLG_CH30 (0x40000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH31] Bits */
-#define DMA_INT0_CLRFLG_CH31_OFS (31) /* CH31 Offset */
-#define DMA_INT0_CLRFLG_CH31 (0x80000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
-/* DMA_STAT[DMA_STAT_MASTEN] Bits */
-#define DMA_STAT_MASTEN_OFS ( 0) /* MASTEN Offset */
-#define DMA_STAT_MASTEN (0x00000001) /* */
-/* DMA_STAT[DMA_STAT_] Bits */
-#define DMA_STAT__OFS ( 4) /* STATE Offset */
-#define DMA_STAT__M (0x000000f0) /* */
-#define DMA_STAT_0 (0x00000010) /* */
-#define DMA_STAT_1 (0x00000020) /* */
-#define DMA_STAT_2 (0x00000040) /* */
-#define DMA_STAT_3 (0x00000080) /* */
-#define DMA_STAT__0 (0x00000000) /* idle */
-#define DMA_STAT__1 (0x00000010) /* reading channel controller data */
-#define DMA_STAT__2 (0x00000020) /* reading source data end pointer */
-#define DMA_STAT__3 (0x00000030) /* reading destination data end pointer */
-#define DMA_STAT__4 (0x00000040) /* reading source data */
-#define DMA_STAT__5 (0x00000050) /* writing destination data */
-#define DMA_STAT__6 (0x00000060) /* waiting for DMA request to clear */
-#define DMA_STAT__7 (0x00000070) /* writing channel controller data */
-#define DMA_STAT__8 (0x00000080) /* stalled */
-#define DMA_STAT__9 (0x00000090) /* done */
-#define DMA_STAT__10 (0x000000a0) /* peripheral scatter-gather transition */
-#define DMA_STAT__11 (0x000000b0) /* Reserved */
-#define DMA_STAT__12 (0x000000c0) /* Reserved */
-#define DMA_STAT__13 (0x000000d0) /* Reserved */
-#define DMA_STAT__14 (0x000000e0) /* Reserved */
-#define DMA_STAT__15 (0x000000f0) /* Reserved */
-/* DMA_STAT[DMA_STAT_] Bits */
-//#define DMA_STAT__OFS (16) /* DMACHANS Offset */
-//#define DMA_STAT__M (0x001f0000) /* */
-//#define DMA_STAT_0 (0x00010000) /* */
-//#define DMA_STAT_1 (0x00020000) /* */
-//#define DMA_STAT_2 (0x00040000) /* */
-//#define DMA_STAT_3 (0x00080000) /* */
-#define DMA_STAT_4 (0x00100000) /* */
-//#define DMA_STAT__0 (0x00000000) /* Controller configured to use 1 DMA channel */
-//#define DMA_STAT__1 (0x00010000) /* Controller configured to use 2 DMA channels */
-#define DMA_STAT__30 (0x001e0000) /* Controller configured to use 31 DMA channels */
-#define DMA_STAT__31 (0x001f0000) /* Controller configured to use 32 DMA channels */
-/* DMA_STAT[DMA_STAT_] Bits */
-//#define DMA_STAT__OFS (28) /* TESTSTAT Offset */
-//#define DMA_STAT__M (0xf0000000) /* */
-//#define DMA_STAT_0 (0x10000000) /* */
-//#define DMA_STAT_1 (0x20000000) /* */
-//#define DMA_STAT_2 (0x40000000) /* */
-//#define DMA_STAT_3 (0x80000000) /* */
-//#define DMA_STAT__0 (0x00000000) /* Controller does not include the integration test logic */
-//#define DMA_STAT__1 (0x10000000) /* Controller includes the integration test logic */
-/* DMA_CFG[DMA_CFG_] Bits */
-#define DMA_CFG__OFS ( 0) /* MASTEN Offset */
-#define DMA_CFG_ (0x00000001) /* */
-/* DMA_CFG[DMA_CFG_] Bits */
-//#define DMA_CFG__OFS ( 5) /* CHPROTCTRL Offset */
-#define DMA_CFG__M (0x000000e0) /* */
-/* DMA_CTLBASE[DMA_CTLBASE_] Bits */
-#define DMA_CTLBASE__OFS ( 5) /* ADDR Offset */
-#define DMA_CTLBASE__M (0xffffffe0) /* */
-/* DMA_ERRCLR[DMA_ERRCLR_] Bits */
-#define DMA_ERRCLR__OFS ( 0) /* ERRCLR Offset */
-#define DMA_ERRCLR_ (0x00000001) /* */
+/******************************************************************************
+* DMA Bits
+******************************************************************************/
+/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */
+#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /**< NUM_DMA_CHANNELS Bit Offset */
+#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /**< NUM_DMA_CHANNELS Bit Mask */
+/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */
+#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /**< NUM_SRC_PER_CHANNEL Bit Offset */
+#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /**< NUM_SRC_PER_CHANNEL Bit Mask */
+/* DMA_SW_CHTRIG[CH0] Bits */
+#define DMA_SW_CHTRIG_CH0_OFS ( 0) /**< CH0 Bit Offset */
+#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /**< Write 1, triggers DMA_CHANNEL0 */
+/* DMA_SW_CHTRIG[CH1] Bits */
+#define DMA_SW_CHTRIG_CH1_OFS ( 1) /**< CH1 Bit Offset */
+#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /**< Write 1, triggers DMA_CHANNEL1 */
+/* DMA_SW_CHTRIG[CH2] Bits */
+#define DMA_SW_CHTRIG_CH2_OFS ( 2) /**< CH2 Bit Offset */
+#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /**< Write 1, triggers DMA_CHANNEL2 */
+/* DMA_SW_CHTRIG[CH3] Bits */
+#define DMA_SW_CHTRIG_CH3_OFS ( 3) /**< CH3 Bit Offset */
+#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /**< Write 1, triggers DMA_CHANNEL3 */
+/* DMA_SW_CHTRIG[CH4] Bits */
+#define DMA_SW_CHTRIG_CH4_OFS ( 4) /**< CH4 Bit Offset */
+#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /**< Write 1, triggers DMA_CHANNEL4 */
+/* DMA_SW_CHTRIG[CH5] Bits */
+#define DMA_SW_CHTRIG_CH5_OFS ( 5) /**< CH5 Bit Offset */
+#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /**< Write 1, triggers DMA_CHANNEL5 */
+/* DMA_SW_CHTRIG[CH6] Bits */
+#define DMA_SW_CHTRIG_CH6_OFS ( 6) /**< CH6 Bit Offset */
+#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /**< Write 1, triggers DMA_CHANNEL6 */
+/* DMA_SW_CHTRIG[CH7] Bits */
+#define DMA_SW_CHTRIG_CH7_OFS ( 7) /**< CH7 Bit Offset */
+#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /**< Write 1, triggers DMA_CHANNEL7 */
+/* DMA_SW_CHTRIG[CH8] Bits */
+#define DMA_SW_CHTRIG_CH8_OFS ( 8) /**< CH8 Bit Offset */
+#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /**< Write 1, triggers DMA_CHANNEL8 */
+/* DMA_SW_CHTRIG[CH9] Bits */
+#define DMA_SW_CHTRIG_CH9_OFS ( 9) /**< CH9 Bit Offset */
+#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /**< Write 1, triggers DMA_CHANNEL9 */
+/* DMA_SW_CHTRIG[CH10] Bits */
+#define DMA_SW_CHTRIG_CH10_OFS (10) /**< CH10 Bit Offset */
+#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /**< Write 1, triggers DMA_CHANNEL10 */
+/* DMA_SW_CHTRIG[CH11] Bits */
+#define DMA_SW_CHTRIG_CH11_OFS (11) /**< CH11 Bit Offset */
+#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /**< Write 1, triggers DMA_CHANNEL11 */
+/* DMA_SW_CHTRIG[CH12] Bits */
+#define DMA_SW_CHTRIG_CH12_OFS (12) /**< CH12 Bit Offset */
+#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /**< Write 1, triggers DMA_CHANNEL12 */
+/* DMA_SW_CHTRIG[CH13] Bits */
+#define DMA_SW_CHTRIG_CH13_OFS (13) /**< CH13 Bit Offset */
+#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /**< Write 1, triggers DMA_CHANNEL13 */
+/* DMA_SW_CHTRIG[CH14] Bits */
+#define DMA_SW_CHTRIG_CH14_OFS (14) /**< CH14 Bit Offset */
+#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /**< Write 1, triggers DMA_CHANNEL14 */
+/* DMA_SW_CHTRIG[CH15] Bits */
+#define DMA_SW_CHTRIG_CH15_OFS (15) /**< CH15 Bit Offset */
+#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /**< Write 1, triggers DMA_CHANNEL15 */
+/* DMA_SW_CHTRIG[CH16] Bits */
+#define DMA_SW_CHTRIG_CH16_OFS (16) /**< CH16 Bit Offset */
+#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /**< Write 1, triggers DMA_CHANNEL16 */
+/* DMA_SW_CHTRIG[CH17] Bits */
+#define DMA_SW_CHTRIG_CH17_OFS (17) /**< CH17 Bit Offset */
+#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /**< Write 1, triggers DMA_CHANNEL17 */
+/* DMA_SW_CHTRIG[CH18] Bits */
+#define DMA_SW_CHTRIG_CH18_OFS (18) /**< CH18 Bit Offset */
+#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /**< Write 1, triggers DMA_CHANNEL18 */
+/* DMA_SW_CHTRIG[CH19] Bits */
+#define DMA_SW_CHTRIG_CH19_OFS (19) /**< CH19 Bit Offset */
+#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /**< Write 1, triggers DMA_CHANNEL19 */
+/* DMA_SW_CHTRIG[CH20] Bits */
+#define DMA_SW_CHTRIG_CH20_OFS (20) /**< CH20 Bit Offset */
+#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /**< Write 1, triggers DMA_CHANNEL20 */
+/* DMA_SW_CHTRIG[CH21] Bits */
+#define DMA_SW_CHTRIG_CH21_OFS (21) /**< CH21 Bit Offset */
+#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /**< Write 1, triggers DMA_CHANNEL21 */
+/* DMA_SW_CHTRIG[CH22] Bits */
+#define DMA_SW_CHTRIG_CH22_OFS (22) /**< CH22 Bit Offset */
+#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /**< Write 1, triggers DMA_CHANNEL22 */
+/* DMA_SW_CHTRIG[CH23] Bits */
+#define DMA_SW_CHTRIG_CH23_OFS (23) /**< CH23 Bit Offset */
+#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /**< Write 1, triggers DMA_CHANNEL23 */
+/* DMA_SW_CHTRIG[CH24] Bits */
+#define DMA_SW_CHTRIG_CH24_OFS (24) /**< CH24 Bit Offset */
+#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /**< Write 1, triggers DMA_CHANNEL24 */
+/* DMA_SW_CHTRIG[CH25] Bits */
+#define DMA_SW_CHTRIG_CH25_OFS (25) /**< CH25 Bit Offset */
+#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /**< Write 1, triggers DMA_CHANNEL25 */
+/* DMA_SW_CHTRIG[CH26] Bits */
+#define DMA_SW_CHTRIG_CH26_OFS (26) /**< CH26 Bit Offset */
+#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /**< Write 1, triggers DMA_CHANNEL26 */
+/* DMA_SW_CHTRIG[CH27] Bits */
+#define DMA_SW_CHTRIG_CH27_OFS (27) /**< CH27 Bit Offset */
+#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /**< Write 1, triggers DMA_CHANNEL27 */
+/* DMA_SW_CHTRIG[CH28] Bits */
+#define DMA_SW_CHTRIG_CH28_OFS (28) /**< CH28 Bit Offset */
+#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /**< Write 1, triggers DMA_CHANNEL28 */
+/* DMA_SW_CHTRIG[CH29] Bits */
+#define DMA_SW_CHTRIG_CH29_OFS (29) /**< CH29 Bit Offset */
+#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /**< Write 1, triggers DMA_CHANNEL29 */
+/* DMA_SW_CHTRIG[CH30] Bits */
+#define DMA_SW_CHTRIG_CH30_OFS (30) /**< CH30 Bit Offset */
+#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /**< Write 1, triggers DMA_CHANNEL30 */
+/* DMA_SW_CHTRIG[CH31] Bits */
+#define DMA_SW_CHTRIG_CH31_OFS (31) /**< CH31 Bit Offset */
+#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /**< Write 1, triggers DMA_CHANNEL31 */
+/* DMA_CHN_SRCCFG[DMA_SRC] Bits */
+#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /**< DMA_SRC Bit Offset */
+#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /**< DMA_SRC Bit Mask */
+/* DMA_INT1_SRCCFG[INT_SRC] Bits */
+#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */
+#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */
+/* DMA_INT1_SRCCFG[EN] Bits */
+#define DMA_INT1_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */
+#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT1 mapping */
+/* DMA_INT2_SRCCFG[INT_SRC] Bits */
+#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */
+#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */
+/* DMA_INT2_SRCCFG[EN] Bits */
+#define DMA_INT2_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */
+#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT2 mapping */
+/* DMA_INT3_SRCCFG[INT_SRC] Bits */
+#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /**< INT_SRC Bit Offset */
+#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /**< INT_SRC Bit Mask */
+/* DMA_INT3_SRCCFG[EN] Bits */
+#define DMA_INT3_SRCCFG_EN_OFS ( 5) /**< EN Bit Offset */
+#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /**< Enables DMA_INT3 mapping */
+/* DMA_INT0_SRCFLG[CH0] Bits */
+#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /**< CH0 Bit Offset */
+#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /**< Channel 0 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH1] Bits */
+#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /**< CH1 Bit Offset */
+#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /**< Channel 1 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH2] Bits */
+#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /**< CH2 Bit Offset */
+#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /**< Channel 2 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH3] Bits */
+#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /**< CH3 Bit Offset */
+#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /**< Channel 3 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH4] Bits */
+#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /**< CH4 Bit Offset */
+#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /**< Channel 4 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH5] Bits */
+#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /**< CH5 Bit Offset */
+#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /**< Channel 5 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH6] Bits */
+#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /**< CH6 Bit Offset */
+#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /**< Channel 6 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH7] Bits */
+#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /**< CH7 Bit Offset */
+#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /**< Channel 7 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH8] Bits */
+#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /**< CH8 Bit Offset */
+#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /**< Channel 8 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH9] Bits */
+#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /**< CH9 Bit Offset */
+#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /**< Channel 9 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH10] Bits */
+#define DMA_INT0_SRCFLG_CH10_OFS (10) /**< CH10 Bit Offset */
+#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /**< Channel 10 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH11] Bits */
+#define DMA_INT0_SRCFLG_CH11_OFS (11) /**< CH11 Bit Offset */
+#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /**< Channel 11 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH12] Bits */
+#define DMA_INT0_SRCFLG_CH12_OFS (12) /**< CH12 Bit Offset */
+#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /**< Channel 12 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH13] Bits */
+#define DMA_INT0_SRCFLG_CH13_OFS (13) /**< CH13 Bit Offset */
+#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /**< Channel 13 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH14] Bits */
+#define DMA_INT0_SRCFLG_CH14_OFS (14) /**< CH14 Bit Offset */
+#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /**< Channel 14 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH15] Bits */
+#define DMA_INT0_SRCFLG_CH15_OFS (15) /**< CH15 Bit Offset */
+#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /**< Channel 15 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH16] Bits */
+#define DMA_INT0_SRCFLG_CH16_OFS (16) /**< CH16 Bit Offset */
+#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /**< Channel 16 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH17] Bits */
+#define DMA_INT0_SRCFLG_CH17_OFS (17) /**< CH17 Bit Offset */
+#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /**< Channel 17 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH18] Bits */
+#define DMA_INT0_SRCFLG_CH18_OFS (18) /**< CH18 Bit Offset */
+#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /**< Channel 18 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH19] Bits */
+#define DMA_INT0_SRCFLG_CH19_OFS (19) /**< CH19 Bit Offset */
+#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /**< Channel 19 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH20] Bits */
+#define DMA_INT0_SRCFLG_CH20_OFS (20) /**< CH20 Bit Offset */
+#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /**< Channel 20 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH21] Bits */
+#define DMA_INT0_SRCFLG_CH21_OFS (21) /**< CH21 Bit Offset */
+#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /**< Channel 21 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH22] Bits */
+#define DMA_INT0_SRCFLG_CH22_OFS (22) /**< CH22 Bit Offset */
+#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /**< Channel 22 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH23] Bits */
+#define DMA_INT0_SRCFLG_CH23_OFS (23) /**< CH23 Bit Offset */
+#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /**< Channel 23 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH24] Bits */
+#define DMA_INT0_SRCFLG_CH24_OFS (24) /**< CH24 Bit Offset */
+#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /**< Channel 24 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH25] Bits */
+#define DMA_INT0_SRCFLG_CH25_OFS (25) /**< CH25 Bit Offset */
+#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /**< Channel 25 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH26] Bits */
+#define DMA_INT0_SRCFLG_CH26_OFS (26) /**< CH26 Bit Offset */
+#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /**< Channel 26 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH27] Bits */
+#define DMA_INT0_SRCFLG_CH27_OFS (27) /**< CH27 Bit Offset */
+#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /**< Channel 27 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH28] Bits */
+#define DMA_INT0_SRCFLG_CH28_OFS (28) /**< CH28 Bit Offset */
+#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /**< Channel 28 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH29] Bits */
+#define DMA_INT0_SRCFLG_CH29_OFS (29) /**< CH29 Bit Offset */
+#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /**< Channel 29 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH30] Bits */
+#define DMA_INT0_SRCFLG_CH30_OFS (30) /**< CH30 Bit Offset */
+#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /**< Channel 30 was the source of DMA_INT0 */
+/* DMA_INT0_SRCFLG[CH31] Bits */
+#define DMA_INT0_SRCFLG_CH31_OFS (31) /**< CH31 Bit Offset */
+#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /**< Channel 31 was the source of DMA_INT0 */
+/* DMA_INT0_CLRFLG[CH0] Bits */
+#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /**< CH0 Bit Offset */
+#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH1] Bits */
+#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /**< CH1 Bit Offset */
+#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH2] Bits */
+#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /**< CH2 Bit Offset */
+#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH3] Bits */
+#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /**< CH3 Bit Offset */
+#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH4] Bits */
+#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /**< CH4 Bit Offset */
+#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH5] Bits */
+#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /**< CH5 Bit Offset */
+#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH6] Bits */
+#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /**< CH6 Bit Offset */
+#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH7] Bits */
+#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /**< CH7 Bit Offset */
+#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH8] Bits */
+#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /**< CH8 Bit Offset */
+#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH9] Bits */
+#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /**< CH9 Bit Offset */
+#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH10] Bits */
+#define DMA_INT0_CLRFLG_CH10_OFS (10) /**< CH10 Bit Offset */
+#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH11] Bits */
+#define DMA_INT0_CLRFLG_CH11_OFS (11) /**< CH11 Bit Offset */
+#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH12] Bits */
+#define DMA_INT0_CLRFLG_CH12_OFS (12) /**< CH12 Bit Offset */
+#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH13] Bits */
+#define DMA_INT0_CLRFLG_CH13_OFS (13) /**< CH13 Bit Offset */
+#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH14] Bits */
+#define DMA_INT0_CLRFLG_CH14_OFS (14) /**< CH14 Bit Offset */
+#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH15] Bits */
+#define DMA_INT0_CLRFLG_CH15_OFS (15) /**< CH15 Bit Offset */
+#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH16] Bits */
+#define DMA_INT0_CLRFLG_CH16_OFS (16) /**< CH16 Bit Offset */
+#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH17] Bits */
+#define DMA_INT0_CLRFLG_CH17_OFS (17) /**< CH17 Bit Offset */
+#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH18] Bits */
+#define DMA_INT0_CLRFLG_CH18_OFS (18) /**< CH18 Bit Offset */
+#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH19] Bits */
+#define DMA_INT0_CLRFLG_CH19_OFS (19) /**< CH19 Bit Offset */
+#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH20] Bits */
+#define DMA_INT0_CLRFLG_CH20_OFS (20) /**< CH20 Bit Offset */
+#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH21] Bits */
+#define DMA_INT0_CLRFLG_CH21_OFS (21) /**< CH21 Bit Offset */
+#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH22] Bits */
+#define DMA_INT0_CLRFLG_CH22_OFS (22) /**< CH22 Bit Offset */
+#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH23] Bits */
+#define DMA_INT0_CLRFLG_CH23_OFS (23) /**< CH23 Bit Offset */
+#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH24] Bits */
+#define DMA_INT0_CLRFLG_CH24_OFS (24) /**< CH24 Bit Offset */
+#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH25] Bits */
+#define DMA_INT0_CLRFLG_CH25_OFS (25) /**< CH25 Bit Offset */
+#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH26] Bits */
+#define DMA_INT0_CLRFLG_CH26_OFS (26) /**< CH26 Bit Offset */
+#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH27] Bits */
+#define DMA_INT0_CLRFLG_CH27_OFS (27) /**< CH27 Bit Offset */
+#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH28] Bits */
+#define DMA_INT0_CLRFLG_CH28_OFS (28) /**< CH28 Bit Offset */
+#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH29] Bits */
+#define DMA_INT0_CLRFLG_CH29_OFS (29) /**< CH29 Bit Offset */
+#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH30] Bits */
+#define DMA_INT0_CLRFLG_CH30_OFS (30) /**< CH30 Bit Offset */
+#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_INT0_CLRFLG[CH31] Bits */
+#define DMA_INT0_CLRFLG_CH31_OFS (31) /**< CH31 Bit Offset */
+#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /**< Clear corresponding DMA_INT0_SRCFLG_REG */
+/* DMA_STAT[MASTEN] Bits */
+#define DMA_STAT_MASTEN_OFS ( 0) /**< MASTEN Bit Offset */
+#define DMA_STAT_MASTEN ((uint32_t)0x00000001)
+/* DMA_STAT[STATE] Bits */
+#define DMA_STAT_STATE_OFS ( 4) /**< STATE Bit Offset */
+#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /**< STATE Bit Mask */
+#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /**< STATE Bit 0 */
+#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /**< STATE Bit 1 */
+#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /**< STATE Bit 2 */
+#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /**< STATE Bit 3 */
+#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /**< idle */
+#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /**< reading channel controller data */
+#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /**< reading source data end pointer */
+#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /**< reading destination data end pointer */
+#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /**< reading source data */
+#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /**< writing destination data */
+#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /**< waiting for DMA request to clear */
+#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /**< writing channel controller data */
+#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /**< stalled */
+#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /**< done */
+#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /**< peripheral scatter-gather transition */
+#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /**< Reserved */
+#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /**< Reserved */
+#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /**< Reserved */
+#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /**< Reserved */
+#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /**< Reserved */
+/* DMA_STAT[DMACHANS] Bits */
+#define DMA_STAT_DMACHANS_OFS (16) /**< DMACHANS Bit Offset */
+#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /**< DMACHANS Bit Mask */
+#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /**< DMACHANS Bit 0 */
+#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /**< DMACHANS Bit 1 */
+#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /**< DMACHANS Bit 2 */
+#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /**< DMACHANS Bit 3 */
+#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /**< DMACHANS Bit 4 */
+#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /**< Controller configured to use 1 DMA channel */
+#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /**< Controller configured to use 2 DMA channels */
+#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /**< Controller configured to use 31 DMA channels */
+#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /**< Controller configured to use 32 DMA channels */
+/* DMA_STAT[TESTSTAT] Bits */
+#define DMA_STAT_TESTSTAT_OFS (28) /**< TESTSTAT Bit Offset */
+#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /**< TESTSTAT Bit Mask */
+#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /**< TESTSTAT Bit 0 */
+#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /**< TESTSTAT Bit 1 */
+#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /**< TESTSTAT Bit 2 */
+#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /**< TESTSTAT Bit 3 */
+#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /**< Controller does not include the integration test logic */
+#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /**< Controller includes the integration test logic */
+/* DMA_CFG[MASTEN] Bits */
+#define DMA_CFG_MASTEN_OFS ( 0) /**< MASTEN Bit Offset */
+#define DMA_CFG_MASTEN ((uint32_t)0x00000001)
+/* DMA_CFG[CHPROTCTRL] Bits */
+#define DMA_CFG_CHPROTCTRL_OFS ( 5) /**< CHPROTCTRL Bit Offset */
+#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /**< CHPROTCTRL Bit Mask */
+/* DMA_CTLBASE[ADDR] Bits */
+#define DMA_CTLBASE_ADDR_OFS ( 5) /**< ADDR Bit Offset */
+#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /**< ADDR Bit Mask */
+/* DMA_ERRCLR[ERRCLR] Bits */
+#define DMA_ERRCLR_ERRCLR_OFS ( 0) /**< ERRCLR Bit Offset */
+#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001)
/* UDMA_STAT Control Bits */
-#define UDMA_STAT_DMACHANS_M 0x001F0000 /* Available uDMA Channels Minus 1 */
-#define UDMA_STAT_STATE_M 0x000000F0 /* Control State Machine Status */
-#define UDMA_STAT_STATE_IDLE 0x00000000 /* Idle */
-#define UDMA_STAT_STATE_RD_CTRL 0x00000010 /* Reading channel controller data */
-#define UDMA_STAT_STATE_RD_SRCENDP 0x00000020 /* Reading source end pointer */
-#define UDMA_STAT_STATE_RD_DSTENDP 0x00000030 /* Reading destination end pointer */
-#define UDMA_STAT_STATE_RD_SRCDAT 0x00000040 /* Reading source data */
-#define UDMA_STAT_STATE_WR_DSTDAT 0x00000050 /* Writing destination data */
-#define UDMA_STAT_STATE_WAIT 0x00000060 /* Waiting for uDMA request to */
- /* clear */
-#define UDMA_STAT_STATE_WR_CTRL 0x00000070 /* Writing channel controller data */
-#define UDMA_STAT_STATE_STALL 0x00000080 /* Stalled */
-#define UDMA_STAT_STATE_DONE 0x00000090 /* Done */
-#define UDMA_STAT_STATE_UNDEF 0x000000A0 /* Undefined */
-#define UDMA_STAT_MASTEN 0x00000001 /* Master Enable Status */
-#define UDMA_STAT_DMACHANS_S 16
+#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /* Available uDMA Channels Minus 1 */
+#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /* Control State Machine Status */
+#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /* Idle */
+#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /* Reading channel controller data */
+#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /* Reading source end pointer */
+#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /* Reading destination end pointer */
+#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /* Reading source data */
+#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /* Writing destination data */
+#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /* Waiting for uDMA request to clear */
+#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /* Writing channel controller data */
+#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /* Stalled */
+#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /* Done */
+#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /* Undefined */
+#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /* Master Enable Status */
+#define UDMA_STAT_DMACHANS_S (16)
/* UDMA_CFG Control Bits */
-#define UDMA_CFG_MASTEN 0x00000001 /* Controller Master Enable */
+#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /* Controller Master Enable */
/* UDMA_CTLBASE Control Bits */
-#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 /* Channel Control Base Address */
-#define UDMA_CTLBASE_ADDR_S 10
+#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /* Channel Control Base Address */
+#define UDMA_CTLBASE_ADDR_S (10)
/* UDMA_ALTBASE Control Bits */
-#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF /* Alternate Channel Address Pointer */
-#define UDMA_ALTBASE_ADDR_S 0
+#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /* Alternate Channel Address Pointer */
+#define UDMA_ALTBASE_ADDR_S ( 0)
/* UDMA_WAITSTAT Control Bits */
-#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF /* Channel [n] Wait Status */
+#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Wait Status */
/* UDMA_SWREQ Control Bits */
-#define UDMA_SWREQ_M 0xFFFFFFFF /* Channel [n] Software Request */
+#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Software Request */
/* UDMA_USEBURSTSET Control Bits */
-#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF /* Channel [n] Useburst Set */
+#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Useburst Set */
/* UDMA_USEBURSTCLR Control Bits */
-#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF /* Channel [n] Useburst Clear */
+#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Useburst Clear */
/* UDMA_REQMASKSET Control Bits */
-#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF /* Channel [n] Request Mask Set */
+#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Request Mask Set */
/* UDMA_REQMASKCLR Control Bits */
-#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF /* Channel [n] Request Mask Clear */
+#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Request Mask Clear */
/* UDMA_ENASET Control Bits */
-#define UDMA_ENASET_SET_M 0xFFFFFFFF /* Channel [n] Enable Set */
+#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Enable Set */
/* UDMA_ENACLR Control Bits */
-#define UDMA_ENACLR_CLR_M 0xFFFFFFFF /* Clear Channel [n] Enable Clear */
+#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Clear Channel [n] Enable Clear */
/* UDMA_ALTSET Control Bits */
-#define UDMA_ALTSET_SET_M 0xFFFFFFFF /* Channel [n] Alternate Set */
+#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Alternate Set */
/* UDMA_ALTCLR Control Bits */
-#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF /* Channel [n] Alternate Clear */
+#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Alternate Clear */
/* UDMA_PRIOSET Control Bits */
-#define UDMA_PRIOSET_SET_M 0xFFFFFFFF /* Channel [n] Priority Set */
+#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Priority Set */
/* UDMA_PRIOCLR Control Bits */
-#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF /* Channel [n] Priority Clear */
+#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Priority Clear */
/* UDMA_ERRCLR Control Bits */
-#define UDMA_ERRCLR_ERRCLR 0x00000001 /* uDMA Bus Error Status */
+#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /* uDMA Bus Error Status */
/* UDMA_CHASGN Control Bits */
-#define UDMA_CHASGN_M 0xFFFFFFFF /* Channel [n] Assignment Select */
-#define UDMA_CHASGN_PRIMARY 0x00000000 /* Use the primary channel */
- /* assignment */
-#define UDMA_CHASGN_SECONDARY 0x00000001 /* Use the secondary channel */
- /* assignment */
+#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /* Channel [n] Assignment Select */
+#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /* Use the primary channel assignment */
+#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /* Use the secondary channel assignment */
/* Micro Direct Memory Access (uDMA) offsets */
-#define UDMA_O_SRCENDP 0x00000000 /* DMA Channel Source Address End */
- /* Pointer */
-#define UDMA_O_DSTENDP 0x00000004 /* DMA Channel Destination Address */
- /* End Pointer */
-#define UDMA_O_CHCTL 0x00000008 /* DMA Channel Control Word */
+#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /* DMA Channel Source Address End Pointer */
+#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /* DMA Channel Destination Address End Pointer */
+#define UDMA_O_CHCTL ((uint32_t)0x00000008) /* DMA Channel Control Word */
/* UDMA_O_SRCENDP Control Bits */
-#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF /* Source Address End Pointer */
-#define UDMA_SRCENDP_ADDR_S 0
+#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /* Source Address End Pointer */
+#define UDMA_SRCENDP_ADDR_S ( 0)
/* UDMA_O_DSTENDP Control Bits */
-#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF /* Destination Address End Pointer */
-#define UDMA_DSTENDP_ADDR_S 0
+#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /* Destination Address End Pointer */
+#define UDMA_DSTENDP_ADDR_S ( 0)
/* UDMA_O_CHCTL Control Bits */
-#define UDMA_CHCTL_DSTINC_M 0xC0000000 /* Destination Address Increment */
-#define UDMA_CHCTL_DSTINC_8 0x00000000 /* Byte */
-#define UDMA_CHCTL_DSTINC_16 0x40000000 /* Half-word */
-#define UDMA_CHCTL_DSTINC_32 0x80000000 /* Word */
-#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 /* No increment */
-#define UDMA_CHCTL_DSTSIZE_M 0x30000000 /* Destination Data Size */
-#define UDMA_CHCTL_DSTSIZE_8 0x00000000 /* Byte */
-#define UDMA_CHCTL_DSTSIZE_16 0x10000000 /* Half-word */
-#define UDMA_CHCTL_DSTSIZE_32 0x20000000 /* Word */
-#define UDMA_CHCTL_SRCINC_M 0x0C000000 /* Source Address Increment */
-#define UDMA_CHCTL_SRCINC_8 0x00000000 /* Byte */
-#define UDMA_CHCTL_SRCINC_16 0x04000000 /* Half-word */
-#define UDMA_CHCTL_SRCINC_32 0x08000000 /* Word */
-#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 /* No increment */
-#define UDMA_CHCTL_SRCSIZE_M 0x03000000 /* Source Data Size */
-#define UDMA_CHCTL_SRCSIZE_8 0x00000000 /* Byte */
-#define UDMA_CHCTL_SRCSIZE_16 0x01000000 /* Half-word */
-#define UDMA_CHCTL_SRCSIZE_32 0x02000000 /* Word */
-#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 /* Arbitration Size */
-#define UDMA_CHCTL_ARBSIZE_1 0x00000000 /* 1 Transfer */
-#define UDMA_CHCTL_ARBSIZE_2 0x00004000 /* 2 Transfers */
-#define UDMA_CHCTL_ARBSIZE_4 0x00008000 /* 4 Transfers */
-#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 /* 8 Transfers */
-#define UDMA_CHCTL_ARBSIZE_16 0x00010000 /* 16 Transfers */
-#define UDMA_CHCTL_ARBSIZE_32 0x00014000 /* 32 Transfers */
-#define UDMA_CHCTL_ARBSIZE_64 0x00018000 /* 64 Transfers */
-#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 /* 128 Transfers */
-#define UDMA_CHCTL_ARBSIZE_256 0x00020000 /* 256 Transfers */
-#define UDMA_CHCTL_ARBSIZE_512 0x00024000 /* 512 Transfers */
-#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 /* 1024 Transfers */
-#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 /* Transfer Size (minus 1) */
-#define UDMA_CHCTL_NXTUSEBURST 0x00000008 /* Next Useburst */
-#define UDMA_CHCTL_XFERMODE_M 0x00000007 /* uDMA Transfer Mode */
-#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 /* Stop */
-#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 /* Basic */
-#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 /* Auto-Request */
-#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 /* Ping-Pong */
-#define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 /* Memory Scatter-Gather */
-#define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 /* Alternate Memory Scatter-Gather */
-#define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 /* Peripheral Scatter-Gather */
-#define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 /* Alternate Peripheral */
- /* Scatter-Gather */
-#define UDMA_CHCTL_XFERSIZE_S 4
+#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /* Destination Address Increment */
+#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /* Byte */
+#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /* Half-word */
+#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /* Word */
+#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /* No increment */
+#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /* Destination Data Size */
+#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /* Byte */
+#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /* Half-word */
+#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /* Word */
+#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /* Source Address Increment */
+#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /* Byte */
+#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /* Half-word */
+#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /* Word */
+#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /* No increment */
+#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /* Source Data Size */
+#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /* Byte */
+#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /* Half-word */
+#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /* Word */
+#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /* Arbitration Size */
+#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /* 1 Transfer */
+#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /* 2 Transfers */
+#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /* 4 Transfers */
+#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /* 8 Transfers */
+#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /* 16 Transfers */
+#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /* 32 Transfers */
+#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /* 64 Transfers */
+#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /* 128 Transfers */
+#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /* 256 Transfers */
+#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /* 512 Transfers */
+#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /* 1024 Transfers */
+#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /* Transfer Size (minus 1) */
+#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /* Next Useburst */
+#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /* uDMA Transfer Mode */
+#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /* Stop */
+#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /* Basic */
+#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /* Auto-Request */
+#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /* Ping-Pong */
+#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /* Memory Scatter-Gather */
+#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /* Alternate Memory Scatter-Gather */
+#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /* Peripheral Scatter-Gather */
+#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /* Alternate Peripheral Scatter-Gather */
+
+#define UDMA_CHCTL_XFERSIZE_S ( 4)
-//*****************************************************************************
-// DWT Bits
-//*****************************************************************************
-/* DWT_CTRL[DWT_CTRL_CYCCNTENA] Bits */
-#define DWT_CTRL_CYCCNTENA_OFS ( 0) /* CYCCNTENA Offset */
-#define DWT_CTRL_CYCCNTENA (0x00000001) /* */
-/* DWT_CTRL[DWT_CTRL_POSTPRESET] Bits */
-#define DWT_CTRL_POSTPRESET_OFS ( 1) /* POSTPRESET Offset */
-#define DWT_CTRL_POSTPRESET_M (0x0000001e) /* */
-/* DWT_CTRL[DWT_CTRL_POSTCNT] Bits */
-#define DWT_CTRL_POSTCNT_OFS ( 5) /* POSTCNT Offset */
-#define DWT_CTRL_POSTCNT_M (0x000001e0) /* */
-/* DWT_CTRL[DWT_CTRL_CYCTAP] Bits */
-#define DWT_CTRL_CYCTAP_OFS ( 9) /* CYCTAP Offset */
-#define DWT_CTRL_CYCTAP (0x00000200) /* */
-/* DWT_CTRL[DWT_CTRL_SYNCTAP] Bits */
-#define DWT_CTRL_SYNCTAP_OFS (10) /* SYNCTAP Offset */
-#define DWT_CTRL_SYNCTAP_M (0x00000c00) /* */
-#define DWT_CTRL_SYNCTAP0 (0x00000400) /* */
-#define DWT_CTRL_SYNCTAP1 (0x00000800) /* */
-#define DWT_CTRL_SYNCTAP_0 (0x00000000) /* Disabled. No synch counting. */
-#define DWT_CTRL_SYNCTAP_1 (0x00000400) /* Tap at CYCCNT bit 24. */
-#define DWT_CTRL_SYNCTAP_2 (0x00000800) /* Tap at CYCCNT bit 26. */
-#define DWT_CTRL_SYNCTAP_3 (0x00000c00) /* Tap at CYCCNT bit 28. */
-/* DWT_CTRL[DWT_CTRL_PCSAMPLEENA] Bits */
-#define DWT_CTRL_PCSAMPLEENA_OFS (12) /* PCSAMPLEENA Offset */
-#define DWT_CTRL_PCSAMPLEENA (0x00001000) /* */
-/* DWT_CTRL[DWT_CTRL_EXCTRCENA] Bits */
-#define DWT_CTRL_EXCTRCENA_OFS (16) /* EXCTRCENA Offset */
-#define DWT_CTRL_EXCTRCENA (0x00010000) /* */
-/* DWT_CTRL[DWT_CTRL_CPIEVTENA] Bits */
-#define DWT_CTRL_CPIEVTENA_OFS (17) /* CPIEVTENA Offset */
-#define DWT_CTRL_CPIEVTENA (0x00020000) /* */
-/* DWT_CTRL[DWT_CTRL_EXCEVTENA] Bits */
-#define DWT_CTRL_EXCEVTENA_OFS (18) /* EXCEVTENA Offset */
-#define DWT_CTRL_EXCEVTENA (0x00040000) /* */
-/* DWT_CTRL[DWT_CTRL_SLEEPEVTENA] Bits */
-#define DWT_CTRL_SLEEPEVTENA_OFS (19) /* SLEEPEVTENA Offset */
-#define DWT_CTRL_SLEEPEVTENA (0x00080000) /* */
-/* DWT_CTRL[DWT_CTRL_LSUEVTENA] Bits */
-#define DWT_CTRL_LSUEVTENA_OFS (20) /* LSUEVTENA Offset */
-#define DWT_CTRL_LSUEVTENA (0x00100000) /* */
-/* DWT_CTRL[DWT_CTRL_FOLDEVTENA] Bits */
-#define DWT_CTRL_FOLDEVTENA_OFS (21) /* FOLDEVTENA Offset */
-#define DWT_CTRL_FOLDEVTENA (0x00200000) /* */
-/* DWT_CTRL[DWT_CTRL_CYCEVTENA] Bits */
-#define DWT_CTRL_CYCEVTENA_OFS (22) /* CYCEVTENA Offset */
-#define DWT_CTRL_CYCEVTENA (0x00400000) /* */
-/* DWT_CTRL[DWT_CTRL_NOPRFCNT] Bits */
-#define DWT_CTRL_NOPRFCNT_OFS (24) /* NOPRFCNT Offset */
-#define DWT_CTRL_NOPRFCNT (0x01000000) /* */
-/* DWT_CTRL[DWT_CTRL_NOCYCCNT] Bits */
-#define DWT_CTRL_NOCYCCNT_OFS (25) /* NOCYCCNT Offset */
-#define DWT_CTRL_NOCYCCNT (0x02000000) /* */
-/* DWT_CPICNT[DWT_CPICNT_CPICNT] Bits */
-#define DWT_CPICNT_CPICNT_OFS ( 0) /* CPICNT Offset */
-#define DWT_CPICNT_CPICNT_M (0x000000ff) /* */
-/* DWT_EXCCNT[DWT_EXCCNT_EXCCNT] Bits */
-#define DWT_EXCCNT_EXCCNT_OFS ( 0) /* EXCCNT Offset */
-#define DWT_EXCCNT_EXCCNT_M (0x000000ff) /* */
-/* DWT_SLEEPCNT[DWT_SLEEPCNT_SLEEPCNT] Bits */
-#define DWT_SLEEPCNT_SLEEPCNT_OFS ( 0) /* SLEEPCNT Offset */
-#define DWT_SLEEPCNT_SLEEPCNT_M (0x000000ff) /* */
-/* DWT_LSUCNT[DWT_LSUCNT_LSUCNT] Bits */
-#define DWT_LSUCNT_LSUCNT_OFS ( 0) /* LSUCNT Offset */
-#define DWT_LSUCNT_LSUCNT_M (0x000000ff) /* */
-/* DWT_FOLDCNT[DWT_FOLDCNT_FOLDCNT] Bits */
-#define DWT_FOLDCNT_FOLDCNT_OFS ( 0) /* FOLDCNT Offset */
-#define DWT_FOLDCNT_FOLDCNT_M (0x000000ff) /* */
-/* DWT_MASK0[DWT_MASK0_MASK] Bits */
-#define DWT_MASK0_MASK_OFS ( 0) /* MASK Offset */
-#define DWT_MASK0_MASK_M (0x0000000f) /* */
-/* DWT_FUNCTION0[DWT_FUNCTION0_FUNCTION] Bits */
-#define DWT_FUNCTION0_FUNCTION_OFS ( 0) /* FUNCTION Offset */
-#define DWT_FUNCTION0_FUNCTION_M (0x0000000f) /* */
-#define DWT_FUNCTION0_FUNCTION0 (0x00000001) /* */
-#define DWT_FUNCTION0_FUNCTION1 (0x00000002) /* */
-#define DWT_FUNCTION0_FUNCTION2 (0x00000004) /* */
-#define DWT_FUNCTION0_FUNCTION3 (0x00000008) /* */
-#define DWT_FUNCTION0_FUNCTION_0 (0x00000000) /* Disabled */
-#define DWT_FUNCTION0_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
-#define DWT_FUNCTION0_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
-#define DWT_FUNCTION0_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
-#define DWT_FUNCTION0_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
-#define DWT_FUNCTION0_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
-#define DWT_FUNCTION0_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
-#define DWT_FUNCTION0_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
-#define DWT_FUNCTION0_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
-#define DWT_FUNCTION0_FUNCTION_9 (0x00000009) /* ETM trigger on read */
-#define DWT_FUNCTION0_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
-#define DWT_FUNCTION0_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
-#define DWT_FUNCTION0_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
-#define DWT_FUNCTION0_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
-#define DWT_FUNCTION0_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
-#define DWT_FUNCTION0_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
-/* DWT_FUNCTION0[DWT_FUNCTION0_EMITRANGE] Bits */
-#define DWT_FUNCTION0_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
-#define DWT_FUNCTION0_EMITRANGE (0x00000020) /* */
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVMATCH] Bits */
-#define DWT_FUNCTION0_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
-#define DWT_FUNCTION0_DATAVMATCH (0x00000100) /* */
-/* DWT_FUNCTION0[DWT_FUNCTION0_LNK1ENA] Bits */
-#define DWT_FUNCTION0_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
-#define DWT_FUNCTION0_LNK1ENA (0x00000200) /* */
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVSIZE] Bits */
-#define DWT_FUNCTION0_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
-#define DWT_FUNCTION0_DATAVSIZE_M (0x00000c00) /* */
-#define DWT_FUNCTION0_DATAVSIZE0 (0x00000400) /* */
-#define DWT_FUNCTION0_DATAVSIZE1 (0x00000800) /* */
-#define DWT_FUNCTION0_DATAVSIZE_0 (0x00000000) /* byte */
-#define DWT_FUNCTION0_DATAVSIZE_1 (0x00000400) /* halfword */
-#define DWT_FUNCTION0_DATAVSIZE_2 (0x00000800) /* word */
-#define DWT_FUNCTION0_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR0] Bits */
-#define DWT_FUNCTION0_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
-#define DWT_FUNCTION0_DATAVADDR0_M (0x0000f000) /* */
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR1] Bits */
-#define DWT_FUNCTION0_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
-#define DWT_FUNCTION0_DATAVADDR1_M (0x000f0000) /* */
-/* DWT_FUNCTION0[DWT_FUNCTION0_MATCHED] Bits */
-#define DWT_FUNCTION0_MATCHED_OFS (24) /* MATCHED Offset */
-#define DWT_FUNCTION0_MATCHED (0x01000000) /* */
-/* DWT_MASK1[DWT_MASK1_MASK] Bits */
-#define DWT_MASK1_MASK_OFS ( 0) /* MASK Offset */
-#define DWT_MASK1_MASK_M (0x0000000f) /* */
-/* DWT_FUNCTION1[DWT_FUNCTION1_FUNCTION] Bits */
-#define DWT_FUNCTION1_FUNCTION_OFS ( 0) /* FUNCTION Offset */
-#define DWT_FUNCTION1_FUNCTION_M (0x0000000f) /* */
-#define DWT_FUNCTION1_FUNCTION0 (0x00000001) /* */
-#define DWT_FUNCTION1_FUNCTION1 (0x00000002) /* */
-#define DWT_FUNCTION1_FUNCTION2 (0x00000004) /* */
-#define DWT_FUNCTION1_FUNCTION3 (0x00000008) /* */
-#define DWT_FUNCTION1_FUNCTION_0 (0x00000000) /* Disabled */
-#define DWT_FUNCTION1_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
-#define DWT_FUNCTION1_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
-#define DWT_FUNCTION1_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
-#define DWT_FUNCTION1_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
-#define DWT_FUNCTION1_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
-#define DWT_FUNCTION1_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
-#define DWT_FUNCTION1_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
-#define DWT_FUNCTION1_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
-#define DWT_FUNCTION1_FUNCTION_9 (0x00000009) /* ETM trigger on read */
-#define DWT_FUNCTION1_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
-#define DWT_FUNCTION1_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
-#define DWT_FUNCTION1_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
-#define DWT_FUNCTION1_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
-#define DWT_FUNCTION1_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
-#define DWT_FUNCTION1_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
-/* DWT_FUNCTION1[DWT_FUNCTION1_EMITRANGE] Bits */
-#define DWT_FUNCTION1_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
-#define DWT_FUNCTION1_EMITRANGE (0x00000020) /* */
-/* DWT_FUNCTION1[DWT_FUNCTION1_CYCMATCH] Bits */
-#define DWT_FUNCTION1_CYCMATCH_OFS ( 7) /* CYCMATCH Offset */
-#define DWT_FUNCTION1_CYCMATCH (0x00000080) /* */
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVMATCH] Bits */
-#define DWT_FUNCTION1_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
-#define DWT_FUNCTION1_DATAVMATCH (0x00000100) /* */
-/* DWT_FUNCTION1[DWT_FUNCTION1_LNK1ENA] Bits */
-#define DWT_FUNCTION1_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
-#define DWT_FUNCTION1_LNK1ENA (0x00000200) /* */
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVSIZE] Bits */
-#define DWT_FUNCTION1_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
-#define DWT_FUNCTION1_DATAVSIZE_M (0x00000c00) /* */
-#define DWT_FUNCTION1_DATAVSIZE0 (0x00000400) /* */
-#define DWT_FUNCTION1_DATAVSIZE1 (0x00000800) /* */
-#define DWT_FUNCTION1_DATAVSIZE_0 (0x00000000) /* byte */
-#define DWT_FUNCTION1_DATAVSIZE_1 (0x00000400) /* halfword */
-#define DWT_FUNCTION1_DATAVSIZE_2 (0x00000800) /* word */
-#define DWT_FUNCTION1_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR0] Bits */
-#define DWT_FUNCTION1_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
-#define DWT_FUNCTION1_DATAVADDR0_M (0x0000f000) /* */
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR1] Bits */
-#define DWT_FUNCTION1_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
-#define DWT_FUNCTION1_DATAVADDR1_M (0x000f0000) /* */
-/* DWT_FUNCTION1[DWT_FUNCTION1_MATCHED] Bits */
-#define DWT_FUNCTION1_MATCHED_OFS (24) /* MATCHED Offset */
-#define DWT_FUNCTION1_MATCHED (0x01000000) /* */
-/* DWT_MASK2[DWT_MASK2_MASK] Bits */
-#define DWT_MASK2_MASK_OFS ( 0) /* MASK Offset */
-#define DWT_MASK2_MASK_M (0x0000000f) /* */
-/* DWT_FUNCTION2[DWT_FUNCTION2_FUNCTION] Bits */
-#define DWT_FUNCTION2_FUNCTION_OFS ( 0) /* FUNCTION Offset */
-#define DWT_FUNCTION2_FUNCTION_M (0x0000000f) /* */
-#define DWT_FUNCTION2_FUNCTION0 (0x00000001) /* */
-#define DWT_FUNCTION2_FUNCTION1 (0x00000002) /* */
-#define DWT_FUNCTION2_FUNCTION2 (0x00000004) /* */
-#define DWT_FUNCTION2_FUNCTION3 (0x00000008) /* */
-#define DWT_FUNCTION2_FUNCTION_0 (0x00000000) /* Disabled */
-#define DWT_FUNCTION2_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
-#define DWT_FUNCTION2_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
-#define DWT_FUNCTION2_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
-#define DWT_FUNCTION2_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
-#define DWT_FUNCTION2_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
-#define DWT_FUNCTION2_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
-#define DWT_FUNCTION2_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
-#define DWT_FUNCTION2_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
-#define DWT_FUNCTION2_FUNCTION_9 (0x00000009) /* ETM trigger on read */
-#define DWT_FUNCTION2_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
-#define DWT_FUNCTION2_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
-#define DWT_FUNCTION2_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
-#define DWT_FUNCTION2_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
-#define DWT_FUNCTION2_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
-#define DWT_FUNCTION2_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
-/* DWT_FUNCTION2[DWT_FUNCTION2_EMITRANGE] Bits */
-#define DWT_FUNCTION2_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
-#define DWT_FUNCTION2_EMITRANGE (0x00000020) /* */
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVMATCH] Bits */
-#define DWT_FUNCTION2_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
-#define DWT_FUNCTION2_DATAVMATCH (0x00000100) /* */
-/* DWT_FUNCTION2[DWT_FUNCTION2_LNK1ENA] Bits */
-#define DWT_FUNCTION2_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
-#define DWT_FUNCTION2_LNK1ENA (0x00000200) /* */
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVSIZE] Bits */
-#define DWT_FUNCTION2_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
-#define DWT_FUNCTION2_DATAVSIZE_M (0x00000c00) /* */
-#define DWT_FUNCTION2_DATAVSIZE0 (0x00000400) /* */
-#define DWT_FUNCTION2_DATAVSIZE1 (0x00000800) /* */
-#define DWT_FUNCTION2_DATAVSIZE_0 (0x00000000) /* byte */
-#define DWT_FUNCTION2_DATAVSIZE_1 (0x00000400) /* halfword */
-#define DWT_FUNCTION2_DATAVSIZE_2 (0x00000800) /* word */
-#define DWT_FUNCTION2_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR0] Bits */
-#define DWT_FUNCTION2_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
-#define DWT_FUNCTION2_DATAVADDR0_M (0x0000f000) /* */
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR1] Bits */
-#define DWT_FUNCTION2_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
-#define DWT_FUNCTION2_DATAVADDR1_M (0x000f0000) /* */
-/* DWT_FUNCTION2[DWT_FUNCTION2_MATCHED] Bits */
-#define DWT_FUNCTION2_MATCHED_OFS (24) /* MATCHED Offset */
-#define DWT_FUNCTION2_MATCHED (0x01000000) /* */
-/* DWT_MASK3[DWT_MASK3_MASK] Bits */
-#define DWT_MASK3_MASK_OFS ( 0) /* MASK Offset */
-#define DWT_MASK3_MASK_M (0x0000000f) /* */
-/* DWT_FUNCTION3[DWT_FUNCTION3_FUNCTION] Bits */
-#define DWT_FUNCTION3_FUNCTION_OFS ( 0) /* FUNCTION Offset */
-#define DWT_FUNCTION3_FUNCTION_M (0x0000000f) /* */
-#define DWT_FUNCTION3_FUNCTION0 (0x00000001) /* */
-#define DWT_FUNCTION3_FUNCTION1 (0x00000002) /* */
-#define DWT_FUNCTION3_FUNCTION2 (0x00000004) /* */
-#define DWT_FUNCTION3_FUNCTION3 (0x00000008) /* */
-#define DWT_FUNCTION3_FUNCTION_0 (0x00000000) /* Disabled */
-#define DWT_FUNCTION3_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
-#define DWT_FUNCTION3_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
-#define DWT_FUNCTION3_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
-#define DWT_FUNCTION3_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
-#define DWT_FUNCTION3_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
-#define DWT_FUNCTION3_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
-#define DWT_FUNCTION3_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
-#define DWT_FUNCTION3_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
-#define DWT_FUNCTION3_FUNCTION_9 (0x00000009) /* ETM trigger on read */
-#define DWT_FUNCTION3_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
-#define DWT_FUNCTION3_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
-#define DWT_FUNCTION3_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
-#define DWT_FUNCTION3_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
-#define DWT_FUNCTION3_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
-#define DWT_FUNCTION3_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
-/* DWT_FUNCTION3[DWT_FUNCTION3_EMITRANGE] Bits */
-#define DWT_FUNCTION3_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
-#define DWT_FUNCTION3_EMITRANGE (0x00000020) /* */
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVMATCH] Bits */
-#define DWT_FUNCTION3_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
-#define DWT_FUNCTION3_DATAVMATCH (0x00000100) /* */
-/* DWT_FUNCTION3[DWT_FUNCTION3_LNK1ENA] Bits */
-#define DWT_FUNCTION3_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
-#define DWT_FUNCTION3_LNK1ENA (0x00000200) /* */
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVSIZE] Bits */
-#define DWT_FUNCTION3_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
-#define DWT_FUNCTION3_DATAVSIZE_M (0x00000c00) /* */
-#define DWT_FUNCTION3_DATAVSIZE0 (0x00000400) /* */
-#define DWT_FUNCTION3_DATAVSIZE1 (0x00000800) /* */
-#define DWT_FUNCTION3_DATAVSIZE_0 (0x00000000) /* byte */
-#define DWT_FUNCTION3_DATAVSIZE_1 (0x00000400) /* halfword */
-#define DWT_FUNCTION3_DATAVSIZE_2 (0x00000800) /* word */
-#define DWT_FUNCTION3_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR0] Bits */
-#define DWT_FUNCTION3_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
-#define DWT_FUNCTION3_DATAVADDR0_M (0x0000f000) /* */
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR1] Bits */
-#define DWT_FUNCTION3_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
-#define DWT_FUNCTION3_DATAVADDR1_M (0x000f0000) /* */
-/* DWT_FUNCTION3[DWT_FUNCTION3_MATCHED] Bits */
-#define DWT_FUNCTION3_MATCHED_OFS (24) /* MATCHED Offset */
-#define DWT_FUNCTION3_MATCHED (0x01000000) /* */
+/******************************************************************************
+* DWT Bits
+******************************************************************************/
-//*****************************************************************************
-// EUSCI_A0 Bits
-//*****************************************************************************
-/* UCA0CTLW0[UCSWRST] Bits */
-#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA0CTLW0[UCTXBRK] Bits */
-#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
-#define UCTXBRK (0x0002) /* Transmit break */
-/* UCA0CTLW0[UCTXADDR] Bits */
-#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
-#define UCTXADDR (0x0004) /* Transmit address */
-/* UCA0CTLW0[UCDORM] Bits */
-#define UCDORM_OFS ( 3) /* UCDORM Offset */
-#define UCDORM (0x0008) /* Dormant */
-/* UCA0CTLW0[UCBRKIE] Bits */
-#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
-#define UCBRKIE (0x0010) /* Receive break character interrupt enable */
-/* UCA0CTLW0[UCRXEIE] Bits */
-#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
-#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
-/* UCA0CTLW0[UCSSEL] Bits */
-#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-#define UCSSEL_0 (0x0000) /* UCLK */
-#define UCSSEL_1 (0x0040) /* ACLK */
-#define UCSSEL_2 (0x0080) /* SMCLK */
-#define UCSSEL__UCLK (0x0000) /* UCLK */
-#define UCSSEL__ACLK (0x0040) /* ACLK */
-#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA0CTLW0[UCSYNC] Bits */
-#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA0CTLW0[UCMODE] Bits */
-#define UCMODE_OFS ( 9) /* UCMODE Offset */
-#define UCMODE_M (0x0600) /* eUSCI_A mode */
-#define UCMODE0 (0x0200) /* eUSCI_A mode */
-#define UCMODE1 (0x0400) /* eUSCI_A mode */
-#define UCMODE_0 (0x0000) /* UART mode */
-#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
-#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
-#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
-/* UCA0CTLW0[UCSPB] Bits */
-#define UCSPB_OFS (11) /* UCSPB Offset */
-#define UCSPB (0x0800) /* Stop bit select */
-/* UCA0CTLW0[UC7BIT] Bits */
-#define UC7BIT_OFS (12) /* UC7BIT Offset */
-#define UC7BIT (0x1000) /* Character length */
-/* UCA0CTLW0[UCMSB] Bits */
-#define UCMSB_OFS (13) /* UCMSB Offset */
-#define UCMSB (0x2000) /* MSB first select */
-/* UCA0CTLW0[UCPAR] Bits */
-#define UCPAR_OFS (14) /* UCPAR Offset */
-#define UCPAR (0x4000) /* Parity select */
-/* UCA0CTLW0[UCPEN] Bits */
-#define UCPEN_OFS (15) /* UCPEN Offset */
-#define UCPEN (0x8000) /* Parity enable */
-/* UCA0CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA0CTLW0_SPI[UCSTEM] Bits */
-#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCA0CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA0CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA0CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-/* UCA0CTLW0_SPI[UCMST] Bits */
-#define UCMST_OFS (11) /* UCMST Offset */
-#define UCMST (0x0800) /* Master mode select */
-/* UCA0CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCA0CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCA0CTLW0_SPI[UCCKPL] Bits */
-#define UCCKPL_OFS (14) /* UCCKPL Offset */
-#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCA0CTLW0_SPI[UCCKPH] Bits */
-#define UCCKPH_OFS (15) /* UCCKPH Offset */
-#define UCCKPH (0x8000) /* Clock phase select */
-/* UCA0CTLW1[UCGLIT] Bits */
-#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-#define UCGLIT_M (0x0003) /* Deglitch time */
-#define UCGLIT0 (0x0001) /* Deglitch time */
-#define UCGLIT1 (0x0002) /* Deglitch time */
-#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
-#define UCGLIT_1 (0x0001) /* Approximately 50 ns */
-#define UCGLIT_2 (0x0002) /* Approximately 100 ns */
-#define UCGLIT_3 (0x0003) /* Approximately 200 ns */
-/* UCA0MCTLW[UCOS16] Bits */
-#define UCOS16_OFS ( 0) /* UCOS16 Offset */
-#define UCOS16 (0x0001) /* Oversampling mode enabled */
-/* UCA0MCTLW[UCBRF] Bits */
-#define UCBRF_OFS ( 4) /* UCBRF Offset */
-#define UCBRF_M (0x00f0) /* First modulation stage select */
-/* UCA0MCTLW[UCBRS] Bits */
-#define UCBRS_OFS ( 8) /* UCBRS Offset */
-#define UCBRS_M (0xff00) /* Second modulation stage select */
-/* UCA0STATW[UCBUSY] Bits */
-#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA0STATW[UCADDR_UCIDLE] Bits */
-#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
-#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
-/* UCA0STATW[UCRXERR] Bits */
-#define UCRXERR_OFS ( 2) /* UCRXERR Offset */
-#define UCRXERR (0x0004) /* Receive error flag */
-/* UCA0STATW[UCBRK] Bits */
-#define UCBRK_OFS ( 3) /* UCBRK Offset */
-#define UCBRK (0x0008) /* Break detect flag */
-/* UCA0STATW[UCPE] Bits */
-#define UCPE_OFS ( 4) /* UCPE Offset */
-#define UCPE (0x0010) /* */
-/* UCA0STATW[UCOE] Bits */
-#define UCOE_OFS ( 5) /* UCOE Offset */
-#define UCOE (0x0020) /* Overrun error flag */
-/* UCA0STATW[UCFE] Bits */
-#define UCFE_OFS ( 6) /* UCFE Offset */
-#define UCFE (0x0040) /* Framing error flag */
-/* UCA0STATW[UCLISTEN] Bits */
-#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA0STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA0STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCA0STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCA0STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA0RXBUF[UCRXBUF] Bits */
-#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA0RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA0TXBUF[UCTXBUF] Bits */
-#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA0TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA0ABCTL[UCABDEN] Bits */
-#define UCABDEN_OFS ( 0) /* UCABDEN Offset */
-#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
-/* UCA0ABCTL[UCBTOE] Bits */
-#define UCBTOE_OFS ( 2) /* UCBTOE Offset */
-#define UCBTOE (0x0004) /* Break time out error */
-/* UCA0ABCTL[UCSTOE] Bits */
-#define UCSTOE_OFS ( 3) /* UCSTOE Offset */
-#define UCSTOE (0x0008) /* Synch field time out error */
-/* UCA0ABCTL[UCDELIM] Bits */
-#define UCDELIM_OFS ( 4) /* UCDELIM Offset */
-#define UCDELIM_M (0x0030) /* Break/synch delimiter length */
-#define UCDELIM0 (0x0010) /* Break/synch delimiter length */
-#define UCDELIM1 (0x0020) /* Break/synch delimiter length */
-#define UCDELIM_0 (0x0000) /* 1 bit time */
-#define UCDELIM_1 (0x0010) /* 2 bit times */
-#define UCDELIM_2 (0x0020) /* 3 bit times */
-#define UCDELIM_3 (0x0030) /* 4 bit times */
-/* UCA0IRCTL[UCIREN] Bits */
-#define UCIREN_OFS ( 0) /* UCIREN Offset */
-#define UCIREN (0x0001) /* IrDA encoder/decoder enable */
-/* UCA0IRCTL[UCIRTXCLK] Bits */
-#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
-#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
-/* UCA0IRCTL[UCIRTXPL] Bits */
-#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
-#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
-/* UCA0IRCTL[UCIRRXFE] Bits */
-#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
-#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
-/* UCA0IRCTL[UCIRRXPL] Bits */
-#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
-#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
-/* UCA0IRCTL[UCIRRXFL] Bits */
-#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
-#define UCIRRXFL_M (0x3c00) /* Receive filter length */
-/* UCA0IE[UCRXIE] Bits */
-#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA0IE[UCTXIE] Bits */
-#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA0IE[UCSTTIE] Bits */
-#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-#define UCSTTIE (0x0004) /* Start bit interrupt enable */
-/* UCA0IE[UCTXCPTIE] Bits */
-#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
-#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
-/* UCA0IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA0IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA0IFG[UCRXIFG] Bits */
-#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA0IFG[UCTXIFG] Bits */
-#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-#define UCTXIFG (0x0002) /* Transmit interrupt flag */
-/* UCA0IFG[UCSTTIFG] Bits */
-#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-#define UCSTTIFG (0x0004) /* Start bit interrupt flag */
-/* UCA0IFG[UCTXCPTIFG] Bits */
-#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
-#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
-/* UCA0IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA0IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
+/******************************************************************************
+* EUSCI_A Bits
+******************************************************************************/
+/* EUSCI_A_CTLW0[SWRST] Bits */
+#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */
+#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */
+/* EUSCI_A_CTLW0[TXBRK] Bits */
+#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /**< UCTXBRK Bit Offset */
+#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /**< Transmit break */
+/* EUSCI_A_CTLW0[TXADDR] Bits */
+#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /**< UCTXADDR Bit Offset */
+#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /**< Transmit address */
+/* EUSCI_A_CTLW0[DORM] Bits */
+#define EUSCI_A_CTLW0_DORM_OFS ( 3) /**< UCDORM Bit Offset */
+#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /**< Dormant */
+/* EUSCI_A_CTLW0[BRKIE] Bits */
+#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /**< UCBRKIE Bit Offset */
+#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /**< Receive break character interrupt enable */
+/* EUSCI_A_CTLW0[RXEIE] Bits */
+#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /**< UCRXEIE Bit Offset */
+#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /**< Receive erroneous-character interrupt enable */
+/* EUSCI_A_CTLW0[SSEL] Bits */
+#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */
+#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */
+#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */
+#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */
+#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLK */
+#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */
+#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */
+#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /**< UCLK */
+#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */
+#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */
+/* EUSCI_A_CTLW0[SYNC] Bits */
+#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */
+#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */
+/* EUSCI_A_CTLW0[MODE] Bits */
+#define EUSCI_A_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */
+#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */
+#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */
+#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */
+#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /**< UART mode */
+#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /**< Idle-line multiprocessor mode */
+#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /**< Address-bit multiprocessor mode */
+#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /**< UART mode with automatic baud-rate detection */
+/* EUSCI_A_CTLW0[SPB] Bits */
+#define EUSCI_A_CTLW0_SPB_OFS (11) /**< UCSPB Bit Offset */
+#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /**< Stop bit select */
+/* EUSCI_A_CTLW0[SEVENBIT] Bits */
+#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */
+#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */
+/* EUSCI_A_CTLW0[MSB] Bits */
+#define EUSCI_A_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */
+#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */
+/* EUSCI_A_CTLW0[PAR] Bits */
+#define EUSCI_A_CTLW0_PAR_OFS (14) /**< UCPAR Bit Offset */
+#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /**< Parity select */
+/* EUSCI_A_CTLW0[PEN] Bits */
+#define EUSCI_A_CTLW0_PEN_OFS (15) /**< UCPEN Bit Offset */
+#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /**< Parity enable */
+/* EUSCI_A_CTLW0[STEM] Bits */
+#define EUSCI_A_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */
+#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */
+/* EUSCI_A_CTLW0[SSEL] Bits */
-//*****************************************************************************
-// EUSCI_A1 Bits
-//*****************************************************************************
-/* UCA1CTLW0[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA1CTLW0[UCTXBRK] Bits */
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
-//#define UCTXBRK (0x0002) /* Transmit break */
-/* UCA1CTLW0[UCTXADDR] Bits */
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
-//#define UCTXADDR (0x0004) /* Transmit address */
-/* UCA1CTLW0[UCDORM] Bits */
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */
-//#define UCDORM (0x0008) /* Dormant */
-/* UCA1CTLW0[UCBRKIE] Bits */
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */
-/* UCA1CTLW0[UCRXEIE] Bits */
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
-/* UCA1CTLW0[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-//#define UCSSEL_0 (0x0000) /* UCLK */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL__UCLK (0x0000) /* UCLK */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA1CTLW0[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA1CTLW0[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */
-//#define UCMODE_0 (0x0000) /* UART mode */
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
-/* UCA1CTLW0[UCSPB] Bits */
-//#define UCSPB_OFS (11) /* UCSPB Offset */
-//#define UCSPB (0x0800) /* Stop bit select */
-/* UCA1CTLW0[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCA1CTLW0[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCA1CTLW0[UCPAR] Bits */
-//#define UCPAR_OFS (14) /* UCPAR Offset */
-//#define UCPAR (0x4000) /* Parity select */
-/* UCA1CTLW0[UCPEN] Bits */
-//#define UCPEN_OFS (15) /* UCPEN Offset */
-//#define UCPEN (0x8000) /* Parity enable */
-/* UCA1CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA1CTLW0_SPI[UCSTEM] Bits */
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCA1CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA1CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA1CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-/* UCA1CTLW0_SPI[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCA1CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCA1CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCA1CTLW0_SPI[UCCKPL] Bits */
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */
-//#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCA1CTLW0_SPI[UCCKPH] Bits */
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */
-//#define UCCKPH (0x8000) /* Clock phase select */
-/* UCA1CTLW1[UCGLIT] Bits */
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-//#define UCGLIT_M (0x0003) /* Deglitch time */
-//#define UCGLIT0 (0x0001) /* Deglitch time */
-//#define UCGLIT1 (0x0002) /* Deglitch time */
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */
-/* UCA1MCTLW[UCOS16] Bits */
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */
-/* UCA1MCTLW[UCBRF] Bits */
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */
-//#define UCBRF_M (0x00f0) /* First modulation stage select */
-/* UCA1MCTLW[UCBRS] Bits */
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */
-//#define UCBRS_M (0xff00) /* Second modulation stage select */
-/* UCA1STATW[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA1STATW[UCADDR_UCIDLE] Bits */
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
-/* UCA1STATW[UCRXERR] Bits */
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */
-//#define UCRXERR (0x0004) /* Receive error flag */
-/* UCA1STATW[UCBRK] Bits */
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */
-//#define UCBRK (0x0008) /* Break detect flag */
-/* UCA1STATW[UCPE] Bits */
-//#define UCPE_OFS ( 4) /* UCPE Offset */
-//#define UCPE (0x0010) /* */
-/* UCA1STATW[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCA1STATW[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCA1STATW[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA1STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA1STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCA1STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCA1STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA1RXBUF[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA1RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA1TXBUF[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA1TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA1ABCTL[UCABDEN] Bits */
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
-/* UCA1ABCTL[UCBTOE] Bits */
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */
-//#define UCBTOE (0x0004) /* Break time out error */
-/* UCA1ABCTL[UCSTOE] Bits */
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */
-//#define UCSTOE (0x0008) /* Synch field time out error */
-/* UCA1ABCTL[UCDELIM] Bits */
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */
-//#define UCDELIM_0 (0x0000) /* 1 bit time */
-//#define UCDELIM_1 (0x0010) /* 2 bit times */
-//#define UCDELIM_2 (0x0020) /* 3 bit times */
-//#define UCDELIM_3 (0x0030) /* 4 bit times */
-/* UCA1IRCTL[UCIREN] Bits */
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */
-/* UCA1IRCTL[UCIRTXCLK] Bits */
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
-/* UCA1IRCTL[UCIRTXPL] Bits */
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
-/* UCA1IRCTL[UCIRRXFE] Bits */
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
-/* UCA1IRCTL[UCIRRXPL] Bits */
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
-/* UCA1IRCTL[UCIRRXFL] Bits */
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */
-/* UCA1IE[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA1IE[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA1IE[UCSTTIE] Bits */
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */
-/* UCA1IE[UCTXCPTIE] Bits */
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
-/* UCA1IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA1IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA1IFG[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA1IFG[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
-/* UCA1IFG[UCSTTIFG] Bits */
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */
-/* UCA1IFG[UCTXCPTIFG] Bits */
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
-/* UCA1IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA1IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
+#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */
-//*****************************************************************************
-// EUSCI_A2 Bits
-//*****************************************************************************
-/* UCA2CTLW0[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA2CTLW0[UCTXBRK] Bits */
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
-//#define UCTXBRK (0x0002) /* Transmit break */
-/* UCA2CTLW0[UCTXADDR] Bits */
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
-//#define UCTXADDR (0x0004) /* Transmit address */
-/* UCA2CTLW0[UCDORM] Bits */
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */
-//#define UCDORM (0x0008) /* Dormant */
-/* UCA2CTLW0[UCBRKIE] Bits */
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */
-/* UCA2CTLW0[UCRXEIE] Bits */
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
-/* UCA2CTLW0[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-//#define UCSSEL_0 (0x0000) /* UCLK */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL__UCLK (0x0000) /* UCLK */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA2CTLW0[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA2CTLW0[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */
-//#define UCMODE_0 (0x0000) /* UART mode */
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
-/* UCA2CTLW0[UCSPB] Bits */
-//#define UCSPB_OFS (11) /* UCSPB Offset */
-//#define UCSPB (0x0800) /* Stop bit select */
-/* UCA2CTLW0[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCA2CTLW0[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCA2CTLW0[UCPAR] Bits */
-//#define UCPAR_OFS (14) /* UCPAR Offset */
-//#define UCPAR (0x4000) /* Parity select */
-/* UCA2CTLW0[UCPEN] Bits */
-//#define UCPEN_OFS (15) /* UCPEN Offset */
-//#define UCPEN (0x8000) /* Parity enable */
-/* UCA2CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA2CTLW0_SPI[UCSTEM] Bits */
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCA2CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA2CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA2CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-/* UCA2CTLW0_SPI[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCA2CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCA2CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCA2CTLW0_SPI[UCCKPL] Bits */
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */
-//#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCA2CTLW0_SPI[UCCKPH] Bits */
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */
-//#define UCCKPH (0x8000) /* Clock phase select */
-/* UCA2CTLW1[UCGLIT] Bits */
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-//#define UCGLIT_M (0x0003) /* Deglitch time */
-//#define UCGLIT0 (0x0001) /* Deglitch time */
-//#define UCGLIT1 (0x0002) /* Deglitch time */
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */
-/* UCA2MCTLW[UCOS16] Bits */
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */
-/* UCA2MCTLW[UCBRF] Bits */
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */
-//#define UCBRF_M (0x00f0) /* First modulation stage select */
-/* UCA2MCTLW[UCBRS] Bits */
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */
-//#define UCBRS_M (0xff00) /* Second modulation stage select */
-/* UCA2STATW[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA2STATW[UCADDR_UCIDLE] Bits */
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
-/* UCA2STATW[UCRXERR] Bits */
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */
-//#define UCRXERR (0x0004) /* Receive error flag */
-/* UCA2STATW[UCBRK] Bits */
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */
-//#define UCBRK (0x0008) /* Break detect flag */
-/* UCA2STATW[UCPE] Bits */
-//#define UCPE_OFS ( 4) /* UCPE Offset */
-//#define UCPE (0x0010) /* */
-/* UCA2STATW[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCA2STATW[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCA2STATW[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA2STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA2STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCA2STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCA2STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA2RXBUF[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA2RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA2TXBUF[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA2TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA2ABCTL[UCABDEN] Bits */
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
-/* UCA2ABCTL[UCBTOE] Bits */
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */
-//#define UCBTOE (0x0004) /* Break time out error */
-/* UCA2ABCTL[UCSTOE] Bits */
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */
-//#define UCSTOE (0x0008) /* Synch field time out error */
-/* UCA2ABCTL[UCDELIM] Bits */
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */
-//#define UCDELIM_0 (0x0000) /* 1 bit time */
-//#define UCDELIM_1 (0x0010) /* 2 bit times */
-//#define UCDELIM_2 (0x0020) /* 3 bit times */
-//#define UCDELIM_3 (0x0030) /* 4 bit times */
-/* UCA2IRCTL[UCIREN] Bits */
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */
-/* UCA2IRCTL[UCIRTXCLK] Bits */
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
-/* UCA2IRCTL[UCIRTXPL] Bits */
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
-/* UCA2IRCTL[UCIRRXFE] Bits */
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
-/* UCA2IRCTL[UCIRRXPL] Bits */
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
-/* UCA2IRCTL[UCIRRXFL] Bits */
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */
-/* UCA2IE[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA2IE[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA2IE[UCSTTIE] Bits */
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */
-/* UCA2IE[UCTXCPTIE] Bits */
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
-/* UCA2IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA2IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA2IFG[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA2IFG[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
-/* UCA2IFG[UCSTTIFG] Bits */
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */
-/* UCA2IFG[UCTXCPTIFG] Bits */
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
-/* UCA2IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA2IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
+/* EUSCI_A_CTLW0[MODE] Bits */
-//*****************************************************************************
-// EUSCI_A3 Bits
-//*****************************************************************************
-/* UCA3CTLW0[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA3CTLW0[UCTXBRK] Bits */
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
-//#define UCTXBRK (0x0002) /* Transmit break */
-/* UCA3CTLW0[UCTXADDR] Bits */
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
-//#define UCTXADDR (0x0004) /* Transmit address */
-/* UCA3CTLW0[UCDORM] Bits */
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */
-//#define UCDORM (0x0008) /* Dormant */
-/* UCA3CTLW0[UCBRKIE] Bits */
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */
-/* UCA3CTLW0[UCRXEIE] Bits */
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
-/* UCA3CTLW0[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-//#define UCSSEL_0 (0x0000) /* UCLK */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL__UCLK (0x0000) /* UCLK */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA3CTLW0[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA3CTLW0[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */
-//#define UCMODE_0 (0x0000) /* UART mode */
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
-/* UCA3CTLW0[UCSPB] Bits */
-//#define UCSPB_OFS (11) /* UCSPB Offset */
-//#define UCSPB (0x0800) /* Stop bit select */
-/* UCA3CTLW0[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCA3CTLW0[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCA3CTLW0[UCPAR] Bits */
-//#define UCPAR_OFS (14) /* UCPAR Offset */
-//#define UCPAR (0x4000) /* Parity select */
-/* UCA3CTLW0[UCPEN] Bits */
-//#define UCPEN_OFS (15) /* UCPEN Offset */
-//#define UCPEN (0x8000) /* Parity enable */
-/* UCA3CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCA3CTLW0_SPI[UCSTEM] Bits */
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCA3CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-/* UCA3CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCA3CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-/* UCA3CTLW0_SPI[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCA3CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCA3CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCA3CTLW0_SPI[UCCKPL] Bits */
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */
-//#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCA3CTLW0_SPI[UCCKPH] Bits */
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */
-//#define UCCKPH (0x8000) /* Clock phase select */
-/* UCA3CTLW1[UCGLIT] Bits */
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-//#define UCGLIT_M (0x0003) /* Deglitch time */
-//#define UCGLIT0 (0x0001) /* Deglitch time */
-//#define UCGLIT1 (0x0002) /* Deglitch time */
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */
-/* UCA3MCTLW[UCOS16] Bits */
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */
-/* UCA3MCTLW[UCBRF] Bits */
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */
-//#define UCBRF_M (0x00f0) /* First modulation stage select */
-/* UCA3MCTLW[UCBRS] Bits */
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */
-//#define UCBRS_M (0xff00) /* Second modulation stage select */
-/* UCA3STATW[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA3STATW[UCADDR_UCIDLE] Bits */
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
-/* UCA3STATW[UCRXERR] Bits */
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */
-//#define UCRXERR (0x0004) /* Receive error flag */
-/* UCA3STATW[UCBRK] Bits */
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */
-//#define UCBRK (0x0008) /* Break detect flag */
-/* UCA3STATW[UCPE] Bits */
-//#define UCPE_OFS ( 4) /* UCPE Offset */
-//#define UCPE (0x0010) /* */
-/* UCA3STATW[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCA3STATW[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCA3STATW[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA3STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_A busy */
-/* UCA3STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCA3STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCA3STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCA3RXBUF[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA3RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCA3TXBUF[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA3TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCA3ABCTL[UCABDEN] Bits */
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
-/* UCA3ABCTL[UCBTOE] Bits */
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */
-//#define UCBTOE (0x0004) /* Break time out error */
-/* UCA3ABCTL[UCSTOE] Bits */
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */
-//#define UCSTOE (0x0008) /* Synch field time out error */
-/* UCA3ABCTL[UCDELIM] Bits */
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */
-//#define UCDELIM_0 (0x0000) /* 1 bit time */
-//#define UCDELIM_1 (0x0010) /* 2 bit times */
-//#define UCDELIM_2 (0x0020) /* 3 bit times */
-//#define UCDELIM_3 (0x0030) /* 4 bit times */
-/* UCA3IRCTL[UCIREN] Bits */
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */
-/* UCA3IRCTL[UCIRTXCLK] Bits */
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
-/* UCA3IRCTL[UCIRTXPL] Bits */
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
-/* UCA3IRCTL[UCIRRXFE] Bits */
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
-/* UCA3IRCTL[UCIRRXPL] Bits */
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
-/* UCA3IRCTL[UCIRRXFL] Bits */
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */
-/* UCA3IE[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA3IE[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA3IE[UCSTTIE] Bits */
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */
-/* UCA3IE[UCTXCPTIE] Bits */
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
-/* UCA3IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCA3IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCA3IFG[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA3IFG[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
-/* UCA3IFG[UCSTTIFG] Bits */
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */
-/* UCA3IFG[UCTXCPTIFG] Bits */
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
-/* UCA3IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCA3IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
+
+/* EUSCI_A_CTLW0[MST] Bits */
+#define EUSCI_A_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */
+#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */
+/* EUSCI_A_CTLW0[CKPL] Bits */
+#define EUSCI_A_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */
+#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */
+/* EUSCI_A_CTLW0[CKPH] Bits */
+#define EUSCI_A_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */
+#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */
+/* EUSCI_A_CTLW1[GLIT] Bits */
+#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */
+#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */
+#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */
+#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */
+#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< Approximately 2 ns (equivalent of 1 delay element) */
+#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< Approximately 50 ns */
+#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< Approximately 100 ns */
+#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< Approximately 200 ns */
+/* EUSCI_A_MCTLW[OS16] Bits */
+#define EUSCI_A_MCTLW_OS16_OFS ( 0) /**< UCOS16 Bit Offset */
+#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /**< Oversampling mode enabled */
+/* EUSCI_A_MCTLW[BRF] Bits */
+#define EUSCI_A_MCTLW_BRF_OFS ( 4) /**< UCBRF Bit Offset */
+#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /**< UCBRF Bit Mask */
+/* EUSCI_A_MCTLW[BRS] Bits */
+#define EUSCI_A_MCTLW_BRS_OFS ( 8) /**< UCBRS Bit Offset */
+#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /**< UCBRS Bit Mask */
+/* EUSCI_A_STATW[BUSY] Bits */
+#define EUSCI_A_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */
+#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_A busy */
+/* EUSCI_A_STATW[ADDR_IDLE] Bits */
+#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /**< UCADDR_UCIDLE Bit Offset */
+#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /**< Address received / Idle line detected */
+/* EUSCI_A_STATW[RXERR] Bits */
+#define EUSCI_A_STATW_RXERR_OFS ( 2) /**< UCRXERR Bit Offset */
+#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /**< Receive error flag */
+/* EUSCI_A_STATW[BRK] Bits */
+#define EUSCI_A_STATW_BRK_OFS ( 3) /**< UCBRK Bit Offset */
+#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /**< Break detect flag */
+/* EUSCI_A_STATW[PE] Bits */
+#define EUSCI_A_STATW_PE_OFS ( 4) /**< UCPE Bit Offset */
+#define EUSCI_A_STATW_PE ((uint16_t)0x0010)
+/* EUSCI_A_STATW[OE] Bits */
+#define EUSCI_A_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */
+#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */
+/* EUSCI_A_STATW[FE] Bits */
+#define EUSCI_A_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */
+#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */
+/* EUSCI_A_STATW[LISTEN] Bits */
+#define EUSCI_A_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */
+#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */
+/* EUSCI_A_RXBUF[RXBUF] Bits */
+#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */
+#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */
+/* EUSCI_A_TXBUF[TXBUF] Bits */
+#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */
+#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */
+/* EUSCI_A_ABCTL[ABDEN] Bits */
+#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /**< UCABDEN Bit Offset */
+#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /**< Automatic baud-rate detect enable */
+/* EUSCI_A_ABCTL[BTOE] Bits */
+#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /**< UCBTOE Bit Offset */
+#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /**< Break time out error */
+/* EUSCI_A_ABCTL[STOE] Bits */
+#define EUSCI_A_ABCTL_STOE_OFS ( 3) /**< UCSTOE Bit Offset */
+#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /**< Synch field time out error */
+/* EUSCI_A_ABCTL[DELIM] Bits */
+#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /**< UCDELIM Bit Offset */
+#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /**< UCDELIM Bit Mask */
+#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /**< DELIM Bit 0 */
+#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /**< DELIM Bit 1 */
+#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /**< 1 bit time */
+#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /**< 2 bit times */
+#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /**< 3 bit times */
+#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /**< 4 bit times */
+/* EUSCI_A_IRCTL[IREN] Bits */
+#define EUSCI_A_IRCTL_IREN_OFS ( 0) /**< UCIREN Bit Offset */
+#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /**< IrDA encoder/decoder enable */
+/* EUSCI_A_IRCTL[IRTXCLK] Bits */
+#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /**< UCIRTXCLK Bit Offset */
+#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /**< IrDA transmit pulse clock select */
+/* EUSCI_A_IRCTL[IRTXPL] Bits */
+#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /**< UCIRTXPL Bit Offset */
+#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /**< UCIRTXPL Bit Mask */
+/* EUSCI_A_IRCTL[IRRXFE] Bits */
+#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /**< UCIRRXFE Bit Offset */
+#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /**< IrDA receive filter enabled */
+/* EUSCI_A_IRCTL[IRRXPL] Bits */
+#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /**< UCIRRXPL Bit Offset */
+#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /**< IrDA receive input UCAxRXD polarity */
+/* EUSCI_A_IRCTL[IRRXFL] Bits */
+#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /**< UCIRRXFL Bit Offset */
+#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /**< UCIRRXFL Bit Mask */
+/* EUSCI_A_IE[RXIE] Bits */
+#define EUSCI_A_IE_RXIE_OFS ( 0) /**< UCRXIE Bit Offset */
+#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */
+/* EUSCI_A_IE[TXIE] Bits */
+#define EUSCI_A_IE_TXIE_OFS ( 1) /**< UCTXIE Bit Offset */
+#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */
+/* EUSCI_A_IE[STTIE] Bits */
+#define EUSCI_A_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */
+#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /**< Start bit interrupt enable */
+/* EUSCI_A_IE[TXCPTIE] Bits */
+#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /**< UCTXCPTIE Bit Offset */
+#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /**< Transmit complete interrupt enable */
+/* EUSCI_A_UCAxIE_SPI[RXIE] Bits */
+#define EUSCI_A__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */
+#define EUSCI_A__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */
+/* EUSCI_A_UCAxIE_SPI[TXIE] Bits */
+#define EUSCI_A__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */
+#define EUSCI_A__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */
+/* EUSCI_A_IFG[RXIFG] Bits */
+#define EUSCI_A_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */
+#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */
+/* EUSCI_A_IFG[TXIFG] Bits */
+#define EUSCI_A_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */
+#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */
+/* EUSCI_A_IFG[STTIFG] Bits */
+#define EUSCI_A_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */
+#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /**< Start bit interrupt flag */
+/* EUSCI_A_IFG[TXCPTIFG] Bits */
+#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /**< UCTXCPTIFG Bit Offset */
+#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /**< Transmit ready interrupt enable */
-//*****************************************************************************
-// EUSCI_B0 Bits
-//*****************************************************************************
-/* UCB0CTLW0[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB0CTLW0[UCTXSTT] Bits */
-#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
-#define UCTXSTT (0x0002) /* Transmit START condition in master mode */
-/* UCB0CTLW0[UCTXSTP] Bits */
-#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
-#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
-/* UCB0CTLW0[UCTXNACK] Bits */
-#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
-#define UCTXNACK (0x0008) /* Transmit a NACK */
-/* UCB0CTLW0[UCTR] Bits */
-#define UCTR_OFS ( 4) /* UCTR Offset */
-#define UCTR (0x0010) /* Transmitter/receiver */
-/* UCB0CTLW0[UCTXACK] Bits */
-#define UCTXACK_OFS ( 5) /* UCTXACK Offset */
-#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
-/* UCB0CTLW0[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_0 (0x0000) /* UCLKI */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-#define UCSSEL__UCLKI (0x0000) /* UCLKI */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB0CTLW0[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB0CTLW0[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB0CTLW0[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB0CTLW0[UCMM] Bits */
-#define UCMM_OFS (13) /* UCMM Offset */
-#define UCMM (0x2000) /* Multi-master environment select */
-/* UCB0CTLW0[UCSLA10] Bits */
-#define UCSLA10_OFS (14) /* UCSLA10 Offset */
-#define UCSLA10 (0x4000) /* Slave addressing mode select */
-/* UCB0CTLW0[UCA10] Bits */
-#define UCA10_OFS (15) /* UCA10 Offset */
-#define UCA10 (0x8000) /* Own addressing mode select */
-/* UCB0CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB0CTLW0_SPI[UCSTEM] Bits */
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCB0CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-//#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB0CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB0CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB0CTLW0_SPI[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB0CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCB0CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCB0CTLW0_SPI[UCCKPL] Bits */
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */
-//#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCB0CTLW0_SPI[UCCKPH] Bits */
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */
-//#define UCCKPH (0x8000) /* Clock phase select */
-/* UCB0CTLW1[UCGLIT] Bits */
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-//#define UCGLIT_M (0x0003) /* Deglitch time */
-//#define UCGLIT0 (0x0001) /* Deglitch time */
-//#define UCGLIT1 (0x0002) /* Deglitch time */
-//#define UCGLIT_0 (0x0000) /* 50 ns */
-//#define UCGLIT_1 (0x0001) /* 25 ns */
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */
-/* UCB0CTLW1[UCASTP] Bits */
-#define UCASTP_OFS ( 2) /* UCASTP Offset */
-#define UCASTP_M (0x000c) /* Automatic STOP condition generation */
-#define UCASTP0 (0x0004) /* Automatic STOP condition generation */
-#define UCASTP1 (0x0008) /* Automatic STOP condition generation */
-#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
-#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
-#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
-/* UCB0CTLW1[UCSWACK] Bits */
-#define UCSWACK_OFS ( 4) /* UCSWACK Offset */
-#define UCSWACK (0x0010) /* SW or HW ACK control */
-/* UCB0CTLW1[UCSTPNACK] Bits */
-#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
-#define UCSTPNACK (0x0020) /* ACK all master bytes */
-/* UCB0CTLW1[UCCLTO] Bits */
-#define UCCLTO_OFS ( 6) /* UCCLTO Offset */
-#define UCCLTO_M (0x00c0) /* Clock low timeout select */
-#define UCCLTO0 (0x0040) /* Clock low timeout select */
-#define UCCLTO1 (0x0080) /* Clock low timeout select */
-#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
-#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
-#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
-#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
-/* UCB0CTLW1[UCETXINT] Bits */
-#define UCETXINT_OFS ( 8) /* UCETXINT Offset */
-#define UCETXINT (0x0100) /* Early UCTXIFG0 */
-/* UCB0STATW[UCBBUSY] Bits */
-#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
-#define UCBBUSY (0x0010) /* Bus busy */
-/* UCB0STATW[UCGC] Bits */
-#define UCGC_OFS ( 5) /* UCGC Offset */
-#define UCGC (0x0020) /* General call address received */
-/* UCB0STATW[UCSCLLOW] Bits */
-#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
-#define UCSCLLOW (0x0040) /* SCL low */
-/* UCB0STATW[UCBCNT] Bits */
-#define UCBCNT_OFS ( 8) /* UCBCNT Offset */
-#define UCBCNT_M (0xff00) /* Hardware byte counter value */
-/* UCB0STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_B busy */
-/* UCB0STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCB0STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCB0STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCB0TBCNT[UCTBCNT] Bits */
-#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
-#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
-/* UCB0RXBUF[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB0RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB0TXBUF[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB0TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB0I2COA0[I2COA0] Bits */
-#define I2COA0_OFS ( 0) /* I2COA0 Offset */
-#define I2COA0_M (0x03ff) /* I2C own address */
-/* UCB0I2COA0[UCOAEN] Bits */
-#define UCOAEN_OFS (10) /* UCOAEN Offset */
-#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB0I2COA0[UCGCEN] Bits */
-#define UCGCEN_OFS (15) /* UCGCEN Offset */
-#define UCGCEN (0x8000) /* General call response enable */
-/* UCB0I2COA1[I2COA1] Bits */
-#define I2COA1_OFS ( 0) /* I2COA1 Offset */
-#define I2COA1_M (0x03ff) /* I2C own address */
-/* UCB0I2COA1[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB0I2COA2[I2COA2] Bits */
-#define I2COA2_OFS ( 0) /* I2COA2 Offset */
-#define I2COA2_M (0x03ff) /* I2C own address */
-/* UCB0I2COA2[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB0I2COA3[I2COA3] Bits */
-#define I2COA3_OFS ( 0) /* I2COA3 Offset */
-#define I2COA3_M (0x03ff) /* I2C own address */
-/* UCB0I2COA3[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB0ADDRX[ADDRX] Bits */
-#define ADDRX_OFS ( 0) /* ADDRX Offset */
-#define ADDRX_M (0x03ff) /* Received Address Register */
-/* UCB0ADDMASK[ADDMASK] Bits */
-#define ADDMASK_OFS ( 0) /* ADDMASK Offset */
-#define ADDMASK_M (0x03ff) /* */
-/* UCB0I2CSA[I2CSA] Bits */
-#define I2CSA_OFS ( 0) /* I2CSA Offset */
-#define I2CSA_M (0x03ff) /* I2C slave address */
-/* UCB0IE[UCRXIE0] Bits */
-#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
-#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
-/* UCB0IE[UCTXIE0] Bits */
-#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
-#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
-/* UCB0IE[UCSTTIE] Bits */
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */
-/* UCB0IE[UCSTPIE] Bits */
-#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
-#define UCSTPIE (0x0008) /* STOP condition interrupt enable */
-/* UCB0IE[UCALIE] Bits */
-#define UCALIE_OFS ( 4) /* UCALIE Offset */
-#define UCALIE (0x0010) /* Arbitration lost interrupt enable */
-/* UCB0IE[UCNACKIE] Bits */
-#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
-#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
-/* UCB0IE[UCBCNTIE] Bits */
-#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
-#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
-/* UCB0IE[UCCLTOIE] Bits */
-#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
-#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
-/* UCB0IE[UCRXIE1] Bits */
-#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
-#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
-/* UCB0IE[UCTXIE1] Bits */
-#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
-#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
-/* UCB0IE[UCRXIE2] Bits */
-#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
-#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
-/* UCB0IE[UCTXIE2] Bits */
-#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
-#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
-/* UCB0IE[UCRXIE3] Bits */
-#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
-#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
-/* UCB0IE[UCTXIE3] Bits */
-#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
-#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
-/* UCB0IE[UCBIT9IE] Bits */
-#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
-#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
-/* UCB0IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCB0IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCB0IFG[UCRXIFG0] Bits */
-#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
-#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
-/* UCB0IFG[UCTXIFG0] Bits */
-#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
-#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
-/* UCB0IFG[UCSTTIFG] Bits */
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */
-/* UCB0IFG[UCSTPIFG] Bits */
-#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
-#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
-/* UCB0IFG[UCALIFG] Bits */
-#define UCALIFG_OFS ( 4) /* UCALIFG Offset */
-#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
-/* UCB0IFG[UCNACKIFG] Bits */
-#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
-#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
-/* UCB0IFG[UCBCNTIFG] Bits */
-#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
-#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
-/* UCB0IFG[UCCLTOIFG] Bits */
-#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
-#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
-/* UCB0IFG[UCRXIFG1] Bits */
-#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
-#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
-/* UCB0IFG[UCTXIFG1] Bits */
-#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
-#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
-/* UCB0IFG[UCRXIFG2] Bits */
-#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
-#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
-/* UCB0IFG[UCTXIFG2] Bits */
-#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
-#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
-/* UCB0IFG[UCRXIFG3] Bits */
-#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
-#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
-/* UCB0IFG[UCTXIFG3] Bits */
-#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
-#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
-/* UCB0IFG[UCBIT9IFG] Bits */
-#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
-#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
-/* UCB0IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCB0IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
+/******************************************************************************
+* EUSCI_B Bits
+******************************************************************************/
+/* EUSCI_B_CTLW0[SWRST] Bits */
+#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */
+#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */
+/* EUSCI_B_CTLW0[TXSTT] Bits */
+#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /**< UCTXSTT Bit Offset */
+#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /**< Transmit START condition in master mode */
+/* EUSCI_B_CTLW0[TXSTP] Bits */
+#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /**< UCTXSTP Bit Offset */
+#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /**< Transmit STOP condition in master mode */
+/* EUSCI_B_CTLW0[TXNACK] Bits */
+#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /**< UCTXNACK Bit Offset */
+#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /**< Transmit a NACK */
+/* EUSCI_B_CTLW0[TR] Bits */
+#define EUSCI_B_CTLW0_TR_OFS ( 4) /**< UCTR Bit Offset */
+#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /**< Transmitter/receiver */
+/* EUSCI_B_CTLW0[TXACK] Bits */
+#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /**< UCTXACK Bit Offset */
+#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /**< Transmit ACK condition in slave mode */
+/* EUSCI_B_CTLW0[SSEL] Bits */
+#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */
+#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */
+#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */
+#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */
+#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLKI */
+#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */
+#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */
+#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /**< UCLKI */
+#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */
+#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */
+#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /**< SMCLK */
+/* EUSCI_B_CTLW0[SYNC] Bits */
+#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */
+#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */
+/* EUSCI_B_CTLW0[MODE] Bits */
+#define EUSCI_B_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */
+#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */
+#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */
+#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */
+#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /**< 3-pin SPI */
+#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /**< 4-pin SPI (master or slave enabled if STE = 1) */
+#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /**< 4-pin SPI (master or slave enabled if STE = 0) */
+#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /**< I2C mode */
+/* EUSCI_B_CTLW0[MST] Bits */
+#define EUSCI_B_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */
+#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */
+/* EUSCI_B_CTLW0[MM] Bits */
+#define EUSCI_B_CTLW0_MM_OFS (13) /**< UCMM Bit Offset */
+#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /**< Multi-master environment select */
+/* EUSCI_B_CTLW0[SLA10] Bits */
+#define EUSCI_B_CTLW0_SLA10_OFS (14) /**< UCSLA10 Bit Offset */
+#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /**< Slave addressing mode select */
+/* EUSCI_B_CTLW0[A10] Bits */
+#define EUSCI_B_CTLW0_A10_OFS (15) /**< UCA10 Bit Offset */
+#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /**< Own addressing mode select */
+/* EUSCI_B_CTLW0[STEM] Bits */
+#define EUSCI_B_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */
+#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */
+/* EUSCI_B_CTLW0[SSEL] Bits */
-//*****************************************************************************
-// EUSCI_B1 Bits
-//*****************************************************************************
-/* UCB1CTLW0[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB1CTLW0[UCTXSTT] Bits */
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */
-/* UCB1CTLW0[UCTXSTP] Bits */
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
-/* UCB1CTLW0[UCTXNACK] Bits */
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
-//#define UCTXNACK (0x0008) /* Transmit a NACK */
-/* UCB1CTLW0[UCTR] Bits */
-//#define UCTR_OFS ( 4) /* UCTR Offset */
-//#define UCTR (0x0010) /* Transmitter/receiver */
-/* UCB1CTLW0[UCTXACK] Bits */
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
-/* UCB1CTLW0[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_0 (0x0000) /* UCLKI */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-//#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB1CTLW0[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB1CTLW0[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB1CTLW0[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB1CTLW0[UCMM] Bits */
-//#define UCMM_OFS (13) /* UCMM Offset */
-//#define UCMM (0x2000) /* Multi-master environment select */
-/* UCB1CTLW0[UCSLA10] Bits */
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */
-/* UCB1CTLW0[UCA10] Bits */
-//#define UCA10_OFS (15) /* UCA10 Offset */
-//#define UCA10 (0x8000) /* Own addressing mode select */
-/* UCB1CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB1CTLW0_SPI[UCSTEM] Bits */
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCB1CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-//#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB1CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB1CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB1CTLW0_SPI[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB1CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCB1CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCB1CTLW0_SPI[UCCKPL] Bits */
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */
-//#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCB1CTLW0_SPI[UCCKPH] Bits */
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */
-//#define UCCKPH (0x8000) /* Clock phase select */
-/* UCB1CTLW1[UCGLIT] Bits */
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-//#define UCGLIT_M (0x0003) /* Deglitch time */
-//#define UCGLIT0 (0x0001) /* Deglitch time */
-//#define UCGLIT1 (0x0002) /* Deglitch time */
-//#define UCGLIT_0 (0x0000) /* 50 ns */
-//#define UCGLIT_1 (0x0001) /* 25 ns */
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */
-/* UCB1CTLW1[UCASTP] Bits */
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
-/* UCB1CTLW1[UCSWACK] Bits */
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */
-//#define UCSWACK (0x0010) /* SW or HW ACK control */
-/* UCB1CTLW1[UCSTPNACK] Bits */
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */
-/* UCB1CTLW1[UCCLTO] Bits */
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
-/* UCB1CTLW1[UCETXINT] Bits */
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */
-/* UCB1STATW[UCBBUSY] Bits */
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
-//#define UCBBUSY (0x0010) /* Bus busy */
-/* UCB1STATW[UCGC] Bits */
-//#define UCGC_OFS ( 5) /* UCGC Offset */
-//#define UCGC (0x0020) /* General call address received */
-/* UCB1STATW[UCSCLLOW] Bits */
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
-//#define UCSCLLOW (0x0040) /* SCL low */
-/* UCB1STATW[UCBCNT] Bits */
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */
-/* UCB1STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_B busy */
-/* UCB1STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCB1STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCB1STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCB1TBCNT[UCTBCNT] Bits */
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
-/* UCB1RXBUF[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB1RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB1TXBUF[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB1TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB1I2COA0[I2COA0] Bits */
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */
-//#define I2COA0_M (0x03ff) /* I2C own address */
-/* UCB1I2COA0[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB1I2COA0[UCGCEN] Bits */
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */
-//#define UCGCEN (0x8000) /* General call response enable */
-/* UCB1I2COA1[I2COA1] Bits */
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */
-//#define I2COA1_M (0x03ff) /* I2C own address */
-/* UCB1I2COA1[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB1I2COA2[I2COA2] Bits */
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */
-//#define I2COA2_M (0x03ff) /* I2C own address */
-/* UCB1I2COA2[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB1I2COA3[I2COA3] Bits */
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */
-//#define I2COA3_M (0x03ff) /* I2C own address */
-/* UCB1I2COA3[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB1ADDRX[ADDRX] Bits */
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */
-//#define ADDRX_M (0x03ff) /* Received Address Register */
-/* UCB1ADDMASK[ADDMASK] Bits */
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */
-//#define ADDMASK_M (0x03ff) /* */
-/* UCB1I2CSA[I2CSA] Bits */
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */
-//#define I2CSA_M (0x03ff) /* I2C slave address */
-/* UCB1IE[UCRXIE0] Bits */
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
-/* UCB1IE[UCTXIE0] Bits */
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
-/* UCB1IE[UCSTTIE] Bits */
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */
-/* UCB1IE[UCSTPIE] Bits */
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */
-/* UCB1IE[UCALIE] Bits */
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */
-/* UCB1IE[UCNACKIE] Bits */
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
-/* UCB1IE[UCBCNTIE] Bits */
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
-/* UCB1IE[UCCLTOIE] Bits */
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
-/* UCB1IE[UCRXIE1] Bits */
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
-/* UCB1IE[UCTXIE1] Bits */
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
-/* UCB1IE[UCRXIE2] Bits */
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
-/* UCB1IE[UCTXIE2] Bits */
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
-/* UCB1IE[UCRXIE3] Bits */
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
-/* UCB1IE[UCTXIE3] Bits */
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
-/* UCB1IE[UCBIT9IE] Bits */
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
-/* UCB1IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCB1IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCB1IFG[UCRXIFG0] Bits */
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
-/* UCB1IFG[UCTXIFG0] Bits */
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
-/* UCB1IFG[UCSTTIFG] Bits */
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */
-/* UCB1IFG[UCSTPIFG] Bits */
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
-/* UCB1IFG[UCALIFG] Bits */
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
-/* UCB1IFG[UCNACKIFG] Bits */
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
-/* UCB1IFG[UCBCNTIFG] Bits */
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
-/* UCB1IFG[UCCLTOIFG] Bits */
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
-/* UCB1IFG[UCRXIFG1] Bits */
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
-/* UCB1IFG[UCTXIFG1] Bits */
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
-/* UCB1IFG[UCRXIFG2] Bits */
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
-/* UCB1IFG[UCTXIFG2] Bits */
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
-/* UCB1IFG[UCRXIFG3] Bits */
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
-/* UCB1IFG[UCTXIFG3] Bits */
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
-/* UCB1IFG[UCBIT9IFG] Bits */
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
-/* UCB1IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCB1IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
+#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */
-//*****************************************************************************
-// EUSCI_B2 Bits
-//*****************************************************************************
-/* UCB2CTLW0[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB2CTLW0[UCTXSTT] Bits */
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */
-/* UCB2CTLW0[UCTXSTP] Bits */
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
-/* UCB2CTLW0[UCTXNACK] Bits */
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
-//#define UCTXNACK (0x0008) /* Transmit a NACK */
-/* UCB2CTLW0[UCTR] Bits */
-//#define UCTR_OFS ( 4) /* UCTR Offset */
-//#define UCTR (0x0010) /* Transmitter/receiver */
-/* UCB2CTLW0[UCTXACK] Bits */
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
-/* UCB2CTLW0[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_0 (0x0000) /* UCLKI */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-//#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB2CTLW0[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB2CTLW0[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB2CTLW0[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB2CTLW0[UCMM] Bits */
-//#define UCMM_OFS (13) /* UCMM Offset */
-//#define UCMM (0x2000) /* Multi-master environment select */
-/* UCB2CTLW0[UCSLA10] Bits */
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */
-/* UCB2CTLW0[UCA10] Bits */
-//#define UCA10_OFS (15) /* UCA10 Offset */
-//#define UCA10 (0x8000) /* Own addressing mode select */
-/* UCB2CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB2CTLW0_SPI[UCSTEM] Bits */
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCB2CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-//#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB2CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB2CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB2CTLW0_SPI[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB2CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCB2CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCB2CTLW0_SPI[UCCKPL] Bits */
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */
-//#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCB2CTLW0_SPI[UCCKPH] Bits */
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */
-//#define UCCKPH (0x8000) /* Clock phase select */
-/* UCB2CTLW1[UCGLIT] Bits */
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-//#define UCGLIT_M (0x0003) /* Deglitch time */
-//#define UCGLIT0 (0x0001) /* Deglitch time */
-//#define UCGLIT1 (0x0002) /* Deglitch time */
-//#define UCGLIT_0 (0x0000) /* 50 ns */
-//#define UCGLIT_1 (0x0001) /* 25 ns */
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */
-/* UCB2CTLW1[UCASTP] Bits */
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
-/* UCB2CTLW1[UCSWACK] Bits */
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */
-//#define UCSWACK (0x0010) /* SW or HW ACK control */
-/* UCB2CTLW1[UCSTPNACK] Bits */
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */
-/* UCB2CTLW1[UCCLTO] Bits */
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
-/* UCB2CTLW1[UCETXINT] Bits */
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */
-/* UCB2STATW[UCBBUSY] Bits */
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
-//#define UCBBUSY (0x0010) /* Bus busy */
-/* UCB2STATW[UCGC] Bits */
-//#define UCGC_OFS ( 5) /* UCGC Offset */
-//#define UCGC (0x0020) /* General call address received */
-/* UCB2STATW[UCSCLLOW] Bits */
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
-//#define UCSCLLOW (0x0040) /* SCL low */
-/* UCB2STATW[UCBCNT] Bits */
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */
-/* UCB2STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_B busy */
-/* UCB2STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCB2STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCB2STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCB2TBCNT[UCTBCNT] Bits */
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
-/* UCB2RXBUF[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB2RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB2TXBUF[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB2TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB2I2COA0[I2COA0] Bits */
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */
-//#define I2COA0_M (0x03ff) /* I2C own address */
-/* UCB2I2COA0[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB2I2COA0[UCGCEN] Bits */
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */
-//#define UCGCEN (0x8000) /* General call response enable */
-/* UCB2I2COA1[I2COA1] Bits */
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */
-//#define I2COA1_M (0x03ff) /* I2C own address */
-/* UCB2I2COA1[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB2I2COA2[I2COA2] Bits */
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */
-//#define I2COA2_M (0x03ff) /* I2C own address */
-/* UCB2I2COA2[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB2I2COA3[I2COA3] Bits */
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */
-//#define I2COA3_M (0x03ff) /* I2C own address */
-/* UCB2I2COA3[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB2ADDRX[ADDRX] Bits */
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */
-//#define ADDRX_M (0x03ff) /* Received Address Register */
-/* UCB2ADDMASK[ADDMASK] Bits */
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */
-//#define ADDMASK_M (0x03ff) /* */
-/* UCB2I2CSA[I2CSA] Bits */
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */
-//#define I2CSA_M (0x03ff) /* I2C slave address */
-/* UCB2IE[UCRXIE0] Bits */
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
-/* UCB2IE[UCTXIE0] Bits */
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
-/* UCB2IE[UCSTTIE] Bits */
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */
-/* UCB2IE[UCSTPIE] Bits */
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */
-/* UCB2IE[UCALIE] Bits */
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */
-/* UCB2IE[UCNACKIE] Bits */
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
-/* UCB2IE[UCBCNTIE] Bits */
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
-/* UCB2IE[UCCLTOIE] Bits */
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
-/* UCB2IE[UCRXIE1] Bits */
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
-/* UCB2IE[UCTXIE1] Bits */
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
-/* UCB2IE[UCRXIE2] Bits */
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
-/* UCB2IE[UCTXIE2] Bits */
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
-/* UCB2IE[UCRXIE3] Bits */
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
-/* UCB2IE[UCTXIE3] Bits */
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
-/* UCB2IE[UCBIT9IE] Bits */
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
-/* UCB2IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCB2IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCB2IFG[UCRXIFG0] Bits */
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
-/* UCB2IFG[UCTXIFG0] Bits */
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
-/* UCB2IFG[UCSTTIFG] Bits */
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */
-/* UCB2IFG[UCSTPIFG] Bits */
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
-/* UCB2IFG[UCALIFG] Bits */
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
-/* UCB2IFG[UCNACKIFG] Bits */
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
-/* UCB2IFG[UCBCNTIFG] Bits */
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
-/* UCB2IFG[UCCLTOIFG] Bits */
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
-/* UCB2IFG[UCRXIFG1] Bits */
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
-/* UCB2IFG[UCTXIFG1] Bits */
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
-/* UCB2IFG[UCRXIFG2] Bits */
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
-/* UCB2IFG[UCTXIFG2] Bits */
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
-/* UCB2IFG[UCRXIFG3] Bits */
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
-/* UCB2IFG[UCTXIFG3] Bits */
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
-/* UCB2IFG[UCBIT9IFG] Bits */
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
-/* UCB2IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCB2IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
+
+/* EUSCI_B_CTLW0[MODE] Bits */
-//*****************************************************************************
-// EUSCI_B3 Bits
-//*****************************************************************************
-/* UCB3CTLW0[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB3CTLW0[UCTXSTT] Bits */
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */
-/* UCB3CTLW0[UCTXSTP] Bits */
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
-/* UCB3CTLW0[UCTXNACK] Bits */
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
-//#define UCTXNACK (0x0008) /* Transmit a NACK */
-/* UCB3CTLW0[UCTR] Bits */
-//#define UCTR_OFS ( 4) /* UCTR Offset */
-//#define UCTR (0x0010) /* Transmitter/receiver */
-/* UCB3CTLW0[UCTXACK] Bits */
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
-/* UCB3CTLW0[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_0 (0x0000) /* UCLKI */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-//#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB3CTLW0[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB3CTLW0[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB3CTLW0[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB3CTLW0[UCMM] Bits */
-//#define UCMM_OFS (13) /* UCMM Offset */
-//#define UCMM (0x2000) /* Multi-master environment select */
-/* UCB3CTLW0[UCSLA10] Bits */
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */
-/* UCB3CTLW0[UCA10] Bits */
-//#define UCA10_OFS (15) /* UCA10 Offset */
-//#define UCA10 (0x8000) /* Own addressing mode select */
-/* UCB3CTLW0_SPI[UCSWRST] Bits */
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
-//#define UCSWRST (0x0001) /* Software reset enable */
-/* UCB3CTLW0_SPI[UCSTEM] Bits */
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */
-/* UCB3CTLW0_SPI[UCSSEL] Bits */
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
-//#define UCSSEL_1 (0x0040) /* ACLK */
-//#define UCSSEL_2 (0x0080) /* SMCLK */
-//#define UCSSEL_0 (0x0000) /* Reserved */
-//#define UCSSEL__ACLK (0x0040) /* ACLK */
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */
-//#define UCSSEL_3 (0x00c0) /* SMCLK */
-/* UCB3CTLW0_SPI[UCSYNC] Bits */
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
-//#define UCSYNC (0x0100) /* Synchronous mode enable */
-/* UCB3CTLW0_SPI[UCMODE] Bits */
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */
-//#define UCMODE_M (0x0600) /* eUSCI mode */
-//#define UCMODE0 (0x0200) /* eUSCI mode */
-//#define UCMODE1 (0x0400) /* eUSCI mode */
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
-//#define UCMODE_3 (0x0600) /* I2C mode */
-/* UCB3CTLW0_SPI[UCMST] Bits */
-//#define UCMST_OFS (11) /* UCMST Offset */
-//#define UCMST (0x0800) /* Master mode select */
-/* UCB3CTLW0_SPI[UC7BIT] Bits */
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */
-//#define UC7BIT (0x1000) /* Character length */
-/* UCB3CTLW0_SPI[UCMSB] Bits */
-//#define UCMSB_OFS (13) /* UCMSB Offset */
-//#define UCMSB (0x2000) /* MSB first select */
-/* UCB3CTLW0_SPI[UCCKPL] Bits */
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */
-//#define UCCKPL (0x4000) /* Clock polarity select */
-/* UCB3CTLW0_SPI[UCCKPH] Bits */
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */
-//#define UCCKPH (0x8000) /* Clock phase select */
-/* UCB3CTLW1[UCGLIT] Bits */
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
-//#define UCGLIT_M (0x0003) /* Deglitch time */
-//#define UCGLIT0 (0x0001) /* Deglitch time */
-//#define UCGLIT1 (0x0002) /* Deglitch time */
-//#define UCGLIT_0 (0x0000) /* 50 ns */
-//#define UCGLIT_1 (0x0001) /* 25 ns */
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */
-/* UCB3CTLW1[UCASTP] Bits */
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
-/* UCB3CTLW1[UCSWACK] Bits */
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */
-//#define UCSWACK (0x0010) /* SW or HW ACK control */
-/* UCB3CTLW1[UCSTPNACK] Bits */
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */
-/* UCB3CTLW1[UCCLTO] Bits */
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
-/* UCB3CTLW1[UCETXINT] Bits */
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */
-/* UCB3STATW[UCBBUSY] Bits */
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
-//#define UCBBUSY (0x0010) /* Bus busy */
-/* UCB3STATW[UCGC] Bits */
-//#define UCGC_OFS ( 5) /* UCGC Offset */
-//#define UCGC (0x0020) /* General call address received */
-/* UCB3STATW[UCSCLLOW] Bits */
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
-//#define UCSCLLOW (0x0040) /* SCL low */
-/* UCB3STATW[UCBCNT] Bits */
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */
-/* UCB3STATW_SPI[UCBUSY] Bits */
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
-//#define UCBUSY (0x0001) /* eUSCI_B busy */
-/* UCB3STATW_SPI[UCOE] Bits */
-//#define UCOE_OFS ( 5) /* UCOE Offset */
-//#define UCOE (0x0020) /* Overrun error flag */
-/* UCB3STATW_SPI[UCFE] Bits */
-//#define UCFE_OFS ( 6) /* UCFE Offset */
-//#define UCFE (0x0040) /* Framing error flag */
-/* UCB3STATW_SPI[UCLISTEN] Bits */
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
-//#define UCLISTEN (0x0080) /* Listen enable */
-/* UCB3TBCNT[UCTBCNT] Bits */
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
-/* UCB3RXBUF[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB3RXBUF_SPI[UCRXBUF] Bits */
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */
-/* UCB3TXBUF[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB3TXBUF_SPI[UCTXBUF] Bits */
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
-/* UCB3I2COA0[I2COA0] Bits */
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */
-//#define I2COA0_M (0x03ff) /* I2C own address */
-/* UCB3I2COA0[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB3I2COA0[UCGCEN] Bits */
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */
-//#define UCGCEN (0x8000) /* General call response enable */
-/* UCB3I2COA1[I2COA1] Bits */
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */
-//#define I2COA1_M (0x03ff) /* I2C own address */
-/* UCB3I2COA1[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB3I2COA2[I2COA2] Bits */
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */
-//#define I2COA2_M (0x03ff) /* I2C own address */
-/* UCB3I2COA2[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB3I2COA3[I2COA3] Bits */
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */
-//#define I2COA3_M (0x03ff) /* I2C own address */
-/* UCB3I2COA3[UCOAEN] Bits */
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */
-//#define UCOAEN (0x0400) /* Own Address enable register */
-/* UCB3ADDRX[ADDRX] Bits */
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */
-//#define ADDRX_M (0x03ff) /* Received Address Register */
-/* UCB3ADDMASK[ADDMASK] Bits */
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */
-//#define ADDMASK_M (0x03ff) /* */
-/* UCB3I2CSA[I2CSA] Bits */
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */
-//#define I2CSA_M (0x03ff) /* I2C slave address */
-/* UCB3IE[UCRXIE0] Bits */
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
-/* UCB3IE[UCTXIE0] Bits */
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
-/* UCB3IE[UCSTTIE] Bits */
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */
-/* UCB3IE[UCSTPIE] Bits */
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */
-/* UCB3IE[UCALIE] Bits */
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */
-/* UCB3IE[UCNACKIE] Bits */
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
-/* UCB3IE[UCBCNTIE] Bits */
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
-/* UCB3IE[UCCLTOIE] Bits */
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
-/* UCB3IE[UCRXIE1] Bits */
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
-/* UCB3IE[UCTXIE1] Bits */
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
-/* UCB3IE[UCRXIE2] Bits */
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
-/* UCB3IE[UCTXIE2] Bits */
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
-/* UCB3IE[UCRXIE3] Bits */
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
-/* UCB3IE[UCTXIE3] Bits */
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
-/* UCB3IE[UCBIT9IE] Bits */
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
-/* UCB3IE_SPI[UCRXIE] Bits */
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
-//#define UCRXIE (0x0001) /* Receive interrupt enable */
-/* UCB3IE_SPI[UCTXIE] Bits */
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */
-/* UCB3IFG[UCRXIFG0] Bits */
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
-/* UCB3IFG[UCTXIFG0] Bits */
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
-/* UCB3IFG[UCSTTIFG] Bits */
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */
-/* UCB3IFG[UCSTPIFG] Bits */
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
-/* UCB3IFG[UCALIFG] Bits */
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
-/* UCB3IFG[UCNACKIFG] Bits */
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
-/* UCB3IFG[UCBCNTIFG] Bits */
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
-/* UCB3IFG[UCCLTOIFG] Bits */
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
-/* UCB3IFG[UCRXIFG1] Bits */
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
-/* UCB3IFG[UCTXIFG1] Bits */
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
-/* UCB3IFG[UCRXIFG2] Bits */
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
-/* UCB3IFG[UCTXIFG2] Bits */
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
-/* UCB3IFG[UCRXIFG3] Bits */
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
-/* UCB3IFG[UCTXIFG3] Bits */
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
-/* UCB3IFG[UCBIT9IFG] Bits */
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
-/* UCB3IFG_SPI[UCRXIFG] Bits */
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */
-/* UCB3IFG_SPI[UCTXIFG] Bits */
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */
-//*****************************************************************************
-// FLCTL Bits
-//*****************************************************************************
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_PSTAT] Bits */
-#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /* PSTAT Offset */
-#define FLCTL_POWER_STAT_PSTAT_M (0x00000007) /* */
-#define FLCTL_POWER_STAT_PSTAT0 (0x00000001) /* */
-#define FLCTL_POWER_STAT_PSTAT1 (0x00000002) /* */
-#define FLCTL_POWER_STAT_PSTAT2 (0x00000004) /* */
-#define FLCTL_POWER_STAT_PSTAT_0 (0x00000000) /* Flash IP in power-down mode */
-#define FLCTL_POWER_STAT_PSTAT_1 (0x00000001) /* Flash IP Vdd domain power-up in progress */
-#define FLCTL_POWER_STAT_PSTAT_2 (0x00000002) /* PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
-#define FLCTL_POWER_STAT_PSTAT_3 (0x00000003) /* Flash IP SAFE_LV check in progress */
-#define FLCTL_POWER_STAT_PSTAT_4 (0x00000004) /* Flash IP Active */
-#define FLCTL_POWER_STAT_PSTAT_5 (0x00000005) /* Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
-#define FLCTL_POWER_STAT_PSTAT_6 (0x00000006) /* Flash IP in Standby mode */
-#define FLCTL_POWER_STAT_PSTAT_7 (0x00000007) /* Flash IP in Current mirror boost state */
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_LDOSTAT] Bits */
-#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /* LDOSTAT Offset */
-#define FLCTL_POWER_STAT_LDOSTAT (0x00000008) /* PSS FLDO GOOD status */
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_VREFSTAT] Bits */
-#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /* VREFSTAT Offset */
-#define FLCTL_POWER_STAT_VREFSTAT (0x00000010) /* PSS VREF stable status */
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_IREFSTAT] Bits */
-#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /* IREFSTAT Offset */
-#define FLCTL_POWER_STAT_IREFSTAT (0x00000020) /* PSS IREF stable status */
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_TRIMSTAT] Bits */
-#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /* TRIMSTAT Offset */
-#define FLCTL_POWER_STAT_TRIMSTAT (0x00000040) /* PSS trim done status */
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_RD_2T] Bits */
-#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /* RD_2T Offset */
-#define FLCTL_POWER_STAT_RD_2T (0x00000080) /* Indicates if Flash is being accessed in 2T mode */
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE] Bits */
-#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */
-#define FLCTL_BANK0_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK0_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK0_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK0_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK0_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK0_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */
-#define FLCTL_BANK0_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */
-#define FLCTL_BANK0_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */
-#define FLCTL_BANK0_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */
-#define FLCTL_BANK0_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */
-#define FLCTL_BANK0_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */
-#define FLCTL_BANK0_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */
-#define FLCTL_BANK0_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFI] Bits */
-#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */
-#define FLCTL_BANK0_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFD] Bits */
-#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */
-#define FLCTL_BANK0_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_WAIT] Bits */
-#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /* WAIT Offset */
-#define FLCTL_BANK0_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */
-#define FLCTL_BANK0_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */
-#define FLCTL_BANK0_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */
-#define FLCTL_BANK0_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */
-#define FLCTL_BANK0_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */
-#define FLCTL_BANK0_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */
-#define FLCTL_BANK0_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE_STATUS] Bits */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE] Bits */
-#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */
-#define FLCTL_BANK1_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK1_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK1_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK1_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK1_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */
-#define FLCTL_BANK1_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */
-#define FLCTL_BANK1_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */
-#define FLCTL_BANK1_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */
-#define FLCTL_BANK1_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */
-#define FLCTL_BANK1_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */
-#define FLCTL_BANK1_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */
-#define FLCTL_BANK1_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */
-#define FLCTL_BANK1_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFI] Bits */
-#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */
-#define FLCTL_BANK1_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFD] Bits */
-#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */
-#define FLCTL_BANK1_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE_STATUS] Bits */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_WAIT] Bits */
-#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /* WAIT Offset */
-#define FLCTL_BANK1_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */
-#define FLCTL_BANK1_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */
-#define FLCTL_BANK1_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */
-#define FLCTL_BANK1_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */
-#define FLCTL_BANK1_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */
-#define FLCTL_BANK1_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */
-#define FLCTL_BANK1_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_START] Bits */
-#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /* START Offset */
-#define FLCTL_RDBRST_CTLSTAT_START (0x00000001) /* Start of burst/compare operation */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_MEM_TYPE] Bits */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /* MEM_TYPE Offset */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M (0x00000006) /* Type of memory that burst is carried out on */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 (0x00000002) /* Type of memory that burst is carried out on */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 (0x00000004) /* Type of memory that burst is carried out on */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 (0x00000000) /* Main Memory */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 (0x00000002) /* Information Memory */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 (0x00000004) /* Reserved */
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 (0x00000006) /* Engineering Memory */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_STOP_FAIL] Bits */
-#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /* STOP_FAIL Offset */
-#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL (0x00000008) /* Terminate burst/compare operation */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_DATA_CMP] Bits */
-#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /* DATA_CMP Offset */
-#define FLCTL_RDBRST_CTLSTAT_DATA_CMP (0x00000010) /* Data pattern used for comparison against memory read data */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_TEST_EN] Bits */
-#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /* TEST_EN Offset */
-#define FLCTL_RDBRST_CTLSTAT_TEST_EN (0x00000040) /* Enable comparison against test data compare registers */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_BRST_STAT] Bits */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /* BRST_STAT Offset */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_M (0x00030000) /* Status of Burst/Compare operation */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 (0x00010000) /* Status of Burst/Compare operation */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 (0x00020000) /* Status of Burst/Compare operation */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 (0x00000000) /* Idle */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 (0x00010000) /* Burst/Compare START bit written, but operation pending */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 (0x00020000) /* Burst/Compare in progress */
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 (0x00030000) /* Burst complete (status of completed burst remains in this state unless explicitly cleared by SW) */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CMP_ERR] Bits */
-#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /* CMP_ERR Offset */
-#define FLCTL_RDBRST_CTLSTAT_CMP_ERR (0x00040000) /* Burst/Compare Operation encountered atleast one data */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_ADDR_ERR] Bits */
-#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /* ADDR_ERR Offset */
-#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR (0x00080000) /* Burst/Compare Operation was terminated due to access to */
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CLR_STAT] Bits */
-#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */
-#define FLCTL_RDBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 19-16 of this register */
-/* FLCTL_RDBRST_STARTADDR[FLCTL_RDBRST_STARTADDR_START_ADDRESS] Bits */
-#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */
-#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_M (0x001fffff) /* Start Address of Burst Operation */
-/* FLCTL_RDBRST_LEN[FLCTL_RDBRST_LEN_BURST_LENGTH] Bits */
-#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /* BURST_LENGTH Offset */
-#define FLCTL_RDBRST_LEN_BURST_LENGTH_M (0x001fffff) /* Length of Burst Operation */
-/* FLCTL_RDBRST_FAILADDR[FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS] Bits */
-#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /* FAIL_ADDRESS Offset */
-#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_M (0x001fffff) /* Reflects address of last failed compare */
-/* FLCTL_RDBRST_FAILCNT[FLCTL_RDBRST_FAILCNT_FAIL_COUNT] Bits */
-#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /* FAIL_COUNT Offset */
-#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_M (0x0001ffff) /* Number of failures encountered in burst operation */
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_ENABLE] Bits */
-#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FLCTL_PRG_CTLSTAT_ENABLE (0x00000001) /* Master control for all word program operations */
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_MODE] Bits */
-#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */
-#define FLCTL_PRG_CTLSTAT_MODE (0x00000002) /* Write mode */
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PRE] Bits */
-#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /* VER_PRE Offset */
-#define FLCTL_PRG_CTLSTAT_VER_PRE (0x00000004) /* Controls automatic pre program verify operations */
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PST] Bits */
-#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /* VER_PST Offset */
-#define FLCTL_PRG_CTLSTAT_VER_PST (0x00000008) /* Controls automatic post program verify operations */
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_STATUS] Bits */
-#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */
-#define FLCTL_PRG_CTLSTAT_STATUS_M (0x00030000) /* Status of program operations in the Flash memory */
-#define FLCTL_PRG_CTLSTAT_STATUS0 (0x00010000) /* Status of program operations in the Flash memory */
-#define FLCTL_PRG_CTLSTAT_STATUS1 (0x00020000) /* Status of program operations in the Flash memory */
-#define FLCTL_PRG_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */
-#define FLCTL_PRG_CTLSTAT_STATUS_1 (0x00010000) /* Single word program operation triggered, but pending */
-#define FLCTL_PRG_CTLSTAT_STATUS_2 (0x00020000) /* Single word program in progress */
-#define FLCTL_PRG_CTLSTAT_STATUS_3 (0x00030000) /* Reserved (Idle) */
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_BNK_ACT] Bits */
-#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /* BNK_ACT Offset */
-#define FLCTL_PRG_CTLSTAT_BNK_ACT (0x00040000) /* Bank active */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_START] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /* START Offset */
-#define FLCTL_PRGBRST_CTLSTAT_START (0x00000001) /* Trigger start of burst program operation */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_TYPE] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /* TYPE Offset */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_M (0x00000006) /* Type of memory that burst program is carried out on */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE0 (0x00000002) /* Type of memory that burst program is carried out on */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE1 (0x00000004) /* Type of memory that burst program is carried out on */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 (0x00000002) /* Information Memory */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 (0x00000004) /* Reserved */
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 (0x00000006) /* Engineering Memory */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_LEN] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /* LEN Offset */
-#define FLCTL_PRGBRST_CTLSTAT_LEN_M (0x00000038) /* Length of burst */
-#define FLCTL_PRGBRST_CTLSTAT_LEN0 (0x00000008) /* Length of burst */
-#define FLCTL_PRGBRST_CTLSTAT_LEN1 (0x00000010) /* Length of burst */
-#define FLCTL_PRGBRST_CTLSTAT_LEN2 (0x00000020) /* Length of burst */
-#define FLCTL_PRGBRST_CTLSTAT_LEN_0 (0x00000000) /* No burst operation */
-#define FLCTL_PRGBRST_CTLSTAT_LEN_1 (0x00000008) /* 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
-#define FLCTL_PRGBRST_CTLSTAT_LEN_2 (0x00000010) /* 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
-#define FLCTL_PRGBRST_CTLSTAT_LEN_3 (0x00000018) /* 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
-#define FLCTL_PRGBRST_CTLSTAT_LEN_4 (0x00000020) /* 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PRE] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /* AUTO_PRE Offset */
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE (0x00000040) /* Auto-Verify operation before the Burst Program */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PST] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /* AUTO_PST Offset */
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST (0x00000080) /* Auto-Verify operation after the Burst Program */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_BURST_STATUS] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /* BURST_STATUS Offset */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_M (0x00070000) /* Status of a Burst Operation */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 (0x00010000) /* Status of a Burst Operation */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 (0x00020000) /* Status of a Burst Operation */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 (0x00040000) /* Status of a Burst Operation */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 (0x00000000) /* Idle (Burst not active) */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 (0x00010000) /* Burst program started but pending */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 (0x00020000) /* Burst active, with 1st 128 bit word being written into Flash */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 (0x00030000) /* Burst active, with 2nd 128 bit word being written into Flash */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 (0x00040000) /* Burst active, with 3rd 128 bit word being written into Flash */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 (0x00050000) /* Burst active, with 4th 128 bit word being written into Flash */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 (0x00060000) /* Reserved (Idle) */
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 (0x00070000) /* Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW) */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PRE_ERR] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /* PRE_ERR Offset */
-#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR (0x00080000) /* Burst Operation encountered preprogram auto-verify errors */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PST_ERR] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /* PST_ERR Offset */
-#define FLCTL_PRGBRST_CTLSTAT_PST_ERR (0x00100000) /* Burst Operation encountered postprogram auto-verify errors */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_ADDR_ERR] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /* ADDR_ERR Offset */
-#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR (0x00200000) /* Burst Operation was terminated due to attempted program of reserved memory */
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_CLR_STAT] Bits */
-#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */
-#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 21-16 of this register */
-/* FLCTL_PRGBRST_STARTADDR[FLCTL_PRGBRST_STARTADDR_START_ADDRESS] Bits */
-#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */
-#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_M (0x003fffff) /* Start Address of Program Burst Operation */
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_START] Bits */
-#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /* START Offset */
-#define FLCTL_ERASE_CTLSTAT_START (0x00000001) /* Start of Erase operation */
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_MODE] Bits */
-#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */
-#define FLCTL_ERASE_CTLSTAT_MODE (0x00000002) /* Erase mode selected by application */
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_TYPE] Bits */
-#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /* TYPE Offset */
-#define FLCTL_ERASE_CTLSTAT_TYPE_M (0x0000000c) /* Type of memory that erase operation is carried out on */
-#define FLCTL_ERASE_CTLSTAT_TYPE0 (0x00000004) /* Type of memory that erase operation is carried out on */
-#define FLCTL_ERASE_CTLSTAT_TYPE1 (0x00000008) /* Type of memory that erase operation is carried out on */
-#define FLCTL_ERASE_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */
-#define FLCTL_ERASE_CTLSTAT_TYPE_1 (0x00000004) /* Information Memory */
-#define FLCTL_ERASE_CTLSTAT_TYPE_2 (0x00000008) /* Reserved */
-#define FLCTL_ERASE_CTLSTAT_TYPE_3 (0x0000000c) /* Engineering Memory */
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_STATUS] Bits */
-#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */
-#define FLCTL_ERASE_CTLSTAT_STATUS_M (0x00030000) /* Status of erase operations in the Flash memory */
-#define FLCTL_ERASE_CTLSTAT_STATUS0 (0x00010000) /* Status of erase operations in the Flash memory */
-#define FLCTL_ERASE_CTLSTAT_STATUS1 (0x00020000) /* Status of erase operations in the Flash memory */
-#define FLCTL_ERASE_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */
-#define FLCTL_ERASE_CTLSTAT_STATUS_1 (0x00010000) /* Erase operation triggered to START but pending */
-#define FLCTL_ERASE_CTLSTAT_STATUS_2 (0x00020000) /* Erase operation in progress */
-#define FLCTL_ERASE_CTLSTAT_STATUS_3 (0x00030000) /* Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW) */
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_ADDR_ERR] Bits */
-#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /* ADDR_ERR Offset */
-#define FLCTL_ERASE_CTLSTAT_ADDR_ERR (0x00040000) /* Erase Operation was terminated due to attempted erase of reserved memory address */
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_CLR_STAT] Bits */
-#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /* CLR_STAT Offset */
-#define FLCTL_ERASE_CTLSTAT_CLR_STAT (0x00080000) /* Clear status bits 18-16 of this register */
-/* FLCTL_ERASE_SECTADDR[FLCTL_ERASE_SECTADDR_SECT_ADDRESS] Bits */
-#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /* SECT_ADDRESS Offset */
-#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_M (0x003fffff) /* Address of Sector being Erased */
-/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT0] Bits */
-#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
-#define FLCTL_BANK0_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */
-/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT1] Bits */
-#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
-#define FLCTL_BANK0_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT0] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT1] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT2] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT3] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT4] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT5] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT6] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT7] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT8] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT9] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT10] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT11] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT12] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT13] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT14] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT15] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT16] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT17] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT18] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT19] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT20] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT21] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT22] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT23] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT24] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT25] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT26] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT27] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT28] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT29] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT30] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase */
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT31] Bits */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */
-#define FLCTL_BANK0_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase */
-/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT0] Bits */
-#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
-#define FLCTL_BANK1_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */
-/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT1] Bits */
-#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
-#define FLCTL_BANK1_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT0] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT1] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT2] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT3] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT4] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT5] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT6] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT7] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT8] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT9] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT10] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT11] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT12] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT13] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT14] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT15] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT16] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT17] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT18] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT19] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT20] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT21] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT22] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT23] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT24] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT25] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT26] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT27] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT28] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT29] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT30] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase operations */
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT31] Bits */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */
-#define FLCTL_BANK1_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase operations */
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_I_BMRK] Bits */
-#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /* I_BMRK Offset */
-#define FLCTL_BMRK_CTLSTAT_I_BMRK (0x00000001) /* */
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_D_BMRK] Bits */
-#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /* D_BMRK Offset */
-#define FLCTL_BMRK_CTLSTAT_D_BMRK (0x00000002) /* */
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_EN] Bits */
-#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /* CMP_EN Offset */
-#define FLCTL_BMRK_CTLSTAT_CMP_EN (0x00000004) /* */
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_SEL] Bits */
-#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /* CMP_SEL Offset */
-#define FLCTL_BMRK_CTLSTAT_CMP_SEL (0x00000008) /* */
-/* FLCTL_IFG[FLCTL_IFG_RDBRST] Bits */
-#define FLCTL_IFG_RDBRST_OFS ( 0) /* RDBRST Offset */
-#define FLCTL_IFG_RDBRST (0x00000001) /* */
-/* FLCTL_IFG[FLCTL_IFG_AVPRE] Bits */
-#define FLCTL_IFG_AVPRE_OFS ( 1) /* AVPRE Offset */
-#define FLCTL_IFG_AVPRE (0x00000002) /* */
-/* FLCTL_IFG[FLCTL_IFG_AVPST] Bits */
-#define FLCTL_IFG_AVPST_OFS ( 2) /* AVPST Offset */
-#define FLCTL_IFG_AVPST (0x00000004) /* */
-/* FLCTL_IFG[FLCTL_IFG_PRG] Bits */
-#define FLCTL_IFG_PRG_OFS ( 3) /* PRG Offset */
-#define FLCTL_IFG_PRG (0x00000008) /* */
-/* FLCTL_IFG[FLCTL_IFG_PRGB] Bits */
-#define FLCTL_IFG_PRGB_OFS ( 4) /* PRGB Offset */
-#define FLCTL_IFG_PRGB (0x00000010) /* */
-/* FLCTL_IFG[FLCTL_IFG_ERASE] Bits */
-#define FLCTL_IFG_ERASE_OFS ( 5) /* ERASE Offset */
-#define FLCTL_IFG_ERASE (0x00000020) /* */
-/* FLCTL_IFG[FLCTL_IFG_BMRK] Bits */
-#define FLCTL_IFG_BMRK_OFS ( 8) /* BMRK Offset */
-#define FLCTL_IFG_BMRK (0x00000100) /* */
-/* FLCTL_IFG[FLCTL_IFG_PRG_ERR] Bits */
-#define FLCTL_IFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
-#define FLCTL_IFG_PRG_ERR (0x00000200) /* */
-/* FLCTL_IE[FLCTL_IE_RDBRST] Bits */
-#define FLCTL_IE_RDBRST_OFS ( 0) /* RDBRST Offset */
-#define FLCTL_IE_RDBRST (0x00000001) /* */
-/* FLCTL_IE[FLCTL_IE_AVPRE] Bits */
-#define FLCTL_IE_AVPRE_OFS ( 1) /* AVPRE Offset */
-#define FLCTL_IE_AVPRE (0x00000002) /* */
-/* FLCTL_IE[FLCTL_IE_AVPST] Bits */
-#define FLCTL_IE_AVPST_OFS ( 2) /* AVPST Offset */
-#define FLCTL_IE_AVPST (0x00000004) /* */
-/* FLCTL_IE[FLCTL_IE_PRG] Bits */
-#define FLCTL_IE_PRG_OFS ( 3) /* PRG Offset */
-#define FLCTL_IE_PRG (0x00000008) /* */
-/* FLCTL_IE[FLCTL_IE_PRGB] Bits */
-#define FLCTL_IE_PRGB_OFS ( 4) /* PRGB Offset */
-#define FLCTL_IE_PRGB (0x00000010) /* */
-/* FLCTL_IE[FLCTL_IE_ERASE] Bits */
-#define FLCTL_IE_ERASE_OFS ( 5) /* ERASE Offset */
-#define FLCTL_IE_ERASE (0x00000020) /* */
-/* FLCTL_IE[FLCTL_IE_BMRK] Bits */
-#define FLCTL_IE_BMRK_OFS ( 8) /* BMRK Offset */
-#define FLCTL_IE_BMRK (0x00000100) /* */
-/* FLCTL_IE[FLCTL_IE_PRG_ERR] Bits */
-#define FLCTL_IE_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
-#define FLCTL_IE_PRG_ERR (0x00000200) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_RDBRST] Bits */
-#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /* RDBRST Offset */
-#define FLCTL_CLRIFG_RDBRST (0x00000001) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPRE] Bits */
-#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /* AVPRE Offset */
-#define FLCTL_CLRIFG_AVPRE (0x00000002) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPST] Bits */
-#define FLCTL_CLRIFG_AVPST_OFS ( 2) /* AVPST Offset */
-#define FLCTL_CLRIFG_AVPST (0x00000004) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG] Bits */
-#define FLCTL_CLRIFG_PRG_OFS ( 3) /* PRG Offset */
-#define FLCTL_CLRIFG_PRG (0x00000008) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRGB] Bits */
-#define FLCTL_CLRIFG_PRGB_OFS ( 4) /* PRGB Offset */
-#define FLCTL_CLRIFG_PRGB (0x00000010) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_ERASE] Bits */
-#define FLCTL_CLRIFG_ERASE_OFS ( 5) /* ERASE Offset */
-#define FLCTL_CLRIFG_ERASE (0x00000020) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_BMRK] Bits */
-#define FLCTL_CLRIFG_BMRK_OFS ( 8) /* BMRK Offset */
-#define FLCTL_CLRIFG_BMRK (0x00000100) /* */
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG_ERR] Bits */
-#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
-#define FLCTL_CLRIFG_PRG_ERR (0x00000200) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_RDBRST] Bits */
-#define FLCTL_SETIFG_RDBRST_OFS ( 0) /* RDBRST Offset */
-#define FLCTL_SETIFG_RDBRST (0x00000001) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_AVPRE] Bits */
-#define FLCTL_SETIFG_AVPRE_OFS ( 1) /* AVPRE Offset */
-#define FLCTL_SETIFG_AVPRE (0x00000002) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_AVPST] Bits */
-#define FLCTL_SETIFG_AVPST_OFS ( 2) /* AVPST Offset */
-#define FLCTL_SETIFG_AVPST (0x00000004) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRG] Bits */
-#define FLCTL_SETIFG_PRG_OFS ( 3) /* PRG Offset */
-#define FLCTL_SETIFG_PRG (0x00000008) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRGB] Bits */
-#define FLCTL_SETIFG_PRGB_OFS ( 4) /* PRGB Offset */
-#define FLCTL_SETIFG_PRGB (0x00000010) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_ERASE] Bits */
-#define FLCTL_SETIFG_ERASE_OFS ( 5) /* ERASE Offset */
-#define FLCTL_SETIFG_ERASE (0x00000020) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_BMRK] Bits */
-#define FLCTL_SETIFG_BMRK_OFS ( 8) /* BMRK Offset */
-#define FLCTL_SETIFG_BMRK (0x00000100) /* */
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRG_ERR] Bits */
-#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
-#define FLCTL_SETIFG_PRG_ERR (0x00000200) /* */
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP] Bits */
-#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
-#define FLCTL_READ_TIMCTL_SETUP_M (0x000000ff) /* */
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_HOLD] Bits */
-#define FLCTL_READ_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
-#define FLCTL_READ_TIMCTL_HOLD_M (0x00000f00) /* */
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_IREF_BOOST1] Bits */
-#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /* IREF_BOOST1 Offset */
-#define FLCTL_READ_TIMCTL_IREF_BOOST1_M (0x0000f000) /* */
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP_LONG] Bits */
-#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /* SETUP_LONG Offset */
-#define FLCTL_READ_TIMCTL_SETUP_LONG_M (0x00ff0000) /* */
-/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_SETUP] Bits */
-#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
-#define FLCTL_READMARGIN_TIMCTL_SETUP_M (0x000000ff) /* */
-/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_HOLD] Bits */
-#define FLCTL_READMARGIN_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
-#define FLCTL_READMARGIN_TIMCTL_HOLD_M (0x00000f00) /* */
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_SETUP] Bits */
-#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
-#define FLCTL_PRGVER_TIMCTL_SETUP_M (0x000000ff) /* */
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_ACTIVE] Bits */
-#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
-#define FLCTL_PRGVER_TIMCTL_ACTIVE_M (0x00000f00) /* */
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_HOLD] Bits */
-#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /* HOLD Offset */
-#define FLCTL_PRGVER_TIMCTL_HOLD_M (0x0000f000) /* */
-/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_SETUP] Bits */
-#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
-#define FLCTL_ERSVER_TIMCTL_SETUP_M (0x000000ff) /* */
-/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_HOLD] Bits */
-#define FLCTL_ERSVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
-#define FLCTL_ERSVER_TIMCTL_HOLD_M (0x00000f00) /* */
-/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_SETUP] Bits */
-#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
-#define FLCTL_LKGVER_TIMCTL_SETUP_M (0x000000ff) /* */
-/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_HOLD] Bits */
-#define FLCTL_LKGVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
-#define FLCTL_LKGVER_TIMCTL_HOLD_M (0x00000f00) /* */
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_SETUP] Bits */
-#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
-#define FLCTL_PROGRAM_TIMCTL_SETUP_M (0x000000ff) /* */
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_ACTIVE] Bits */
-#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
-#define FLCTL_PROGRAM_TIMCTL_ACTIVE_M (0x0fffff00) /* */
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_HOLD] Bits */
-#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /* HOLD Offset */
-#define FLCTL_PROGRAM_TIMCTL_HOLD_M (0xf0000000) /* */
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_SETUP] Bits */
-#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
-#define FLCTL_ERASE_TIMCTL_SETUP_M (0x000000ff) /* */
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_ACTIVE] Bits */
-#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
-#define FLCTL_ERASE_TIMCTL_ACTIVE_M (0x0fffff00) /* */
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_HOLD] Bits */
-#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /* HOLD Offset */
-#define FLCTL_ERASE_TIMCTL_HOLD_M (0xf0000000) /* */
-/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE] Bits */
-#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /* BOOST_ACTIVE Offset */
-#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_M (0x000000ff) /* */
-/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_HOLD] Bits */
-#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /* BOOST_HOLD Offset */
-#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_M (0x0000ff00) /* */
-/* FLCTL_BURSTPRG_TIMCTL[FLCTL_BURSTPRG_TIMCTL_ACTIVE] Bits */
-#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
-#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_M (0x0fffff00) /* */
+/* EUSCI_B_CTLW0[SEVENBIT] Bits */
+#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */
+#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */
+/* EUSCI_B_CTLW0[MSB] Bits */
+#define EUSCI_B_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */
+#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */
+/* EUSCI_B_CTLW0[CKPL] Bits */
+#define EUSCI_B_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */
+#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */
+/* EUSCI_B_CTLW0[CKPH] Bits */
+#define EUSCI_B_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */
+#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */
+/* EUSCI_B_CTLW1[GLIT] Bits */
+#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */
+#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */
+#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */
+#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */
+#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< 50 ns */
+#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< 25 ns */
+#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< 12.5 ns */
+#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< 6.25 ns */
+/* EUSCI_B_CTLW1[ASTP] Bits */
+#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /**< UCASTP Bit Offset */
+#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /**< UCASTP Bit Mask */
+#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /**< ASTP Bit 0 */
+#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /**< ASTP Bit 1 */
+#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /**< No automatic STOP generation. The STOP condition is generated after the user */
+ /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
+#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /**< UCBCNTIFG is set with the byte counter reaches the threshold defined in */
+ /* UCBxTBCNT */
+#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /**< A STOP condition is generated automatically after the byte counter value */
+ /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */
+ /* threshold */
+/* EUSCI_B_CTLW1[SWACK] Bits */
+#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /**< UCSWACK Bit Offset */
+#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /**< SW or HW ACK control */
+/* EUSCI_B_CTLW1[STPNACK] Bits */
+#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /**< UCSTPNACK Bit Offset */
+#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /**< ACK all master bytes */
+/* EUSCI_B_CTLW1[CLTO] Bits */
+#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /**< UCCLTO Bit Offset */
+#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /**< UCCLTO Bit Mask */
+#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /**< CLTO Bit 0 */
+#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /**< CLTO Bit 1 */
+#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /**< Disable clock low timeout counter */
+#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /**< 135 000 SYSCLK cycles (approximately 28 ms) */
+#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /**< 150 000 SYSCLK cycles (approximately 31 ms) */
+#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /**< 165 000 SYSCLK cycles (approximately 34 ms) */
+/* EUSCI_B_CTLW1[ETXINT] Bits */
+#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /**< UCETXINT Bit Offset */
+#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /**< Early UCTXIFG0 */
+/* EUSCI_B_STATW[BBUSY] Bits */
+#define EUSCI_B_STATW_BBUSY_OFS ( 4) /**< UCBBUSY Bit Offset */
+#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /**< Bus busy */
+/* EUSCI_B_STATW[GC] Bits */
+#define EUSCI_B_STATW_GC_OFS ( 5) /**< UCGC Bit Offset */
+#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /**< General call address received */
+/* EUSCI_B_STATW[SCLLOW] Bits */
+#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /**< UCSCLLOW Bit Offset */
+#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /**< SCL low */
+/* EUSCI_B_STATW[BCNT] Bits */
+#define EUSCI_B_STATW_BCNT_OFS ( 8) /**< UCBCNT Bit Offset */
+#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /**< UCBCNT Bit Mask */
+/* EUSCI_B_STATW[BUSY] Bits */
+#define EUSCI_B_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */
+#define EUSCI_B_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_B busy */
+/* EUSCI_B_STATW[OE] Bits */
+#define EUSCI_B_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */
+#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */
+/* EUSCI_B_STATW[FE] Bits */
+#define EUSCI_B_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */
+#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */
+/* EUSCI_B_STATW[LISTEN] Bits */
+#define EUSCI_B_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */
+#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */
+/* EUSCI_B_TBCNT[TBCNT] Bits */
+#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /**< UCTBCNT Bit Offset */
+#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /**< UCTBCNT Bit Mask */
+/* EUSCI_B_RXBUF[RXBUF] Bits */
+#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */
+#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */
+/* EUSCI_B_TXBUF[TXBUF] Bits */
+#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */
+#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */
+/* EUSCI_B_I2COA0[I2COA0] Bits */
+#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /**< I2COA0 Bit Offset */
+#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /**< I2COA0 Bit Mask */
+/* EUSCI_B_I2COA0[OAEN] Bits */
+#define EUSCI_B_I2COA0_OAEN_OFS (10) /**< UCOAEN Bit Offset */
+#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
+/* EUSCI_B_I2COA0[GCEN] Bits */
+#define EUSCI_B_I2COA0_GCEN_OFS (15) /**< UCGCEN Bit Offset */
+#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /**< General call response enable */
+/* EUSCI_B_I2COA1[I2COA1] Bits */
+#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /**< I2COA1 Bit Offset */
+#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /**< I2COA1 Bit Mask */
+/* EUSCI_B_I2COA1[OAEN] Bits */
+#define EUSCI_B_I2COA1_OAEN_OFS (10) /**< UCOAEN Bit Offset */
+#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
+/* EUSCI_B_I2COA2[I2COA2] Bits */
+#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /**< I2COA2 Bit Offset */
+#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /**< I2COA2 Bit Mask */
+/* EUSCI_B_I2COA2[OAEN] Bits */
+#define EUSCI_B_I2COA2_OAEN_OFS (10) /**< UCOAEN Bit Offset */
+#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
+/* EUSCI_B_I2COA3[I2COA3] Bits */
+#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /**< I2COA3 Bit Offset */
+#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /**< I2COA3 Bit Mask */
+/* EUSCI_B_I2COA3[OAEN] Bits */
+#define EUSCI_B_I2COA3_OAEN_OFS (10) /**< UCOAEN Bit Offset */
+#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /**< Own Address enable register */
+/* EUSCI_B_ADDRX[ADDRX] Bits */
+#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /**< ADDRX Bit Offset */
+#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /**< ADDRX Bit Mask */
+/* EUSCI_B_ADDMASK[ADDMASK] Bits */
+#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /**< ADDMASK Bit Offset */
+#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /**< ADDMASK Bit Mask */
+/* EUSCI_B_I2CSA[I2CSA] Bits */
+#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /**< I2CSA Bit Offset */
+#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /**< I2CSA Bit Mask */
+/* EUSCI_B_IE[RXIE0] Bits */
+#define EUSCI_B_IE_RXIE0_OFS ( 0) /**< UCRXIE0 Bit Offset */
+#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /**< Receive interrupt enable 0 */
+/* EUSCI_B_IE[TXIE0] Bits */
+#define EUSCI_B_IE_TXIE0_OFS ( 1) /**< UCTXIE0 Bit Offset */
+#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /**< Transmit interrupt enable 0 */
+/* EUSCI_B_IE[STTIE] Bits */
+#define EUSCI_B_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */
+#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /**< START condition interrupt enable */
+/* EUSCI_B_IE[STPIE] Bits */
+#define EUSCI_B_IE_STPIE_OFS ( 3) /**< UCSTPIE Bit Offset */
+#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /**< STOP condition interrupt enable */
+/* EUSCI_B_IE[ALIE] Bits */
+#define EUSCI_B_IE_ALIE_OFS ( 4) /**< UCALIE Bit Offset */
+#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /**< Arbitration lost interrupt enable */
+/* EUSCI_B_IE[NACKIE] Bits */
+#define EUSCI_B_IE_NACKIE_OFS ( 5) /**< UCNACKIE Bit Offset */
+#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /**< Not-acknowledge interrupt enable */
+/* EUSCI_B_IE[BCNTIE] Bits */
+#define EUSCI_B_IE_BCNTIE_OFS ( 6) /**< UCBCNTIE Bit Offset */
+#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /**< Byte counter interrupt enable */
+/* EUSCI_B_IE[CLTOIE] Bits */
+#define EUSCI_B_IE_CLTOIE_OFS ( 7) /**< UCCLTOIE Bit Offset */
+#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /**< Clock low timeout interrupt enable */
+/* EUSCI_B_IE[RXIE1] Bits */
+#define EUSCI_B_IE_RXIE1_OFS ( 8) /**< UCRXIE1 Bit Offset */
+#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /**< Receive interrupt enable 1 */
+/* EUSCI_B_IE[TXIE1] Bits */
+#define EUSCI_B_IE_TXIE1_OFS ( 9) /**< UCTXIE1 Bit Offset */
+#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /**< Transmit interrupt enable 1 */
+/* EUSCI_B_IE[RXIE2] Bits */
+#define EUSCI_B_IE_RXIE2_OFS (10) /**< UCRXIE2 Bit Offset */
+#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /**< Receive interrupt enable 2 */
+/* EUSCI_B_IE[TXIE2] Bits */
+#define EUSCI_B_IE_TXIE2_OFS (11) /**< UCTXIE2 Bit Offset */
+#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /**< Transmit interrupt enable 2 */
+/* EUSCI_B_IE[RXIE3] Bits */
+#define EUSCI_B_IE_RXIE3_OFS (12) /**< UCRXIE3 Bit Offset */
+#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /**< Receive interrupt enable 3 */
+/* EUSCI_B_IE[TXIE3] Bits */
+#define EUSCI_B_IE_TXIE3_OFS (13) /**< UCTXIE3 Bit Offset */
+#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /**< Transmit interrupt enable 3 */
+/* EUSCI_B_IE[BIT9IE] Bits */
+#define EUSCI_B_IE_BIT9IE_OFS (14) /**< UCBIT9IE Bit Offset */
+#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /**< Bit position 9 interrupt enable */
+/* EUSCI_B_UCBxIE_SPI[RXIE] Bits */
+#define EUSCI_B__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */
+#define EUSCI_B__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */
+/* EUSCI_B_UCBxIE_SPI[TXIE] Bits */
+#define EUSCI_B__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */
+#define EUSCI_B__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */
+/* EUSCI_B_IFG[RXIFG0] Bits */
+#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /**< UCRXIFG0 Bit Offset */
+#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /**< eUSCI_B receive interrupt flag 0 */
+/* EUSCI_B_IFG[TXIFG0] Bits */
+#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /**< UCTXIFG0 Bit Offset */
+#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /**< eUSCI_B transmit interrupt flag 0 */
+/* EUSCI_B_IFG[STTIFG] Bits */
+#define EUSCI_B_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */
+#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /**< START condition interrupt flag */
+/* EUSCI_B_IFG[STPIFG] Bits */
+#define EUSCI_B_IFG_STPIFG_OFS ( 3) /**< UCSTPIFG Bit Offset */
+#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /**< STOP condition interrupt flag */
+/* EUSCI_B_IFG[ALIFG] Bits */
+#define EUSCI_B_IFG_ALIFG_OFS ( 4) /**< UCALIFG Bit Offset */
+#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /**< Arbitration lost interrupt flag */
+/* EUSCI_B_IFG[NACKIFG] Bits */
+#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /**< UCNACKIFG Bit Offset */
+#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /**< Not-acknowledge received interrupt flag */
+/* EUSCI_B_IFG[BCNTIFG] Bits */
+#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /**< UCBCNTIFG Bit Offset */
+#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /**< Byte counter interrupt flag */
+/* EUSCI_B_IFG[CLTOIFG] Bits */
+#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /**< UCCLTOIFG Bit Offset */
+#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /**< Clock low timeout interrupt flag */
+/* EUSCI_B_IFG[RXIFG1] Bits */
+#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /**< UCRXIFG1 Bit Offset */
+#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /**< eUSCI_B receive interrupt flag 1 */
+/* EUSCI_B_IFG[TXIFG1] Bits */
+#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /**< UCTXIFG1 Bit Offset */
+#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /**< eUSCI_B transmit interrupt flag 1 */
+/* EUSCI_B_IFG[RXIFG2] Bits */
+#define EUSCI_B_IFG_RXIFG2_OFS (10) /**< UCRXIFG2 Bit Offset */
+#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /**< eUSCI_B receive interrupt flag 2 */
+/* EUSCI_B_IFG[TXIFG2] Bits */
+#define EUSCI_B_IFG_TXIFG2_OFS (11) /**< UCTXIFG2 Bit Offset */
+#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /**< eUSCI_B transmit interrupt flag 2 */
+/* EUSCI_B_IFG[RXIFG3] Bits */
+#define EUSCI_B_IFG_RXIFG3_OFS (12) /**< UCRXIFG3 Bit Offset */
+#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /**< eUSCI_B receive interrupt flag 3 */
+/* EUSCI_B_IFG[TXIFG3] Bits */
+#define EUSCI_B_IFG_TXIFG3_OFS (13) /**< UCTXIFG3 Bit Offset */
+#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /**< eUSCI_B transmit interrupt flag 3 */
+/* EUSCI_B_IFG[BIT9IFG] Bits */
+#define EUSCI_B_IFG_BIT9IFG_OFS (14) /**< UCBIT9IFG Bit Offset */
+#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /**< Bit position 9 interrupt flag */
+/* EUSCI_B_IFG[RXIFG] Bits */
+#define EUSCI_B_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */
+#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */
+/* EUSCI_B_IFG[TXIFG] Bits */
+#define EUSCI_B_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */
+#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */
-//*****************************************************************************
-// FPB Bits
-//*****************************************************************************
-/* FPB_FP_CTRL[FPB_FP_CTRL_ENABLE] Bits */
-#define FPB_FP_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_CTRL_ENABLE (0x00000001) /* */
-/* FPB_FP_CTRL[FPB_FP_CTRL_KEY] Bits */
-#define FPB_FP_CTRL_KEY_OFS ( 1) /* KEY Offset */
-#define FPB_FP_CTRL_KEY (0x00000002) /* */
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE1] Bits */
-#define FPB_FP_CTRL_NUM_CODE1_OFS ( 4) /* NUM_CODE1 Offset */
-#define FPB_FP_CTRL_NUM_CODE1_M (0x000000f0) /* */
-#define FPB_FP_CTRL_NUM_CODE10 (0x00000010) /* */
-#define FPB_FP_CTRL_NUM_CODE11 (0x00000020) /* */
-#define FPB_FP_CTRL_NUM_CODE12 (0x00000040) /* */
-#define FPB_FP_CTRL_NUM_CODE13 (0x00000080) /* */
-#define FPB_FP_CTRL_NUM_CODE1_0 (0x00000000) /* no code slots */
-#define FPB_FP_CTRL_NUM_CODE1_2 (0x00000020) /* two code slots */
-#define FPB_FP_CTRL_NUM_CODE1_6 (0x00000060) /* six code slots */
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_LIT] Bits */
-#define FPB_FP_CTRL_NUM_LIT_OFS ( 8) /* NUM_LIT Offset */
-#define FPB_FP_CTRL_NUM_LIT_M (0x00000f00) /* */
-#define FPB_FP_CTRL_NUM_LIT0 (0x00000100) /* */
-#define FPB_FP_CTRL_NUM_LIT1 (0x00000200) /* */
-#define FPB_FP_CTRL_NUM_LIT2 (0x00000400) /* */
-#define FPB_FP_CTRL_NUM_LIT3 (0x00000800) /* */
-#define FPB_FP_CTRL_NUM_LIT_0 (0x00000000) /* no literal slots */
-#define FPB_FP_CTRL_NUM_LIT_2 (0x00000200) /* two literal slots */
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE2] Bits */
-#define FPB_FP_CTRL_NUM_CODE2_OFS (12) /* NUM_CODE2 Offset */
-#define FPB_FP_CTRL_NUM_CODE2_M (0x00003000) /* */
-/* FPB_FP_REMAP[FPB_FP_REMAP_REMAP] Bits */
-#define FPB_FP_REMAP_REMAP_OFS ( 5) /* REMAP Offset */
-#define FPB_FP_REMAP_REMAP_M (0x1fffffe0) /* */
-/* FPB_FP_COMP0[FPB_FP_COMP0_ENABLE] Bits */
-#define FPB_FP_COMP0_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP0_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP0[FPB_FP_COMP0_COMP] Bits */
-#define FPB_FP_COMP0_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP0_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP0[FPB_FP_COMP0_REPLACE] Bits */
-#define FPB_FP_COMP0_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP0_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP0_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP0_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP0_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP0_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP0_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP0_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
-/* FPB_FP_COMP1[FPB_FP_COMP1_ENABLE] Bits */
-#define FPB_FP_COMP1_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP1_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP1[FPB_FP_COMP1_COMP] Bits */
-#define FPB_FP_COMP1_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP1_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP1[FPB_FP_COMP1_REPLACE] Bits */
-#define FPB_FP_COMP1_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP1_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP1_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP1_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP1_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP1_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP1_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP1_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
-/* FPB_FP_COMP2[FPB_FP_COMP2_ENABLE] Bits */
-#define FPB_FP_COMP2_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP2_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP2[FPB_FP_COMP2_COMP] Bits */
-#define FPB_FP_COMP2_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP2_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP2[FPB_FP_COMP2_REPLACE] Bits */
-#define FPB_FP_COMP2_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP2_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP2_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP2_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP2_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP2_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP2_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP2_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
-/* FPB_FP_COMP3[FPB_FP_COMP3_ENABLE] Bits */
-#define FPB_FP_COMP3_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP3_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP3[FPB_FP_COMP3_COMP] Bits */
-#define FPB_FP_COMP3_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP3_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP3[FPB_FP_COMP3_REPLACE] Bits */
-#define FPB_FP_COMP3_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP3_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP3_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP3_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP3_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP3_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP3_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP3_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
-/* FPB_FP_COMP4[FPB_FP_COMP4_ENABLE] Bits */
-#define FPB_FP_COMP4_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP4_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP4[FPB_FP_COMP4_COMP] Bits */
-#define FPB_FP_COMP4_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP4_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP4[FPB_FP_COMP4_REPLACE] Bits */
-#define FPB_FP_COMP4_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP4_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP4_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP4_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP4_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP4_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP4_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP4_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
-/* FPB_FP_COMP5[FPB_FP_COMP5_ENABLE] Bits */
-#define FPB_FP_COMP5_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP5_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP5[FPB_FP_COMP5_COMP] Bits */
-#define FPB_FP_COMP5_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP5_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP5[FPB_FP_COMP5_REPLACE] Bits */
-#define FPB_FP_COMP5_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP5_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP5_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP5_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP5_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP5_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP5_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP5_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
-/* FPB_FP_COMP6[FPB_FP_COMP6_ENABLE] Bits */
-#define FPB_FP_COMP6_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP6_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP6[FPB_FP_COMP6_COMP] Bits */
-#define FPB_FP_COMP6_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP6_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP6[FPB_FP_COMP6_REPLACE] Bits */
-#define FPB_FP_COMP6_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP6_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP6_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP6_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP6_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP6_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP6_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP6_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
-/* FPB_FP_COMP7[FPB_FP_COMP7_ENABLE] Bits */
-#define FPB_FP_COMP7_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define FPB_FP_COMP7_ENABLE (0x00000001) /* */
-/* FPB_FP_COMP7[FPB_FP_COMP7_COMP] Bits */
-#define FPB_FP_COMP7_COMP_OFS ( 2) /* COMP Offset */
-#define FPB_FP_COMP7_COMP_M (0x1ffffffc) /* */
-/* FPB_FP_COMP7[FPB_FP_COMP7_REPLACE] Bits */
-#define FPB_FP_COMP7_REPLACE_OFS (30) /* REPLACE Offset */
-#define FPB_FP_COMP7_REPLACE_M (0xc0000000) /* */
-#define FPB_FP_COMP7_REPLACE0 (0x40000000) /* */
-#define FPB_FP_COMP7_REPLACE1 (0x80000000) /* */
-#define FPB_FP_COMP7_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
-#define FPB_FP_COMP7_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
-#define FPB_FP_COMP7_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
-#define FPB_FP_COMP7_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
+/******************************************************************************
+* FLCTL Bits
+******************************************************************************/
+/* FLCTL_POWER_STAT[PSTAT] Bits */
+#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /**< PSTAT Bit Offset */
+#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /**< PSTAT Bit Mask */
+#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /**< PSTAT Bit 0 */
+#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /**< PSTAT Bit 1 */
+#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /**< PSTAT Bit 2 */
+#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /**< Flash IP in power-down mode */
+#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /**< Flash IP Vdd domain power-up in progress */
+#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /**< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
+#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /**< Flash IP SAFE_LV check in progress */
+#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /**< Flash IP Active */
+#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /**< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
+#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /**< Flash IP in Standby mode */
+#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /**< Flash IP in Current mirror boost state */
+/* FLCTL_POWER_STAT[LDOSTAT] Bits */
+#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /**< LDOSTAT Bit Offset */
+#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /**< PSS FLDO GOOD status */
+/* FLCTL_POWER_STAT[VREFSTAT] Bits */
+#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /**< VREFSTAT Bit Offset */
+#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /**< PSS VREF stable status */
+/* FLCTL_POWER_STAT[IREFSTAT] Bits */
+#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /**< IREFSTAT Bit Offset */
+#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /**< PSS IREF stable status */
+/* FLCTL_POWER_STAT[TRIMSTAT] Bits */
+#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /**< TRIMSTAT Bit Offset */
+#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /**< PSS trim done status */
+/* FLCTL_POWER_STAT[RD_2T] Bits */
+#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /**< RD_2T Bit Offset */
+#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /**< Indicates if Flash is being accessed in 2T mode */
+/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */
+#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */
+#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */
+#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */
+#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */
+#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */
+#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */
+/* FLCTL_BANK0_RDCTL[BUFI] Bits */
+#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */
+#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */
+/* FLCTL_BANK0_RDCTL[BUFD] Bits */
+#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */
+#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */
+/* FLCTL_BANK0_RDCTL[WAIT] Bits */
+#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */
+#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */
+#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */
+#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */
+#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */
+#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */
+#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */
+#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */
+/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */
+/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */
+#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */
+#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */
+#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */
+#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */
+#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */
+#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */
+/* FLCTL_BANK1_RDCTL[BUFI] Bits */
+#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */
+#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */
+/* FLCTL_BANK1_RDCTL[BUFD] Bits */
+#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */
+#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */
+/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */
+/* FLCTL_BANK1_RDCTL[WAIT] Bits */
+#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */
+#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */
+#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */
+#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */
+#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */
+#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */
+#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */
+#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */
+/* FLCTL_RDBRST_CTLSTAT[START] Bits */
+#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of burst/compare operation */
+/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /**< MEM_TYPE Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /**< MEM_TYPE Bit Mask */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /**< MEM_TYPE Bit 0 */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /**< MEM_TYPE Bit 1 */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */
+/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /**< STOP_FAIL Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /**< Terminate burst/compare operation */
+/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /**< DATA_CMP Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /**< Data pattern used for comparison against memory read data */
+/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /**< TEST_EN Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /**< Enable comparison against test data compare registers */
+/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /**< BRST_STAT Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /**< BRST_STAT Bit Mask */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /**< BRST_STAT Bit 0 */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /**< BRST_STAT Bit 1 */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /**< Idle */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /**< Burst/Compare START bit written, but operation pending */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /**< Burst/Compare in progress */
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /**< Burst complete (status of completed burst remains in this state unless */
+ /* explicitly cleared by SW) */
+/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /**< CMP_ERR Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /**< Burst/Compare Operation encountered atleast one data */
+/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /**< ADDR_ERR Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /**< Burst/Compare Operation was terminated due to access to */
+/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 19-16 of this register */
+/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< START_ADDRESS Bit Mask */
+/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /**< BURST_LENGTH Bit Offset */
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /**< BURST_LENGTH Bit Mask */
+/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /**< FAIL_ADDRESS Bit Offset */
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< FAIL_ADDRESS Bit Mask */
+/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /**< FAIL_COUNT Bit Offset */
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /**< FAIL_COUNT Bit Mask */
+/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */
+#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /**< ENABLE Bit Offset */
+#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /**< Master control for all word program operations */
+/* FLCTL_PRG_CTLSTAT[MODE] Bits */
+#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */
+#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Write mode */
+/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */
+#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /**< VER_PRE Bit Offset */
+#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /**< Controls automatic pre program verify operations */
+/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */
+#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /**< VER_PST Bit Offset */
+#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /**< Controls automatic post program verify operations */
+/* FLCTL_PRG_CTLSTAT[STATUS] Bits */
+#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */
+#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */
+#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */
+#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */
+#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */
+#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Single word program operation triggered, but pending */
+#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Single word program in progress */
+#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Reserved (Idle) */
+/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */
+#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /**< BNK_ACT Bit Offset */
+#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /**< Bank active */
+/* FLCTL_PRGBRST_CTLSTAT[START] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Trigger start of burst program operation */
+/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /**< TYPE Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /**< TYPE Bit Mask */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /**< TYPE Bit 0 */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /**< TYPE Bit 1 */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */
+/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /**< LEN Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /**< LEN Bit Mask */
+#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /**< LEN Bit 0 */
+#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /**< LEN Bit 1 */
+#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /**< LEN Bit 2 */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /**< No burst operation */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /**< 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR */
+ /* Register */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /**< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */
+ /* Register */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /**< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */
+ /* Register */
+#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /**< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */
+ /* Register */
+/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /**< AUTO_PRE Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /**< Auto-Verify operation before the Burst Program */
+/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /**< AUTO_PST Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /**< Auto-Verify operation after the Burst Program */
+/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /**< BURST_STATUS Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /**< BURST_STATUS Bit Mask */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /**< BURST_STATUS Bit 0 */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /**< BURST_STATUS Bit 1 */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /**< BURST_STATUS Bit 2 */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /**< Idle (Burst not active) */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /**< Burst program started but pending */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /**< Burst active, with 1st 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /**< Burst active, with 2nd 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /**< Burst active, with 3rd 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /**< Burst active, with 4th 128 bit word being written into Flash */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /**< Reserved (Idle) */
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /**< Burst Complete (status of completed burst remains in this state unless */
+ /* explicitly cleared by SW) */
+/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /**< PRE_ERR Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /**< Burst Operation encountered preprogram auto-verify errors */
+/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /**< PST_ERR Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /**< Burst Operation encountered postprogram auto-verify errors */
+/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /**< ADDR_ERR Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /**< Burst Operation was terminated due to attempted program of reserved memory */
+/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 21-16 of this register */
+/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< START_ADDRESS Bit Mask */
+/* FLCTL_ERASE_CTLSTAT[START] Bits */
+#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */
+#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of Erase operation */
+/* FLCTL_ERASE_CTLSTAT[MODE] Bits */
+#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */
+#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Erase mode selected by application */
+/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */
+#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /**< TYPE Bit Offset */
+#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /**< TYPE Bit Mask */
+#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /**< TYPE Bit 0 */
+#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /**< TYPE Bit 1 */
+#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */
+#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /**< Information Memory */
+#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /**< Reserved */
+#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /**< Engineering Memory */
+/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */
+#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */
+#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */
+#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */
+#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */
+#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */
+#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Erase operation triggered to START but pending */
+#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Erase operation in progress */
+#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Erase operation completed (status of completed erase remains in this state */
+ /* unless explicitly cleared by SW) */
+/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /**< ADDR_ERR Bit Offset */
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /**< Erase Operation was terminated due to attempted erase of reserved memory */
+ /* address */
+/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /**< CLR_STAT Bit Offset */
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /**< Clear status bits 18-16 of this register */
+/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /**< SECT_ADDRESS Bit Offset */
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< SECT_ADDRESS Bit Mask */
+/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */
+#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
+#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */
+/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */
+#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
+#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase */
+/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase */
+/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */
+#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
+#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */
+/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */
+#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
+#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase operations */
+/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase operations */
+/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */
+#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /**< I_BMRK Bit Offset */
+#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001)
+/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */
+#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /**< D_BMRK Bit Offset */
+#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002)
+/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */
+#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /**< CMP_EN Bit Offset */
+#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004)
+/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /**< CMP_SEL Bit Offset */
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008)
+/* FLCTL_IFG[RDBRST] Bits */
+#define FLCTL_IFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
+#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001)
+/* FLCTL_IFG[AVPRE] Bits */
+#define FLCTL_IFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
+#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002)
+/* FLCTL_IFG[AVPST] Bits */
+#define FLCTL_IFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */
+#define FLCTL_IFG_AVPST ((uint32_t)0x00000004)
+/* FLCTL_IFG[PRG] Bits */
+#define FLCTL_IFG_PRG_OFS ( 3) /**< PRG Bit Offset */
+#define FLCTL_IFG_PRG ((uint32_t)0x00000008)
+/* FLCTL_IFG[PRGB] Bits */
+#define FLCTL_IFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */
+#define FLCTL_IFG_PRGB ((uint32_t)0x00000010)
+/* FLCTL_IFG[ERASE] Bits */
+#define FLCTL_IFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */
+#define FLCTL_IFG_ERASE ((uint32_t)0x00000020)
+/* FLCTL_IFG[BMRK] Bits */
+#define FLCTL_IFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */
+#define FLCTL_IFG_BMRK ((uint32_t)0x00000100)
+/* FLCTL_IFG[PRG_ERR] Bits */
+#define FLCTL_IFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
+#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200)
+/* FLCTL_IE[RDBRST] Bits */
+#define FLCTL_IE_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
+#define FLCTL_IE_RDBRST ((uint32_t)0x00000001)
+/* FLCTL_IE[AVPRE] Bits */
+#define FLCTL_IE_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
+#define FLCTL_IE_AVPRE ((uint32_t)0x00000002)
+/* FLCTL_IE[AVPST] Bits */
+#define FLCTL_IE_AVPST_OFS ( 2) /**< AVPST Bit Offset */
+#define FLCTL_IE_AVPST ((uint32_t)0x00000004)
+/* FLCTL_IE[PRG] Bits */
+#define FLCTL_IE_PRG_OFS ( 3) /**< PRG Bit Offset */
+#define FLCTL_IE_PRG ((uint32_t)0x00000008)
+/* FLCTL_IE[PRGB] Bits */
+#define FLCTL_IE_PRGB_OFS ( 4) /**< PRGB Bit Offset */
+#define FLCTL_IE_PRGB ((uint32_t)0x00000010)
+/* FLCTL_IE[ERASE] Bits */
+#define FLCTL_IE_ERASE_OFS ( 5) /**< ERASE Bit Offset */
+#define FLCTL_IE_ERASE ((uint32_t)0x00000020)
+/* FLCTL_IE[BMRK] Bits */
+#define FLCTL_IE_BMRK_OFS ( 8) /**< BMRK Bit Offset */
+#define FLCTL_IE_BMRK ((uint32_t)0x00000100)
+/* FLCTL_IE[PRG_ERR] Bits */
+#define FLCTL_IE_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
+#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200)
+/* FLCTL_CLRIFG[RDBRST] Bits */
+#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
+#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001)
+/* FLCTL_CLRIFG[AVPRE] Bits */
+#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
+#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002)
+/* FLCTL_CLRIFG[AVPST] Bits */
+#define FLCTL_CLRIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */
+#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004)
+/* FLCTL_CLRIFG[PRG] Bits */
+#define FLCTL_CLRIFG_PRG_OFS ( 3) /**< PRG Bit Offset */
+#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008)
+/* FLCTL_CLRIFG[PRGB] Bits */
+#define FLCTL_CLRIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */
+#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010)
+/* FLCTL_CLRIFG[ERASE] Bits */
+#define FLCTL_CLRIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */
+#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020)
+/* FLCTL_CLRIFG[BMRK] Bits */
+#define FLCTL_CLRIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */
+#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100)
+/* FLCTL_CLRIFG[PRG_ERR] Bits */
+#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
+#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200)
+/* FLCTL_SETIFG[RDBRST] Bits */
+#define FLCTL_SETIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */
+#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001)
+/* FLCTL_SETIFG[AVPRE] Bits */
+#define FLCTL_SETIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */
+#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002)
+/* FLCTL_SETIFG[AVPST] Bits */
+#define FLCTL_SETIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */
+#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004)
+/* FLCTL_SETIFG[PRG] Bits */
+#define FLCTL_SETIFG_PRG_OFS ( 3) /**< PRG Bit Offset */
+#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008)
+/* FLCTL_SETIFG[PRGB] Bits */
+#define FLCTL_SETIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */
+#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010)
+/* FLCTL_SETIFG[ERASE] Bits */
+#define FLCTL_SETIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */
+#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020)
+/* FLCTL_SETIFG[BMRK] Bits */
+#define FLCTL_SETIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */
+#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100)
+/* FLCTL_SETIFG[PRG_ERR] Bits */
+#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */
+#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200)
+/* FLCTL_READ_TIMCTL[SETUP] Bits */
+#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
+#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
+/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /**< IREF_BOOST1 Bit Offset */
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /**< IREF_BOOST1 Bit Mask */
+/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */
+#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /**< SETUP_LONG Bit Offset */
+#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /**< SETUP_LONG Bit Mask */
+/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */
+#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
+#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
+/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */
+#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
+#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
+/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /**< ACTIVE Bit Mask */
+/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */
+#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /**< HOLD Bit Offset */
+#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /**< HOLD Bit Mask */
+/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */
+#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
+#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
+/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */
+#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
+#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
+/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */
+#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
+#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
+/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */
+/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */
+#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */
+#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */
+/* FLCTL_ERASE_TIMCTL[SETUP] Bits */
+#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */
+#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */
+/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */
+#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
+#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */
+/* FLCTL_ERASE_TIMCTL[HOLD] Bits */
+#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */
+#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */
+/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /**< BOOST_ACTIVE Bit Offset */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /**< BOOST_ACTIVE Bit Mask */
+/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /**< BOOST_HOLD Bit Offset */
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /**< BOOST_HOLD Bit Mask */
+/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */
-//*****************************************************************************
-// FPU Bits
-//*****************************************************************************
-/* FPU_FPCCR[FPU_FPCCR_ASPEN] Bits */
-#define FPU_FPCCR_ASPEN_OFS (31) /* ASPEN Offset */
-#define FPU_FPCCR_ASPEN (0x80000000) /* */
-/* FPU_FPCCR[FPU_FPCCR_LSPEN] Bits */
-#define FPU_FPCCR_LSPEN_OFS (30) /* LSPEN Offset */
-#define FPU_FPCCR_LSPEN (0x40000000) /* */
-/* FPU_FPCCR[FPU_FPCCR_MONRDY] Bits */
-#define FPU_FPCCR_MONRDY_OFS ( 8) /* MONRDY Offset */
-#define FPU_FPCCR_MONRDY (0x00000100) /* */
-/* FPU_FPCCR[FPU_FPCCR_BFRDY] Bits */
-#define FPU_FPCCR_BFRDY_OFS ( 6) /* BFRDY Offset */
-#define FPU_FPCCR_BFRDY (0x00000040) /* */
-/* FPU_FPCCR[FPU_FPCCR_MMRDY] Bits */
-#define FPU_FPCCR_MMRDY_OFS ( 5) /* MMRDY Offset */
-#define FPU_FPCCR_MMRDY (0x00000020) /* */
-/* FPU_FPCCR[FPU_FPCCR_HFRDY] Bits */
-#define FPU_FPCCR_HFRDY_OFS ( 4) /* HFRDY Offset */
-#define FPU_FPCCR_HFRDY (0x00000010) /* */
-/* FPU_FPCCR[FPU_FPCCR_THREAD] Bits */
-#define FPU_FPCCR_THREAD_OFS ( 3) /* THREAD Offset */
-#define FPU_FPCCR_THREAD (0x00000008) /* */
-/* FPU_FPCCR[FPU_FPCCR_USER] Bits */
-#define FPU_FPCCR_USER_OFS ( 1) /* USER Offset */
-#define FPU_FPCCR_USER (0x00000002) /* */
-/* FPU_FPCCR[FPU_FPCCR_LSPACT] Bits */
-#define FPU_FPCCR_LSPACT_OFS ( 0) /* LSPACT Offset */
-#define FPU_FPCCR_LSPACT (0x00000001) /* */
-/* FPU_FPCAR[FPU_FPCAR_ADDRESS] Bits */
-#define FPU_FPCAR_ADDRESS_OFS ( 2) /* ADDRESS Offset */
-#define FPU_FPCAR_ADDRESS_M (0x7ffffffc) /* */
-/* FPU_FPDSCR[FPU_FPDSCR_AHP] Bits */
-#define FPU_FPDSCR_AHP_OFS (26) /* AHP Offset */
-#define FPU_FPDSCR_AHP (0x04000000) /* */
-/* FPU_FPDSCR[FPU_FPDSCR_DN] Bits */
-#define FPU_FPDSCR_DN_OFS (25) /* DN Offset */
-#define FPU_FPDSCR_DN (0x02000000) /* */
-/* FPU_FPDSCR[FPU_FPDSCR_FZ] Bits */
-#define FPU_FPDSCR_FZ_OFS (24) /* FZ Offset */
-#define FPU_FPDSCR_FZ (0x01000000) /* */
-/* FPU_FPDSCR[FPU_FPDSCR_RMODE] Bits */
-#define FPU_FPDSCR_RMODE_OFS (22) /* RMODE Offset */
-#define FPU_FPDSCR_RMODE_M (0x00c00000) /* */
-/* FPU_MVFR0[FPU_MVFR0_FP_ROUNDING_MODES] Bits */
-#define FPU_MVFR0_FP_ROUNDING_MODES_OFS (28) /* FP_ROUNDING_MODES Offset */
-#define FPU_MVFR0_FP_ROUNDING_MODES_M (0xf0000000) /* */
-/* FPU_MVFR0[FPU_MVFR0_SHORT_VECTORS] Bits */
-#define FPU_MVFR0_SHORT_VECTORS_OFS (24) /* SHORT_VECTORS Offset */
-#define FPU_MVFR0_SHORT_VECTORS_M (0x0f000000) /* */
-/* FPU_MVFR0[FPU_MVFR0_SQUARE_ROOT] Bits */
-#define FPU_MVFR0_SQUARE_ROOT_OFS (20) /* SQUARE_ROOT Offset */
-#define FPU_MVFR0_SQUARE_ROOT_M (0x00f00000) /* */
-/* FPU_MVFR0[FPU_MVFR0_DIVIDE] Bits */
-#define FPU_MVFR0_DIVIDE_OFS (16) /* DIVIDE Offset */
-#define FPU_MVFR0_DIVIDE_M (0x000f0000) /* */
-/* FPU_MVFR0[FPU_MVFR0_FP_ECEPTION_TRAPPING] Bits */
-#define FPU_MVFR0_FP_ECEPTION_TRAPPING_OFS (12) /* FP_EXCEPTION_TRAPPING Offset */
-#define FPU_MVFR0_FP_ECEPTION_TRAPPING_M (0x0000f000) /* */
-/* FPU_MVFR0[FPU_MVFR0_DOUBLE_PRECISION] Bits */
-#define FPU_MVFR0_DOUBLE_PRECISION_OFS ( 8) /* DOUBLE_PRECISION Offset */
-#define FPU_MVFR0_DOUBLE_PRECISION_M (0x00000f00) /* */
-/* FPU_MVFR0[FPU_MVFR0_SINGLE_PRECISION] Bits */
-#define FPU_MVFR0_SINGLE_PRECISION_OFS ( 4) /* SINGLE_PRECISION Offset */
-#define FPU_MVFR0_SINGLE_PRECISION_M (0x000000f0) /* */
-/* FPU_MVFR0[FPU_MVFR0_A_SIMD_REGISTERS] Bits */
-#define FPU_MVFR0_A_SIMD_REGISTERS_OFS ( 0) /* A_SIMD_REGISTERS Offset */
-#define FPU_MVFR0_A_SIMD_REGISTERS_M (0x0000000f) /* */
-/* FPU_MVFR1[FPU_MVFR1_FP_FUSED_MAC] Bits */
-#define FPU_MVFR1_FP_FUSED_MAC_OFS (28) /* FP_FUSED_MAC Offset */
-#define FPU_MVFR1_FP_FUSED_MAC_M (0xf0000000) /* */
-/* FPU_MVFR1[FPU_MVFR1_FP_HPFP] Bits */
-#define FPU_MVFR1_FP_HPFP_OFS (24) /* FP_HPFP Offset */
-#define FPU_MVFR1_FP_HPFP_M (0x0f000000) /* */
-/* FPU_MVFR1[FPU_MVFR1_D_NAN_MODE] Bits */
-#define FPU_MVFR1_D_NAN_MODE_OFS ( 4) /* D_NAN_MODE Offset */
-#define FPU_MVFR1_D_NAN_MODE_M (0x000000f0) /* */
-/* FPU_MVFR1[FPU_MVFR1_FTZ_MODE] Bits */
-#define FPU_MVFR1_FTZ_MODE_OFS ( 0) /* FTZ_MODE Offset */
-#define FPU_MVFR1_FTZ_MODE_M (0x0000000f) /* */
+/******************************************************************************
+* FPB Bits
+******************************************************************************/
-//*****************************************************************************
-// ITM Bits
-//*****************************************************************************
-/* ITM_TPR[ITM_TPR_PRIVMASK] Bits */
-#define ITM_TPR_PRIVMASK_OFS ( 0) /* PRIVMASK Offset */
-#define ITM_TPR_PRIVMASK_M (0x0000000f) /* */
-/* ITM_TCR[ITM_TCR_ITMENA] Bits */
-#define ITM_TCR_ITMENA_OFS ( 0) /* ITMENA Offset */
-#define ITM_TCR_ITMENA (0x00000001) /* */
-/* ITM_TCR[ITM_TCR_TSENA] Bits */
-#define ITM_TCR_TSENA_OFS ( 1) /* TSENA Offset */
-#define ITM_TCR_TSENA (0x00000002) /* */
-/* ITM_TCR[ITM_TCR_SYNCENA] Bits */
-#define ITM_TCR_SYNCENA_OFS ( 2) /* SYNCENA Offset */
-#define ITM_TCR_SYNCENA (0x00000004) /* */
-/* ITM_TCR[ITM_TCR_DWTENA] Bits */
-#define ITM_TCR_DWTENA_OFS ( 3) /* DWTENA Offset */
-#define ITM_TCR_DWTENA (0x00000008) /* */
-/* ITM_TCR[ITM_TCR_SWOENA] Bits */
-#define ITM_TCR_SWOENA_OFS ( 4) /* SWOENA Offset */
-#define ITM_TCR_SWOENA (0x00000010) /* */
-/* ITM_TCR[ITM_TCR_TSPRESCALE] Bits */
-#define ITM_TCR_TSPRESCALE_OFS ( 8) /* TSPRESCALE Offset */
-#define ITM_TCR_TSPRESCALE_M (0x00000300) /* */
-#define ITM_TCR_TSPRESCALE0 (0x00000100) /* */
-#define ITM_TCR_TSPRESCALE1 (0x00000200) /* */
-#define ITM_TCR_TSPRESCALE_0 (0x00000000) /* no prescaling */
-#define ITM_TCR_TSPRESCALE_1 (0x00000100) /* divide by 4 */
-#define ITM_TCR_TSPRESCALE_2 (0x00000200) /* divide by 16 */
-#define ITM_TCR_TSPRESCALE_3 (0x00000300) /* divide by 64 */
-/* ITM_TCR[ITM_TCR_ATBID] Bits */
-#define ITM_TCR_ATBID_OFS (16) /* ATBID Offset */
-#define ITM_TCR_ATBID_M (0x007f0000) /* */
-/* ITM_TCR[ITM_TCR_BUSY] Bits */
-#define ITM_TCR_BUSY_OFS (23) /* BUSY Offset */
-#define ITM_TCR_BUSY (0x00800000) /* */
-/* ITM_IWR[ITM_IWR_ATVALIDM] Bits */
-#define ITM_IWR_ATVALIDM_OFS ( 0) /* ATVALIDM Offset */
-#define ITM_IWR_ATVALIDM (0x00000001) /* */
-/* ITM_IMCR[ITM_IMCR_INTEGRATION] Bits */
-#define ITM_IMCR_INTEGRATION_OFS ( 0) /* INTEGRATION Offset */
-#define ITM_IMCR_INTEGRATION (0x00000001) /* */
-/* ITM_LSR[ITM_LSR_PRESENT] Bits */
-#define ITM_LSR_PRESENT_OFS ( 0) /* PRESENT Offset */
-#define ITM_LSR_PRESENT (0x00000001) /* */
-/* ITM_LSR[ITM_LSR_ACCESS] Bits */
-#define ITM_LSR_ACCESS_OFS ( 1) /* ACCESS Offset */
-#define ITM_LSR_ACCESS (0x00000002) /* */
-/* ITM_LSR[ITM_LSR_BYTEACC] Bits */
-#define ITM_LSR_BYTEACC_OFS ( 2) /* BYTEACC Offset */
-#define ITM_LSR_BYTEACC (0x00000004) /* */
+/******************************************************************************
+* FPU Bits
+******************************************************************************/
-//*****************************************************************************
-// MPU Bits
-//*****************************************************************************
-/* MPU_TYPE[MPU_TYPE_SEPARATE] Bits */
-#define MPU_TYPE_SEPARATE_OFS ( 0) /* SEPARATE Offset */
-#define MPU_TYPE_SEPARATE (0x00000001) /* */
-/* MPU_TYPE[MPU_TYPE_DREGION] Bits */
-#define MPU_TYPE_DREGION_OFS ( 8) /* DREGION Offset */
-#define MPU_TYPE_DREGION_M (0x0000ff00) /* */
-/* MPU_TYPE[MPU_TYPE_IREGION] Bits */
-#define MPU_TYPE_IREGION_OFS (16) /* IREGION Offset */
-#define MPU_TYPE_IREGION_M (0x00ff0000) /* */
-/* MPU_CTRL[MPU_CTRL_ENABLE] Bits */
-#define MPU_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define MPU_CTRL_ENABLE (0x00000001) /* */
-/* MPU_CTRL[MPU_CTRL_HFNMIENA] Bits */
-#define MPU_CTRL_HFNMIENA_OFS ( 1) /* HFNMIENA Offset */
-#define MPU_CTRL_HFNMIENA (0x00000002) /* */
-/* MPU_CTRL[MPU_CTRL_PRIVDEFENA] Bits */
-#define MPU_CTRL_PRIVDEFENA_OFS ( 2) /* PRIVDEFENA Offset */
-#define MPU_CTRL_PRIVDEFENA (0x00000004) /* */
-/* MPU_RNR[MPU_RNR_REGION] Bits */
-#define MPU_RNR_REGION_OFS ( 0) /* REGION Offset */
-#define MPU_RNR_REGION_M (0x000000ff) /* */
-/* MPU_RBAR[MPU_RBAR_REGION] Bits */
-#define MPU_RBAR_REGION_OFS ( 0) /* REGION Offset */
-#define MPU_RBAR_REGION_M (0x0000000f) /* */
-/* MPU_RBAR[MPU_RBAR_VALID] Bits */
-#define MPU_RBAR_VALID_OFS ( 4) /* VALID Offset */
-#define MPU_RBAR_VALID (0x00000010) /* */
-/* MPU_RBAR[MPU_RBAR_ADDR] Bits */
-#define MPU_RBAR_ADDR_OFS ( 5) /* ADDR Offset */
-#define MPU_RBAR_ADDR_M (0xffffffe0) /* */
-/* MPU_RASR[MPU_RASR_ENABLE] Bits */
-#define MPU_RASR_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define MPU_RASR_ENABLE (0x00000001) /* */
-/* MPU_RASR[MPU_RASR_SIZE] Bits */
-#define MPU_RASR_SIZE_OFS ( 1) /* SIZE Offset */
-#define MPU_RASR_SIZE_M (0x0000003e) /* */
-#define MPU_RASR_SIZE0 (0x00000002) /* */
-#define MPU_RASR_SIZE1 (0x00000004) /* */
-#define MPU_RASR_SIZE2 (0x00000008) /* */
-#define MPU_RASR_SIZE3 (0x00000010) /* */
-#define MPU_RASR_SIZE4 (0x00000020) /* */
-#define MPU_RASR_SIZE_0 (0x00000000) /* 4KB */
-#define MPU_RASR_SIZE_1 (0x00000002) /* 256MB */
-#define MPU_RASR_SIZE_4 (0x00000008) /* 32B */
-#define MPU_RASR_SIZE_5 (0x0000000a) /* 64B */
-#define MPU_RASR_SIZE_6 (0x0000000c) /* 128B */
-#define MPU_RASR_SIZE_7 (0x0000000e) /* 256B */
-#define MPU_RASR_SIZE_8 (0x00000010) /* 512B */
-#define MPU_RASR_SIZE_9 (0x00000012) /* 1KB */
-#define MPU_RASR_SIZE_10 (0x00000014) /* 2KB */
-#define MPU_RASR_SIZE_12 (0x00000018) /* 8KB */
-#define MPU_RASR_SIZE_13 (0x0000001a) /* 16KB */
-#define MPU_RASR_SIZE_14 (0x0000001c) /* 32KB */
-#define MPU_RASR_SIZE_15 (0x0000001e) /* 64KB */
-#define MPU_RASR_SIZE_16 (0x00000020) /* 128KB */
-#define MPU_RASR_SIZE_17 (0x00000022) /* 256KB */
-#define MPU_RASR_SIZE_18 (0x00000024) /* 512KB */
-#define MPU_RASR_SIZE_19 (0x00000026) /* 1MB */
-#define MPU_RASR_SIZE_20 (0x00000028) /* 2MB */
-#define MPU_RASR_SIZE_21 (0x0000002a) /* 4MB */
-#define MPU_RASR_SIZE_22 (0x0000002c) /* 8MB */
-#define MPU_RASR_SIZE_23 (0x0000002e) /* 16MB */
-#define MPU_RASR_SIZE_24 (0x00000030) /* 32MB */
-#define MPU_RASR_SIZE_25 (0x00000032) /* 64MB */
-#define MPU_RASR_SIZE_26 (0x00000034) /* 128MB */
-#define MPU_RASR_SIZE_28 (0x00000038) /* 512MB */
-#define MPU_RASR_SIZE_29 (0x0000003a) /* 1GB */
-#define MPU_RASR_SIZE_30 (0x0000003c) /* 2GB */
-#define MPU_RASR_SIZE_31 (0x0000003e) /* 4GB */
-/* MPU_RASR[MPU_RASR_SRD] Bits */
-#define MPU_RASR_SRD_OFS ( 8) /* SRD Offset */
-#define MPU_RASR_SRD_M (0x0000ff00) /* */
-/* MPU_RASR[MPU_RASR_B] Bits */
-#define MPU_RASR_B_OFS (16) /* B Offset */
-#define MPU_RASR_B (0x00010000) /* */
-/* MPU_RASR[MPU_RASR_C] Bits */
-#define MPU_RASR_C_OFS (17) /* C Offset */
-#define MPU_RASR_C (0x00020000) /* */
-/* MPU_RASR[MPU_RASR_S] Bits */
-#define MPU_RASR_S_OFS (18) /* S Offset */
-#define MPU_RASR_S (0x00040000) /* */
-/* MPU_RASR[MPU_RASR_TEX] Bits */
-#define MPU_RASR_TEX_OFS (19) /* TEX Offset */
-#define MPU_RASR_TEX_M (0x00380000) /* */
-/* MPU_RASR[MPU_RASR_AP] Bits */
-#define MPU_RASR_AP_OFS (24) /* AP Offset */
-#define MPU_RASR_AP_M (0x07000000) /* */
-#define MPU_RASR_AP0 (0x01000000) /* */
-#define MPU_RASR_AP1 (0x02000000) /* */
-#define MPU_RASR_AP2 (0x04000000) /* */
-#define MPU_RASR_AP_0 (0x00000000) /* Priviliged permissions: No access. User permissions: No access. */
-#define MPU_RASR_AP_1 (0x01000000) /* Priviliged permissions: Read-write. User permissions: No access. */
-#define MPU_RASR_AP_2 (0x02000000) /* Priviliged permissions: Read-write. User permissions: Read-only. */
-#define MPU_RASR_AP_3 (0x03000000) /* Priviliged permissions: Read-write. User permissions: Read-write. */
-#define MPU_RASR_AP_5 (0x05000000) /* Priviliged permissions: Read-only. User permissions: No access. */
-#define MPU_RASR_AP_6 (0x06000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */
-#define MPU_RASR_AP_7 (0x07000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */
-/* MPU_RASR[MPU_RASR_XN] Bits */
-#define MPU_RASR_XN_OFS (28) /* XN Offset */
-#define MPU_RASR_XN (0x10000000) /* */
+/******************************************************************************
+* ITM Bits
+******************************************************************************/
+
+
+/******************************************************************************
+* MPU Bits
+******************************************************************************/
/* Pre-defined bitfield values */
/* MPU_RASR_SIZE Bitfield Bits */
-#define MPU_RASR_SIZE__4 (0x00000008) /* 64B */
-#define MPU_RASR_SIZE__32B (0x00000008) /* 32B */
-#define MPU_RASR_SIZE__64B (0x0000000c) /* 128B */
-#define MPU_RASR_SIZE__256B (0x0000000e) /* 256B */
-#define MPU_RASR_SIZE__512B (0x00000010) /* 512B */
-#define MPU_RASR_SIZE__1K (0x00000012) /* 1KB */
-#define MPU_RASR_SIZE__2K (0x00000014) /* 2KB */
-#define MPU_RASR_SIZE__4K (0x00000016) /* 4KB */
-#define MPU_RASR_SIZE__8K (0x00000018) /* 8KB */
-#define MPU_RASR_SIZE__16K (0x0000001a) /* 16KB */
-#define MPU_RASR_SIZE__32K (0x0000001c) /* 32KB */
-#define MPU_RASR_SIZE__64K (0x0000001e) /* 64KB */
-#define MPU_RASR_SIZE__128K (0x00000020) /* 128KB */
-#define MPU_RASR_SIZE__256K (0x00000022) /* 256KB */
-#define MPU_RASR_SIZE__512K (0x00000024) /* 512KB */
-#define MPU_RASR_SIZE__1M (0x00000026) /* 1MB */
-#define MPU_RASR_SIZE__2M (0x00000028) /* 2MB */
-#define MPU_RASR_SIZE__4M (0x0000002a) /* 4MB */
-#define MPU_RASR_SIZE__8M (0x0000002c) /* 8MB */
-#define MPU_RASR_SIZE__16M (0x0000002e) /* 16MB */
-#define MPU_RASR_SIZE__32M (0x00000030) /* 32MB */
-#define MPU_RASR_SIZE__64M (0x00000032) /* 64MB */
-#define MPU_RASR_SIZE__128M (0x00000034) /* 128MB */
-#define MPU_RASR_SIZE__256M (0x00000036) /* 256MB */
-#define MPU_RASR_SIZE__512M (0x00000038) /* 512MB */
-#define MPU_RASR_SIZE__1G (0x0000003a) /* 1GB */
-#define MPU_RASR_SIZE__2G (0x0000003c) /* 2GB */
-#define MPU_RASR_SIZE__4G (0x0000003e) /* 4GB */
+#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /* 32B */
+#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /* 64B */
+#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /* 128B */
+#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /* 256B */
+#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /* 512B */
+#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /* 1KB */
+#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /* 2KB */
+#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /* 4KB */
+#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /* 8KB */
+#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /* 16KB */
+#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /* 32KB */
+#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /* 64KB */
+#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /* 128KB */
+#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /* 256KB */
+#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /* 512KB */
+#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /* 1MB */
+#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /* 2MB */
+#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /* 4MB */
+#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /* 8MB */
+#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /* 16MB */
+#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /* 32MB */
+#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /* 64MB */
+#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /* 128MB */
+#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /* 256MB */
+#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /* 512MB */
+#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /* 1GB */
+#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /* 2GB */
+#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /* 4GB */
/* MPU_RASR_AP Bitfield Bits */
-#define MPU_RASR_AP_PRV_NO_USR_NO (0x00000000) /* Priviliged permissions: No access. User permissions: No access. */
-#define MPU_RASR_AP_PRV_RW_USR_NO (0x01000000) /* Priviliged permissions: Read-write. User permissions: No access. */
-#define MPU_RASR_AP_PRV_RW_USR_RO (0x02000000) /* Priviliged permissions: Read-write. User permissions: Read-only. */
-#define MPU_RASR_AP_PRV_RW_USR_RW (0x03000000) /* Priviliged permissions: Read-write. User permissions: Read-write. */
-#define MPU_RASR_AP_PRV_RO_USR_NO (0x05000000) /* Priviliged permissions: Read-only. User permissions: No access. */
-#define MPU_RASR_AP_PRV_RO_USR_RO (0x06000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */
+#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /* Privileged permissions: No access. User permissions: No access. */
+#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /* Privileged permissions: Read-write. User permissions: No access. */
+#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /* Privileged permissions: Read-write. User permissions: Read-only. */
+#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /* Privileged permissions: Read-write. User permissions: Read-write. */
+#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /* Privileged permissions: Read-only. User permissions: No access. */
+#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /* Privileged permissions: Read-only. User permissions: Read-only. */
/* MPU_RASR_XN Bitfield Bits */
-#define MPU_RASR_AP_EXEC (0x00000000) /* Instruction access enabled */
-#define MPU_RASR_AP_NOEXEC (0x10000000) /* Instruction access disabled */
+#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /* Instruction access enabled */
+#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /* Instruction access disabled */
-//*****************************************************************************
-// NVIC Bits
-//*****************************************************************************
-/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */
-#define NVIC_IPR0_PRI_0_OFS ( 0) /* PRI_0 Offset */
-#define NVIC_IPR0_PRI_0_M (0x000000ff) /* */
-/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */
-#define NVIC_IPR0_PRI_1_OFS ( 8) /* PRI_1 Offset */
-#define NVIC_IPR0_PRI_1_M (0x0000ff00) /* */
-/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */
-#define NVIC_IPR0_PRI_2_OFS (16) /* PRI_2 Offset */
-#define NVIC_IPR0_PRI_2_M (0x00ff0000) /* */
-/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */
-#define NVIC_IPR0_PRI_3_OFS (24) /* PRI_3 Offset */
-#define NVIC_IPR0_PRI_3_M (0xff000000) /* */
-/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */
-#define NVIC_IPR1_PRI_4_OFS ( 0) /* PRI_4 Offset */
-#define NVIC_IPR1_PRI_4_M (0x000000ff) /* */
-/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */
-#define NVIC_IPR1_PRI_5_OFS ( 8) /* PRI_5 Offset */
-#define NVIC_IPR1_PRI_5_M (0x0000ff00) /* */
-/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */
-#define NVIC_IPR1_PRI_6_OFS (16) /* PRI_6 Offset */
-#define NVIC_IPR1_PRI_6_M (0x00ff0000) /* */
-/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */
-#define NVIC_IPR1_PRI_7_OFS (24) /* PRI_7 Offset */
-#define NVIC_IPR1_PRI_7_M (0xff000000) /* */
-/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */
-#define NVIC_IPR2_PRI_8_OFS ( 0) /* PRI_8 Offset */
-#define NVIC_IPR2_PRI_8_M (0x000000ff) /* */
-/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */
-#define NVIC_IPR2_PRI_9_OFS ( 8) /* PRI_9 Offset */
-#define NVIC_IPR2_PRI_9_M (0x0000ff00) /* */
-/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */
-#define NVIC_IPR2_PRI_10_OFS (16) /* PRI_10 Offset */
-#define NVIC_IPR2_PRI_10_M (0x00ff0000) /* */
-/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */
-#define NVIC_IPR2_PRI_11_OFS (24) /* PRI_11 Offset */
-#define NVIC_IPR2_PRI_11_M (0xff000000) /* */
-/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */
-#define NVIC_IPR3_PRI_12_OFS ( 0) /* PRI_12 Offset */
-#define NVIC_IPR3_PRI_12_M (0x000000ff) /* */
-/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */
-#define NVIC_IPR3_PRI_13_OFS ( 8) /* PRI_13 Offset */
-#define NVIC_IPR3_PRI_13_M (0x0000ff00) /* */
-/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */
-#define NVIC_IPR3_PRI_14_OFS (16) /* PRI_14 Offset */
-#define NVIC_IPR3_PRI_14_M (0x00ff0000) /* */
-/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */
-#define NVIC_IPR3_PRI_15_OFS (24) /* PRI_15 Offset */
-#define NVIC_IPR3_PRI_15_M (0xff000000) /* */
-/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */
-#define NVIC_IPR4_PRI_16_OFS ( 0) /* PRI_16 Offset */
-#define NVIC_IPR4_PRI_16_M (0x000000ff) /* */
-/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */
-#define NVIC_IPR4_PRI_17_OFS ( 8) /* PRI_17 Offset */
-#define NVIC_IPR4_PRI_17_M (0x0000ff00) /* */
-/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */
-#define NVIC_IPR4_PRI_18_OFS (16) /* PRI_18 Offset */
-#define NVIC_IPR4_PRI_18_M (0x00ff0000) /* */
-/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */
-#define NVIC_IPR4_PRI_19_OFS (24) /* PRI_19 Offset */
-#define NVIC_IPR4_PRI_19_M (0xff000000) /* */
-/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */
-#define NVIC_IPR5_PRI_20_OFS ( 0) /* PRI_20 Offset */
-#define NVIC_IPR5_PRI_20_M (0x000000ff) /* */
-/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */
-#define NVIC_IPR5_PRI_21_OFS ( 8) /* PRI_21 Offset */
-#define NVIC_IPR5_PRI_21_M (0x0000ff00) /* */
-/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */
-#define NVIC_IPR5_PRI_22_OFS (16) /* PRI_22 Offset */
-#define NVIC_IPR5_PRI_22_M (0x00ff0000) /* */
-/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */
-#define NVIC_IPR5_PRI_23_OFS (24) /* PRI_23 Offset */
-#define NVIC_IPR5_PRI_23_M (0xff000000) /* */
-/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */
-#define NVIC_IPR6_PRI_24_OFS ( 0) /* PRI_24 Offset */
-#define NVIC_IPR6_PRI_24_M (0x000000ff) /* */
-/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */
-#define NVIC_IPR6_PRI_25_OFS ( 8) /* PRI_25 Offset */
-#define NVIC_IPR6_PRI_25_M (0x0000ff00) /* */
-/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */
-#define NVIC_IPR6_PRI_26_OFS (16) /* PRI_26 Offset */
-#define NVIC_IPR6_PRI_26_M (0x00ff0000) /* */
-/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */
-#define NVIC_IPR6_PRI_27_OFS (24) /* PRI_27 Offset */
-#define NVIC_IPR6_PRI_27_M (0xff000000) /* */
-/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */
-#define NVIC_IPR7_PRI_28_OFS ( 0) /* PRI_28 Offset */
-#define NVIC_IPR7_PRI_28_M (0x000000ff) /* */
-/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */
-#define NVIC_IPR7_PRI_29_OFS ( 8) /* PRI_29 Offset */
-#define NVIC_IPR7_PRI_29_M (0x0000ff00) /* */
-/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */
-#define NVIC_IPR7_PRI_30_OFS (16) /* PRI_30 Offset */
-#define NVIC_IPR7_PRI_30_M (0x00ff0000) /* */
-/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */
-#define NVIC_IPR7_PRI_31_OFS (24) /* PRI_31 Offset */
-#define NVIC_IPR7_PRI_31_M (0xff000000) /* */
-/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */
-#define NVIC_IPR8_PRI_32_OFS ( 0) /* PRI_32 Offset */
-#define NVIC_IPR8_PRI_32_M (0x000000ff) /* */
-/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */
-#define NVIC_IPR8_PRI_33_OFS ( 8) /* PRI_33 Offset */
-#define NVIC_IPR8_PRI_33_M (0x0000ff00) /* */
-/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */
-#define NVIC_IPR8_PRI_34_OFS (16) /* PRI_34 Offset */
-#define NVIC_IPR8_PRI_34_M (0x00ff0000) /* */
-/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */
-#define NVIC_IPR8_PRI_35_OFS (24) /* PRI_35 Offset */
-#define NVIC_IPR8_PRI_35_M (0xff000000) /* */
-/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */
-#define NVIC_IPR9_PRI_36_OFS ( 0) /* PRI_36 Offset */
-#define NVIC_IPR9_PRI_36_M (0x000000ff) /* */
-/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */
-#define NVIC_IPR9_PRI_37_OFS ( 8) /* PRI_37 Offset */
-#define NVIC_IPR9_PRI_37_M (0x0000ff00) /* */
-/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */
-#define NVIC_IPR9_PRI_38_OFS (16) /* PRI_38 Offset */
-#define NVIC_IPR9_PRI_38_M (0x00ff0000) /* */
-/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */
-#define NVIC_IPR9_PRI_39_OFS (24) /* PRI_39 Offset */
-#define NVIC_IPR9_PRI_39_M (0xff000000) /* */
-/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */
-#define NVIC_IPR10_PRI_40_OFS ( 0) /* PRI_40 Offset */
-#define NVIC_IPR10_PRI_40_M (0x000000ff) /* */
-/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */
-#define NVIC_IPR10_PRI_41_OFS ( 8) /* PRI_41 Offset */
-#define NVIC_IPR10_PRI_41_M (0x0000ff00) /* */
-/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */
-#define NVIC_IPR10_PRI_42_OFS (16) /* PRI_42 Offset */
-#define NVIC_IPR10_PRI_42_M (0x00ff0000) /* */
-/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */
-#define NVIC_IPR10_PRI_43_OFS (24) /* PRI_43 Offset */
-#define NVIC_IPR10_PRI_43_M (0xff000000) /* */
-/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */
-#define NVIC_IPR11_PRI_44_OFS ( 0) /* PRI_44 Offset */
-#define NVIC_IPR11_PRI_44_M (0x000000ff) /* */
-/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */
-#define NVIC_IPR11_PRI_45_OFS ( 8) /* PRI_45 Offset */
-#define NVIC_IPR11_PRI_45_M (0x0000ff00) /* */
-/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */
-#define NVIC_IPR11_PRI_46_OFS (16) /* PRI_46 Offset */
-#define NVIC_IPR11_PRI_46_M (0x00ff0000) /* */
-/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */
-#define NVIC_IPR11_PRI_47_OFS (24) /* PRI_47 Offset */
-#define NVIC_IPR11_PRI_47_M (0xff000000) /* */
-/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */
-#define NVIC_IPR12_PRI_48_OFS ( 0) /* PRI_48 Offset */
-#define NVIC_IPR12_PRI_48_M (0x000000ff) /* */
-/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */
-#define NVIC_IPR12_PRI_49_OFS ( 8) /* PRI_49 Offset */
-#define NVIC_IPR12_PRI_49_M (0x0000ff00) /* */
-/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */
-#define NVIC_IPR12_PRI_50_OFS (16) /* PRI_50 Offset */
-#define NVIC_IPR12_PRI_50_M (0x00ff0000) /* */
-/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */
-#define NVIC_IPR12_PRI_51_OFS (24) /* PRI_51 Offset */
-#define NVIC_IPR12_PRI_51_M (0xff000000) /* */
-/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */
-#define NVIC_IPR13_PRI_52_OFS ( 0) /* PRI_52 Offset */
-#define NVIC_IPR13_PRI_52_M (0x000000ff) /* */
-/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */
-#define NVIC_IPR13_PRI_53_OFS ( 8) /* PRI_53 Offset */
-#define NVIC_IPR13_PRI_53_M (0x0000ff00) /* */
-/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */
-#define NVIC_IPR13_PRI_54_OFS (16) /* PRI_54 Offset */
-#define NVIC_IPR13_PRI_54_M (0x00ff0000) /* */
-/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */
-#define NVIC_IPR13_PRI_55_OFS (24) /* PRI_55 Offset */
-#define NVIC_IPR13_PRI_55_M (0xff000000) /* */
-/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */
-#define NVIC_IPR14_PRI_56_OFS ( 0) /* PRI_56 Offset */
-#define NVIC_IPR14_PRI_56_M (0x000000ff) /* */
-/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */
-#define NVIC_IPR14_PRI_57_OFS ( 8) /* PRI_57 Offset */
-#define NVIC_IPR14_PRI_57_M (0x0000ff00) /* */
-/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */
-#define NVIC_IPR14_PRI_58_OFS (16) /* PRI_58 Offset */
-#define NVIC_IPR14_PRI_58_M (0x00ff0000) /* */
-/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */
-#define NVIC_IPR14_PRI_59_OFS (24) /* PRI_59 Offset */
-#define NVIC_IPR14_PRI_59_M (0xff000000) /* */
-/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */
-#define NVIC_IPR15_PRI_60_OFS ( 0) /* PRI_60 Offset */
-#define NVIC_IPR15_PRI_60_M (0x000000ff) /* */
-/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */
-#define NVIC_IPR15_PRI_61_OFS ( 8) /* PRI_61 Offset */
-#define NVIC_IPR15_PRI_61_M (0x0000ff00) /* */
-/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */
-#define NVIC_IPR15_PRI_62_OFS (16) /* PRI_62 Offset */
-#define NVIC_IPR15_PRI_62_M (0x00ff0000) /* */
-/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */
-#define NVIC_IPR15_PRI_63_OFS (24) /* PRI_63 Offset */
-#define NVIC_IPR15_PRI_63_M (0xff000000) /* */
-/* NVIC_STIR[NVIC_STIR_INTID] Bits */
-#define NVIC_STIR_INTID_OFS ( 0) /* INTID Offset */
-#define NVIC_STIR_INTID_M (0x000001ff) /* */
+/******************************************************************************
+* NVIC Bits
+******************************************************************************/
-//*****************************************************************************
-// PCM Bits
-//*****************************************************************************
-/* PCMCTL0[AMR] Bits */
-#define AMR_OFS ( 0) /* AMR Offset */
-#define AMR_M (0x0000000f) /* Active Mode Request */
-#define AMR0 (0x00000001) /* Active Mode Request */
-#define AMR1 (0x00000002) /* Active Mode Request */
-#define AMR2 (0x00000004) /* Active Mode Request */
-#define AMR3 (0x00000008) /* Active Mode Request */
-#define AMR_0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
-#define AMR_1 (0x00000001) /* LDO based Active Mode at Core voltage setting 1. */
-#define AMR_4 (0x00000004) /* DC-DC based Active Mode at Core voltage setting 0. */
-#define AMR_5 (0x00000005) /* DC-DC based Active Mode at Core voltage setting 1. */
-#define AMR_8 (0x00000008) /* Low-Frequency Active Mode at Core voltage setting 0. */
-#define AMR_9 (0x00000009) /* Low-Frequency Active Mode at Core voltage setting 1. */
-#define AMR__AM_LDO_VCORE0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
-#define AMR__AM_LDO_VCORE1 (0x00000001) /* LDO based Active Mode at Core voltage setting 1. */
-#define AMR__AM_DCDC_VCORE0 (0x00000004) /* DC-DC based Active Mode at Core voltage setting 0. */
-#define AMR__AM_DCDC_VCORE1 (0x00000005) /* DC-DC based Active Mode at Core voltage setting 1. */
-#define AMR__AM_LF_VCORE0 (0x00000008) /* Low-Frequency Active Mode at Core voltage setting 0. */
-#define AMR__AM_LF_VCORE1 (0x00000009) /* Low-Frequency Active Mode at Core voltage setting 1. */
-/* PCMCTL0[LPMR] Bits */
-#define LPMR_OFS ( 4) /* LPMR Offset */
-#define LPMR_M (0x000000f0) /* Low Power Mode Request */
-#define LPMR0 (0x00000010) /* Low Power Mode Request */
-#define LPMR1 (0x00000020) /* Low Power Mode Request */
-#define LPMR2 (0x00000040) /* Low Power Mode Request */
-#define LPMR3 (0x00000080) /* Low Power Mode Request */
-#define LPMR_0 (0x00000000) /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
-#define LPMR_10 (0x000000a0) /* LPM3.5. Core voltage setting 0. */
-#define LPMR_12 (0x000000c0) /* LPM4.5 */
-#define LPMR__LPM3 (0x00000000) /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
-#define LPMR__LPM35 (0x000000a0) /* LPM3.5. Core voltage setting 0. */
-#define LPMR__LPM45 (0x000000c0) /* LPM4.5 */
-/* PCMCTL0[CPM] Bits */
-#define CPM_OFS ( 8) /* CPM Offset */
-#define CPM_M (0x00003f00) /* Current Power Mode */
-#define CPM0 (0x00000100) /* Current Power Mode */
-#define CPM1 (0x00000200) /* Current Power Mode */
-#define CPM2 (0x00000400) /* Current Power Mode */
-#define CPM3 (0x00000800) /* Current Power Mode */
-#define CPM4 (0x00001000) /* Current Power Mode */
-#define CPM5 (0x00002000) /* Current Power Mode */
-#define CPM_0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
-#define CPM_1 (0x00000100) /* LDO based Active Mode at Core voltage setting 1. */
-#define CPM_4 (0x00000400) /* DC-DC based Active Mode at Core voltage setting 0. */
-#define CPM_5 (0x00000500) /* DC-DC based Active Mode at Core voltage setting 1. */
-#define CPM_8 (0x00000800) /* Low-Frequency Active Mode at Core voltage setting 0. */
-#define CPM_9 (0x00000900) /* Low-Frequency Active Mode at Core voltage setting 1. */
-#define CPM_16 (0x00001000) /* LDO based LPM0 at Core voltage setting 0. */
-#define CPM_17 (0x00001100) /* LDO based LPM0 at Core voltage setting 1. */
-#define CPM_20 (0x00001400) /* DC-DC based LPM0 at Core voltage setting 0. */
-#define CPM_21 (0x00001500) /* DC-DC based LPM0 at Core voltage setting 1. */
-#define CPM_24 (0x00001800) /* Low-Frequency LPM0 at Core voltage setting 0. */
-#define CPM_25 (0x00001900) /* Low-Frequency LPM0 at Core voltage setting 1. */
-#define CPM_32 (0x00002000) /* LPM3 */
-#define CPM__AM_LDO_VCORE0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
-#define CPM__AM_LDO_VCORE1 (0x00000100) /* LDO based Active Mode at Core voltage setting 1. */
-#define CPM__AM_DCDC_VCORE0 (0x00000400) /* DC-DC based Active Mode at Core voltage setting 0. */
-#define CPM__AM_DCDC_VCORE1 (0x00000500) /* DC-DC based Active Mode at Core voltage setting 1. */
-#define CPM__AM_LF_VCORE0 (0x00000800) /* Low-Frequency Active Mode at Core voltage setting 0. */
-#define CPM__AM_LF_VCORE1 (0x00000900) /* Low-Frequency Active Mode at Core voltage setting 1. */
-#define CPM__LPM0_LDO_VCORE0 (0x00001000) /* LDO based LPM0 at Core voltage setting 0. */
-#define CPM__LPM0_LDO_VCORE1 (0x00001100) /* LDO based LPM0 at Core voltage setting 1. */
-#define CPM__LPM0_DCDC_VCORE0 (0x00001400) /* DC-DC based LPM0 at Core voltage setting 0. */
-#define CPM__LPM0_DCDC_VCORE1 (0x00001500) /* DC-DC based LPM0 at Core voltage setting 1. */
-#define CPM__LPM0_LF_VCORE0 (0x00001800) /* Low-Frequency LPM0 at Core voltage setting 0. */
-#define CPM__LPM0_LF_VCORE1 (0x00001900) /* Low-Frequency LPM0 at Core voltage setting 1. */
-#define CPM__LPM3 (0x00002000) /* LPM3 */
-/* PCMCTL0[PCMKEY] Bits */
-#define PCMKEY_OFS (16) /* PCMKEY Offset */
-#define PCMKEY_M (0xffff0000) /* PCM key */
-/* PCMCTL1[LOCKLPM5] Bits */
-#define LOCKLPM5_OFS ( 0) /* LOCKLPM5 Offset */
-#define LOCKLPM5 (0x00000001) /* Lock LPM5 */
-/* PCMCTL1[LOCKBKUP] Bits */
-#define LOCKBKUP_OFS ( 1) /* LOCKBKUP Offset */
-#define LOCKBKUP (0x00000002) /* Lock Backup */
-/* PCMCTL1[FORCE_LPM_ENTRY] Bits */
-#define FORCE_LPM_ENTRY_OFS ( 2) /* FORCE_LPM_ENTRY Offset */
-#define FORCE_LPM_ENTRY (0x00000004) /* Force LPM entry */
-/* PCMCTL1[PMR_BUSY] Bits */
-#define PMR_BUSY_OFS ( 8) /* PMR_BUSY Offset */
-#define PMR_BUSY (0x00000100) /* Power mode request busy flag */
-/* PCMCTL1[PCMKEY] Bits */
-//#define PCMKEY_OFS (16) /* PCMKEY Offset */
-//#define PCMKEY_M (0xffff0000) /* PCM key */
-/* PCMIE[LPM_INVALID_TR_IE] Bits */
-#define LPM_INVALID_TR_IE_OFS ( 0) /* LPM_INVALID_TR_IE Offset */
-#define LPM_INVALID_TR_IE (0x00000001) /* LPM invalid transition interrupt enable */
-/* PCMIE[LPM_INVALID_CLK_IE] Bits */
-#define LPM_INVALID_CLK_IE_OFS ( 1) /* LPM_INVALID_CLK_IE Offset */
-#define LPM_INVALID_CLK_IE (0x00000002) /* LPM invalid clock interrupt enable */
-/* PCMIE[AM_INVALID_TR_IE] Bits */
-#define AM_INVALID_TR_IE_OFS ( 2) /* AM_INVALID_TR_IE Offset */
-#define AM_INVALID_TR_IE (0x00000004) /* Active mode invalid transition interrupt enable */
-/* PCMIE[DCDC_ERROR_IE] Bits */
-#define DCDC_ERROR_IE_OFS ( 6) /* DCDC_ERROR_IE Offset */
-#define DCDC_ERROR_IE (0x00000040) /* DC-DC error interrupt enable */
-/* PCMIFG[LPM_INVALID_TR_IFG] Bits */
-#define LPM_INVALID_TR_IFG_OFS ( 0) /* LPM_INVALID_TR_IFG Offset */
-#define LPM_INVALID_TR_IFG (0x00000001) /* LPM invalid transition flag */
-/* PCMIFG[LPM_INVALID_CLK_IFG] Bits */
-#define LPM_INVALID_CLK_IFG_OFS ( 1) /* LPM_INVALID_CLK_IFG Offset */
-#define LPM_INVALID_CLK_IFG (0x00000002) /* LPM invalid clock flag */
-/* PCMIFG[AM_INVALID_TR_IFG] Bits */
-#define AM_INVALID_TR_IFG_OFS ( 2) /* AM_INVALID_TR_IFG Offset */
-#define AM_INVALID_TR_IFG (0x00000004) /* Active mode invalid transition flag */
-/* PCMIFG[DCDC_ERROR_IFG] Bits */
-#define DCDC_ERROR_IFG_OFS ( 6) /* DCDC_ERROR_IFG Offset */
-#define DCDC_ERROR_IFG (0x00000040) /* DC-DC error flag */
-/* PCMCLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */
-#define CLR_LPM_INVALID_TR_IFG_OFS ( 0) /* CLR_LPM_INVALID_TR_IFG Offset */
-#define CLR_LPM_INVALID_TR_IFG (0x00000001) /* Clear LPM invalid transition flag */
-/* PCMCLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */
-#define CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /* CLR_LPM_INVALID_CLK_IFG Offset */
-#define CLR_LPM_INVALID_CLK_IFG (0x00000002) /* Clear LPM invalid clock flag */
-/* PCMCLRIFG[CLR_AM_INVALID_TR_IFG] Bits */
-#define CLR_AM_INVALID_TR_IFG_OFS ( 2) /* CLR_AM_INVALID_TR_IFG Offset */
-#define CLR_AM_INVALID_TR_IFG (0x00000004) /* Clear active mode invalid transition flag */
-/* PCMCLRIFG[CLR_DCDC_ERROR_IFG] Bits */
-#define CLR_DCDC_ERROR_IFG_OFS ( 6) /* CLR_DCDC_ERROR_IFG Offset */
-#define CLR_DCDC_ERROR_IFG (0x00000040) /* Clear DC-DC error flag */
+/******************************************************************************
+* PCM Bits
+******************************************************************************/
+/* PCM_CTL0[AMR] Bits */
+#define PCM_CTL0_AMR_OFS ( 0) /**< AMR Bit Offset */
+#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /**< AMR Bit Mask */
+#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /**< AMR Bit 0 */
+#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /**< AMR Bit 1 */
+#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /**< AMR Bit 2 */
+#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /**< AMR Bit 3 */
+#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /**< LDO based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /**< DC-DC based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /**< DC-DC based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /**< Low-Frequency Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /**< Low-Frequency Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /**< LDO based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /**< DC-DC based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /**< DC-DC based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /**< Low-Frequency Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /**< Low-Frequency Active Mode at Core voltage setting 1. */
+/* PCM_CTL0[LPMR] Bits */
+#define PCM_CTL0_LPMR_OFS ( 4) /**< LPMR Bit Offset */
+#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /**< LPMR Bit Mask */
+#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /**< LPMR Bit 0 */
+#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /**< LPMR Bit 1 */
+#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /**< LPMR Bit 2 */
+#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /**< LPMR Bit 3 */
+#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /**< LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
+#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /**< LPM3.5. Core voltage setting 0. */
+#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /**< LPM4.5 */
+#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /**< LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
+#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /**< LPM3.5. Core voltage setting 0. */
+#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /**< LPM4.5 */
+/* PCM_CTL0[CPM] Bits */
+#define PCM_CTL0_CPM_OFS ( 8) /**< CPM Bit Offset */
+#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /**< CPM Bit Mask */
+#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /**< CPM Bit 0 */
+#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /**< CPM Bit 1 */
+#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /**< CPM Bit 2 */
+#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /**< CPM Bit 3 */
+#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /**< CPM Bit 4 */
+#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /**< CPM Bit 5 */
+#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /**< LDO based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /**< DC-DC based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /**< DC-DC based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /**< Low-Frequency Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /**< Low-Frequency Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /**< LDO based LPM0 at Core voltage setting 0. */
+#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /**< LDO based LPM0 at Core voltage setting 1. */
+#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /**< DC-DC based LPM0 at Core voltage setting 0. */
+#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /**< DC-DC based LPM0 at Core voltage setting 1. */
+#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /**< Low-Frequency LPM0 at Core voltage setting 0. */
+#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /**< Low-Frequency LPM0 at Core voltage setting 1. */
+#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /**< LPM3 */
+#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /**< LDO based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /**< LDO based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /**< DC-DC based Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /**< DC-DC based Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /**< Low-Frequency Active Mode at Core voltage setting 0. */
+#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /**< Low-Frequency Active Mode at Core voltage setting 1. */
+#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /**< LDO based LPM0 at Core voltage setting 0. */
+#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /**< LDO based LPM0 at Core voltage setting 1. */
+#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /**< DC-DC based LPM0 at Core voltage setting 0. */
+#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /**< DC-DC based LPM0 at Core voltage setting 1. */
+#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /**< Low-Frequency LPM0 at Core voltage setting 0. */
+#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /**< Low-Frequency LPM0 at Core voltage setting 1. */
+#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /**< LPM3 */
+/* PCM_CTL0[KEY] Bits */
+#define PCM_CTL0_KEY_OFS (16) /**< PCMKEY Bit Offset */
+#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /**< PCMKEY Bit Mask */
+/* PCM_CTL1[LOCKLPM5] Bits */
+#define PCM_CTL1_LOCKLPM5_OFS ( 0) /**< LOCKLPM5 Bit Offset */
+#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /**< Lock LPM5 */
+/* PCM_CTL1[LOCKBKUP] Bits */
+#define PCM_CTL1_LOCKBKUP_OFS ( 1) /**< LOCKBKUP Bit Offset */
+#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /**< Lock Backup */
+/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */
+#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /**< FORCE_LPM_ENTRY Bit Offset */
+#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /**< Force LPM entry */
+/* PCM_CTL1[PMR_BUSY] Bits */
+#define PCM_CTL1_PMR_BUSY_OFS ( 8) /**< PMR_BUSY Bit Offset */
+#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /**< Power mode request busy flag */
+/* PCM_CTL1[KEY] Bits */
+#define PCM_CTL1_KEY_OFS (16) /**< PCMKEY Bit Offset */
+#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /**< PCMKEY Bit Mask */
+/* PCM_IE[LPM_INVALID_TR_IE] Bits */
+#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /**< LPM_INVALID_TR_IE Bit Offset */
+#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /**< LPM invalid transition interrupt enable */
+/* PCM_IE[LPM_INVALID_CLK_IE] Bits */
+#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /**< LPM_INVALID_CLK_IE Bit Offset */
+#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /**< LPM invalid clock interrupt enable */
+/* PCM_IE[AM_INVALID_TR_IE] Bits */
+#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /**< AM_INVALID_TR_IE Bit Offset */
+#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /**< Active mode invalid transition interrupt enable */
+/* PCM_IE[DCDC_ERROR_IE] Bits */
+#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /**< DCDC_ERROR_IE Bit Offset */
+#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /**< DC-DC error interrupt enable */
+/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */
+#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /**< LPM_INVALID_TR_IFG Bit Offset */
+#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /**< LPM invalid transition flag */
+/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */
+#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /**< LPM_INVALID_CLK_IFG Bit Offset */
+#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /**< LPM invalid clock flag */
+/* PCM_IFG[AM_INVALID_TR_IFG] Bits */
+#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /**< AM_INVALID_TR_IFG Bit Offset */
+#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /**< Active mode invalid transition flag */
+/* PCM_IFG[DCDC_ERROR_IFG] Bits */
+#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /**< DCDC_ERROR_IFG Bit Offset */
+#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /**< DC-DC error flag */
+/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */
+#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /**< CLR_LPM_INVALID_TR_IFG Bit Offset */
+#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /**< Clear LPM invalid transition flag */
+/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */
+#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /**< CLR_LPM_INVALID_CLK_IFG Bit Offset */
+#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /**< Clear LPM invalid clock flag */
+/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */
+#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /**< CLR_AM_INVALID_TR_IFG Bit Offset */
+#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /**< Clear active mode invalid transition flag */
+/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */
+#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /**< CLR_DCDC_ERROR_IFG Bit Offset */
+#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /**< Clear DC-DC error flag */
/* Pre-defined bitfield values */
-#define PCM_PMR_KEY_VAL (0x695A0000) /* PCM key value */
-#define PCM_CTL_KEY_VAL (0x695A0000) /* PCM key value */
+#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /* PCM key value */
+#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /* PCM key value */
-//*****************************************************************************
-// PMAP Bits
-//*****************************************************************************
-/* PMAPCTL[PMAPLOCKED] Bits */
-#define PMAPLOCKED_OFS ( 0) /* PMAPLOCKED Offset */
-#define PMAPLOCKED (0x0001) /* Port mapping lock bit */
-/* PMAPCTL[PMAPRECFG] Bits */
-#define PMAPRECFG_OFS ( 1) /* PMAPRECFG Offset */
-#define PMAPRECFG (0x0002) /* Port mapping reconfiguration control bit */
+/******************************************************************************
+* PMAP Bits
+******************************************************************************/
+/* PMAP_CTL[LOCKED] Bits */
+#define PMAP_CTL_LOCKED_OFS ( 0) /**< PMAPLOCKED Bit Offset */
+#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /**< Port mapping lock bit */
+/* PMAP_CTL[PRECFG] Bits */
+#define PMAP_CTL_PRECFG_OFS ( 1) /**< PMAPRECFG Bit Offset */
+#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /**< Port mapping reconfiguration control bit */
/* Pre-defined bitfield values */
-#define PM_NONE 0
-#define PM_UCA0CLK 1
-#define PM_UCA0RXD 2
-#define PM_UCA0SOMI 2
-#define PM_UCA0TXD 3
-#define PM_UCA0SIMO 3
-#define PM_UCB0CLK 4
-#define PM_UCB0SDA 5
-#define PM_UCB0SIMO 5
-#define PM_UCB0SCL 6
-#define PM_UCB0SOMI 6
-#define PM_UCA1STE 7
-#define PM_UCA1CLK 8
-#define PM_UCA1RXD 9
-#define PM_UCA1SOMI 9
-#define PM_UCA1TXD 10
-#define PM_UCA1SIMO 10
-#define PM_UCA2STE 11
-#define PM_UCA2CLK 12
-#define PM_UCA2RXD 13
-#define PM_UCA2SOMI 13
-#define PM_UCA2TXD 14
-#define PM_UCA2SIMO 14
-#define PM_UCB2STE 15
-#define PM_UCB2CLK 16
-#define PM_UCB2SDA 17
-#define PM_UCB2SIMO 17
-#define PM_UCB2SCL 18
-#define PM_UCB2SOMI 18
-#define PM_TA0CCR0A 19
-#define PM_TA0CCR1A 20
-#define PM_TA0CCR2A 21
-#define PM_TA0CCR3A 22
-#define PM_TA0CCR4A 23
-#define PM_TA1CCR1A 24
-#define PM_TA1CCR2A 25
-#define PM_TA1CCR3A 26
-#define PM_TA1CCR4A 27
-#define PM_TA0CLK 28
-#define PM_CE0OUT 28
-#define PM_TA1CLK 29
-#define PM_CE1OUT 29
-#define PM_DMAE0 30
-#define PM_SMCLK 30
-#define PM_ANALOG 31
+#define PMAP_NONE 0
+#define PMAP_UCA0CLK 1
+#define PMAP_UCA0RXD 2
+#define PMAP_UCA0SOMI 2
+#define PMAP_UCA0TXD 3
+#define PMAP_UCA0SIMO 3
+#define PMAP_UCB0CLK 4
+#define PMAP_UCB0SDA 5
+#define PMAP_UCB0SIMO 5
+#define PMAP_UCB0SCL 6
+#define PMAP_UCB0SOMI 6
+#define PMAP_UCA1STE 7
+#define PMAP_UCA1CLK 8
+#define PMAP_UCA1RXD 9
+#define PMAP_UCA1SOMI 9
+#define PMAP_UCA1TXD 10
+#define PMAP_UCA1SIMO 10
+#define PMAP_UCA2STE 11
+#define PMAP_UCA2CLK 12
+#define PMAP_UCA2RXD 13
+#define PMAP_UCA2SOMI 13
+#define PMAP_UCA2TXD 14
+#define PMAP_UCA2SIMO 14
+#define PMAP_UCB2STE 15
+#define PMAP_UCB2CLK 16
+#define PMAP_UCB2SDA 17
+#define PMAP_UCB2SIMO 17
+#define PMAP_UCB2SCL 18
+#define PMAP_UCB2SOMI 18
+#define PMAP_TA0CCR0A 19
+#define PMAP_TA0CCR1A 20
+#define PMAP_TA0CCR2A 21
+#define PMAP_TA0CCR3A 22
+#define PMAP_TA0CCR4A 23
+#define PMAP_TA1CCR1A 24
+#define PMAP_TA1CCR2A 25
+#define PMAP_TA1CCR3A 26
+#define PMAP_TA1CCR4A 27
+#define PMAP_TA0CLK 28
+#define PMAP_CE0OUT 28
+#define PMAP_TA1CLK 29
+#define PMAP_CE1OUT 29
+#define PMAP_DMAE0 30
+#define PMAP_SMCLK 30
+#define PMAP_ANALOG 31
-#define PMAP_KEYID_VAL (0x2D52) /* Port mapping controller write access key */
-
+#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /**< Port Mapping Key */
-//*****************************************************************************
-// PSS Bits
-//*****************************************************************************
-/* PSSKEY[PSSKEY] Bits */
-#define PSSKEY_OFS ( 0) /* PSSKEY Offset */
-#define PSSKEY_M (0x0000ffff) /* PSS control key */
-/* PSSCTL0[SVSMHOFF] Bits */
-#define SVSMHOFF_OFS ( 0) /* SVSMHOFF Offset */
-#define SVSMHOFF (0x00000001) /* SVSM high-side off */
-/* PSSCTL0[SVSMHLP] Bits */
-#define SVSMHLP_OFS ( 1) /* SVSMHLP Offset */
-#define SVSMHLP (0x00000002) /* SVSM high-side low power normal performance mode */
-/* PSSCTL0[SVSMHS] Bits */
-#define SVSMHS_OFS ( 2) /* SVSMHS Offset */
-#define SVSMHS (0x00000004) /* Supply supervisor or monitor selection for the high-side */
-/* PSSCTL0[SVSMHTH] Bits */
-#define SVSMHTH_OFS ( 3) /* SVSMHTH Offset */
-#define SVSMHTH_M (0x00000038) /* SVSM high-side reset voltage level */
-/* PSSCTL0[SVMHOE] Bits */
-#define SVMHOE_OFS ( 6) /* SVMHOE Offset */
-#define SVMHOE (0x00000040) /* SVSM high-side output enable */
-/* PSSCTL0[SVMHOUTPOLAL] Bits */
-#define SVMHOUTPOLAL_OFS ( 7) /* SVMHOUTPOLAL Offset */
-#define SVMHOUTPOLAL (0x00000080) /* SVMHOUT pin polarity active low */
-/* PSSCTL0[SVSLOFF] Bits */
-#define SVSLOFF_OFS ( 8) /* SVSLOFF Offset */
-#define SVSLOFF (0x00000100) /* SVS low-side off */
-/* PSSCTL0[SVSLLP] Bits */
-#define SVSLLP_OFS ( 9) /* SVSLLP Offset */
-#define SVSLLP (0x00000200) /* SVS low-side low power normal performance mode */
-/* PSSCTL0[DCDC_FORCE] Bits */
-#define DCDC_FORCE_OFS (10) /* DCDC_FORCE Offset */
-#define DCDC_FORCE (0x00000400) /* Disables automatic supply voltage detection */
-/* PSSCTL0[VCORETRAN] Bits */
-#define VCORETRAN_OFS (12) /* VCORETRAN Offset */
-#define VCORETRAN_M (0x00003000) /* Controls VCORE Level Transition time */
-#define VCORETRAN0 (0x00001000) /* Controls VCORE Level Transition time */
-#define VCORETRAN1 (0x00002000) /* Controls VCORE Level Transition time */
-#define VCORETRAN_0 (0x00000000) /* 32 ?s / 100 mV */
-#define VCORETRAN_1 (0x00001000) /* 64 ?s / 100 mV */
-#define VCORETRAN_2 (0x00002000) /* 128 ?s / 100 mV (default) */
-#define VCORETRAN_3 (0x00003000) /* 256 ?s / 100 mV */
-#define VCORETRAN__32 (0x00000000) /* 32 ?s / 100 mV */
-#define VCORETRAN__64 (0x00001000) /* 64 ?s / 100 mV */
-#define VCORETRAN__128 (0x00002000) /* 128 ?s / 100 mV (default) */
-#define VCORETRAN__256 (0x00003000) /* 256 ?s / 100 mV */
-/* PSSIE[SVSMHIE] Bits */
-#define SVSMHIE_OFS ( 1) /* SVSMHIE Offset */
-#define SVSMHIE (0x00000002) /* High-side SVSM interrupt enable */
-/* PSSIFG[SVSMHIFG] Bits */
-#define SVSMHIFG_OFS ( 1) /* SVSMHIFG Offset */
-#define SVSMHIFG (0x00000002) /* High-side SVSM interrupt flag */
-/* PSSCLRIFG[CLRSVSMHIFG] Bits */
-#define CLRSVSMHIFG_OFS ( 1) /* CLRSVSMHIFG Offset */
-#define CLRSVSMHIFG (0x00000002) /* SVSMH clear interrupt flag */
+
+/******************************************************************************
+* PSS Bits
+******************************************************************************/
+/* PSS_KEY[KEY] Bits */
+#define PSS_KEY_KEY_OFS ( 0) /**< PSSKEY Bit Offset */
+#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /**< PSSKEY Bit Mask */
+/* PSS_CTL0[SVSMHOFF] Bits */
+#define PSS_CTL0_SVSMHOFF_OFS ( 0) /**< SVSMHOFF Bit Offset */
+#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /**< SVSM high-side off */
+/* PSS_CTL0[SVSMHLP] Bits */
+#define PSS_CTL0_SVSMHLP_OFS ( 1) /**< SVSMHLP Bit Offset */
+#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /**< SVSM high-side low power normal performance mode */
+/* PSS_CTL0[SVSMHS] Bits */
+#define PSS_CTL0_SVSMHS_OFS ( 2) /**< SVSMHS Bit Offset */
+#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /**< Supply supervisor or monitor selection for the high-side */
+/* PSS_CTL0[SVSMHTH] Bits */
+#define PSS_CTL0_SVSMHTH_OFS ( 3) /**< SVSMHTH Bit Offset */
+#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /**< SVSMHTH Bit Mask */
+/* PSS_CTL0[SVMHOE] Bits */
+#define PSS_CTL0_SVMHOE_OFS ( 6) /**< SVMHOE Bit Offset */
+#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /**< SVSM high-side output enable */
+/* PSS_CTL0[SVMHOUTPOLAL] Bits */
+#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /**< SVMHOUTPOLAL Bit Offset */
+#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /**< SVMHOUT pin polarity active low */
+/* PSS_CTL0[DCDC_FORCE] Bits */
+#define PSS_CTL0_DCDC_FORCE_OFS (10) /**< DCDC_FORCE Bit Offset */
+#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /**< Force DC-DC regulator operation */
+/* PSS_CTL0[VCORETRAN] Bits */
+#define PSS_CTL0_VCORETRAN_OFS (12) /**< VCORETRAN Bit Offset */
+#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /**< VCORETRAN Bit Mask */
+#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /**< VCORETRAN Bit 0 */
+#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /**< VCORETRAN Bit 1 */
+#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /**< 32 ?s / 100 mV */
+#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /**< 64 ?s / 100 mV */
+#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /**< 128 ?s / 100 mV (default) */
+#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /**< 256 ?s / 100 mV */
+#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /**< 32 ?s / 100 mV */
+#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /**< 64 ?s / 100 mV */
+#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /**< 128 ?s / 100 mV (default) */
+#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /**< 256 ?s / 100 mV */
+/* PSS_IE[SVSMHIE] Bits */
+#define PSS_IE_SVSMHIE_OFS ( 1) /**< SVSMHIE Bit Offset */
+#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /**< High-side SVSM interrupt enable */
+/* PSS_IFG[SVSMHIFG] Bits */
+#define PSS_IFG_SVSMHIFG_OFS ( 1) /**< SVSMHIFG Bit Offset */
+#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /**< High-side SVSM interrupt flag */
+/* PSS_CLRIFG[CLRSVSMHIFG] Bits */
+#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /**< CLRSVSMHIFG Bit Offset */
+#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /**< SVSMH clear interrupt flag */
/* Pre-defined bitfield values */
-#define PSS_KEY_KEY_VAL (0x0000695A) /* PSS control key value */
+#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /* PSS control key value */
-//*****************************************************************************
-// REF_A Bits
-//*****************************************************************************
-/* REFCTL0[REFON] Bits */
-#define REFON_OFS ( 0) /* REFON Offset */
-#define REFON (0x0001) /* Reference enable */
-/* REFCTL0[REFOUT] Bits */
-#define REFOUT_OFS ( 1) /* REFOUT Offset */
-#define REFOUT (0x0002) /* Reference output buffer */
-/* REFCTL0[REFTCOFF] Bits */
-#define REFTCOFF_OFS ( 3) /* REFTCOFF Offset */
-#define REFTCOFF (0x0008) /* Temperature sensor disabled */
-/* REFCTL0[REFVSEL] Bits */
-#define REFVSEL_OFS ( 4) /* REFVSEL Offset */
-#define REFVSEL_M (0x0030) /* Reference voltage level select */
-#define REFVSEL0 (0x0010) /* Reference voltage level select */
-#define REFVSEL1 (0x0020) /* Reference voltage level select */
-#define REFVSEL_0 (0x0000) /* 1.2 V available when reference requested or REFON = 1 */
-#define REFVSEL_1 (0x0010) /* 1.45 V available when reference requested or REFON = 1 */
-#define REFVSEL_3 (0x0030) /* 2.5 V available when reference requested or REFON = 1 */
-/* REFCTL0[REFGENOT] Bits */
-#define REFGENOT_OFS ( 6) /* REFGENOT Offset */
-#define REFGENOT (0x0040) /* Reference generator one-time trigger */
-/* REFCTL0[REFBGOT] Bits */
-#define REFBGOT_OFS ( 7) /* REFBGOT Offset */
-#define REFBGOT (0x0080) /* Bandgap and bandgap buffer one-time trigger */
-/* REFCTL0[REFGENACT] Bits */
-#define REFGENACT_OFS ( 8) /* REFGENACT Offset */
-#define REFGENACT (0x0100) /* Reference generator active */
-/* REFCTL0[REFBGACT] Bits */
-#define REFBGACT_OFS ( 9) /* REFBGACT Offset */
-#define REFBGACT (0x0200) /* Reference bandgap active */
-/* REFCTL0[REFGENBUSY] Bits */
-#define REFGENBUSY_OFS (10) /* REFGENBUSY Offset */
-#define REFGENBUSY (0x0400) /* Reference generator busy */
-/* REFCTL0[BGMODE] Bits */
-#define BGMODE_OFS (11) /* BGMODE Offset */
-#define BGMODE (0x0800) /* Bandgap mode */
-/* REFCTL0[REFGENRDY] Bits */
-#define REFGENRDY_OFS (12) /* REFGENRDY Offset */
-#define REFGENRDY (0x1000) /* Variable reference voltage ready status */
-/* REFCTL0[REFBGRDY] Bits */
-#define REFBGRDY_OFS (13) /* REFBGRDY Offset */
-#define REFBGRDY (0x2000) /* Buffered bandgap voltage ready status */
+/******************************************************************************
+* REF_A Bits
+******************************************************************************/
+/* REF_A_CTL0[ON] Bits */
+#define REF_A_CTL0_ON_OFS ( 0) /**< REFON Bit Offset */
+#define REF_A_CTL0_ON ((uint16_t)0x0001) /**< Reference enable */
+/* REF_A_CTL0[OUT] Bits */
+#define REF_A_CTL0_OUT_OFS ( 1) /**< REFOUT Bit Offset */
+#define REF_A_CTL0_OUT ((uint16_t)0x0002) /**< Reference output buffer */
+/* REF_A_CTL0[TCOFF] Bits */
+#define REF_A_CTL0_TCOFF_OFS ( 3) /**< REFTCOFF Bit Offset */
+#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /**< Temperature sensor disabled */
+/* REF_A_CTL0[VSEL] Bits */
+#define REF_A_CTL0_VSEL_OFS ( 4) /**< REFVSEL Bit Offset */
+#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /**< REFVSEL Bit Mask */
+#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /**< VSEL Bit 0 */
+#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /**< VSEL Bit 1 */
+#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /**< 1.2 V available when reference requested or REFON = 1 */
+#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /**< 1.45 V available when reference requested or REFON = 1 */
+#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /**< 2.5 V available when reference requested or REFON = 1 */
+/* REF_A_CTL0[GENOT] Bits */
+#define REF_A_CTL0_GENOT_OFS ( 6) /**< REFGENOT Bit Offset */
+#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /**< Reference generator one-time trigger */
+/* REF_A_CTL0[BGOT] Bits */
+#define REF_A_CTL0_BGOT_OFS ( 7) /**< REFBGOT Bit Offset */
+#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /**< Bandgap and bandgap buffer one-time trigger */
+/* REF_A_CTL0[GENACT] Bits */
+#define REF_A_CTL0_GENACT_OFS ( 8) /**< REFGENACT Bit Offset */
+#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /**< Reference generator active */
+/* REF_A_CTL0[BGACT] Bits */
+#define REF_A_CTL0_BGACT_OFS ( 9) /**< REFBGACT Bit Offset */
+#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /**< Reference bandgap active */
+/* REF_A_CTL0[GENBUSY] Bits */
+#define REF_A_CTL0_GENBUSY_OFS (10) /**< REFGENBUSY Bit Offset */
+#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /**< Reference generator busy */
+/* REF_A_CTL0[BGMODE] Bits */
+#define REF_A_CTL0_BGMODE_OFS (11) /**< BGMODE Bit Offset */
+#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /**< Bandgap mode */
+/* REF_A_CTL0[GENRDY] Bits */
+#define REF_A_CTL0_GENRDY_OFS (12) /**< REFGENRDY Bit Offset */
+#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /**< Variable reference voltage ready status */
+/* REF_A_CTL0[BGRDY] Bits */
+#define REF_A_CTL0_BGRDY_OFS (13) /**< REFBGRDY Bit Offset */
+#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /**< Buffered bandgap voltage ready status */
-//*****************************************************************************
-// RSTCTL Bits
-//*****************************************************************************
-/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_SOFT_REQ] Bits */
-#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /* SOFT_REQ Offset */
-#define RSTCTL_RESET_REQ_SOFT_REQ (0x00000001) /* Soft Reset request */
-/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_HARD_REQ] Bits */
-#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /* HARD_REQ Offset */
-#define RSTCTL_RESET_REQ_HARD_REQ (0x00000002) /* Hard Reset request */
-/* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_RSTKEY] Bits */
-#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /* RSTKEY Offset */
-#define RSTCTL_RESET_REQ_RSTKEY_M (0x0000ff00) /* Write key to unlock reset request bits */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC0] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /* SRC0 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC0 (0x00000001) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC1] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /* SRC1 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC1 (0x00000002) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC2] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /* SRC2 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC2 (0x00000004) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC3] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /* SRC3 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC3 (0x00000008) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC4] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /* SRC4 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC4 (0x00000010) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC5] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /* SRC5 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC5 (0x00000020) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC6] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /* SRC6 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC6 (0x00000040) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC7] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /* SRC7 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC7 (0x00000080) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC8] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /* SRC8 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC8 (0x00000100) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC9] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /* SRC9 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC9 (0x00000200) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC10] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /* SRC10 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC10 (0x00000400) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC11] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /* SRC11 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC11 (0x00000800) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC12] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /* SRC12 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC12 (0x00001000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC13] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /* SRC13 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC13 (0x00002000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC14] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /* SRC14 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC14 (0x00004000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
-/* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC15] Bits */
-#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /* SRC15 Offset */
-#define RSTCTL_HARDRESET_CLR_SRC15 (0x00008000) /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC0] Bits */
-#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /* SRC0 Offset */
-#define RSTCTL_HARDRESET_SET_SRC0 (0x00000001) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC1] Bits */
-#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /* SRC1 Offset */
-#define RSTCTL_HARDRESET_SET_SRC1 (0x00000002) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC2] Bits */
-#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /* SRC2 Offset */
-#define RSTCTL_HARDRESET_SET_SRC2 (0x00000004) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC3] Bits */
-#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /* SRC3 Offset */
-#define RSTCTL_HARDRESET_SET_SRC3 (0x00000008) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC4] Bits */
-#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /* SRC4 Offset */
-#define RSTCTL_HARDRESET_SET_SRC4 (0x00000010) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC5] Bits */
-#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /* SRC5 Offset */
-#define RSTCTL_HARDRESET_SET_SRC5 (0x00000020) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC6] Bits */
-#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /* SRC6 Offset */
-#define RSTCTL_HARDRESET_SET_SRC6 (0x00000040) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC7] Bits */
-#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /* SRC7 Offset */
-#define RSTCTL_HARDRESET_SET_SRC7 (0x00000080) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC8] Bits */
-#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /* SRC8 Offset */
-#define RSTCTL_HARDRESET_SET_SRC8 (0x00000100) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC9] Bits */
-#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /* SRC9 Offset */
-#define RSTCTL_HARDRESET_SET_SRC9 (0x00000200) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC10] Bits */
-#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /* SRC10 Offset */
-#define RSTCTL_HARDRESET_SET_SRC10 (0x00000400) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC11] Bits */
-#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /* SRC11 Offset */
-#define RSTCTL_HARDRESET_SET_SRC11 (0x00000800) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC12] Bits */
-#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /* SRC12 Offset */
-#define RSTCTL_HARDRESET_SET_SRC12 (0x00001000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC13] Bits */
-#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /* SRC13 Offset */
-#define RSTCTL_HARDRESET_SET_SRC13 (0x00002000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC14] Bits */
-#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /* SRC14 Offset */
-#define RSTCTL_HARDRESET_SET_SRC14 (0x00004000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC15] Bits */
-#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /* SRC15 Offset */
-#define RSTCTL_HARDRESET_SET_SRC15 (0x00008000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC0] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /* SRC0 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC0 (0x00000001) /* If 1, indicates that SRC0 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC1] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /* SRC1 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC1 (0x00000002) /* If 1, indicates that SRC1 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC2] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /* SRC2 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC2 (0x00000004) /* If 1, indicates that SRC2 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC3] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /* SRC3 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC3 (0x00000008) /* If 1, indicates that SRC3 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC4] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /* SRC4 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC4 (0x00000010) /* If 1, indicates that SRC4 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC5] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /* SRC5 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC5 (0x00000020) /* If 1, indicates that SRC5 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC6] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /* SRC6 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC6 (0x00000040) /* If 1, indicates that SRC6 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC7] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /* SRC7 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC7 (0x00000080) /* If 1, indicates that SRC7 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC8] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /* SRC8 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC8 (0x00000100) /* If 1, indicates that SRC8 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC9] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /* SRC9 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC9 (0x00000200) /* If 1, indicates that SRC9 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC10] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /* SRC10 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC10 (0x00000400) /* If 1, indicates that SRC10 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC11] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /* SRC11 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC11 (0x00000800) /* If 1, indicates that SRC11 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC12] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /* SRC12 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC12 (0x00001000) /* If 1, indicates that SRC12 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC13] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /* SRC13 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC13 (0x00002000) /* If 1, indicates that SRC13 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC14] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /* SRC14 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC14 (0x00004000) /* If 1, indicates that SRC14 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC15] Bits */
-#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /* SRC15 Offset */
-#define RSTCTL_SOFTRESET_STAT_SRC15 (0x00008000) /* If 1, indicates that SRC15 was the source of the Soft Reset */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC0] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /* SRC0 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC0 (0x00000001) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC1] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /* SRC1 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC1 (0x00000002) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC2] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /* SRC2 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC2 (0x00000004) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC3] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /* SRC3 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC3 (0x00000008) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC4] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /* SRC4 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC4 (0x00000010) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC5] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /* SRC5 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC5 (0x00000020) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC6] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /* SRC6 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC6 (0x00000040) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC7] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /* SRC7 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC7 (0x00000080) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC8] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /* SRC8 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC8 (0x00000100) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC9] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /* SRC9 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC9 (0x00000200) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC10] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /* SRC10 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC10 (0x00000400) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC11] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /* SRC11 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC11 (0x00000800) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC12] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /* SRC12 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC12 (0x00001000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC13] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /* SRC13 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC13 (0x00002000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC14] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /* SRC14 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC14 (0x00004000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC15] Bits */
-#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /* SRC15 Offset */
-#define RSTCTL_SOFTRESET_CLR_SRC15 (0x00008000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC0] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /* SRC0 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC0 (0x00000001) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC1] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /* SRC1 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC1 (0x00000002) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC2] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /* SRC2 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC2 (0x00000004) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC3] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /* SRC3 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC3 (0x00000008) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC4] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /* SRC4 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC4 (0x00000010) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC5] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /* SRC5 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC5 (0x00000020) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC6] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /* SRC6 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC6 (0x00000040) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC7] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /* SRC7 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC7 (0x00000080) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC8] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /* SRC8 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC8 (0x00000100) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC9] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /* SRC9 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC9 (0x00000200) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC10] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /* SRC10 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC10 (0x00000400) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC11] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /* SRC11 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC11 (0x00000800) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC12] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /* SRC12 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC12 (0x00001000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC13] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /* SRC13 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC13 (0x00002000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC14] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /* SRC14 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC14 (0x00004000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC15] Bits */
-#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /* SRC15 Offset */
-#define RSTCTL_SOFTRESET_SET_SRC15 (0x00008000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSL] Bits */
-#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /* SVSL Offset */
-#define RSTCTL_PSSRESET_STAT_SVSL (0x00000001) /* Indicates if POR was caused by an SVSL trip condition in the PSS */
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSMH] Bits */
-#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /* SVSMH Offset */
-#define RSTCTL_PSSRESET_STAT_SVSMH (0x00000002) /* Indicates if POR was caused by an SVSMH trip condition int the PSS */
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_BGREF] Bits */
-#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /* BGREF Offset */
-#define RSTCTL_PSSRESET_STAT_BGREF (0x00000004) /* Indicates if POR was caused by a BGREF not okay condition in the PSS */
-/* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_VCCDET] Bits */
-#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /* VCCDET Offset */
-#define RSTCTL_PSSRESET_STAT_VCCDET (0x00000008) /* Indicates if POR was caused by a VCCDET trip condition in the PSS */
-/* RSTCTL_PSSRESET_CLR[RSTCTL_PSSRESET_CLR_CLR] Bits */
-#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
-#define RSTCTL_PSSRESET_CLR_CLR (0x00000001) /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
-/* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM35] Bits */
-#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /* LPM35 Offset */
-#define RSTCTL_PCMRESET_STAT_LPM35 (0x00000001) /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */
-/* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM45] Bits */
-#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /* LPM45 Offset */
-#define RSTCTL_PCMRESET_STAT_LPM45 (0x00000002) /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */
-/* RSTCTL_PCMRESET_CLR[RSTCTL_PCMRESET_CLR_CLR] Bits */
-#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
-#define RSTCTL_PCMRESET_CLR_CLR (0x00000001) /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
-/* RSTCTL_PINRESET_STAT[RSTCTL_PINRESET_STAT_RSTNMI] Bits */
-#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /* RSTNMI Offset */
-#define RSTCTL_PINRESET_STAT_RSTNMI (0x00000001) /* POR was caused by RSTn/NMI pin based reset event */
-/* RSTCTL_PINRESET_CLR[RSTCTL_PINRESET_CLR_CLR] Bits */
-#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
-#define RSTCTL_PINRESET_CLR_CLR (0x00000001) /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
-/* RSTCTL_REBOOTRESET_STAT[RSTCTL_REBOOTRESET_STAT_REBOOT] Bits */
-#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /* REBOOT Offset */
-#define RSTCTL_REBOOTRESET_STAT_REBOOT (0x00000001) /* Indicates if Reboot reset was caused by the SYSCTL module. */
-/* RSTCTL_REBOOTRESET_CLR[RSTCTL_REBOOTRESET_CLR_CLR] Bits */
-#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
-#define RSTCTL_REBOOTRESET_CLR_CLR (0x00000001) /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
+/******************************************************************************
+* RSTCTL Bits
+******************************************************************************/
+/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */
+#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /**< SOFT_REQ Bit Offset */
+#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /**< Soft Reset request */
+/* RSTCTL_RESET_REQ[HARD_REQ] Bits */
+#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /**< HARD_REQ Bit Offset */
+#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /**< Hard Reset request */
+/* RSTCTL_RESET_REQ[RSTKEY] Bits */
+#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /**< RSTKEY Bit Offset */
+#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /**< RSTKEY Bit Mask */
+/* RSTCTL_HARDRESET_STAT[SRC0] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /**< Indicates that SRC0 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC1] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /**< Indicates that SRC1 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC2] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /**< Indicates that SRC2 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC3] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /**< Indicates that SRC3 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC4] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /**< Indicates that SRC4 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC5] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /**< Indicates that SRC5 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC6] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /**< Indicates that SRC6 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC7] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /**< Indicates that SRC7 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC8] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /**< Indicates that SRC8 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC9] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /**< Indicates that SRC9 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC10] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /**< SRC10 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /**< Indicates that SRC10 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC11] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /**< SRC11 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /**< Indicates that SRC11 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC12] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /**< SRC12 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /**< Indicates that SRC12 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC13] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /**< SRC13 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /**< Indicates that SRC13 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC14] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /**< SRC14 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /**< Indicates that SRC14 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_STAT[SRC15] Bits */
+#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /**< SRC15 Bit Offset */
+#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /**< Indicates that SRC15 was the source of the Hard Reset */
+/* RSTCTL_HARDRESET_CLR[SRC0] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC1] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC2] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC3] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC4] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC5] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC6] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC7] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC8] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC9] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC10] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /**< SRC10 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC11] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /**< SRC11 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC12] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /**< SRC12 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC13] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /**< SRC13 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC14] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /**< SRC14 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /**< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
+/* RSTCTL_HARDRESET_CLR[SRC15] Bits */
+#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /**< SRC15 Bit Offset */
+#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /**< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
+/* RSTCTL_HARDRESET_SET[SRC0] Bits */
+#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC1] Bits */
+#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC2] Bits */
+#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC3] Bits */
+#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC4] Bits */
+#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC5] Bits */
+#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC6] Bits */
+#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC7] Bits */
+#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC8] Bits */
+#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC9] Bits */
+#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC10] Bits */
+#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /**< SRC10 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC11] Bits */
+#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /**< SRC11 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC12] Bits */
+#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /**< SRC12 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC13] Bits */
+#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /**< SRC13 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC14] Bits */
+#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /**< SRC14 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_HARDRESET_SET[SRC15] Bits */
+#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /**< SRC15 Bit Offset */
+#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /**< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates */
+ /* a Hard Reset) */
+/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /**< If 1, indicates that SRC0 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /**< If 1, indicates that SRC1 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /**< If 1, indicates that SRC2 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /**< If 1, indicates that SRC3 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /**< If 1, indicates that SRC4 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /**< If 1, indicates that SRC5 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /**< If 1, indicates that SRC6 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /**< If 1, indicates that SRC7 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /**< If 1, indicates that SRC8 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /**< If 1, indicates that SRC9 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /**< SRC10 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /**< If 1, indicates that SRC10 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /**< SRC11 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /**< If 1, indicates that SRC11 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /**< SRC12 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /**< If 1, indicates that SRC12 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /**< SRC13 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /**< If 1, indicates that SRC13 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /**< SRC14 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /**< If 1, indicates that SRC14 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */
+#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /**< SRC15 Bit Offset */
+#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /**< If 1, indicates that SRC15 was the source of the Soft Reset */
+/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /**< SRC10 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /**< SRC11 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /**< SRC12 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /**< SRC13 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /**< SRC14 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */
+#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /**< SRC15 Bit Offset */
+#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /**< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
+/* RSTCTL_SOFTRESET_SET[SRC0] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /**< SRC0 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC1] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /**< SRC1 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC2] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /**< SRC2 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC3] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /**< SRC3 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC4] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /**< SRC4 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC5] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /**< SRC5 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC6] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /**< SRC6 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC7] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /**< SRC7 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC8] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /**< SRC8 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC9] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /**< SRC9 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC10] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /**< SRC10 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC11] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /**< SRC11 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC12] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /**< SRC12 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC13] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /**< SRC13 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC14] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /**< SRC14 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_SOFTRESET_SET[SRC15] Bits */
+#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /**< SRC15 Bit Offset */
+#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /**< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates */
+ /* a Soft Reset) */
+/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */
+#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /**< SVSMH Bit Offset */
+#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /**< Indicates if POR was caused by an SVSMH trip condition int the PSS */
+/* RSTCTL_PSSRESET_STAT[BGREF] Bits */
+#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /**< BGREF Bit Offset */
+#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /**< Indicates if POR was caused by a BGREF not okay condition in the PSS */
+/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */
+#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /**< VCCDET Bit Offset */
+#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /**< Indicates if POR was caused by a VCCDET trip condition in the PSS */
+/* RSTCTL_PSSRESET_STAT[SVSL] Bits */
+#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /**< SVSL Bit Offset */
+#define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /**< Indicates if POR was caused by an SVSL trip condition in the PSS */
+/* RSTCTL_PSSRESET_CLR[CLR] Bits */
+#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
+#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
+/* RSTCTL_PCMRESET_STAT[LPM35] Bits */
+#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /**< LPM35 Bit Offset */
+#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /**< Indicates if POR was caused by PCM due to an exit from LPM3.5 */
+/* RSTCTL_PCMRESET_STAT[LPM45] Bits */
+#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /**< LPM45 Bit Offset */
+#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /**< Indicates if POR was caused by PCM due to an exit from LPM4.5 */
+/* RSTCTL_PCMRESET_CLR[CLR] Bits */
+#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
+#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
+/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */
+#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /**< RSTNMI Bit Offset */
+#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /**< POR was caused by RSTn/NMI pin based reset event */
+/* RSTCTL_PINRESET_CLR[CLR] Bits */
+#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
+#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
+/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */
+#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /**< REBOOT Bit Offset */
+#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /**< Indicates if Reboot reset was caused by the SYSCTL module. */
+/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */
+#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
+#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
+/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */
+#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /**< DCOR_SHT Bit Offset */
+#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /**< Indicates if POR was caused by DCO short circuit fault in the external */
+ /* resistor mode */
+/* RSTCTL_CSRESET_CLR[CLR] Bits */
+#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /**< CLR Bit Offset */
+#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /**< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG */
+ /* flag in CSIFG register of clock system */
/* Pre-defined bitfield values */
-#define RSTCTL_RESETREQ_RSTKEY_VAL (0x00006900) /* Key value to enable writes to bits 1-0 */
+#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /* Key value to enable writes to bits 1-0 */
-//*****************************************************************************
-// RTC_C Bits
-//*****************************************************************************
-/* RTCCTL0[RTCRDYIFG] Bits */
-#define RTCRDYIFG_OFS ( 0) /* RTCRDYIFG Offset */
-#define RTCRDYIFG (0x0001) /* Real-time clock ready interrupt flag */
-/* RTCCTL0[RTCAIFG] Bits */
-#define RTCAIFG_OFS ( 1) /* RTCAIFG Offset */
-#define RTCAIFG (0x0002) /* Real-time clock alarm interrupt flag */
-/* RTCCTL0[RTCTEVIFG] Bits */
-#define RTCTEVIFG_OFS ( 2) /* RTCTEVIFG Offset */
-#define RTCTEVIFG (0x0004) /* Real-time clock time event interrupt flag */
-/* RTCCTL0[RTCOFIFG] Bits */
-#define RTCOFIFG_OFS ( 3) /* RTCOFIFG Offset */
-#define RTCOFIFG (0x0008) /* 32-kHz crystal oscillator fault interrupt flag */
-/* RTCCTL0[RTCRDYIE] Bits */
-#define RTCRDYIE_OFS ( 4) /* RTCRDYIE Offset */
-#define RTCRDYIE (0x0010) /* Real-time clock ready interrupt enable */
-/* RTCCTL0[RTCAIE] Bits */
-#define RTCAIE_OFS ( 5) /* RTCAIE Offset */
-#define RTCAIE (0x0020) /* Real-time clock alarm interrupt enable */
-/* RTCCTL0[RTCTEVIE] Bits */
-#define RTCTEVIE_OFS ( 6) /* RTCTEVIE Offset */
-#define RTCTEVIE (0x0040) /* Real-time clock time event interrupt enable */
-/* RTCCTL0[RTCOFIE] Bits */
-#define RTCOFIE_OFS ( 7) /* RTCOFIE Offset */
-#define RTCOFIE (0x0080) /* 32-kHz crystal oscillator fault interrupt enable */
-/* RTCCTL0[RTCKEY] Bits */
-#define RTCKEY_OFS ( 8) /* RTCKEY Offset */
-#define RTCKEY_M (0xff00) /* Real-time clock key */
-/* RTCCTL13[RTCTEV] Bits */
-#define RTCTEV_OFS ( 0) /* RTCTEV Offset */
-#define RTCTEV_M (0x0003) /* Real-time clock time event */
-#define RTCTEV0 (0x0001) /* Real-time clock time event */
-#define RTCTEV1 (0x0002) /* Real-time clock time event */
-#define RTCTEV_0 (0x0000) /* Minute changed */
-#define RTCTEV_1 (0x0001) /* Hour changed */
-#define RTCTEV_2 (0x0002) /* Every day at midnight (00:00) */
-#define RTCTEV_3 (0x0003) /* Every day at noon (12:00) */
-/* RTCCTL13[RTCSSEL] Bits */
-#define RTCSSEL_OFS ( 2) /* RTCSSEL Offset */
-#define RTCSSEL_M (0x000c) /* Real-time clock source select */
-#define RTCSSEL0 (0x0004) /* Real-time clock source select */
-#define RTCSSEL1 (0x0008) /* Real-time clock source select */
-#define RTCSSEL_0 (0x0000) /* BCLK */
-#define RTCSSEL__BCLK (0x0000) /* BCLK */
-/* RTCCTL13[RTCRDY] Bits */
-#define RTCRDY_OFS ( 4) /* RTCRDY Offset */
-#define RTCRDY (0x0010) /* Real-time clock ready */
-/* RTCCTL13[RTCMODE] Bits */
-#define RTCMODE_OFS ( 5) /* RTCMODE Offset */
-#define RTCMODE (0x0020) /* */
-/* RTCCTL13[RTCHOLD] Bits */
-#define RTCHOLD_OFS ( 6) /* RTCHOLD Offset */
-#define RTCHOLD (0x0040) /* Real-time clock hold */
-/* RTCCTL13[RTCBCD] Bits */
-#define RTCBCD_OFS ( 7) /* RTCBCD Offset */
-#define RTCBCD (0x0080) /* Real-time clock BCD select */
-/* RTCCTL13[RTCCALF] Bits */
-#define RTCCALF_OFS ( 8) /* RTCCALF Offset */
-#define RTCCALF_M (0x0300) /* Real-time clock calibration frequency */
-#define RTCCALF0 (0x0100) /* Real-time clock calibration frequency */
-#define RTCCALF1 (0x0200) /* Real-time clock calibration frequency */
-#define RTCCALF_0 (0x0000) /* No frequency output to RTCCLK pin */
-#define RTCCALF_1 (0x0100) /* 512 Hz */
-#define RTCCALF_2 (0x0200) /* 256 Hz */
-#define RTCCALF_3 (0x0300) /* 1 Hz */
-#define RTCCALF__NONE (0x0000) /* No frequency output to RTCCLK pin */
-#define RTCCALF__512 (0x0100) /* 512 Hz */
-#define RTCCALF__256 (0x0200) /* 256 Hz */
-#define RTCCALF__1 (0x0300) /* 1 Hz */
-/* RTCOCAL[RTCOCAL] Bits */
-#define RTCOCAL_OFS ( 0) /* RTCOCAL Offset */
-#define RTCOCAL_M (0x00ff) /* Real-time clock offset error calibration */
-/* RTCOCAL[RTCOCALS] Bits */
-#define RTCOCALS_OFS (15) /* RTCOCALS Offset */
-#define RTCOCALS (0x8000) /* Real-time clock offset error calibration sign */
-/* RTCTCMP[RTCTCMP] Bits */
-#define RTCTCMP_OFS ( 0) /* RTCTCMP Offset */
-#define RTCTCMP_M (0x00ff) /* Real-time clock temperature compensation */
-/* RTCTCMP[RTCTCOK] Bits */
-#define RTCTCOK_OFS (13) /* RTCTCOK Offset */
-#define RTCTCOK (0x2000) /* Real-time clock temperature compensation write OK */
-/* RTCTCMP[RTCTCRDY] Bits */
-#define RTCTCRDY_OFS (14) /* RTCTCRDY Offset */
-#define RTCTCRDY (0x4000) /* Real-time clock temperature compensation ready */
-/* RTCTCMP[RTCTCMPS] Bits */
-#define RTCTCMPS_OFS (15) /* RTCTCMPS Offset */
-#define RTCTCMPS (0x8000) /* Real-time clock temperature compensation sign */
-/* RTCPS0CTL[RT0PSIFG] Bits */
-#define RT0PSIFG_OFS ( 0) /* RT0PSIFG Offset */
-#define RT0PSIFG (0x0001) /* Prescale timer 0 interrupt flag */
-/* RTCPS0CTL[RT0PSIE] Bits */
-#define RT0PSIE_OFS ( 1) /* RT0PSIE Offset */
-#define RT0PSIE (0x0002) /* Prescale timer 0 interrupt enable */
-/* RTCPS0CTL[RT0IP] Bits */
-#define RT0IP_OFS ( 2) /* RT0IP Offset */
-#define RT0IP_M (0x001c) /* Prescale timer 0 interrupt interval */
-#define RT0IP0 (0x0004) /* Prescale timer 0 interrupt interval */
-#define RT0IP1 (0x0008) /* Prescale timer 0 interrupt interval */
-#define RT0IP2 (0x0010) /* Prescale timer 0 interrupt interval */
-#define RT0IP_0 (0x0000) /* Divide by 2 */
-#define RT0IP_1 (0x0004) /* Divide by 4 */
-#define RT0IP_2 (0x0008) /* Divide by 8 */
-#define RT0IP_3 (0x000c) /* Divide by 16 */
-#define RT0IP_4 (0x0010) /* Divide by 32 */
-#define RT0IP_5 (0x0014) /* Divide by 64 */
-#define RT0IP_6 (0x0018) /* Divide by 128 */
-#define RT0IP_7 (0x001c) /* Divide by 256 */
-#define RT0IP__2 (0x0000) /* Divide by 2 */
-#define RT0IP__4 (0x0004) /* Divide by 4 */
-#define RT0IP__8 (0x0008) /* Divide by 8 */
-#define RT0IP__16 (0x000c) /* Divide by 16 */
-#define RT0IP__32 (0x0010) /* Divide by 32 */
-#define RT0IP__64 (0x0014) /* Divide by 64 */
-#define RT0IP__128 (0x0018) /* Divide by 128 */
-#define RT0IP__256 (0x001c) /* Divide by 256 */
-/* RTCPS1CTL[RT1PSIFG] Bits */
-#define RT1PSIFG_OFS ( 0) /* RT1PSIFG Offset */
-#define RT1PSIFG (0x0001) /* Prescale timer 1 interrupt flag */
-/* RTCPS1CTL[RT1PSIE] Bits */
-#define RT1PSIE_OFS ( 1) /* RT1PSIE Offset */
-#define RT1PSIE (0x0002) /* Prescale timer 1 interrupt enable */
-/* RTCPS1CTL[RT1IP] Bits */
-#define RT1IP_OFS ( 2) /* RT1IP Offset */
-#define RT1IP_M (0x001c) /* Prescale timer 1 interrupt interval */
-#define RT1IP0 (0x0004) /* Prescale timer 1 interrupt interval */
-#define RT1IP1 (0x0008) /* Prescale timer 1 interrupt interval */
-#define RT1IP2 (0x0010) /* Prescale timer 1 interrupt interval */
-#define RT1IP_0 (0x0000) /* Divide by 2 */
-#define RT1IP_1 (0x0004) /* Divide by 4 */
-#define RT1IP_2 (0x0008) /* Divide by 8 */
-#define RT1IP_3 (0x000c) /* Divide by 16 */
-#define RT1IP_4 (0x0010) /* Divide by 32 */
-#define RT1IP_5 (0x0014) /* Divide by 64 */
-#define RT1IP_6 (0x0018) /* Divide by 128 */
-#define RT1IP_7 (0x001c) /* Divide by 256 */
-#define RT1IP__2 (0x0000) /* Divide by 2 */
-#define RT1IP__4 (0x0004) /* Divide by 4 */
-#define RT1IP__8 (0x0008) /* Divide by 8 */
-#define RT1IP__16 (0x000c) /* Divide by 16 */
-#define RT1IP__32 (0x0010) /* Divide by 32 */
-#define RT1IP__64 (0x0014) /* Divide by 64 */
-#define RT1IP__128 (0x0018) /* Divide by 128 */
-#define RT1IP__256 (0x001c) /* Divide by 256 */
-/* RTCPS[RT0PS] Bits */
-#define RT0PS_OFS ( 0) /* RT0PS Offset */
-#define RT0PS_M (0x00ff) /* Prescale timer 0 counter value */
-/* RTCPS[RT1PS] Bits */
-#define RT1PS_OFS ( 8) /* RT1PS Offset */
-#define RT1PS_M (0xff00) /* Prescale timer 1 counter value */
-/* RTCTIM0[SECONDS] Bits */
-#define SECONDS_OFS ( 0) /* Seconds Offset */
-#define SECONDS_M (0x003f) /* Seconds (0 to 59) */
-/* RTCTIM0[MINUTES] Bits */
-#define MINUTES_OFS ( 8) /* Minutes Offset */
-#define MINUTES_M (0x3f00) /* Minutes (0 to 59) */
-/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */
-#define SECONDSLOWDIGIT_OFS ( 0) /* SecondsLowDigit Offset */
-#define SECONDSLOWDIGIT_M (0x000f) /* Seconds ? low digit (0 to 9) */
-/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */
-#define SECONDSHIGHDIGIT_OFS ( 4) /* SecondsHighDigit Offset */
-#define SECONDSHIGHDIGIT_M (0x0070) /* Seconds ? high digit (0 to 5) */
-/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */
-#define MINUTESLOWDIGIT_OFS ( 8) /* MinutesLowDigit Offset */
-#define MINUTESLOWDIGIT_M (0x0f00) /* Minutes ? low digit (0 to 9) */
-/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */
-#define MINUTESHIGHDIGIT_OFS (12) /* MinutesHighDigit Offset */
-#define MINUTESHIGHDIGIT_M (0x7000) /* Minutes ? high digit (0 to 5) */
-/* RTCTIM1[HOURS] Bits */
-#define HOURS_OFS ( 0) /* Hours Offset */
-#define HOURS_M (0x001f) /* Hours (0 to 23) */
-/* RTCTIM1[DAYOFWEEK] Bits */
-#define DAYOFWEEK_OFS ( 8) /* DayofWeek Offset */
-#define DAYOFWEEK_M (0x0700) /* Day of week (0 to 6) */
-/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */
-#define HOURSLOWDIGIT_OFS ( 0) /* HoursLowDigit Offset */
-#define HOURSLOWDIGIT_M (0x000f) /* Hours ? low digit (0 to 9) */
-/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */
-#define HOURSHIGHDIGIT_OFS ( 4) /* HoursHighDigit Offset */
-#define HOURSHIGHDIGIT_M (0x0030) /* Hours ? high digit (0 to 2) */
-/* RTCTIM1_BCD[DAYOFWEEK] Bits */
-//#define DAYOFWEEK_OFS ( 8) /* DayofWeek Offset */
-//#define DAYOFWEEK_M (0x0700) /* Day of week (0 to 6) */
-/* RTCDATE[DAY] Bits */
-#define DAY_OFS ( 0) /* Day Offset */
-#define DAY_M (0x001f) /* Day of month (1 to 28, 29, 30, 31) */
-/* RTCDATE[MONTH] Bits */
-#define MONTH_OFS ( 8) /* Month Offset */
-#define MONTH_M (0x0f00) /* Month (1 to 12) */
-/* RTCDATE_BCD[DAYLOWDIGIT] Bits */
-#define DAYLOWDIGIT_OFS ( 0) /* DayLowDigit Offset */
-#define DAYLOWDIGIT_M (0x000f) /* Day of month ? low digit (0 to 9) */
-/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */
-#define DAYHIGHDIGIT_OFS ( 4) /* DayHighDigit Offset */
-#define DAYHIGHDIGIT_M (0x0030) /* Day of month ? high digit (0 to 3) */
-/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */
-#define MONTHLOWDIGIT_OFS ( 8) /* MonthLowDigit Offset */
-#define MONTHLOWDIGIT_M (0x0f00) /* Month ? low digit (0 to 9) */
-/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */
-#define MONTHHIGHDIGIT_OFS (12) /* MonthHighDigit Offset */
-#define MONTHHIGHDIGIT (0x1000) /* Month ? high digit (0 or 1) */
-/* RTCYEAR[YEARLOWBYTE] Bits */
-#define YEARLOWBYTE_OFS ( 0) /* YearLowByte Offset */
-#define YEARLOWBYTE_M (0x00ff) /* Year ? low byte. Valid values for Year are 0 to 4095. */
-/* RTCYEAR[YEARHIGHBYTE] Bits */
-#define YEARHIGHBYTE_OFS ( 8) /* YearHighByte Offset */
-#define YEARHIGHBYTE_M (0x0f00) /* Year ? high byte. Valid values for Year are 0 to 4095. */
-/* RTCYEAR_BCD[YEAR] Bits */
-#define YEAR_OFS ( 0) /* Year Offset */
-#define YEAR_M (0x000f) /* Year ? lowest digit (0 to 9) */
-/* RTCYEAR_BCD[DECADE] Bits */
-#define DECADE_OFS ( 4) /* Decade Offset */
-#define DECADE_M (0x00f0) /* Decade (0 to 9) */
-/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */
-#define CENTURYLOWDIGIT_OFS ( 8) /* CenturyLowDigit Offset */
-#define CENTURYLOWDIGIT_M (0x0f00) /* Century ? low digit (0 to 9) */
-/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */
-#define CENTURYHIGHDIGIT_OFS (12) /* CenturyHighDigit Offset */
-#define CENTURYHIGHDIGIT_M (0x7000) /* Century ? high digit (0 to 4) */
-/* RTCAMINHR[MINUTES] Bits */
-//#define MINUTES_OFS ( 0) /* Minutes Offset */
-//#define MINUTES_M (0x003f) /* Minutes (0 to 59) */
-/* RTCAMINHR[MINAE] Bits */
-#define MINAE_OFS ( 7) /* MINAE Offset */
-#define MINAE (0x0080) /* Alarm enable */
-/* RTCAMINHR[HOURS] Bits */
-//#define HOURS_OFS ( 8) /* Hours Offset */
-//#define HOURS_M (0x1f00) /* Hours (0 to 23) */
-/* RTCAMINHR[HOURAE] Bits */
-#define HOURAE_OFS (15) /* HOURAE Offset */
-#define HOURAE (0x8000) /* Alarm enable */
-/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */
-//#define MINUTESLOWDIGIT_OFS ( 0) /* MinutesLowDigit Offset */
-//#define MINUTESLOWDIGIT_M (0x000f) /* Minutes ? low digit (0 to 9) */
-/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */
-//#define MINUTESHIGHDIGIT_OFS ( 4) /* MinutesHighDigit Offset */
-//#define MINUTESHIGHDIGIT_M (0x0070) /* Minutes ? high digit (0 to 5) */
-/* RTCAMINHR_BCD[MINAE] Bits */
-//#define MINAE_OFS ( 7) /* MINAE Offset */
-//#define MINAE (0x0080) /* Alarm enable */
-/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */
-//#define HOURSLOWDIGIT_OFS ( 8) /* HoursLowDigit Offset */
-//#define HOURSLOWDIGIT_M (0x0f00) /* Hours ? low digit (0 to 9) */
-/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */
-//#define HOURSHIGHDIGIT_OFS (12) /* HoursHighDigit Offset */
-//#define HOURSHIGHDIGIT_M (0x3000) /* Hours ? high digit (0 to 2) */
-/* RTCAMINHR_BCD[HOURAE] Bits */
-//#define HOURAE_OFS (15) /* HOURAE Offset */
-//#define HOURAE (0x8000) /* Alarm enable */
-/* RTCADOWDAY[DAYOFWEEK] Bits */
-//#define DAYOFWEEK_OFS ( 0) /* DayofWeek Offset */
-//#define DAYOFWEEK_M (0x0007) /* Day of week (0 to 6) */
-/* RTCADOWDAY[DOWAE] Bits */
-#define DOWAE_OFS ( 7) /* DOWAE Offset */
-#define DOWAE (0x0080) /* Alarm enable */
-/* RTCADOWDAY[DAYOFMONTH] Bits */
-#define DAYOFMONTH_OFS ( 8) /* DayofMonth Offset */
-#define DAYOFMONTH_M (0x1f00) /* Day of month (1 to 28, 29, 30, 31) */
-/* RTCADOWDAY[DAYAE] Bits */
-#define DAYAE_OFS (15) /* DAYAE Offset */
-#define DAYAE (0x8000) /* Alarm enable */
-/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */
-//#define DAYOFWEEK_OFS ( 0) /* DayofWeek Offset */
-//#define DAYOFWEEK_M (0x0007) /* Day of week (0 to 6) */
-/* RTCADOWDAY_BCD[DOWAE] Bits */
-//#define DOWAE_OFS ( 7) /* DOWAE Offset */
-//#define DOWAE (0x0080) /* Alarm enable */
-/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */
-//#define DAYLOWDIGIT_OFS ( 8) /* DayLowDigit Offset */
-//#define DAYLOWDIGIT_M (0x0f00) /* Day of month ? low digit (0 to 9) */
-/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */
-//#define DAYHIGHDIGIT_OFS (12) /* DayHighDigit Offset */
-//#define DAYHIGHDIGIT_M (0x3000) /* Day of month ? high digit (0 to 3) */
-/* RTCADOWDAY_BCD[DAYAE] Bits */
-//#define DAYAE_OFS (15) /* DAYAE Offset */
-//#define DAYAE (0x8000) /* Alarm enable */
+/******************************************************************************
+* RTC_C Bits
+******************************************************************************/
+/* RTC_C_CTL0[RDYIFG] Bits */
+#define RTC_C_CTL0_RDYIFG_OFS ( 0) /**< RTCRDYIFG Bit Offset */
+#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /**< Real-time clock ready interrupt flag */
+/* RTC_C_CTL0[AIFG] Bits */
+#define RTC_C_CTL0_AIFG_OFS ( 1) /**< RTCAIFG Bit Offset */
+#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /**< Real-time clock alarm interrupt flag */
+/* RTC_C_CTL0[TEVIFG] Bits */
+#define RTC_C_CTL0_TEVIFG_OFS ( 2) /**< RTCTEVIFG Bit Offset */
+#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /**< Real-time clock time event interrupt flag */
+/* RTC_C_CTL0[OFIFG] Bits */
+#define RTC_C_CTL0_OFIFG_OFS ( 3) /**< RTCOFIFG Bit Offset */
+#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /**< 32-kHz crystal oscillator fault interrupt flag */
+/* RTC_C_CTL0[RDYIE] Bits */
+#define RTC_C_CTL0_RDYIE_OFS ( 4) /**< RTCRDYIE Bit Offset */
+#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /**< Real-time clock ready interrupt enable */
+/* RTC_C_CTL0[AIE] Bits */
+#define RTC_C_CTL0_AIE_OFS ( 5) /**< RTCAIE Bit Offset */
+#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /**< Real-time clock alarm interrupt enable */
+/* RTC_C_CTL0[TEVIE] Bits */
+#define RTC_C_CTL0_TEVIE_OFS ( 6) /**< RTCTEVIE Bit Offset */
+#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /**< Real-time clock time event interrupt enable */
+/* RTC_C_CTL0[OFIE] Bits */
+#define RTC_C_CTL0_OFIE_OFS ( 7) /**< RTCOFIE Bit Offset */
+#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /**< 32-kHz crystal oscillator fault interrupt enable */
+/* RTC_C_CTL0[KEY] Bits */
+#define RTC_C_CTL0_KEY_OFS ( 8) /**< RTCKEY Bit Offset */
+#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /**< RTCKEY Bit Mask */
+/* RTC_C_CTL13[TEV] Bits */
+#define RTC_C_CTL13_TEV_OFS ( 0) /**< RTCTEV Bit Offset */
+#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /**< RTCTEV Bit Mask */
+#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /**< TEV Bit 0 */
+#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /**< TEV Bit 1 */
+#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /**< Minute changed */
+#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /**< Hour changed */
+#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /**< Every day at midnight (00:00) */
+#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /**< Every day at noon (12:00) */
+/* RTC_C_CTL13[SSEL] Bits */
+#define RTC_C_CTL13_SSEL_OFS ( 2) /**< RTCSSEL Bit Offset */
+#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /**< RTCSSEL Bit Mask */
+#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /**< SSEL Bit 0 */
+#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /**< SSEL Bit 1 */
+#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /**< BCLK */
+#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /**< BCLK */
+/* RTC_C_CTL13[RDY] Bits */
+#define RTC_C_CTL13_RDY_OFS ( 4) /**< RTCRDY Bit Offset */
+#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /**< Real-time clock ready */
+/* RTC_C_CTL13[MODE] Bits */
+#define RTC_C_CTL13_MODE_OFS ( 5) /**< RTCMODE Bit Offset */
+#define RTC_C_CTL13_MODE ((uint16_t)0x0020)
+/* RTC_C_CTL13[HOLD] Bits */
+#define RTC_C_CTL13_HOLD_OFS ( 6) /**< RTCHOLD Bit Offset */
+#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /**< Real-time clock hold */
+/* RTC_C_CTL13[BCD] Bits */
+#define RTC_C_CTL13_BCD_OFS ( 7) /**< RTCBCD Bit Offset */
+#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /**< Real-time clock BCD select */
+/* RTC_C_CTL13[CALF] Bits */
+#define RTC_C_CTL13_CALF_OFS ( 8) /**< RTCCALF Bit Offset */
+#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /**< RTCCALF Bit Mask */
+#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /**< CALF Bit 0 */
+#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /**< CALF Bit 1 */
+#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /**< No frequency output to RTCCLK pin */
+#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /**< 512 Hz */
+#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /**< 256 Hz */
+#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /**< 1 Hz */
+#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /**< No frequency output to RTCCLK pin */
+#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /**< 512 Hz */
+#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /**< 256 Hz */
+#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /**< 1 Hz */
+/* RTC_C_OCAL[OCAL] Bits */
+#define RTC_C_OCAL_OCAL_OFS ( 0) /**< RTCOCAL Bit Offset */
+#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /**< RTCOCAL Bit Mask */
+/* RTC_C_OCAL[OCALS] Bits */
+#define RTC_C_OCAL_OCALS_OFS (15) /**< RTCOCALS Bit Offset */
+#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /**< Real-time clock offset error calibration sign */
+/* RTC_C_TCMP[TCMPX] Bits */
+#define RTC_C_TCMP_TCMPX_OFS ( 0) /**< RTCTCMP Bit Offset */
+#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /**< RTCTCMP Bit Mask */
+/* RTC_C_TCMP[TCOK] Bits */
+#define RTC_C_TCMP_TCOK_OFS (13) /**< RTCTCOK Bit Offset */
+#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /**< Real-time clock temperature compensation write OK */
+/* RTC_C_TCMP[TCRDY] Bits */
+#define RTC_C_TCMP_TCRDY_OFS (14) /**< RTCTCRDY Bit Offset */
+#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /**< Real-time clock temperature compensation ready */
+/* RTC_C_TCMP[TCMPS] Bits */
+#define RTC_C_TCMP_TCMPS_OFS (15) /**< RTCTCMPS Bit Offset */
+#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /**< Real-time clock temperature compensation sign */
+/* RTC_C_PS0CTL[RT0PSIFG] Bits */
+#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /**< RT0PSIFG Bit Offset */
+#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /**< Prescale timer 0 interrupt flag */
+/* RTC_C_PS0CTL[RT0PSIE] Bits */
+#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /**< RT0PSIE Bit Offset */
+#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /**< Prescale timer 0 interrupt enable */
+/* RTC_C_PS0CTL[RT0IP] Bits */
+#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /**< RT0IP Bit Offset */
+#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /**< RT0IP Bit Mask */
+#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /**< RT0IP Bit 0 */
+#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /**< RT0IP Bit 1 */
+#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /**< RT0IP Bit 2 */
+#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /**< Divide by 2 */
+#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /**< Divide by 4 */
+#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /**< Divide by 8 */
+#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /**< Divide by 16 */
+#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /**< Divide by 32 */
+#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /**< Divide by 64 */
+#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /**< Divide by 128 */
+#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /**< Divide by 256 */
+#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /**< Divide by 2 */
+#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /**< Divide by 4 */
+#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /**< Divide by 8 */
+#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /**< Divide by 16 */
+#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /**< Divide by 32 */
+#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /**< Divide by 64 */
+#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /**< Divide by 128 */
+#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /**< Divide by 256 */
+/* RTC_C_PS1CTL[RT1PSIFG] Bits */
+#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /**< RT1PSIFG Bit Offset */
+#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /**< Prescale timer 1 interrupt flag */
+/* RTC_C_PS1CTL[RT1PSIE] Bits */
+#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /**< RT1PSIE Bit Offset */
+#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /**< Prescale timer 1 interrupt enable */
+/* RTC_C_PS1CTL[RT1IP] Bits */
+#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /**< RT1IP Bit Offset */
+#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /**< RT1IP Bit Mask */
+#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /**< RT1IP Bit 0 */
+#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /**< RT1IP Bit 1 */
+#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /**< RT1IP Bit 2 */
+#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /**< Divide by 2 */
+#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /**< Divide by 4 */
+#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /**< Divide by 8 */
+#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /**< Divide by 16 */
+#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /**< Divide by 32 */
+#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /**< Divide by 64 */
+#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /**< Divide by 128 */
+#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /**< Divide by 256 */
+#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /**< Divide by 2 */
+#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /**< Divide by 4 */
+#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /**< Divide by 8 */
+#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /**< Divide by 16 */
+#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /**< Divide by 32 */
+#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /**< Divide by 64 */
+#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /**< Divide by 128 */
+#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /**< Divide by 256 */
+/* RTC_C_PS[RT0PS] Bits */
+#define RTC_C_PS_RT0PS_OFS ( 0) /**< RT0PS Bit Offset */
+#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /**< RT0PS Bit Mask */
+/* RTC_C_PS[RT1PS] Bits */
+#define RTC_C_PS_RT1PS_OFS ( 8) /**< RT1PS Bit Offset */
+#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /**< RT1PS Bit Mask */
+/* RTC_C_TIM0[SEC] Bits */
+#define RTC_C_TIM0_SEC_OFS ( 0) /**< Seconds Bit Offset */
+#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /**< Seconds Bit Mask */
+/* RTC_C_TIM0[MIN] Bits */
+#define RTC_C_TIM0_MIN_OFS ( 8) /**< Minutes Bit Offset */
+#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /**< Minutes Bit Mask */
+/* RTC_C_TIM0[SEC_LD] Bits */
+#define RTC_C_TIM0_SEC_LD_OFS ( 0) /**< SecondsLowDigit Bit Offset */
+#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /**< SecondsLowDigit Bit Mask */
+/* RTC_C_TIM0[SEC_HD] Bits */
+#define RTC_C_TIM0_SEC_HD_OFS ( 4) /**< SecondsHighDigit Bit Offset */
+#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /**< SecondsHighDigit Bit Mask */
+/* RTC_C_TIM0[MIN_LD] Bits */
+#define RTC_C_TIM0_MIN_LD_OFS ( 8) /**< MinutesLowDigit Bit Offset */
+#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /**< MinutesLowDigit Bit Mask */
+/* RTC_C_TIM0[MIN_HD] Bits */
+#define RTC_C_TIM0_MIN_HD_OFS (12) /**< MinutesHighDigit Bit Offset */
+#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /**< MinutesHighDigit Bit Mask */
+/* RTC_C_TIM1[HOUR] Bits */
+#define RTC_C_TIM1_HOUR_OFS ( 0) /**< Hours Bit Offset */
+#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /**< Hours Bit Mask */
+/* RTC_C_TIM1[DOW] Bits */
+#define RTC_C_TIM1_DOW_OFS ( 8) /**< DayofWeek Bit Offset */
+#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /**< DayofWeek Bit Mask */
+/* RTC_C_TIM1[HOUR_LD] Bits */
+#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /**< HoursLowDigit Bit Offset */
+#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /**< HoursLowDigit Bit Mask */
+/* RTC_C_TIM1[HOUR_HD] Bits */
+#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /**< HoursHighDigit Bit Offset */
+#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /**< HoursHighDigit Bit Mask */
+/* RTC_C_DATE[DAY] Bits */
+#define RTC_C_DATE_DAY_OFS ( 0) /**< Day Bit Offset */
+#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /**< Day Bit Mask */
+/* RTC_C_DATE[MON] Bits */
+#define RTC_C_DATE_MON_OFS ( 8) /**< Month Bit Offset */
+#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /**< Month Bit Mask */
+/* RTC_C_DATE[DAY_LD] Bits */
+#define RTC_C_DATE_DAY_LD_OFS ( 0) /**< DayLowDigit Bit Offset */
+#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /**< DayLowDigit Bit Mask */
+/* RTC_C_DATE[DAY_HD] Bits */
+#define RTC_C_DATE_DAY_HD_OFS ( 4) /**< DayHighDigit Bit Offset */
+#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /**< DayHighDigit Bit Mask */
+/* RTC_C_DATE[MON_LD] Bits */
+#define RTC_C_DATE_MON_LD_OFS ( 8) /**< MonthLowDigit Bit Offset */
+#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /**< MonthLowDigit Bit Mask */
+/* RTC_C_DATE[MON_HD] Bits */
+#define RTC_C_DATE_MON_HD_OFS (12) /**< MonthHighDigit Bit Offset */
+#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /**< Month ? high digit (0 or 1) */
+/* RTC_C_YEAR[YEAR_LB] Bits */
+#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /**< YearLowByte Bit Offset */
+#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /**< YearLowByte Bit Mask */
+/* RTC_C_YEAR[YEAR_HB] Bits */
+#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /**< YearHighByte Bit Offset */
+#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /**< YearHighByte Bit Mask */
+/* RTC_C_YEAR[YEAR] Bits */
+#define RTC_C_YEAR_YEAR_OFS ( 0) /**< Year Bit Offset */
+#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /**< Year Bit Mask */
+/* RTC_C_YEAR[DEC] Bits */
+#define RTC_C_YEAR_DEC_OFS ( 4) /**< Decade Bit Offset */
+#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /**< Decade Bit Mask */
+/* RTC_C_YEAR[CENT_LD] Bits */
+#define RTC_C_YEAR_CENT_LD_OFS ( 8) /**< CenturyLowDigit Bit Offset */
+#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /**< CenturyLowDigit Bit Mask */
+/* RTC_C_YEAR[CENT_HD] Bits */
+#define RTC_C_YEAR_CENT_HD_OFS (12) /**< CenturyHighDigit Bit Offset */
+#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /**< CenturyHighDigit Bit Mask */
+/* RTC_C_AMINHR[MIN] Bits */
+#define RTC_C_AMINHR_MIN_OFS ( 0) /**< Minutes Bit Offset */
+#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /**< Minutes Bit Mask */
+/* RTC_C_AMINHR[MINAE] Bits */
+#define RTC_C_AMINHR_MINAE_OFS ( 7) /**< MINAE Bit Offset */
+#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /**< Alarm enable */
+/* RTC_C_AMINHR[HOUR] Bits */
+#define RTC_C_AMINHR_HOUR_OFS ( 8) /**< Hours Bit Offset */
+#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /**< Hours Bit Mask */
+/* RTC_C_AMINHR[HOURAE] Bits */
+#define RTC_C_AMINHR_HOURAE_OFS (15) /**< HOURAE Bit Offset */
+#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /**< Alarm enable */
+/* RTC_C_AMINHR[MIN_LD] Bits */
+#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /**< MinutesLowDigit Bit Offset */
+#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /**< MinutesLowDigit Bit Mask */
+/* RTC_C_AMINHR[MIN_HD] Bits */
+#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /**< MinutesHighDigit Bit Offset */
+#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /**< MinutesHighDigit Bit Mask */
+/* RTC_C_AMINHR[HOUR_LD] Bits */
+#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /**< HoursLowDigit Bit Offset */
+#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /**< HoursLowDigit Bit Mask */
+/* RTC_C_AMINHR[HOUR_HD] Bits */
+#define RTC_C_AMINHR_HOUR_HD_OFS (12) /**< HoursHighDigit Bit Offset */
+#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /**< HoursHighDigit Bit Mask */
+/* RTC_C_ADOWDAY[DOW] Bits */
+#define RTC_C_ADOWDAY_DOW_OFS ( 0) /**< DayofWeek Bit Offset */
+#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /**< DayofWeek Bit Mask */
+/* RTC_C_ADOWDAY[DOWAE] Bits */
+#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /**< DOWAE Bit Offset */
+#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /**< Alarm enable */
+/* RTC_C_ADOWDAY[DAY] Bits */
+#define RTC_C_ADOWDAY_DAY_OFS ( 8) /**< DayofMonth Bit Offset */
+#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /**< DayofMonth Bit Mask */
+/* RTC_C_ADOWDAY[DAYAE] Bits */
+#define RTC_C_ADOWDAY_DAYAE_OFS (15) /**< DAYAE Bit Offset */
+#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /**< Alarm enable */
+/* RTC_C_ADOWDAY[DAY_LD] Bits */
+#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /**< DayLowDigit Bit Offset */
+#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /**< DayLowDigit Bit Mask */
+/* RTC_C_ADOWDAY[DAY_HD] Bits */
+#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /**< DayHighDigit Bit Offset */
+#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /**< DayHighDigit Bit Mask */
/* Pre-defined bitfield values */
-#define RTCKEY (0xA500) /* RTC_C Key Value for RTC_C write access */
-#define RTCKEY_H (0x00A5) /* RTC_C Key Value for RTC_C write access */
-#define RTCKEY_VAL (0xA500) /* RTC_C Key Value for RTC_C write access */
+#define RTC_C_KEY ((uint16_t)0xA500) /* RTC_C Key Value for RTC_C write access */
+#define RTC_C_KEY_H ((uint16_t)0x00A5) /* RTC_C Key Value for RTC_C write access */
+#define RTC_C_KEY_VAL ((uint16_t)0xA500) /* RTC_C Key Value for RTC_C write access */
-//*****************************************************************************
-// SCB Bits
-//*****************************************************************************
-/* SCB_CPUID[SCB_CPUID_REVISION] Bits */
-#define SCB_CPUID_REVISION_OFS ( 0) /* REVISION Offset */
-#define SCB_CPUID_REVISION_M (0x0000000f) /* */
-/* SCB_CPUID[SCB_CPUID_PARTNO] Bits */
-#define SCB_CPUID_PARTNO_OFS ( 4) /* PARTNO Offset */
-#define SCB_CPUID_PARTNO_M (0x0000fff0) /* */
-/* SCB_CPUID[SCB_CPUID_CONSTANT] Bits */
-#define SCB_CPUID_CONSTANT_OFS (16) /* CONSTANT Offset */
-#define SCB_CPUID_CONSTANT_M (0x000f0000) /* */
-/* SCB_CPUID[SCB_CPUID_VARIANT] Bits */
-#define SCB_CPUID_VARIANT_OFS (20) /* VARIANT Offset */
-#define SCB_CPUID_VARIANT_M (0x00f00000) /* */
-/* SCB_CPUID[SCB_CPUID_IMPLEMENTER] Bits */
-#define SCB_CPUID_IMPLEMENTER_OFS (24) /* IMPLEMENTER Offset */
-#define SCB_CPUID_IMPLEMENTER_M (0xff000000) /* */
-/* SCB_ICSR[SCB_ICSR_VECTACTIVE] Bits */
-#define SCB_ICSR_VECTACTIVE_OFS ( 0) /* VECTACTIVE Offset */
-#define SCB_ICSR_VECTACTIVE_M (0x000001ff) /* */
-/* SCB_ICSR[SCB_ICSR_RETTOBASE] Bits */
-#define SCB_ICSR_RETTOBASE_OFS (11) /* RETTOBASE Offset */
-#define SCB_ICSR_RETTOBASE (0x00000800) /* */
-/* SCB_ICSR[SCB_ICSR_VECTPENDING] Bits */
-#define SCB_ICSR_VECTPENDING_OFS (12) /* VECTPENDING Offset */
-#define SCB_ICSR_VECTPENDING_M (0x0003f000) /* */
-/* SCB_ICSR[SCB_ICSR_ISRPENDING] Bits */
-#define SCB_ICSR_ISRPENDING_OFS (22) /* ISRPENDING Offset */
-#define SCB_ICSR_ISRPENDING (0x00400000) /* */
-/* SCB_ICSR[SCB_ICSR_ISRPREEMPT] Bits */
-#define SCB_ICSR_ISRPREEMPT_OFS (23) /* ISRPREEMPT Offset */
-#define SCB_ICSR_ISRPREEMPT (0x00800000) /* */
-/* SCB_ICSR[SCB_ICSR_PENDSTCLR] Bits */
-#define SCB_ICSR_PENDSTCLR_OFS (25) /* PENDSTCLR Offset */
-#define SCB_ICSR_PENDSTCLR (0x02000000) /* */
-/* SCB_ICSR[SCB_ICSR_PENDSTSET] Bits */
-#define SCB_ICSR_PENDSTSET_OFS (26) /* PENDSTSET Offset */
-#define SCB_ICSR_PENDSTSET (0x04000000) /* */
-/* SCB_ICSR[SCB_ICSR_PENDSVCLR] Bits */
-#define SCB_ICSR_PENDSVCLR_OFS (27) /* PENDSVCLR Offset */
-#define SCB_ICSR_PENDSVCLR (0x08000000) /* */
-/* SCB_ICSR[SCB_ICSR_PENDSVSET] Bits */
-#define SCB_ICSR_PENDSVSET_OFS (28) /* PENDSVSET Offset */
-#define SCB_ICSR_PENDSVSET (0x10000000) /* */
-/* SCB_ICSR[SCB_ICSR_NMIPENDSET] Bits */
-#define SCB_ICSR_NMIPENDSET_OFS (31) /* NMIPENDSET Offset */
-#define SCB_ICSR_NMIPENDSET (0x80000000) /* */
-/* SCB_VTOR[SCB_VTOR_TBLOFF] Bits */
-#define SCB_VTOR_TBLOFF_OFS ( 7) /* TBLOFF Offset */
-#define SCB_VTOR_TBLOFF_M (0x1fffff80) /* */
-/* SCB_VTOR[SCB_VTOR_TBLBASE] Bits */
-#define SCB_VTOR_TBLBASE_OFS (29) /* TBLBASE Offset */
-#define SCB_VTOR_TBLBASE (0x20000000) /* */
-/* SCB_AIRCR[SCB_AIRCR_VECTRESET] Bits */
-#define SCB_AIRCR_VECTRESET_OFS ( 0) /* VECTRESET Offset */
-#define SCB_AIRCR_VECTRESET (0x00000001) /* */
-/* SCB_AIRCR[SCB_AIRCR_VECTCLRACTIVE] Bits */
-#define SCB_AIRCR_VECTCLRACTIVE_OFS ( 1) /* VECTCLRACTIVE Offset */
-#define SCB_AIRCR_VECTCLRACTIVE (0x00000002) /* */
-/* SCB_AIRCR[SCB_AIRCR_SYSRESETREQ] Bits */
-#define SCB_AIRCR_SYSRESETREQ_OFS ( 2) /* SYSRESETREQ Offset */
-#define SCB_AIRCR_SYSRESETREQ (0x00000004) /* */
-/* SCB_AIRCR[SCB_AIRCR_PRIGROUP] Bits */
-#define SCB_AIRCR_PRIGROUP_OFS ( 8) /* PRIGROUP Offset */
-#define SCB_AIRCR_PRIGROUP_M (0x00000700) /* */
-/* SCB_AIRCR[SCB_AIRCR_ENDIANESS] Bits */
-#define SCB_AIRCR_ENDIANESS_OFS (15) /* ENDIANESS Offset */
-#define SCB_AIRCR_ENDIANESS (0x00008000) /* */
-/* SCB_AIRCR[SCB_AIRCR_VECTKEY] Bits */
-#define SCB_AIRCR_VECTKEY_OFS (16) /* VECTKEY Offset */
-#define SCB_AIRCR_VECTKEY_M (0xffff0000) /* */
-/* SCB_SCR[SCB_SCR_SLEEPONEXIT] Bits */
-#define SCB_SCR_SLEEPONEXIT_OFS ( 1) /* SLEEPONEXIT Offset */
-#define SCB_SCR_SLEEPONEXIT (0x00000002) /* */
-/* SCB_SCR[SCB_SCR_SLEEPDEEP] Bits */
-#define SCB_SCR_SLEEPDEEP_OFS ( 2) /* SLEEPDEEP Offset */
-#define SCB_SCR_SLEEPDEEP (0x00000004) /* */
-/* SCB_SCR[SCB_SCR_SEVONPEND] Bits */
-#define SCB_SCR_SEVONPEND_OFS ( 4) /* SEVONPEND Offset */
-#define SCB_SCR_SEVONPEND (0x00000010) /* */
-/* SCB_CCR[SCB_CCR_NONBASETHREDENA] Bits */
-#define SCB_CCR_NONBASETHREDENA_OFS ( 0) /* NONBASETHREDENA Offset */
-#define SCB_CCR_NONBASETHREDENA (0x00000001) /* */
-/* SCB_CCR[SCB_CCR_USERSETMPEND] Bits */
-#define SCB_CCR_USERSETMPEND_OFS ( 1) /* USERSETMPEND Offset */
-#define SCB_CCR_USERSETMPEND (0x00000002) /* */
-/* SCB_CCR[SCB_CCR_UNALIGN_TRP] Bits */
-#define SCB_CCR_UNALIGN_TRP_OFS ( 3) /* UNALIGN_TRP Offset */
-#define SCB_CCR_UNALIGN_TRP (0x00000008) /* */
-/* SCB_CCR[SCB_CCR_DIV_0_TRP] Bits */
-#define SCB_CCR_DIV_0_TRP_OFS ( 4) /* DIV_0_TRP Offset */
-#define SCB_CCR_DIV_0_TRP (0x00000010) /* */
-/* SCB_CCR[SCB_CCR_BFHFNMIGN] Bits */
-#define SCB_CCR_BFHFNMIGN_OFS ( 8) /* BFHFNMIGN Offset */
-#define SCB_CCR_BFHFNMIGN (0x00000100) /* */
-/* SCB_CCR[SCB_CCR_STKALIGN] Bits */
-#define SCB_CCR_STKALIGN_OFS ( 9) /* STKALIGN Offset */
-#define SCB_CCR_STKALIGN (0x00000200) /* */
-/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */
-#define SCB_SHPR1_PRI_4_OFS ( 0) /* PRI_4 Offset */
-#define SCB_SHPR1_PRI_4_M (0x000000ff) /* */
-/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */
-#define SCB_SHPR1_PRI_5_OFS ( 8) /* PRI_5 Offset */
-#define SCB_SHPR1_PRI_5_M (0x0000ff00) /* */
-/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */
-#define SCB_SHPR1_PRI_6_OFS (16) /* PRI_6 Offset */
-#define SCB_SHPR1_PRI_6_M (0x00ff0000) /* */
-/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */
-#define SCB_SHPR1_PRI_7_OFS (24) /* PRI_7 Offset */
-#define SCB_SHPR1_PRI_7_M (0xff000000) /* */
-/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */
-#define SCB_SHPR2_PRI_8_OFS ( 0) /* PRI_8 Offset */
-#define SCB_SHPR2_PRI_8_M (0x000000ff) /* */
-/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */
-#define SCB_SHPR2_PRI_9_OFS ( 8) /* PRI_9 Offset */
-#define SCB_SHPR2_PRI_9_M (0x0000ff00) /* */
-/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */
-#define SCB_SHPR2_PRI_10_OFS (16) /* PRI_10 Offset */
-#define SCB_SHPR2_PRI_10_M (0x00ff0000) /* */
-/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */
-#define SCB_SHPR2_PRI_11_OFS (24) /* PRI_11 Offset */
-#define SCB_SHPR2_PRI_11_M (0xff000000) /* */
-/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */
-#define SCB_SHPR3_PRI_12_OFS ( 0) /* PRI_12 Offset */
-#define SCB_SHPR3_PRI_12_M (0x000000ff) /* */
-/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */
-#define SCB_SHPR3_PRI_13_OFS ( 8) /* PRI_13 Offset */
-#define SCB_SHPR3_PRI_13_M (0x0000ff00) /* */
-/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */
-#define SCB_SHPR3_PRI_14_OFS (16) /* PRI_14 Offset */
-#define SCB_SHPR3_PRI_14_M (0x00ff0000) /* */
-/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */
-#define SCB_SHPR3_PRI_15_OFS (24) /* PRI_15 Offset */
-#define SCB_SHPR3_PRI_15_M (0xff000000) /* */
-/* SCB_SHCSR[SCB_SHCSR_MEMFAULTACT] Bits */
-#define SCB_SHCSR_MEMFAULTACT_OFS ( 0) /* MEMFAULTACT Offset */
-#define SCB_SHCSR_MEMFAULTACT (0x00000001) /* */
-/* SCB_SHCSR[SCB_SHCSR_BUSFAULTACT] Bits */
-#define SCB_SHCSR_BUSFAULTACT_OFS ( 1) /* BUSFAULTACT Offset */
-#define SCB_SHCSR_BUSFAULTACT (0x00000002) /* */
-/* SCB_SHCSR[SCB_SHCSR_USGFAULTACT] Bits */
-#define SCB_SHCSR_USGFAULTACT_OFS ( 3) /* USGFAULTACT Offset */
-#define SCB_SHCSR_USGFAULTACT (0x00000008) /* */
-/* SCB_SHCSR[SCB_SHCSR_SVCALLACT] Bits */
-#define SCB_SHCSR_SVCALLACT_OFS ( 7) /* SVCALLACT Offset */
-#define SCB_SHCSR_SVCALLACT (0x00000080) /* */
-/* SCB_SHCSR[SCB_SHCSR_MONITORACT] Bits */
-#define SCB_SHCSR_MONITORACT_OFS ( 8) /* MONITORACT Offset */
-#define SCB_SHCSR_MONITORACT (0x00000100) /* */
-/* SCB_SHCSR[SCB_SHCSR_PENDSVACT] Bits */
-#define SCB_SHCSR_PENDSVACT_OFS (10) /* PENDSVACT Offset */
-#define SCB_SHCSR_PENDSVACT (0x00000400) /* */
-/* SCB_SHCSR[SCB_SHCSR_SYSTICKACT] Bits */
-#define SCB_SHCSR_SYSTICKACT_OFS (11) /* SYSTICKACT Offset */
-#define SCB_SHCSR_SYSTICKACT (0x00000800) /* */
-/* SCB_SHCSR[SCB_SHCSR_USGFAULTPENDED] Bits */
-#define SCB_SHCSR_USGFAULTPENDED_OFS (12) /* USGFAULTPENDED Offset */
-#define SCB_SHCSR_USGFAULTPENDED (0x00001000) /* */
-/* SCB_SHCSR[SCB_SHCSR_MEMFAULTPENDED] Bits */
-#define SCB_SHCSR_MEMFAULTPENDED_OFS (13) /* MEMFAULTPENDED Offset */
-#define SCB_SHCSR_MEMFAULTPENDED (0x00002000) /* */
-/* SCB_SHCSR[SCB_SHCSR_BUSFAULTPENDED] Bits */
-#define SCB_SHCSR_BUSFAULTPENDED_OFS (14) /* BUSFAULTPENDED Offset */
-#define SCB_SHCSR_BUSFAULTPENDED (0x00004000) /* */
-/* SCB_SHCSR[SCB_SHCSR_SVCALLPENDED] Bits */
-#define SCB_SHCSR_SVCALLPENDED_OFS (15) /* SVCALLPENDED Offset */
-#define SCB_SHCSR_SVCALLPENDED (0x00008000) /* */
-/* SCB_SHCSR[SCB_SHCSR_MEMFAULTENA] Bits */
-#define SCB_SHCSR_MEMFAULTENA_OFS (16) /* MEMFAULTENA Offset */
-#define SCB_SHCSR_MEMFAULTENA (0x00010000) /* */
-/* SCB_SHCSR[SCB_SHCSR_BUSFAULTENA] Bits */
-#define SCB_SHCSR_BUSFAULTENA_OFS (17) /* BUSFAULTENA Offset */
-#define SCB_SHCSR_BUSFAULTENA (0x00020000) /* */
-/* SCB_SHCSR[SCB_SHCSR_USGFAULTENA] Bits */
-#define SCB_SHCSR_USGFAULTENA_OFS (18) /* USGFAULTENA Offset */
-#define SCB_SHCSR_USGFAULTENA (0x00040000) /* */
-/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */
-#define SCB_CFSR_IACCVIOL_OFS ( 0) /* IACCVIOL Offset */
-#define SCB_CFSR_IACCVIOL (0x00000001) /* */
-/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */
-#define SCB_CFSR_DACCVIOL_OFS ( 1) /* DACCVIOL Offset */
-#define SCB_CFSR_DACCVIOL (0x00000002) /* */
-/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */
-#define SCB_CFSR_MUNSTKERR_OFS ( 3) /* MUNSTKERR Offset */
-#define SCB_CFSR_MUNSTKERR (0x00000008) /* */
-/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */
-#define SCB_CFSR_MSTKERR_OFS ( 4) /* MSTKERR Offset */
-#define SCB_CFSR_MSTKERR (0x00000010) /* */
-/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */
-#define SCB_CFSR_MMARVALID_OFS ( 7) /* MMARVALID Offset */
-#define SCB_CFSR_MMARVALID (0x00000080) /* */
-/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */
-#define SCB_CFSR_IBUSERR_OFS ( 8) /* IBUSERR Offset */
-#define SCB_CFSR_IBUSERR (0x00000100) /* */
-/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */
-#define SCB_CFSR_PRECISERR_OFS ( 9) /* PRECISERR Offset */
-#define SCB_CFSR_PRECISERR (0x00000200) /* */
-/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */
-#define SCB_CFSR_IMPRECISERR_OFS (10) /* IMPRECISERR Offset */
-#define SCB_CFSR_IMPRECISERR (0x00000400) /* */
-/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */
-#define SCB_CFSR_UNSTKERR_OFS (11) /* UNSTKERR Offset */
-#define SCB_CFSR_UNSTKERR (0x00000800) /* */
-/* SCB_CFSR[SCB_CFSR_STKERR] Bits */
-#define SCB_CFSR_STKERR_OFS (12) /* STKERR Offset */
-#define SCB_CFSR_STKERR (0x00001000) /* */
-/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */
-#define SCB_CFSR_BFARVALID_OFS (15) /* BFARVALID Offset */
-#define SCB_CFSR_BFARVALID (0x00008000) /* */
-/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */
-#define SCB_CFSR_UNDEFINSTR_OFS (16) /* UNDEFINSTR Offset */
-#define SCB_CFSR_UNDEFINSTR (0x00010000) /* */
-/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */
-#define SCB_CFSR_INVSTATE_OFS (17) /* INVSTATE Offset */
-#define SCB_CFSR_INVSTATE (0x00020000) /* */
-/* SCB_CFSR[SCB_CFSR_INVPC] Bits */
-#define SCB_CFSR_INVPC_OFS (18) /* INVPC Offset */
-#define SCB_CFSR_INVPC (0x00040000) /* */
-/* SCB_CFSR[SCB_CFSR_NOCP] Bits */
-#define SCB_CFSR_NOCP_OFS (19) /* NOCP Offset */
-#define SCB_CFSR_NOCP (0x00080000) /* */
-/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */
-#define SCB_CFSR_UNALIGNED_OFS (24) /* UNALIGNED Offset */
-#define SCB_CFSR_UNALIGNED (0x01000000) /* */
-/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */
-#define SCB_CFSR_DIVBYZERO_OFS (25) /* DIVBYZERO Offset */
-#define SCB_CFSR_DIVBYZERO (0x02000000) /* */
-/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */
-#define SCB_CFSR_MLSPERR_OFS ( 5) /* MLSPERR Offset */
-#define SCB_CFSR_MLSPERR (0x00000020) /* */
-/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */
-#define SCB_CFSR_LSPERR_OFS (13) /* LSPERR Offset */
-#define SCB_CFSR_LSPERR (0x00002000) /* */
-/* SCB_HFSR[SCB_HFSR_VECTTBL] Bits */
-#define SCB_HFSR_VECTTBL_OFS ( 1) /* VECTTBL Offset */
-#define SCB_HFSR_VECTTBL (0x00000002) /* */
-/* SCB_HFSR[SCB_HFSR_FORCED] Bits */
-#define SCB_HFSR_FORCED_OFS (30) /* FORCED Offset */
-#define SCB_HFSR_FORCED (0x40000000) /* */
-/* SCB_HFSR[SCB_HFSR_DEBUGEVT] Bits */
-#define SCB_HFSR_DEBUGEVT_OFS (31) /* DEBUGEVT Offset */
-#define SCB_HFSR_DEBUGEVT (0x80000000) /* */
-/* SCB_DFSR[SCB_DFSR_HALTED] Bits */
-#define SCB_DFSR_HALTED_OFS ( 0) /* HALTED Offset */
-#define SCB_DFSR_HALTED (0x00000001) /* */
-/* SCB_DFSR[SCB_DFSR_BKPT] Bits */
-#define SCB_DFSR_BKPT_OFS ( 1) /* BKPT Offset */
-#define SCB_DFSR_BKPT (0x00000002) /* */
-/* SCB_DFSR[SCB_DFSR_DWTTRAP] Bits */
-#define SCB_DFSR_DWTTRAP_OFS ( 2) /* DWTTRAP Offset */
-#define SCB_DFSR_DWTTRAP (0x00000004) /* */
-/* SCB_DFSR[SCB_DFSR_VCATCH] Bits */
-#define SCB_DFSR_VCATCH_OFS ( 3) /* VCATCH Offset */
-#define SCB_DFSR_VCATCH (0x00000008) /* */
-/* SCB_DFSR[SCB_DFSR_EXTERNAL] Bits */
-#define SCB_DFSR_EXTERNAL_OFS ( 4) /* EXTERNAL Offset */
-#define SCB_DFSR_EXTERNAL (0x00000010) /* */
-/* SCB_PFR0[SCB_PFR0_STATE0] Bits */
-#define SCB_PFR0_STATE0_OFS ( 0) /* STATE0 Offset */
-#define SCB_PFR0_STATE0_M (0x0000000f) /* */
-#define SCB_PFR0_STATE00 (0x00000001) /* */
-#define SCB_PFR0_STATE01 (0x00000002) /* */
-#define SCB_PFR0_STATE02 (0x00000004) /* */
-#define SCB_PFR0_STATE03 (0x00000008) /* */
-#define SCB_PFR0_STATE0_0 (0x00000000) /* no ARM encoding */
-#define SCB_PFR0_STATE0_1 (0x00000001) /* N/A */
-/* SCB_PFR0[SCB_PFR0_STATE1] Bits */
-#define SCB_PFR0_STATE1_OFS ( 4) /* STATE1 Offset */
-#define SCB_PFR0_STATE1_M (0x000000f0) /* */
-#define SCB_PFR0_STATE10 (0x00000010) /* */
-#define SCB_PFR0_STATE11 (0x00000020) /* */
-#define SCB_PFR0_STATE12 (0x00000040) /* */
-#define SCB_PFR0_STATE13 (0x00000080) /* */
-#define SCB_PFR0_STATE1_0 (0x00000000) /* N/A */
-#define SCB_PFR0_STATE1_1 (0x00000010) /* N/A */
-#define SCB_PFR0_STATE1_2 (0x00000020) /* Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) */
-#define SCB_PFR0_STATE1_3 (0x00000030) /* Thumb-2 encoding with all Thumb-2 basic instructions */
-/* SCB_PFR1[SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /* MICROCONTROLLER_PROGRAMMERS_MODEL Offset */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M (0x00000f00) /* */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 (0x00000100) /* */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 (0x00000200) /* */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 (0x00000400) /* */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 (0x00000800) /* */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 (0x00000000) /* not supported */
-#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 (0x00000200) /* two-stack support */
-/* SCB_DFR0[SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL] Bits */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /* MICROCONTROLLER_DEBUG_MODEL Offset */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_M (0x00f00000) /* */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 (0x00100000) /* */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 (0x00200000) /* */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 (0x00400000) /* */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 (0x00800000) /* */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 (0x00000000) /* not supported */
-#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 (0x00100000) /* Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */
-/* SCB_MMFR0[SCB_MMFR0_PMSA_SUPPORT] Bits */
-#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /* PMSA_SUPPORT Offset */
-#define SCB_MMFR0_PMSA_SUPPORT_M (0x000000f0) /* */
-#define SCB_MMFR0_PMSA_SUPPORT0 (0x00000010) /* */
-#define SCB_MMFR0_PMSA_SUPPORT1 (0x00000020) /* */
-#define SCB_MMFR0_PMSA_SUPPORT2 (0x00000040) /* */
-#define SCB_MMFR0_PMSA_SUPPORT3 (0x00000080) /* */
-#define SCB_MMFR0_PMSA_SUPPORT_0 (0x00000000) /* not supported */
-#define SCB_MMFR0_PMSA_SUPPORT_1 (0x00000010) /* IMPLEMENTATION DEFINED (N/A) */
-#define SCB_MMFR0_PMSA_SUPPORT_2 (0x00000020) /* PMSA base (features as defined for ARMv6) (N/A) */
-#define SCB_MMFR0_PMSA_SUPPORT_3 (0x00000030) /* PMSAv7 (base plus subregion support) */
-/* SCB_MMFR0[SCB_MMFR0_CACHE_COHERENCE_SUPPORT] Bits */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /* CACHE_COHERENCE_SUPPORT Offset */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_M (0x00000f00) /* */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 (0x00000100) /* */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 (0x00000200) /* */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 (0x00000400) /* */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 (0x00000800) /* */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 (0x00000000) /* no shared support */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 (0x00000100) /* partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain) */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 (0x00000200) /* full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain) */
-#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 (0x00000300) /* full coherency (coherency amongst all of the entities) */
-/* SCB_MMFR0[SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT] Bits */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /* OUTER_NON_SHARABLE_SUPPORT Offset */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_M (0x0000f000) /* */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 (0x00001000) /* */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 (0x00002000) /* */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 (0x00004000) /* */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 (0x00008000) /* */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 (0x00000000) /* Outer non-sharable not supported */
-#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 (0x00001000) /* Outer sharable supported */
-/* SCB_MMFR0[SCB_MMFR0_AUILIARY_REGISTER_SUPPORT] Bits */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /* AUXILIARY_REGISTER_SUPPORT Offset */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_M (0x00f00000) /* */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 (0x00100000) /* */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 (0x00200000) /* */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 (0x00400000) /* */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 (0x00800000) /* */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 (0x00000000) /* not supported */
-#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 (0x00100000) /* Auxiliary control register */
-/* SCB_MMFR2[SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING] Bits */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /* WAIT_FOR_INTERRUPT_STALLING Offset */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M (0x0f000000) /* */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 (0x01000000) /* */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 (0x02000000) /* */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 (0x04000000) /* */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 (0x08000000) /* */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 (0x00000000) /* not supported */
-#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 (0x01000000) /* wait for interrupt supported */
-/* SCB_ISAR0[SCB_ISAR0_BITCOUNT_INSTRS] Bits */
-#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /* BITCOUNT_INSTRS Offset */
-#define SCB_ISAR0_BITCOUNT_INSTRS_M (0x000000f0) /* */
-#define SCB_ISAR0_BITCOUNT_INSTRS0 (0x00000010) /* */
-#define SCB_ISAR0_BITCOUNT_INSTRS1 (0x00000020) /* */
-#define SCB_ISAR0_BITCOUNT_INSTRS2 (0x00000040) /* */
-#define SCB_ISAR0_BITCOUNT_INSTRS3 (0x00000080) /* */
-#define SCB_ISAR0_BITCOUNT_INSTRS_0 (0x00000000) /* no bit-counting instructions present */
-#define SCB_ISAR0_BITCOUNT_INSTRS_1 (0x00000010) /* adds CLZ */
-/* SCB_ISAR0[SCB_ISAR0_BITFIELD_INSTRS] Bits */
-#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /* BITFIELD_INSTRS Offset */
-#define SCB_ISAR0_BITFIELD_INSTRS_M (0x00000f00) /* */
-#define SCB_ISAR0_BITFIELD_INSTRS0 (0x00000100) /* */
-#define SCB_ISAR0_BITFIELD_INSTRS1 (0x00000200) /* */
-#define SCB_ISAR0_BITFIELD_INSTRS2 (0x00000400) /* */
-#define SCB_ISAR0_BITFIELD_INSTRS3 (0x00000800) /* */
-#define SCB_ISAR0_BITFIELD_INSTRS_0 (0x00000000) /* no bitfield instructions present */
-#define SCB_ISAR0_BITFIELD_INSTRS_1 (0x00000100) /* adds BFC, BFI, SBFX, UBFX */
-/* SCB_ISAR0[SCB_ISAR0_CMPBRANCH_INSTRS] Bits */
-#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /* CMPBRANCH_INSTRS Offset */
-#define SCB_ISAR0_CMPBRANCH_INSTRS_M (0x0000f000) /* */
-#define SCB_ISAR0_CMPBRANCH_INSTRS0 (0x00001000) /* */
-#define SCB_ISAR0_CMPBRANCH_INSTRS1 (0x00002000) /* */
-#define SCB_ISAR0_CMPBRANCH_INSTRS2 (0x00004000) /* */
-#define SCB_ISAR0_CMPBRANCH_INSTRS3 (0x00008000) /* */
-#define SCB_ISAR0_CMPBRANCH_INSTRS_0 (0x00000000) /* no combined compare-and-branch instructions present */
-#define SCB_ISAR0_CMPBRANCH_INSTRS_1 (0x00001000) /* adds CB{N}Z */
-/* SCB_ISAR0[SCB_ISAR0_COPROC_INSTRS] Bits */
-#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /* COPROC_INSTRS Offset */
-#define SCB_ISAR0_COPROC_INSTRS_M (0x000f0000) /* */
-#define SCB_ISAR0_COPROC_INSTRS0 (0x00010000) /* */
-#define SCB_ISAR0_COPROC_INSTRS1 (0x00020000) /* */
-#define SCB_ISAR0_COPROC_INSTRS2 (0x00040000) /* */
-#define SCB_ISAR0_COPROC_INSTRS3 (0x00080000) /* */
-#define SCB_ISAR0_COPROC_INSTRS_0 (0x00000000) /* no coprocessor support, other than for separately attributed architectures such as CP15 or VFP */
-#define SCB_ISAR0_COPROC_INSTRS_1 (0x00010000) /* adds generic CDP, LDC, MCR, MRC, STC */
-#define SCB_ISAR0_COPROC_INSTRS_2 (0x00020000) /* adds generic CDP2, LDC2, MCR2, MRC2, STC2 */
-#define SCB_ISAR0_COPROC_INSTRS_3 (0x00030000) /* adds generic MCRR, MRRC */
-#define SCB_ISAR0_COPROC_INSTRS_4 (0x00040000) /* adds generic MCRR2, MRRC2 */
-/* SCB_ISAR0[SCB_ISAR0_DEBUG_INSTRS] Bits */
-#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /* DEBUG_INSTRS Offset */
-#define SCB_ISAR0_DEBUG_INSTRS_M (0x00f00000) /* */
-#define SCB_ISAR0_DEBUG_INSTRS0 (0x00100000) /* */
-#define SCB_ISAR0_DEBUG_INSTRS1 (0x00200000) /* */
-#define SCB_ISAR0_DEBUG_INSTRS2 (0x00400000) /* */
-#define SCB_ISAR0_DEBUG_INSTRS3 (0x00800000) /* */
-#define SCB_ISAR0_DEBUG_INSTRS_0 (0x00000000) /* no debug instructions present */
-#define SCB_ISAR0_DEBUG_INSTRS_1 (0x00100000) /* adds BKPT */
-/* SCB_ISAR0[SCB_ISAR0_DIVIDE_INSTRS] Bits */
-#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /* DIVIDE_INSTRS Offset */
-#define SCB_ISAR0_DIVIDE_INSTRS_M (0x0f000000) /* */
-#define SCB_ISAR0_DIVIDE_INSTRS0 (0x01000000) /* */
-#define SCB_ISAR0_DIVIDE_INSTRS1 (0x02000000) /* */
-#define SCB_ISAR0_DIVIDE_INSTRS2 (0x04000000) /* */
-#define SCB_ISAR0_DIVIDE_INSTRS3 (0x08000000) /* */
-#define SCB_ISAR0_DIVIDE_INSTRS_0 (0x00000000) /* no divide instructions present */
-#define SCB_ISAR0_DIVIDE_INSTRS_1 (0x01000000) /* adds SDIV, UDIV (v1 quotient only result) */
-/* SCB_ISAR1[SCB_ISAR1_ETEND_INSRS] Bits */
-#define SCB_ISAR1_ETEND_INSRS_OFS (12) /* EXTEND_INSRS Offset */
-#define SCB_ISAR1_ETEND_INSRS_M (0x0000f000) /* */
-#define SCB_ISAR1_ETEND_INSRS0 (0x00001000) /* */
-#define SCB_ISAR1_ETEND_INSRS1 (0x00002000) /* */
-#define SCB_ISAR1_ETEND_INSRS2 (0x00004000) /* */
-#define SCB_ISAR1_ETEND_INSRS3 (0x00008000) /* */
-#define SCB_ISAR1_ETEND_INSRS_0 (0x00000000) /* no scalar (i.e. non-SIMD) sign/zero-extend instructions present */
-#define SCB_ISAR1_ETEND_INSRS_1 (0x00001000) /* adds SXTB, SXTH, UXTB, UXTH */
-#define SCB_ISAR1_ETEND_INSRS_2 (0x00002000) /* N/A */
-/* SCB_ISAR1[SCB_ISAR1_IFTHEN_INSTRS] Bits */
-#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /* IFTHEN_INSTRS Offset */
-#define SCB_ISAR1_IFTHEN_INSTRS_M (0x000f0000) /* */
-#define SCB_ISAR1_IFTHEN_INSTRS0 (0x00010000) /* */
-#define SCB_ISAR1_IFTHEN_INSTRS1 (0x00020000) /* */
-#define SCB_ISAR1_IFTHEN_INSTRS2 (0x00040000) /* */
-#define SCB_ISAR1_IFTHEN_INSTRS3 (0x00080000) /* */
-#define SCB_ISAR1_IFTHEN_INSTRS_0 (0x00000000) /* IT instructions not present */
-#define SCB_ISAR1_IFTHEN_INSTRS_1 (0x00010000) /* adds IT instructions (and IT bits in PSRs) */
-/* SCB_ISAR1[SCB_ISAR1_IMMEDIATE_INSTRS] Bits */
-#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /* IMMEDIATE_INSTRS Offset */
-#define SCB_ISAR1_IMMEDIATE_INSTRS_M (0x00f00000) /* */
-#define SCB_ISAR1_IMMEDIATE_INSTRS0 (0x00100000) /* */
-#define SCB_ISAR1_IMMEDIATE_INSTRS1 (0x00200000) /* */
-#define SCB_ISAR1_IMMEDIATE_INSTRS2 (0x00400000) /* */
-#define SCB_ISAR1_IMMEDIATE_INSTRS3 (0x00800000) /* */
-#define SCB_ISAR1_IMMEDIATE_INSTRS_0 (0x00000000) /* no special immediate-generating instructions present */
-#define SCB_ISAR1_IMMEDIATE_INSTRS_1 (0x00100000) /* adds ADDW, MOVW, MOVT, SUBW */
-/* SCB_ISAR1[SCB_ISAR1_INTERWORK_INSTRS] Bits */
-#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /* INTERWORK_INSTRS Offset */
-#define SCB_ISAR1_INTERWORK_INSTRS_M (0x0f000000) /* */
-#define SCB_ISAR1_INTERWORK_INSTRS0 (0x01000000) /* */
-#define SCB_ISAR1_INTERWORK_INSTRS1 (0x02000000) /* */
-#define SCB_ISAR1_INTERWORK_INSTRS2 (0x04000000) /* */
-#define SCB_ISAR1_INTERWORK_INSTRS3 (0x08000000) /* */
-#define SCB_ISAR1_INTERWORK_INSTRS_0 (0x00000000) /* no interworking instructions supported */
-#define SCB_ISAR1_INTERWORK_INSTRS_1 (0x01000000) /* adds BX (and T bit in PSRs) */
-#define SCB_ISAR1_INTERWORK_INSTRS_2 (0x02000000) /* adds BLX, and PC loads have BX-like behavior */
-#define SCB_ISAR1_INTERWORK_INSTRS_3 (0x03000000) /* N/A */
-/* SCB_ISAR2[SCB_ISAR2_LOADSTORE_INSTRS] Bits */
-#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /* LOADSTORE_INSTRS Offset */
-#define SCB_ISAR2_LOADSTORE_INSTRS_M (0x0000000f) /* */
-#define SCB_ISAR2_LOADSTORE_INSTRS0 (0x00000001) /* */
-#define SCB_ISAR2_LOADSTORE_INSTRS1 (0x00000002) /* */
-#define SCB_ISAR2_LOADSTORE_INSTRS2 (0x00000004) /* */
-#define SCB_ISAR2_LOADSTORE_INSTRS3 (0x00000008) /* */
-#define SCB_ISAR2_LOADSTORE_INSTRS_0 (0x00000000) /* no additional normal load/store instructions present */
-#define SCB_ISAR2_LOADSTORE_INSTRS_1 (0x00000001) /* adds LDRD/STRD */
-/* SCB_ISAR2[SCB_ISAR2_MEMHINT_INSTRS] Bits */
-#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /* MEMHINT_INSTRS Offset */
-#define SCB_ISAR2_MEMHINT_INSTRS_M (0x000000f0) /* */
-#define SCB_ISAR2_MEMHINT_INSTRS0 (0x00000010) /* */
-#define SCB_ISAR2_MEMHINT_INSTRS1 (0x00000020) /* */
-#define SCB_ISAR2_MEMHINT_INSTRS2 (0x00000040) /* */
-#define SCB_ISAR2_MEMHINT_INSTRS3 (0x00000080) /* */
-#define SCB_ISAR2_MEMHINT_INSTRS_0 (0x00000000) /* no memory hint instructions presen */
-#define SCB_ISAR2_MEMHINT_INSTRS_1 (0x00000010) /* adds PLD */
-#define SCB_ISAR2_MEMHINT_INSTRS_2 (0x00000020) /* adds PLD (ie a repeat on value 1) */
-#define SCB_ISAR2_MEMHINT_INSTRS_3 (0x00000030) /* adds PLI */
-/* SCB_ISAR2[SCB_ISAR2_MULTIACCESSINT_INSTRS] Bits */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /* MULTIACCESSINT_INSTRS Offset */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_M (0x00000f00) /* */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 (0x00000100) /* */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 (0x00000200) /* */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 (0x00000400) /* */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 (0x00000800) /* */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 (0x00000000) /* the (LDM/STM) instructions are non-interruptible */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 (0x00000100) /* the (LDM/STM) instructions are restartable */
-#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 (0x00000200) /* the (LDM/STM) instructions are continuable */
-/* SCB_ISAR2[SCB_ISAR2_MULT_INSTRS] Bits */
-#define SCB_ISAR2_MULT_INSTRS_OFS (12) /* MULT_INSTRS Offset */
-#define SCB_ISAR2_MULT_INSTRS_M (0x0000f000) /* */
-#define SCB_ISAR2_MULT_INSTRS0 (0x00001000) /* */
-#define SCB_ISAR2_MULT_INSTRS1 (0x00002000) /* */
-#define SCB_ISAR2_MULT_INSTRS2 (0x00004000) /* */
-#define SCB_ISAR2_MULT_INSTRS3 (0x00008000) /* */
-#define SCB_ISAR2_MULT_INSTRS_0 (0x00000000) /* only MUL present */
-#define SCB_ISAR2_MULT_INSTRS_1 (0x00001000) /* adds MLA */
-#define SCB_ISAR2_MULT_INSTRS_2 (0x00002000) /* adds MLS */
-/* SCB_ISAR2[SCB_ISAR2_MULTS_INSTRS] Bits */
-#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /* MULTS_INSTRS Offset */
-#define SCB_ISAR2_MULTS_INSTRS_M (0x000f0000) /* */
-#define SCB_ISAR2_MULTS_INSTRS0 (0x00010000) /* */
-#define SCB_ISAR2_MULTS_INSTRS1 (0x00020000) /* */
-#define SCB_ISAR2_MULTS_INSTRS2 (0x00040000) /* */
-#define SCB_ISAR2_MULTS_INSTRS3 (0x00080000) /* */
-#define SCB_ISAR2_MULTS_INSTRS_0 (0x00000000) /* no signed multiply instructions present */
-#define SCB_ISAR2_MULTS_INSTRS_1 (0x00010000) /* adds SMULL, SMLAL */
-#define SCB_ISAR2_MULTS_INSTRS_2 (0x00020000) /* N/A */
-#define SCB_ISAR2_MULTS_INSTRS_3 (0x00030000) /* N/A */
-/* SCB_ISAR2[SCB_ISAR2_MULTU_INSTRS] Bits */
-#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /* MULTU_INSTRS Offset */
-#define SCB_ISAR2_MULTU_INSTRS_M (0x00f00000) /* */
-#define SCB_ISAR2_MULTU_INSTRS0 (0x00100000) /* */
-#define SCB_ISAR2_MULTU_INSTRS1 (0x00200000) /* */
-#define SCB_ISAR2_MULTU_INSTRS2 (0x00400000) /* */
-#define SCB_ISAR2_MULTU_INSTRS3 (0x00800000) /* */
-#define SCB_ISAR2_MULTU_INSTRS_0 (0x00000000) /* no unsigned multiply instructions present */
-#define SCB_ISAR2_MULTU_INSTRS_1 (0x00100000) /* adds UMULL, UMLAL */
-#define SCB_ISAR2_MULTU_INSTRS_2 (0x00200000) /* N/A */
-/* SCB_ISAR2[SCB_ISAR2_REVERSAL_INSTRS] Bits */
-#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /* REVERSAL_INSTRS Offset */
-#define SCB_ISAR2_REVERSAL_INSTRS_M (0xf0000000) /* */
-#define SCB_ISAR2_REVERSAL_INSTRS0 (0x10000000) /* */
-#define SCB_ISAR2_REVERSAL_INSTRS1 (0x20000000) /* */
-#define SCB_ISAR2_REVERSAL_INSTRS2 (0x40000000) /* */
-#define SCB_ISAR2_REVERSAL_INSTRS3 (0x80000000) /* */
-#define SCB_ISAR2_REVERSAL_INSTRS_0 (0x00000000) /* no reversal instructions present */
-#define SCB_ISAR2_REVERSAL_INSTRS_1 (0x10000000) /* adds REV, REV16, REVSH */
-#define SCB_ISAR2_REVERSAL_INSTRS_2 (0x20000000) /* adds RBIT */
-/* SCB_ISAR3[SCB_ISAR3_SATRUATE_INSTRS] Bits */
-#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /* SATRUATE_INSTRS Offset */
-#define SCB_ISAR3_SATRUATE_INSTRS_M (0x0000000f) /* */
-#define SCB_ISAR3_SATRUATE_INSTRS0 (0x00000001) /* */
-#define SCB_ISAR3_SATRUATE_INSTRS1 (0x00000002) /* */
-#define SCB_ISAR3_SATRUATE_INSTRS2 (0x00000004) /* */
-#define SCB_ISAR3_SATRUATE_INSTRS3 (0x00000008) /* */
-#define SCB_ISAR3_SATRUATE_INSTRS_0 (0x00000000) /* no non-SIMD saturate instructions present */
-#define SCB_ISAR3_SATRUATE_INSTRS_1 (0x00000001) /* N/A */
-/* SCB_ISAR3[SCB_ISAR3_SIMD_INSTRS] Bits */
-#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /* SIMD_INSTRS Offset */
-#define SCB_ISAR3_SIMD_INSTRS_M (0x000000f0) /* */
-#define SCB_ISAR3_SIMD_INSTRS0 (0x00000010) /* */
-#define SCB_ISAR3_SIMD_INSTRS1 (0x00000020) /* */
-#define SCB_ISAR3_SIMD_INSTRS2 (0x00000040) /* */
-#define SCB_ISAR3_SIMD_INSTRS3 (0x00000080) /* */
-#define SCB_ISAR3_SIMD_INSTRS_0 (0x00000000) /* no SIMD instructions present */
-#define SCB_ISAR3_SIMD_INSTRS_1 (0x00000010) /* adds SSAT, USAT (and the Q flag in the PSRs) */
-#define SCB_ISAR3_SIMD_INSTRS_3 (0x00000030) /* N/A */
-/* SCB_ISAR3[SCB_ISAR3_SVC_INSTRS] Bits */
-#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /* SVC_INSTRS Offset */
-#define SCB_ISAR3_SVC_INSTRS_M (0x00000f00) /* */
-#define SCB_ISAR3_SVC_INSTRS0 (0x00000100) /* */
-#define SCB_ISAR3_SVC_INSTRS1 (0x00000200) /* */
-#define SCB_ISAR3_SVC_INSTRS2 (0x00000400) /* */
-#define SCB_ISAR3_SVC_INSTRS3 (0x00000800) /* */
-#define SCB_ISAR3_SVC_INSTRS_0 (0x00000000) /* no SVC (SWI) instructions present */
-#define SCB_ISAR3_SVC_INSTRS_1 (0x00000100) /* adds SVC (SWI) */
-/* SCB_ISAR3[SCB_ISAR3_SYNCPRIM_INSTRS] Bits */
-#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /* SYNCPRIM_INSTRS Offset */
-#define SCB_ISAR3_SYNCPRIM_INSTRS_M (0x0000f000) /* */
-#define SCB_ISAR3_SYNCPRIM_INSTRS0 (0x00001000) /* */
-#define SCB_ISAR3_SYNCPRIM_INSTRS1 (0x00002000) /* */
-#define SCB_ISAR3_SYNCPRIM_INSTRS2 (0x00004000) /* */
-#define SCB_ISAR3_SYNCPRIM_INSTRS3 (0x00008000) /* */
-#define SCB_ISAR3_SYNCPRIM_INSTRS_0 (0x00000000) /* no synchronization primitives present */
-#define SCB_ISAR3_SYNCPRIM_INSTRS_1 (0x00001000) /* adds LDREX, STREX */
-#define SCB_ISAR3_SYNCPRIM_INSTRS_2 (0x00002000) /* adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */
-/* SCB_ISAR3[SCB_ISAR3_TABBRANCH_INSTRS] Bits */
-#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /* TABBRANCH_INSTRS Offset */
-#define SCB_ISAR3_TABBRANCH_INSTRS_M (0x000f0000) /* */
-#define SCB_ISAR3_TABBRANCH_INSTRS0 (0x00010000) /* */
-#define SCB_ISAR3_TABBRANCH_INSTRS1 (0x00020000) /* */
-#define SCB_ISAR3_TABBRANCH_INSTRS2 (0x00040000) /* */
-#define SCB_ISAR3_TABBRANCH_INSTRS3 (0x00080000) /* */
-#define SCB_ISAR3_TABBRANCH_INSTRS_0 (0x00000000) /* no table-branch instructions present */
-#define SCB_ISAR3_TABBRANCH_INSTRS_1 (0x00010000) /* adds TBB, TBH */
-/* SCB_ISAR3[SCB_ISAR3_THUMBCOPY_INSTRS] Bits */
-#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /* THUMBCOPY_INSTRS Offset */
-#define SCB_ISAR3_THUMBCOPY_INSTRS_M (0x00f00000) /* */
-#define SCB_ISAR3_THUMBCOPY_INSTRS0 (0x00100000) /* */
-#define SCB_ISAR3_THUMBCOPY_INSTRS1 (0x00200000) /* */
-#define SCB_ISAR3_THUMBCOPY_INSTRS2 (0x00400000) /* */
-#define SCB_ISAR3_THUMBCOPY_INSTRS3 (0x00800000) /* */
-#define SCB_ISAR3_THUMBCOPY_INSTRS_0 (0x00000000) /* Thumb MOV(register) instruction does not allow low reg -> low reg */
-#define SCB_ISAR3_THUMBCOPY_INSTRS_1 (0x00100000) /* adds Thumb MOV(register) low reg -> low reg and the CPY alias */
-/* SCB_ISAR3[SCB_ISAR3_TRUENOP_INSTRS] Bits */
-#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /* TRUENOP_INSTRS Offset */
-#define SCB_ISAR3_TRUENOP_INSTRS_M (0x0f000000) /* */
-#define SCB_ISAR3_TRUENOP_INSTRS0 (0x01000000) /* */
-#define SCB_ISAR3_TRUENOP_INSTRS1 (0x02000000) /* */
-#define SCB_ISAR3_TRUENOP_INSTRS2 (0x04000000) /* */
-#define SCB_ISAR3_TRUENOP_INSTRS3 (0x08000000) /* */
-#define SCB_ISAR3_TRUENOP_INSTRS_0 (0x00000000) /* true NOP instructions not present - that is, NOP instructions with no register dependencies */
-#define SCB_ISAR3_TRUENOP_INSTRS_1 (0x01000000) /* adds "true NOP", and the capability of additional "NOP compatible hints" */
-/* SCB_ISAR4[SCB_ISAR4_UNPRIV_INSTRS] Bits */
-#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /* UNPRIV_INSTRS Offset */
-#define SCB_ISAR4_UNPRIV_INSTRS_M (0x0000000f) /* */
-#define SCB_ISAR4_UNPRIV_INSTRS0 (0x00000001) /* */
-#define SCB_ISAR4_UNPRIV_INSTRS1 (0x00000002) /* */
-#define SCB_ISAR4_UNPRIV_INSTRS2 (0x00000004) /* */
-#define SCB_ISAR4_UNPRIV_INSTRS3 (0x00000008) /* */
-#define SCB_ISAR4_UNPRIV_INSTRS_0 (0x00000000) /* no "T variant" instructions exist */
-#define SCB_ISAR4_UNPRIV_INSTRS_1 (0x00000001) /* adds LDRBT, LDRT, STRBT, STRT */
-#define SCB_ISAR4_UNPRIV_INSTRS_2 (0x00000002) /* adds LDRHT, LDRSBT, LDRSHT, STRHT */
-/* SCB_ISAR4[SCB_ISAR4_WITHSHIFTS_INSTRS] Bits */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /* WITHSHIFTS_INSTRS Offset */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_M (0x000000f0) /* */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS0 (0x00000010) /* */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS1 (0x00000020) /* */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS2 (0x00000040) /* */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS3 (0x00000080) /* */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 (0x00000000) /* non-zero shifts only support MOV and shift instructions (see notes) */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 (0x00000010) /* shifts of loads/stores over the range LSL 0-3 */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 (0x00000030) /* adds other constant shift options. */
-#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 (0x00000040) /* adds register-controlled shift options. */
-/* SCB_ISAR4[SCB_ISAR4_WRITEBACK_INSTRS] Bits */
-#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /* WRITEBACK_INSTRS Offset */
-#define SCB_ISAR4_WRITEBACK_INSTRS_M (0x00000f00) /* */
-#define SCB_ISAR4_WRITEBACK_INSTRS0 (0x00000100) /* */
-#define SCB_ISAR4_WRITEBACK_INSTRS1 (0x00000200) /* */
-#define SCB_ISAR4_WRITEBACK_INSTRS2 (0x00000400) /* */
-#define SCB_ISAR4_WRITEBACK_INSTRS3 (0x00000800) /* */
-#define SCB_ISAR4_WRITEBACK_INSTRS_0 (0x00000000) /* only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */
-#define SCB_ISAR4_WRITEBACK_INSTRS_1 (0x00000100) /* adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */
-/* SCB_ISAR4[SCB_ISAR4_BARRIER_INSTRS] Bits */
-#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /* BARRIER_INSTRS Offset */
-#define SCB_ISAR4_BARRIER_INSTRS_M (0x000f0000) /* */
-#define SCB_ISAR4_BARRIER_INSTRS0 (0x00010000) /* */
-#define SCB_ISAR4_BARRIER_INSTRS1 (0x00020000) /* */
-#define SCB_ISAR4_BARRIER_INSTRS2 (0x00040000) /* */
-#define SCB_ISAR4_BARRIER_INSTRS3 (0x00080000) /* */
-#define SCB_ISAR4_BARRIER_INSTRS_0 (0x00000000) /* no barrier instructions supported */
-#define SCB_ISAR4_BARRIER_INSTRS_1 (0x00010000) /* adds DMB, DSB, ISB barrier instructions */
-/* SCB_ISAR4[SCB_ISAR4_SYNCPRIM_INSTRS_FRAC] Bits */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /* SYNCPRIM_INSTRS_FRAC Offset */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_M (0x00f00000) /* */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 (0x00100000) /* */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 (0x00200000) /* */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 (0x00400000) /* */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 (0x00800000) /* */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 (0x00000000) /* no additional support */
-#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 (0x00300000) /* adds CLREX, LDREXB, STREXB, LDREXH, STREXH */
-/* SCB_ISAR4[SCB_ISAR4_PSR_M_INSTRS] Bits */
-#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /* PSR_M_INSTRS Offset */
-#define SCB_ISAR4_PSR_M_INSTRS_M (0x0f000000) /* */
-#define SCB_ISAR4_PSR_M_INSTRS0 (0x01000000) /* */
-#define SCB_ISAR4_PSR_M_INSTRS1 (0x02000000) /* */
-#define SCB_ISAR4_PSR_M_INSTRS2 (0x04000000) /* */
-#define SCB_ISAR4_PSR_M_INSTRS3 (0x08000000) /* */
-#define SCB_ISAR4_PSR_M_INSTRS_0 (0x00000000) /* instructions not present */
-#define SCB_ISAR4_PSR_M_INSTRS_1 (0x01000000) /* adds CPS, MRS, and MSR instructions (M-profile forms) */
-/* SCB_CPACR[SCB_CPACR_CP11] Bits */
-#define SCB_CPACR_CP11_OFS (22) /* CP11 Offset */
-#define SCB_CPACR_CP11_M (0x00c00000) /* */
-/* SCB_CPACR[SCB_CPACR_CP10] Bits */
-#define SCB_CPACR_CP10_OFS (20) /* CP10 Offset */
-#define SCB_CPACR_CP10_M (0x00300000) /* */
+/******************************************************************************
+* SCB Bits
+******************************************************************************/
+/* SCB_PFR0[STATE0] Bits */
+#define SCB_PFR0_STATE0_OFS ( 0) /**< STATE0 Bit Offset */
+#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /**< STATE0 Bit Mask */
+#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /**< STATE0 Bit 0 */
+#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /**< STATE0 Bit 1 */
+#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /**< STATE0 Bit 2 */
+#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /**< STATE0 Bit 3 */
+#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /**< no ARM encoding */
+#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /**< N/A */
+/* SCB_PFR0[STATE1] Bits */
+#define SCB_PFR0_STATE1_OFS ( 4) /**< STATE1 Bit Offset */
+#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /**< STATE1 Bit Mask */
+#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /**< STATE1 Bit 0 */
+#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /**< STATE1 Bit 1 */
+#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /**< STATE1 Bit 2 */
+#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /**< STATE1 Bit 3 */
+#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /**< N/A */
+#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /**< N/A */
+#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /**< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but */
+ /* no other 32-bit basic instructions (Note non-basic 32-bit instructions can be */
+ /* added using the appropriate instruction attribute, but other 32-bit basic */
+ /* instructions cannot.) */
+#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /**< Thumb-2 encoding with all Thumb-2 basic instructions */
+/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /**< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /**< not supported */
+#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /**< two-stack support */
+/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /**< MICROCONTROLLER_DEBUG_MODEL Bit Offset */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /**< MICROCONTROLLER_DEBUG_MODEL Bit Mask */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 0 */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 1 */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 2 */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /**< MICROCONTROLLER_DEBUG_MODEL Bit 3 */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /**< not supported */
+#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /**< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */
+/* SCB_MMFR0[PMSA_SUPPORT] Bits */
+#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /**< PMSA_SUPPORT Bit Offset */
+#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /**< PMSA_SUPPORT Bit Mask */
+#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /**< PMSA_SUPPORT Bit 0 */
+#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /**< PMSA_SUPPORT Bit 1 */
+#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /**< PMSA_SUPPORT Bit 2 */
+#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /**< PMSA_SUPPORT Bit 3 */
+#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /**< not supported */
+#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /**< IMPLEMENTATION DEFINED (N/A) */
+#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /**< PMSA base (features as defined for ARMv6) (N/A) */
+#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /**< PMSAv7 (base plus subregion support) */
+/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /**< CACHE_COHERENCE_SUPPORT Bit Offset */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /**< CACHE_COHERENCE_SUPPORT Bit Mask */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /**< CACHE_COHERENCE_SUPPORT Bit 0 */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /**< CACHE_COHERENCE_SUPPORT Bit 1 */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /**< CACHE_COHERENCE_SUPPORT Bit 2 */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /**< CACHE_COHERENCE_SUPPORT Bit 3 */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /**< no shared support */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /**< partial-inner-shared coherency (coherency amongst some - but not all - of the */
+ /* entities within an inner-coherent domain) */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /**< full-inner-shared coherency (coherency amongst all of the entities within an */
+ /* inner-coherent domain) */
+#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /**< full coherency (coherency amongst all of the entities) */
+/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /**< OUTER_NON_SHARABLE_SUPPORT Bit Offset */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /**< OUTER_NON_SHARABLE_SUPPORT Bit Mask */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 0 */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 1 */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 2 */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /**< OUTER_NON_SHARABLE_SUPPORT Bit 3 */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /**< Outer non-sharable not supported */
+#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /**< Outer sharable supported */
+/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /**< AUXILIARY_REGISTER_SUPPORT Bit Offset */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /**< AUXILIARY_REGISTER_SUPPORT Bit Mask */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /**< AUILIARY_REGISTER_SUPPORT Bit 0 */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /**< AUILIARY_REGISTER_SUPPORT Bit 1 */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /**< AUILIARY_REGISTER_SUPPORT Bit 2 */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /**< AUILIARY_REGISTER_SUPPORT Bit 3 */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /**< not supported */
+#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /**< Auxiliary control register */
+/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /**< WAIT_FOR_INTERRUPT_STALLING Bit Offset */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit Mask */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 0 */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 1 */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 2 */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /**< WAIT_FOR_INTERRUPT_STALLING Bit 3 */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /**< not supported */
+#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /**< wait for interrupt supported */
+/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */
+#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /**< BITCOUNT_INSTRS Bit Offset */
+#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /**< BITCOUNT_INSTRS Bit Mask */
+#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /**< BITCOUNT_INSTRS Bit 0 */
+#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /**< BITCOUNT_INSTRS Bit 1 */
+#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /**< BITCOUNT_INSTRS Bit 2 */
+#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /**< BITCOUNT_INSTRS Bit 3 */
+#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /**< no bit-counting instructions present */
+#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /**< adds CLZ */
+/* SCB_ISAR0[BITFIELD_INSTRS] Bits */
+#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /**< BITFIELD_INSTRS Bit Offset */
+#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /**< BITFIELD_INSTRS Bit Mask */
+#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /**< BITFIELD_INSTRS Bit 0 */
+#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /**< BITFIELD_INSTRS Bit 1 */
+#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /**< BITFIELD_INSTRS Bit 2 */
+#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /**< BITFIELD_INSTRS Bit 3 */
+#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /**< no bitfield instructions present */
+#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /**< adds BFC, BFI, SBFX, UBFX */
+/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /**< CMPBRANCH_INSTRS Bit Offset */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /**< CMPBRANCH_INSTRS Bit Mask */
+#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /**< CMPBRANCH_INSTRS Bit 0 */
+#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /**< CMPBRANCH_INSTRS Bit 1 */
+#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /**< CMPBRANCH_INSTRS Bit 2 */
+#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /**< CMPBRANCH_INSTRS Bit 3 */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /**< no combined compare-and-branch instructions present */
+#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /**< adds CB{N}Z */
+/* SCB_ISAR0[COPROC_INSTRS] Bits */
+#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /**< COPROC_INSTRS Bit Offset */
+#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /**< COPROC_INSTRS Bit Mask */
+#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /**< COPROC_INSTRS Bit 0 */
+#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /**< COPROC_INSTRS Bit 1 */
+#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /**< COPROC_INSTRS Bit 2 */
+#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /**< COPROC_INSTRS Bit 3 */
+#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /**< no coprocessor support, other than for separately attributed architectures */
+ /* such as CP15 or VFP */
+#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /**< adds generic CDP, LDC, MCR, MRC, STC */
+#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /**< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */
+#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /**< adds generic MCRR, MRRC */
+#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /**< adds generic MCRR2, MRRC2 */
+/* SCB_ISAR0[DEBUG_INSTRS] Bits */
+#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /**< DEBUG_INSTRS Bit Offset */
+#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /**< DEBUG_INSTRS Bit Mask */
+#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /**< DEBUG_INSTRS Bit 0 */
+#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /**< DEBUG_INSTRS Bit 1 */
+#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /**< DEBUG_INSTRS Bit 2 */
+#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /**< DEBUG_INSTRS Bit 3 */
+#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /**< no debug instructions present */
+#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /**< adds BKPT */
+/* SCB_ISAR0[DIVIDE_INSTRS] Bits */
+#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /**< DIVIDE_INSTRS Bit Offset */
+#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /**< DIVIDE_INSTRS Bit Mask */
+#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /**< DIVIDE_INSTRS Bit 0 */
+#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /**< DIVIDE_INSTRS Bit 1 */
+#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /**< DIVIDE_INSTRS Bit 2 */
+#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /**< DIVIDE_INSTRS Bit 3 */
+#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /**< no divide instructions present */
+#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /**< adds SDIV, UDIV (v1 quotient only result) */
+/* SCB_ISAR1[ETEND_INSRS] Bits */
+#define SCB_ISAR1_ETEND_INSRS_OFS (12) /**< EXTEND_INSRS Bit Offset */
+#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /**< EXTEND_INSRS Bit Mask */
+#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /**< ETEND_INSRS Bit 0 */
+#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /**< ETEND_INSRS Bit 1 */
+#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /**< ETEND_INSRS Bit 2 */
+#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /**< ETEND_INSRS Bit 3 */
+#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /**< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */
+#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /**< adds SXTB, SXTH, UXTB, UXTH */
+#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /**< N/A */
+/* SCB_ISAR1[IFTHEN_INSTRS] Bits */
+#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /**< IFTHEN_INSTRS Bit Offset */
+#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /**< IFTHEN_INSTRS Bit Mask */
+#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /**< IFTHEN_INSTRS Bit 0 */
+#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /**< IFTHEN_INSTRS Bit 1 */
+#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /**< IFTHEN_INSTRS Bit 2 */
+#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /**< IFTHEN_INSTRS Bit 3 */
+#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /**< IT instructions not present */
+#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /**< adds IT instructions (and IT bits in PSRs) */
+/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /**< IMMEDIATE_INSTRS Bit Offset */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /**< IMMEDIATE_INSTRS Bit Mask */
+#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /**< IMMEDIATE_INSTRS Bit 0 */
+#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /**< IMMEDIATE_INSTRS Bit 1 */
+#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /**< IMMEDIATE_INSTRS Bit 2 */
+#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /**< IMMEDIATE_INSTRS Bit 3 */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /**< no special immediate-generating instructions present */
+#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /**< adds ADDW, MOVW, MOVT, SUBW */
+/* SCB_ISAR1[INTERWORK_INSTRS] Bits */
+#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /**< INTERWORK_INSTRS Bit Offset */
+#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /**< INTERWORK_INSTRS Bit Mask */
+#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /**< INTERWORK_INSTRS Bit 0 */
+#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /**< INTERWORK_INSTRS Bit 1 */
+#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /**< INTERWORK_INSTRS Bit 2 */
+#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /**< INTERWORK_INSTRS Bit 3 */
+#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /**< no interworking instructions supported */
+#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /**< adds BX (and T bit in PSRs) */
+#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /**< adds BLX, and PC loads have BX-like behavior */
+#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /**< N/A */
+/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */
+#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /**< LOADSTORE_INSTRS Bit Offset */
+#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /**< LOADSTORE_INSTRS Bit Mask */
+#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /**< LOADSTORE_INSTRS Bit 0 */
+#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /**< LOADSTORE_INSTRS Bit 1 */
+#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /**< LOADSTORE_INSTRS Bit 2 */
+#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /**< LOADSTORE_INSTRS Bit 3 */
+#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /**< no additional normal load/store instructions present */
+#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /**< adds LDRD/STRD */
+/* SCB_ISAR2[MEMHINT_INSTRS] Bits */
+#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /**< MEMHINT_INSTRS Bit Offset */
+#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /**< MEMHINT_INSTRS Bit Mask */
+#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /**< MEMHINT_INSTRS Bit 0 */
+#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /**< MEMHINT_INSTRS Bit 1 */
+#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /**< MEMHINT_INSTRS Bit 2 */
+#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /**< MEMHINT_INSTRS Bit 3 */
+#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /**< no memory hint instructions presen */
+#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /**< adds PLD */
+#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /**< adds PLD (ie a repeat on value 1) */
+#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /**< adds PLI */
+/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /**< MULTIACCESSINT_INSTRS Bit Offset */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /**< MULTIACCESSINT_INSTRS Bit Mask */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /**< MULTIACCESSINT_INSTRS Bit 0 */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /**< MULTIACCESSINT_INSTRS Bit 1 */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /**< MULTIACCESSINT_INSTRS Bit 2 */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /**< MULTIACCESSINT_INSTRS Bit 3 */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /**< the (LDM/STM) instructions are non-interruptible */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /**< the (LDM/STM) instructions are restartable */
+#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /**< the (LDM/STM) instructions are continuable */
+/* SCB_ISAR2[MULT_INSTRS] Bits */
+#define SCB_ISAR2_MULT_INSTRS_OFS (12) /**< MULT_INSTRS Bit Offset */
+#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /**< MULT_INSTRS Bit Mask */
+#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /**< MULT_INSTRS Bit 0 */
+#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /**< MULT_INSTRS Bit 1 */
+#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /**< MULT_INSTRS Bit 2 */
+#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /**< MULT_INSTRS Bit 3 */
+#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /**< only MUL present */
+#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /**< adds MLA */
+#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /**< adds MLS */
+/* SCB_ISAR2[MULTS_INSTRS] Bits */
+#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /**< MULTS_INSTRS Bit Offset */
+#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /**< MULTS_INSTRS Bit Mask */
+#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /**< MULTS_INSTRS Bit 0 */
+#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /**< MULTS_INSTRS Bit 1 */
+#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /**< MULTS_INSTRS Bit 2 */
+#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /**< MULTS_INSTRS Bit 3 */
+#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /**< no signed multiply instructions present */
+#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /**< adds SMULL, SMLAL */
+#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /**< N/A */
+#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /**< N/A */
+/* SCB_ISAR2[MULTU_INSTRS] Bits */
+#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /**< MULTU_INSTRS Bit Offset */
+#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /**< MULTU_INSTRS Bit Mask */
+#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /**< MULTU_INSTRS Bit 0 */
+#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /**< MULTU_INSTRS Bit 1 */
+#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /**< MULTU_INSTRS Bit 2 */
+#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /**< MULTU_INSTRS Bit 3 */
+#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /**< no unsigned multiply instructions present */
+#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /**< adds UMULL, UMLAL */
+#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /**< N/A */
+/* SCB_ISAR2[REVERSAL_INSTRS] Bits */
+#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /**< REVERSAL_INSTRS Bit Offset */
+#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /**< REVERSAL_INSTRS Bit Mask */
+#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /**< REVERSAL_INSTRS Bit 0 */
+#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /**< REVERSAL_INSTRS Bit 1 */
+#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /**< REVERSAL_INSTRS Bit 2 */
+#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /**< REVERSAL_INSTRS Bit 3 */
+#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /**< no reversal instructions present */
+#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /**< adds REV, REV16, REVSH */
+#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /**< adds RBIT */
+/* SCB_ISAR3[SATRUATE_INSTRS] Bits */
+#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /**< SATRUATE_INSTRS Bit Offset */
+#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /**< SATRUATE_INSTRS Bit Mask */
+#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /**< SATRUATE_INSTRS Bit 0 */
+#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /**< SATRUATE_INSTRS Bit 1 */
+#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /**< SATRUATE_INSTRS Bit 2 */
+#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /**< SATRUATE_INSTRS Bit 3 */
+#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /**< no non-SIMD saturate instructions present */
+#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /**< N/A */
+/* SCB_ISAR3[SIMD_INSTRS] Bits */
+#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /**< SIMD_INSTRS Bit Offset */
+#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /**< SIMD_INSTRS Bit Mask */
+#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /**< SIMD_INSTRS Bit 0 */
+#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /**< SIMD_INSTRS Bit 1 */
+#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /**< SIMD_INSTRS Bit 2 */
+#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /**< SIMD_INSTRS Bit 3 */
+#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /**< no SIMD instructions present */
+#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /**< adds SSAT, USAT (and the Q flag in the PSRs) */
+#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /**< N/A */
+/* SCB_ISAR3[SVC_INSTRS] Bits */
+#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /**< SVC_INSTRS Bit Offset */
+#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /**< SVC_INSTRS Bit Mask */
+#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /**< SVC_INSTRS Bit 0 */
+#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /**< SVC_INSTRS Bit 1 */
+#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /**< SVC_INSTRS Bit 2 */
+#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /**< SVC_INSTRS Bit 3 */
+#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /**< no SVC (SWI) instructions present */
+#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /**< adds SVC (SWI) */
+/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /**< SYNCPRIM_INSTRS Bit Offset */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /**< SYNCPRIM_INSTRS Bit Mask */
+#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /**< SYNCPRIM_INSTRS Bit 0 */
+#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /**< SYNCPRIM_INSTRS Bit 1 */
+#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /**< SYNCPRIM_INSTRS Bit 2 */
+#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /**< SYNCPRIM_INSTRS Bit 3 */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /**< no synchronization primitives present */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /**< adds LDREX, STREX */
+#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /**< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */
+/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */
+#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /**< TABBRANCH_INSTRS Bit Offset */
+#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /**< TABBRANCH_INSTRS Bit Mask */
+#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /**< TABBRANCH_INSTRS Bit 0 */
+#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /**< TABBRANCH_INSTRS Bit 1 */
+#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /**< TABBRANCH_INSTRS Bit 2 */
+#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /**< TABBRANCH_INSTRS Bit 3 */
+#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /**< no table-branch instructions present */
+#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /**< adds TBB, TBH */
+/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /**< THUMBCOPY_INSTRS Bit Offset */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /**< THUMBCOPY_INSTRS Bit Mask */
+#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /**< THUMBCOPY_INSTRS Bit 0 */
+#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /**< THUMBCOPY_INSTRS Bit 1 */
+#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /**< THUMBCOPY_INSTRS Bit 2 */
+#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /**< THUMBCOPY_INSTRS Bit 3 */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /**< Thumb MOV(register) instruction does not allow low reg -> low reg */
+#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /**< adds Thumb MOV(register) low reg -> low reg and the CPY alias */
+/* SCB_ISAR3[TRUENOP_INSTRS] Bits */
+#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /**< TRUENOP_INSTRS Bit Offset */
+#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /**< TRUENOP_INSTRS Bit Mask */
+#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /**< TRUENOP_INSTRS Bit 0 */
+#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /**< TRUENOP_INSTRS Bit 1 */
+#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /**< TRUENOP_INSTRS Bit 2 */
+#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /**< TRUENOP_INSTRS Bit 3 */
+#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /**< true NOP instructions not present - that is, NOP instructions with no register */
+ /* dependencies */
+#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /**< adds "true NOP", and the capability of additional "NOP compatible hints" */
+/* SCB_ISAR4[UNPRIV_INSTRS] Bits */
+#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /**< UNPRIV_INSTRS Bit Offset */
+#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /**< UNPRIV_INSTRS Bit Mask */
+#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /**< UNPRIV_INSTRS Bit 0 */
+#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /**< UNPRIV_INSTRS Bit 1 */
+#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /**< UNPRIV_INSTRS Bit 2 */
+#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /**< UNPRIV_INSTRS Bit 3 */
+#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /**< no "T variant" instructions exist */
+#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /**< adds LDRBT, LDRT, STRBT, STRT */
+#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /**< adds LDRHT, LDRSBT, LDRSHT, STRHT */
+/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /**< WITHSHIFTS_INSTRS Bit Offset */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /**< WITHSHIFTS_INSTRS Bit Mask */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /**< WITHSHIFTS_INSTRS Bit 0 */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /**< WITHSHIFTS_INSTRS Bit 1 */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /**< WITHSHIFTS_INSTRS Bit 2 */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /**< WITHSHIFTS_INSTRS Bit 3 */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /**< non-zero shifts only support MOV and shift instructions (see notes) */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /**< shifts of loads/stores over the range LSL 0-3 */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /**< adds other constant shift options. */
+#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /**< adds register-controlled shift options. */
+/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */
+#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /**< WRITEBACK_INSTRS Bit Offset */
+#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /**< WRITEBACK_INSTRS Bit Mask */
+#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /**< WRITEBACK_INSTRS Bit 0 */
+#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /**< WRITEBACK_INSTRS Bit 1 */
+#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /**< WRITEBACK_INSTRS Bit 2 */
+#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /**< WRITEBACK_INSTRS Bit 3 */
+#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /**< only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP */
+ /* instructions support writeback addressing. */
+#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /**< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */
+/* SCB_ISAR4[BARRIER_INSTRS] Bits */
+#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /**< BARRIER_INSTRS Bit Offset */
+#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /**< BARRIER_INSTRS Bit Mask */
+#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /**< BARRIER_INSTRS Bit 0 */
+#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /**< BARRIER_INSTRS Bit 1 */
+#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /**< BARRIER_INSTRS Bit 2 */
+#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /**< BARRIER_INSTRS Bit 3 */
+#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /**< no barrier instructions supported */
+#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /**< adds DMB, DSB, ISB barrier instructions */
+/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /**< SYNCPRIM_INSTRS_FRAC Bit Offset */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /**< SYNCPRIM_INSTRS_FRAC Bit Mask */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /**< SYNCPRIM_INSTRS_FRAC Bit 0 */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /**< SYNCPRIM_INSTRS_FRAC Bit 1 */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /**< SYNCPRIM_INSTRS_FRAC Bit 2 */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /**< SYNCPRIM_INSTRS_FRAC Bit 3 */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /**< no additional support */
+#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /**< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */
+/* SCB_ISAR4[PSR_M_INSTRS] Bits */
+#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /**< PSR_M_INSTRS Bit Offset */
+#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /**< PSR_M_INSTRS Bit Mask */
+#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /**< PSR_M_INSTRS Bit 0 */
+#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /**< PSR_M_INSTRS Bit 1 */
+#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /**< PSR_M_INSTRS Bit 2 */
+#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /**< PSR_M_INSTRS Bit 3 */
+#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /**< instructions not present */
+#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /**< adds CPS, MRS, and MSR instructions (M-profile forms) */
+/* SCB_CPACR[CP11] Bits */
+#define SCB_CPACR_CP11_OFS (22) /**< CP11 Bit Offset */
+#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /**< CP11 Bit Mask */
+/* SCB_CPACR[CP10] Bits */
+#define SCB_CPACR_CP10_OFS (20) /**< CP10 Bit Offset */
+#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /**< CP10 Bit Mask */
-//*****************************************************************************
-// SCnSCB Bits
-//*****************************************************************************
-/* SCSCB_ICTR[SCNSCB_ICTR_INTLINESNUM] Bits */
-#define SCNSCB_ICTR_INTLINESNUM_OFS ( 0) /* INTLINESNUM Offset */
-#define SCNSCB_ICTR_INTLINESNUM_M (0x0000001f) /* */
-/* SCSCB_ACTLR[SCNSCB_ACTLR_DISMCYCINT] Bits */
-#define SCNSCB_ACTLR_DISMCYCINT_OFS ( 0) /* DISMCYCINT Offset */
-#define SCNSCB_ACTLR_DISMCYCINT (0x00000001) /* */
-/* SCSCB_ACTLR[SCNSCB_ACTLR_DISDEFWBUF] Bits */
-#define SCNSCB_ACTLR_DISDEFWBUF_OFS ( 1) /* DISDEFWBUF Offset */
-#define SCNSCB_ACTLR_DISDEFWBUF (0x00000002) /* */
-/* SCSCB_ACTLR[SCNSCB_ACTLR_DISFOLD] Bits */
-#define SCNSCB_ACTLR_DISFOLD_OFS ( 2) /* DISFOLD Offset */
-#define SCNSCB_ACTLR_DISFOLD (0x00000004) /* */
+/******************************************************************************
+* SCnSCB Bits
+******************************************************************************/
-//*****************************************************************************
-// SYSCTL Bits
-//*****************************************************************************
-/* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_REBOOT] Bits */
-#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /* REBOOT Offset */
-#define SYSCTL_REBOOT_CTL_REBOOT (0x00000001) /* Write 1 initiates a Reboot of the device */
-/* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_WKEY] Bits */
-#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /* WKEY Offset */
-#define SYSCTL_REBOOT_CTL_WKEY_M (0x0000ff00) /* Key to enable writes to bit 0 */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_SRC] Bits */
-#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /* CS_SRC Offset */
-#define SYSCTL_NMI_CTLSTAT_CS_SRC (0x00000001) /* CS interrupt as a source of NMI */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_SRC] Bits */
-#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /* PSS_SRC Offset */
-#define SYSCTL_NMI_CTLSTAT_PSS_SRC (0x00000002) /* PSS interrupt as a source of NMI */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_SRC] Bits */
-#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /* PCM_SRC Offset */
-#define SYSCTL_NMI_CTLSTAT_PCM_SRC (0x00000004) /* PCM interrupt as a source of NMI */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_SRC] Bits */
-#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /* PIN_SRC Offset */
-#define SYSCTL_NMI_CTLSTAT_PIN_SRC (0x00000008) /* */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_FLG] Bits */
-#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /* CS_FLG Offset */
-#define SYSCTL_NMI_CTLSTAT_CS_FLG (0x00010000) /* CS interrupt was the source of NMI */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_FLG] Bits */
-#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /* PSS_FLG Offset */
-#define SYSCTL_NMI_CTLSTAT_PSS_FLG (0x00020000) /* PSS interrupt was the source of NMI */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_FLG] Bits */
-#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /* PCM_FLG Offset */
-#define SYSCTL_NMI_CTLSTAT_PCM_FLG (0x00040000) /* PCM interrupt was the source of NMI */
-/* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_FLG] Bits */
-#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /* PIN_FLG Offset */
-#define SYSCTL_NMI_CTLSTAT_PIN_FLG (0x00080000) /* RSTn/NMI pin was the source of NMI */
-/* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_TIMEOUT] Bits */
-#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /* TIMEOUT Offset */
-#define SYSCTL_WDTRESET_CTL_TIMEOUT (0x00000001) /* WDT timeout reset type */
-/* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_VIOLATION] Bits */
-#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /* VIOLATION Offset */
-#define SYSCTL_WDTRESET_CTL_VIOLATION (0x00000002) /* WDT password violation reset type */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_0] Bits */
-#define SYSCTL_PERIHALT_CTL_T16_0_OFS ( 0) /* T16_0 Offset */
-#define SYSCTL_PERIHALT_CTL_T16_0 (0x00000001) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_1] Bits */
-#define SYSCTL_PERIHALT_CTL_T16_1_OFS ( 1) /* T16_1 Offset */
-#define SYSCTL_PERIHALT_CTL_T16_1 (0x00000002) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_2] Bits */
-#define SYSCTL_PERIHALT_CTL_T16_2_OFS ( 2) /* T16_2 Offset */
-#define SYSCTL_PERIHALT_CTL_T16_2 (0x00000004) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_3] Bits */
-#define SYSCTL_PERIHALT_CTL_T16_3_OFS ( 3) /* T16_3 Offset */
-#define SYSCTL_PERIHALT_CTL_T16_3 (0x00000008) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T32_0] Bits */
-#define SYSCTL_PERIHALT_CTL_T32_0_OFS ( 4) /* T32_0 Offset */
-#define SYSCTL_PERIHALT_CTL_T32_0 (0x00000010) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA0] Bits */
-#define SYSCTL_PERIHALT_CTL_EUA0_OFS ( 5) /* eUA0 Offset */
-#define SYSCTL_PERIHALT_CTL_EUA0 (0x00000020) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA1] Bits */
-#define SYSCTL_PERIHALT_CTL_EUA1_OFS ( 6) /* eUA1 Offset */
-#define SYSCTL_PERIHALT_CTL_EUA1 (0x00000040) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA2] Bits */
-#define SYSCTL_PERIHALT_CTL_EUA2_OFS ( 7) /* eUA2 Offset */
-#define SYSCTL_PERIHALT_CTL_EUA2 (0x00000080) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA3] Bits */
-#define SYSCTL_PERIHALT_CTL_EUA3_OFS ( 8) /* eUA3 Offset */
-#define SYSCTL_PERIHALT_CTL_EUA3 (0x00000100) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB0] Bits */
-#define SYSCTL_PERIHALT_CTL_EUB0_OFS ( 9) /* eUB0 Offset */
-#define SYSCTL_PERIHALT_CTL_EUB0 (0x00000200) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB1] Bits */
-#define SYSCTL_PERIHALT_CTL_EUB1_OFS (10) /* eUB1 Offset */
-#define SYSCTL_PERIHALT_CTL_EUB1 (0x00000400) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB2] Bits */
-#define SYSCTL_PERIHALT_CTL_EUB2_OFS (11) /* eUB2 Offset */
-#define SYSCTL_PERIHALT_CTL_EUB2 (0x00000800) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB3] Bits */
-#define SYSCTL_PERIHALT_CTL_EUB3_OFS (12) /* eUB3 Offset */
-#define SYSCTL_PERIHALT_CTL_EUB3 (0x00001000) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_ADC] Bits */
-#define SYSCTL_PERIHALT_CTL_ADC_OFS (13) /* ADC Offset */
-#define SYSCTL_PERIHALT_CTL_ADC (0x00002000) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_WDT] Bits */
-#define SYSCTL_PERIHALT_CTL_WDT_OFS (14) /* WDT Offset */
-#define SYSCTL_PERIHALT_CTL_WDT (0x00004000) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_DMA] Bits */
-#define SYSCTL_PERIHALT_CTL_DMA_OFS (15) /* DMA Offset */
-#define SYSCTL_PERIHALT_CTL_DMA (0x00008000) /* Freezes IP operation when CPU is halted */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK0_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /* BNK0_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK0_EN (0x00000001) /* SRAM Bank0 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK1_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /* BNK1_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK1_EN (0x00000002) /* SRAM Bank1 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK2_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /* BNK2_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK2_EN (0x00000004) /* SRAM Bank1 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK3_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /* BNK3_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK3_EN (0x00000008) /* SRAM Bank1 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK4_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /* BNK4_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK4_EN (0x00000010) /* SRAM Bank1 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK5_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /* BNK5_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK5_EN (0x00000020) /* SRAM Bank1 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK6_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /* BNK6_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK6_EN (0x00000040) /* SRAM Bank1 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK7_EN] Bits */
-#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /* BNK7_EN Offset */
-#define SYSCTL_SRAM_BANKEN_BNK7_EN (0x00000080) /* SRAM Bank1 enable */
-/* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_SRAM_RDY] Bits */
-#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /* SRAM_RDY Offset */
-#define SYSCTL_SRAM_BANKEN_SRAM_RDY (0x00010000) /* SRAM ready */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK0_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /* BNK0_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK0_RET (0x00000001) /* Bank0 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK1_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /* BNK1_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK1_RET (0x00000002) /* Bank1 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK2_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /* BNK2_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK2_RET (0x00000004) /* Bank2 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK3_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /* BNK3_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK3_RET (0x00000008) /* Bank3 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK4_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /* BNK4_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK4_RET (0x00000010) /* Bank4 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK5_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /* BNK5_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK5_RET (0x00000020) /* Bank5 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK6_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /* BNK6_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK6_RET (0x00000040) /* Bank6 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK7_RET] Bits */
-#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /* BNK7_RET Offset */
-#define SYSCTL_SRAM_BANKRET_BNK7_RET (0x00000080) /* Bank7 retention */
-/* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_SRAM_RDY] Bits */
-#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /* SRAM_RDY Offset */
-#define SYSCTL_SRAM_BANKRET_SRAM_RDY (0x00010000) /* SRAM ready */
-/* SYSCTL_DIO_GLTFLT_CTL[SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN] Bits */
-#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /* GLTCH_EN Offset */
-#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN (0x00000001) /* Glitch filter enable */
-/* SYSCTL_SECDATA_UNLOCK[SYSCTL_SECDATA_UNLOCK_UNLKEY] Bits */
-#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /* UNLKEY Offset */
-#define SYSCTL_SECDATA_UNLOCK_UNLKEY_M (0x0000ffff) /* Unlock key */
-/* SYSCTL_MASTER_UNLOCK[SYSCTL_MASTER_UNLOCK_UNLKEY] Bits */
-#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /* UNLKEY Offset */
-#define SYSCTL_MASTER_UNLOCK_UNLKEY_M (0x0000ffff) /* Unlock Key */
-/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_POR] Bits */
-#define SYSCTL_RESET_REQ_POR_OFS ( 0) /* POR Offset */
-#define SYSCTL_RESET_REQ_POR (0x00000001) /* Generate POR */
-/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_REBOOT] Bits */
-#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /* REBOOT Offset */
-#define SYSCTL_RESET_REQ_REBOOT (0x00000002) /* Generate Reboot_Reset */
-/* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_WKEY] Bits */
-#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /* WKEY Offset */
-#define SYSCTL_RESET_REQ_WKEY_M (0x0000ff00) /* Write key */
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT] Bits */
-#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /* SOFT Offset */
-#define SYSCTL_RESET_STATOVER_SOFT (0x00000001) /* Indicates if SOFT Reset is active */
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD] Bits */
-#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /* HARD Offset */
-#define SYSCTL_RESET_STATOVER_HARD (0x00000002) /* Indicates if HARD Reset is active */
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_REBOOT] Bits */
-#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /* REBOOT Offset */
-#define SYSCTL_RESET_STATOVER_REBOOT (0x00000004) /* Indicates if Reboot Reset is active */
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT_OVER] Bits */
-#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /* SOFT_OVER Offset */
-#define SYSCTL_RESET_STATOVER_SOFT_OVER (0x00000100) /* SOFT_Reset overwrite request */
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD_OVER] Bits */
-#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /* HARD_OVER Offset */
-#define SYSCTL_RESET_STATOVER_HARD_OVER (0x00000200) /* HARD_Reset overwrite request */
-/* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_RBT_OVER] Bits */
-#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /* RBT_OVER Offset */
-#define SYSCTL_RESET_STATOVER_RBT_OVER (0x00000400) /* Reboot Reset overwrite request */
-/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_DBG_SEC_ACT] Bits */
-#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /* DBG_SEC_ACT Offset */
-#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT (0x00000008) /* Debug Security active */
-/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT] Bits */
-#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /* JTAG_SWD_LOCK_ACT Offset */
-#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT (0x00000010) /* Indicates if JTAG and SWD Lock is active */
-/* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_IP_PROT_ACT] Bits */
-#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /* IP_PROT_ACT Offset */
-#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT (0x00000020) /* Indicates if IP protection is active */
+/******************************************************************************
+* SYSCTL Bits
+******************************************************************************/
+/* SYSCTL_REBOOT_CTL[REBOOT] Bits */
+#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /**< REBOOT Bit Offset */
+#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /**< Write 1 initiates a Reboot of the device */
+/* SYSCTL_REBOOT_CTL[WKEY] Bits */
+#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */
+#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
+/* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /**< CS_SRC Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /**< CS interrupt as a source of NMI */
+/* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /**< PSS_SRC Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /**< PSS interrupt as a source of NMI */
+/* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /**< PCM_SRC Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /**< PCM interrupt as a source of NMI */
+/* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */
+#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /**< PIN_SRC Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008)
+/* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /**< CS_FLG Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /**< CS interrupt was the source of NMI */
+/* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /**< PSS_FLG Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /**< PSS interrupt was the source of NMI */
+/* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /**< PCM_FLG Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /**< PCM interrupt was the source of NMI */
+/* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */
+#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /**< PIN_FLG Bit Offset */
+#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /**< RSTn/NMI pin was the source of NMI */
+/* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */
+#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /**< TIMEOUT Bit Offset */
+#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /**< WDT timeout reset type */
+/* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */
+#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /**< VIOLATION Bit Offset */
+#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /**< WDT password violation reset type */
+/* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /**< HALT_T16_0 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /**< HALT_T16_1 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /**< HALT_T16_2 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /**< HALT_T16_3 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /**< HALT_T32_0 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUA0] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /**< HALT_eUA0 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUA1] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /**< HALT_eUA1 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUA2] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /**< HALT_eUA2 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUA3] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /**< HALT_eUA3 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUB0] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /**< HALT_eUB0 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUB1] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /**< HALT_eUB1 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUB2] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /**< HALT_eUB2 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_EUB3] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /**< HALT_eUB3 Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /**< HALT_ADC Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /**< HALT_WDT Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */
+#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /**< HALT_DMA Bit Offset */
+#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /**< Freezes IP operation when CPU is halted */
+/* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /**< BNK0_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /**< SRAM Bank0 enable */
+/* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /**< BNK1_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /**< SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /**< BNK2_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /**< SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /**< BNK3_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /**< SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /**< BNK4_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /**< SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /**< BNK5_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /**< SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /**< BNK6_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /**< SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */
+#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /**< BNK7_EN Bit Offset */
+#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /**< SRAM Bank1 enable */
+/* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */
+#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /**< SRAM_RDY Bit Offset */
+#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /**< SRAM ready */
+/* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /**< BNK0_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /**< Bank0 retention */
+/* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /**< BNK1_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /**< Bank1 retention */
+/* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /**< BNK2_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /**< Bank2 retention */
+/* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /**< BNK3_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /**< Bank3 retention */
+/* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /**< BNK4_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /**< Bank4 retention */
+/* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /**< BNK5_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /**< Bank5 retention */
+/* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /**< BNK6_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /**< Bank6 retention */
+/* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */
+#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /**< BNK7_RET Bit Offset */
+#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /**< Bank7 retention */
+/* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */
+#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /**< SRAM_RDY Bit Offset */
+#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /**< SRAM ready */
+/* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */
+#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /**< GLTCH_EN Bit Offset */
+#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /**< Glitch filter enable */
+/* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */
+#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */
+#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */
+/* SYSCTL_CSYS_MASTER_UNLOCK[UNLKEY] Bits */
+#define SYSCTL_CSYS_MASTER_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */
+#define SYSCTL_CSYS_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */
+/* SYSCTL_BOOT_CTL[BOOT_SECEN] Bits */
+#define SYSCTL_BOOT_CTL_BOOT_SECEN_OFS ( 0) /**< BOOT_SECEN Bit Offset */
+#define SYSCTL_BOOT_CTL_BOOT_SECEN ((uint32_t)0x00000001)
+/* SYSCTL_BOOT_CTL[BOOTACT] Bits */
+#define SYSCTL_BOOT_CTL_BOOTACT_OFS ( 1) /**< BOOTACT Bit Offset */
+#define SYSCTL_BOOT_CTL_BOOTACT ((uint32_t)0x00000002)
+/* SYSCTL_BOOT_CTL[BOOTCMPL] Bits */
+#define SYSCTL_BOOT_CTL_BOOTCMPL_OFS ( 2) /**< BOOTCMPL Bit Offset */
+#define SYSCTL_BOOT_CTL_BOOTCMPL ((uint32_t)0x00000004)
+/* SYSCTL_BOOT_CTL[BOOT_REMAPEN] Bits */
+#define SYSCTL_BOOT_CTL_BOOT_REMAPEN_OFS ( 3) /**< BOOT_REMAPEN Bit Offset */
+#define SYSCTL_BOOT_CTL_BOOT_REMAPEN ((uint32_t)0x00000008)
+/* SYSCTL_BOOT_CTL[ENGR_DIS] Bits */
+#define SYSCTL_BOOT_CTL_ENGR_DIS_OFS ( 4) /**< ENGR_DIS Bit Offset */
+#define SYSCTL_BOOT_CTL_ENGR_DIS ((uint32_t)0x00000010)
+/* SYSCTL_BOOT_CTL[WKEY] Bits */
+#define SYSCTL_BOOT_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */
+#define SYSCTL_BOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
+/* SYSCTL_SEC_CTL[JTAG_SWD_LOCK_EN] Bits */
+#define SYSCTL_SEC_CTL_JTAG_SWD_LOCK_EN_OFS ( 0) /**< JTAG_SWD_LOCK_EN Bit Offset */
+#define SYSCTL_SEC_CTL_JTAG_SWD_LOCK_EN ((uint32_t)0x00000001)
+/* SYSCTL_SEC_CTL[IP_PROT_EN] Bits */
+#define SYSCTL_SEC_CTL_IP_PROT_EN_OFS ( 1) /**< IP_PROT_EN Bit Offset */
+#define SYSCTL_SEC_CTL_IP_PROT_EN ((uint32_t)0x00000002)
+/* SYSCTL_SEC_CTL[DLOCK_EN] Bits */
+#define SYSCTL_SEC_CTL_DLOCK_EN_OFS ( 2) /**< DLOCK_EN Bit Offset */
+#define SYSCTL_SEC_CTL_DLOCK_EN ((uint32_t)0x00000004)
+/* SYSCTL_SEC_CTL[SBUS_IF_DIS] Bits */
+#define SYSCTL_SEC_CTL_SBUS_IF_DIS_OFS ( 3) /**< SBUS_IF_DIS Bit Offset */
+#define SYSCTL_SEC_CTL_SBUS_IF_DIS ((uint32_t)0x00000008)
+/* SYSCTL_SEC_CTL[SEC_ZONE0_EN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE0_EN_OFS ( 8) /**< SEC_ZONE0_EN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE0_EN ((uint32_t)0x00000100)
+/* SYSCTL_SEC_CTL[SEC_ZONE1_EN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE1_EN_OFS ( 9) /**< SEC_ZONE1_EN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE1_EN ((uint32_t)0x00000200)
+/* SYSCTL_SEC_CTL[SEC_ZONE2_EN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE2_EN_OFS (10) /**< SEC_ZONE2_EN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE2_EN ((uint32_t)0x00000400)
+/* SYSCTL_SEC_CTL[SEC_ZONE3_EN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE3_EN_OFS (11) /**< SEC_ZONE3_EN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE3_EN ((uint32_t)0x00000800)
+/* SYSCTL_SEC_CTL[SEC_ZONE0_DATAEN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE0_DATAEN_OFS (16) /**< SEC_ZONE0_DATAEN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE0_DATAEN ((uint32_t)0x00010000)
+/* SYSCTL_SEC_CTL[SEC_ZONE1_DATAEN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE1_DATAEN_OFS (17) /**< SEC_ZONE1_DATAEN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE1_DATAEN ((uint32_t)0x00020000)
+/* SYSCTL_SEC_CTL[SEC_ZONE2_DATAEN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE2_DATAEN_OFS (18) /**< SEC_ZONE2_DATAEN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE2_DATAEN ((uint32_t)0x00040000)
+/* SYSCTL_SEC_CTL[SEC_ZONE3_DATAEN] Bits */
+#define SYSCTL_SEC_CTL_SEC_ZONE3_DATAEN_OFS (19) /**< SEC_ZONE3_DATAEN Bit Offset */
+#define SYSCTL_SEC_CTL_SEC_ZONE3_DATAEN ((uint32_t)0x00080000)
+/* SYSCTL_SEC_STARTADDR0[START_ADDR] Bits */
+#define SYSCTL_SEC_STARTADDR0_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
+#define SYSCTL_SEC_STARTADDR0_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
+/* SYSCTL_SEC_STARTADDR1[START_ADDR] Bits */
+#define SYSCTL_SEC_STARTADDR1_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
+#define SYSCTL_SEC_STARTADDR1_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
+/* SYSCTL_SEC_STARTADDR2[START_ADDR] Bits */
+#define SYSCTL_SEC_STARTADDR2_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
+#define SYSCTL_SEC_STARTADDR2_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
+/* SYSCTL_SEC_STARTADDR3[START_ADDR] Bits */
+#define SYSCTL_SEC_STARTADDR3_START_ADDR_OFS ( 0) /**< START_ADDR Bit Offset */
+#define SYSCTL_SEC_STARTADDR3_START_ADDR_MASK ((uint32_t)0x0003FFFF) /**< START_ADDR Bit Mask */
+/* SYSCTL_SEC_SIZE0[SIZE] Bits */
+#define SYSCTL_SEC_SIZE0_SIZE_OFS ( 0) /**< SIZE Bit Offset */
+#define SYSCTL_SEC_SIZE0_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
+/* SYSCTL_SEC_SIZE1[SIZE] Bits */
+#define SYSCTL_SEC_SIZE1_SIZE_OFS ( 0) /**< SIZE Bit Offset */
+#define SYSCTL_SEC_SIZE1_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
+/* SYSCTL_SEC_SIZE2[SIZE] Bits */
+#define SYSCTL_SEC_SIZE2_SIZE_OFS ( 0) /**< SIZE Bit Offset */
+#define SYSCTL_SEC_SIZE2_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
+/* SYSCTL_SEC_SIZE3[SIZE] Bits */
+#define SYSCTL_SEC_SIZE3_SIZE_OFS ( 0) /**< SIZE Bit Offset */
+#define SYSCTL_SEC_SIZE3_SIZE_MASK ((uint32_t)0x0003FFFF) /**< SIZE Bit Mask */
+/* SYSCTL_ETW_CTL[ETSEL] Bits */
+#define SYSCTL_ETW_CTL_ETSEL_OFS ( 0) /**< ETSEL Bit Offset */
+#define SYSCTL_ETW_CTL_ETSEL ((uint32_t)0x00000001)
+/* SYSCTL_ETW_CTL[DBGEN] Bits */
+#define SYSCTL_ETW_CTL_DBGEN_OFS ( 1) /**< DBGEN Bit Offset */
+#define SYSCTL_ETW_CTL_DBGEN ((uint32_t)0x00000002)
+/* SYSCTL_ETW_CTL[WKEY] Bits */
+#define SYSCTL_ETW_CTL_WKEY_OFS ( 8) /**< WKEY Bit Offset */
+#define SYSCTL_ETW_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
+/* SYSCTL_FLASH_SIZECFG[SIZE] Bits */
+#define SYSCTL_FLASH_SIZECFG_SIZE_OFS ( 0) /**< SIZE Bit Offset */
+#define SYSCTL_FLASH_SIZECFG_SIZE_MASK ((uint32_t)0x0007FFFF) /**< SIZE Bit Mask */
+/* SYSCTL_SRAM_SIZECFG[SIZE] Bits */
+#define SYSCTL_SRAM_SIZECFG_SIZE_OFS ( 0) /**< SIZE Bit Offset */
+#define SYSCTL_SRAM_SIZECFG_SIZE_MASK ((uint32_t)0x0001FFFF) /**< SIZE Bit Mask */
+/* SYSCTL_SRAM_NUMBANK[NUM_BANK] Bits */
+#define SYSCTL_SRAM_NUMBANK_NUM_BANK_OFS ( 0) /**< NUM_BANK Bit Offset */
+#define SYSCTL_SRAM_NUMBANK_NUM_BANK_MASK ((uint32_t)0x0000001F) /**< NUM_BANK Bit Mask */
+/* SYSCTL_TIMER_CFG[T0_EN] Bits */
+#define SYSCTL_TIMER_CFG_T0_EN_OFS ( 0) /**< T0_EN Bit Offset */
+#define SYSCTL_TIMER_CFG_T0_EN ((uint32_t)0x00000001) /**< Enable bit for Timer0 */
+/* SYSCTL_TIMER_CFG[T1_EN] Bits */
+#define SYSCTL_TIMER_CFG_T1_EN_OFS ( 1) /**< T1_EN Bit Offset */
+#define SYSCTL_TIMER_CFG_T1_EN ((uint32_t)0x00000002) /**< Enable bit for Timer1 */
+/* SYSCTL_TIMER_CFG[T2_EN] Bits */
+#define SYSCTL_TIMER_CFG_T2_EN_OFS ( 2) /**< T2_EN Bit Offset */
+#define SYSCTL_TIMER_CFG_T2_EN ((uint32_t)0x00000004) /**< Enable bit for Timer2 */
+/* SYSCTL_TIMER_CFG[T3_EN] Bits */
+#define SYSCTL_TIMER_CFG_T3_EN_OFS ( 3) /**< T3_EN Bit Offset */
+#define SYSCTL_TIMER_CFG_T3_EN ((uint32_t)0x00000008) /**< Enable bit for Timer3 */
+/* SYSCTL_TIMER_CFG[T32_EN] Bits */
+#define SYSCTL_TIMER_CFG_T32_EN_OFS (16) /**< T32_EN Bit Offset */
+#define SYSCTL_TIMER_CFG_T32_EN ((uint32_t)0x00010000) /**< Enable bit for Timer32 */
+/* SYSCTL_EUSCI_CFG[EUA0_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUA0_EN_OFS ( 0) /**< eUA0_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUA0_EN ((uint32_t)0x00000001) /**< Enable bit for eUSCI_A0 */
+/* SYSCTL_EUSCI_CFG[EUA1_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUA1_EN_OFS ( 1) /**< eUA1_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUA1_EN ((uint32_t)0x00000002) /**< Enable bit for eUSCI_A1 */
+/* SYSCTL_EUSCI_CFG[EUA2_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUA2_EN_OFS ( 2) /**< eUA2_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUA2_EN ((uint32_t)0x00000004) /**< Enable bit for eUSCI_A2 */
+/* SYSCTL_EUSCI_CFG[EUA3_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUA3_EN_OFS ( 3) /**< eUA3_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUA3_EN ((uint32_t)0x00000008) /**< Enable bit for eUSCI_A3 */
+/* SYSCTL_EUSCI_CFG[EUB0_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUB0_EN_OFS (16) /**< eUB0_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUB0_EN ((uint32_t)0x00010000) /**< Enable bit for eUSCI_B0 */
+/* SYSCTL_EUSCI_CFG[EUB1_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUB1_EN_OFS (17) /**< eUB1_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUB1_EN ((uint32_t)0x00020000) /**< Enable bit for eUSCI_B1 */
+/* SYSCTL_EUSCI_CFG[EUB2_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUB2_EN_OFS (18) /**< eUB2_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUB2_EN ((uint32_t)0x00040000) /**< Enable bit for eUSCI_B2 */
+/* SYSCTL_EUSCI_CFG[EUB3_EN] Bits */
+#define SYSCTL_EUSCI_CFG_EUB3_EN_OFS (19) /**< eUB3_EN Bit Offset */
+#define SYSCTL_EUSCI_CFG_EUB3_EN ((uint32_t)0x00080000) /**< Enable bit for eUSCI_B3 */
+/* SYSCTL_ADC_CFG[ADC_EN] Bits */
+#define SYSCTL_ADC_CFG_ADC_EN_OFS ( 0) /**< ADC_EN Bit Offset */
+#define SYSCTL_ADC_CFG_ADC_EN ((uint32_t)0x00000001) /**< Enable bit for ADC */
+/* SYSCTL_XTAL_CFG[LFXT_EN] Bits */
+#define SYSCTL_XTAL_CFG_LFXT_EN_OFS ( 0) /**< LFXT_EN Bit Offset */
+#define SYSCTL_XTAL_CFG_LFXT_EN ((uint32_t)0x00000001) /**< Enable bit for LFXT */
+/* SYSCTL_XTAL_CFG[HFXT_EN] Bits */
+#define SYSCTL_XTAL_CFG_HFXT_EN_OFS ( 1) /**< HFXT_EN Bit Offset */
+#define SYSCTL_XTAL_CFG_HFXT_EN ((uint32_t)0x00000002) /**< Enable bit for HFXT */
+/* SYSCTL_XTAL_CFG[HFXT2_EN] Bits */
+#define SYSCTL_XTAL_CFG_HFXT2_EN_OFS ( 2) /**< HFXT2_EN Bit Offset */
+#define SYSCTL_XTAL_CFG_HFXT2_EN ((uint32_t)0x00000004) /**< Enable bit for HFXT2 */
+/* SYSCTL_BOC_CFG[BOC_CTL] Bits */
+#define SYSCTL_BOC_CFG_BOC_CTL_OFS ( 0) /**< BOC_CTL Bit Offset */
+#define SYSCTL_BOC_CFG_BOC_CTL_MASK ((uint32_t)0x00000007) /**< BOC_CTL Bit Mask */
+#define SYSCTL_BOC_CFG_BOC_CTL0 ((uint32_t)0x00000001) /**< BOC_CTL Bit 0 */
+#define SYSCTL_BOC_CFG_BOC_CTL1 ((uint32_t)0x00000002) /**< BOC_CTL Bit 1 */
+#define SYSCTL_BOC_CFG_BOC_CTL2 ((uint32_t)0x00000004) /**< BOC_CTL Bit 2 */
+#define SYSCTL_BOC_CFG_BOC_CTL_0 ((uint32_t)0x00000000) /**< 100pin package */
+#define SYSCTL_BOC_CFG_BOC_CTL_1 ((uint32_t)0x00000001) /**< 80pin package */
+#define SYSCTL_BOC_CFG_BOC_CTL_2 ((uint32_t)0x00000002) /**< 64pin package */
+#define SYSCTL_BOC_CFG_BOC_CTL_3 ((uint32_t)0x00000003) /**< 64pin package */
+#define SYSCTL_BOC_CFG_BOC_CTL__PIN_100 ((uint32_t)0x00000000) /**< 100pin package */
+#define SYSCTL_BOC_CFG_BOC_CTL__PIN_80 ((uint32_t)0x00000001) /**< 80pin package */
+#define SYSCTL_BOC_CFG_BOC_CTL__PIN_64 ((uint32_t)0x00000002) /**< 64pin package */
+
+#define SYSCTL_BOC_CFG_BOC_CTL_4 ((uint32_t)0x00000004) /**< Reserved for future use */
+#define SYSCTL_BOC_CFG_BOC_CTL_5 ((uint32_t)0x00000005) /**< Reserved for future use */
+#define SYSCTL_BOC_CFG_BOC_CTL_6 ((uint32_t)0x00000006) /**< Reserved for future use */
+#define SYSCTL_BOC_CFG_BOC_CTL_7 ((uint32_t)0x00000007) /**< Reserved for future use */
+/* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */
+#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /**< UNLKEY Bit Offset */
+#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /**< UNLKEY Bit Mask */
+/* SYSCTL_RESET_REQ[POR] Bits */
+#define SYSCTL_RESET_REQ_POR_OFS ( 0) /**< POR Bit Offset */
+#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /**< Generate POR */
+/* SYSCTL_RESET_REQ[REBOOT] Bits */
+#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /**< REBOOT Bit Offset */
+#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /**< Generate Reboot_Reset */
+/* SYSCTL_RESET_REQ[WKEY] Bits */
+#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /**< WKEY Bit Offset */
+#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /**< WKEY Bit Mask */
+/* SYSCTL_RESET_STATOVER[SOFT] Bits */
+#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /**< SOFT Bit Offset */
+#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /**< Indicates if SOFT Reset is active */
+/* SYSCTL_RESET_STATOVER[HARD] Bits */
+#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /**< HARD Bit Offset */
+#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /**< Indicates if HARD Reset is active */
+/* SYSCTL_RESET_STATOVER[REBOOT] Bits */
+#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /**< REBOOT Bit Offset */
+#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /**< Indicates if Reboot Reset is active */
+/* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */
+#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /**< SOFT_OVER Bit Offset */
+#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /**< SOFT_Reset overwrite request */
+/* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */
+#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /**< HARD_OVER Bit Offset */
+#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /**< HARD_Reset overwrite request */
+/* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */
+#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /**< RBT_OVER Bit Offset */
+#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /**< Reboot Reset overwrite request */
+/* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */
+#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /**< DBG_SEC_ACT Bit Offset */
+#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /**< Debug Security active */
+/* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */
+#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /**< JTAG_SWD_LOCK_ACT Bit Offset */
+#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /**< Indicates if JTAG and SWD Lock is active */
+/* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */
+#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /**< IP_PROT_ACT Bit Offset */
+#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /**< Indicates if IP protection is active */
/* Pre-defined bitfield values */
-#define SYSCTL_REBOOT_CTL_WKEY_VAL (0x00006900) /* Key value to enable writes to bit 0 */
+#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /* Key value to enable writes to bit 0 */
/* cleared */
-//*****************************************************************************
-// SYSTICK Bits
-//*****************************************************************************
-/* SYSTICK_STCSR[SYSTICK_STCSR_ENABLE] Bits */
-#define SYSTICK_STCSR_ENABLE_OFS ( 0) /* ENABLE Offset */
-#define SYSTICK_STCSR_ENABLE (0x00000001) /* */
-/* SYSTICK_STCSR[SYSTICK_STCSR_TICKINT] Bits */
-#define SYSTICK_STCSR_TICKINT_OFS ( 1) /* TICKINT Offset */
-#define SYSTICK_STCSR_TICKINT (0x00000002) /* */
-/* SYSTICK_STCSR[SYSTICK_STCSR_CLKSOURCE] Bits */
-#define SYSTICK_STCSR_CLKSOURCE_OFS ( 2) /* CLKSOURCE Offset */
-#define SYSTICK_STCSR_CLKSOURCE (0x00000004) /* */
-/* SYSTICK_STCSR[SYSTICK_STCSR_COUNTFLAG] Bits */
-#define SYSTICK_STCSR_COUNTFLAG_OFS (16) /* COUNTFLAG Offset */
-#define SYSTICK_STCSR_COUNTFLAG (0x00010000) /* */
-/* SYSTICK_STRVR[SYSTICK_STRVR_RELOAD] Bits */
-#define SYSTICK_STRVR_RELOAD_OFS ( 0) /* RELOAD Offset */
-#define SYSTICK_STRVR_RELOAD_M (0x00ffffff) /* */
-/* SYSTICK_STCVR[SYSTICK_STCVR_CURRENT] Bits */
-#define SYSTICK_STCVR_CURRENT_OFS ( 0) /* CURRENT Offset */
-#define SYSTICK_STCVR_CURRENT_M (0x00ffffff) /* */
-/* SYSTICK_STCR[SYSTICK_STCR_TENMS] Bits */
-#define SYSTICK_STCR_TENMS_OFS ( 0) /* TENMS Offset */
-#define SYSTICK_STCR_TENMS_M (0x00ffffff) /* */
-/* SYSTICK_STCR[SYSTICK_STCR_SKEW] Bits */
-#define SYSTICK_STCR_SKEW_OFS (30) /* SKEW Offset */
-#define SYSTICK_STCR_SKEW (0x40000000) /* */
-/* SYSTICK_STCR[SYSTICK_STCR_NOREF] Bits */
-#define SYSTICK_STCR_NOREF_OFS (31) /* NOREF Offset */
-#define SYSTICK_STCR_NOREF (0x80000000) /* */
+
+/******************************************************************************
+* SYSTICK Bits
+******************************************************************************/
+
+/******************************************************************************
+* Timer32 Bits
+******************************************************************************/
+/* TIMER32_CONTROL[ONESHOT] Bits */
+#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /**< ONESHOT Bit Offset */
+#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /**< Selects one-shot or wrapping counter mode */
+/* TIMER32_CONTROL[SIZE] Bits */
+#define TIMER32_CONTROL_SIZE_OFS ( 1) /**< SIZE Bit Offset */
+#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /**< Selects 16 or 32 bit counter operation */
+/* TIMER32_CONTROL[PRESCALE] Bits */
+#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /**< PRESCALE Bit Offset */
+#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /**< PRESCALE Bit Mask */
+#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /**< PRESCALE Bit 0 */
+#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /**< PRESCALE Bit 1 */
+#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /**< 0 stages of prescale, clock is divided by 1 */
+#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /**< 4 stages of prescale, clock is divided by 16 */
+#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /**< 8 stages of prescale, clock is divided by 256 */
+/* TIMER32_CONTROL[IE] Bits */
+#define TIMER32_CONTROL_IE_OFS ( 5) /**< IE Bit Offset */
+#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /**< Interrupt enable bit */
+/* TIMER32_CONTROL[MODE] Bits */
+#define TIMER32_CONTROL_MODE_OFS ( 6) /**< MODE Bit Offset */
+#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /**< Mode bit */
+/* TIMER32_CONTROL[ENABLE] Bits */
+#define TIMER32_CONTROL_ENABLE_OFS ( 7) /**< ENABLE Bit Offset */
+#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080)
+/* TIMER32_RIS[RAW_IFG] Bits */
+#define TIMER32_RIS_RAW_IFG_OFS ( 0) /**< RAW_IFG Bit Offset */
+#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /**< Raw interrupt status */
+/* TIMER32_MIS[IFG] Bits */
+#define TIMER32_MIS_IFG_OFS ( 0) /**< IFG Bit Offset */
+#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /**< Enabled interrupt status */
-//*****************************************************************************
-// TIMER32 Bits
-//*****************************************************************************
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_ONESHOT] Bits */
-#define TIMER32_CONTROL1_ONESHOT_OFS ( 0) /* ONESHOT Offset */
-#define TIMER32_CONTROL1_ONESHOT (0x00000001) /* Selects one-shot or wrapping counter mode */
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_SIZE] Bits */
-#define TIMER32_CONTROL1_SIZE_OFS ( 1) /* SIZE Offset */
-#define TIMER32_CONTROL1_SIZE (0x00000002) /* Selects 16 or 32 bit counter operation */
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_PRESCALE] Bits */
-#define TIMER32_CONTROL1_PRESCALE_OFS ( 2) /* PRESCALE Offset */
-#define TIMER32_CONTROL1_PRESCALE_M (0x0000000c) /* Prescale bits */
-#define TIMER32_CONTROL1_PRESCALE0 (0x00000004) /* Prescale bits */
-#define TIMER32_CONTROL1_PRESCALE1 (0x00000008) /* Prescale bits */
-#define TIMER32_CONTROL1_PRESCALE_0 (0x00000000) /* 0 stages of prescale, clock is divided by 1 */
-#define TIMER32_CONTROL1_PRESCALE_1 (0x00000004) /* 4 stages of prescale, clock is divided by 16 */
-#define TIMER32_CONTROL1_PRESCALE_2 (0x00000008) /* 8 stages of prescale, clock is divided by 256 */
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_IE] Bits */
-#define TIMER32_CONTROL1_IE_OFS ( 5) /* IE Offset */
-#define TIMER32_CONTROL1_IE (0x00000020) /* Interrupt enable bit */
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_MODE] Bits */
-#define TIMER32_CONTROL1_MODE_OFS ( 6) /* MODE Offset */
-#define TIMER32_CONTROL1_MODE (0x00000040) /* Mode bit */
-/* TIMER32_CONTROL1[TIMER32_CONTROL1_ENABLE] Bits */
-#define TIMER32_CONTROL1_ENABLE_OFS ( 7) /* ENABLE Offset */
-#define TIMER32_CONTROL1_ENABLE (0x00000080) /* */
-/* TIMER32_RIS1[TIMER32_RIS1_RAW_IFG] Bits */
-#define TIMER32_RIS1_RAW_IFG_OFS ( 0) /* RAW_IFG Offset */
-#define TIMER32_RIS1_RAW_IFG (0x00000001) /* Raw interrupt status */
-/* TIMER32_MIS1[TIMER32_MIS1_] Bits */
-#define TIMER32_MIS1__OFS ( 0) /* IFG Offset */
-#define TIMER32_MIS1_ (0x00000001) /* Enabled interrupt status */
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_ONESHOT] Bits */
-#define TIMER32_CONTROL2_ONESHOT_OFS ( 0) /* ONESHOT Offset */
-#define TIMER32_CONTROL2_ONESHOT (0x00000001) /* Selects one-shot or wrapping counter mode */
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_SIZE] Bits */
-#define TIMER32_CONTROL2_SIZE_OFS ( 1) /* SIZE Offset */
-#define TIMER32_CONTROL2_SIZE (0x00000002) /* Selects 16 or 32 bit counter operation */
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_PRESCALE] Bits */
-#define TIMER32_CONTROL2_PRESCALE_OFS ( 2) /* PRESCALE Offset */
-#define TIMER32_CONTROL2_PRESCALE_M (0x0000000c) /* Prescale bits */
-#define TIMER32_CONTROL2_PRESCALE0 (0x00000004) /* Prescale bits */
-#define TIMER32_CONTROL2_PRESCALE1 (0x00000008) /* Prescale bits */
-#define TIMER32_CONTROL2_PRESCALE_0 (0x00000000) /* 0 stages of prescale, clock is divided by 1 */
-#define TIMER32_CONTROL2_PRESCALE_1 (0x00000004) /* 4 stages of prescale, clock is divided by 16 */
-#define TIMER32_CONTROL2_PRESCALE_2 (0x00000008) /* 8 stages of prescale, clock is divided by 256 */
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_IE] Bits */
-#define TIMER32_CONTROL2_IE_OFS ( 5) /* IE Offset */
-#define TIMER32_CONTROL2_IE (0x00000020) /* Interrupt enable bit */
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_MODE] Bits */
-#define TIMER32_CONTROL2_MODE_OFS ( 6) /* MODE Offset */
-#define TIMER32_CONTROL2_MODE (0x00000040) /* Mode bit */
-/* TIMER32_CONTROL2[TIMER32_CONTROL2_ENABLE] Bits */
-#define TIMER32_CONTROL2_ENABLE_OFS ( 7) /* ENABLE Offset */
-#define TIMER32_CONTROL2_ENABLE (0x00000080) /* */
-/* TIMER32_RIS2[TIMER32_RIS2_RAW_IFG] Bits */
-#define TIMER32_RIS2_RAW_IFG_OFS ( 0) /* RAW_IFG Offset */
-#define TIMER32_RIS2_RAW_IFG (0x00000001) /* Raw interrupt status */
-/* TIMER32_MIS2[TIMER32_MIS2_IFG] Bits */
-#define TIMER32_MIS2_IFG_OFS ( 0) /* IFG Offset */
-#define TIMER32_MIS2_IFG (0x00000001) /* Enabled interrupt status */
+
+/******************************************************************************
+* Timer_A Bits
+******************************************************************************/
+/* TIMER_A_CTL[IFG] Bits */
+#define TIMER_A_CTL_IFG_OFS ( 0) /**< TAIFG Bit Offset */
+#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /**< TimerA interrupt flag */
+/* TIMER_A_CTL[IE] Bits */
+#define TIMER_A_CTL_IE_OFS ( 1) /**< TAIE Bit Offset */
+#define TIMER_A_CTL_IE ((uint16_t)0x0002) /**< TimerA interrupt enable */
+/* TIMER_A_CTL[CLR] Bits */
+#define TIMER_A_CTL_CLR_OFS ( 2) /**< TACLR Bit Offset */
+#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /**< TimerA clear */
+/* TIMER_A_CTL[MC] Bits */
+#define TIMER_A_CTL_MC_OFS ( 4) /**< MC Bit Offset */
+#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /**< MC Bit Mask */
+#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /**< MC Bit 0 */
+#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /**< MC Bit 1 */
+#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /**< Stop mode: Timer is halted */
+#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /**< Up mode: Timer counts up to TAxCCR0 */
+#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /**< Continuous mode: Timer counts up to 0FFFFh */
+#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /**< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /**< Stop mode: Timer is halted */
+#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /**< Up mode: Timer counts up to TAxCCR0 */
+#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /**< Continuous mode: Timer counts up to 0FFFFh */
+#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /**< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
+/* TIMER_A_CTL[ID] Bits */
+#define TIMER_A_CTL_ID_OFS ( 6) /**< ID Bit Offset */
+#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /**< ID Bit Mask */
+#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /**< ID Bit 0 */
+#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /**< ID Bit 1 */
+#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /**< /1 */
+#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /**< /2 */
+#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /**< /4 */
+#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /**< /8 */
+#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /**< /1 */
+#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /**< /2 */
+#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /**< /4 */
+#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /**< /8 */
+/* TIMER_A_CTL[SSEL] Bits */
+#define TIMER_A_CTL_SSEL_OFS ( 8) /**< TASSEL Bit Offset */
+#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /**< TASSEL Bit Mask */
+#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /**< SSEL Bit 0 */
+#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /**< SSEL Bit 1 */
+#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /**< TAxCLK */
+#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /**< ACLK */
+#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /**< SMCLK */
+#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /**< INCLK */
+#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /**< TAxCLK */
+#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /**< ACLK */
+#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /**< SMCLK */
+#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /**< INCLK */
+/* TIMER_A_CCTLN[CCIFG] Bits */
+#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /**< CCIFG Bit Offset */
+#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /**< Capture/compare interrupt flag */
+/* TIMER_A_CCTLN[COV] Bits */
+#define TIMER_A_CCTLN_COV_OFS ( 1) /**< COV Bit Offset */
+#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /**< Capture overflow */
+/* TIMER_A_CCTLN[OUT] Bits */
+#define TIMER_A_CCTLN_OUT_OFS ( 2) /**< OUT Bit Offset */
+#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /**< Output */
+/* TIMER_A_CCTLN[CCI] Bits */
+#define TIMER_A_CCTLN_CCI_OFS ( 3) /**< CCI Bit Offset */
+#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /**< Capture/compare input */
+/* TIMER_A_CCTLN[CCIE] Bits */
+#define TIMER_A_CCTLN_CCIE_OFS ( 4) /**< CCIE Bit Offset */
+#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /**< Capture/compare interrupt enable */
+/* TIMER_A_CCTLN[OUTMOD] Bits */
+#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /**< OUTMOD Bit Offset */
+#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /**< OUTMOD Bit Mask */
+#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /**< OUTMOD Bit 0 */
+#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /**< OUTMOD Bit 1 */
+#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /**< OUTMOD Bit 2 */
+#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /**< OUT bit value */
+#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /**< Set */
+#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /**< Toggle/reset */
+#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /**< Set/reset */
+#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /**< Toggle */
+#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /**< Reset */
+#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /**< Toggle/set */
+#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /**< Reset/set */
+/* TIMER_A_CCTLN[CAP] Bits */
+#define TIMER_A_CCTLN_CAP_OFS ( 8) /**< CAP Bit Offset */
+#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /**< Capture mode */
+/* TIMER_A_CCTLN[SCCI] Bits */
+#define TIMER_A_CCTLN_SCCI_OFS (10) /**< SCCI Bit Offset */
+#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /**< Synchronized capture/compare input */
+/* TIMER_A_CCTLN[SCS] Bits */
+#define TIMER_A_CCTLN_SCS_OFS (11) /**< SCS Bit Offset */
+#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /**< Synchronize capture source */
+/* TIMER_A_CCTLN[CCIS] Bits */
+#define TIMER_A_CCTLN_CCIS_OFS (12) /**< CCIS Bit Offset */
+#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /**< CCIS Bit Mask */
+#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /**< CCIS Bit 0 */
+#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /**< CCIS Bit 1 */
+#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /**< CCIxA */
+#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /**< CCIxB */
+#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /**< GND */
+#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /**< VCC */
+#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /**< CCIxA */
+#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /**< CCIxB */
+#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /**< GND */
+#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /**< VCC */
+/* TIMER_A_CCTLN[CM] Bits */
+#define TIMER_A_CCTLN_CM_OFS (14) /**< CM Bit Offset */
+#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /**< CM Bit Mask */
+#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /**< CM Bit 0 */
+#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /**< CM Bit 1 */
+#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /**< No capture */
+#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /**< Capture on rising edge */
+#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /**< Capture on falling edge */
+#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /**< Capture on both rising and falling edges */
+#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /**< No capture */
+#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /**< Capture on rising edge */
+#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /**< Capture on falling edge */
+#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /**< Capture on both rising and falling edges */
+/* TIMER_A_EX0[IDEX] Bits */
+#define TIMER_A_EX0_IDEX_OFS ( 0) /**< TAIDEX Bit Offset */
+#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /**< TAIDEX Bit Mask */
+#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /**< IDEX Bit 0 */
+#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /**< IDEX Bit 1 */
+#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /**< IDEX Bit 2 */
+#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /**< Divide by 1 */
+#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /**< Divide by 2 */
+#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /**< Divide by 3 */
+#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /**< Divide by 4 */
+#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /**< Divide by 5 */
+#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /**< Divide by 6 */
+#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /**< Divide by 7 */
+#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /**< Divide by 8 */
+#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /**< Divide by 1 */
+#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /**< Divide by 2 */
+#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /**< Divide by 3 */
+#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /**< Divide by 4 */
+#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /**< Divide by 5 */
+#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /**< Divide by 6 */
+#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /**< Divide by 7 */
+#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /**< Divide by 8 */
-//*****************************************************************************
-// TIMER_A0 Bits
-//*****************************************************************************
-/* TA0CTL[TAIFG] Bits */
-#define TAIFG_OFS ( 0) /* TAIFG Offset */
-#define TAIFG (0x0001) /* TimerA interrupt flag */
-/* TA0CTL[TAIE] Bits */
-#define TAIE_OFS ( 1) /* TAIE Offset */
-#define TAIE (0x0002) /* TimerA interrupt enable */
-/* TA0CTL[TACLR] Bits */
-#define TACLR_OFS ( 2) /* TACLR Offset */
-#define TACLR (0x0004) /* TimerA clear */
-/* TA0CTL[MC] Bits */
-#define MC_OFS ( 4) /* MC Offset */
-#define MC_M (0x0030) /* Mode control */
-#define MC0 (0x0010) /* Mode control */
-#define MC1 (0x0020) /* Mode control */
-#define MC_0 (0x0000) /* Stop mode: Timer is halted */
-#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-#define MC__STOP (0x0000) /* Stop mode: Timer is halted */
-#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-/* TA0CTL[ID] Bits */
-#define ID_OFS ( 6) /* ID Offset */
-#define ID_M (0x00c0) /* Input divider */
-#define ID0 (0x0040) /* Input divider */
-#define ID1 (0x0080) /* Input divider */
-#define ID_0 (0x0000) /* /1 */
-#define ID_1 (0x0040) /* /2 */
-#define ID_2 (0x0080) /* /4 */
-#define ID_3 (0x00c0) /* /8 */
-#define ID__1 (0x0000) /* /1 */
-#define ID__2 (0x0040) /* /2 */
-#define ID__4 (0x0080) /* /4 */
-#define ID__8 (0x00c0) /* /8 */
-/* TA0CTL[TASSEL] Bits */
-#define TASSEL_OFS ( 8) /* TASSEL Offset */
-#define TASSEL_M (0x0300) /* TimerA clock source select */
-#define TASSEL0 (0x0100) /* TimerA clock source select */
-#define TASSEL1 (0x0200) /* TimerA clock source select */
-#define TASSEL_0 (0x0000) /* TAxCLK */
-#define TASSEL_1 (0x0100) /* ACLK */
-#define TASSEL_2 (0x0200) /* SMCLK */
-#define TASSEL_3 (0x0300) /* INCLK */
-#define TASSEL__TACLK (0x0000) /* TAxCLK */
-#define TASSEL__ACLK (0x0100) /* ACLK */
-#define TASSEL__SMCLK (0x0200) /* SMCLK */
-#define TASSEL__INCLK (0x0300) /* INCLK */
-/* TA0CCTL[CCIFG] Bits */
-#define CCIFG_OFS ( 0) /* CCIFG Offset */
-#define CCIFG (0x0001) /* Capture/compare interrupt flag */
-/* TA0CCTL[COV] Bits */
-#define COV_OFS ( 1) /* COV Offset */
-#define COV (0x0002) /* Capture overflow */
-/* TA0CCTL[OUT] Bits */
-#define OUT_OFS ( 2) /* OUT Offset */
-#define OUT (0x0004) /* Output */
-/* TA0CCTL[CCI] Bits */
-#define CCI_OFS ( 3) /* CCI Offset */
-#define CCI (0x0008) /* Capture/compare input */
-/* TA0CCTL[CCIE] Bits */
-#define CCIE_OFS ( 4) /* CCIE Offset */
-#define CCIE (0x0010) /* Capture/compare interrupt enable */
-/* TA0CCTL[OUTMOD] Bits */
-#define OUTMOD_OFS ( 5) /* OUTMOD Offset */
-#define OUTMOD_M (0x00e0) /* Output mode */
-#define OUTMOD0 (0x0020) /* Output mode */
-#define OUTMOD1 (0x0040) /* Output mode */
-#define OUTMOD2 (0x0080) /* Output mode */
-#define OUTMOD_0 (0x0000) /* OUT bit value */
-#define OUTMOD_1 (0x0020) /* Set */
-#define OUTMOD_2 (0x0040) /* Toggle/reset */
-#define OUTMOD_3 (0x0060) /* Set/reset */
-#define OUTMOD_4 (0x0080) /* Toggle */
-#define OUTMOD_5 (0x00a0) /* Reset */
-#define OUTMOD_6 (0x00c0) /* Toggle/set */
-#define OUTMOD_7 (0x00e0) /* Reset/set */
-/* TA0CCTL[CAP] Bits */
-#define CAP_OFS ( 8) /* CAP Offset */
-#define CAP (0x0100) /* Capture mode */
-/* TA0CCTL[SCCI] Bits */
-#define SCCI_OFS (10) /* SCCI Offset */
-#define SCCI (0x0400) /* Synchronized capture/compare input */
-/* TA0CCTL[SCS] Bits */
-#define SCS_OFS (11) /* SCS Offset */
-#define SCS (0x0800) /* Synchronize capture source */
-/* TA0CCTL[CCIS] Bits */
-#define CCIS_OFS (12) /* CCIS Offset */
-#define CCIS_M (0x3000) /* Capture/compare input select */
-#define CCIS0 (0x1000) /* Capture/compare input select */
-#define CCIS1 (0x2000) /* Capture/compare input select */
-#define CCIS_0 (0x0000) /* CCIxA */
-#define CCIS_1 (0x1000) /* CCIxB */
-#define CCIS_2 (0x2000) /* GND */
-#define CCIS_3 (0x3000) /* VCC */
-#define CCIS__CCIA (0x0000) /* CCIxA */
-#define CCIS__CCIB (0x1000) /* CCIxB */
-#define CCIS__GND (0x2000) /* GND */
-#define CCIS__VCC (0x3000) /* VCC */
-/* TA0CCTL[CM] Bits */
-#define CM_OFS (14) /* CM Offset */
-#define CM_M (0xc000) /* Capture mode */
-#define CM0 (0x4000) /* Capture mode */
-#define CM1 (0x8000) /* Capture mode */
-#define CM_0 (0x0000) /* No capture */
-#define CM_1 (0x4000) /* Capture on rising edge */
-#define CM_2 (0x8000) /* Capture on falling edge */
-#define CM_3 (0xc000) /* Capture on both rising and falling edges */
-#define CM__NONE (0x0000) /* No capture */
-#define CM__RISING (0x4000) /* Capture on rising edge */
-#define CM__FALLING (0x8000) /* Capture on falling edge */
-#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
-/* TA0EX0[TAIDEX] Bits */
-#define TAIDEX_OFS ( 0) /* TAIDEX Offset */
-#define TAIDEX_M (0x0007) /* Input divider expansion */
-#define TAIDEX0 (0x0001) /* Input divider expansion */
-#define TAIDEX1 (0x0002) /* Input divider expansion */
-#define TAIDEX2 (0x0004) /* Input divider expansion */
-#define TAIDEX_0 (0x0000) /* Divide by 1 */
-#define TAIDEX_1 (0x0001) /* Divide by 2 */
-#define TAIDEX_2 (0x0002) /* Divide by 3 */
-#define TAIDEX_3 (0x0003) /* Divide by 4 */
-#define TAIDEX_4 (0x0004) /* Divide by 5 */
-#define TAIDEX_5 (0x0005) /* Divide by 6 */
-#define TAIDEX_6 (0x0006) /* Divide by 7 */
-#define TAIDEX_7 (0x0007) /* Divide by 8 */
-#define TAIDEX__1 (0x0000) /* Divide by 1 */
-#define TAIDEX__2 (0x0001) /* Divide by 2 */
-#define TAIDEX__3 (0x0002) /* Divide by 3 */
-#define TAIDEX__4 (0x0003) /* Divide by 4 */
-#define TAIDEX__5 (0x0004) /* Divide by 5 */
-#define TAIDEX__6 (0x0005) /* Divide by 6 */
-#define TAIDEX__7 (0x0006) /* Divide by 7 */
-#define TAIDEX__8 (0x0007) /* Divide by 8 */
+/******************************************************************************
+* TLV Bits
+******************************************************************************/
+
+/******************************************************************************
+* TLV table start and TLV tags *
+******************************************************************************/
+#define TLV_START_ADDR (TLV_BASE + 0x0004) /* Start Address of the TLV structure */
+
+#define TLV_TAG_RESERVED1 1
+#define TLV_TAG_RESERVED2 2
+#define TLV_TAG_CS 3
+#define TLV_TAG_FLASHCTL 4
+#define TLV_TAG_ADC14 5
+#define TLV_TAG_RESERVED6 6
+#define TLV_TAG_RESERVED7 7
+#define TLV_TAG_REF 8
+#define TLV_TAG_RESERVED9 9
+#define TLV_TAG_RESERVED10 10
+#define TLV_TAG_DEVINFO 11
+#define TLV_TAG_DIEREC 12
+#define TLV_TAG_RANDNUM 13
+#define TLV_TAG_RESERVED14 14
+#define TLV_TAG_BSL 15
+#define TLV_TAG_END (0x0BD0E11D)
-//*****************************************************************************
-// TIMER_A1 Bits
-//*****************************************************************************
-/* TA1CTL[TAIFG] Bits */
-//#define TAIFG_OFS ( 0) /* TAIFG Offset */
-//#define TAIFG (0x0001) /* TimerA interrupt flag */
-/* TA1CTL[TAIE] Bits */
-//#define TAIE_OFS ( 1) /* TAIE Offset */
-//#define TAIE (0x0002) /* TimerA interrupt enable */
-/* TA1CTL[TACLR] Bits */
-//#define TACLR_OFS ( 2) /* TACLR Offset */
-//#define TACLR (0x0004) /* TimerA clear */
-/* TA1CTL[MC] Bits */
-//#define MC_OFS ( 4) /* MC Offset */
-//#define MC_M (0x0030) /* Mode control */
-//#define MC0 (0x0010) /* Mode control */
-//#define MC1 (0x0020) /* Mode control */
-//#define MC_0 (0x0000) /* Stop mode: Timer is halted */
-//#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-//#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-//#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-//#define MC__STOP (0x0000) /* Stop mode: Timer is halted */
-//#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-//#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-//#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-/* TA1CTL[ID] Bits */
-//#define ID_OFS ( 6) /* ID Offset */
-//#define ID_M (0x00c0) /* Input divider */
-//#define ID0 (0x0040) /* Input divider */
-//#define ID1 (0x0080) /* Input divider */
-//#define ID_0 (0x0000) /* /1 */
-//#define ID_1 (0x0040) /* /2 */
-//#define ID_2 (0x0080) /* /4 */
-//#define ID_3 (0x00c0) /* /8 */
-//#define ID__1 (0x0000) /* /1 */
-//#define ID__2 (0x0040) /* /2 */
-//#define ID__4 (0x0080) /* /4 */
-//#define ID__8 (0x00c0) /* /8 */
-/* TA1CTL[TASSEL] Bits */
-//#define TASSEL_OFS ( 8) /* TASSEL Offset */
-//#define TASSEL_M (0x0300) /* TimerA clock source select */
-//#define TASSEL0 (0x0100) /* TimerA clock source select */
-//#define TASSEL1 (0x0200) /* TimerA clock source select */
-//#define TASSEL_0 (0x0000) /* TAxCLK */
-//#define TASSEL_1 (0x0100) /* ACLK */
-//#define TASSEL_2 (0x0200) /* SMCLK */
-//#define TASSEL_3 (0x0300) /* INCLK */
-//#define TASSEL__TACLK (0x0000) /* TAxCLK */
-//#define TASSEL__ACLK (0x0100) /* ACLK */
-//#define TASSEL__SMCLK (0x0200) /* SMCLK */
-//#define TASSEL__INCLK (0x0300) /* INCLK */
-/* TA1CCTL[CCIFG] Bits */
-//#define CCIFG_OFS ( 0) /* CCIFG Offset */
-//#define CCIFG (0x0001) /* Capture/compare interrupt flag */
-/* TA1CCTL[COV] Bits */
-//#define COV_OFS ( 1) /* COV Offset */
-//#define COV (0x0002) /* Capture overflow */
-/* TA1CCTL[OUT] Bits */
-//#define OUT_OFS ( 2) /* OUT Offset */
-//#define OUT (0x0004) /* Output */
-/* TA1CCTL[CCI] Bits */
-//#define CCI_OFS ( 3) /* CCI Offset */
-//#define CCI (0x0008) /* Capture/compare input */
-/* TA1CCTL[CCIE] Bits */
-//#define CCIE_OFS ( 4) /* CCIE Offset */
-//#define CCIE (0x0010) /* Capture/compare interrupt enable */
-/* TA1CCTL[OUTMOD] Bits */
-//#define OUTMOD_OFS ( 5) /* OUTMOD Offset */
-//#define OUTMOD_M (0x00e0) /* Output mode */
-//#define OUTMOD0 (0x0020) /* Output mode */
-//#define OUTMOD1 (0x0040) /* Output mode */
-//#define OUTMOD2 (0x0080) /* Output mode */
-//#define OUTMOD_0 (0x0000) /* OUT bit value */
-//#define OUTMOD_1 (0x0020) /* Set */
-//#define OUTMOD_2 (0x0040) /* Toggle/reset */
-//#define OUTMOD_3 (0x0060) /* Set/reset */
-//#define OUTMOD_4 (0x0080) /* Toggle */
-//#define OUTMOD_5 (0x00a0) /* Reset */
-//#define OUTMOD_6 (0x00c0) /* Toggle/set */
-//#define OUTMOD_7 (0x00e0) /* Reset/set */
-/* TA1CCTL[CAP] Bits */
-//#define CAP_OFS ( 8) /* CAP Offset */
-//#define CAP (0x0100) /* Capture mode */
-/* TA1CCTL[SCCI] Bits */
-//#define SCCI_OFS (10) /* SCCI Offset */
-//#define SCCI (0x0400) /* Synchronized capture/compare input */
-/* TA1CCTL[SCS] Bits */
-//#define SCS_OFS (11) /* SCS Offset */
-//#define SCS (0x0800) /* Synchronize capture source */
-/* TA1CCTL[CCIS] Bits */
-//#define CCIS_OFS (12) /* CCIS Offset */
-//#define CCIS_M (0x3000) /* Capture/compare input select */
-//#define CCIS0 (0x1000) /* Capture/compare input select */
-//#define CCIS1 (0x2000) /* Capture/compare input select */
-//#define CCIS_0 (0x0000) /* CCIxA */
-//#define CCIS_1 (0x1000) /* CCIxB */
-//#define CCIS_2 (0x2000) /* GND */
-//#define CCIS_3 (0x3000) /* VCC */
-//#define CCIS__CCIA (0x0000) /* CCIxA */
-//#define CCIS__CCIB (0x1000) /* CCIxB */
-//#define CCIS__GND (0x2000) /* GND */
-//#define CCIS__VCC (0x3000) /* VCC */
-/* TA1CCTL[CM] Bits */
-//#define CM_OFS (14) /* CM Offset */
-//#define CM_M (0xc000) /* Capture mode */
-//#define CM0 (0x4000) /* Capture mode */
-//#define CM1 (0x8000) /* Capture mode */
-//#define CM_0 (0x0000) /* No capture */
-//#define CM_1 (0x4000) /* Capture on rising edge */
-//#define CM_2 (0x8000) /* Capture on falling edge */
-//#define CM_3 (0xc000) /* Capture on both rising and falling edges */
-//#define CM__NONE (0x0000) /* No capture */
-//#define CM__RISING (0x4000) /* Capture on rising edge */
-//#define CM__FALLING (0x8000) /* Capture on falling edge */
-//#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
-/* TA1EX0[TAIDEX] Bits */
-//#define TAIDEX_OFS ( 0) /* TAIDEX Offset */
-//#define TAIDEX_M (0x0007) /* Input divider expansion */
-//#define TAIDEX0 (0x0001) /* Input divider expansion */
-//#define TAIDEX1 (0x0002) /* Input divider expansion */
-//#define TAIDEX2 (0x0004) /* Input divider expansion */
-//#define TAIDEX_0 (0x0000) /* Divide by 1 */
-//#define TAIDEX_1 (0x0001) /* Divide by 2 */
-//#define TAIDEX_2 (0x0002) /* Divide by 3 */
-//#define TAIDEX_3 (0x0003) /* Divide by 4 */
-//#define TAIDEX_4 (0x0004) /* Divide by 5 */
-//#define TAIDEX_5 (0x0005) /* Divide by 6 */
-//#define TAIDEX_6 (0x0006) /* Divide by 7 */
-//#define TAIDEX_7 (0x0007) /* Divide by 8 */
-//#define TAIDEX__1 (0x0000) /* Divide by 1 */
-//#define TAIDEX__2 (0x0001) /* Divide by 2 */
-//#define TAIDEX__3 (0x0002) /* Divide by 3 */
-//#define TAIDEX__4 (0x0003) /* Divide by 4 */
-//#define TAIDEX__5 (0x0004) /* Divide by 5 */
-//#define TAIDEX__6 (0x0005) /* Divide by 6 */
-//#define TAIDEX__7 (0x0006) /* Divide by 7 */
-//#define TAIDEX__8 (0x0007) /* Divide by 8 */
-
-
-//*****************************************************************************
-// TIMER_A2 Bits
-//*****************************************************************************
-/* TA2CTL[TAIFG] Bits */
-//#define TAIFG_OFS ( 0) /* TAIFG Offset */
-//#define TAIFG (0x0001) /* TimerA interrupt flag */
-/* TA2CTL[TAIE] Bits */
-//#define TAIE_OFS ( 1) /* TAIE Offset */
-//#define TAIE (0x0002) /* TimerA interrupt enable */
-/* TA2CTL[TACLR] Bits */
-//#define TACLR_OFS ( 2) /* TACLR Offset */
-//#define TACLR (0x0004) /* TimerA clear */
-/* TA2CTL[MC] Bits */
-//#define MC_OFS ( 4) /* MC Offset */
-//#define MC_M (0x0030) /* Mode control */
-//#define MC0 (0x0010) /* Mode control */
-//#define MC1 (0x0020) /* Mode control */
-//#define MC_0 (0x0000) /* Stop mode: Timer is halted */
-//#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-//#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-//#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-//#define MC__STOP (0x0000) /* Stop mode: Timer is halted */
-//#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-//#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-//#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-/* TA2CTL[ID] Bits */
-//#define ID_OFS ( 6) /* ID Offset */
-//#define ID_M (0x00c0) /* Input divider */
-//#define ID0 (0x0040) /* Input divider */
-//#define ID1 (0x0080) /* Input divider */
-//#define ID_0 (0x0000) /* /1 */
-//#define ID_1 (0x0040) /* /2 */
-//#define ID_2 (0x0080) /* /4 */
-//#define ID_3 (0x00c0) /* /8 */
-//#define ID__1 (0x0000) /* /1 */
-//#define ID__2 (0x0040) /* /2 */
-//#define ID__4 (0x0080) /* /4 */
-//#define ID__8 (0x00c0) /* /8 */
-/* TA2CTL[TASSEL] Bits */
-//#define TASSEL_OFS ( 8) /* TASSEL Offset */
-//#define TASSEL_M (0x0300) /* TimerA clock source select */
-//#define TASSEL0 (0x0100) /* TimerA clock source select */
-//#define TASSEL1 (0x0200) /* TimerA clock source select */
-//#define TASSEL_0 (0x0000) /* TAxCLK */
-//#define TASSEL_1 (0x0100) /* ACLK */
-//#define TASSEL_2 (0x0200) /* SMCLK */
-//#define TASSEL_3 (0x0300) /* INCLK */
-//#define TASSEL__TACLK (0x0000) /* TAxCLK */
-//#define TASSEL__ACLK (0x0100) /* ACLK */
-//#define TASSEL__SMCLK (0x0200) /* SMCLK */
-//#define TASSEL__INCLK (0x0300) /* INCLK */
-/* TA2CCTL[CCIFG] Bits */
-//#define CCIFG_OFS ( 0) /* CCIFG Offset */
-//#define CCIFG (0x0001) /* Capture/compare interrupt flag */
-/* TA2CCTL[COV] Bits */
-//#define COV_OFS ( 1) /* COV Offset */
-//#define COV (0x0002) /* Capture overflow */
-/* TA2CCTL[OUT] Bits */
-//#define OUT_OFS ( 2) /* OUT Offset */
-//#define OUT (0x0004) /* Output */
-/* TA2CCTL[CCI] Bits */
-//#define CCI_OFS ( 3) /* CCI Offset */
-//#define CCI (0x0008) /* Capture/compare input */
-/* TA2CCTL[CCIE] Bits */
-//#define CCIE_OFS ( 4) /* CCIE Offset */
-//#define CCIE (0x0010) /* Capture/compare interrupt enable */
-/* TA2CCTL[OUTMOD] Bits */
-//#define OUTMOD_OFS ( 5) /* OUTMOD Offset */
-//#define OUTMOD_M (0x00e0) /* Output mode */
-//#define OUTMOD0 (0x0020) /* Output mode */
-//#define OUTMOD1 (0x0040) /* Output mode */
-//#define OUTMOD2 (0x0080) /* Output mode */
-//#define OUTMOD_0 (0x0000) /* OUT bit value */
-//#define OUTMOD_1 (0x0020) /* Set */
-//#define OUTMOD_2 (0x0040) /* Toggle/reset */
-//#define OUTMOD_3 (0x0060) /* Set/reset */
-//#define OUTMOD_4 (0x0080) /* Toggle */
-//#define OUTMOD_5 (0x00a0) /* Reset */
-//#define OUTMOD_6 (0x00c0) /* Toggle/set */
-//#define OUTMOD_7 (0x00e0) /* Reset/set */
-/* TA2CCTL[CAP] Bits */
-//#define CAP_OFS ( 8) /* CAP Offset */
-//#define CAP (0x0100) /* Capture mode */
-/* TA2CCTL[SCCI] Bits */
-//#define SCCI_OFS (10) /* SCCI Offset */
-//#define SCCI (0x0400) /* Synchronized capture/compare input */
-/* TA2CCTL[SCS] Bits */
-//#define SCS_OFS (11) /* SCS Offset */
-//#define SCS (0x0800) /* Synchronize capture source */
-/* TA2CCTL[CCIS] Bits */
-//#define CCIS_OFS (12) /* CCIS Offset */
-//#define CCIS_M (0x3000) /* Capture/compare input select */
-//#define CCIS0 (0x1000) /* Capture/compare input select */
-//#define CCIS1 (0x2000) /* Capture/compare input select */
-//#define CCIS_0 (0x0000) /* CCIxA */
-//#define CCIS_1 (0x1000) /* CCIxB */
-//#define CCIS_2 (0x2000) /* GND */
-//#define CCIS_3 (0x3000) /* VCC */
-//#define CCIS__CCIA (0x0000) /* CCIxA */
-//#define CCIS__CCIB (0x1000) /* CCIxB */
-//#define CCIS__GND (0x2000) /* GND */
-//#define CCIS__VCC (0x3000) /* VCC */
-/* TA2CCTL[CM] Bits */
-//#define CM_OFS (14) /* CM Offset */
-//#define CM_M (0xc000) /* Capture mode */
-//#define CM0 (0x4000) /* Capture mode */
-//#define CM1 (0x8000) /* Capture mode */
-//#define CM_0 (0x0000) /* No capture */
-//#define CM_1 (0x4000) /* Capture on rising edge */
-//#define CM_2 (0x8000) /* Capture on falling edge */
-//#define CM_3 (0xc000) /* Capture on both rising and falling edges */
-//#define CM__NONE (0x0000) /* No capture */
-//#define CM__RISING (0x4000) /* Capture on rising edge */
-//#define CM__FALLING (0x8000) /* Capture on falling edge */
-//#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
-/* TA2EX0[TAIDEX] Bits */
-//#define TAIDEX_OFS ( 0) /* TAIDEX Offset */
-//#define TAIDEX_M (0x0007) /* Input divider expansion */
-//#define TAIDEX0 (0x0001) /* Input divider expansion */
-//#define TAIDEX1 (0x0002) /* Input divider expansion */
-//#define TAIDEX2 (0x0004) /* Input divider expansion */
-//#define TAIDEX_0 (0x0000) /* Divide by 1 */
-//#define TAIDEX_1 (0x0001) /* Divide by 2 */
-//#define TAIDEX_2 (0x0002) /* Divide by 3 */
-//#define TAIDEX_3 (0x0003) /* Divide by 4 */
-//#define TAIDEX_4 (0x0004) /* Divide by 5 */
-//#define TAIDEX_5 (0x0005) /* Divide by 6 */
-//#define TAIDEX_6 (0x0006) /* Divide by 7 */
-//#define TAIDEX_7 (0x0007) /* Divide by 8 */
-//#define TAIDEX__1 (0x0000) /* Divide by 1 */
-//#define TAIDEX__2 (0x0001) /* Divide by 2 */
-//#define TAIDEX__3 (0x0002) /* Divide by 3 */
-//#define TAIDEX__4 (0x0003) /* Divide by 4 */
-//#define TAIDEX__5 (0x0004) /* Divide by 5 */
-//#define TAIDEX__6 (0x0005) /* Divide by 6 */
-//#define TAIDEX__7 (0x0006) /* Divide by 7 */
-//#define TAIDEX__8 (0x0007) /* Divide by 8 */
-
-
-//*****************************************************************************
-// TIMER_A3 Bits
-//*****************************************************************************
-/* TA3CTL[TAIFG] Bits */
-//#define TAIFG_OFS ( 0) /* TAIFG Offset */
-//#define TAIFG (0x0001) /* TimerA interrupt flag */
-/* TA3CTL[TAIE] Bits */
-//#define TAIE_OFS ( 1) /* TAIE Offset */
-//#define TAIE (0x0002) /* TimerA interrupt enable */
-/* TA3CTL[TACLR] Bits */
-//#define TACLR_OFS ( 2) /* TACLR Offset */
-//#define TACLR (0x0004) /* TimerA clear */
-/* TA3CTL[MC] Bits */
-//#define MC_OFS ( 4) /* MC Offset */
-//#define MC_M (0x0030) /* Mode control */
-//#define MC0 (0x0010) /* Mode control */
-//#define MC1 (0x0020) /* Mode control */
-//#define MC_0 (0x0000) /* Stop mode: Timer is halted */
-//#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-//#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-//#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-//#define MC__STOP (0x0000) /* Stop mode: Timer is halted */
-//#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
-//#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
-//#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
-/* TA3CTL[ID] Bits */
-//#define ID_OFS ( 6) /* ID Offset */
-//#define ID_M (0x00c0) /* Input divider */
-//#define ID0 (0x0040) /* Input divider */
-//#define ID1 (0x0080) /* Input divider */
-//#define ID_0 (0x0000) /* /1 */
-//#define ID_1 (0x0040) /* /2 */
-//#define ID_2 (0x0080) /* /4 */
-//#define ID_3 (0x00c0) /* /8 */
-//#define ID__1 (0x0000) /* /1 */
-//#define ID__2 (0x0040) /* /2 */
-//#define ID__4 (0x0080) /* /4 */
-//#define ID__8 (0x00c0) /* /8 */
-/* TA3CTL[TASSEL] Bits */
-//#define TASSEL_OFS ( 8) /* TASSEL Offset */
-//#define TASSEL_M (0x0300) /* TimerA clock source select */
-//#define TASSEL0 (0x0100) /* TimerA clock source select */
-//#define TASSEL1 (0x0200) /* TimerA clock source select */
-//#define TASSEL_0 (0x0000) /* TAxCLK */
-//#define TASSEL_1 (0x0100) /* ACLK */
-//#define TASSEL_2 (0x0200) /* SMCLK */
-//#define TASSEL_3 (0x0300) /* INCLK */
-//#define TASSEL__TACLK (0x0000) /* TAxCLK */
-//#define TASSEL__ACLK (0x0100) /* ACLK */
-//#define TASSEL__SMCLK (0x0200) /* SMCLK */
-//#define TASSEL__INCLK (0x0300) /* INCLK */
-/* TA3CCTL[CCIFG] Bits */
-//#define CCIFG_OFS ( 0) /* CCIFG Offset */
-//#define CCIFG (0x0001) /* Capture/compare interrupt flag */
-/* TA3CCTL[COV] Bits */
-//#define COV_OFS ( 1) /* COV Offset */
-//#define COV (0x0002) /* Capture overflow */
-/* TA3CCTL[OUT] Bits */
-//#define OUT_OFS ( 2) /* OUT Offset */
-//#define OUT (0x0004) /* Output */
-/* TA3CCTL[CCI] Bits */
-//#define CCI_OFS ( 3) /* CCI Offset */
-//#define CCI (0x0008) /* Capture/compare input */
-/* TA3CCTL[CCIE] Bits */
-//#define CCIE_OFS ( 4) /* CCIE Offset */
-//#define CCIE (0x0010) /* Capture/compare interrupt enable */
-/* TA3CCTL[OUTMOD] Bits */
-//#define OUTMOD_OFS ( 5) /* OUTMOD Offset */
-//#define OUTMOD_M (0x00e0) /* Output mode */
-//#define OUTMOD0 (0x0020) /* Output mode */
-//#define OUTMOD1 (0x0040) /* Output mode */
-//#define OUTMOD2 (0x0080) /* Output mode */
-//#define OUTMOD_0 (0x0000) /* OUT bit value */
-//#define OUTMOD_1 (0x0020) /* Set */
-//#define OUTMOD_2 (0x0040) /* Toggle/reset */
-//#define OUTMOD_3 (0x0060) /* Set/reset */
-//#define OUTMOD_4 (0x0080) /* Toggle */
-//#define OUTMOD_5 (0x00a0) /* Reset */
-//#define OUTMOD_6 (0x00c0) /* Toggle/set */
-//#define OUTMOD_7 (0x00e0) /* Reset/set */
-/* TA3CCTL[CAP] Bits */
-//#define CAP_OFS ( 8) /* CAP Offset */
-//#define CAP (0x0100) /* Capture mode */
-/* TA3CCTL[SCCI] Bits */
-//#define SCCI_OFS (10) /* SCCI Offset */
-//#define SCCI (0x0400) /* Synchronized capture/compare input */
-/* TA3CCTL[SCS] Bits */
-//#define SCS_OFS (11) /* SCS Offset */
-//#define SCS (0x0800) /* Synchronize capture source */
-/* TA3CCTL[CCIS] Bits */
-//#define CCIS_OFS (12) /* CCIS Offset */
-//#define CCIS_M (0x3000) /* Capture/compare input select */
-//#define CCIS0 (0x1000) /* Capture/compare input select */
-//#define CCIS1 (0x2000) /* Capture/compare input select */
-//#define CCIS_0 (0x0000) /* CCIxA */
-//#define CCIS_1 (0x1000) /* CCIxB */
-//#define CCIS_2 (0x2000) /* GND */
-//#define CCIS_3 (0x3000) /* VCC */
-//#define CCIS__CCIA (0x0000) /* CCIxA */
-//#define CCIS__CCIB (0x1000) /* CCIxB */
-//#define CCIS__GND (0x2000) /* GND */
-//#define CCIS__VCC (0x3000) /* VCC */
-/* TA3CCTL[CM] Bits */
-//#define CM_OFS (14) /* CM Offset */
-//#define CM_M (0xc000) /* Capture mode */
-//#define CM0 (0x4000) /* Capture mode */
-//#define CM1 (0x8000) /* Capture mode */
-//#define CM_0 (0x0000) /* No capture */
-//#define CM_1 (0x4000) /* Capture on rising edge */
-//#define CM_2 (0x8000) /* Capture on falling edge */
-//#define CM_3 (0xc000) /* Capture on both rising and falling edges */
-//#define CM__NONE (0x0000) /* No capture */
-//#define CM__RISING (0x4000) /* Capture on rising edge */
-//#define CM__FALLING (0x8000) /* Capture on falling edge */
-//#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
-/* TA3EX0[TAIDEX] Bits */
-//#define TAIDEX_OFS ( 0) /* TAIDEX Offset */
-//#define TAIDEX_M (0x0007) /* Input divider expansion */
-//#define TAIDEX0 (0x0001) /* Input divider expansion */
-//#define TAIDEX1 (0x0002) /* Input divider expansion */
-//#define TAIDEX2 (0x0004) /* Input divider expansion */
-//#define TAIDEX_0 (0x0000) /* Divide by 1 */
-//#define TAIDEX_1 (0x0001) /* Divide by 2 */
-//#define TAIDEX_2 (0x0002) /* Divide by 3 */
-//#define TAIDEX_3 (0x0003) /* Divide by 4 */
-//#define TAIDEX_4 (0x0004) /* Divide by 5 */
-//#define TAIDEX_5 (0x0005) /* Divide by 6 */
-//#define TAIDEX_6 (0x0006) /* Divide by 7 */
-//#define TAIDEX_7 (0x0007) /* Divide by 8 */
-//#define TAIDEX__1 (0x0000) /* Divide by 1 */
-//#define TAIDEX__2 (0x0001) /* Divide by 2 */
-//#define TAIDEX__3 (0x0002) /* Divide by 3 */
-//#define TAIDEX__4 (0x0003) /* Divide by 4 */
-//#define TAIDEX__5 (0x0004) /* Divide by 5 */
-//#define TAIDEX__6 (0x0005) /* Divide by 6 */
-//#define TAIDEX__7 (0x0006) /* Divide by 7 */
-//#define TAIDEX__8 (0x0007) /* Divide by 8 */
-
-
-//*****************************************************************************
-// TLV Bits
-//*****************************************************************************
-
-
-//*****************************************************************************
-// WDT_A Bits
-//*****************************************************************************
-/* WDTCTL[WDTIS] Bits */
-#define WDTIS_OFS ( 0) /* WDTIS Offset */
-#define WDTIS_M (0x0007) /* Watchdog timer interval select */
-#define WDTIS0 (0x0001) /* Watchdog timer interval select */
-#define WDTIS1 (0x0002) /* Watchdog timer interval select */
-#define WDTIS2 (0x0004) /* Watchdog timer interval select */
-#define WDTIS_0 (0x0000) /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
-#define WDTIS_1 (0x0001) /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
-#define WDTIS_2 (0x0002) /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
-#define WDTIS_3 (0x0003) /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
-#define WDTIS_4 (0x0004) /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
-#define WDTIS_5 (0x0005) /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
-#define WDTIS_6 (0x0006) /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
-#define WDTIS_7 (0x0007) /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
-/* WDTCTL[WDTCNTCL] Bits */
-#define WDTCNTCL_OFS ( 3) /* WDTCNTCL Offset */
-#define WDTCNTCL (0x0008) /* Watchdog timer counter clear */
-/* WDTCTL[WDTTMSEL] Bits */
-#define WDTTMSEL_OFS ( 4) /* WDTTMSEL Offset */
-#define WDTTMSEL (0x0010) /* Watchdog timer mode select */
-/* WDTCTL[WDTSSEL] Bits */
-#define WDTSSEL_OFS ( 5) /* WDTSSEL Offset */
-#define WDTSSEL_M (0x0060) /* Watchdog timer clock source select */
-#define WDTSSEL0 (0x0020) /* Watchdog timer clock source select */
-#define WDTSSEL1 (0x0040) /* Watchdog timer clock source select */
-#define WDTSSEL_0 (0x0000) /* SMCLK */
-#define WDTSSEL_1 (0x0020) /* ACLK */
-#define WDTSSEL_2 (0x0040) /* VLOCLK */
-#define WDTSSEL_3 (0x0060) /* BCLK */
-#define WDTSSEL__SMCLK (0x0000) /* SMCLK */
-#define WDTSSEL__ACLK (0x0020) /* ACLK */
-#define WDTSSEL__VLOCLK (0x0040) /* VLOCLK */
-#define WDTSSEL__BCLK (0x0060) /* BCLK */
-/* WDTCTL[WDTHOLD] Bits */
-#define WDTHOLD_OFS ( 7) /* WDTHOLD Offset */
-#define WDTHOLD (0x0080) /* Watchdog timer hold */
-/* WDTCTL[WDTPW] Bits */
-#define WDTPW_OFS ( 8) /* WDTPW Offset */
-#define WDTPW_M (0xff00) /* Watchdog timer password */
+/******************************************************************************
+* WDT_A Bits
+******************************************************************************/
+/* WDT_A_CTL[IS] Bits */
+#define WDT_A_CTL_IS_OFS ( 0) /**< WDTIS Bit Offset */
+#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /**< WDTIS Bit Mask */
+#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /**< IS Bit 0 */
+#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /**< IS Bit 1 */
+#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /**< IS Bit 2 */
+#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /**< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
+#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /**< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
+#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /**< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
+#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /**< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
+#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /**< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
+#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /**< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
+#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /**< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
+#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /**< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
+/* WDT_A_CTL[CNTCL] Bits */
+#define WDT_A_CTL_CNTCL_OFS ( 3) /**< WDTCNTCL Bit Offset */
+#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /**< Watchdog timer counter clear */
+/* WDT_A_CTL[TMSEL] Bits */
+#define WDT_A_CTL_TMSEL_OFS ( 4) /**< WDTTMSEL Bit Offset */
+#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /**< Watchdog timer mode select */
+/* WDT_A_CTL[SSEL] Bits */
+#define WDT_A_CTL_SSEL_OFS ( 5) /**< WDTSSEL Bit Offset */
+#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /**< WDTSSEL Bit Mask */
+#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /**< SSEL Bit 0 */
+#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /**< SSEL Bit 1 */
+#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /**< SMCLK */
+#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /**< ACLK */
+#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /**< VLOCLK */
+#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /**< BCLK */
+#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /**< SMCLK */
+#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /**< ACLK */
+#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /**< VLOCLK */
+#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /**< BCLK */
+/* WDT_A_CTL[HOLD] Bits */
+#define WDT_A_CTL_HOLD_OFS ( 7) /**< WDTHOLD Bit Offset */
+#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /**< Watchdog timer hold */
+/* WDT_A_CTL[PW] Bits */
+#define WDT_A_CTL_PW_OFS ( 8) /**< WDTPW Bit Offset */
+#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /**< WDTPW Bit Mask */
/* Pre-defined bitfield values */
-#define WDTPW (0x5A00) /* WDT Key Value for WDT write access */
+#define WDT_A_CTL_PW ((uint16_t)0x5A00) /* WDT Key Value for WDT write access */
-//*****************************************************************************
-// BSL
-//*****************************************************************************
+
+/******************************************************************************
+* BSL *
+******************************************************************************/
#define BSL_DEFAULT_PARAM (0xFC48FFFF) /* I2C slave address = 0x48, Interface selection = Auto */
#define BSL_API_TABLE_ADDR (0x00202000) /* Address of BSL API table */
#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR))
@@ -18049,10 +6767,10 @@
#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /* Invoke the BSL with paramters */
-//*****************************************************************************
-// ULP Advisor
-//*****************************************************************************
-#ifdef __TMS470__
+/******************************************************************************
+* ULP Advisor *
+******************************************************************************/
+#ifdef __TI_ARM__
#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})
#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})
#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})
@@ -18065,66 +6783,9 @@
#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})
#endif
-//*****************************************************************************
-// NVIC interrupts
-//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
-// System exceptions
-#define FAULT_NMI ( 2) /* NMI fault */
-#define FAULT_HARD ( 3) /* Hard fault */
-#define FAULT_MPU ( 4) /* MPU fault */
-#define FAULT_BUS ( 5) /* Bus fault */
-#define FAULT_USAGE ( 6) /* Usage fault */
-#define FAULT_SVCALL (11) /* SVCall */
-#define FAULT_DEBUG (12) /* Debug monitor */
-#define FAULT_PENDSV (14) /* PendSV */
-#define FAULT_SYSTICK (15) /* System Tick */
-
-// External interrupts
-#define INT_PSS (16) /* PSS IRQ */
-#define INT_CS (17) /* CS IRQ */
-#define INT_PCM (18) /* PCM IRQ */
-#define INT_WDT_A (19) /* WDT_A IRQ */
-#define INT_FPU (20) /* FPU IRQ */
-#define INT_FLCTL (21) /* FLCTL IRQ */
-#define INT_COMP_E0 (22) /* COMP_E0 IRQ */
-#define INT_COMP_E1 (23) /* COMP_E1 IRQ */
-#define INT_TA0_0 (24) /* TA0_0 IRQ */
-#define INT_TA0_N (25) /* TA0_N IRQ */
-#define INT_TA1_0 (26) /* TA1_0 IRQ */
-#define INT_TA1_N (27) /* TA1_N IRQ */
-#define INT_TA2_0 (28) /* TA2_0 IRQ */
-#define INT_TA2_N (29) /* TA2_N IRQ */
-#define INT_TA3_0 (30) /* TA3_0 IRQ */
-#define INT_TA3_N (31) /* TA3_N IRQ */
-#define INT_EUSCIA0 (32) /* EUSCIA0 IRQ */
-#define INT_EUSCIA1 (33) /* EUSCIA1 IRQ */
-#define INT_EUSCIA2 (34) /* EUSCIA2 IRQ */
-#define INT_EUSCIA3 (35) /* EUSCIA3 IRQ */
-#define INT_EUSCIB0 (36) /* EUSCIB0 IRQ */
-#define INT_EUSCIB1 (37) /* EUSCIB1 IRQ */
-#define INT_EUSCIB2 (38) /* EUSCIB2 IRQ */
-#define INT_EUSCIB3 (39) /* EUSCIB3 IRQ */
-#define INT_ADC14 (40) /* ADC14 IRQ */
-#define INT_T32_INT1 (41) /* T32_INT1 IRQ */
-#define INT_T32_INT2 (42) /* T32_INT2 IRQ */
-#define INT_T32_INTC (43) /* T32_INTC IRQ */
-#define INT_AES256 (44) /* AES256 IRQ */
-#define INT_RTC_C (45) /* RTC_C IRQ */
-#define INT_DMA_ERR (46) /* DMA_ERR IRQ */
-#define INT_DMA_INT3 (47) /* DMA_INT3 IRQ */
-#define INT_DMA_INT2 (48) /* DMA_INT2 IRQ */
-#define INT_DMA_INT1 (49) /* DMA_INT1 IRQ */
-#define INT_DMA_INT0 (50) /* DMA_INT0 IRQ */
-#define INT_PORT1 (51) /* PORT1 IRQ */
-#define INT_PORT2 (52) /* PORT2 IRQ */
-#define INT_PORT3 (53) /* PORT3 IRQ */
-#define INT_PORT4 (54) /* PORT4 IRQ */
-#define INT_PORT5 (55) /* PORT5 IRQ */
-#define INT_PORT6 (56) /* PORT6 IRQ */
-
-// Highest interrupt available
-#define NUM_INTERRUPTS (56)
-
-#endif // __MSP432P401R_H__
+#endif /* __MSP432P401R_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h
index 15dec1f..9541a2b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/msp_compatibility.h
@@ -1,6 +1,6 @@
//*****************************************************************************
//
-// Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com/
+// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -34,8 +34,27 @@
//
//****************************************************************************
+/******************************************************************************
+* Definitions for 8/16/32-bit wide memory access *
+******************************************************************************/
+#define HWREG8(x) (*((volatile uint8_t *)(x)))
+#define HWREG16(x) (*((volatile uint16_t *)(x)))
+#define HWREG32(x) (*((volatile uint32_t *)(x)))
+#define HWREG(x) (HWREG16(x))
+#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
+#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
+#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
+#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
+
+/******************************************************************************
+* Definitions for 8/16/32-bit wide bit band access *
+******************************************************************************/
+#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
+
// Intrinsics with ARM equivalents
-#if defined ( __TMS470__ ) /* TI CGT Compiler */
+#if defined ( __TI_ARM__ ) /* TI CGT Compiler */
#include <cmsis_ccs.h>
@@ -87,6 +106,7 @@
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#elif defined ( __CC_ARM ) /* ARM Compiler */
@@ -118,9 +138,11 @@
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#elif defined ( __GNUC__ ) /* GCC Compiler */
-
+#undef __wfi
+#define __wfi() asm(" wfi")
#define __sleep() __wfi()
#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; }
#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; }
@@ -149,6 +171,7 @@
#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ }
#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ }
+#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ }
#endif
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/system_msp432p401r.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/system_msp432p401r.h
new file mode 100644
index 0000000..3478b51
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/inc/system_msp432p401r.h
@@ -0,0 +1,91 @@
+/**************************************************************************//**
+* @file system_msp432p401r.h
+* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for
+* MSP432P401R
+* @version V1.00
+* @date 20-Oct-2015
+*
+* @note View configuration instructions embedded in comments
+*
+******************************************************************************/
+//*****************************************************************************
+//
+// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef SYSTEM_MSP432P401R_H
+#define SYSTEM_MSP432P401R_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ *
+ * Performs the following initialization steps:
+ * 1. Enables the FPU
+ * 2. Halts the WDT
+ * 3. Enables all SRAM banks
+ * 4. Sets up power __REGULATOR and VCORE
+ * 5. Enable Flash wait states if needed
+ * 6. Change MCLK to desired frequency
+ * 7. Enable Flash read buffering
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_MSP432P401R_H */
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c
index b1fb81d..7fb7440 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,6 +41,7 @@
#include <debug.h>
#include <cpu.h>
#include <interrupt.h>
+#include <hw_memmap.h>
//*****************************************************************************
//
@@ -232,7 +233,7 @@
//
// Set the priority grouping.
//
- SCB->AIRCR = SCB_AIRCR_VECTKEY_M | g_pulPriority[bits];
+ SCB->AIRCR = SCB_AIRCR_VECTKEY_Msk | g_pulPriority[bits];
}
uint32_t Interrupt_getPriorityGrouping(void)
@@ -311,19 +312,19 @@
//
// Enable the MemManage interrupt.
//
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA;
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
} else if (interruptNumber == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
- SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA;
+ SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
} else if (interruptNumber == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
- SCB->SHCSR |= SCB_SHCSR_USGFAULTENA;
+ SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
@@ -355,19 +356,19 @@
//
// Disable the MemManage interrupt.
//
- SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA);
+ SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA_Msk);
} else if (interruptNumber == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
- SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA);
+ SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA_Msk);
} else if (interruptNumber == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
- SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA);
+ SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA_Msk);
} else if (interruptNumber == FAULT_SYSTICK)
{
//
@@ -406,19 +407,19 @@
//
// Check the MemManage interrupt.
//
- ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA;
+ ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA_Msk;
} else if (interruptNumber == FAULT_BUS)
{
//
// Check the bus fault interrupt.
//
- ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA;
+ ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA_Msk;
} else if (interruptNumber == FAULT_USAGE)
{
//
// Check the usage fault interrupt.
//
- ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA;
+ ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
@@ -451,19 +452,19 @@
//
// Pend the NMI interrupt.
//
- SCB->ICSR |= SCB_ICSR_NMIPENDSET;
+ SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk;
} else if (interruptNumber == FAULT_PENDSV)
{
//
// Pend the PendSV interrupt.
//
- SCB->ICSR |= SCB_ICSR_PENDSVSET;
+ SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Pend the SysTick interrupt.
//
- SCB->ICSR |= SCB_ICSR_PENDSTSET;
+ SCB->ICSR |= SCB_ICSR_PENDSTSET_Msk;
} else if (interruptNumber >= 16)
{
//
@@ -489,13 +490,13 @@
//
// Unpend the PendSV interrupt.
//
- SCB->ICSR |= SCB_ICSR_PENDSVCLR;
+ SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk;
} else if (interruptNumber == FAULT_SYSTICK)
{
//
// Unpend the SysTick interrupt.
//
- SCB->ICSR |= SCB_ICSR_PENDSTCLR;
+ SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
} else if (interruptNumber >= 16)
{
//
@@ -528,10 +529,10 @@
void Interrupt_enableSleepOnIsrExit(void)
{
- SCB->SCR |= SCB_SCR_SLEEPONEXIT;
+ SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
}
void Interrupt_disableSleepOnIsrExit(void)
{
- SCB->SCR &= ~SCB_SCR_SLEEPONEXIT;
+ SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h
index 253dd66..1cb78cf 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/interrupt.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -60,6 +60,64 @@
#include <stdbool.h>
#include <msp.h>
+/******************************************************************************
+* NVIC interrupts *
+******************************************************************************/
+/* System exceptions */
+#define FAULT_NMI ( 2) /* NMI fault */
+#define FAULT_HARD ( 3) /* Hard fault */
+#define FAULT_MPU ( 4) /* MPU fault */
+#define FAULT_BUS ( 5) /* Bus fault */
+#define FAULT_USAGE ( 6) /* Usage fault */
+#define FAULT_SVCALL (11) /* SVCall */
+#define FAULT_DEBUG (12) /* Debug monitor */
+#define FAULT_PENDSV (14) /* PendSV */
+#define FAULT_SYSTICK (15) /* System Tick */
+
+/* External interrupts */
+#define INT_PSS (16) /* PSS IRQ */
+#define INT_CS (17) /* CS IRQ */
+#define INT_PCM (18) /* PCM IRQ */
+#define INT_WDT_A (19) /* WDT_A IRQ */
+#define INT_FPU (20) /* FPU IRQ */
+#define INT_FLCTL (21) /* FLCTL IRQ */
+#define INT_COMP_E0 (22) /* COMP_E0 IRQ */
+#define INT_COMP_E1 (23) /* COMP_E1 IRQ */
+#define INT_TA0_0 (24) /* TA0_0 IRQ */
+#define INT_TA0_N (25) /* TA0_N IRQ */
+#define INT_TA1_0 (26) /* TA1_0 IRQ */
+#define INT_TA1_N (27) /* TA1_N IRQ */
+#define INT_TA2_0 (28) /* TA2_0 IRQ */
+#define INT_TA2_N (29) /* TA2_N IRQ */
+#define INT_TA3_0 (30) /* TA3_0 IRQ */
+#define INT_TA3_N (31) /* TA3_N IRQ */
+#define INT_EUSCIA0 (32) /* EUSCIA0 IRQ */
+#define INT_EUSCIA1 (33) /* EUSCIA1 IRQ */
+#define INT_EUSCIA2 (34) /* EUSCIA2 IRQ */
+#define INT_EUSCIA3 (35) /* EUSCIA3 IRQ */
+#define INT_EUSCIB0 (36) /* EUSCIB0 IRQ */
+#define INT_EUSCIB1 (37) /* EUSCIB1 IRQ */
+#define INT_EUSCIB2 (38) /* EUSCIB2 IRQ */
+#define INT_EUSCIB3 (39) /* EUSCIB3 IRQ */
+#define INT_ADC14 (40) /* ADC14 IRQ */
+#define INT_T32_INT1 (41) /* T32_INT1 IRQ */
+#define INT_T32_INT2 (42) /* T32_INT2 IRQ */
+#define INT_T32_INTC (43) /* T32_INTC IRQ */
+#define INT_AES256 (44) /* AES256 IRQ */
+#define INT_RTC_C (45) /* RTC_C IRQ */
+#define INT_DMA_ERR (46) /* DMA_ERR IRQ */
+#define INT_DMA_INT3 (47) /* DMA_INT3 IRQ */
+#define INT_DMA_INT2 (48) /* DMA_INT2 IRQ */
+#define INT_DMA_INT1 (49) /* DMA_INT1 IRQ */
+#define INT_DMA_INT0 (50) /* DMA_INT0 IRQ */
+#define INT_PORT1 (51) /* PORT1 IRQ */
+#define INT_PORT2 (52) /* PORT2 IRQ */
+#define INT_PORT3 (53) /* PORT3 IRQ */
+#define INT_PORT4 (54) /* PORT4 IRQ */
+#define INT_PORT5 (55) /* PORT5 IRQ */
+#define INT_PORT6 (56) /* PORT6 IRQ */
+
+#define NUM_INTERRUPTS (56)
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
@@ -157,6 +215,11 @@
//! See the discussion of compile-time versus run-time interrupt handler
//! registration in the introduction to this chapter.
//!
+//! \note This function is only used if the customer wants to specify the
+//! interrupt handler at run time. In most cases, this is done through means
+//! of the user setting the ISR function pointer in the startup file. Refer
+//! Refer to the Module Operation section for more details.
+//!
//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
//! parameter
//!
@@ -484,18 +547,16 @@
//! this is ideal as power cycles are not wasted with the processing required
//! for waking up from an ISR and going back to sleep.
//!
-//! \return Address of the vector table.
+//! \return None
//
//*****************************************************************************
extern void Interrupt_enableSleepOnIsrExit(void);
//*****************************************************************************
//
-//! Enables the processor to sleep when exiting an ISR. For low power operation,
-//! this is ideal as power cycles are not wasted with the processing required
-//! for waking up from an ISR and going back to sleep.
+//! Disables the processor to sleep when exiting an ISR.
//!
-//! \return Address of the vector table.
+//! \return None
//
//*****************************************************************************
extern void Interrupt_disableSleepOnIsrExit(void);
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c
index 04bf35d..00e85ce 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -49,7 +49,7 @@
// Set the MPU control bits according to the flags passed by the user,
// and also set the enable bit.
//
- MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE;
+ MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE_Msk;
}
void MPU_disableModule(void)
@@ -57,7 +57,7 @@
//
// Turn off the MPU enable bit.
//
- MPU->CTRL &= ~MPU_CTRL_ENABLE;
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
@@ -67,7 +67,7 @@
// Read the DREGION field of the MPU type register and mask off
// the bits of interest to get the count of regions.
//
- return ((MPU->TYPE & MPU_TYPE_DREGION_M) >> NVIC_MPU_TYPE_DREGION_S);
+ return ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> NVIC_MPU_TYPE_DREGION_S);
}
void MPU_enableRegion(uint32_t region)
@@ -85,7 +85,7 @@
//
// Modify the enable bit in the region attributes.
//
- MPU->RASR |= MPU_RASR_ENABLE;
+ MPU->RASR |= MPU_RASR_ENABLE_Msk;
}
void MPU_disableRegion(uint32_t region)
@@ -103,7 +103,7 @@
//
// Modify the enable bit in the region attributes.
//
- MPU->RASR &= ~MPU_RASR_ENABLE;
+ MPU->RASR &= ~MPU_RASR_ENABLE_Msk;
}
void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags)
@@ -117,15 +117,15 @@
// Program the base address, use the region field to select the
// region at the same time.
//
- MPU->RBAR = addr | region | MPU_RBAR_VALID;
+ MPU->RBAR = addr | region | MPU_RBAR_VALID_Msk;
//
// Program the region attributes. Set the TEX field and the S, C,
// and B bits to fixed values that are suitable for all Stellaris
// memory.
//
- MPU->RASR = (flags & ~(MPU_RASR_TEX_M | MPU_RASR_C)) | MPU_RASR_S
- | MPU_RASR_B;
+ MPU->RASR = (flags & ~(MPU_RASR_TEX_Msk | MPU_RASR_C_Msk)) | MPU_RASR_S_Msk
+ | MPU_RASR_B_Msk;
}
void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags)
@@ -145,7 +145,7 @@
//
// Read and store the base address for the region.
//
- *addr = MPU->RBAR & MPU_RBAR_ADDR_M;
+ *addr = MPU->RBAR & MPU_RBAR_ADDR_Msk;
//
// Read and store the region attributes.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h
index 1b1162c..e7925f4 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/mpu.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -64,8 +64,8 @@
// Flags that can be passed to MPU_enableModule.
//
//*****************************************************************************
-#define MPU_CONFIG_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA
-#define MPU_CONFIG_HARDFLT_NMI MPU_CTRL_HFNMIENA
+#define MPU_CONFIG_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
+#define MPU_CONFIG_HARDFLT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_CONFIG_NONE 0
//*****************************************************************************
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c
index f3c92f5..fc17880 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,15 +41,12 @@
#include <pcm.h>
#include <debug.h>
#include <interrupt.h>
+#include <wdt_a.h>
+#include <rtc_c.h>
#include <cpu.h>
-bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel)
-{
- return PCM_setCoreVoltageLevelWithTimeout(voltageLevel, 0);
-}
-
-bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
- uint32_t timeOut)
+static bool __PCM_setCoreVoltageLevelAdvanced(uint_fast8_t voltageLevel,
+ uint32_t timeOut, bool blocking)
{
uint8_t powerMode, bCurrentVoltageLevel;
uint32_t regValue;
@@ -69,31 +66,38 @@
while (bCurrentVoltageLevel != voltageLevel)
{
- regValue = PCM->rCTL0.r;
+ regValue = PCM->CTL0;
switch (PCM_getPowerState())
{
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
case PCM_AM_LDO_VCORE0:
- PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE1)
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1)
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LF_VCORE0:
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LDO_VCORE1:
- PCM->rCTL0.r = (PCM_KEY | (PCM_AM_LDO_VCORE0)
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0)
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
default:
ASSERT(false);
}
- while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+ if(blocking)
{
- if (boolTimeout && !(--timeOut))
- return false;
+ while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
+ {
+ if (boolTimeout && !(--timeOut))
+ return false;
+ }
+ }
+ else
+ {
+ return true;
}
bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
@@ -112,9 +116,21 @@
}
-bool PCM_setPowerMode(uint_fast8_t powerMode)
+
+bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel)
{
- return PCM_setPowerModeWithTimeout(powerMode, 0);
+ return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, true);
+}
+
+bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
+ uint32_t timeOut)
+{
+ return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, timeOut, true);
+}
+
+bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel)
+{
+ return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, false);
}
uint8_t PCM_getPowerMode(void)
@@ -176,7 +192,8 @@
}
}
-bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
+static bool __PCM_setPowerModeAdvanced(uint_fast8_t powerMode, uint32_t timeOut,
+bool blocking)
{
uint8_t bCurrentPowerMode, bCurrentPowerState;
uint32_t regValue;
@@ -200,30 +217,30 @@
/* Go through the while loop while we haven't achieved the power mode */
while (bCurrentPowerMode != powerMode)
{
- regValue = PCM->rCTL0.r;
+ regValue = PCM->CTL0;
switch (bCurrentPowerState)
{
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LF_VCORE0:
- PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE0
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
- PCM->rCTL0.r = (PCM_KEY | PCM_AM_LDO_VCORE1
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LDO_VCORE1:
{
if (powerMode == PCM_DCDC_MODE)
{
- PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE1
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else if (powerMode == PCM_LF_MODE)
{
- PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE1
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else
ASSERT(false);
@@ -233,12 +250,12 @@
{
if (powerMode == PCM_DCDC_MODE)
{
- PCM->rCTL0.r = (PCM_KEY | PCM_AM_DCDC_VCORE0
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else if (powerMode == PCM_LF_MODE)
{
- PCM->rCTL0.r = (PCM_KEY | PCM_AM_LF_VCORE0
- | (regValue & ~(PCMKEY_M | AMR_M)));
+ PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0
+ | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
} else
ASSERT(false);
@@ -248,12 +265,16 @@
ASSERT(false);
}
- while (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+ if (blocking)
{
- if (boolTimeout && !(--timeOut))
- return false;
+ while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
+ {
+ if (boolTimeout && !(--timeOut))
+ return false;
- }
+ }
+ } else
+ return true;
bCurrentPowerMode = PCM_getPowerMode();
bCurrentPowerState = PCM_getPowerState();
@@ -263,12 +284,24 @@
}
-bool PCM_setPowerState(uint_fast8_t powerState)
+bool PCM_setPowerMode(uint_fast8_t powerMode)
{
- return PCM_setPowerStateWithTimeout(powerState, 0);
+ return __PCM_setPowerModeAdvanced(powerMode, 0, true);
}
-bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
+bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode)
+{
+ return __PCM_setPowerModeAdvanced(powerMode, 0, false);
+}
+
+bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
+{
+ return __PCM_setPowerModeAdvanced(powerMode, timeOut, true);
+}
+
+static bool __PCM_setPowerStateAdvanced(uint_fast8_t powerState,
+ uint32_t timeout,
+ bool blocking)
{
uint8_t bCurrentPowerState;
bCurrentPowerState = PCM_getPowerState();
@@ -280,7 +313,7 @@
|| powerState == PCM_LPM0_LDO_VCORE0 || powerState == PCM_LPM0_LDO_VCORE1
|| powerState == PCM_LPM0_DCDC_VCORE0 || powerState == PCM_LPM0_DCDC_VCORE1
|| powerState == PCM_LPM3 || powerState == PCM_LPM35_VCORE0
- || powerState == PCM_LPM45);
+ || powerState == PCM_LPM45 || powerState == PCM_LPM4);
if (bCurrentPowerState == powerState)
return true;
@@ -288,55 +321,59 @@
switch (powerState)
{
case PCM_AM_LDO_VCORE0:
- return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
- && PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
+ return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+ && __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking));
case PCM_AM_LDO_VCORE1:
- return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
- && PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout));
+ return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+ && __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking));
case PCM_AM_DCDC_VCORE0:
- return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
- && PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
+ return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+ && __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking));
case PCM_AM_DCDC_VCORE1:
- return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
- && PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout));
+ return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+ && __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking));
case PCM_AM_LF_VCORE0:
- return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
- && PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
+ return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+ && __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking));
case PCM_AM_LF_VCORE1:
- return (PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
- && PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout));
+ return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+ && __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking));
case PCM_LPM0_LDO_VCORE0:
- if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
- || !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
+ if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+ || !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LDO_VCORE1:
- if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
- || !PCM_setPowerModeWithTimeout(PCM_LDO_MODE, timeout))
+ if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+ || !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_DCDC_VCORE0:
- if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
- || !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
+ if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+ || !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout,
+ blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_DCDC_VCORE1:
- if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
- || !PCM_setPowerModeWithTimeout(PCM_DCDC_MODE, timeout))
+ if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+ || !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout,
+ blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LF_VCORE0:
- if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE0, timeout)
- || !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
+ if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+ || !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM0_LF_VCORE1:
- if (!PCM_setCoreVoltageLevelWithTimeout(PCM_VCORE1, timeout)
- || !PCM_setPowerModeWithTimeout(PCM_LF_MODE, timeout))
+ if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+ || !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking))
break;
return PCM_gotoLPM0();
case PCM_LPM3:
return PCM_gotoLPM3();
+ case PCM_LPM4:
+ return PCM_gotoLPM4();
case PCM_LPM45:
return PCM_shutdownDevice(PCM_LPM45);
case PCM_LPM35_VCORE0:
@@ -350,36 +387,81 @@
}
+bool PCM_setPowerState(uint_fast8_t powerState)
+{
+ return __PCM_setPowerStateAdvanced(powerState, 0, true);
+}
+
+bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
+{
+ return __PCM_setPowerStateAdvanced(powerState, timeout, true);
+}
+
+bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState)
+{
+ return __PCM_setPowerStateAdvanced(powerState, 0, false);
+}
+
bool PCM_shutdownDevice(uint32_t shutdownMode)
{
- uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ? LPMR_12 : LPMR_10;
+ uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ?
+ PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
ASSERT(
shutdownMode == PCM_SHUTDOWN_PARTIAL
|| shutdownMode == PCM_SHUTDOWN_COMPLETE);
/* If a power transition is occuring, return false */
- if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+ if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
/* Initiating the shutdown */
- HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
- PCM->rCTL0.r = (PCM_KEY | shutdownModeBits
- | (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)));
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ PCM->CTL0 = (PCM_KEY | shutdownModeBits
+ | (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)));
CPU_wfi();
return true;
}
+bool PCM_gotoLPM4(void)
+{
+ /* Disabling RTC_C and WDT_A */
+ WDT_A_holdTimer();
+ RTC_C_holdClock();
+
+ /* LPM4 is just LPM3 with WDT_A/RTC_C disabled... */
+ return PCM_gotoLPM3();
+}
+
+bool PCM_gotoLPM4InterruptSafe(void)
+{
+ bool slHappenedCorrect;
+
+ /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
+ master interrupts are disabled and a WFI happens the WFI will
+ immediately exit. */
+ Interrupt_disableMaster();
+
+ slHappenedCorrect = PCM_gotoLPM4();
+
+ /* Enabling and Disabling Interrupts very quickly so that the
+ processor catches any pending interrupts */
+ Interrupt_enableMaster();
+ Interrupt_disableMaster();
+
+ return slHappenedCorrect;
+}
+
bool PCM_gotoLPM0(void)
{
-
/* If we are in the middle of a state transition, return false */
- if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+ if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
- HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
CPU_wfi();
@@ -388,7 +470,6 @@
bool PCM_gotoLPM0InterruptSafe(void)
{
-
bool slHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
@@ -412,11 +493,12 @@
uint_fast8_t currentPowerMode;
/* If we are in the middle of a state transition, return false */
- if (BITBAND_PERI(PCM->rCTL1.r, PMR_BUSY_OFS))
+ if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
/* If we are in the middle of a shutdown, return false */
- if ((PCM->rCTL0.r & LPMR_M) == LPMR_10 || (PCM->rCTL0.r & LPMR_M) == LPMR_12)
+ if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10
+ || (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
return false;
currentPowerMode = PCM_getPowerMode();
@@ -426,76 +508,78 @@
PCM_setPowerMode(PCM_LDO_MODE);
/* Clearing the SDR */
- PCM->rCTL0.r = (PCM->rCTL0.r & ~(PCMKEY_M | LPMR_M)) | PCM_KEY;
+ PCM->CTL0 = (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY;
/* Setting the sleep deep bit */
- HWREG32(SCS_BASE + OFS_SCB_SCR) |= (SCB_SCR_SLEEPDEEP);
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
CPU_wfi();
- HWREG32(SCS_BASE + OFS_SCB_SCR) &= ~(SCB_SCR_SLEEPDEEP);
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
return PCM_setPowerState(bCurrentPowerState);
}
bool PCM_gotoLPM3InterruptSafe(void)
{
- bool dslHappenedCorrect;
+ bool lpmHappenedCorrect;
/* Disabling master interrupts. In Cortex M, if an interrupt is enabled but
master interrupts are disabled and a WFI happens the WFI will
immediately exit. */
Interrupt_disableMaster();
- dslHappenedCorrect = PCM_gotoLPM3();
+ lpmHappenedCorrect = PCM_gotoLPM3();
/* Enabling and Disabling Interrupts very quickly so that the
processor catches any pending interrupts */
Interrupt_enableMaster();
Interrupt_disableMaster();
- return dslHappenedCorrect;
+ return lpmHappenedCorrect;
}
uint8_t PCM_getPowerState(void)
{
- return PCM->rCTL0.b.bCPM;
+ return (PCM->CTL0 | PCM_CTL0_CPM_MASK);
}
void PCM_enableRudeMode(void)
{
- PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M)) | PCM_KEY | FORCE_LPM_ENTRY;
+ PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK)) | PCM_KEY
+ | PCM_CTL1_FORCE_LPM_ENTRY;
}
void PCM_disableRudeMode(void)
{
- PCM->rCTL1.r = (PCM->rCTL1.r & ~(PCMKEY_M | FORCE_LPM_ENTRY)) | PCM_KEY;
+ PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK | PCM_CTL1_FORCE_LPM_ENTRY))
+ | PCM_KEY;
}
void PCM_enableInterrupt(uint32_t flags)
{
- PCM->rIE.r |= flags;
+ PCM->IE |= flags;
}
void PCM_disableInterrupt(uint32_t flags)
{
- PCM->rIE.r &= ~flags;
+ PCM->IE &= ~flags;
}
uint32_t PCM_getInterruptStatus(void)
{
- return PCM->rIFG.r;
+ return PCM->IFG;
}
uint32_t PCM_getEnabledInterruptStatus(void)
{
- return PCM_getInterruptStatus() & PCM->rIE.r;
+ return PCM_getInterruptStatus() & PCM->IE;
}
void PCM_clearInterruptFlag(uint32_t flags)
{
- PCM->rCLRIFG.r |= flags;
+ PCM->CLRIFG |= flags;
}
void PCM_registerInterrupt(void (*intHandler)(void))
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h
index 64bc9d5..70b2029 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pcm.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -80,6 +80,7 @@
#define PCM_LPM0_LF_VCORE0 0x18
#define PCM_LPM0_LF_VCORE1 0x19
#define PCM_LPM3 0x20
+#define PCM_LPM4 0x21
#define PCM_LPM35_VCORE0 0xC0
#define PCM_LPM45 0xA0
@@ -94,10 +95,10 @@
#define PCM_SHUTDOWN_PARTIAL PCM_LPM35_VCORE0
#define PCM_SHUTDOWN_COMPLETE PCM_LPM45
-#define PCM_DCDCERROR PCM_INTEN_EN_DCDC_ERROR
-#define PCM_AM_INVALIDTRANSITION PCM_INTEN_EN_AM_INVALID_TR
-#define PCM_SM_INVALIDCLOCK PCM_INTEN_EN_SM_INVALID_CLK
-#define PCM_SM_INVALIDTRANSITION PCM_INTEN_EN_SM_INVALID_TR
+#define PCM_DCDCERROR PCM_IE_DCDC_ERROR_IE
+#define PCM_AM_INVALIDTRANSITION PCM_IE_AM_INVALID_TR_IE
+#define PCM_SM_INVALIDCLOCK PCM_IE_LPM_INVALID_CLK_IE
+#define PCM_SM_INVALIDTRANSITION PCM_IE_LPM_INVALID_TR_IE
//*****************************************************************************
//
@@ -174,6 +175,29 @@
//******************************************************************************
//
+//! Sets the core voltage level (Vcore). This function is similar to
+//! PCM_setCoreVoltageLevel, however there are no polling flags to ensure
+//! a state has changed. Execution is returned back to the calling program
+// and it is up to the user to ensure proper state transitions happen
+//! correctly. For MSP432, changing into different power modes/states
+//! require very specific logic. This function will initiate only one state
+//! transition and then return. It is up to the user to keep calling this
+//! function until the correct power state has been achieved.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param voltageLevel The voltage level to be shifted to.
+//! - \b PCM_VCORE0,
+//! - \b PCM_VCORE1
+//!
+//! \return true if voltage level set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel);
+
+//******************************************************************************
+//
//! Switches between power modes. This function will take care of all
//! power state transitions needed to shift between power modes. Note for
//! changing to DCDC mode, specific hardware considerations are required.
@@ -219,6 +243,30 @@
//******************************************************************************
//
+//! Sets the core voltage level (Vcore). This function is similar to
+//! PCM_setPowerMode, however there are no polling flags to ensure
+//! a state has changed. Execution is returned back to the calling program
+// and it is up to the user to ensure proper state transitions happen
+//! correctly. For MSP432, changing into different power modes/states
+//! require very specific logic. This function will initiate only one state
+//! transition and then return. It is up to the user to keep calling this
+//! function until the correct power state has been achieved.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param powerMode The voltage modes to be shifted to. Valid values are:
+//! - \b PCM_LDO_MODE,
+//! - \b PCM_DCDC_MODE,
+//! - \b PCM_LF_MODE
+//!
+//! \return true if power mode change was initiated, false otherwise
+//
+//******************************************************************************
+extern bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode);
+
+//******************************************************************************
+//
//! Returns the current powers state of the system see the \b PCM_setPowerState
//! function for specific information about the modes.
//!
@@ -231,8 +279,8 @@
//******************************************************************************
//
//! Switches between power states. This is a convenience function that combines
-//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
-//! the sleep/LPM3/shutdown functions.
+//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as
+//! the LPM0/LPM3 functions.
//!
//! Refer to the device specific data sheet for specifics about power states.
//!
@@ -251,6 +299,7 @@
//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
//! - \b PCM_LPM3, [LPM3]
//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
+//! - \b PCM_LPM4, [LPM4]
//! - \b PCM_LPM45, [LPM4.5]
//!
//! \return true if power state is set, false otherwise.
@@ -261,10 +310,10 @@
//******************************************************************************
//
//! Switches between power states. This is a convenience function that combines
-//! the functionality of PCMSetPowerMode and PCMSetCoreVoltageLevel as well as
+//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as
//! the LPM modes.
//!
-//! This function is similar to PCMChangePowerState, however a timeout
+//! This function is similar to PCM_setPowerState, however a timeout
//! mechanism is used.
//!
//! Refer to the device specific data sheet for specifics about power states.
@@ -284,6 +333,7 @@
//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
//! - \b PCM_LPM3, [LPM3]
//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
+//! - \b PCM_LPM4, [LPM4]
//! - \b PCM_LPM45, [LPM4.5]
//!
//! \param timeout Number of loop iterations to timeout when checking for
@@ -314,6 +364,42 @@
//******************************************************************************
//
+//! Sets the power state of the part. This function is similar to
+//! PCM_getPowerState, however there are no polling flags to ensure
+//! a state has changed. Execution is returned back to the calling program
+// and it is up to the user to ensure proper state transitions happen
+//! correctly. For MSP432, changing into different power modes/states
+//! require very specific logic. This function will initiate only one state
+//! transition and then return. It is up to the user to keep calling this
+//! function until the correct power state has been achieved.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param powerState The voltage modes to be shifted to. Valid values are:
+//! - \b PCM_AM_LDO_VCORE0, [Active Mode, LDO, VCORE0]
+//! - \b PCM_AM_LDO_VCORE1, [Active Mode, LDO, VCORE1]
+//! - \b PCM_AM_DCDC_VCORE0, [Active Mode, DCDC, VCORE0]
+//! - \b PCM_AM_DCDC_VCORE1, [Active Mode, DCDC, VCORE1]
+//! - \b PCM_AM_LF_VCORE0, [Active Mode, Low Frequency, VCORE0]
+//! - \b PCM_AM_LF_VCORE1, [Active Mode, Low Frequency, VCORE1]
+//! - \b PCM_LPM0_LDO_VCORE0, [LMP0, LDO, VCORE0]
+//! - \b PCM_LPM0_LDO_VCORE1, [LMP0, LDO, VCORE1]
+//! - \b PCM_LPM0_DCDC_VCORE0, [LMP0, DCDC, VCORE0]
+//! - \b PCM_LPM0_DCDC_VCORE1, [LMP0, DCDC, VCORE1]
+//! - \b PCM_LPM0_LF_VCORE0, [LMP0, Low Frequency, VCORE0]
+//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1]
+//! - \b PCM_LPM3, [LPM3]
+//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0]
+//! - \b PCM_LPM45, [LPM4.5]
+//!
+//! \return true if power state change was initiated, false otherwise
+//
+//******************************************************************************
+extern bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState);
+
+//******************************************************************************
+//
//! Transitions the device into LPM3.5/LPM4.5 mode.
//!
//! Refer to the device specific data sheet for specifics about shutdown modes.
@@ -368,7 +454,7 @@
//! Transitions the device into LPM0 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to sleep, however does not want
-//! to go to "miss" any interrupts due to the fact that going to DSL is not
+//! to go to "miss" any interrupts due to the fact that going to LPM0 is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
@@ -384,7 +470,7 @@
//! Transitions the device into LPM3 while maintaining a safe
//! interrupt handling mentality. This function is meant to be used in
//! situations where the user wants to go to LPM3, however does not want
-//! to go to "miss" any interrupts due to the fact that going to DSL is not
+//! to go to "miss" any interrupts due to the fact that going to LPM3 is not
//! an atomic operation. This function will modify the PRIMASK and on exit of
//! the program the master interrupts will be disabled.
//!
@@ -400,6 +486,36 @@
//******************************************************************************
//
+//! Transitions the device into LPM4. LPM4 is the exact same with LPM3, just
+//! with RTC_C and WDT_A disabled. When waking up, RTC_C and WDT_A will remain
+//! disabled until reconfigured by the user.
+//!
+//! \return false if sleep state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM4(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM4 while maintaining a safe
+//! interrupt handling mentality. This function is meant to be used in
+//! situations where the user wants to go to LPM4, however does not want
+//! to go to "miss" any interrupts due to the fact that going to LPM4 is not
+//! an atomic operation. This function will modify the PRIMASK and on exit of
+//! the program the master interrupts will be disabled.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//! Note that since LPM3 cannot be entered from a DCDC power modes, the
+//! power mode is first switched to LDO operation (if in DCDC mode), the deep
+//! sleep is entered, and the DCDC mode is restored on wake up.
+//!
+//! \return false if sleep state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM4InterruptSafe(void);
+
+//******************************************************************************
+//
//! Enables "rude mode" entry into LPM3 and shutdown modes. With this mode
//! enabled, an entry into shutdown or LPM3 will occur even if there are
//! clock systems active. The system will forcibly turn off all clock/systems
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c
index 98b4530..c1568b3 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -36,21 +36,22 @@
* --/COPYRIGHT--*/
#include <debug.h>
#include <pmap.h>
+#include <hw_memmap.h>
void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
uint8_t numberOfPorts, uint8_t portMapReconfigure)
{
- uint16_t i;
+ uint_fast16_t i;
ASSERT(
(portMapReconfigure == PMAP_ENABLE_RECONFIGURATION)
|| (portMapReconfigure == PMAP_DISABLE_RECONFIGURATION));
//Get write-access to port mapping registers:
- PMAP->rKEYID = PMAP_KEYID_VAL;
+ PMAP->KEYID = PMAP_KEYID_VAL;
//Enable/Disable reconfiguration during runtime
- PMAP->rCTL.r = (PMAP->rCTL.r & ~PMAPRECFG) | portMapReconfigure;
+ PMAP->CTL = (PMAP->CTL & ~PMAP_CTL_PRECFG) | portMapReconfigure;
//Configure Port Mapping:
@@ -60,6 +61,6 @@
}
//Disable write-access to port mapping registers:
- PMAP->rKEYID = 0;
+ PMAP->KEYID = 0;
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h
index c3f8052..51b872f 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pmap.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -64,7 +64,7 @@
//as the portMapReconfigure parameter.
//
//*****************************************************************************
-#define PMAP_ENABLE_RECONFIGURATION PMAPRECFG
+#define PMAP_ENABLE_RECONFIGURATION PMAP_CTL_PRECFG
#define PMAP_DISABLE_RECONFIGURATION 0x00
//*****************************************************************************
@@ -73,13 +73,13 @@
//as the portMapReconfigure parameter.
//
//*****************************************************************************
-#define P1MAP OFS_P1MAP01
-#define P2MAP OFS_P2MAP01
-#define P3MAP OFS_P3MAP01
-#define P4MAP OFS_P4MAP01
-#define P5MAP OFS_P5MAP01
-#define P6MAP OFS_P6MAP01
-#define P7MAP OFS_P7MAP01
+#define PMAP_P1MAP ((uint32_t)P1MAP - PMAP_BASE)
+#define PMAP_P2MAP ((uint32_t)P2MAP - PMAP_BASE)
+#define PMAP_P3MAP ((uint32_t)P3MAP - PMAP_BASE)
+#define PMAP_P4MAP ((uint32_t)P4MAP - PMAP_BASE)
+#define PMAP_P5MAP ((uint32_t)P5MAP - PMAP_BASE)
+#define PMAP_P6MAP ((uint32_t)P6MAP - PMAP_BASE)
+#define PMAP_P7MAP ((uint32_t)P7MAP - PMAP_BASE)
//*****************************************************************************
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c
index 249072e..dbd8195 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,12 +45,32 @@
static void __PSSUnlock()
{
- PSS->rKEY.r = PSS_KEY_VALUE;
+ PSS->KEY = PSS_KEY_VALUE;
}
static void __PSSLock()
{
- PSS->rKEY.r = 0;
+ PSS->KEY = 0;
+}
+
+
+void PSS_enableForcedDCDCOperation(void)
+{
+ __PSSUnlock();
+
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 1;
+
+ __PSSLock();
+}
+
+void PSS_disableForcedDCDCOperation(void)
+{
+ __PSSUnlock();
+
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 0;
+
+ __PSSLock();
+
}
void PSS_enableHighSidePinToggle(bool activeLow)
@@ -58,11 +78,11 @@
__PSSUnlock();
if (activeLow)
- PSS->rCTL0.r |= (SVMHOE | SVMHOUTPOLAL);
+ PSS->CTL0 |= (PSS_CTL0_SVMHOE | PSS_CTL0_SVMHOUTPOLAL);
else
{
- BITBAND_PERI(PSS->rCTL0.r, SVMHOUTPOLAL_OFS) = 0;
- BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 1;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOUTPOLAL_OFS) = 0;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 1;
}
__PSSLock();
@@ -72,7 +92,7 @@
{
__PSSUnlock();
- BITBAND_PERI(PSS->rCTL0.r, SVMHOE_OFS) = 0;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 0;
__PSSLock();
}
@@ -81,7 +101,7 @@
{
__PSSUnlock();
- BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 0;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 0;
__PSSLock();
}
@@ -90,7 +110,7 @@
{
__PSSUnlock();
- BITBAND_PERI(PSS->rCTL0.r, SVSMHOFF_OFS) = 1;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 1;
__PSSLock();
}
@@ -100,16 +120,16 @@
__PSSUnlock();
if (powerMode == PSS_FULL_PERFORMANCE_MODE)
- BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 0;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 0;
else
- BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS) = 1;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 1;
__PSSLock();
}
uint_fast8_t PSS_getHighSidePerformanceMode(void)
{
- if (BITBAND_PERI(PSS->rCTL0.r, SVSMHLP_OFS))
+ if (BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS))
return PSS_NORMAL_PERFORMANCE_MODE;
else
return PSS_FULL_PERFORMANCE_MODE;
@@ -119,7 +139,7 @@
{
__PSSUnlock();
- BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 1;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 1;
__PSSLock();
}
@@ -128,7 +148,7 @@
{
__PSSUnlock();
- BITBAND_PERI(PSS->rCTL0.r, SVSMHS_OFS) = 0;
+ BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 0;
__PSSLock();
}
@@ -139,80 +159,41 @@
ASSERT(!(triggerVoltage & 0xF8))
- PSS->rCTL0.b.bSVSMHTH = triggerVoltage & 0x07;
+ PSS->CTL0 &= ~PSS_CTL0_SVSMHTH_MASK;
+ PSS->CTL0 |= (triggerVoltage & 0x07) << PSS_CTL0_SVSMHTH_OFS;
__PSSLock();
}
uint_fast8_t PSS_getHighSideVoltageTrigger(void)
{
- return PSS->rCTL0.b.bSVSMHTH;
+ return (uint_fast8_t)((PSS->CTL0 & PSS_CTL0_SVSMHTH_MASK)
+ >> PSS_CTL0_SVSMHTH_OFS);
}
-
-void PSS_enableLowSide(void)
-{
- __PSSUnlock();
-
- BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 0;
-
- __PSSLock();
-}
-
-void PSS_disableLowSide(void)
-{
- __PSSUnlock();
-
- BITBAND_PERI(PSS->rCTL0.r, SVSLOFF_OFS) = 1;
-
- __PSSLock();
-}
-
-
-void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode)
-{
- __PSSUnlock();
-
- if (ui8PowerMode == PSS_FULL_PERFORMANCE_MODE)
- BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 0;
- else
- BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS) = 1;
-
- __PSSLock();
-}
-
-uint_fast8_t PSS_getLowSidePerformanceMode(void)
-{
- if (BITBAND_PERI(PSS->rCTL0.r, SVSLLP_OFS))
- return PSS_NORMAL_PERFORMANCE_MODE;
- else
- return PSS_FULL_PERFORMANCE_MODE;
-}
-
-
void PSS_enableInterrupt(void)
{
__PSSUnlock();
- BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 1;
+ BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 1;
__PSSLock();
}
void PSS_disableInterrupt(void)
{
__PSSUnlock();
- BITBAND_PERI(PSS->rIE.r,SVSMHIE_OFS) = 0;
+ BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 0;
__PSSLock();
}
uint32_t PSS_getInterruptStatus(void)
{
- return PSS->rIFG.r;
+ return PSS->IFG;
}
void PSS_clearInterruptFlag(void)
{
__PSSUnlock();
- BITBAND_PERI(PSS->rCLRIFG.r,CLRSVSMHIFG_OFS) = 0;
+ BITBAND_PERI(PSS->CLRIFG,PSS_CLRIFG_CLRSVSMHIFG_OFS) = 0;
__PSSLock();
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h
index 5638f4f..da23222 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/pss.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -64,9 +64,9 @@
// Control specific variables
//
//*****************************************************************************
-#define PSS_KEY_VALUE 0x0000695A
+#define PSS_KEY_VALUE PSS_KEY_KEY_VAL
-#define PSS_SVSMH SVSMHIE
+#define PSS_SVSMH PSS_IE_SVSMHIE
#define PSS_FULL_PERFORMANCE_MODE 0x01
#define PSS_NORMAL_PERFORMANCE_MODE 0x00
@@ -205,51 +205,6 @@
//*****************************************************************************
//
-//! Enables low side voltage supervisor/monitor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-extern void PSS_enableLowSide(void);
-
-//*****************************************************************************
-//
-//! Disables low side voltage supervisor/monitor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-extern void PSS_disableLowSide(void);
-
-//*****************************************************************************
-//
-//! Sets the performance mode of the high side regulator. Full performance
-//! mode allows for the best response times while normal performance mode is
-//! optimized for the lowest possible current consumption.
-//!
-//! \param ui8PowerMode is the performance mode to set. Valid values are one of
-//! the following:
-//! - \b PSS_FULL_PERFORMANCE_MODE,
-//! - \b PSS_NORMAL_PERFORMANCE_MODE
-//!
-//! \return None.
-//
-//*****************************************************************************
-extern void PSS_setLowSidePerformanceMode(uint_fast8_t ui8PowerMode);
-
-//*****************************************************************************
-//
-//! Gets the performance mode of the low side voltage regulator. Refer to the
-//! user's guide for specific information about information about the different
-//! performance modes.
-//!
-//! \return Performance mode of the voltage regulator
-//
-//*****************************************************************************
-extern uint_fast8_t PSS_getLowSidePerformanceMode(void);
-
-//*****************************************************************************
-//
//! Enables the power supply system interrupt source.
//!
//! \return None.
@@ -284,6 +239,32 @@
//*****************************************************************************
extern void PSS_clearInterruptFlag(void);
+
+//*****************************************************************************
+//
+//! Enables the "forced" mode of the DCDC regulator. In this mode, the fail
+//! safe mechanism that disables the regulator to LDO mode when the supply
+//! voltage falls below the minimum supply voltage required for DCDC operation
+//! is turned off.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableForcedDCDCOperation(void);
+
+
+//*****************************************************************************
+//
+//! Disables the "forced" mode of the DCDC regulator. In this mode, the fail
+//! safe mechanism that disables the regulator to LDO mode when the supply
+//! voltage falls below the minimum supply voltage required for DCDC operation
+//! is turned on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableForcedDCDCOperation(void);
+
//*****************************************************************************
//
//! Registers an interrupt handler for the power supply system interrupt.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c
index cc3bd0e..509f4d4 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,76 +41,76 @@
{
ASSERT(referenceVoltageSelect <= REF_A_VREF2_5V);
- REF_A->rCTL0.r = (REF_A->rCTL0.r & ~REFVSEL_3) | referenceVoltageSelect;
+ REF_A->CTL0 = (REF_A->CTL0 & ~REF_A_CTL0_VSEL_3) | referenceVoltageSelect;
}
void REF_A_disableTempSensor(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 1;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 1;
}
void REF_A_enableTempSensor(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFTCOFF_OFS) = 0;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 0;
}
void REF_A_enableReferenceVoltageOutput(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 1;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 1;
}
void REF_A_disableReferenceVoltageOutput(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFOUT_OFS) = 0;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 0;
}
void REF_A_enableReferenceVoltage(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 1;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 1;
}
void REF_A_disableReferenceVoltage(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFON_OFS) = 0;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 0;
}
uint_fast8_t REF_A_getBandgapMode(void)
{
- return (REF_A->rCTL0.r & BGMODE);
+ return (REF_A->CTL0 & REF_A_CTL0_BGMODE);
}
bool REF_A_isBandgapActive(void)
{
- return BITBAND_PERI(REF_A->rCTL0.r,REFBGACT_OFS);
+ return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGACT_OFS);
}
bool REF_A_isRefGenBusy(void)
{
- return BITBAND_PERI(REF_A->rCTL0.r,REFGENBUSY_OFS);
+ return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENBUSY_OFS);
}
bool REF_A_isRefGenActive(void)
{
- return BITBAND_PERI(REF_A->rCTL0.r,REFGENACT_OFS);
+ return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENACT_OFS);
}
bool REF_A_getBufferedBandgapVoltageStatus(void)
{
- return BITBAND_PERI(REF_A->rCTL0.r,REFBGRDY_OFS);
+ return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGRDY_OFS);
}
bool REF_A_getVariableReferenceVoltageStatus(void)
{
- return BITBAND_PERI(REF_A->rCTL0.r,REFGENRDY_OFS);
+ return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENRDY_OFS);
}
void REF_A_setReferenceVoltageOneTimeTrigger(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFGENOT_OFS) = 1;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENOT_OFS) = 1;
}
void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void)
{
- BITBAND_PERI(REF_A->rCTL0.r,REFBGOT_OFS) = 1;
+ BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGOT_OFS) = 1;
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h
index e9fe91a..2585ec3 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/ref_a.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -65,9 +65,9 @@
//in the referenceVoltageSelect parameter.
//
//*****************************************************************************
-#define REF_A_VREF1_2V REFVSEL_0
-#define REF_A_VREF1_45V REFVSEL_1
-#define REF_A_VREF2_5V REFVSEL_3
+#define REF_A_VREF1_2V REF_A_CTL0_VSEL_0
+#define REF_A_VREF1_45V REF_A_CTL0_VSEL_1
+#define REF_A_VREF2_5V REF_A_CTL0_VSEL_3
//*****************************************************************************
//
@@ -75,7 +75,7 @@
//
//*****************************************************************************
#define REF_A_STATICMODE 0x0
-#define REF_A_SAMPLEMODE BGMODE
+#define REF_A_SAMPLEMODE REF_A_CTL0_BGMODE
//*****************************************************************************
//
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c
index 6dbe20b..71b6960 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,61 +39,61 @@
void ResetCtl_initiateSoftReset(void)
{
- RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_SOFT_RESET);
+ RSTCTL->RESET_REQ |= (RESET_KEY | RESET_SOFT_RESET);
}
void ResetCtl_initiateSoftResetWithSource(uint32_t source)
{
- RSTCTL->rSOFTRESET_SET.r |= (source);
+ RSTCTL->SOFTRESET_SET |= (source);
}
uint32_t ResetCtl_getSoftResetSource(void)
{
- return RSTCTL->rSOFTRESET_STAT.r;
+ return RSTCTL->SOFTRESET_STAT;
}
void ResetCtl_clearSoftResetSource(uint32_t mask)
{
- RSTCTL->rSOFTRESET_CLR.r |= mask;
+ RSTCTL->SOFTRESET_CLR |= mask;
}
void ResetCtl_initiateHardReset(void)
{
- RSTCTL->rRESET_REQ.r |= (RESET_KEY | RESET_HARD_RESET);
+ RSTCTL->RESET_REQ |= (RESET_KEY | RESET_HARD_RESET);
}
void ResetCtl_initiateHardResetWithSource(uint32_t source)
{
- RSTCTL->rHARDRESET_SET.r |= (source);
+ RSTCTL->HARDRESET_SET |= (source);
}
uint32_t ResetCtl_getHardResetSource(void)
{
- return RSTCTL->rHARDRESET_STAT.r;
+ return RSTCTL->HARDRESET_STAT;
}
void ResetCtl_clearHardResetSource(uint32_t mask)
{
- RSTCTL->rHARDRESET_CLR.r |= mask;
+ RSTCTL->HARDRESET_CLR |= mask;
}
uint32_t ResetCtl_getPSSSource(void)
{
- return RSTCTL->rPSSRESET_STAT.r;
+ return RSTCTL->PSSRESET_STAT;
}
void ResetCtl_clearPSSFlags(void)
{
- RSTCTL->rPSSRESET_CLR.r |= RSTCTL_PSSRESET_CLR_CLR;
+ RSTCTL->PSSRESET_CLR |= RSTCTL_PSSRESET_CLR_CLR;
}
uint32_t ResetCtl_getPCMSource(void)
{
- return RSTCTL->rPCMRESET_STAT.r;
+ return RSTCTL->PCMRESET_STAT;
}
void ResetCtl_clearPCMFlags(void)
{
- RSTCTL->rPCMRESET_CLR.r |= RSTCTL_PCMRESET_CLR_CLR;
+ RSTCTL->PCMRESET_CLR |= RSTCTL_PCMRESET_CLR_CLR;
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h
index c8d060c..0aa3067 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/reset.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -86,11 +86,10 @@
#define RESET_VCCDET RSTCTL_PSSRESET_CLR_BGREF
#define RESET_SVSH_TRIP RSTCTL_PSSRESET_CLR_SVSMH
-#define RESET_SVSL_TRIP RSTCTL_PSSRESET_CLR_SVSL
#define RESET_BGREF_BAD RSTCTL_PSSRESET_CLR_BGREF
-#define RESET_SD0 RSTCTL_PCMRESET_CLR_LPM35
-#define RESET_SD1 RSTCTL_PCMRESET_CLR_LPM45
+#define RESET_LPM35 RSTCTL_PCMRESET_CLR_LPM35
+#define RESET_LPM45 RSTCTL_PCMRESET_CLR_LPM45
//*****************************************************************************
//
@@ -291,7 +290,6 @@
//! \return Bitwise OR of any of the following values:
//! - RESET_VCCDET,
//! - RESET_SVSH_TRIP,
-//! - RESET_SVSL_TRIP,
//! - RESET_BGREF_BAD
//
//*****************************************************************************
@@ -311,8 +309,8 @@
//! Indicates the last cause of a power-on reset (POR) due to PCM operation.
//!
//! \return Bitwise OR of any of the following values:
-//! - RESET_SD0,
-//! - RESET_SD1
+//! - RESET_LPM35,
+//! - RESET_LPM45
//
//*****************************************************************************
extern uint32_t ResetCtl_getPCMSource(void);
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h
index 8fae525..c5285d2 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,6 +34,16 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
+// TI Information - Selective Disclosure
+//
+//*****************************************************************************
+//
+
#ifndef __ROM_H__
#define __ROM_H__
@@ -1631,8 +1641,9 @@
#endif
#if defined(TARGET_IS_MSP432P4XX)
#define ROM_Timer_A_getCaptureCompareInterruptStatus \
- (( (*)(, \
- ))ROM_TIMER_ATABLE[22])
+ ((uint32_t (*)(uint32_t timer, \
+ uint_fast16_t captureCompareRegister, \
+ uint_fast16_t mask))ROM_TIMER_ATABLE[22])
#endif
#if defined(TARGET_IS_MSP432P4XX)
#define ROM_Timer_A_getCaptureCompareEnabledInterruptStatus \
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h
index 5f654c8..78c3725 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rom_map.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,6 +34,17 @@
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* --/COPYRIGHT--*/
+//*****************************************************************************
+//
+// rom_map.h - Macros to facilitate calling functions in the ROM when they are
+// available and in flash otherwise.
+//
+// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
+// TI Information - Selective Disclosure
+//
+//
+//*****************************************************************************
+
#ifndef __ROM_MAP_H__
#define __ROM_MAP_H__
@@ -405,6 +416,13 @@
#define MAP_AES256_unregisterInterrupt \
AES256_unregisterInterrupt
#endif
+#ifdef ROM_AES256_getInterruptFlagStatus
+#define MAP_AES256_getInterruptFlagStatus \
+ ROM_AES256_getInterruptFlagStatus
+#else
+#define MAP_AES256_getInterruptFlagStatus \
+ AES256_getInterruptFlagStatus
+#endif
//*****************************************************************************
//
@@ -850,6 +868,13 @@
#define MAP_CS_setExternalClockSourceFrequency \
CS_setExternalClockSourceFrequency
#endif
+#ifdef ROM_CS_setDCOExternalResistorCalibration
+#define MAP_CS_setDCOExternalResistorCalibration \
+ ROM_CS_setDCOExternalResistorCalibration
+#else
+#define MAP_CS_setDCOExternalResistorCalibration \
+ CS_setDCOExternalResistorCalibration
+#endif
//*****************************************************************************
//
@@ -1240,6 +1265,69 @@
#define MAP_FlashCtl_unregisterInterrupt \
FlashCtl_unregisterInterrupt
#endif
+#ifdef ROM___FlashCtl_remaskData8Post
+#define MAP___FlashCtl_remaskData8Post \
+ ROM___FlashCtl_remaskData8Post
+#else
+#define MAP___FlashCtl_remaskData8Post \
+ __FlashCtl_remaskData8Post
+#endif
+#ifdef ROM___FlashCtl_remaskData8Pre
+#define MAP___FlashCtl_remaskData8Pre \
+ ROM___FlashCtl_remaskData8Pre
+#else
+#define MAP___FlashCtl_remaskData8Pre \
+ __FlashCtl_remaskData8Pre
+#endif
+#ifdef ROM___FlashCtl_remaskData32Pre
+#define MAP___FlashCtl_remaskData32Pre \
+ ROM___FlashCtl_remaskData32Pre
+#else
+#define MAP___FlashCtl_remaskData32Pre \
+ __FlashCtl_remaskData32Pre
+#endif
+#ifdef ROM___FlashCtl_remaskData32Post
+#define MAP___FlashCtl_remaskData32Post \
+ ROM___FlashCtl_remaskData32Post
+#else
+#define MAP___FlashCtl_remaskData32Post \
+ __FlashCtl_remaskData32Post
+#endif
+#ifdef ROM___FlashCtl_remaskBurstDataPre
+#define MAP___FlashCtl_remaskBurstDataPre \
+ ROM___FlashCtl_remaskBurstDataPre
+#else
+#define MAP___FlashCtl_remaskBurstDataPre \
+ __FlashCtl_remaskBurstDataPre
+#endif
+#ifdef ROM___FlashCtl_remaskBurstDataPost
+#define MAP___FlashCtl_remaskBurstDataPost \
+ ROM___FlashCtl_remaskBurstDataPost
+#else
+#define MAP___FlashCtl_remaskBurstDataPost \
+ __FlashCtl_remaskBurstDataPost
+#endif
+#ifdef ROM_FlashCtl_initiateSectorErase
+#define MAP_FlashCtl_initiateSectorErase \
+ ROM_FlashCtl_initiateSectorErase
+#else
+#define MAP_FlashCtl_initiateSectorErase \
+ FlashCtl_initiateSectorErase
+#endif
+#ifdef ROM_FlashCtl_initiateMassErase
+#define MAP_FlashCtl_initiateMassErase \
+ ROM_FlashCtl_initiateMassErase
+#else
+#define MAP_FlashCtl_initiateMassErase \
+ FlashCtl_initiateMassErase
+#endif
+#ifdef ROM_FlashCtl_getMemoryInfo
+#define MAP_FlashCtl_getMemoryInfo \
+ ROM_FlashCtl_getMemoryInfo
+#else
+#define MAP_FlashCtl_getMemoryInfo \
+ FlashCtl_getMemoryInfo
+#endif
//*****************************************************************************
//
@@ -1748,6 +1836,13 @@
#define MAP_I2C_unregisterInterrupt \
I2C_unregisterInterrupt
#endif
+#ifdef ROM_I2C_slaveSendNAK
+#define MAP_I2C_slaveSendNAK \
+ ROM_I2C_slaveSendNAK
+#else
+#define MAP_I2C_slaveSendNAK \
+ I2C_slaveSendNAK
+#endif
//*****************************************************************************
//
@@ -1873,6 +1968,20 @@
#define MAP_Interrupt_registerInterrupt \
Interrupt_registerInterrupt
#endif
+#ifdef ROM_Interrupt_unregisterInterrupt
+#define MAP_Interrupt_unregisterInterrupt \
+ ROM_Interrupt_unregisterInterrupt
+#else
+#define MAP_Interrupt_unregisterInterrupt \
+ Interrupt_unregisterInterrupt
+#endif
+#ifdef ROM_Interrupt_unpendInterrupt
+#define MAP_Interrupt_unpendInterrupt \
+ ROM_Interrupt_unpendInterrupt
+#else
+#define MAP_Interrupt_unpendInterrupt \
+ Interrupt_unpendInterrupt
+#endif
//*****************************************************************************
//
@@ -2123,6 +2232,41 @@
#define MAP_PCM_unregisterInterrupt \
PCM_unregisterInterrupt
#endif
+#ifdef ROM_PCM_setCoreVoltageLevelNonBlocking
+#define MAP_PCM_setCoreVoltageLevelNonBlocking \
+ ROM_PCM_setCoreVoltageLevelNonBlocking
+#else
+#define MAP_PCM_setCoreVoltageLevelNonBlocking \
+ PCM_setCoreVoltageLevelNonBlocking
+#endif
+#ifdef ROM_PCM_setPowerModeNonBlocking
+#define MAP_PCM_setPowerModeNonBlocking \
+ ROM_PCM_setPowerModeNonBlocking
+#else
+#define MAP_PCM_setPowerModeNonBlocking \
+ PCM_setPowerModeNonBlocking
+#endif
+#ifdef ROM_PCM_setPowerStateNonBlocking
+#define MAP_PCM_setPowerStateNonBlocking \
+ ROM_PCM_setPowerStateNonBlocking
+#else
+#define MAP_PCM_setPowerStateNonBlocking \
+ PCM_setPowerStateNonBlocking
+#endif
+#ifdef ROM_PCM_gotoLPM4
+#define MAP_PCM_gotoLPM4 \
+ ROM_PCM_gotoLPM4
+#else
+#define MAP_PCM_gotoLPM4 \
+ PCM_gotoLPM4
+#endif
+#ifdef ROM_PCM_gotoLPM4InterruptSafe
+#define MAP_PCM_gotoLPM4InterruptSafe \
+ ROM_PCM_gotoLPM4InterruptSafe
+#else
+#define MAP_PCM_gotoLPM4InterruptSafe \
+ PCM_gotoLPM4InterruptSafe
+#endif
//*****************************************************************************
//
@@ -2156,34 +2300,6 @@
#define MAP_PSS_disableHighSidePinToggle \
PSS_disableHighSidePinToggle
#endif
-#ifdef ROM_setLowSidePerformanceMode
-#define MAP_PSS_setLowSidePerformanceMode \
- ROM_PSS_setLowSidePerformanceMode
-#else
-#define MAP_PSS_setLowSidePerformanceMode \
- PSS_setLowSidePerformanceMode
-#endif
-#ifdef ROM_getLowSidePerformanceMode
-#define MAP_PSS_getLowSidePerformanceMode \
- ROM_PSS_getLowSidePerformanceMode
-#else
-#define MAP_PSS_getLowSidePerformanceMode \
- PSS_getLowSidePerformanceMode
-#endif
-#ifdef ROM_PSS_disableLowSide
-#define MAP_PSS_disableLowSide \
- ROM_PSS_disableLowSide
-#else
-#define MAP_PSS_disableLowSide \
- PSS_disableLowSide
-#endif
-#ifdef ROM_PSS_enableLowSide
-#define MAP_PSS_enableLowSide \
- ROM_PSS_enableLowSide
-#else
-#define MAP_PSS_enableLowSide \
- PSS_enableLowSide
-#endif
#ifdef ROM_PSS_enableHighSide
#define MAP_PSS_enableHighSide \
ROM_PSS_enableHighSide
@@ -2282,6 +2398,20 @@
#define MAP_PSS_unregisterInterrupt \
PSS_unregisterInterrupt
#endif
+#ifdef ROM_PSS_enableForcedDCDCOperation
+#define MAP_PSS_enableForcedDCDCOperation \
+ ROM_PSS_enableForcedDCDCOperation
+#else
+#define MAP_PSS_enableForcedDCDCOperation \
+ PSS_enableForcedDCDCOperation
+#endif
+#ifdef ROM_PSS_disableForcedDCDCOperation
+#define MAP_PSS_disableForcedDCDCOperation \
+ ROM_PSS_disableForcedDCDCOperation
+#else
+#define MAP_PSS_disableForcedDCDCOperation \
+ PSS_disableForcedDCDCOperation
+#endif
//*****************************************************************************
//
@@ -2886,6 +3016,27 @@
#define MAP_SysCtl_getTempCalibrationConstant \
SysCtl_getTempCalibrationConstant
#endif
+#ifdef ROM_SysCtl_enableGlitchFilter
+#define MAP_SysCtl_enableGlitchFilter \
+ ROM_SysCtl_enableGlitchFilter
+#else
+#define MAP_SysCtl_enableGlitchFilter \
+ SysCtl_enableGlitchFilter
+#endif
+#ifdef ROM_SysCtl_disableGlitchFilter
+#define MAP_SysCtl_disableGlitchFilter \
+ ROM_SysCtl_disableGlitchFilter
+#else
+#define MAP_SysCtl_disableGlitchFilter \
+ SysCtl_disableGlitchFilter
+#endif
+#ifdef ROM_SysCtl_getTLVInfo
+#define MAP_SysCtl_getTLVInfo \
+ ROM_SysCtl_getTLVInfo
+#else
+#define MAP_SysCtl_getTLVInfo \
+ SysCtl_getTLVInfo
+#endif
//*****************************************************************************
//
@@ -3143,6 +3294,13 @@
#define MAP_Timer_A_unregisterInterrupt \
Timer_A_unregisterInterrupt
#endif
+#ifdef ROM_Timer_A_getCounterValue
+#define MAP_Timer_A_getCounterValue \
+ ROM_Timer_A_getCounterValue
+#else
+#define MAP_Timer_A_getCounterValue \
+ Timer_A_getCounterValue
+#endif
//*****************************************************************************
//
@@ -3434,5 +3592,19 @@
#define MAP_WDT_A_unregisterInterrupt \
WDT_A_unregisterInterrupt
#endif
+#ifdef ROM_WDT_A_setPasswordViolationReset
+#define MAP_WDT_A_setPasswordViolationReset \
+ ROM_WDT_A_setPasswordViolationReset
+#else
+#define MAP_WDT_A_setPasswordViolationReset \
+ WDT_A_setPasswordViolationReset
+#endif
+#ifdef ROM_WDT_A_setTimeoutReset
+#define MAP_WDT_A_setTimeoutReset \
+ ROM_WDT_A_setTimeoutReset
+#else
+#define MAP_WDT_A_setTimeoutReset \
+ WDT_A_setTimeoutReset
+#endif
#endif // __ROM_MAP_H__
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c
index 6f90093..757e0c2 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,45 +37,46 @@
#include <rtc_c.h>
#include <interrupt.h>
#include <debug.h>
+#include <hw_memmap.h>
void RTC_C_startClock(void)
{
- RTC_C->rCTL0.b.bKEY = RTCKEY_H;
- BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 0;
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+ BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 0;
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_holdClock(void)
{
- RTC_C->rCTL0.b.bKEY = RTCKEY_H;
- BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+ BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect)
{
- RTC_C->rCTL0.b.bKEY = RTCKEY_H;
- RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCCALF_3)) | frequencySelect;
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+ RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_CALF_3)) | frequencySelect;
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
uint_fast8_t offsetValue)
{
- RTC_C->rCTL0.b.bKEY = RTCKEY_H;
- RTC_C->rOCAL.r = offsetValue + offsetDirection;
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+ RTC_C->OCAL = offsetValue + offsetDirection;
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
uint_fast8_t offsetValue)
{
- while (!BITBAND_PERI(RTC_C->rTCMP.r, RTCTCRDY_OFS))
+ while (!BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCRDY_OFS))
;
- RTC_C->rTCMP.r = offsetValue + offsetDirection;
+ RTC_C->TCMP = offsetValue + offsetDirection;
- if (BITBAND_PERI(RTC_C->rTCMP.r, RTCTCOK_OFS))
+ if (BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCOK_OFS))
return true;
else
return false;
@@ -84,40 +85,37 @@
void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
uint_fast16_t formatSelect)
{
- RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+ RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
- BITBAND_PERI(RTC_C->rCTL13.r, RTCHOLD_OFS) = 1;
+ BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
if (formatSelect)
- BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 1;
+ BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 1;
else
- BITBAND_PERI(RTC_C->rCTL13.r, RTCBCD_OFS) = 0;
+ BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 0;
- RTC_C->rTIM0.b.bSEC = calendarTime->seconds;
- RTC_C->rTIM0.b.bMIN = calendarTime->minutes;
- RTC_C->rTIM1.b.bHOUR = calendarTime->hours;
- RTC_C->rTIM1.b.bDOW = calendarTime->dayOfWeek;
- RTC_C->rDATE.b.bDAY = calendarTime->dayOfmonth;
- RTC_C->rDATE.b.bMON = calendarTime->month;
- RTC_C->rYEAR.r = calendarTime->year;
+ RTC_C->TIM0 = (calendarTime->minutes<<RTC_C_TIM0_MIN_OFS) | calendarTime->seconds;
+ RTC_C->TIM1 = (calendarTime->dayOfWeek<<RTC_C_TIM1_DOW_OFS) | calendarTime->hours;
+ RTC_C->DATE = (calendarTime->month<<RTC_C_DATE_MON_OFS) | calendarTime->dayOfmonth;
+ RTC_C->YEAR = calendarTime->year;
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
RTC_C_Calendar RTC_C_getCalendarTime(void)
{
RTC_C_Calendar tempCal;
- while (!(BITBAND_PERI(RTC_C->rCTL13.r, RTCRDY_OFS)))
+ while (!(BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_RDY_OFS)))
;
- tempCal.seconds = RTC_C->rTIM0.b.bSEC;
- tempCal.minutes = RTC_C->rTIM0.b.bMIN;
- tempCal.hours = RTC_C->rTIM1.b.bHOUR;
- tempCal.dayOfWeek = RTC_C->rTIM1.b.bDOW;
- tempCal.dayOfmonth = RTC_C->rDATE.b.bDAY;
- tempCal.month = RTC_C->rDATE.b.bMON;
- tempCal.year = RTC_C->rYEAR.r;
+ tempCal.seconds = RTC_C->TIM0 & RTC_C_TIM0_SEC_MASK;
+ tempCal.minutes = (RTC_C->TIM0 & RTC_C_TIM0_MIN_MASK)>>RTC_C_TIM0_MIN_OFS;
+ tempCal.hours = RTC_C->TIM1 & RTC_C_TIM1_HOUR_MASK;
+ tempCal.dayOfWeek = (RTC_C->TIM1 & RTC_C_TIM1_DOW_MASK)>>RTC_C_TIM1_DOW_OFS;
+ tempCal.dayOfmonth = RTC_C->DATE & RTC_C_DATE_DAY_MASK;
+ tempCal.month = (RTC_C->DATE & RTC_C_DATE_MON_MASK)>>RTC_C_DATE_MON_OFS;
+ tempCal.year = RTC_C->YEAR;
return (tempCal);
}
@@ -127,24 +125,22 @@
{
//Each of these is XORed with 0x80 to turn on if an integer is passed,
//or turn OFF if RTC_ALARM_OFF (0x80) is passed.
- HWREG8(RTC_C_BASE + OFS_RTCAMINHR) = (minutesAlarm ^ 0x80);
- HWREG8(RTC_C_BASE + OFS_RTCAMINHR + 1) = (hoursAlarm ^ 0x80);
- HWREG8(RTC_C_BASE + OFS_RTCADOWDAY) = (dayOfWeekAlarm ^ 0x80);
- HWREG8(RTC_C_BASE + OFS_RTCADOWDAY + 1) = (dayOfmonthAlarm ^ 0x80);
+ RTC_C->AMINHR = ((hoursAlarm ^ 0x80) << 8 )| (minutesAlarm ^ 0x80);
+ RTC_C->ADOWDAY = ((dayOfmonthAlarm ^ 0x80) << 8 )| (dayOfWeekAlarm ^ 0x80);
}
void RTC_C_setCalendarEvent(uint_fast16_t eventSelect)
{
- RTC_C->rCTL0.b.bKEY = RTCKEY_H;
- RTC_C->rCTL13.r = (RTC_C->rCTL13.r & ~(RTCTEV_3)) | eventSelect;
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+ RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_TEV_3)) | eventSelect;
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleEventDivider)
{
- HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) &= ~(RT0IP_7);
- HWREG8(RTC_C_BASE + OFS_RTCPS0CTL + prescaleSelect) |=
+ HWREG8(&RTC_C->PS0CTL + prescaleSelect) &= ~(RTC_C_PS0CTL_RT0IP_7);
+ HWREG8(&RTC_C->PS0CTL + prescaleSelect) |=
prescaleEventDivider;
}
@@ -152,10 +148,10 @@
{
if (RTC_C_PRESCALE_0 == prescaleSelect)
{
- return (RTC_C->rPS.b.bRT0PS);
+ return (RTC_C->PS & RTC_C_PS_RT0PS_MASK);
} else if (RTC_C_PRESCALE_1 == prescaleSelect)
{
- return (RTC_C->rPS.b.bRT1PS);
+ return (RTC_C->PS & RTC_C_PS_RT1PS_MASK)>>RTC_C_PS_RT1PS_OFS;
} else
{
return (0);
@@ -165,70 +161,74 @@
void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
uint_fast8_t prescaleCounterValue)
{
- RTC_C->rCTL0.b.bKEY = RTCKEY_H;
+ RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
if (RTC_C_PRESCALE_0 == prescaleSelect)
{
- RTC_C->rPS.b.bRT0PS = prescaleCounterValue;
+ RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT0PS_MASK) | prescaleCounterValue;
} else if (RTC_C_PRESCALE_1 == prescaleSelect)
{
- RTC_C->rPS.b.bRT1PS = prescaleCounterValue;
+ RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT1PS_MASK)
+ | (prescaleCounterValue << RTC_C_PS_RT1PS_OFS);
}
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert)
{
- RTC_C->rBCD2BIN = valueToConvert;
- return (RTC_C->rBCD2BIN);
+ RTC_C->BCD2BIN = valueToConvert;
+ return (RTC_C->BCD2BIN);
}
uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert)
{
- RTC_C->rBIN2BCD = valueToConvert;
- return (RTC_C->rBIN2BCD);
+ RTC_C->BIN2BCD = valueToConvert;
+ return (RTC_C->BIN2BCD);
}
void RTC_C_enableInterrupt(uint8_t interruptMask)
{
- if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
+ if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ + RTC_C_CTL0_RDYIE))
{
- RTC_C->rCTL0.r = RTCKEY | (interruptMask
- & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE));
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = RTC_C_KEY | (interruptMask
+ & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ + RTC_C_CTL0_RDYIE));
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
- BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 1;
+ BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 1;
}
if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
- BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 1;
+ BITBAND_PERI(RTC_C->PS1CTL,RTC_C_PS1CTL_RT1PSIE_OFS) = 1;
}
}
void RTC_C_disableInterrupt(uint8_t interruptMask)
{
- if (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE))
+ if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ + RTC_C_CTL0_RDYIE))
{
- RTC_C->rCTL0.r = RTCKEY
- | (RTC_C->rCTL0.r
- & ~((interruptMask | RTCKEY_M)
- & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)));
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = RTC_C_KEY
+ | (RTC_C->CTL0 & ~((interruptMask | RTC_C_CTL0_KEY_MASK)
+ & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+ + RTC_C_CTL0_RDYIE)));
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
- BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIE_OFS) = 0;
+ BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 0;
}
if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
- BITBAND_PERI(RTC_C->rPS1CTL.r,RT1PSIE_OFS) = 0;
+ BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS) = 0;
}
}
@@ -240,13 +240,13 @@
| RTC_C_PRESCALE_TIMER0_INTERRUPT | RTC_C_PRESCALE_TIMER1_INTERRUPT
| RTC_C_OSCILLATOR_FAULT_INTERRUPT;
- tempInterruptFlagMask |= (RTC_C->rCTL0.r & (interruptFlagMask >> 4));
+ tempInterruptFlagMask |= (RTC_C->CTL0 & (interruptFlagMask >> 4));
tempInterruptFlagMask = tempInterruptFlagMask << 4;
if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
- if (BITBAND_PERI(RTC_C->rPS0CTL.r, RT0PSIFG_OFS))
+ if (BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT;
}
@@ -254,7 +254,7 @@
if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
- if (BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS))
+ if (BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS))
{
tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT;
}
@@ -268,32 +268,32 @@
uint32_t intStatus = RTC_C_getInterruptStatus();
- if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCOFIE_OFS))
+ if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_OFIE_OFS))
{
intStatus &= ~RTC_C_OSCILLATOR_FAULT_INTERRUPT;
}
- if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCTEVIE_OFS))
+ if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_TEVIE_OFS))
{
intStatus &= ~RTC_C_TIME_EVENT_INTERRUPT;
}
- if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCAIE_OFS))
+ if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_AIE_OFS))
{
intStatus &= ~RTC_C_CLOCK_ALARM_INTERRUPT;
}
- if (!BITBAND_PERI(RTC_C->rCTL0.r, RTCRDYIE_OFS))
+ if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_RDYIE_OFS))
{
intStatus &= ~RTC_C_CLOCK_READ_READY_INTERRUPT;
}
- if (!BITBAND_PERI(RTC_C->rPS0CTL, RT0PSIE_OFS))
+ if (!BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS))
{
intStatus &= ~RTC_C_PRESCALE_TIMER0_INTERRUPT;
}
- if (!BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIE_OFS))
+ if (!BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS))
{
intStatus &= ~RTC_C_PRESCALE_TIMER1_INTERRUPT;
}
@@ -308,19 +308,19 @@
+ RTC_C_CLOCK_READ_READY_INTERRUPT
+ RTC_C_OSCILLATOR_FAULT_INTERRUPT))
{
- RTC_C->rCTL0.r = RTCKEY
- | (RTC_C->rCTL0.r & ~((interruptFlagMask >> 4) | RTCKEY_M));
- BITBAND_PERI(RTC_C->rCTL0.r, RTCKEY_OFS) = 0;
+ RTC_C->CTL0 = RTC_C_KEY
+ | (RTC_C->CTL0 & ~((interruptFlagMask >> 4) | RTC_C_CTL0_KEY_MASK));
+ BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
{
- BITBAND_PERI(RTC_C->rPS0CTL.r,RT0PSIFG_OFS) = 0;
+ BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS) = 0;
}
if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
{
- BITBAND_PERI(RTC_C->rPS1CTL.r, RT1PSIFG_OFS) = 0;
+ BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS) = 0;
}
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h
index 6786d4a..1044e08 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/rtc_c.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -82,18 +82,18 @@
//The following are values that can be passed to RTC_setCalibrationData()
//
//*****************************************************************************
-#define RTC_C_CALIBRATIONFREQ_OFF (RTCCALF_0)
-#define RTC_C_CALIBRATIONFREQ_512HZ (RTCCALF_1)
-#define RTC_C_CALIBRATIONFREQ_256HZ (RTCCALF_2)
-#define RTC_C_CALIBRATIONFREQ_1HZ (RTCCALF_3)
+#define RTC_C_CALIBRATIONFREQ_OFF (RTC_C_CTL13_CALF_0)
+#define RTC_C_CALIBRATIONFREQ_512HZ (RTC_C_CTL13_CALF_1)
+#define RTC_C_CALIBRATIONFREQ_256HZ (RTC_C_CTL13_CALF_2)
+#define RTC_C_CALIBRATIONFREQ_1HZ (RTC_C_CTL13_CALF_3)
//*****************************************************************************
//
//The following are values that can be passed to RTC_setCalibrationData()
//
//*****************************************************************************
-#define RTC_C_CALIBRATION_DOWN1PPM ( !(RTCOCALS) )
-#define RTC_C_CALIBRATION_UP1PPM (RTCOCALS)
+#define RTC_C_CALIBRATION_DOWN1PPM ( !(RTC_C_OCAL_OCALS) )
+#define RTC_C_CALIBRATION_UP1PPM (RTC_C_OCAL_OCALS)
//*****************************************************************************
//
@@ -101,16 +101,16 @@
//RTC_setTemperatureCompensation()
//
//*****************************************************************************
-#define RTC_C_COMPENSATION_DOWN1PPM ( !(RTCTCMPS) )
-#define RTC_C_COMPENSATION_UP1PPM (RTCTCMPS)
+#define RTC_C_COMPENSATION_DOWN1PPM ( !(RTC_C_TCMP_TCMPS) )
+#define RTC_C_COMPENSATION_UP1PPM (RTC_C_TCMP_TCMPS)
//*****************************************************************************
//
//The following are values that can be passed to RTC_iniRTC_Calendar()
//
//*****************************************************************************
-#define RTC_C_FORMAT_BINARY ( !(RTCBCD) )
-#define RTC_C_FORMAT_BCD (RTCBCD)
+#define RTC_C_FORMAT_BINARY ( !(RTC_C_CTL13_BCD) )
+#define RTC_C_FORMAT_BCD (RTC_C_CTL13_BCD)
//*****************************************************************************
//
@@ -125,10 +125,10 @@
//in the eventSelect parameter.
//
//*****************************************************************************
-#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTCTEV_0)
-#define RTC_C_CALENDAREVENT_HOURCHANGE (RTCTEV_1)
-#define RTC_C_CALENDAREVENT_NOON (RTCTEV_2)
-#define RTC_C_CALENDAREVENT_MIDNIGHT (RTCTEV_3)
+#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTC_C_CTL13_TEV_0)
+#define RTC_C_CALENDAREVENT_HOURCHANGE (RTC_C_CTL13_TEV_1)
+#define RTC_C_CALENDAREVENT_NOON (RTC_C_CTL13_TEV_2)
+#define RTC_C_CALENDAREVENT_MIDNIGHT (RTC_C_CTL13_TEV_3)
//*****************************************************************************
//
@@ -144,24 +144,24 @@
//in the prescaleEventDivider parameter.
//
//*****************************************************************************
-#define RTC_C_PSEVENTDIVIDER_2 (RT0IP_0)
-#define RTC_C_PSEVENTDIVIDER_4 (RT0IP_1)
-#define RTC_C_PSEVENTDIVIDER_8 (RT0IP_2)
-#define RTC_C_PSEVENTDIVIDER_16 (RT0IP_3)
-#define RTC_C_PSEVENTDIVIDER_32 (RT0IP_4)
-#define RTC_C_PSEVENTDIVIDER_64 (RT0IP_5)
-#define RTC_C_PSEVENTDIVIDER_128 (RT0IP_6)
-#define RTC_C_PSEVENTDIVIDER_256 (RT0IP_7)
+#define RTC_C_PSEVENTDIVIDER_2 (RTC_C_PS0CTL_RT0IP_0)
+#define RTC_C_PSEVENTDIVIDER_4 (RTC_C_PS0CTL_RT0IP_1)
+#define RTC_C_PSEVENTDIVIDER_8 (RTC_C_PS0CTL_RT0IP_2)
+#define RTC_C_PSEVENTDIVIDER_16 (RTC_C_PS0CTL_RT0IP_3)
+#define RTC_C_PSEVENTDIVIDER_32 (RTC_C_PS0CTL_RT0IP_4)
+#define RTC_C_PSEVENTDIVIDER_64 (RTC_C_PS0CTL_RT0IP_5)
+#define RTC_C_PSEVENTDIVIDER_128 (RTC_C_PS0CTL_RT0IP_6)
+#define RTC_C_PSEVENTDIVIDER_256 (RTC_C_PS0CTL_RT0IP_7)
//*****************************************************************************
//
//The following are values that can be passed to the interrupt functions
//
//*****************************************************************************
-#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTCOFIE
-#define RTC_C_TIME_EVENT_INTERRUPT RTCTEVIE
-#define RTC_C_CLOCK_ALARM_INTERRUPT RTCAIE
-#define RTC_C_CLOCK_READ_READY_INTERRUPT RTCRDYIE
+#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTC_C_CTL0_OFIE
+#define RTC_C_TIME_EVENT_INTERRUPT RTC_C_CTL0_TEVIE
+#define RTC_C_CLOCK_ALARM_INTERRUPT RTC_C_CTL0_AIE
+#define RTC_C_CLOCK_READ_READY_INTERRUPT RTC_C_CTL0_RDYIE
#define RTC_C_PRESCALE_TIMER0_INTERRUPT 0x02
#define RTC_C_PRESCALE_TIMER1_INTERRUPT 0x01
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c
index b782564..7529b0c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,12 +41,12 @@
static bool is_A_Module(uint32_t module)
{
- if (module == EUSCI_A0_MODULE || module == EUSCI_A1_MODULE
-#ifdef EUSCI_A2_MODULE
- || module == EUSCI_A2_MODULE
+ if (module == EUSCI_A0_BASE || module == EUSCI_A1_BASE
+#ifdef EUSCI_A2_BASE
+ || module == EUSCI_A2_BASE
#endif
-#ifdef EUSCI_A3_MODULE
- || module == EUSCI_A3_MODULE
+#ifdef EUSCI_A3_BASE
+ || module == EUSCI_A3_BASE
#endif
)
return true;
@@ -56,6 +56,13 @@
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
+ /* Returning false if we are not divisible */
+ if((config->clockSourceFrequency
+ % config->desiredSpiClock) != 0)
+ {
+ return false;
+ }
+
if (is_A_Module(moduleInstance))
{
ASSERT(
@@ -85,31 +92,31 @@
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
-
+
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
- * UCMST = Master mode
- * UCSYNC = Synchronous mode
+ * EUSCI_A_CTLW0_MST = Master mode
+ * EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
- + UCMODE_3 + UCSYNC))
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
- + UCMST + UCSYNC + config->spiMode);
-
- EUSCI_A_CMSIS(moduleInstance)->rBRW =
+ + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
+
+ EUSCI_A_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
//No modulation
- EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = 0;
+ EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
return true;
} else
@@ -143,24 +150,24 @@
== config->spiMode));
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
- * UCMST = Master mode
- * UCSYNC = Synchronous mode
+ * EUSCI_A_CTLW0_MST = Master mode
+ * EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
- + UCMODE_3 + UCSYNC))
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
- + UCMST + UCSYNC + config->spiMode);
+ + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
- EUSCI_B_CMSIS(moduleInstance)->rBRW =
+ EUSCI_B_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
@@ -227,14 +234,14 @@
== config->spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (config->clockPhase + config->clockPolarity
- + config->msbFirst + UCSYNC + config->spiMode);
+ + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
return true;
} else
@@ -263,14 +270,14 @@
== config->spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
- EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
+ EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_B_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
| (config->clockPhase + config->clockPolarity
- + config->msbFirst + UCSYNC + config->spiMode);
+ + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
return true;
}
@@ -418,12 +425,13 @@
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
- & HWREG16(moduleInstance + OFS_UCA0IE);
+ & EUSCI_A_CMSIS(moduleInstance)->IE;
+
} else
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
- & HWREG16(moduleInstance + OFS_UCB0IE);
+ & EUSCI_B_CMSIS(moduleInstance)->IE;
}
}
@@ -444,42 +452,42 @@
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA3);
break;
#endif
- case EUSCI_B0_MODULE:
+ case EUSCI_B0_BASE:
Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB0);
break;
- case EUSCI_B1_MODULE:
+ case EUSCI_B1_BASE:
Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB1);
break;
-#ifdef EUSCI_B2_MODULE
- case EUSCI_B2_MODULE:
+#ifdef EUSCI_B2_BASE
+ case EUSCI_B2_BASE:
Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB2);
break;
#endif
-#ifdef EUSCI_B3_MODULE
- case EUSCI_B3_MODULE:
+#ifdef EUSCI_B3_BASE
+ case EUSCI_B3_BASE:
Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIB3);
break;
@@ -493,42 +501,42 @@
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_disableInterrupt(INT_EUSCIA0);
Interrupt_unregisterInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_disableInterrupt(INT_EUSCIA1);
Interrupt_unregisterInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_disableInterrupt(INT_EUSCIA2);
Interrupt_unregisterInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_disableInterrupt(INT_EUSCIA3);
Interrupt_unregisterInterrupt(INT_EUSCIA3);
break;
#endif
- case EUSCI_B0_MODULE:
+ case EUSCI_B0_BASE:
Interrupt_disableInterrupt(INT_EUSCIB0);
Interrupt_unregisterInterrupt(INT_EUSCIB0);
break;
- case EUSCI_B1_MODULE:
+ case EUSCI_B1_BASE:
Interrupt_disableInterrupt(INT_EUSCIB1);
Interrupt_unregisterInterrupt(INT_EUSCIB1);
break;
-#ifdef EUSCI_B2_MODULE
- case EUSCI_B2_MODULE:
+#ifdef EUSCI_B2_BASE
+ case EUSCI_B2_BASE:
Interrupt_disableInterrupt(INT_EUSCIB2);
Interrupt_unregisterInterrupt(INT_EUSCIB2);
break;
#endif
-#ifdef EUSCI_B3_MODULE
- case EUSCI_B3_MODULE:
+#ifdef EUSCI_B3_BASE
+ case EUSCI_B3_BASE:
Interrupt_disableInterrupt(INT_EUSCIB3);
Interrupt_unregisterInterrupt(INT_EUSCIB3);
break;
@@ -568,8 +576,8 @@
|| (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
== select4PinFunctionality));
- EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
- & ~UCSTEM) | select4PinFunctionality;
+ EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
+ & ~EUSCI_B_CTLW0_STEM) | select4PinFunctionality;
}
//*****************************************************************************
@@ -590,13 +598,13 @@
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_B_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
+ EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@@ -628,7 +636,7 @@
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
-//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
+//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
@@ -658,12 +666,12 @@
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
- EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
- | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
+ EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
+ | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
return true;
}
@@ -684,7 +692,7 @@
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//!
-//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
+//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
//! register.
//!
//! \return None
@@ -706,13 +714,13 @@
== clockPhase));
//Disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
+ EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@@ -730,7 +738,7 @@
//*****************************************************************************
void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
{
- EUSCI_B_CMSIS(baseAddress)->rTXBUF.r = transmitData;
+ EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData;
}
//*****************************************************************************
@@ -747,7 +755,7 @@
//*****************************************************************************
uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
{
- return EUSCI_B_CMSIS(baseAddress)->rRXBUF.r;
+ return EUSCI_B_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
@@ -776,7 +784,7 @@
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_B_CMSIS(baseAddress)->rIE.r |= mask;
+ EUSCI_B_CMSIS(baseAddress)->IE |= mask;
}
//*****************************************************************************
@@ -805,7 +813,7 @@
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_B_CMSIS(baseAddress)->rIE.r &= ~mask;
+ EUSCI_B_CMSIS(baseAddress)->IE &= ~mask;
}
//*****************************************************************************
@@ -834,7 +842,7 @@
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- return EUSCI_B_CMSIS(baseAddress)->rIFG.r & mask;
+ return EUSCI_B_CMSIS(baseAddress)->IFG & mask;
}
//*****************************************************************************
@@ -859,7 +867,7 @@
& ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
| EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_B_CMSIS(baseAddress)->rIFG.r &= ~mask;
+ EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask;
}
//*****************************************************************************
@@ -878,7 +886,7 @@
void EUSCI_B_SPI_enable(uint32_t baseAddress)
{
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@@ -897,7 +905,7 @@
void EUSCI_B_SPI_disable(uint32_t baseAddress)
{
//Set the UCSWRST bit to disable the USCI Module
- BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
//*****************************************************************************
@@ -914,7 +922,7 @@
//*****************************************************************************
uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCB0RXBUF;
+ return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF));
}
//*****************************************************************************
@@ -931,7 +939,7 @@
//*****************************************************************************
uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCB0TXBUF;
+ return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF));
}
//*****************************************************************************
@@ -949,7 +957,7 @@
bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
- return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
+ return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
}
//*****************************************************************************
@@ -979,8 +987,8 @@
|| (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
== select4PinFunctionality));
- EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
- & ~UCSTEM) | select4PinFunctionality;
+ EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
+ & ~EUSCI_A_CTLW0_STEM) | select4PinFunctionality;
}
//*****************************************************************************
@@ -1001,13 +1009,13 @@
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_A_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
+ EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@@ -1039,7 +1047,7 @@
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
-//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
+//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
@@ -1069,12 +1077,12 @@
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
- EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
- | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
+ EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
+ | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
return true;
}
@@ -1095,7 +1103,7 @@
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//!
-//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
+//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
//! register.
//!
//! \return None
@@ -1117,13 +1125,13 @@
== clockPhase));
//Disable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
- EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
- & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
+ EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
+ & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@@ -1141,7 +1149,7 @@
//*****************************************************************************
void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
{
- EUSCI_A_CMSIS(baseAddress)->rTXBUF.r = transmitData;
+ EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData;
}
//*****************************************************************************
@@ -1158,7 +1166,7 @@
//*****************************************************************************
uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
{
- return EUSCI_A_CMSIS(baseAddress)->rRXBUF.r;
+ return EUSCI_A_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
@@ -1187,7 +1195,7 @@
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_A_CMSIS(baseAddress)->rIE.r |= mask;
+ EUSCI_A_CMSIS(baseAddress)->IE |= mask;
}
//*****************************************************************************
@@ -1216,7 +1224,7 @@
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_A_CMSIS(baseAddress)->rIE.r &= ~mask;
+ EUSCI_A_CMSIS(baseAddress)->IE &= ~mask;
}
//*****************************************************************************
@@ -1245,7 +1253,7 @@
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- return EUSCI_A_CMSIS(baseAddress)->rIFG.r & mask;
+ return EUSCI_A_CMSIS(baseAddress)->IFG & mask;
}
//*****************************************************************************
@@ -1270,7 +1278,7 @@
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
- EUSCI_A_CMSIS(baseAddress)->rIFG.r &= ~mask;
+ EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask;
}
//*****************************************************************************
@@ -1289,7 +1297,7 @@
void EUSCI_A_SPI_enable(uint32_t baseAddress)
{
//Reset the UCSWRST bit to enable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
//*****************************************************************************
@@ -1308,7 +1316,7 @@
void EUSCI_A_SPI_disable(uint32_t baseAddress)
{
//Set the UCSWRST bit to disable the USCI Module
- BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
//*****************************************************************************
@@ -1325,7 +1333,7 @@
//*****************************************************************************
uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCA0RXBUF;
+ return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF;
}
//*****************************************************************************
@@ -1342,7 +1350,7 @@
//*****************************************************************************
uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
{
- return baseAddress + OFS_UCA0TXBUF;
+ return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF;
}
//*****************************************************************************
@@ -1359,5 +1367,5 @@
bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
- return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
+ return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h
index d874494..6edb0e7 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -61,34 +61,34 @@
#include "eusci.h"
/* Configuration Defines */
-#define EUSCI_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
-#define EUSCI_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
+#define EUSCI_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK
+#define EUSCI_SPI_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK
-#define EUSCI_SPI_MSB_FIRST UCMSB
+#define EUSCI_SPI_MSB_FIRST EUSCI_B_CTLW0_MSB
#define EUSCI_SPI_LSB_FIRST 0x00
-#define EUSCI_SPI_BUSY UCBUSY
+#define EUSCI_SPI_BUSY EUSCI_A_STATW_BUSY
#define EUSCI_SPI_NOT_BUSY 0x00
#define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
-#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
+#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_B_CTLW0_CKPH
-#define EUSCI_SPI_3PIN UCMODE_0
-#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
-#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
+#define EUSCI_SPI_3PIN EUSCI_B_CTLW0_MODE_0
+#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_B_CTLW0_MODE_1
+#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_B_CTLW0_MODE_2
-#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
+#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL
#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
-#define EUSCI_SPI_TRANSMIT_INTERRUPT UCTXIE
-#define EUSCI_SPI_RECEIVE_INTERRUPT UCRXIE
+#define EUSCI_SPI_TRANSMIT_INTERRUPT EUSCI_B__TXIE
+#define EUSCI_SPI_RECEIVE_INTERRUPT EUSCI_B__RXIE
-#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
+#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM
#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00
//*****************************************************************************
//
-//! \typedef eUSCI_SPI_MasterConfig
+//! ypedef eUSCI_SPI_MasterConfig
//! \brief Type definition for \link _eUSCI_SPI_MasterConfig \endlink structure
//!
//! \struct _eUSCI_SPI_MasterConfig
@@ -109,7 +109,7 @@
//*****************************************************************************
//
-//! \typedef eUSCI_SPI_SlaveConfig
+//! ypedef eUSCI_SPI_SlaveConfig
//! \brief Type definition for \link _eUSCI_SPI_SlaveConfig \endlink structure
//!
//! \struct _eUSCI_SPI_SlaveConfig
@@ -131,14 +131,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! \param config Configuration structure for SPI master mode
//!
//! <hr>
@@ -187,14 +187,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! \param select4PinFunctionality selects Clock source. Valid values are
//! - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
@@ -217,14 +217,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! \param clockSourceFrequency is the frequency of the selected clock source
//! \param desiredSpiClock is the desired clock rate for SPI communication.
@@ -244,14 +244,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! \param config Configuration structure for SPI slave mode
//!
//! <hr>
@@ -295,14 +295,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! \param clockPhase is clock phase select.
//! Valid values are:
@@ -329,14 +329,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! \param transmitData data to be transmitted from the SPI module
//!
@@ -357,14 +357,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//!
//! This function reads a byte of data from the SPI receive data Register.
@@ -381,14 +381,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//!
//! This will enable operation of the SPI block.
@@ -405,14 +405,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//!
//! This will disable operation of the SPI block.
@@ -430,14 +430,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//!
//! Returns the address of the SPI RX Buffer. This can be used in conjunction
@@ -454,14 +454,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//!
//! Returns the address of the SPI TX Buffer. This can be used in conjunction
@@ -478,14 +478,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//!
//! This function returns an indication of whether or not the SPI bus is
@@ -503,14 +503,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! \param mask is the bit mask of the interrupt sources to be enabled.
//!
@@ -535,14 +535,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! \param mask is the bit mask of the interrupt sources to be
//! disabled.
@@ -568,14 +568,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! \param mask Mask of interrupt to filter. This can include:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
@@ -600,14 +600,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! Modified registers are \b UCAxIFG.
//!
@@ -625,14 +625,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! \param mask is the masked interrupt flag to be cleared.
//!
@@ -652,14 +652,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI (SPI) module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//! It is important to note that for eUSCI modules, only "B" modules such as
//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
//! I2C mode.
@@ -685,14 +685,14 @@
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
-//! - \b EUSCI_B0_MODULE
-//! - \b EUSCI_B1_MODULE
-//! - \b EUSCI_B2_MODULE
-//! - \b EUSCI_B3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
+//! - \b EUSCI_B0_BASE
+//! - \b EUSCI_B1_BASE
+//! - \b EUSCI_B2_BASE
+//! - \b EUSCI_B3_BASE
//!
//! This function unregisters the handler to be called when timer
//! interrupt occurs. This function also masks off the interrupt in the
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c
index abc6bc9..4635a2b 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -83,29 +83,70 @@
}
#endif
+void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
+ uint_fast8_t *length, uint32_t **data_address)
+{
+ /* TLV Structure Start Address */
+ uint32_t *TLV_address = (uint32_t *) TLV_START;
+
+ while (((*TLV_address != tag)) // check for tag and instance
+ && (*TLV_address != TLV_TAGEND)) // do range check first
+ {
+ if (*TLV_address == tag)
+ {
+ if(instance == 0)
+ {
+ break;
+ }
+
+ /* Repeat until requested instance is reached */
+ instance--;
+ }
+
+ TLV_address += (*(TLV_address + 1)) + 2;
+ }
+
+ /* Check if Tag match happened... */
+ if (*TLV_address == tag)
+ {
+ /* Return length = Address + 1 */
+ *length = (*(TLV_address + 1))*4;
+ /* Return address of first data/value info = Address + 2 */
+ *data_address = (uint32_t *) (TLV_address + 2);
+ }
+ // If there was no tag match and the end of TLV structure was reached..
+ else
+ {
+ // Return 0 for TAG not found
+ *length = 0;
+ // Return 0 for TAG not found
+ *data_address = 0;
+ }
+}
+
uint_least32_t SysCtl_getSRAMSize(void)
{
- return SYSCTL->rSRAM_SIZE;
+ return SYSCTL->SRAM_SIZE;
}
uint_least32_t SysCtl_getFlashSize(void)
{
- return SYSCTL->rFLASH_SIZE;
+ return SYSCTL->FLASH_SIZE;
}
void SysCtl_disableNMISource(uint_fast8_t flags)
{
- SYSCTL->rNMI_CTLSTAT.r &= ~(flags);
+ SYSCTL->NMI_CTLSTAT &= ~(flags);
}
void SysCtl_enableNMISource(uint_fast8_t flags)
{
- SYSCTL->rNMI_CTLSTAT.r |= flags;
+ SYSCTL->NMI_CTLSTAT |= flags;
}
uint_fast8_t SysCtl_getNMISourceStatus(void)
{
- return SYSCTL->rNMI_CTLSTAT.r;
+ return SYSCTL->NMI_CTLSTAT;
}
void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
@@ -113,10 +154,10 @@
ASSERT(SysCtlSRAMBankValid(sramBank));
/* Waiting for SRAM Ready Bit to be set */
- while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
+ while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
;
- SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
+ SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
}
void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
@@ -124,8 +165,8 @@
ASSERT(SysCtlSRAMBankValid(sramBank));
/* Waiting for SRAM Ready Bit to be set */
- while (!SYSCTL->rSRAM_BANKEN.b.bSRAM_RDY)
- ;
+ while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
+ ;
switch (sramBank)
{
@@ -160,7 +201,7 @@
return;
}
- SYSCTL->rSRAM_BANKEN.r = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
+ SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
}
void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
@@ -168,10 +209,10 @@
ASSERT(SysCtlSRAMBankValidRet(sramBank));
/* Waiting for SRAM Ready Bit to be set */
- while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
- ;
+ while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
+ ;
- SYSCTL->rSRAM_BANKRET.r |= sramBank;
+ SYSCTL->SRAM_BANKRET |= sramBank;
}
void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
@@ -179,36 +220,36 @@
ASSERT(SysCtlSRAMBankValidRet(sramBank));
/* Waiting for SRAM Ready Bit to be set */
- while (!SYSCTL->rSRAM_BANKRET.b.bSRAM_RDY)
- ;
+ while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
+ ;
- SYSCTL->rSRAM_BANKRET.r &= ~sramBank;
+ SYSCTL->SRAM_BANKRET &= ~sramBank;
}
void SysCtl_rebootDevice(void)
{
- SYSCTL->rREBOOT_CTL.r = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
+ SYSCTL->REBOOT_CTL = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
}
void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
{
ASSERT(SysCtlPeripheralIsValid(devices));
- SYSCTL->rPERIHALT_CTL.r &= ~devices;
+ SYSCTL->PERIHALT_CTL &= ~devices;
}
void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
{
ASSERT(SysCtlPeripheralIsValid(devices));
- SYSCTL->rPERIHALT_CTL.r |= devices;
+ SYSCTL->PERIHALT_CTL |= devices;
}
void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
{
if (resetType)
- SYSCTL->rWDTRESET_CTL.r |=
+ SYSCTL->WDTRESET_CTL |=
SYSCTL_WDTRESET_CTL_TIMEOUT;
else
- SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
+ SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
}
void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
@@ -216,20 +257,20 @@
ASSERT(resetType <= SYSCTL_HARD_RESET);
if (resetType)
- SYSCTL->rWDTRESET_CTL.r |=
+ SYSCTL->WDTRESET_CTL |=
SYSCTL_WDTRESET_CTL_VIOLATION;
else
- SYSCTL->rWDTRESET_CTL.r &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
+ SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
}
void SysCtl_enableGlitchFilter(void)
{
- SYSCTL->rDIO_GLTFLT_CTL.r |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
+ SYSCTL->DIO_GLTFLT_CTL |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
}
void SysCtl_disableGlitchFilter(void)
{
- SYSCTL->rDIO_GLTFLT_CTL.r &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
+ SYSCTL->DIO_GLTFLT_CTL &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
}
uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h
index 1e32a9e..3ffc9be 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/sysctl.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -74,22 +74,22 @@
#define SYSCTL_HARD_RESET 1
#define SYSCTL_SOFT_RESET 0
-#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_DMA
-#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_WDT
-#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_ADC
-#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_EUB3
-#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_EUB2
-#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_EUB1
-#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_EUB0
-#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_EUA3
-#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_EUA2
-#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_EUA1
-#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_EUA0
-#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_T32_0
-#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_T16_3
-#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_T16_2
-#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_T16_1
-#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_T16_0
+#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
+#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
+#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
+#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
+#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
+#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
+#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
+#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
+#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
+#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
+#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
+#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
+#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
+#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
+#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
+#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
#define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
#define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
@@ -98,12 +98,63 @@
#define SYSCTL_REBOOT_KEY 0x6900
-#define SYSCTL_1_2V_REF OFS_TLV_ADC14_REF1P2V_TS30C
-#define SYSCTL_1_45V_REF OFS_TLV_ADC14_REF1P45V_TS30C
-#define SYSCTL_2_5V_REF OFS_TLV_ADC14_REF2P5V_TS30C
+#define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
+#define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
+#define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
-#define SYSCTL_85_DEGREES_C 0
-#define SYSCTL_30_DEGREES_C 16
+#define SYSCTL_85_DEGREES_C 4
+#define SYSCTL_30_DEGREES_C 0
+
+
+#define TLV_START 0x00201004
+#define TLV_TAG_RESERVED1 1
+#define TLV_TAG_RESERVED2 2
+#define TLV_TAG_CS 3
+#define TLV_TAG_FLASHCTL 4
+#define TLV_TAG_ADC14 5
+#define TLV_TAG_RESERVED6 6
+#define TLV_TAG_RESERVED7 7
+#define TLV_TAG_REF 8
+#define TLV_TAG_RESERVED9 9
+#define TLV_TAG_RESERVED10 10
+#define TLV_TAG_DEVINFO 11
+#define TLV_TAG_DIEREC 12
+#define TLV_TAG_RANDNUM 13
+#define TLV_TAG_RESERVED14 14
+#define TLV_TAG_BSL 15
+#define TLV_TAGEND 0x0BD0E11D
+
+//*****************************************************************************
+//
+// Structures for TLV definitions
+//
+//*****************************************************************************
+typedef struct
+{
+ uint32_t maxProgramPulses;
+ uint32_t maxErasePulses;
+} SysCtl_FlashTLV_Info;
+
+typedef struct
+{
+ uint32_t rDCOIR_FCAL_RSEL04;
+ uint32_t rDCOIR_FCAL_RSEL5;
+ uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
+ uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
+ uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
+ uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
+ uint32_t rDCOIR_CONSTK_RSEL04;
+ uint32_t rDCOIR_CONSTK_RSEL5;
+ uint32_t rDCOER_FCAL_RSEL04;
+ uint32_t rDCOER_FCAL_RSEL5;
+ uint32_t rDCOER_MAXPOSTUNE_RSEL04;
+ uint32_t rDCOER_MAXNEGTUNE_RSEL04;
+ uint32_t rDCOER_MAXPOSTUNE_RSEL5;
+ uint32_t rDCOER_MAXNEGTUNE_RSEL5;
+ uint32_t rDCOER_CONSTK_RSEL04;
+ uint32_t rDCOER_CONSTK_RSEL5;
+
+} SysCtl_CSCalTLV_Info;
//*****************************************************************************
//
@@ -140,6 +191,51 @@
//*****************************************************************************
//
+//! The TLV structure uses a tag or base address to identify segments of the
+//! table where information is stored. Some examples of TLV tags are Peripheral
+//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves
+//! the value of a tag and the length of the tag.
+//!
+//! \param tag represents the tag for which the information needs to be
+//! retrieved.
+//! Valid values are:
+//! - \b TLV_TAG_RESERVED1
+//! - \b TLV_TAG_RESERVED2
+//! - \b TLV_TAG_CS
+//! - \b TLV_TAG_FLASHCTL
+//! - \b TLV_TAG_ADC14
+//! - \b TLV_TAG_RESERVED6
+//! - \b TLV_TAG_RESERVED7
+//! - \b TLV_TAG_REF
+//! - \b TLV_TAG_RESERVED9
+//! - \b TLV_TAG_RESERVED10
+//! - \b TLV_TAG_DEVINFO
+//! - \b TLV_TAG_DIEREC
+//! - \b TLV_TAG_RANDNUM
+//! - \b TLV_TAG_RESERVED14
+//! \param instance In some cases a specific tag may have more than one
+//! instance. For example there may be multiple instances of timer
+//! calibration data present under a single Timer Cal tag. This variable
+//! specifies the instance for which information is to be retrieved (0,
+//! 1, etc.). When only one instance exists; 0 is passed.
+//! \param length Acts as a return through indirect reference. The function
+//! retrieves the value of the TLV tag length. This value is pointed to
+//! by *length and can be used by the application level once the
+//! function is called. If the specified tag is not found then the
+//! pointer is null 0.
+//! \param data_address acts as a return through indirect reference. Once the
+//! function is called data_address points to the pointer that holds the
+//! value retrieved from the specified TLV tag. If the specified tag is
+//! not found then the pointer is null 0.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
+ uint_fast8_t *length, uint32_t **data_address);
+
+//*****************************************************************************
+//
//! Enables a set of banks in the SRAM. This can be used to optimize power
//! consumption when every SRAM bank isn't needed. It is important to note
//! that when a higher bank is enabled, all of the SRAM banks below that bank
@@ -410,7 +506,7 @@
//!
//! \param refVoltage Reference voltage being used.
//!
-//! The \e resetType parameter must be only one of the following values:
+//! The \e refVoltage parameter must be only one of the following values:
//! - \b SYSCTL_1_2V_REF
//! - \b SYSCTL_1_45V_REF
//! - \b SYSCTL_2_5V_REF
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c
index 519baae..3409214 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h
index d18c8ea..8b66996 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/systick.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c
index 4377867..6b087b6 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -43,17 +43,21 @@
{
/* Setting up one shot or continuous mode */
if (mode == TIMER32_PERIODIC_MODE)
- HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 1;
+ BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
+ = 1;
else if (mode == TIMER32_FREE_RUN_MODE)
- HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_MODE_OFS) = 0;
+ BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
+ = 0;
else
ASSERT(false);
/* Setting the resolution of the timer */
if (resolution == TIMER32_1_MODULE6BIT)
- HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 0;
+ BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+ = 0;
else if (resolution == TIMER32_32BIT)
- HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_SIZE_OFS) = 1;
+ BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+ = 1;
else
ASSERT(false);
@@ -63,33 +67,32 @@
|| resolution == TIMER32_PRESCALER_16
|| resolution == TIMER32_PRESCALER_256);
- HWREG32(timer + OFS_TIMER32_CONTROL1) =
- (HWREG32(timer + OFS_TIMER32_CONTROL1)
- & ~TIMER32_CONTROL1_PRESCALE_M) | preScaler;
+ TIMER32_CMSIS(timer)->CONTROL = TIMER32_CMSIS(timer)->CONTROL
+ & (~TIMER32_CONTROL_PRESCALE_MASK) | preScaler;
}
void Timer32_setCount(uint32_t timer, uint32_t count)
{
- if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
- TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
- HWREG32(timer + OFS_TIMER32_LOAD1) = UINT16_MAX;
+ if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+ && (count > UINT16_MAX))
+ TIMER32_CMSIS(timer)->LOAD = UINT16_MAX;
else
- HWREG32(timer + OFS_TIMER32_LOAD1) = count;
+ TIMER32_CMSIS(timer)->LOAD = count;
}
void Timer32_setCountInBackground(uint32_t timer, uint32_t count)
{
- if (!HWREGBIT32(timer + OFS_TIMER32_CONTROL1,
- TIMER32_CONTROL1_SIZE_OFS) && (count > UINT16_MAX))
- HWREG32(timer + OFS_TIMER32_BGLOAD1) = UINT16_MAX;
+ if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+ && (count > UINT16_MAX))
+ TIMER32_CMSIS(timer)->BGLOAD = UINT16_MAX;
else
- HWREG32(timer + OFS_TIMER32_BGLOAD1) = count;
+ TIMER32_CMSIS(timer)->BGLOAD = count;
}
uint32_t Timer32_getValue(uint32_t timer)
{
- return HWREG32(timer + OFS_TIMER32_VALUE1);
+ return TIMER32_CMSIS(timer)->VALUE;
}
void Timer32_startTimer(uint32_t timer, bool oneShot)
@@ -97,40 +100,40 @@
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
if (oneShot)
- HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
- 1;
+ BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
+ = 1;
else
- HWREGBIT8(timer + OFS_TIMER32_CONTROL1, TIMER32_CONTROL1_ONESHOT_OFS) =
- 0;
+ BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
+ = 0;
- HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_ENABLE;
+ TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_ENABLE;
}
void Timer32_haltTimer(uint32_t timer)
{
ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
- HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_ENABLE;
+ TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_ENABLE;
}
void Timer32_enableInterrupt(uint32_t timer)
{
- HWREG32(timer + OFS_TIMER32_CONTROL1) |= TIMER32_CONTROL1_IE;
+ TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_IE;
}
void Timer32_disableInterrupt(uint32_t timer)
{
- HWREG32(timer + OFS_TIMER32_CONTROL1) &= ~TIMER32_CONTROL1_IE;
+ TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_IE;
}
void Timer32_clearInterruptFlag(uint32_t timer)
{
- HWREG32(timer + OFS_TIMER32_INTCLR1) |= 0x01;
+ TIMER32_CMSIS(timer)->INTCLR |= 0x01;
}
uint32_t Timer32_getInterruptStatus(uint32_t timer)
{
- return HWREG32(timer + OFS_TIMER32_MIS1);
+ return TIMER32_CMSIS(timer)->MIS;
}
void Timer32_registerInterrupt(uint32_t timerInterrupt,
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h
index 4fdd0fb..051ea3c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer32.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -63,10 +63,12 @@
// Control specific variables
//
//*****************************************************************************
+#define TIMER32_CMSIS(x) ((Timer32_Type *) x)
+
#define TIMER_OFFSET 0x020
-#define TIMER32_0_MODULE TIMER32_BASE
-#define TIMER32_1_MODULE (TIMER32_BASE + OFS_TIMER32_LOAD2)
+#define TIMER32_0_BASE TIMER32_1
+#define TIMER32_1_BASE TIMER32_2
#define TIMER32_0_INTERRUPT INT_T32_INT1
#define TIMER32_1_INTERRUPT INT_T32_INT2
@@ -94,8 +96,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! \param preScaler is the prescaler (or divider) to apply to the clock
//! source given to the Timer32 module.
@@ -130,8 +132,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//! \param count Value of the timer to set. Note that
//! if the timer is in 16-bit mode and a value is passed in that exceeds
//! UINT16_MAX, the value will be truncated to UINT16_MAX.
@@ -153,8 +155,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//! \param count Value of the timer to set in the background. Note that
//! if the timer is in 16-bit mode and a value is passed in that exceeds
//! UINT16_MAX, the value will be truncated to UINT16_MAX.
@@ -174,8 +176,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! \return The current count of the timer.
//
@@ -190,8 +192,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! \param oneShot sets whether the Timer32 module operates in one shot
//! or continuous mode. In one shot mode, the timer will halt when a zero is
@@ -214,8 +216,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! \return None
//
@@ -228,8 +230,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! Enables the indicated Timer32 interrupt source.
//!
@@ -244,8 +246,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! Disables the indicated Timer32 interrupt source.
//!
@@ -260,8 +262,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! The Timer32 interrupt source is cleared, so that it no longer asserts.
//!
@@ -276,8 +278,8 @@
//!
//! \param timer is the instance of the Timer32 module.
//! Valid parameters must be one of the following values:
-//! - \b TIMER32_0_MODULE
-//! - \b TIMER32_1_MODULE
+//! - \b TIMER32_0_BASE
+//! - \b TIMER32_1_BASE
//!
//! This returns the interrupt status for the Timer32 module. A positive value
//! will indicate that an interrupt is pending while a zero value will indicate
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c
index d8ec5bb..d4f67f9 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,53 +41,53 @@
static void privateTimer_AProcessClockSourceDivider(uint32_t timer,
uint16_t clockSourceDivider)
{
- TIMER_A_CMSIS(timer)->rCTL.r &= ~ID__8;
- TIMER_A_CMSIS(timer)->rEX0.r &= ~TAIDEX_7;
+ TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_ID__8;
+ TIMER_A_CMSIS(timer)->EX0 &= ~TIMER_A_EX0_IDEX_MASK;
switch (clockSourceDivider)
{
case TIMER_A_CLOCKSOURCE_DIVIDER_1:
case TIMER_A_CLOCKSOURCE_DIVIDER_2:
- TIMER_A_CMSIS(timer)->rCTL.r |= ((clockSourceDivider - 1) << 6);
- TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
+ TIMER_A_CMSIS(timer)->CTL |= ((clockSourceDivider - 1) << 6);
+ TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_4:
- TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
- TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
+ TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
+ TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_8:
- TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
- TIMER_A_CMSIS(timer)->rEX0.r = TAIDEX_0;
+ TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
+ TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_3:
case TIMER_A_CLOCKSOURCE_DIVIDER_5:
case TIMER_A_CLOCKSOURCE_DIVIDER_6:
case TIMER_A_CLOCKSOURCE_DIVIDER_7:
- TIMER_A_CMSIS(timer)->rCTL.r |= ID__1;
- TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider - 1);
+ TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__1;
+ TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_10:
case TIMER_A_CLOCKSOURCE_DIVIDER_12:
case TIMER_A_CLOCKSOURCE_DIVIDER_14:
case TIMER_A_CLOCKSOURCE_DIVIDER_16:
- TIMER_A_CMSIS(timer)->rCTL.r |= ID__2;
- TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 2 - 1);
+ TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__2;
+ TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 2 - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_20:
case TIMER_A_CLOCKSOURCE_DIVIDER_24:
case TIMER_A_CLOCKSOURCE_DIVIDER_28:
case TIMER_A_CLOCKSOURCE_DIVIDER_32:
- TIMER_A_CMSIS(timer)->rCTL.r |= ID__4;
- TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 4 - 1);
+ TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
+ TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 4 - 1);
break;
case TIMER_A_CLOCKSOURCE_DIVIDER_40:
case TIMER_A_CLOCKSOURCE_DIVIDER_48:
case TIMER_A_CLOCKSOURCE_DIVIDER_56:
case TIMER_A_CLOCKSOURCE_DIVIDER_64:
- TIMER_A_CMSIS(timer)->rCTL.r |= ID__8;
- TIMER_A_CMSIS(timer)->rEX0.r = (clockSourceDivider / 8 - 1);
+ TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
+ TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 8 - 1);
break;
}
}
@@ -99,7 +99,7 @@
|| (TIMER_A_CONTINUOUS_MODE == timerMode)
|| (TIMER_A_UP_MODE == timerMode));
- TIMER_A_CMSIS(timer)->rCTL.r |= timerMode;
+ TIMER_A_CMSIS(timer)->CTL |= timerMode;
}
void Timer_A_configureContinuousMode(uint32_t timer,
@@ -164,7 +164,7 @@
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
- TIMER_A_CMSIS(timer)->rCTL.r = (TIMER_A_CMSIS(timer)->rCTL.r
+ TIMER_A_CMSIS(timer)->CTL = (TIMER_A_CMSIS(timer)->CTL
& ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+ TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR
+ TIMER_A_TAIE_INTERRUPT_ENABLE))
@@ -191,20 +191,20 @@
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
- TIMER_A_CMSIS(timer)->rCTL.r &=
+ TIMER_A_CMSIS(timer)->CTL &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
- TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + config->timerClear
+ TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + config->timerClear
+ config->timerInterruptEnable_TAIE);
if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
== config->captureCompareInterruptEnable_CCR0_CCIE)
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
else
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
- TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
+ TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
}
void Timer_A_configureUpDownMode(uint32_t timer,
@@ -227,19 +227,19 @@
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
- TIMER_A_CMSIS(timer)->rCTL.r &=
+ TIMER_A_CMSIS(timer)->CTL &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
- TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_STOP_MODE
+ TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_STOP_MODE
+ config->timerClear + config->timerInterruptEnable_TAIE);
if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
== config->captureCompareInterruptEnable_CCR0_CCIE)
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 1;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
else
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCCTL0.r,CCIE_OFS) = 0;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
- TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
+ TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
}
void Timer_A_initCapture(uint32_t timer,
@@ -312,17 +312,18 @@
|| (TIMER_A_OUTPUTMODE_RESET
== config->captureOutputMode));
}
-
- HWREG16(timer + config->captureRegister) =
- (HWREG16(timer + config->captureRegister)
+ uint8_t idx = (config->captureRegister>>1)-1;
+ TIMER_A_CMSIS(timer)->CCTL[idx] =
+ (TIMER_A_CMSIS(timer)->CCTL[idx]
& ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
| TIMER_A_CAPTURE_INPUTSELECT_Vcc
| TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR
- | TIMER_A_TAIE_INTERRUPT_ENABLE | CM_3))
+ | TIMER_A_TAIE_INTERRUPT_ENABLE | TIMER_A_CCTLN_CM_3))
| (config->captureMode | config->captureInputSelect
| config->synchronizeCaptureSource
| config->captureInterruptEnable
- | config->captureOutputMode | CAP);
+ | config->captureOutputMode | TIMER_A_CCTLN_CAP);
+
}
void Timer_A_initCompare(uint32_t timer,
@@ -375,26 +376,27 @@
== config->compareOutputMode));
}
- HWREG16(timer + config->compareRegister) =
- (HWREG16(timer + config->compareRegister)
- & ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
- | TIMER_A_OUTPUTMODE_RESET_SET | CAP))
- | (config->compareInterruptEnable
- + config->compareOutputMode);
+ uint8_t idx = (config->compareRegister>>1)-1;
+ TIMER_A_CMSIS(timer)->CCTL[idx] =
+ (TIMER_A_CMSIS(timer)->CCTL[idx]
+ & ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+ | TIMER_A_OUTPUTMODE_RESET_SET | TIMER_A_CCTLN_CAP))
+ | (config->compareInterruptEnable + config->compareOutputMode);
- HWREG16(timer + config->compareRegister + OFS_TA0R) = config->compareValue;
+ TIMER_A_CMSIS(timer)->CCR[idx] = config->compareValue;
+
}
uint16_t Timer_A_getCounterValue(uint32_t timer)
{
- uint16_t voteOne, voteTwo, res;
+ uint_fast16_t voteOne, voteTwo, res;
- voteTwo = TIMER_A_CMSIS(timer)->rR;
+ voteTwo = TIMER_A_CMSIS(timer)->R;
do
{
voteOne = voteTwo;
- voteTwo = TIMER_A_CMSIS(timer)->rR;
+ voteTwo = TIMER_A_CMSIS(timer)->R;
if (voteTwo > voteOne)
res = voteTwo - voteOne;
@@ -411,7 +413,7 @@
void Timer_A_clearTimer(uint32_t timer)
{
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r , TACLR_OFS) = 1;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL , TIMER_A_CTL_CLR_OFS) = 1;
}
uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
@@ -437,7 +439,8 @@
|| (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT
== synchronizedSetting));
- if (HWREG16(timer + captureCompareRegister) & synchronizedSetting)
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ if (TIMER_A_CMSIS(timer)->CCTL[idx] & synchronizedSetting)
return TIMER_A_CAPTURECOMPARE_INPUT_HIGH;
else
return TIMER_A_CAPTURECOMPARE_INPUT_LOW;
@@ -461,7 +464,8 @@
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
- if (HWREGBIT16(timer + captureCompareRegister, OUT_OFS))
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_OUT_OFS))
return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH;
else
return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW;
@@ -485,15 +489,19 @@
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
- return HWREG16(timer + OFS_TA0R + captureCompareRegister);
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ return (TIMER_A_CMSIS(timer)->CCR[idx]);
}
void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
uint_fast16_t captureCompareRegister,
uint_fast8_t outputModeOutBitValue)
{
- TIMER_A_setOutputForOutputModeOutBitValue(timer, captureCompareRegister,
- outputModeOutBitValue);
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ TIMER_A_CMSIS(timer)->CCTL[idx] =
+ ((TIMER_A_CMSIS(timer)->CCTL[idx])
+ & ~(TIMER_A_OUTPUTMODE_RESET_SET))
+ | (outputModeOutBitValue);
}
void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config)
@@ -536,25 +544,26 @@
privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
- TIMER_A_CMSIS(timer)->rCTL.r &=
+ TIMER_A_CMSIS(timer)->CTL &=
~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+ TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
- TIMER_A_CMSIS(timer)->rCTL.r |= (config->clockSource + TIMER_A_UP_MODE
+ TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_UP_MODE
+ TIMER_A_DO_CLEAR);
- TIMER_A_CMSIS(timer)->rCCR0 = config->timerPeriod;
+ TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
- HWREG16(timer + OFS_TA0CCTL0) &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+ TIMER_A_CMSIS(timer)->CCTL[0] &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+ TIMER_A_OUTPUTMODE_RESET_SET);
- HWREG16(timer + config->compareRegister) |= config->compareOutputMode;
- HWREG16(timer + config->compareRegister + OFS_TA0R) = config->dutyCycle;
+ uint8_t idx = (config->compareRegister>>1) - 1;
+ TIMER_A_CMSIS(timer)->CCTL[idx] |= config->compareOutputMode;
+ TIMER_A_CMSIS(timer)->CCR[idx] = config->dutyCycle;
}
void Timer_A_stopTimer(uint32_t timer)
{
- TIMER_A_CMSIS(timer)->rCTL.r &= ~MC_3;
+ TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_MC_3;
}
void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister,
@@ -569,12 +578,13 @@
|| (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister)
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister));
- HWREG16(timer + compareRegister + OFS_TA0R) = compareValue;
+ uint8_t idx = (compareRegister>>1) - 1;
+ TIMER_A_CMSIS(timer)->CCR[idx] = compareValue;
}
void Timer_A_clearInterruptFlag(uint32_t timer)
{
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIFG_OFS) = 0;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IFG_OFS) = 0;
}
void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
@@ -595,22 +605,23 @@
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
- HWREGBIT16(timer + captureCompareRegister, CCIFG_OFS) = 0;
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIFG_OFS) = 0;
}
void Timer_A_enableInterrupt(uint32_t timer)
{
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 1;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 1;
}
void Timer_A_disableInterrupt(uint32_t timer)
{
- BITBAND_PERI(TIMER_A_CMSIS(timer)->rCTL.r,TAIE_OFS) = 0;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 0;
}
uint32_t Timer_A_getInterruptStatus(uint32_t timer)
{
- return TIMER_A_CMSIS(timer)->rCTL.b.bIFG;
+ return (TIMER_A_CMSIS(timer)->CTL) & TIMER_A_CTL_IFG;
}
void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
@@ -631,7 +642,8 @@
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
- HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 1;
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 1;
}
void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
@@ -652,18 +664,21 @@
|| (TIMER_A_CAPTURECOMPARE_REGISTER_6
== captureCompareRegister));
- HWREGBIT16(timer + captureCompareRegister, CCIE_OFS) = 0;
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 0;
+
}
uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister, uint_fast16_t mask)
{
- return HWREG16(timer + captureCompareRegister) & mask;
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ return (TIMER_A_CMSIS(timer)->CCTL[idx]) & mask;
}
uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer)
{
- if (TIMER_A_CMSIS(timer)->rCTL.r & TAIE)
+ if (TIMER_A_CMSIS(timer)->CTL & TIMER_A_CTL_IE)
{
return Timer_A_getInterruptStatus(timer);
} else
@@ -676,8 +691,9 @@
uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister)
{
- if (HWREGBIT16(timer + captureCompareRegister, CCIE_OFS))
- return Timer_A_getCaptureCompareInterruptStatus(timer,
+ uint8_t idx = (captureCompareRegister>>1) - 1;
+ if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS))
+ return Timer_A_getCaptureCompareInterruptStatus(timer,
captureCompareRegister,
TIMER_A_CAPTURE_OVERFLOW |
TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG);
@@ -692,19 +708,19 @@
{
switch (timer)
{
- case TIMER_A0_MODULE:
+ case TIMER_A0_BASE:
Interrupt_registerInterrupt(INT_TA0_0, intHandler);
Interrupt_enableInterrupt(INT_TA0_0);
break;
- case TIMER_A1_MODULE:
+ case TIMER_A1_BASE:
Interrupt_registerInterrupt(INT_TA1_0, intHandler);
Interrupt_enableInterrupt(INT_TA1_0);
break;
- case TIMER_A2_MODULE:
+ case TIMER_A2_BASE:
Interrupt_registerInterrupt(INT_TA2_0, intHandler);
Interrupt_enableInterrupt(INT_TA2_0);
break;
- case TIMER_A3_MODULE:
+ case TIMER_A3_BASE:
Interrupt_registerInterrupt(INT_TA3_0, intHandler);
Interrupt_enableInterrupt(INT_TA3_0);
break;
@@ -715,19 +731,19 @@
{
switch (timer)
{
- case TIMER_A0_MODULE:
+ case TIMER_A0_BASE:
Interrupt_registerInterrupt(INT_TA0_N, intHandler);
Interrupt_enableInterrupt(INT_TA0_N);
break;
- case TIMER_A1_MODULE:
+ case TIMER_A1_BASE:
Interrupt_registerInterrupt(INT_TA1_N, intHandler);
Interrupt_enableInterrupt(INT_TA1_N);
break;
- case TIMER_A2_MODULE:
+ case TIMER_A2_BASE:
Interrupt_registerInterrupt(INT_TA2_N, intHandler);
Interrupt_enableInterrupt(INT_TA2_N);
break;
- case TIMER_A3_MODULE:
+ case TIMER_A3_BASE:
Interrupt_registerInterrupt(INT_TA3_N, intHandler);
Interrupt_enableInterrupt(INT_TA3_N);
break;
@@ -746,19 +762,19 @@
{
switch (timer)
{
- case TIMER_A0_MODULE:
+ case TIMER_A0_BASE:
Interrupt_disableInterrupt(INT_TA0_0);
Interrupt_unregisterInterrupt(INT_TA0_0);
break;
- case TIMER_A1_MODULE:
+ case TIMER_A1_BASE:
Interrupt_disableInterrupt(INT_TA1_0);
Interrupt_unregisterInterrupt(INT_TA1_0);
break;
- case TIMER_A2_MODULE:
+ case TIMER_A2_BASE:
Interrupt_disableInterrupt(INT_TA2_0);
Interrupt_unregisterInterrupt(INT_TA2_0);
break;
- case TIMER_A3_MODULE:
+ case TIMER_A3_BASE:
Interrupt_disableInterrupt(INT_TA3_0);
Interrupt_unregisterInterrupt(INT_TA3_0);
break;
@@ -769,19 +785,19 @@
{
switch (timer)
{
- case TIMER_A0_MODULE:
+ case TIMER_A0_BASE:
Interrupt_disableInterrupt(INT_TA0_N);
Interrupt_unregisterInterrupt(INT_TA0_N);
break;
- case TIMER_A1_MODULE:
+ case TIMER_A1_BASE:
Interrupt_disableInterrupt(INT_TA1_N);
Interrupt_unregisterInterrupt(INT_TA1_N);
break;
- case TIMER_A2_MODULE:
+ case TIMER_A2_BASE:
Interrupt_disableInterrupt(INT_TA2_N);
Interrupt_unregisterInterrupt(INT_TA2_N);
break;
- case TIMER_A3_MODULE:
+ case TIMER_A3_BASE:
Interrupt_disableInterrupt(INT_TA3_N);
Interrupt_unregisterInterrupt(INT_TA3_N);
break;
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h
index 6fe7f17..d493a3f 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/timer_a.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -63,14 +63,14 @@
// Timer_A Specific Parameters
//
//*****************************************************************************
-#define TIMER_A_CMSIS(x) ((TIMER_A0_Type *) x)
+#define TIMER_A_CMSIS(x) ((Timer_A_Type *) x)
#define TIMER_A_CCR0_INTERRUPT 0x00
#define TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT 0x01
//*****************************************************************************
//
-//! \typedef Timer_A_ContinuousModeConfig
+//! ypedef Timer_A_ContinuousModeConfig
//! \brief Type definition for \link _Timer_A_ContinuousModeConfig \endlink
//! structure
//!
@@ -90,7 +90,7 @@
//*****************************************************************************
//
-//! \typedef Timer_A_UpModeConfig
+//! ypedef Timer_A_UpModeConfig
//! \brief Type definition for \link _Timer_A_UpModeConfig \endlink
//! structure
//!
@@ -112,7 +112,7 @@
//*****************************************************************************
//
-//! \typedef Timer_A_UpDownModeConfig
+//! ypedef Timer_A_UpDownModeConfig
//! \brief Type definition for \link _Timer_A_UpDownModeConfig \endlink
//! structure
//!
@@ -134,7 +134,7 @@
//*****************************************************************************
//
-//! \typedef Timer_A_CaptureModeConfig
+//! ypedef Timer_A_CaptureModeConfig
//! \brief Type definition for \link _Timer_A_CaptureModeConfig \endlink
//! structure
//!
@@ -156,7 +156,7 @@
//*****************************************************************************
//
-//! \typedef Timer_A_CompareModeConfig
+//! ypedef Timer_A_CompareModeConfig
//! \brief Type definition for \link _Timer_A_CompareModeConfig \endlink
//! structure
//!
@@ -176,7 +176,7 @@
//*****************************************************************************
//
-//! \typedef Timer_A_PWMConfig
+//! ypedef Timer_A_PWMConfig
//! \brief Type definition for \link _Timer_A_PWMConfig \endlink
//! structure
//!
@@ -237,17 +237,17 @@
// The following are values that can be passed to the timerMode parameter
//
//*****************************************************************************
-#define TIMER_A_STOP_MODE MC_0
-#define TIMER_A_UP_MODE MC_1
-#define TIMER_A_CONTINUOUS_MODE MC_2
-#define TIMER_A_UPDOWN_MODE MC_3
+#define TIMER_A_STOP_MODE TIMER_A_CTL_MC_0
+#define TIMER_A_UP_MODE TIMER_A_CTL_MC_1
+#define TIMER_A_CONTINUOUS_MODE TIMER_A_CTL_MC_2
+#define TIMER_A_UPDOWN_MODE TIMER_A_CTL_MC_3
//*****************************************************************************
//
// The following are values that can be passed to the timerClear parameter
//
//*****************************************************************************
-#define TIMER_A_DO_CLEAR TACLR
+#define TIMER_A_DO_CLEAR TIMER_A_CTL_CLR
#define TIMER_A_SKIP_CLEAR 0x00
//*****************************************************************************
@@ -255,10 +255,10 @@
// The following are values that can be passed to the clockSource parameter
//
//*****************************************************************************
-#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TASSEL__TACLK
-#define TIMER_A_CLOCKSOURCE_ACLK TASSEL__ACLK
-#define TIMER_A_CLOCKSOURCE_SMCLK TASSEL__SMCLK
-#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TASSEL__INCLK
+#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TIMER_A_CTL_SSEL__TACLK
+#define TIMER_A_CLOCKSOURCE_ACLK TIMER_A_CTL_SSEL__ACLK
+#define TIMER_A_CLOCKSOURCE_SMCLK TIMER_A_CTL_SSEL__SMCLK
+#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TIMER_A_CTL_SSEL__INCLK
//*****************************************************************************
//
@@ -266,7 +266,7 @@
// parameter
//
//*****************************************************************************
-#define TIMER_A_TAIE_INTERRUPT_ENABLE TAIE
+#define TIMER_A_TAIE_INTERRUPT_ENABLE TIMER_A_CTL_IE
#define TIMER_A_TAIE_INTERRUPT_DISABLE 0x00
//*****************************************************************************
@@ -275,7 +275,7 @@
// captureCompareInterruptEnable_CCR0_CCIE parameter
//
//*****************************************************************************
-#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE CCIE
+#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE TIMER_A_CCTLN_CCIE
#define TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE 0x00
//*****************************************************************************
@@ -285,7 +285,7 @@
//
//*****************************************************************************
#define TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00
-#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE TIMER_A_CCTLN_CCIE
//*****************************************************************************
//
@@ -293,10 +293,10 @@
// parameter
//
//*****************************************************************************
-#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA CCIS_0
-#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB CCIS_1
-#define TIMER_A_CAPTURE_INPUTSELECT_GND CCIS_2
-#define TIMER_A_CAPTURE_INPUTSELECT_Vcc CCIS_3
+#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA TIMER_A_CCTLN_CCIS_0
+#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB TIMER_A_CCTLN_CCIS_1
+#define TIMER_A_CAPTURE_INPUTSELECT_GND TIMER_A_CCTLN_CCIS_2
+#define TIMER_A_CAPTURE_INPUTSELECT_Vcc TIMER_A_CCTLN_CCIS_3
//*****************************************************************************
//
@@ -304,14 +304,14 @@
// parameter
//
//*****************************************************************************
-#define TIMER_A_OUTPUTMODE_OUTBITVALUE OUTMOD_0
-#define TIMER_A_OUTPUTMODE_SET OUTMOD_1
-#define TIMER_A_OUTPUTMODE_TOGGLE_RESET OUTMOD_2
-#define TIMER_A_OUTPUTMODE_SET_RESET OUTMOD_3
-#define TIMER_A_OUTPUTMODE_TOGGLE OUTMOD_4
-#define TIMER_A_OUTPUTMODE_RESET OUTMOD_5
-#define TIMER_A_OUTPUTMODE_TOGGLE_SET OUTMOD_6
-#define TIMER_A_OUTPUTMODE_RESET_SET OUTMOD_7
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE TIMER_A_CCTLN_OUTMOD_0
+#define TIMER_A_OUTPUTMODE_SET TIMER_A_CCTLN_OUTMOD_1
+#define TIMER_A_OUTPUTMODE_TOGGLE_RESET TIMER_A_CCTLN_OUTMOD_2
+#define TIMER_A_OUTPUTMODE_SET_RESET TIMER_A_CCTLN_OUTMOD_3
+#define TIMER_A_OUTPUTMODE_TOGGLE TIMER_A_CCTLN_OUTMOD_4
+#define TIMER_A_OUTPUTMODE_RESET TIMER_A_CCTLN_OUTMOD_5
+#define TIMER_A_OUTPUTMODE_TOGGLE_SET TIMER_A_CCTLN_OUTMOD_6
+#define TIMER_A_OUTPUTMODE_RESET_SET TIMER_A_CCTLN_OUTMOD_7
//*****************************************************************************
//
@@ -331,10 +331,10 @@
// The following are values that can be passed to the captureMode parameter
//
//*****************************************************************************
-#define TIMER_A_CAPTUREMODE_NO_CAPTURE CM_0
-#define TIMER_A_CAPTUREMODE_RISING_EDGE CM_1
-#define TIMER_A_CAPTUREMODE_FALLING_EDGE CM_2
-#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3
+#define TIMER_A_CAPTUREMODE_NO_CAPTURE TIMER_A_CCTLN_CM_0
+#define TIMER_A_CAPTUREMODE_RISING_EDGE TIMER_A_CCTLN_CM_1
+#define TIMER_A_CAPTUREMODE_FALLING_EDGE TIMER_A_CCTLN_CM_2
+#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE TIMER_A_CCTLN_CM_3
//*****************************************************************************
//
@@ -343,23 +343,23 @@
//
//*****************************************************************************
#define TIMER_A_CAPTURE_ASYNCHRONOUS 0x00
-#define TIMER_A_CAPTURE_SYNCHRONOUS SCS
+#define TIMER_A_CAPTURE_SYNCHRONOUS TIMER_A_CCTLN_SCS
//*****************************************************************************
//
// The following are values that can be passed to the mask parameter
//
//*****************************************************************************
-#define TIMER_A_CAPTURE_OVERFLOW COV
-#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG
+#define TIMER_A_CAPTURE_OVERFLOW TIMER_A_CCTLN_COV
+#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG TIMER_A_CCTLN_CCIFG
//*****************************************************************************
//
// The following are values that can be passed to the synchronized parameter
//
//*****************************************************************************
-#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI
-#define TIMER_A_READ_CAPTURE_COMPARE_INPUT CCI
+#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT TIMER_A_CCTLN_SCCI
+#define TIMER_A_READ_CAPTURE_COMPARE_INPUT TIMER_A_CCTLN_CCI
#define TIMER_A_CAPTURECOMPARE_INPUT_HIGH 0x01
@@ -371,7 +371,7 @@
// parameter
//
//*****************************************************************************
-#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH OUT
+#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH TIMER_A_CCTLN_OUT
#define TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW 0x00
//*****************************************************************************
@@ -400,10 +400,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param timerMode selects Clock source. Valid values are
//! - \b TIMER_A_CONTINUOUS_MODE [Default value]
//! - \b TIMER_A_UPDOWN_MODE
@@ -424,10 +424,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A continuous mode
//!
//! <hr>
@@ -486,10 +486,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A Up mode
//!
//! <hr>
@@ -553,10 +553,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A UpDown mode
//!
//! <hr>
@@ -620,10 +620,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A capture mode
//!
//! <hr>
@@ -682,10 +682,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A compare mode
//!
//! <hr>
@@ -730,10 +730,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \returns None
//
@@ -746,10 +746,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@@ -780,10 +780,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@@ -809,10 +809,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@@ -837,10 +837,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture register being used.
//! are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@@ -870,10 +870,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param config Configuration structure for Timer_A PWM mode
//!
//! <hr>
@@ -942,10 +942,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \returns None
//
@@ -958,10 +958,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param compareRegister selects the Capture register being used. Valid
//! values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@@ -993,10 +993,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \returns The value of the specified timer
//
@@ -1009,10 +1009,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \return None
//
@@ -1025,10 +1025,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister selects the Capture-compare register being
//! used. Valid values are
//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0
@@ -1053,10 +1053,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \return None
//
@@ -1069,10 +1069,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \return None
//
@@ -1085,10 +1085,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \return uint32_t. Return interrupt status. Valid values are
//! - \b TIMER_A_INTERRUPT_PENDING
@@ -1106,10 +1106,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \return uint32_t. Return interrupt status. Valid values are
//! - \b TIMER_A_INTERRUPT_PENDING
@@ -1124,10 +1124,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \return None
@@ -1142,10 +1142,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \return None
@@ -1160,10 +1160,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \param mask is the mask for the interrupt status
@@ -1177,7 +1177,7 @@
//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG
//
//*****************************************************************************
-uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
+extern uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
uint_fast16_t captureCompareRegister, uint_fast16_t mask);
//*****************************************************************************
@@ -1189,10 +1189,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//! \param captureCompareRegister is the selected capture compare register
//!
//! \returns uint32_t. The mask of the set flags.
@@ -1210,10 +1210,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \param interruptSelect Selects which timer interrupt handler to
//! register. For the timer module, there are two separate interrupt handlers
@@ -1244,10 +1244,10 @@
//!
//! \param timer is the instance of the Timer_A module. Valid parameters
//! vary from part to part, but can include:
-//! - \b TIMER_A0_MODULE
-//! - \b TIMER_A1_MODULE
-//! - \b TIMER_A2_MODULE
-//! - \b TIMER_A3_MODULE
+//! - \b TIMER_A0_BASE
+//! - \b TIMER_A1_BASE
+//! - \b TIMER_A2_BASE
+//! - \b TIMER_A3_BASE
//!
//! \param interruptSelect Selects which timer interrupt handler to
//! register. For the timer module, there are two separate interrupt handlers
@@ -1270,22 +1270,15 @@
uint_fast8_t interruptSelect);
/* Backwards Compatibility Layer */
-#define TIMER_A_startCounter Timer_A_startCounter
-#define TIMER_A_clearTimerInterruptFlag Timer_A_clearInterruptFlag
-#define TIMER_A_clearCaptureCompareInterruptFlag Timer_A_clearCaptureCompareInterrupt
-#define TIMER_A_getCounterValue Timer_A_getCounterValue
-#define TIMER_A_setCompareValue Timer_A_setCompareValue
-#define TIMER_A_stop Timer_A_stopTimer
-#define TIMER_A_setOutputForOutputModeOutBitValue Timer_A_setOutputForOutputModeOutBitValue
-#define TIMER_A_enableInterrupt Timer_A_enableInterrupt
-#define TIMER_A_disableInterrupt Timer_A_disableInterrupt
-#define TIMER_A_getInterruptStatus Timer_A_getInterruptStatus
-#define TIMER_A_enableCaptureCompareInterrupt Timer_A_enableCaptureCompareInterrupt
-#define TIMER_A_disableCaptureCompareInterrupt Timer_A_disableCaptureCompareInterrupt
-#define TIMER_A_getCaptureCompareInterruptStatus Timer_A_getCaptureCompareInterruptStatus
-#define TIMER_A_clear Timer_A_clearTimer
-#define TIMER_A_getSynchronizedCaptureCompareInput Timer_A_getSynchronizedCaptureCompareInput
-#define TIMER_A_getCaptureCompareCount Timer_A_getCaptureCompareCount
+#define Timer_A_clearTimerInterrupt Timer_A_clearInterruptFlag
+#define Timer_A_clear Timer_A_clearTimer
+#define Timer_A_initCaptureMode Timer_A_initCapture
+#define Timer_A_initCompareMode Timer_A_initCompare
+#define Timer_A_initContinuousMode Timer_A_configureContinuousMode
+#define Timer_A_initUpDownMode Timer_A_configureUpDownMode
+#define Timer_A_initUpMode Timer_A_configureUpMode
+#define Timer_A_outputPWM Timer_A_generatePWM
+#define Timer_A_stop Timer_A_stopTimer
//*****************************************************************************
//
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c
index a3fb2ea..e595126 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -71,51 +71,51 @@
|| (EUSCI_A_UART_EVEN_PARITY == config->parity));
/* Disable the USCI Module */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/* Clock source select */
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_3)
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
| config->selectClockSource;
/* MSB, LSB select */
if (config->msborLsbFirst)
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
else
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCMSB_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
/* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
if (config->numberofStopBits)
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
else
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSPB_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
/* Parity */
switch (config->parity)
{
case EUSCI_A_UART_NO_PARITY:
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
break;
case EUSCI_A_UART_ODD_PARITY:
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
break;
case EUSCI_A_UART_EVEN_PARITY:
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPEN_OFS) = 1;
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCPAR_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
break;
}
/* BaudRate Control Register */
- EUSCI_A_CMSIS(moduleInstance)->rBRW = config->clockPrescalar;
- EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = ((config->secondModReg << 8)
+ EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
+ EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
+ (config->firstModReg << 4) + config->overSampling);
/* Asynchronous mode & 8 bit character select & clear mode */
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
- & ~(UCSYNC | UC7BIT | UCMODE_3 | UCRXEIE | UCBRKIE | UCDORM
- | UCTXADDR | UCTXBRK)) | config->uartMode;
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+ & ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
+ | EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
return retVal;
}
@@ -123,33 +123,33 @@
void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
/* If interrupts are not used, poll for flags */
- if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
- while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
+ while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitData;
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
}
uint8_t UART_receiveData(uint32_t moduleInstance)
{
/* If interrupts are not used, poll for flags */
- if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCRXIE_OFS))
- while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS))
+ if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__RXIE_OFS))
+ while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
;
- return EUSCI_A_CMSIS(moduleInstance)->rRXBUF.r;
+ return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
void UART_enableModule(uint32_t moduleInstance)
{
/* Reset the UCSWRST bit to enable the USCI Module */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
}
void UART_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
@@ -164,56 +164,56 @@
+ EUSCI_A_UART_ADDRESS_RECEIVED
+ EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
- return EUSCI_A_CMSIS(moduleInstance)->rSTATW.r & mask;
+ return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
}
void UART_setDormant(uint32_t moduleInstance)
{
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;
}
void UART_resetDormant(uint32_t moduleInstance)
{
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCDORM_OFS) = 0;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
}
void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
{
/* Set UCTXADDR bit */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXADDR_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
/* Place next byte to be sent into the transmit buffer */
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = transmitAddress;
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
}
void UART_transmitBreak(uint32_t moduleInstance)
{
/* Set UCTXADDR bit */
- BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCTXBRK_OFS) = 1;
+ BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
/* If current mode is automatic baud-rate detection */
if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
- == (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
+ == (EUSCI_A_CMSIS(moduleInstance)->CTLW0
& EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r =
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF =
EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
else
- EUSCI_A_CMSIS(moduleInstance)->rTXBUF.r = DEFAULT_SYNC;
+ EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
/* If interrupts are not used, poll for flags */
- if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS))
- while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS))
+ if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
+ while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
}
uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
- return moduleInstance + OFS_UCA0RXBUF;
+ return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
{
- return moduleInstance + OFS_UCA0TXBUF;
+ return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
}
void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
@@ -224,15 +224,15 @@
|| (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
- EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r =
- (EUSCI_A_CMSIS(moduleInstance)->rCTLW1.r & ~(UCGLIT_M))
+ EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
+ (EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
| deglitchTime;
}
void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
- uint8_t locMask;
+ uint_fast8_t locMask;
ASSERT(
!(mask
@@ -248,17 +248,17 @@
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rIE.r |= locMask;
+ EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r |= locMask;
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
}
void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
- uint8_t locMask;
+ uint_fast8_t locMask;
ASSERT(
!(mask
@@ -273,12 +273,12 @@
& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rIE.r &= ~locMask;
+ EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
- EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r &= ~locMask;
+ EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;
}
uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
@@ -290,14 +290,14 @@
| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
- return EUSCI_A_CMSIS(moduleInstance)->rIFG.r & mask;
+ return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
}
uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
{
uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
- uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->rIE.r;
+ uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
{
@@ -309,7 +309,7 @@
intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
}
- intEnabled = EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r;
+ intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
{
@@ -334,29 +334,29 @@
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
//Clear the UART interrupt source.
- EUSCI_A_CMSIS(moduleInstance)->rIFG.r &= ~(mask);
+ EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
}
void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
Interrupt_enableInterrupt(INT_EUSCIA3);
break;
@@ -370,22 +370,22 @@
{
switch (moduleInstance)
{
- case EUSCI_A0_MODULE:
+ case EUSCI_A0_BASE:
Interrupt_disableInterrupt(INT_EUSCIA0);
Interrupt_unregisterInterrupt(INT_EUSCIA0);
break;
- case EUSCI_A1_MODULE:
+ case EUSCI_A1_BASE:
Interrupt_disableInterrupt(INT_EUSCIA1);
Interrupt_unregisterInterrupt(INT_EUSCIA1);
break;
-#ifdef EUSCI_A2_MODULE
- case EUSCI_A2_MODULE:
+#ifdef EUSCI_A2_BASE
+ case EUSCI_A2_BASE:
Interrupt_disableInterrupt(INT_EUSCIA2);
Interrupt_unregisterInterrupt(INT_EUSCIA2);
break;
#endif
-#ifdef EUSCI_A3_MODULE
- case EUSCI_A3_MODULE:
+#ifdef EUSCI_A3_BASE
+ case EUSCI_A3_BASE:
Interrupt_disableInterrupt(INT_EUSCIA3);
Interrupt_unregisterInterrupt(INT_EUSCIA3);
break;
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h
index d9f9899..515ff3c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/uart.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -61,60 +61,60 @@
#include <msp.h>
#include "eusci.h"
-#define DEFAULT_SYNC 0x00
-#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55
+#define DEFAULT_SYNC 0x00
+#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55
-#define EUSCI_A_UART_NO_PARITY 0x00
-#define EUSCI_A_UART_ODD_PARITY 0x01
-#define EUSCI_A_UART_EVEN_PARITY 0x02
+#define EUSCI_A_UART_NO_PARITY 0x00
+#define EUSCI_A_UART_ODD_PARITY 0x01
+#define EUSCI_A_UART_EVEN_PARITY 0x02
-#define EUSCI_A_UART_MSB_FIRST UCMSB
-#define EUSCI_A_UART_LSB_FIRST 0x00
+#define EUSCI_A_UART_MSB_FIRST EUSCI_A_CTLW0_MSB
+#define EUSCI_A_UART_LSB_FIRST 0x00
-#define EUSCI_A_UART_MODE UCMODE_0
-#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1
-#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2
-#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3
+#define EUSCI_A_UART_MODE EUSCI_A_CTLW0_MODE_0
+#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_1
+#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_2
+#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE EUSCI_A_CTLW0_MODE_3
-#define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
-#define EUSCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK
+#define EUSCI_A_UART_CLOCKSOURCE_SMCLK EUSCI_A_CTLW0_SSEL__SMCLK
+#define EUSCI_A_UART_CLOCKSOURCE_ACLK EUSCI_A_CTLW0_SSEL__ACLK
-#define EUSCI_A_UART_ONE_STOP_BIT 0x00
-#define EUSCI_A_UART_TWO_STOP_BITS UCSPB
+#define EUSCI_A_UART_ONE_STOP_BIT 0x00
+#define EUSCI_A_UART_TWO_STOP_BITS EUSCI_A_CTLW0_SPB
-#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01
-#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00
+#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01
+#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00
-#define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE
-#define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE
-#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE
-#define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE
-#define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE
-#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE
+#define EUSCI_A_UART_RECEIVE_INTERRUPT EUSCI_A_IE_RXIE
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT EUSCI_A_IE_TXIE
+#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT EUSCI_A_CTLW0_RXEIE
+#define EUSCI_A_UART_BREAKCHAR_INTERRUPT EUSCI_A_CTLW0_BRKIE
+#define EUSCI_A_UART_STARTBIT_INTERRUPT EUSCI_A_IE_STTIE
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT EUSCI_B_IE_STPIE
-#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG
-#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG
-#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG
-#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG
+#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG EUSCI_A_IFG_RXIFG
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG EUSCI_A_IFG_TXIFG
+#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG EUSCI_A_IFG_STTIFG
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG EUSCI_A_IFG_TXCPTIFG
-#define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN
-#define EUSCI_A_UART_FRAMING_ERROR UCFE
-#define EUSCI_A_UART_OVERRUN_ERROR UCOE
-#define EUSCI_A_UART_PARITY_ERROR UCPE
-#define EUSCI_A_UART_BREAK_DETECT UCBRK
-#define EUSCI_A_UART_RECEIVE_ERROR UCRXERR
-#define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR
-#define EUSCI_A_UART_IDLELINE UCIDLE
-#define EUSCI_A_UART_BUSY UCBUSY
+#define EUSCI_A_UART_LISTEN_ENABLE EUSCI_A_STATW_LISTEN
+#define EUSCI_A_UART_FRAMING_ERROR EUSCI_A_STATW_FE
+#define EUSCI_A_UART_OVERRUN_ERROR EUSCI_A_STATW_OE
+#define EUSCI_A_UART_PARITY_ERROR EUSCI_A_STATW_PE
+#define EUSCI_A_UART_BREAK_DETECT EUSCI_A_STATW_BRK
+#define EUSCI_A_UART_RECEIVE_ERROR EUSCI_A_STATW_RXERR
+#define EUSCI_A_UART_ADDRESS_RECEIVED EUSCI_A_STATW_ADDR_IDLE
+#define EUSCI_A_UART_IDLELINE EUSCI_A_STATW_ADDR_IDLE
+#define EUSCI_A_UART_BUSY EUSCI_A_STATW_BUSY
-#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00
-#define EUSCI_A_UART_DEGLITCH_TIME_50ns 0x0001
-#define EUSCI_A_UART_DEGLITCH_TIME_100ns 0x0002
-#define EUSCI_A_UART_DEGLITCH_TIME_200ns (0x0001 + 0x0002)
+#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00
+#define EUSCI_A_UART_DEGLITCH_TIME_50ns 0x0001
+#define EUSCI_A_UART_DEGLITCH_TIME_100ns 0x0002
+#define EUSCI_A_UART_DEGLITCH_TIME_200ns (0x0001 + 0x0002)
//*****************************************************************************
//
-//! \typedef eUSCI_eUSCI_UART_Config
+//! ypedef eUSCI_eUSCI_UART_Config
//! \brief Type definition for \link _eUSCI_UART_Config \endlink
//! structure
//!
@@ -145,10 +145,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! \param config Configuration structure for the UART module
//!
//! <hr>
@@ -218,10 +218,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -243,10 +243,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -267,10 +267,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -290,10 +290,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -313,10 +313,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -349,10 +349,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -375,10 +375,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -399,10 +399,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -427,10 +427,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! asEUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -448,10 +448,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -470,10 +470,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -492,10 +492,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -522,10 +522,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -557,10 +557,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -591,10 +591,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -624,10 +624,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -645,10 +645,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode
@@ -674,10 +674,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode.
@@ -703,10 +703,10 @@
//!
//! \param moduleInstance is the instance of the eUSCI A (UART) module.
//! Valid parameters vary from part to part, but can include:
-//! - \b EUSCI_A0_MODULE
-//! - \b EUSCI_A1_MODULE
-//! - \b EUSCI_A2_MODULE
-//! - \b EUSCI_A3_MODULE
+//! - \b EUSCI_A0_BASE
+//! - \b EUSCI_A1_BASE
+//! - \b EUSCI_A2_BASE
+//! - \b EUSCI_A3_BASE
//! <br> It is important to note that for eUSCI modules, only "A" modules such
//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
//! UART mode.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c
index b3b3b85..094a6f5 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.c
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,31 +45,31 @@
void WDT_A_holdTimer(void)
{
//Set Hold bit
- uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTHOLD);
+ uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_HOLD);
- WDT_A->rCTL.r = WDTPW + newWDTStatus;
+ WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
}
void WDT_A_startTimer(void)
{
//Reset Hold bit
- uint8_t newWDTStatus = (WDT_A->rCTL.r & ~(WDTHOLD));
+ uint8_t newWDTStatus = (WDT_A->CTL & ~(WDT_A_CTL_HOLD));
- WDT_A->rCTL.r = WDTPW + newWDTStatus;
+ WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
}
void WDT_A_clearTimer(void)
{
//Set Counter Clear bit
- uint8_t newWDTStatus = (WDT_A->rCTL.r | WDTCNTCL);
+ uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_CNTCL);
- WDT_A->rCTL.r = WDTPW + newWDTStatus;
+ WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
}
void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
uint_fast8_t clockIterations)
{
- WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD +
+ WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD +
clockSelect + clockIterations;
}
@@ -77,7 +77,7 @@
uint_fast8_t clockIterations)
{
- WDT_A->rCTL.r = WDTPW + WDTCNTCL + WDTHOLD + WDTTMSEL
+ WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD + WDT_A_CTL_TMSEL
+ clockSelect + clockIterations;
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h
index 3c215bd..7d31be8 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/wdt_a.h
@@ -1,10 +1,10 @@
/*
* -------------------------------------------
- * MSP432 DriverLib - v01_04_00_18
+ * MSP432 DriverLib - v3_10_00_09
* -------------------------------------------
*
* --COPYRIGHT--,BSD,BSD
- * Copyright (c) 2015, Texas Instruments Incorporated
+ * Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -68,10 +68,11 @@
// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
//
//*****************************************************************************
-#define WDT_A_CLOCKSOURCE_SMCLK (WDTSSEL_0)
-#define WDT_A_CLOCKSOURCE_ACLK (WDTSSEL_1)
-#define WDT_A_CLOCKSOURCE_VLOCLK (WDTSSEL_2)
-#define WDT_A_CLOCKSOURCE_XCLK (WDTSSEL_3)
+#define WDT_A_CLOCKSOURCE_SMCLK (WDT_A_CTL_SSEL_0)
+#define WDT_A_CLOCKSOURCE_ACLK (WDT_A_CTL_SSEL_1)
+#define WDT_A_CLOCKSOURCE_VLOCLK (WDT_A_CTL_SSEL_2)
+#define WDT_A_CLOCKSOURCE_XCLK (WDT_A_CTL_SSEL_3)
+#define WDT_A_CLOCKSOURCE_BCLK (WDT_A_CTL_SSEL_4)
//*****************************************************************************
//
@@ -79,14 +80,14 @@
// for functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
//
//*****************************************************************************
-#define WDT_A_CLOCKDIVIDER_2G (WDTIS_0)
-#define WDT_A_CLOCKDIVIDER_128M (WDTIS_1)
-#define WDT_A_CLOCKDIVIDER_8192K (WDTIS_2)
-#define WDT_A_CLOCKDIVIDER_512K (WDTIS_3)
-#define WDT_A_CLOCKDIVIDER_32K (WDTIS_4)
-#define WDT_A_CLOCKDIVIDER_8192 (WDTIS_5)
-#define WDT_A_CLOCKDIVIDER_512 (WDTIS_6)
-#define WDT_A_CLOCKDIVIDER_64 (WDTIS_7)
+#define WDT_A_CLOCKDIVIDER_2G (WDT_A_CTL_IS_0)
+#define WDT_A_CLOCKDIVIDER_128M (WDT_A_CTL_IS_1)
+#define WDT_A_CLOCKDIVIDER_8192K (WDT_A_CTL_IS_2)
+#define WDT_A_CLOCKDIVIDER_512K (WDT_A_CTL_IS_3)
+#define WDT_A_CLOCKDIVIDER_32K (WDT_A_CTL_IS_4)
+#define WDT_A_CLOCKDIVIDER_8192 (WDT_A_CTL_IS_5)
+#define WDT_A_CLOCKDIVIDER_512 (WDT_A_CTL_IS_6)
+#define WDT_A_CLOCKDIVIDER_64 (WDT_A_CTL_IS_7)
#define WDT_A_CLOCKITERATIONS_2G WDT_A_CLOCKDIVIDER_2G
#define WDT_A_CLOCKITERATIONS_128M WDT_A_CLOCKDIVIDER_128M
#define WDT_A_CLOCKITERATIONS_8192K WDT_A_CLOCKDIVIDER_8192K
@@ -146,7 +147,7 @@
//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
//! - \b WDT_A_CLOCKSOURCE_ACLK
//! - \b WDT_A_CLOCKSOURCE_VLOCLK
-//! - \b WDT_A_CLOCKSOURCE_XCLK
+//! - \b WDT_A_CLOCKSOURCE_BCLK
//! \param clockIterations is the number of clock iterations for a watchdog
//! timeout.
//! Valid values are
@@ -178,7 +179,7 @@
//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
//! - \b WDT_A_CLOCKSOURCE_ACLK
//! - \b WDT_A_CLOCKSOURCE_VLOCLK
-//! - \b WDT_A_CLOCKSOURCE_XCLK
+//! - \b WDT_A_CLOCKSOURCE_BCLK
//! \param clockIterations is the number of clock iterations for a watchdog
//! interval.
//! Valid values are
@@ -264,7 +265,7 @@
/* Defines for future devices that might have multiple instances */
#define WDT_A_holdTimerMultipleTimer(a) WDT_A_holdTimer()
#define WDT_A_startTimerMultipleTimer(a) WDT_A_startTimer()
-#define WDT_A_resetTimerMultipleTimer(a) WDT_A_resetTimer()
+#define WDT_A_resetTimerMultipleTimer(a) WDT_A_clearTimer()
#define WDT_A_initWatchdogTimerMultipleTimer(a,b,c) WDT_A_initWatchdogTimer(b,c)
#define WDT_A_initIntervalTimerMultipleTimer(a,b,c) WDT_A_initIntervalTimer(b,c)
#define WDT_A_registerInterruptMultipleTimer(a,b) WDT_A_registerInterrupt(b)
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c
index b143f4c..bef0c67 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/main.c
@@ -122,7 +122,7 @@
/* The configCREATE_SIMPLE_TICKLESS_DEMO setting is described at the top
of this file. */
- #if configCREATE_SIMPLE_TICKLESS_DEMO == 1
+ #if( configCREATE_SIMPLE_TICKLESS_DEMO == 1 )
{
main_blinky();
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt
index 9342bb4..075af26 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dbgdt
@@ -19,7 +19,7 @@
- <Column0>233</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+ <Column0>277</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<col-names>
@@ -39,7 +39,7 @@
- <Wnd1>
+ <Wnd3>
<Tabs>
<Tab>
<Identity>TabID-24437-20285</Identity>
@@ -55,7 +55,7 @@
</Tab>
</Tabs>
- <SelectedTab>0</SelectedTab></Wnd1><Wnd3>
+ <SelectedTab>0</SelectedTab></Wnd3><Wnd4>
<Tabs>
<Tab>
<Identity>TabID-2417-20288</Identity>
@@ -67,20 +67,20 @@
</Tab>
</Tabs>
- <SelectedTab>0</SelectedTab></Wnd3></Windows>
+ <SelectedTab>0</SelectedTab></Wnd4></Windows>
<Editor>
- <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>100</YPos2><SelStart2>5615</SelStart2><SelEnd2>5615</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\tasks.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>2232</YPos2><SelStart2>76407</SelStart2><SelEnd2>76435</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\include\StackMacros.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>76</YPos2><SelStart2>4839</SelStart2><SelEnd2>4839</SelEnd2></Tab><ActiveTab>2</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>74</YPos2><SelStart2>4540</SelStart2><SelEnd2>4540</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>96</YPos2><SelStart2>5983</SelStart2><SelEnd2>5983</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>39</YPos2><SelStart2>2555</SelStart2><SelEnd2>2555</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\SimplyBlinkyDemo\main_blinky.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>149</YPos2><SelStart2>8275</SelStart2><SelEnd2>8275</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Full_Demo\main_full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>256</YPos2><SelStart2>11768</SelStart2><SelEnd2>11768</SelEnd2></Tab><ActiveTab>3</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
- <Top><Row0><Sizes><Toolbar-00C4A4B8><key>iaridepm.enu1</key></Toolbar-00C4A4B8></Sizes></Row0><Row1><Sizes><Toolbar-0F081000><key>debuggergui.enu1</key></Toolbar-0F081000></Sizes></Row1><Row2><Sizes><Toolbar-0F0810C8><key>armjet.enu1</key></Toolbar-0F0810C8></Sizes></Row2></Top><Left><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>585</Bottom><Right>307</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>183929</sizeVertCX><sizeVertCY>596545</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>307</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>309</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>314024</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+ <Top><Row0><Sizes><Toolbar-026F17B0><key>iaridepm.enu1</key></Toolbar-026F17B0></Sizes></Row0><Row1><Sizes><Toolbar-07156000><key>debuggergui.enu1</key></Toolbar-07156000></Sizes></Row1><Row2><Sizes><Toolbar-07157838><key>armjet.enu1</key></Toolbar-07157838></Sizes></Row2></Top><Left><Row0><Sizes><Wnd4><Rect><Top>-2</Top><Left>-2</Left><Bottom>688</Bottom><Right>351</Right><x>-2</x><y>-2</y><xscreen>229</xscreen><yscreen>230</yscreen><sizeHorzCX>119271</sizeHorzCX><sizeHorzCY>202822</sizeHorzCY><sizeVertCX>183854</sizeVertCX><sizeVertCY>608466</sizeVertCY></Rect></Wnd4></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>354</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>356</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>313933</sizeHorzCY><sizeVertCX>119271</sizeVertCX><sizeVertCY>202822</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni
index 32d1b18..dca95f7 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.dni
@@ -9,17 +9,17 @@
LimitSize=0
ByteLimit=50
[PlDriver]
-MemConfigValue=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\TexasInstruments\MSP432P401R.svd
+MemConfigValue=C:\DevTools\IAR Systems\Embedded Workbench 7.3\arm\CONFIG\debugger\TexasInstruments\MSP432P401R.ddf
FirstRun=0
[Jet]
-JetConnSerialNo=73866
+JetConnSerialNo=59065
JetConnFoundProbes=
DisableInterrupts=0
MultiCoreRunAll=0
OnlineReset=Software
PrevWtdReset=System
[DebugChecksum]
-Checksum=-1201177865
+Checksum=-851533712
[Exceptions]
StopOnUncaught=_ 0
StopOnThrow=_ 0
@@ -30,8 +30,8 @@
[SWOManager]
SamplingDivider=8192
OverrideClock=0
-CpuClock=696008061
-SwoClock=560889384
+CpuClock=542261577
+SwoClock=1953724755
DataLogMode=0
ItmPortsEnabled=63
ItmTermIOPorts=1
@@ -64,31 +64,6 @@
ITMlogFile=$PROJ_DIR$\ITM.log
[Breakpoints]
Count=0
-[PlCacheRanges]
-CustomRanges0=0 0 536870912 1 0
-CustomRangesText0=Code
-CustomRanges1=0 536870912 33554432 0 0
-CustomRangesText1=SRAM
-CustomRanges2=0 570425344 33554432 0 0
-CustomRangesText2=bit-banding
-CustomRanges3=0 1073741824 33554432 2 0
-CustomRangesText3=Peripheral
-CustomRanges4=0 1107296256 33554432 2 0
-CustomRangesText4=bit-banding
-CustomRanges5=0 3758096384 536870912 2 0
-CustomRangesText5=Private peripheral
-[Trace2]
-Enabled=0
-ShowSource=0
-[SWOTraceWindow]
-ForcedPcSampling=0
-ForcedInterruptLogs=0
-ForcedItmLogs=0
-EventCPI=0
-EventEXC=0
-EventFOLD=0
-EventLSU=0
-EventSLEEP=0
[PowerLog]
Title_0=I0
Symbol_0=0 4 1
@@ -139,6 +114,34 @@
Frequency=10000
Probe0=I0
ProbeSetup0=2 1 1 2 0 0
+[XdsDriver]
+CStepIntDis=_ 0
+[Trace1]
+Enabled=0
+ShowSource=1
+[ETMTraceWindow]
+PortWidth=4
+PortMode=0
+CaptureDataValues=0
+CaptureDataAddresses=0
+CaptureDataRange=0
+DataFirst=0
+DataLast=-1
+StopWhen=0
+StallCPU=0
+NoPCCapture=0
+[Trace2]
+Enabled=0
+ShowSource=0
+[SWOTraceWindow]
+ForcedPcSampling=0
+ForcedInterruptLogs=0
+ForcedItmLogs=0
+EventCPI=0
+EventEXC=0
+EventFOLD=0
+EventLSU=0
+EventSLEEP=0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt
index 18cc65a..8b48bce 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wsdt
@@ -12,7 +12,7 @@
- <Column0>307</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+ <Column0>362</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build>
@@ -32,7 +32,7 @@
<Factory>Workspace</Factory>
<Session>
- <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source/tasks.c</ExpandedNode></NodeDict></Session>
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/DriverLibrary</ExpandedNode><ExpandedNode>RTOSDemo/Simply Blinky Demo</ExpandedNode><ExpandedNode>RTOSDemo/System</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
@@ -52,14 +52,14 @@
- <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>67</YPos2><SelStart2>5615</SelStart2><SelEnd2>5615</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>63</YPos2><SelStart2>5983</SelStart2><SelEnd2>5983</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
- <Top><Row0><Sizes><Toolbar-00C4A4B8><key>iaridepm.enu1</key></Toolbar-00C4A4B8></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>587</Bottom><Right>381</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>227976</sizeVertCX><sizeVertCY>598577</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>353</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>355</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>360772</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+ <Top><Row0><Sizes><Toolbar-026F17B0><key>iaridepm.enu1</key></Toolbar-026F17B0></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>683</Bottom><Right>436</Right><x>-2</x><y>-2</y><xscreen>229</xscreen><yscreen>230</yscreen><sizeHorzCX>119271</sizeHorzCX><sizeHorzCY>202822</sizeHorzCY><sizeVertCX>228125</sizeVertCX><sizeVertCY>604056</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>407</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>409</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>360670</sizeHorzCY><sizeVertCX>119271</sizeVertCX><sizeVertCY>202822</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos
index cd790b7..40c842c 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/settings/RTOSDemo.wspos
@@ -1,2 +1,2 @@
[MainWindow]
-WindowPlacement=_ 515 5 1615 901 3
+WindowPlacement=_ 290 75 1390 947 3
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c
index 31d6dde..165605f 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/msp432_startup_ccs.c
@@ -1,38 +1,38 @@
-//*****************************************************************************
-//
-// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//
-// Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the
-// distribution.
-//
-// Neither the name of Texas Instruments Incorporated nor the names of
-// its contributors may be used to endorse or promote products derived
-// from this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// MSP432 Family Interrupt Vector Table for CGT
-//
-//****************************************************************************
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* MSP432P401R Interrupt Vector Table and startup code for CCS TI ARM
+*
+*****************************************************************************/
#include <stdint.h>
#include <driverlib.h>
@@ -48,6 +48,8 @@
/* processor is started */
extern void _c_int00(void);
+/* External declaration for system initialization function */
+extern void SystemInit(void);
/* Linker variable that marks the top of the stack. */
extern unsigned long __STACK_END;
@@ -67,6 +69,7 @@
/* Intrrupt vector table. Note that the proper constructs must be placed on this to */
/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
/* the program if located at a start address other than 0. */
+#pragma RETAIN(interruptVectors)
#pragma DATA_SECTION(interruptVectors, ".intvecs")
void (* const interruptVectors[])(void) =
{
@@ -163,6 +166,8 @@
/* application. */
void resetISR(void)
{
+ SystemInit();
+
/* Jump to the CCS C Initialization Routine. */
MAP_WDT_A_holdTimer();
__asm(" .global _c_int00\n"
@@ -175,10 +180,16 @@
/* by a debugger. */
static void nmiISR(void)
{
+ /* Fault trap exempt from ULP advisor */
+ #pragma diag_push
+ #pragma CHECK_ULP("-2.1")
+
/* Enter an infinite loop. */
while(1)
{
}
+
+ #pragma diag_pop
}
@@ -187,10 +198,16 @@
/* for examination by a debugger. */
static void faultISR(void)
{
+ /* Fault trap exempt from ULP advisor */
+ #pragma diag_push
+ #pragma CHECK_ULP("-2.1")
+
/* Enter an infinite loop. */
while(1)
{
}
+
+ #pragma diag_pop
}
@@ -199,8 +216,14 @@
/* for examination by a debugger. */
static void defaultISR(void)
{
+ /* Fault trap exempt from ULP advisor */
+ #pragma diag_push
+ #pragma CHECK_ULP("-2.1")
+
/* Enter an infinite loop. */
while(1)
{
}
+
+ #pragma diag_pop
}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/system_msp432p401r.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/system_msp432p401r.c
new file mode 100644
index 0000000..fb2b92e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/CCS/system_msp432p401r.c
@@ -0,0 +1,399 @@
+/**************************************************************************//**
+* @file system_msp432p401r.c
+* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
+* MSP432P401R
+* @version V2.1.0
+* @date 2016-01-26
+*
+* @note View configuration instructions embedded in comments
+*
+******************************************************************************/
+//*****************************************************************************
+//
+// Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "msp.h"
+
+/*--------------------- Configuration Instructions ----------------------------
+ 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
+ #define __HALT_WDT 1
+ 2. Insert your desired CPU frequency in Hz at:
+ #define __SYSTEM_CLOCK 12000000
+ 3. If you prefer the DC-DC power regulator (more efficient at higher
+ frequencies), set the __REGULATOR to 1:
+ #define __REGULATOR 1
+ *---------------------------------------------------------------------------*/
+
+/*--------------------- Watchdog Timer Configuration ------------------------*/
+// Halt the Watchdog Timer
+// <0> Do not halt the WDT
+// <1> Halt the WDT
+#define __HALT_WDT 1
+
+/*--------------------- CPU Frequency Configuration -------------------------*/
+// CPU Frequency
+// <1500000> 1.5 MHz
+// <3000000> 3 MHz
+// <12000000> 12 MHz
+// <24000000> 24 MHz
+// <48000000> 48 MHz
+#define __SYSTEM_CLOCK 3000000
+
+/*--------------------- Power Regulator Configuration -----------------------*/
+// Power Regulator Mode
+// <0> LDO
+// <1> DC-DC
+#define __REGULATOR 0
+
+/*----------------------------------------------------------------------------
+ Define clocks, used for SystemCoreClockUpdate()
+ *---------------------------------------------------------------------------*/
+#define __VLOCLK 10000
+#define __MODCLK 24000000
+#define __LFXT 32768
+#define __HFXT 48000000
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *---------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t source, divider;
+ uint8_t dividerValue;
+
+ float dcoConst;
+ int32_t calVal;
+ uint32_t centeredFreq;
+ int16_t dcoTune;
+
+ divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
+ dividerValue = 1 << divider;
+ source = CS->CTL1 & CS_CTL1_SELM_MASK;
+
+ switch(source)
+ {
+ case CS_CTL1_SELM__LFXTCLK:
+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+ {
+ // Clear interrupt flag
+ CS->KEY = CS_KEY_VAL;
+ CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
+ CS->KEY = 1;
+
+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+ {
+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ }
+ else
+ {
+ SystemCoreClock = __LFXT / dividerValue;
+ }
+ }
+ else
+ {
+ SystemCoreClock = __LFXT / dividerValue;
+ }
+ break;
+ case CS_CTL1_SELM__VLOCLK:
+ SystemCoreClock = __VLOCLK / dividerValue;
+ break;
+ case CS_CTL1_SELM__REFOCLK:
+ if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ break;
+ case CS_CTL1_SELM__DCOCLK:
+ dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
+
+ switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
+ {
+ case CS_CTL0_DCORSEL_0:
+ centeredFreq = 1500000;
+ break;
+ case CS_CTL0_DCORSEL_1:
+ centeredFreq = 3000000;
+ break;
+ case CS_CTL0_DCORSEL_2:
+ centeredFreq = 6000000;
+ break;
+ case CS_CTL0_DCORSEL_3:
+ centeredFreq = 12000000;
+ break;
+ case CS_CTL0_DCORSEL_4:
+ centeredFreq = 24000000;
+ break;
+ case CS_CTL0_DCORSEL_5:
+ centeredFreq = 48000000;
+ break;
+ }
+
+ if(dcoTune == 0)
+ {
+ SystemCoreClock = centeredFreq;
+ }
+ else
+ {
+
+ if(dcoTune & 0x1000)
+ {
+ dcoTune = dcoTune | 0xF000;
+ }
+
+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+ {
+ dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
+ calVal = TLV->DCOER_FCAL_RSEL04;
+ }
+ /* Internal Resistor */
+ else
+ {
+ dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
+ calVal = TLV->DCOIR_FCAL_RSEL04;
+ }
+
+ SystemCoreClock = (uint32_t) ((centeredFreq)
+ / (1
+ - ((dcoConst * dcoTune)
+ / (8 * (1 + dcoConst * (768 - calVal))))));
+ }
+ break;
+ case CS_CTL1_SELM__MODOSC:
+ SystemCoreClock = __MODCLK / dividerValue;
+ break;
+ case CS_CTL1_SELM__HFXTCLK:
+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+ {
+ // Clear interrupt flag
+ CS->KEY = CS_KEY_VAL;
+ CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
+ CS->KEY = 1;
+
+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+ {
+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ }
+ else
+ {
+ SystemCoreClock = __HFXT / dividerValue;
+ }
+ }
+ else
+ {
+ SystemCoreClock = __HFXT / dividerValue;
+ }
+ break;
+ }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ *
+ * Performs the following initialization steps:
+ * 1. Enables the FPU
+ * 2. Halts the WDT if requested
+ * 3. Enables all SRAM banks
+ * 4. Sets up power regulator and VCORE
+ * 5. Enable Flash wait states if needed
+ * 6. Change MCLK to desired frequency
+ * 7. Enable Flash read buffering
+ */
+void SystemInit(void)
+{
+ // Enable FPU if used
+ #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
+ SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
+ (3UL << 11 * 2)); /* Set CP11 Full Access */
+ #endif
+
+ #if (__HALT_WDT == 1)
+ WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
+ #endif
+
+ SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
+
+ #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 1.5 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 3 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 12 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
+ FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
+ FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
+
+ // DCO = 24 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
+ // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+
+ // Switches LDO VCORE1 to DCDC VCORE1 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
+ FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
+ FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
+
+ // DCO = 48 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
+ #endif
+
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c
index fe3c4d2..721a2d5 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c
@@ -1,5 +1,76 @@
+/*
+ * -------------------------------------------
+ * MSP432 DriverLib - v3_10_00_09
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+//*****************************************************************************
+//
+// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// MSP432 Startup Code for IAR Embedded Workbench for ARM
+//
+//****************************************************************************
+
#include <stdint.h>
-#include <msp.h>
//*****************************************************************************
//
@@ -13,10 +84,10 @@
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
-void resetISR(void);
-static void nmiSR(void);
-static void faultISR(void);
-static void intDefaultHandler(void);
+void ResetISR(void);
+static void NmiSR(void);
+static void FaultISR(void);
+static void IntDefaultHandler(void);
//*****************************************************************************
//
@@ -67,86 +138,86 @@
{
{ .ptr = (uint32_t)systemStack + sizeof(systemStack) },
// The initial stack pointer
- resetISR, // The reset handler
- nmiSR, // The NMI handler
- faultISR, // The hard fault handler
- intDefaultHandler, // The MPU fault handler
- intDefaultHandler, // The bus fault handler
- intDefaultHandler, // The usage fault handler
+ ResetISR, // The reset handler
+ NmiSR, // The NMI handler
+ FaultISR, // The hard fault handler
+ IntDefaultHandler, // The MPU fault handler
+ IntDefaultHandler, // The bus fault handler
+ IntDefaultHandler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
- intDefaultHandler, // Debug monitor handler
+ IntDefaultHandler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
- intDefaultHandler, // PSS ISR
- intDefaultHandler, // CS ISR
- intDefaultHandler, // PCM ISR
- intDefaultHandler, // WDT ISR
- intDefaultHandler, // FPU ISR
- intDefaultHandler, // FLCTL ISR
- intDefaultHandler, // COMP0 ISR
- intDefaultHandler, // COMP1 ISR
- intDefaultHandler, // TA0_0 ISR
- intDefaultHandler, // TA0_N ISR
- intDefaultHandler, // TA1_0 ISR
- intDefaultHandler, // TA1_N ISR
- intDefaultHandler, // TA2_0 ISR
- intDefaultHandler, // TA2_N ISR
- intDefaultHandler, // TA3_0 ISR
- intDefaultHandler, // TA3_N ISR
+ IntDefaultHandler, // PSS ISR
+ IntDefaultHandler, // CS ISR
+ IntDefaultHandler, // PCM ISR
+ IntDefaultHandler, // WDT ISR
+ IntDefaultHandler, // FPU ISR
+ IntDefaultHandler, // FLCTL ISR
+ IntDefaultHandler, // COMP_E0_MODULE ISR
+ IntDefaultHandler, // COMP_E1_MODULE ISR
+ IntDefaultHandler, // TA0_0 ISR
+ IntDefaultHandler, // TA0_N ISR
+ IntDefaultHandler, // TA1_0 ISR
+ IntDefaultHandler, // TA1_N ISR
+ IntDefaultHandler, // TA2_0 ISR
+ IntDefaultHandler, // TA2_N ISR
+ IntDefaultHandler, // TA3_0 ISR
+ IntDefaultHandler, // TA3_N ISR
vUART_Handler, // EUSCIA0 ISR
- intDefaultHandler, // EUSCIA1 ISR
- intDefaultHandler, // EUSCIA2 ISR
- intDefaultHandler, // EUSCIA3 ISR
- intDefaultHandler, // EUSCIB0 ISR
- intDefaultHandler, // EUSCIB1 ISR
- intDefaultHandler, // EUSCIB2 ISR
- intDefaultHandler, // EUSCIB3 ISR
- intDefaultHandler, // ADC14 ISR
+ IntDefaultHandler, // EUSCIA1 ISR
+ IntDefaultHandler, // EUSCIA2 ISR
+ IntDefaultHandler, // EUSCIA3 ISR
+ IntDefaultHandler, // EUSCIB0 ISR
+ IntDefaultHandler, // EUSCIB1 ISR
+ IntDefaultHandler, // EUSCIB2 ISR
+ IntDefaultHandler, // EUSCIB3 ISR
+ IntDefaultHandler, // ADC12 ISR
vT32_0_Handler, // T32_INT1 ISR
vT32_1_Handler, // T32_INT2 ISR
- intDefaultHandler, // T32_INTC ISR
- intDefaultHandler, // AES ISR
- intDefaultHandler, // RTC ISR
- intDefaultHandler, // DMA_ERR ISR
- intDefaultHandler, // DMA_INT3 ISR
- intDefaultHandler, // DMA_INT2 ISR
- intDefaultHandler, // DMA_INT1 ISR
- intDefaultHandler, // DMA_INT0 ISR
- intDefaultHandler, // PORT1 ISR
- intDefaultHandler, // PORT2 ISR
- intDefaultHandler, // PORT3 ISR
- intDefaultHandler, // PORT4 ISR
- intDefaultHandler, // PORT5 ISR
- intDefaultHandler, // PORT6 ISR
- intDefaultHandler, // Reserved 41
- intDefaultHandler, // Reserved 42
- intDefaultHandler, // Reserved 43
- intDefaultHandler, // Reserved 44
- intDefaultHandler, // Reserved 45
- intDefaultHandler, // Reserved 46
- intDefaultHandler, // Reserved 47
- intDefaultHandler, // Reserved 48
- intDefaultHandler, // Reserved 49
- intDefaultHandler, // Reserved 50
- intDefaultHandler, // Reserved 51
- intDefaultHandler, // Reserved 52
- intDefaultHandler, // Reserved 53
- intDefaultHandler, // Reserved 54
- intDefaultHandler, // Reserved 55
- intDefaultHandler, // Reserved 56
- intDefaultHandler, // Reserved 57
- intDefaultHandler, // Reserved 58
- intDefaultHandler, // Reserved 59
- intDefaultHandler, // Reserved 60
- intDefaultHandler, // Reserved 61
- intDefaultHandler, // Reserved 62
- intDefaultHandler, // Reserved 63
- intDefaultHandler // Reserved 64
+ IntDefaultHandler, // T32_INTC ISR
+ IntDefaultHandler, // AES ISR
+ IntDefaultHandler, // RTC ISR
+ IntDefaultHandler, // DMA_ERR ISR
+ IntDefaultHandler, // DMA_INT3 ISR
+ IntDefaultHandler, // DMA_INT2 ISR
+ IntDefaultHandler, // DMA_INT1 ISR
+ IntDefaultHandler, // DMA_INT0 ISR
+ IntDefaultHandler, // PORT1 ISR
+ IntDefaultHandler, // PORT2 ISR
+ IntDefaultHandler, // PORT3 ISR
+ IntDefaultHandler, // PORT4 ISR
+ IntDefaultHandler, // PORT5 ISR
+ IntDefaultHandler, // PORT6 ISR
+ IntDefaultHandler, // Reserved 41
+ IntDefaultHandler, // Reserved 42
+ IntDefaultHandler, // Reserved 43
+ IntDefaultHandler, // Reserved 44
+ IntDefaultHandler, // Reserved 45
+ IntDefaultHandler, // Reserved 46
+ IntDefaultHandler, // Reserved 47
+ IntDefaultHandler, // Reserved 48
+ IntDefaultHandler, // Reserved 49
+ IntDefaultHandler, // Reserved 50
+ IntDefaultHandler, // Reserved 51
+ IntDefaultHandler, // Reserved 52
+ IntDefaultHandler, // Reserved 53
+ IntDefaultHandler, // Reserved 54
+ IntDefaultHandler, // Reserved 55
+ IntDefaultHandler, // Reserved 56
+ IntDefaultHandler, // Reserved 57
+ IntDefaultHandler, // Reserved 58
+ IntDefaultHandler, // Reserved 59
+ IntDefaultHandler, // Reserved 60
+ IntDefaultHandler, // Reserved 61
+ IntDefaultHandler, // Reserved 62
+ IntDefaultHandler, // Reserved 63
+ IntDefaultHandler // Reserved 64
};
//*****************************************************************************
@@ -160,10 +231,12 @@
//
//*****************************************************************************
void
-resetISR(void)
+ResetISR(void)
{
+void SystemInit(void);
- WDTCTL = WDTPW | WDTHOLD; // Stop WDT
+ // Initialize the device
+ SystemInit();
//
// Call the application's entry point.
@@ -179,7 +252,7 @@
//
//*****************************************************************************
static void
-nmiSR(void)
+NmiSR(void)
{
//
// Enter an infinite loop.
@@ -197,7 +270,7 @@
//
//*****************************************************************************
static void
-faultISR(void)
+FaultISR(void)
{
//
// Enter an infinite loop.
@@ -215,7 +288,7 @@
//
//*****************************************************************************
static void
-intDefaultHandler(void)
+IntDefaultHandler(void)
{
//
// Go into an infinite loop.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/system_msp432p401r.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/system_msp432p401r.c
new file mode 100644
index 0000000..9479e03
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/system_msp432p401r.c
@@ -0,0 +1,434 @@
+/*
+ * -------------------------------------------
+ * MSP432 DriverLib - v3_10_00_09
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/**************************************************************************//**
+* @file system_msp432p401r.c
+* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
+* MSP432P401R
+* @version V1.00
+* @date 20-Oct-2015
+*
+* @note View configuration instructions embedded in comments
+*
+******************************************************************************/
+//*****************************************************************************
+//
+// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "msp.h"
+
+/*--------------------- Configuration Instructions ----------------------------
+ 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
+ #define __HALT_WDT 1
+ 2. Insert your desired CPU frequency in Hz at:
+ #define __SYSTEM_CLOCK 3000000
+ 3. If you prefer the DC-DC power regulator (more efficient at higher
+ frequencies), set the __REGULATOR to 1:
+ #define __REGULATOR 1
+ *---------------------------------------------------------------------------*/
+
+/*--------------------- Watchdog Timer Configuration ------------------------*/
+// Halt the Watchdog Timer
+// <0> Do not halt the WDT
+// <1> Halt the WDT
+#define __HALT_WDT 1
+
+/*--------------------- CPU Frequency Configuration -------------------------*/
+// CPU Frequency
+// <1500000> 1.5 MHz
+// <3000000> 3 MHz
+// <12000000> 12 MHz
+// <24000000> 24 MHz
+// <48000000> 48 MHz
+#define __SYSTEM_CLOCK 1500000
+
+/*--------------------- Power Regulator Configuration -----------------------*/
+// Power Regulator Mode
+// <0> LDO
+// <1> DC-DC
+#define __REGULATOR 1
+
+/*----------------------------------------------------------------------------
+ Define clocks, used for SystemCoreClockUpdate()
+ *---------------------------------------------------------------------------*/
+#define __VLOCLK 10000
+#define __MODCLK 24000000
+#define __LFXT 32768
+#define __HFXT 48000000
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *---------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t source, divider;
+ uint8_t dividerValue;
+
+ float dcoConst;
+ int32_t calVal;
+ uint32_t centeredFreq;
+ int16_t dcoTune;
+
+ divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
+ dividerValue = 1 << divider;
+ source = CS->CTL1 & CS_CTL1_SELM_MASK;
+
+ switch(source)
+ {
+ case CS_CTL1_SELM__LFXTCLK:
+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+ {
+ // Clear interrupt flag
+ CS->KEY = CS_KEY_VAL;
+ CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
+ CS->KEY = 1;
+
+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+ {
+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ }
+ else
+ {
+ SystemCoreClock = __LFXT / dividerValue;
+ }
+ }
+ else
+ {
+ SystemCoreClock = __LFXT / dividerValue;
+ }
+ break;
+ case CS_CTL1_SELM__VLOCLK:
+ SystemCoreClock = __VLOCLK / dividerValue;
+ break;
+ case CS_CTL1_SELM__REFOCLK:
+ if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ break;
+ case CS_CTL1_SELM__DCOCLK:
+ dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
+
+ switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
+ {
+ case CS_CTL0_DCORSEL_0:
+ centeredFreq = 1500000;
+ break;
+ case CS_CTL0_DCORSEL_1:
+ centeredFreq = 3000000;
+ break;
+ case CS_CTL0_DCORSEL_2:
+ centeredFreq = 6000000;
+ break;
+ case CS_CTL0_DCORSEL_3:
+ centeredFreq = 12000000;
+ break;
+ case CS_CTL0_DCORSEL_4:
+ centeredFreq = 24000000;
+ break;
+ case CS_CTL0_DCORSEL_5:
+ centeredFreq = 48000000;
+ break;
+ }
+
+ if(dcoTune == 0)
+ {
+ SystemCoreClock = centeredFreq;
+ }
+ else
+ {
+
+ if(dcoTune & 0x1000)
+ {
+ dcoTune = dcoTune | 0xF000;
+ }
+
+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+ {
+ dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
+ calVal = TLV->DCOER_FCAL_RSEL04;
+ }
+ /* Internal Resistor */
+ else
+ {
+ dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
+ calVal = TLV->DCOIR_FCAL_RSEL04;
+ }
+
+ SystemCoreClock = (uint32_t) ((centeredFreq)
+ / (1
+ - ((dcoConst * dcoTune)
+ / (8 * (1 + dcoConst * (768 - calVal))))));
+ }
+ break;
+ case CS_CTL1_SELM__MODOSC:
+ SystemCoreClock = __MODCLK / dividerValue;
+ break;
+ case CS_CTL1_SELM__HFXTCLK:
+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+ {
+ // Clear interrupt flag
+ CS->KEY = CS_KEY_VAL;
+ CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
+ CS->KEY = 1;
+
+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+ {
+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ }
+ else
+ {
+ SystemCoreClock = __HFXT / dividerValue;
+ }
+ }
+ else
+ {
+ SystemCoreClock = __HFXT / dividerValue;
+ }
+ break;
+ }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ *
+ * Performs the following initialization steps:
+ * 1. Enables the FPU
+ * 2. Halts the WDT if requested
+ * 3. Enables all SRAM banks
+ * 4. Sets up power regulator and VCORE
+ * 5. Enable Flash wait states if needed
+ * 6. Change MCLK to desired frequency
+ * 7. Enable Flash read buffering
+ */
+void SystemInit(void)
+{
+ // Enable FPU if used
+ #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
+ SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
+ (3UL << 11 * 2)); /* Set CP11 Full Access */
+ #endif
+
+ #if (__HALT_WDT == 1)
+ WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
+ #endif
+
+ SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
+
+ #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 1.5 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 3 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 12 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
+ FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
+ FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
+
+ // DCO = 24 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
+ // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+
+ // Switches LDO VCORE1 to DCDC VCORE1 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
+ FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
+ FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
+
+ // DCO = 48 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
+ #endif
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s
index 2d84037..bb8c611 100644
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s
@@ -43,85 +43,85 @@
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
+ DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
- DCD IntDefault_Handler ; PSS ISR
- DCD IntDefault_Handler ; CS ISR
- DCD IntDefault_Handler ; PCM ISR
- DCD IntDefault_Handler ; WDT ISR
- DCD IntDefault_Handler ; FPU ISR
- DCD IntDefault_Handler ; FLCTL ISR
- DCD IntDefault_Handler ; COMP0 ISR
- DCD IntDefault_Handler ; COMP1 ISR
- DCD IntDefault_Handler ; TA0_0 ISR
- DCD IntDefault_Handler ; TA0_N ISR
- DCD IntDefault_Handler ; TA1_0 ISR
- DCD IntDefault_Handler ; TA1_N ISR
- DCD IntDefault_Handler ; TA2_0 ISR
- DCD IntDefault_Handler ; TA2_N ISR
- DCD IntDefault_Handler ; TA3_0 ISR
- DCD IntDefault_Handler ; TA3_N ISR
+ DCD PSS_IRQHandler ; 0: PSS Interrupt
+ DCD CS_IRQHandler ; 1: CS Interrupt
+ DCD PCM_IRQHandler ; 2: PCM Interrupt
+ DCD WDT_A_IRQHandler ; 3: WDT_A Interrupt
+ DCD FPU_IRQHandler ; 4: FPU Interrupt
+ DCD FLCTL_IRQHandler ; 5: FLCTL Interrupt
+ DCD COMP_E0_IRQHandler ; 6: COMP_E0 Interrupt
+ DCD COMP_E1_IRQHandler ; 7: COMP_E1 Interrupt
+ DCD TA0_0_IRQHandler ; 8: TA0_0 Interrupt
+ DCD TA0_N_IRQHandler ; 9: TA0_N Interrupt
+ DCD TA1_0_IRQHandler ; 10: TA1_0 Interrupt
+ DCD TA1_N_IRQHandler ; 11: TA1_N Interrupt
+ DCD TA2_0_IRQHandler ; 12: TA2_0 Interrupt
+ DCD TA2_N_IRQHandler ; 13: TA2_N Interrupt
+ DCD TA3_0_IRQHandler ; 14: TA3_0 Interrupt
+ DCD TA3_N_IRQHandler ; 15: TA3_N Interrupt
DCD vUART_Handler ; EUSCIA0 ISR
- DCD IntDefault_Handler ; EUSCIA1 ISR
- DCD IntDefault_Handler ; EUSCIA2 ISR
- DCD IntDefault_Handler ; EUSCIA3 ISR
- DCD IntDefault_Handler ; EUSCIB0 ISR
- DCD IntDefault_Handler ; EUSCIB1 ISR
- DCD IntDefault_Handler ; EUSCIB2 ISR
- DCD IntDefault_Handler ; EUSCIB3 ISR
- DCD IntDefault_Handler ; ADC12 ISR
+ DCD EUSCIA1_IRQHandler ; 17: EUSCIA1 Interrupt
+ DCD EUSCIA2_IRQHandler ; 18: EUSCIA2 Interrupt
+ DCD EUSCIA3_IRQHandler ; 19: EUSCIA3 Interrupt
+ DCD EUSCIB0_IRQHandler ; 20: EUSCIB0 Interrupt
+ DCD EUSCIB1_IRQHandler ; 21: EUSCIB1 Interrupt
+ DCD EUSCIB2_IRQHandler ; 22: EUSCIB2 Interrupt
+ DCD EUSCIB3_IRQHandler ; 23: EUSCIB3 Interrupt
+ DCD ADC14_IRQHandler ; 24: ADC14 Interrupt
DCD vT32_0_Handler ; T32_INT1 ISR
DCD vT32_1_Handler ; T32_INT2 ISR
- DCD IntDefault_Handler ; T32_INTC ISR
- DCD IntDefault_Handler ; AES ISR
- DCD IntDefault_Handler ; RTC ISR
- DCD IntDefault_Handler ; DMA_ERR ISR
- DCD IntDefault_Handler ; DMA_INT3 ISR
- DCD IntDefault_Handler ; DMA_INT2 ISR
- DCD IntDefault_Handler ; DMA_INT1 ISR
- DCD IntDefault_Handler ; DMA_INT0 ISR
- DCD IntDefault_Handler ; PORT1 ISR
- DCD IntDefault_Handler ; PORT2 ISR
- DCD IntDefault_Handler ; PORT3 ISR
- DCD IntDefault_Handler ; PORT4 ISR
- DCD IntDefault_Handler ; PORT5 ISR
- DCD IntDefault_Handler ; PORT6 ISR
- DCD IntDefault_Handler ; Reserved 41
- DCD IntDefault_Handler ; Reserved 42
- DCD IntDefault_Handler ; Reserved 43
- DCD IntDefault_Handler ; Reserved 44
- DCD IntDefault_Handler ; Reserved 45
- DCD IntDefault_Handler ; Reserved 46
- DCD IntDefault_Handler ; Reserved 47
- DCD IntDefault_Handler ; Reserved 48
- DCD IntDefault_Handler ; Reserved 49
- DCD IntDefault_Handler ; Reserved 50
- DCD IntDefault_Handler ; Reserved 51
- DCD IntDefault_Handler ; Reserved 52
- DCD IntDefault_Handler ; Reserved 53
- DCD IntDefault_Handler ; Reserved 54
- DCD IntDefault_Handler ; Reserved 55
- DCD IntDefault_Handler ; Reserved 56
- DCD IntDefault_Handler ; Reserved 57
- DCD IntDefault_Handler ; Reserved 58
- DCD IntDefault_Handler ; Reserved 59
- DCD IntDefault_Handler ; Reserved 60
- DCD IntDefault_Handler ; Reserved 61
- DCD IntDefault_Handler ; Reserved 62
- DCD IntDefault_Handler ; Reserved 63
- DCD IntDefault_Handler ; Reserved 64
+ DCD T32_INTC_IRQHandler ; 27: T32_INTC Interrupt
+ DCD AES256_IRQHandler ; 28: AES256 Interrupt
+ DCD RTC_C_IRQHandler ; 29: RTC_C Interrupt
+ DCD DMA_ERR_IRQHandler ; 30: DMA_ERR Interrupt
+ DCD DMA_INT3_IRQHandler ; 31: DMA_INT3 Interrupt
+ DCD DMA_INT2_IRQHandler ; 32: DMA_INT2 Interrupt
+ DCD DMA_INT1_IRQHandler ; 33: DMA_INT1 Interrupt
+ DCD DMA_INT0_IRQHandler ; 34: DMA_INT0 Interrupt
+ DCD PORT1_IRQHandler ; 35: PORT1 Interrupt
+ DCD PORT2_IRQHandler ; 36: PORT2 Interrupt
+ DCD PORT3_IRQHandler ; 37: PORT3 Interrupt
+ DCD PORT4_IRQHandler ; 38: PORT4 Interrupt
+ DCD PORT5_IRQHandler ; 39: PORT5 Interrupt
+ DCD PORT6_IRQHandler ; 40: PORT6 Interrupt
+ DCD 0 ; 41: Reserved
+ DCD 0 ; 42: Reserved
+ DCD 0 ; 43: Reserved
+ DCD 0 ; 44: Reserved
+ DCD 0 ; 45: Reserved
+ DCD 0 ; 46: Reserved
+ DCD 0 ; 47: Reserved
+ DCD 0 ; 48: Reserved
+ DCD 0 ; 49: Reserved
+ DCD 0 ; 50: Reserved
+ DCD 0 ; 51: Reserved
+ DCD 0 ; 52: Reserved
+ DCD 0 ; 53: Reserved
+ DCD 0 ; 54: Reserved
+ DCD 0 ; 55: Reserved
+ DCD 0 ; 56: Reserved
+ DCD 0 ; 57: Reserved
+ DCD 0 ; 58: Reserved
+ DCD 0 ; 59: Reserved
+ DCD 0 ; 60: Reserved
+ DCD 0 ; 61: Reserved
+ DCD 0 ; 62: Reserved
+ DCD 0 ; 63: Reserved
+ DCD 0 ; 64: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@@ -153,10 +153,30 @@
EXPORT HardFault_Handler [WEAK]
B .
ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
@@ -165,14 +185,97 @@
EXPORT SysTick_Handler [WEAK]
B .
ENDP
-IntDefault_Handler PROC
- EXPORT IntDefault_Handler [WEAK]
+
+Default_Handler PROC
+ EXPORT PSS_IRQHandler [WEAK]
+ EXPORT CS_IRQHandler [WEAK]
+ EXPORT PCM_IRQHandler [WEAK]
+ EXPORT WDT_A_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT FLCTL_IRQHandler [WEAK]
+ EXPORT COMP_E0_IRQHandler [WEAK]
+ EXPORT COMP_E1_IRQHandler [WEAK]
+ EXPORT TA0_0_IRQHandler [WEAK]
+ EXPORT TA0_N_IRQHandler [WEAK]
+ EXPORT TA1_0_IRQHandler [WEAK]
+ EXPORT TA1_N_IRQHandler [WEAK]
+ EXPORT TA2_0_IRQHandler [WEAK]
+ EXPORT TA2_N_IRQHandler [WEAK]
+ EXPORT TA3_0_IRQHandler [WEAK]
+ EXPORT TA3_N_IRQHandler [WEAK]
+ EXPORT EUSCIA0_IRQHandler [WEAK]
+ EXPORT EUSCIA1_IRQHandler [WEAK]
+ EXPORT EUSCIA2_IRQHandler [WEAK]
+ EXPORT EUSCIA3_IRQHandler [WEAK]
+ EXPORT EUSCIB0_IRQHandler [WEAK]
+ EXPORT EUSCIB1_IRQHandler [WEAK]
+ EXPORT EUSCIB2_IRQHandler [WEAK]
+ EXPORT EUSCIB3_IRQHandler [WEAK]
+ EXPORT ADC14_IRQHandler [WEAK]
+ EXPORT T32_INT1_IRQHandler [WEAK]
+ EXPORT T32_INT2_IRQHandler [WEAK]
+ EXPORT T32_INTC_IRQHandler [WEAK]
+ EXPORT AES256_IRQHandler [WEAK]
+ EXPORT RTC_C_IRQHandler [WEAK]
+ EXPORT DMA_ERR_IRQHandler [WEAK]
+ EXPORT DMA_INT3_IRQHandler [WEAK]
+ EXPORT DMA_INT2_IRQHandler [WEAK]
+ EXPORT DMA_INT1_IRQHandler [WEAK]
+ EXPORT DMA_INT0_IRQHandler [WEAK]
+ EXPORT PORT1_IRQHandler [WEAK]
+ EXPORT PORT2_IRQHandler [WEAK]
+ EXPORT PORT3_IRQHandler [WEAK]
+ EXPORT PORT4_IRQHandler [WEAK]
+ EXPORT PORT5_IRQHandler [WEAK]
+ EXPORT PORT6_IRQHandler [WEAK]
+
+PSS_IRQHandler
+CS_IRQHandler
+PCM_IRQHandler
+WDT_A_IRQHandler
+FPU_IRQHandler
+FLCTL_IRQHandler
+COMP_E0_IRQHandler
+COMP_E1_IRQHandler
+TA0_0_IRQHandler
+TA0_N_IRQHandler
+TA1_0_IRQHandler
+TA1_N_IRQHandler
+TA2_0_IRQHandler
+TA2_N_IRQHandler
+TA3_0_IRQHandler
+TA3_N_IRQHandler
+EUSCIA0_IRQHandler
+EUSCIA1_IRQHandler
+EUSCIA2_IRQHandler
+EUSCIA3_IRQHandler
+EUSCIB0_IRQHandler
+EUSCIB1_IRQHandler
+EUSCIB2_IRQHandler
+EUSCIB3_IRQHandler
+ADC14_IRQHandler
+T32_INT1_IRQHandler
+T32_INT2_IRQHandler
+T32_INTC_IRQHandler
+AES256_IRQHandler
+RTC_C_IRQHandler
+DMA_ERR_IRQHandler
+DMA_INT3_IRQHandler
+DMA_INT2_IRQHandler
+DMA_INT1_IRQHandler
+DMA_INT0_IRQHandler
+PORT1_IRQHandler
+PORT2_IRQHandler
+PORT3_IRQHandler
+PORT4_IRQHandler
+PORT5_IRQHandler
+PORT6_IRQHandler
B .
ENDP
ALIGN
-
+
; User Initial Stack & Heap
IF :DEF:__MICROLIB
@@ -185,13 +288,14 @@
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
-__user_initial_stackheap
+__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
+ ENDP
ALIGN
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_MSP432P4.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_MSP432P4.c
deleted file mode 100644
index b822064..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_MSP432P4.c
+++ /dev/null
@@ -1,68 +0,0 @@
-//*****************************************************************************
-//
-// Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//
-// Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the
-// distribution.
-//
-// Neither the name of Texas Instruments Incorporated nor the names of
-// its contributors may be used to endorse or promote products derived
-// from this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// MSP432 Startup File
-//
-// File creation date: 2014-07-08
-//
-//*****************************************************************************
-
-#include <stdint.h>
-#include "msp432.h"
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-#define __SYSTEM_CLOCK (2000000)
-
-/*----------------------------------------------------------------------------
- Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
- Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
-{
- SystemCoreClock = __SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
- Initialize the system
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
- SystemCoreClock = __SYSTEM_CLOCK;
- WDT_A->rCTL.r = WDTPW + WDTHOLD;
-}
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_msp432p401r.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_msp432p401r.c
new file mode 100644
index 0000000..6f02dd1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/system_msp432p401r.c
@@ -0,0 +1,398 @@
+/**************************************************************************//**
+* @file system_msp432p401r.c
+* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
+* MSP432P401R
+* @version V1.00
+* @date 20-Oct-2015
+*
+* @note View configuration instructions embedded in comments
+*
+******************************************************************************/
+//*****************************************************************************
+//
+// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include "msp.h"
+
+/*--------------------- Configuration Instructions ----------------------------
+ 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
+ #define __HALT_WDT 1
+ 2. Insert your desired CPU frequency in Hz at:
+ #define __SYSTEM_CLOCK 3000000
+ 3. If you prefer the DC-DC power regulator (more efficient at higher
+ frequencies), set the __REGULATOR to 1:
+ #define __REGULATOR 1
+ *---------------------------------------------------------------------------*/
+
+/*--------------------- Watchdog Timer Configuration ------------------------*/
+// Halt the Watchdog Timer
+// <0> Do not halt the WDT
+// <1> Halt the WDT
+#define __HALT_WDT 1
+
+/*--------------------- CPU Frequency Configuration -------------------------*/
+// CPU Frequency
+// <1500000> 1.5 MHz
+// <3000000> 3 MHz
+// <12000000> 12 MHz
+// <24000000> 24 MHz
+// <48000000> 48 MHz
+#define __SYSTEM_CLOCK 1500000
+
+/*--------------------- Power Regulator Configuration -----------------------*/
+// Power Regulator Mode
+// <0> LDO
+// <1> DC-DC
+#define __REGULATOR 1
+
+/*----------------------------------------------------------------------------
+ Define clocks, used for SystemCoreClockUpdate()
+ *---------------------------------------------------------------------------*/
+#define __VLOCLK 10000
+#define __MODCLK 24000000
+#define __LFXT 32768
+#define __HFXT 48000000
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *---------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t source, divider;
+ uint8_t dividerValue;
+
+ float dcoConst;
+ int32_t calVal;
+ uint32_t centeredFreq;
+ int16_t dcoTune;
+
+ divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
+ dividerValue = 1 << divider;
+ source = CS->CTL1 & CS_CTL1_SELM_MASK;
+
+ switch(source)
+ {
+ case CS_CTL1_SELM__LFXTCLK:
+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+ {
+ // Clear interrupt flag
+ CS->KEY = CS_KEY_VAL;
+ CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
+ CS->KEY = 1;
+
+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+ {
+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ }
+ else
+ {
+ SystemCoreClock = __LFXT / dividerValue;
+ }
+ }
+ else
+ {
+ SystemCoreClock = __LFXT / dividerValue;
+ }
+ break;
+ case CS_CTL1_SELM__VLOCLK:
+ SystemCoreClock = __VLOCLK / dividerValue;
+ break;
+ case CS_CTL1_SELM__REFOCLK:
+ if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ break;
+ case CS_CTL1_SELM__DCOCLK:
+ dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
+
+ switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
+ {
+ case CS_CTL0_DCORSEL_0:
+ centeredFreq = 1500000;
+ break;
+ case CS_CTL0_DCORSEL_1:
+ centeredFreq = 3000000;
+ break;
+ case CS_CTL0_DCORSEL_2:
+ centeredFreq = 6000000;
+ break;
+ case CS_CTL0_DCORSEL_3:
+ centeredFreq = 12000000;
+ break;
+ case CS_CTL0_DCORSEL_4:
+ centeredFreq = 24000000;
+ break;
+ case CS_CTL0_DCORSEL_5:
+ centeredFreq = 48000000;
+ break;
+ }
+
+ if(dcoTune == 0)
+ {
+ SystemCoreClock = centeredFreq;
+ }
+ else
+ {
+
+ if(dcoTune & 0x1000)
+ {
+ dcoTune = dcoTune | 0xF000;
+ }
+
+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+ {
+ dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
+ calVal = TLV->DCOER_FCAL_RSEL04;
+ }
+ /* Internal Resistor */
+ else
+ {
+ dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
+ calVal = TLV->DCOIR_FCAL_RSEL04;
+ }
+
+ SystemCoreClock = (uint32_t) ((centeredFreq)
+ / (1
+ - ((dcoConst * dcoTune)
+ / (8 * (1 + dcoConst * (768 - calVal))))));
+ }
+ break;
+ case CS_CTL1_SELM__MODOSC:
+ SystemCoreClock = __MODCLK / dividerValue;
+ break;
+ case CS_CTL1_SELM__HFXTCLK:
+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+ {
+ // Clear interrupt flag
+ CS->KEY = CS_KEY_VAL;
+ CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
+ CS->KEY = 1;
+
+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+ {
+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+ {
+ SystemCoreClock = (128000 / dividerValue);
+ }
+ else
+ {
+ SystemCoreClock = (32000 / dividerValue);
+ }
+ }
+ else
+ {
+ SystemCoreClock = __HFXT / dividerValue;
+ }
+ }
+ else
+ {
+ SystemCoreClock = __HFXT / dividerValue;
+ }
+ break;
+ }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ *
+ * Performs the following initialization steps:
+ * 1. Enables the FPU
+ * 2. Halts the WDT if requested
+ * 3. Enables all SRAM banks
+ * 4. Sets up power regulator and VCORE
+ * 5. Enable Flash wait states if needed
+ * 6. Change MCLK to desired frequency
+ * 7. Enable Flash read buffering
+ */
+void SystemInit(void)
+{
+ // Enable FPU if used
+ #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
+ SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */
+ (3UL << 11 * 2)); /* Set CP11 Full Access */
+ #endif
+
+ #if (__HALT_WDT == 1)
+ WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
+ #endif
+
+ SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
+
+ #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 1.5 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 3 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // No flash wait states necessary
+
+ // DCO = 12 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
+ // Default VCORE is LDO VCORE0 so no change necessary
+
+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
+ FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
+ FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1;
+
+ // DCO = 24 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+
+ #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
+ // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+
+ // Switches LDO VCORE1 to DCDC VCORE1 if requested
+ #if __REGULATOR
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
+ #endif
+
+ // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
+ FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2;
+ FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2;
+
+ // DCO = 48 MHz; MCLK = source
+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
+ CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
+ CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source
+ CS->KEY = 0;
+
+ // Set Flash Bank read buffering
+ FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
+ FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
+ #endif
+
+}
diff --git a/FreeRTOS/Demo/Common/Minimal/TimerDemo.c b/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
index c7b4c52..b657d0d 100644
--- a/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
+++ b/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
@@ -302,7 +302,7 @@
}
else
{
- configASSERT( strcmp( pcTimerGetTimerName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 );
+ configASSERT( strcmp( pcTimerGetName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 );
/* The scheduler has not yet started, so the block period of
portMAX_DELAY should just get set to zero in xTimerStart(). Also,
diff --git a/FreeRTOS/Demo/Common/ReadMe.txt b/FreeRTOS/Demo/Common/ReadMe.txt
new file mode 100644
index 0000000..72b46db
--- /dev/null
+++ b/FreeRTOS/Demo/Common/ReadMe.txt
@@ -0,0 +1,14 @@
+Contains the files that are not specific to any one demo, but are instead used
+by all the demo applications.
+
+Most of the directories are now obsolete, and only maintained for backward
+compatibility. The directories in active use are:
+
++ Minimal - this contains the implementation of what are referred to as the
+"Standard Demo Tasks". These are used by all the demo applications. Their only
+purpose is to demonstrate the FreeRTOS API and test the FreeRTOS features. The
+directory is called 'Minimal' as it contains a minimal implementation of files
+contained in the 'Full' directory - but the 'Full' directory is no longer used.
+
++ include - contains header files for the C source files located in the Minimal
+directory.
\ No newline at end of file
diff --git a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewd
index f1be6d4..b986d19 100644
--- a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewd
+++ b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewd
@@ -153,7 +153,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
- <version>29</version>
+ <version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -318,6 +318,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
+ <option>
+ <name>variablewatch</name>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -563,7 +567,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
- <version>29</version>
+ <version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -728,6 +732,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
+ <option>
+ <name>variablewatch</name>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -973,7 +981,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
- <version>29</version>
+ <version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -1138,6 +1146,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
+ <option>
+ <name>variablewatch</name>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
@@ -1383,7 +1395,7 @@
<name>430FET</name>
<archiveVersion>1</archiveVersion>
<data>
- <version>29</version>
+ <version>30</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@@ -1548,6 +1560,10 @@
<name>cycleCounterLevel</name>
<state>0</state>
</option>
+ <option>
+ <name>variablewatch</name>
+ <state>0</state>
+ </option>
</data>
</settings>
<settings>
diff --git a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp
index 0febc95..f0cd7ba 100644
--- a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp
+++ b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewp
@@ -10,7 +10,7 @@
<debug>1</debug>
<settings>
<name>General</name>
- <archiveVersion>17</archiveVersion>
+ <archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@@ -754,7 +754,7 @@
</option>
<option>
<name>FormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
@@ -948,7 +948,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
@@ -1139,7 +1139,7 @@
<debug>1</debug>
<settings>
<name>General</name>
- <archiveVersion>17</archiveVersion>
+ <archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@@ -1883,7 +1883,7 @@
</option>
<option>
<name>FormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
@@ -2077,7 +2077,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
@@ -2268,7 +2268,7 @@
<debug>1</debug>
<settings>
<name>General</name>
- <archiveVersion>17</archiveVersion>
+ <archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@@ -3012,7 +3012,7 @@
</option>
<option>
<name>FormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
@@ -3206,7 +3206,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
@@ -3397,7 +3397,7 @@
<debug>1</debug>
<settings>
<name>General</name>
- <archiveVersion>17</archiveVersion>
+ <archiveVersion>18</archiveVersion>
<data>
<version>33</version>
<wantNonLocal>1</wantNonLocal>
@@ -4141,7 +4141,7 @@
</option>
<option>
<name>FormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
@@ -4335,7 +4335,7 @@
</option>
<option>
<name>ExtraFormatVariant</name>
- <version>8</version>
+ <version>9</version>
<state>2</state>
</option>
<option>
diff --git a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewt b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewt
index dc27952..4c3a124 100644
--- a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewt
+++ b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/RTOSDemo.ewt
@@ -12,6 +12,14 @@
<name>C-STAT</name>
<archiveVersion>1</archiveVersion>
<data>
+ <version>1</version>
+ <cstatargs>
+ <useExtraArgs>0</useExtraArgs>
+ <extraArgs></extraArgs>
+ <analyzeTimeout>600</analyzeTimeout>
+ <enableParallel>0</enableParallel>
+ <parallelThreads>2</parallelThreads>
+ </cstatargs>
<cstatsettings>
<package checked="true" name="STDCHECKS">
<group checked="true" name="ARR">
@@ -983,6 +991,14 @@
<name>C-STAT</name>
<archiveVersion>1</archiveVersion>
<data>
+ <version>1</version>
+ <cstatargs>
+ <useExtraArgs>0</useExtraArgs>
+ <extraArgs></extraArgs>
+ <analyzeTimeout>600</analyzeTimeout>
+ <enableParallel>0</enableParallel>
+ <parallelThreads>2</parallelThreads>
+ </cstatargs>
<cstatsettings>
<package checked="true" name="STDCHECKS">
<group checked="true" name="ARR">
@@ -1954,6 +1970,14 @@
<name>C-STAT</name>
<archiveVersion>1</archiveVersion>
<data>
+ <version>1</version>
+ <cstatargs>
+ <useExtraArgs>0</useExtraArgs>
+ <extraArgs></extraArgs>
+ <analyzeTimeout>600</analyzeTimeout>
+ <enableParallel>0</enableParallel>
+ <parallelThreads>2</parallelThreads>
+ </cstatargs>
<cstatsettings>
<package checked="true" name="STDCHECKS">
<group checked="true" name="ARR">
@@ -2925,6 +2949,14 @@
<name>C-STAT</name>
<archiveVersion>1</archiveVersion>
<data>
+ <version>1</version>
+ <cstatargs>
+ <useExtraArgs>0</useExtraArgs>
+ <extraArgs></extraArgs>
+ <analyzeTimeout>600</analyzeTimeout>
+ <enableParallel>0</enableParallel>
+ <parallelThreads>2</parallelThreads>
+ </cstatargs>
<cstatsettings>
<package checked="true" name="STDCHECKS">
<group checked="true" name="ARR">
diff --git a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt
index 9eae4ff..9336f18 100644
--- a/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt
+++ b/FreeRTOS/Demo/MSP430X_MSP430F5438_IAR/settings/RTOSDemo.wsdt
@@ -12,7 +12,7 @@
- <Column0>335</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+ <Column0>394</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build>
@@ -25,7 +25,7 @@
<Windows>
- <Wnd2>
+ <Wnd0>
<Tabs>
<Tab>
<Identity>TabID-18858-27566</Identity>
@@ -37,7 +37,7 @@
</Tab>
</Tabs>
- <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-15348-8476</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-12693-9958</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-15348-8476</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-12693-9958</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>
<Editor>
@@ -50,7 +50,7 @@
- <Top><Row0><Sizes><Toolbar-00F763E8><key>iaridepm.enu1</key></Toolbar-00F763E8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>611</Bottom><Right>409</Right><x>-2</x><y>-2</y><xscreen>331</xscreen><yscreen>268</yscreen><sizeHorzCX>197024</sizeHorzCX><sizeHorzCY>272358</sizeHorzCY><sizeVertCX>244643</sizeVertCX><sizeVertCY>622967</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>329</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>331</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>336382</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+ <Top><Row0><Sizes><Toolbar-01101698><key>iaridepm.enu1</key></Toolbar-01101698></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>711</Bottom><Right>468</Right><x>-2</x><y>-2</y><xscreen>378</xscreen><yscreen>309</yscreen><sizeHorzCX>196875</sizeHorzCX><sizeHorzCY>272487</sizeHorzCY><sizeVertCX>244792</sizeVertCX><sizeVertCY>628748</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>379</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>381</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>335979</sizeHorzCY><sizeVertCX>119271</sizeVertCX><sizeVertCY>202822</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>
diff --git a/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h b/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h
index 862f480..8b845a0 100644
--- a/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h
@@ -146,7 +146,6 @@
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xEventGroupSetBitsFromISR 1
#define INCLUDE_xTimerPendFunctionCall 1
-#define INCLUDE_pcTaskGetTaskName 1
/* Include functions that format system and run-time stats into human readable
tables. */
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
index 046c010..ef86ac3 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
@@ -154,7 +154,6 @@
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
-#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTaskResumeFromISR 0
diff --git a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h
index 9e478bf..f819bcc 100644
--- a/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only/FreeRTOSConfig.h
@@ -154,7 +154,6 @@
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
-#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTaskGetTaskHandle 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
diff --git a/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h b/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h
index ad52b81..118de4d 100644
--- a/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/WIN32-MSVC/FreeRTOSConfig.h
@@ -145,7 +145,6 @@
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
-#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTaskGetTaskHandle 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
diff --git a/FreeRTOS/Demo/WIN32-MSVC/main_full.c b/FreeRTOS/Demo/WIN32-MSVC/main_full.c
index 724c55c..7d8907f 100644
--- a/FreeRTOS/Demo/WIN32-MSVC/main_full.c
+++ b/FreeRTOS/Demo/WIN32-MSVC/main_full.c
@@ -174,11 +174,20 @@
static void prvDemonstratePendingFunctionCall( void );
/*
- * The function that is pended by prvDemonstratePendingFunctionCall().
- */
+* The function that is pended by prvDemonstratePendingFunctionCall().
+*/
static void prvPendedFunction( void *pvParameter1, uint32_t ulParameter2 );
/*
+ * prvDemonstrateTimerQueryFunctions() is called from the idle task hook
+ * function to demonstrate the use of functions that query information about a
+ * software timer. prvTestTimerCallback() is the callback function for the
+ * timer being queried.
+ */
+static void prvDemonstrateTimerQueryFunctions( void );
+static void prvTestTimerCallback( TimerHandle_t xTimer );
+
+/*
* A task to demonstrate the use of the xQueueSpacesAvailable() function.
*/
static void prvDemoQueueSpaceFunctions( void *pvParameters );
@@ -418,6 +427,11 @@
demonstrated by any of the standard demo tasks. */
prvDemonstratePendingFunctionCall();
+ /* Demonstrate the use of functions that query information about a software
+ timer. */
+ prvDemonstrateTimerQueryFunctions();
+
+
/* If xMutexToDelete has not already been deleted, then delete it now.
This is done purely to demonstrate the use of, and test, the
vSemaphoreDelete() macro. Care must be taken not to delete a semaphore
@@ -428,11 +442,11 @@
again, before it is deleted - checking its name is as expected before
and after the assertion into the registry and its removal from the
registry. */
- configASSERT( pcQueueGetQueueName( xMutexToDelete ) == NULL );
+ configASSERT( pcQueueGetName( xMutexToDelete ) == NULL );
vQueueAddToRegistry( xMutexToDelete, "Test_Mutex" );
- configASSERT( strcmp( pcQueueGetQueueName( xMutexToDelete ), "Test_Mutex" ) == 0 );
+ configASSERT( strcmp( pcQueueGetName( xMutexToDelete ), "Test_Mutex" ) == 0 );
vQueueUnregisterQueue( xMutexToDelete );
- configASSERT( pcQueueGetQueueName( xMutexToDelete ) == NULL );
+ configASSERT( pcQueueGetName( xMutexToDelete ) == NULL );
vSemaphoreDelete( xMutexToDelete );
xMutexToDelete = NULL;
@@ -499,6 +513,53 @@
}
/*-----------------------------------------------------------*/
+static void prvTestTimerCallback( TimerHandle_t xTimer )
+{
+ /* This is the callback function for the timer accessed by
+ prvDemonstrateTimerQueryFunctions(). The callback does not do anything. */
+ ( void ) xTimer;
+}
+/*-----------------------------------------------------------*/
+
+static void prvDemonstrateTimerQueryFunctions( void )
+{
+static TimerHandle_t xTimer = NULL;
+const char *pcTimerName = "TestTimer";
+volatile TickType_t xExpiryTime;
+const TickType_t xDontBlock = 0;
+
+ if( xTimer == NULL )
+ {
+ xTimer = xTimerCreate( pcTimerName, portMAX_DELAY, pdTRUE, NULL, prvTestTimerCallback );
+
+ if( xTimer != NULL )
+ {
+ /* Called from the idle task so a block time must not be
+ specified. */
+ xTimerStart( xTimer, xDontBlock );
+ }
+ }
+
+ if( xTimer != NULL )
+ {
+ /* Demonstrate querying a timer's name. */
+ configASSERT( strcmp( pcTimerGetName( xTimer ), pcTimerName ) == 0 );
+
+ /* Demonstrate querying a timer's period. */
+ configASSERT( xTimerGetPeriod( xTimer ) == portMAX_DELAY );
+
+ /* Demonstrate querying a timer's next expiry time, although nothing is
+ done with the returned value. Note if the expiry time is less than the
+ maximum tick count then the expiry time has overflowed from the current
+ time. In this case the expiry time was set to portMAX_DELAY, so it is
+ expected to be less than the current time until the current time has
+ itself overflowed. */
+ xExpiryTime = xTimerGetExpiryTime( xTimer );
+ ( void ) xExpiryTime;
+ }
+}
+/*-----------------------------------------------------------*/
+
static void prvDemonstratePendingFunctionCall( void )
{
static uint32_t ulParameter1 = 1000UL, ulParameter2 = 0UL;
@@ -549,7 +610,7 @@
}
/* Check the timer task handle was returned correctly. */
- pcTaskName = pcTaskGetTaskName( xTimerTaskHandle );
+ pcTaskName = pcTaskGetName( xTimerTaskHandle );
if( strcmp( pcTaskName, "Tmr Svc" ) != 0 )
{
pcStatusMessage = "Error: Returned timer task handle was incorrect";
diff --git a/FreeRTOS/Demo/WIN32-MingW/FreeRTOSConfig.h b/FreeRTOS/Demo/WIN32-MingW/FreeRTOSConfig.h
index 42d7770..f327164 100644
--- a/FreeRTOS/Demo/WIN32-MingW/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/WIN32-MingW/FreeRTOSConfig.h
@@ -143,7 +143,6 @@
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
-#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
#define INCLUDE_xTimerPendFunctionCall 1
diff --git a/FreeRTOS/Demo/WIN32-MingW/main_full.c b/FreeRTOS/Demo/WIN32-MingW/main_full.c
index e37b92b..cfcd96a 100644
--- a/FreeRTOS/Demo/WIN32-MingW/main_full.c
+++ b/FreeRTOS/Demo/WIN32-MingW/main_full.c
@@ -500,7 +500,7 @@
}
/* Check the timer task handle was returned correctly. */
- pcTaskName = pcTaskGetTaskName( xTimerTaskHandle );
+ pcTaskName = pcTaskGetName( xTimerTaskHandle );
if( strcmp( pcTaskName, "Tmr Svc" ) != 0 )
{
pcStatusMessage = "Error: Returned timer task handle was incorrect";
diff --git a/FreeRTOS/Source/include/timers.h b/FreeRTOS/Source/include/timers.h
index 1e029db..70525ca 100644
--- a/FreeRTOS/Source/include/timers.h
+++ b/FreeRTOS/Source/include/timers.h
@@ -478,9 +478,6 @@
/**
* TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
*
- * xTimerGetTimerDaemonTaskHandle() is only available if
- * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.
- *
* Simply returns the handle of the timer service/daemon task. It it not valid
* to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
*/
diff --git a/FreeRTOS/Source/timers.c b/FreeRTOS/Source/timers.c
index 5c0d4eb..c6596d5 100644
--- a/FreeRTOS/Source/timers.c
+++ b/FreeRTOS/Source/timers.c
@@ -435,7 +435,7 @@
TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
{
-const Timer_t * const pxTimer = ( const Timer_t * const ) xTimer;
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
configASSERT( xTimer );
return pxTimer->xTimerPeriodInTicks;
@@ -444,7 +444,7 @@
TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
{
-const Timer_t * const pxTimer = ( const Timer_t * const ) xTimer;
+Timer_t * pxTimer = ( Timer_t * ) xTimer;
TickType_t xReturn;
configASSERT( xTimer );
