Update MSP432 projects to use updated driver library files. Remove references to INCLUDE_pcTaskGetTaskName and INCLUDE_xTimerGetTimerDaemonTaskHandle, which are no longer required.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c index fe3c4d2..721a2d5 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c
@@ -1,5 +1,76 @@ +/* + * ------------------------------------------- + * MSP432 DriverLib - v3_10_00_09 + * ------------------------------------------- + * + * --COPYRIGHT--,BSD,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// MSP432 Startup Code for IAR Embedded Workbench for ARM +// +//**************************************************************************** + #include <stdint.h> -#include <msp.h> //***************************************************************************** // @@ -13,10 +84,10 @@ // Forward declaration of the default fault handlers. // //***************************************************************************** -void resetISR(void); -static void nmiSR(void); -static void faultISR(void); -static void intDefaultHandler(void); +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); //***************************************************************************** // @@ -67,86 +138,86 @@ { { .ptr = (uint32_t)systemStack + sizeof(systemStack) }, // The initial stack pointer - resetISR, // The reset handler - nmiSR, // The NMI handler - faultISR, // The hard fault handler - intDefaultHandler, // The MPU fault handler - intDefaultHandler, // The bus fault handler - intDefaultHandler, // The usage fault handler + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler 0, // Reserved 0, // Reserved 0, // Reserved 0, // Reserved SVC_Handler, // SVCall handler - intDefaultHandler, // Debug monitor handler + IntDefaultHandler, // Debug monitor handler 0, // Reserved PendSV_Handler, // The PendSV handler SysTick_Handler, // The SysTick handler - intDefaultHandler, // PSS ISR - intDefaultHandler, // CS ISR - intDefaultHandler, // PCM ISR - intDefaultHandler, // WDT ISR - intDefaultHandler, // FPU ISR - intDefaultHandler, // FLCTL ISR - intDefaultHandler, // COMP0 ISR - intDefaultHandler, // COMP1 ISR - intDefaultHandler, // TA0_0 ISR - intDefaultHandler, // TA0_N ISR - intDefaultHandler, // TA1_0 ISR - intDefaultHandler, // TA1_N ISR - intDefaultHandler, // TA2_0 ISR - intDefaultHandler, // TA2_N ISR - intDefaultHandler, // TA3_0 ISR - intDefaultHandler, // TA3_N ISR + IntDefaultHandler, // PSS ISR + IntDefaultHandler, // CS ISR + IntDefaultHandler, // PCM ISR + IntDefaultHandler, // WDT ISR + IntDefaultHandler, // FPU ISR + IntDefaultHandler, // FLCTL ISR + IntDefaultHandler, // COMP_E0_MODULE ISR + IntDefaultHandler, // COMP_E1_MODULE ISR + IntDefaultHandler, // TA0_0 ISR + IntDefaultHandler, // TA0_N ISR + IntDefaultHandler, // TA1_0 ISR + IntDefaultHandler, // TA1_N ISR + IntDefaultHandler, // TA2_0 ISR + IntDefaultHandler, // TA2_N ISR + IntDefaultHandler, // TA3_0 ISR + IntDefaultHandler, // TA3_N ISR vUART_Handler, // EUSCIA0 ISR - intDefaultHandler, // EUSCIA1 ISR - intDefaultHandler, // EUSCIA2 ISR - intDefaultHandler, // EUSCIA3 ISR - intDefaultHandler, // EUSCIB0 ISR - intDefaultHandler, // EUSCIB1 ISR - intDefaultHandler, // EUSCIB2 ISR - intDefaultHandler, // EUSCIB3 ISR - intDefaultHandler, // ADC14 ISR + IntDefaultHandler, // EUSCIA1 ISR + IntDefaultHandler, // EUSCIA2 ISR + IntDefaultHandler, // EUSCIA3 ISR + IntDefaultHandler, // EUSCIB0 ISR + IntDefaultHandler, // EUSCIB1 ISR + IntDefaultHandler, // EUSCIB2 ISR + IntDefaultHandler, // EUSCIB3 ISR + IntDefaultHandler, // ADC12 ISR vT32_0_Handler, // T32_INT1 ISR vT32_1_Handler, // T32_INT2 ISR - intDefaultHandler, // T32_INTC ISR - intDefaultHandler, // AES ISR - intDefaultHandler, // RTC ISR - intDefaultHandler, // DMA_ERR ISR - intDefaultHandler, // DMA_INT3 ISR - intDefaultHandler, // DMA_INT2 ISR - intDefaultHandler, // DMA_INT1 ISR - intDefaultHandler, // DMA_INT0 ISR - intDefaultHandler, // PORT1 ISR - intDefaultHandler, // PORT2 ISR - intDefaultHandler, // PORT3 ISR - intDefaultHandler, // PORT4 ISR - intDefaultHandler, // PORT5 ISR - intDefaultHandler, // PORT6 ISR - intDefaultHandler, // Reserved 41 - intDefaultHandler, // Reserved 42 - intDefaultHandler, // Reserved 43 - intDefaultHandler, // Reserved 44 - intDefaultHandler, // Reserved 45 - intDefaultHandler, // Reserved 46 - intDefaultHandler, // Reserved 47 - intDefaultHandler, // Reserved 48 - intDefaultHandler, // Reserved 49 - intDefaultHandler, // Reserved 50 - intDefaultHandler, // Reserved 51 - intDefaultHandler, // Reserved 52 - intDefaultHandler, // Reserved 53 - intDefaultHandler, // Reserved 54 - intDefaultHandler, // Reserved 55 - intDefaultHandler, // Reserved 56 - intDefaultHandler, // Reserved 57 - intDefaultHandler, // Reserved 58 - intDefaultHandler, // Reserved 59 - intDefaultHandler, // Reserved 60 - intDefaultHandler, // Reserved 61 - intDefaultHandler, // Reserved 62 - intDefaultHandler, // Reserved 63 - intDefaultHandler // Reserved 64 + IntDefaultHandler, // T32_INTC ISR + IntDefaultHandler, // AES ISR + IntDefaultHandler, // RTC ISR + IntDefaultHandler, // DMA_ERR ISR + IntDefaultHandler, // DMA_INT3 ISR + IntDefaultHandler, // DMA_INT2 ISR + IntDefaultHandler, // DMA_INT1 ISR + IntDefaultHandler, // DMA_INT0 ISR + IntDefaultHandler, // PORT1 ISR + IntDefaultHandler, // PORT2 ISR + IntDefaultHandler, // PORT3 ISR + IntDefaultHandler, // PORT4 ISR + IntDefaultHandler, // PORT5 ISR + IntDefaultHandler, // PORT6 ISR + IntDefaultHandler, // Reserved 41 + IntDefaultHandler, // Reserved 42 + IntDefaultHandler, // Reserved 43 + IntDefaultHandler, // Reserved 44 + IntDefaultHandler, // Reserved 45 + IntDefaultHandler, // Reserved 46 + IntDefaultHandler, // Reserved 47 + IntDefaultHandler, // Reserved 48 + IntDefaultHandler, // Reserved 49 + IntDefaultHandler, // Reserved 50 + IntDefaultHandler, // Reserved 51 + IntDefaultHandler, // Reserved 52 + IntDefaultHandler, // Reserved 53 + IntDefaultHandler, // Reserved 54 + IntDefaultHandler, // Reserved 55 + IntDefaultHandler, // Reserved 56 + IntDefaultHandler, // Reserved 57 + IntDefaultHandler, // Reserved 58 + IntDefaultHandler, // Reserved 59 + IntDefaultHandler, // Reserved 60 + IntDefaultHandler, // Reserved 61 + IntDefaultHandler, // Reserved 62 + IntDefaultHandler, // Reserved 63 + IntDefaultHandler // Reserved 64 }; //***************************************************************************** @@ -160,10 +231,12 @@ // //***************************************************************************** void -resetISR(void) +ResetISR(void) { +void SystemInit(void); - WDTCTL = WDTPW | WDTHOLD; // Stop WDT + // Initialize the device + SystemInit(); // // Call the application's entry point. @@ -179,7 +252,7 @@ // //***************************************************************************** static void -nmiSR(void) +NmiSR(void) { // // Enter an infinite loop. @@ -197,7 +270,7 @@ // //***************************************************************************** static void -faultISR(void) +FaultISR(void) { // // Enter an infinite loop. @@ -215,7 +288,7 @@ // //***************************************************************************** static void -intDefaultHandler(void) +IntDefaultHandler(void) { // // Go into an infinite loop.
diff --git a/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/system_msp432p401r.c b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/system_msp432p401r.c new file mode 100644 index 0000000..9479e03 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/system_msp432p401r.c
@@ -0,0 +1,434 @@ +/* + * ------------------------------------------- + * MSP432 DriverLib - v3_10_00_09 + * ------------------------------------------- + * + * --COPYRIGHT--,BSD,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/**************************************************************************//** +* @file system_msp432p401r.c +* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for +* MSP432P401R +* @version V1.00 +* @date 20-Oct-2015 +* +* @note View configuration instructions embedded in comments +* +******************************************************************************/ +//***************************************************************************** +// +// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#include <stdint.h> +#include "msp.h" + +/*--------------------- Configuration Instructions ---------------------------- + 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: + #define __HALT_WDT 1 + 2. Insert your desired CPU frequency in Hz at: + #define __SYSTEM_CLOCK 3000000 + 3. If you prefer the DC-DC power regulator (more efficient at higher + frequencies), set the __REGULATOR to 1: + #define __REGULATOR 1 + *---------------------------------------------------------------------------*/ + +/*--------------------- Watchdog Timer Configuration ------------------------*/ +// Halt the Watchdog Timer +// <0> Do not halt the WDT +// <1> Halt the WDT +#define __HALT_WDT 1 + +/*--------------------- CPU Frequency Configuration -------------------------*/ +// CPU Frequency +// <1500000> 1.5 MHz +// <3000000> 3 MHz +// <12000000> 12 MHz +// <24000000> 24 MHz +// <48000000> 48 MHz +#define __SYSTEM_CLOCK 1500000 + +/*--------------------- Power Regulator Configuration -----------------------*/ +// Power Regulator Mode +// <0> LDO +// <1> DC-DC +#define __REGULATOR 1 + +/*---------------------------------------------------------------------------- + Define clocks, used for SystemCoreClockUpdate() + *---------------------------------------------------------------------------*/ +#define __VLOCLK 10000 +#define __MODCLK 24000000 +#define __LFXT 32768 +#define __HFXT 48000000 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *---------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t source, divider; + uint8_t dividerValue; + + float dcoConst; + int32_t calVal; + uint32_t centeredFreq; + int16_t dcoTune; + + divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; + dividerValue = 1 << divider; + source = CS->CTL1 & CS_CTL1_SELM_MASK; + + switch(source) + { + case CS_CTL1_SELM__LFXTCLK: + if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) + { + // Clear interrupt flag + CS->KEY = CS_KEY_VAL; + CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; + CS->KEY = 1; + + if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) + { + if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) + { + SystemCoreClock = (128000 / dividerValue); + } + else + { + SystemCoreClock = (32000 / dividerValue); + } + } + else + { + SystemCoreClock = __LFXT / dividerValue; + } + } + else + { + SystemCoreClock = __LFXT / dividerValue; + } + break; + case CS_CTL1_SELM__VLOCLK: + SystemCoreClock = __VLOCLK / dividerValue; + break; + case CS_CTL1_SELM__REFOCLK: + if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) + { + SystemCoreClock = (128000 / dividerValue); + } + else + { + SystemCoreClock = (32000 / dividerValue); + } + break; + case CS_CTL1_SELM__DCOCLK: + dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; + + switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) + { + case CS_CTL0_DCORSEL_0: + centeredFreq = 1500000; + break; + case CS_CTL0_DCORSEL_1: + centeredFreq = 3000000; + break; + case CS_CTL0_DCORSEL_2: + centeredFreq = 6000000; + break; + case CS_CTL0_DCORSEL_3: + centeredFreq = 12000000; + break; + case CS_CTL0_DCORSEL_4: + centeredFreq = 24000000; + break; + case CS_CTL0_DCORSEL_5: + centeredFreq = 48000000; + break; + } + + if(dcoTune == 0) + { + SystemCoreClock = centeredFreq; + } + else + { + + if(dcoTune & 0x1000) + { + dcoTune = dcoTune | 0xF000; + } + + if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) + { + dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); + calVal = TLV->DCOER_FCAL_RSEL04; + } + /* Internal Resistor */ + else + { + dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); + calVal = TLV->DCOIR_FCAL_RSEL04; + } + + SystemCoreClock = (uint32_t) ((centeredFreq) + / (1 + - ((dcoConst * dcoTune) + / (8 * (1 + dcoConst * (768 - calVal)))))); + } + break; + case CS_CTL1_SELM__MODOSC: + SystemCoreClock = __MODCLK / dividerValue; + break; + case CS_CTL1_SELM__HFXTCLK: + if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) + { + // Clear interrupt flag + CS->KEY = CS_KEY_VAL; + CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; + CS->KEY = 1; + + if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) + { + if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) + { + SystemCoreClock = (128000 / dividerValue); + } + else + { + SystemCoreClock = (32000 / dividerValue); + } + } + else + { + SystemCoreClock = __HFXT / dividerValue; + } + } + else + { + SystemCoreClock = __HFXT / dividerValue; + } + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * + * Performs the following initialization steps: + * 1. Enables the FPU + * 2. Halts the WDT if requested + * 3. Enables all SRAM banks + * 4. Sets up power regulator and VCORE + * 5. Enable Flash wait states if needed + * 6. Change MCLK to desired frequency + * 7. Enable Flash read buffering + */ +void SystemInit(void) +{ + // Enable FPU if used + #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ + SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ + (3UL << 11 * 2)); /* Set CP11 Full Access */ + #endif + + #if (__HALT_WDT == 1) + WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT + #endif + + SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks + + #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz + // Default VCORE is LDO VCORE0 so no change necessary + + // Switches LDO VCORE0 to DCDC VCORE0 if requested + #if __REGULATOR + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + #endif + + // No flash wait states necessary + + // DCO = 1.5 MHz; MCLK = source + CS->KEY = CS_KEY_VAL; // Unlock CS module for register access + CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz + CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source + CS->KEY = 0; + + // Set Flash Bank read buffering + FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + + #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz + // Default VCORE is LDO VCORE0 so no change necessary + + // Switches LDO VCORE0 to DCDC VCORE0 if requested + #if __REGULATOR + while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); + PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; + while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); + #endif + + // No flash wait states necessary + + // DCO = 3 MHz; MCLK = source + CS->KEY = CS_KEY_VAL; // Unlock CS module for register access + CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz + CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source + CS->KEY = 0; + + // Set Flash Bank read buffering + FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + + #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz + // Default VCORE is LDO VCORE0 so no change necessary + + // Switches LDO VCORE0 to DCDC VCORE0 if requested + #if __REGULATOR + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + #endif + + // No flash wait states necessary + + // DCO = 12 MHz; MCLK = source + CS->KEY = CS_KEY_VAL; // Unlock CS module for register access + CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz + CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source + CS->KEY = 0; + + // Set Flash Bank read buffering + FLCTL->BANK0_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + + #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz + // Default VCORE is LDO VCORE0 so no change necessary + + // Switches LDO VCORE0 to DCDC VCORE0 if requested + #if __REGULATOR + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + #endif + + // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) + FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; + FLCTL->BANK1_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_1; + + // DCO = 24 MHz; MCLK = source + CS->KEY = CS_KEY_VAL; // Unlock CS module for register access + CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz + CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source + CS->KEY = 0; + + // Set Flash Bank read buffering + FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + FLCTL->BANK1_RDCTL &= ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + + #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz + // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + + // Switches LDO VCORE1 to DCDC VCORE1 if requested + #if __REGULATOR + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; + while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); + #endif + + // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) + FLCTL->BANK0_RDCTL &= ~FLCTL_BANK0_RDCTL_WAIT_MASK | FLCTL_BANK0_RDCTL_WAIT_2; + FLCTL->BANK1_RDCTL &= ~FLCTL_BANK1_RDCTL_WAIT_MASK | FLCTL_BANK1_RDCTL_WAIT_2; + + // DCO = 48 MHz; MCLK = source + CS->KEY = CS_KEY_VAL; // Unlock CS module for register access + CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz + CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source + CS->KEY = 0; + + // Set Flash Bank read buffering + FLCTL->BANK0_RDCTL |= (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); + FLCTL->BANK1_RDCTL |= (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); + #endif + +}