Release_Notes.html - third_party/github/STMicroelectronics/cmsis_device_f7 - Git at Google

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 <h1 id="release-notes-for-stm32f7xx-cmsis"><strong>Release Notes for STM32F7xx CMSIS</strong></h1>
 <p>Copyright © 2019 STMicroelectronics<br />
 </p>
 <a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
 </center>
 </div>
 </div>
 <h1 id="license">License</h1>
 <p>This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this file except in compliance with the License. You may obtain a copy of the License at:</p>
 <center>
 <a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
 </center>
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 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history"><strong>Update History</strong></h1>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_2_5"  aria-hidden="true"> <label for="collapse-section1_2_5" aria-hidden="true"><strong>V1.2.5 / 13-February-2020</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
 <li>Add ADC missing calibration address for Vref and Temperature sensor.</li>
 <li>Align GPIO Bits Definitions to use _POS and _MSK.</li>
 <li>Add IS_UART_WAKEUP_FROMSTOP_INSTANCE macro for STM32F765xx, STM32F767xx, STM32F769xx,STM32F777xx and STM32F779xx devices.</li>
 <li>Add missing USART Bits Definitions in USART_CR1, USART_CR3, USART_ISR and USART_ICR registers for STM32F765xx, STM32F767xx, STM32F769xx,STM32F777xx and STM32F779xx devices.</li>
 <li>Add USB missing Bit Definition in USB_OTG_GUSBCFG register for STM32F722xx and STM32F732xx devices</li>
 <li>Remove dublicated Bits Definitions for OTG register</li>
 <li>Remove IS_TIM_SYNCHRO_INSTANCE macro.</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_2_4"  aria-hidden="true"> <label for="collapse-section1_2_4" aria-hidden="true"><strong>V1.2.4 / 08-February-2019</strong></label>
 <div>
 <h2 id="main-changes-1">Main Changes</h2>
 <ul>
 <li>CRYP
 <ul>
 <li>Update CMSIS devices with correct CRYP data input register name: DIN instead of DR<br />
 </li>
 </ul></li>
 <li>SAI -Fix frame length in SAI_xFRCR_FSALL &amp; SAI_xFRCR_FRL bits description</li>
 <li>USB
 <ul>
 <li>Add missing Bits Definitions in USB_OTG_DOEPMSK register
 <ul>
 <li>USB_OTG_DOEPMSK_AHBERRM</li>
 <li>USB_OTG_DOEPMSK_OTEPSPRM</li>
 <li>USB_OTG_DOEPMSK_BERRM</li>
 <li>USB_OTG_DOEPMSK_NAKM</li>
 <li>USB_OTG_DOEPMSK_NYETM</li>
 </ul></li>
 <li>Add missing Bits Definitions in USB_OTG_DIEPINT register
 <ul>
 <li>USB_OTG_DIEPINT_INEPNM</li>
 <li>USB_OTG_DIEPINT_AHBERR</li>
 <li>USB_OTG_DOEPINT_OUTPKTERR</li>
 <li>USB_OTG_DOEPINT_NAK</li>
 <li>USB_OTG_DOEPINT_STPKTRX</li>
 </ul></li>
 <li>Add missing Bits Definitions in USB_OTG_DCFG register
 <ul>
 <li>USB_OTG_DCFG_XCVRDLY</li>
 <li>USB_OTG_DCFG_ERRATIM</li>
 </ul></li>
 <li>Add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() defines</li>
 <li>Remove GADPCTL parameter from USB_OTG_GlobalTypeDef() structure</li>
 <li>Remove GPWRDN parameter from USB_OTG_GlobalTypeDef5° STRUCTURE</li>
 </ul></li>
 <li>DFSDM
 <ul>
 <li>Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF–&gt; DFSDM_FLTICR_CLRSCDF</li>
 </ul></li>
 <li>CEC
 <ul>
 <li>Align Bit naming for CEC_RXDR register: CEC_TXDR_RXD–&gt; CEC_RXDR_RXD</li>
 </ul></li>
 <li>QSPI
 <ul>
 <li>Update FLEVEL field in QuadSPI Status register definition to be compliant with user manual</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_2_3"  aria-hidden="true"> <label for="collapse-section1_2_3" aria-hidden="true"><strong>V1.2.3 / 29-June-2018</strong></label>
 <div>
 <h2 id="main-changes-2">Main Changes</h2>
 <ul>
 <li>Add the support of <strong>STM32F730xx and STM32F750xx</strong> devices
 <ul>
 <li>Add “stm32f730xx.h” and “stm32f750xx.h” header files</li>
 <li>Add startup files “startup_stm32f730xx.s” and “startup_stm32f750xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
 <li>Add Linker files “stm32f730xx_flash.icf”, “stm32f730xx_sram.icf” and “stm32f730xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f750xx_flash.icf”, “stm32f750xx_sram.icf” and “stm32f750xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_2_2"  aria-hidden="true"> <label for="collapse-section1_2_2" aria-hidden="true"><strong>V1.2.2 / 26-December-2017</strong></label>
 <div>
 <h2 id="main-changes-3">Main Changes</h2>
 <ul>
 <li>Update bits definition for USBPHYC_PLL1 and USBPHYC_LDO registers to be inline with products documentation.</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_2_1"  aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true"><strong>V1.2.1 / 25-August-2017</strong></label>
 <div>
 <h2 id="main-changes-4">Main Changes</h2>
 <ul>
 <li>Update FLASHSIZE_BASE and UID_BASE defined values for STM32F72x and STM32F73x devices.</li>
 <li>Update stm32f7xx.h to include stm32f7xx_hal.h file instead of stm32f7xx_hal_conf.h file</li>
 <li>Remove Date and Version from header files</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_2_0"  aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true"><strong>V1.2.0 / 30-December-2016</strong></label>
 <div>
 <h2 id="main-changes-5">Main Changes</h2>
 <ul>
 <li>Add the support of <strong>STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx</strong> devices
 <ul>
 <li>Add “stm32f722xx.h”, “stm32f723xx.h”, “stm32f732xx.h” and “stm32f733xx.h” header files</li>
 <li>Add startup files “startup_stm32f722xx.s”, “startup_stm32f723xx.s”, “startup_stm32f732xx.s” and “startup_stm32f733xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
 <li>Add Linker files “stm32f722xx_flash.icf”, “stm32f722xx_sram.icf” and “stm32f722xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f723xx_flash.icf”, “stm32f723xx_sram.icf” and “stm32f723xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f732xx_flash.icf”, “stm32f732xx_sram.icf” and “stm32f732xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f733xx_flash.icf”, “stm32f733xx_sram.icf” and “stm32f733xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 </ul></li>
 <li>All devices header files
 <ul>
 <li>Use _Pos and _Mask macro for all Bit Definitions</li>
 <li>Use DAC1 instance instead of DAC</li>
 <li>Add IS_SMBUS_ALL_INSTANCE macro</li>
 <li>Add ADC123_COMMON instance</li>
 <li>Add DMA_SxPAR_PA, DMA_SxM0AR_M0A and DMA_SxM1AR_M1A registers Bits Definition</li>
 <li>Add DBGMCU_APB1_FZ_DBG_LPTIM1_STOP and DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT Bits Definition</li>
 <li>Add FLASH_OTP_BASE and FLASH_OTP_END defines</li>
 <li>Add MACDBGR register Bits Definition</li>
 <li>Add GPIO_AFRL and GPIO_AFRH registers Bits Definition</li>
 <li>Add TIM2_OR, TIM5_OR and TIM11_OR registers Bits Definition</li>
 <li>Add TIM1_AF1_BKINP Bit Definition for TIM1_AF1 register</li>
 <li>Add IS_TIM_32B_COUNTER_INSTANCE, IS_TIM_BREAK_INSTANCE, IS_TIM_BREAKSOURCE_INSTANCE and IS_TIM_BKIN2_INSTANCE, IS_TIM_CLOCK_DIVISION_INSTANCE, IS_TIM_REPETITION_COUNTER_INSTANCE, IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE, IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE, IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE and IS_TIM_COMMUTATION_EVENT_INSTANCE macros</li>
 <li>Add IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE, IS_UART_HALFDUPLEX_INSTANCE and IS_UART_LIN_INSTANCE macros</li>
 <li>Remove TIM_SMCR_OCCS Bit Definition for TIM_SMCR register</li>
 <li>Remove USART_ISR_WUF and USART_ISR_REACK Bits Definition from USART_ISR register</li>
 <li>Rename USART_CR1_M_0 / USART_CR1_M_1 defines to USART_CR1_M0 / USART_CR1_M1</li>
 <li>Rename PACKAGESIZE_BASE define to PACKAGE_BASE</li>
 <li>Rename RTC_OR_ALARMTYPE Bit Definition to RTC_OR_ALARMOUTTYPE</li>
 <li>Rename RTC_CR_BCK Bit Definition to RTC_CR_BKP in RTC_CR register</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_1_1"  aria-hidden="true"> <label for="collapse-section1_1_1" aria-hidden="true"><strong>V1.1.1 / 01-July-2016</strong></label>
 <div>
 <h2 id="main-changes-6">Main Changes</h2>
 <ul>
 <li>stm32f7xx.h
 <ul>
 <li>update to respectively associate STM32F778xx and STM32F768xx devices to STM32F779xx and STM32F769xx devices</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_1_0"  aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true"><strong>V1.1.0 / 22-April-2016</strong></label>
 <div>
 <h2 id="main-changes-7">Main Changes</h2>
 <ul>
 <li>Add the support of <strong>STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx</strong> devices
 <ul>
 <li>Add “stm32f765xx.h”, “stm32f767xx.h”, “stm32f769xx.h”, “stm32f777xx.h” and “stm32f779xx.h” header files</li>
 <li>Add startup files “startup_stm32f765xx.s”, “startup_stm32f767xx.s”, “startup_stm32f769xx.s”, “startup_stm32f777xx.s” and “startup_stm32f779xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
 <li>Add Linker files “stm32f765xx_flash.icf”, “stm32f765xx_sram.icf” and “stm32f765xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f767xx_flash.icf”, “stm32f767xx_sram.icf” and “stm32f767xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f769xx_flash.icf”, “stm32f769xx_sram.icf” and “stm32f769xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f777xx_flash.icf”, “stm32f777xx_sram.icf” and “stm32f777xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>Add Linker files “stm32f779xx_flash.icf”, “stm32f779xx_sram.icf” and “stm32f779xx_ITCM_flash.icf” used within EWARM Workspaces</li>
 <li>STM32F768xx cmsis files are associated with STM32F767xx ones, as there is no difference between these devices on HAL side</li>
 <li>STM32F778xx cmsis files are associated with STM32F777xx ones, as there is no difference between these devices on HAL side</li>
 </ul></li>
 <li>All devices header files
 <ul>
 <li>Update Bit Definition names in DCMI_RISR / DCMI_IER registers</li>
 <li>Update Bit Definition names in DMA2D_CR / DMA2D_FGPFCCR / DMA2D_BGPFCCR / DMA2D_OPFCCR registers</li>
 <li>Update QUADSPI_CR_FTHRES Bit Definition in QUADSPI_CR register</li>
 <li>Rename SAI_xFRCR_FSPO to SAI_xFRCR_FSPOL in SAI_xFRCR register</li>
 <li>Rename ADC_CSR_DOVRx Bit Definition to ADC_CSR_OVRx in ADC_CSR register</li>
 <li>Rename LTDC_GCR_DTEN Bit Definition to LTDC_GCR_DEN in LTDC_GCR register</li>
 <li>Rename PWR_CSR1_UDSWRDY Bit Definition to PWR_CSR1_UDRDY in PWR_CSR1 register</li>
 <li>Rename RTC_TAMPCR_TAMPx_TRG Bit Definition to RTC_TAMPCR_TAMPxTRG in RTC_TAMPCR register</li>
 <li>Rename USART_ISR_LBD Bit Definition to USART_ISR_LBDF in USART_ISR register</li>
 <li>Rename IS_SAI_BLOCK_PERIPH macro to IS_SAI_ALL_INSTANCE</li>
 <li>Rename DCMI_ICR_OVF_ISC Bit Definition to DCMI_ICR_OVR_ISC</li>
 <li>Rename DMA2D_IFSR register to DMA2D_IFCR</li>
 <li>Rename EXTI_IMR_MRx Bit Definition to EXTI_IMR_IM0x</li>
 <li>Rename EXTI_EMR_MRx Bit Definition to EXTI_EMR_EMx</li>
 <li>Fix LPTIM_CR_SNGSTRT Bit Definition value in LPTIM_CR register</li>
 <li>Fix mask incorrect naming in DBGMCU_APB2_FZ register</li>
 <li>Fix Bits Definition for SYSCFG_EXTICR4_EXTI13_PI and SYSCFG_EXTICR4_EXTI13_PJ</li>
 <li>Add DAC_CR_DMAUDRIEx Bit Definition in DAC_CR register</li>
 <li>Add a new mask EXTI_IMR_IM in EXTI bits definition: Interrupt Mask All</li>
 <li>Add UID_BASE define for Unique ID register base address</li>
 <li>Add FLASHSIZE_BASE define for register base address</li>
 <li>Add PACKAGESIZE_BASE define for register base address</li>
 <li>Add FLASH_SECTOR_TOTAL define for total Flash sector number</li>
 <li>Add Bits Definition for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE and DCMI_DR registers</li>
 <li>Add PWR_CSR1_EIWUP Bit Definition in PWR_CSR1 register</li>
 <li>Add IP version define for QSPI: QSPI_V1_0</li>
 <li>Add IS_UART_DRIVER_ENABLE_INSTANCE macro</li>
 <li>Apply an ‘U’ suffix to all constants of ‘unsigned’ type (MISRA-C 2004 rule 10.6)</li>
 <li>Remove uint32_t cast in all defines</li>
 <li>Remove DMA_SxCR_ACK Bit Definition in DMA_SxCR register</li>
 <li>Remove I2C_CR1_SWRST / I2C_CR1_WUPEN Bit Definitions in I2C_CR1 register</li>
 <li>Keep the same DCMI register names (RISR, MISR, CWSTRTR and CWSIZER) as F4 family</li>
 </ul></li>
 <li>system_stm32f7xx.c/.h files
 <ul>
 <li>Remove external memories configuration from the system_stm32f7xx.c common file (moved to Template Projects)</li>
 <li>Add declaration of AHBPrescTable / APBPrescTable constant tables</li>
 </ul></li>
 <li>stm32f7xx.h
 <ul>
 <li>Rename __STM32F7xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F7_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_0_3"  aria-hidden="true"> <label for="collapse-section1_0_3" aria-hidden="true"><strong>V1.0.3 / 13-November-2015</strong></label>
 <div>
 <h2 id="main-changes-8">Main Changes</h2>
 <ul>
 <li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
 <ul>
 <li>update __CM7_REV with proper Cortex M7 core revision</li>
 <li>update SAI_xCR2_CPL bit definition</li>
 <li>update WWDG bits naming to be aligned with reference manual</li>
 <li>rename I2C_CR1_DFN bit to I2C_CR1_DNF</li>
 <li>remove OR register definition from LPTIM_TypeDef structure</li>
 </ul></li>
 <li>system_stm32f7xx.c
 <ul>
 <li>update SystemInit_ExtMemCtl() function implementation to allow simultaneous use of SDRAM and SRAM external memories</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_0_2"  aria-hidden="true"> <label for="collapse-section1_0_2" aria-hidden="true"><strong>V1.0.2 / 21-September-2015</strong></label>
 <div>
 <h2 id="main-changes-9">Main Changes</h2>
 <ul>
 <li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
 <ul>
 <li>add new define USB_OTG_DOEPMSK_OTEPSPRM</li>
 <li>add new define USB_OTG_DOEPINT_OTEPSPR</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_0_1"  aria-hidden="true"> <label for="collapse-section1_0_1" aria-hidden="true"><strong>V1.0.1 / 25-June-2015</strong></label>
 <div>
 <h2 id="main-changes-10">Main Changes</h2>
 <ul>
 <li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
 <ul>
 <li>update IDR field declaration in CRC_TypeDef sructure</li>
 <li>add I2C Own address 2 mask bits defininition in the I2C_OAR2 register</li>
 <li>update SAI_xSR_FLVL_2 bit definition</li>
 </ul></li>
 <li>stm32f756xx.h file
 <ul>
 <li>rename HASH_STR_NBWx bits definition to HASH_STR_NBLWx</li>
 <li>rename HASH_IMR_DINIM bit definition to HASH_IMR_DINIE</li>
 <li>rename HASH_IMR_DCIM bit definition to HASH_IMR_DCIE</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1_0_0"  aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true"><strong>V1.0.0 / 12-April-2019</strong></label>
 <div>
 <h2 id="main-changes-11">Main Changes</h2>
 <h3 id="first-release">First release</h3>
 <p>First official release for <strong>STM32F756xx/746xx/745xx</strong> devices</p>
 </div>
 </div>
 </div>
 </div>
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 For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span> <em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em>
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	<h1 id="release-notes-for-stm32f7xx-cmsis"><strong>Release Notes for STM32F7xx CMSIS</strong></h1>
	<p>Copyright © 2019 STMicroelectronics<br />
	</p>
	<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
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	<h1 id="license">License</h1>
	<p>This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this file except in compliance with the License. You may obtain a copy of the License at:</p>
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	<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
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	<h1 id="update-history"><strong>Update History</strong></h1>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_2_5" aria-hidden="true"> <label for="collapse-section1_2_5" aria-hidden="true"><strong>V1.2.5 / 13-February-2020</strong></label>
	<div>
	<h2 id="main-changes">Main Changes</h2>
	<ul>
	<li>Add ADC missing calibration address for Vref and Temperature sensor.</li>
	<li>Align GPIO Bits Definitions to use _POS and _MSK.</li>
	<li>Add IS_UART_WAKEUP_FROMSTOP_INSTANCE macro for STM32F765xx, STM32F767xx, STM32F769xx,STM32F777xx and STM32F779xx devices.</li>
	<li>Add missing USART Bits Definitions in USART_CR1, USART_CR3, USART_ISR and USART_ICR registers for STM32F765xx, STM32F767xx, STM32F769xx,STM32F777xx and STM32F779xx devices.</li>
	<li>Add USB missing Bit Definition in USB_OTG_GUSBCFG register for STM32F722xx and STM32F732xx devices</li>
	<li>Remove dublicated Bits Definitions for OTG register</li>
	<li>Remove IS_TIM_SYNCHRO_INSTANCE macro.</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_2_4" aria-hidden="true"> <label for="collapse-section1_2_4" aria-hidden="true"><strong>V1.2.4 / 08-February-2019</strong></label>
	<div>
	<h2 id="main-changes-1">Main Changes</h2>
	<ul>
	<li>CRYP
	<ul>
	<li>Update CMSIS devices with correct CRYP data input register name: DIN instead of DR<br />
	</li>
	</ul></li>
	<li>SAI -Fix frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits description</li>
	<li>USB
	<ul>
	<li>Add missing Bits Definitions in USB_OTG_DOEPMSK register
	<ul>
	<li>USB_OTG_DOEPMSK_AHBERRM</li>
	<li>USB_OTG_DOEPMSK_OTEPSPRM</li>
	<li>USB_OTG_DOEPMSK_BERRM</li>
	<li>USB_OTG_DOEPMSK_NAKM</li>
	<li>USB_OTG_DOEPMSK_NYETM</li>
	</ul></li>
	<li>Add missing Bits Definitions in USB_OTG_DIEPINT register
	<ul>
	<li>USB_OTG_DIEPINT_INEPNM</li>
	<li>USB_OTG_DIEPINT_AHBERR</li>
	<li>USB_OTG_DOEPINT_OUTPKTERR</li>
	<li>USB_OTG_DOEPINT_NAK</li>
	<li>USB_OTG_DOEPINT_STPKTRX</li>
	</ul></li>
	<li>Add missing Bits Definitions in USB_OTG_DCFG register
	<ul>
	<li>USB_OTG_DCFG_XCVRDLY</li>
	<li>USB_OTG_DCFG_ERRATIM</li>
	</ul></li>
	<li>Add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() defines</li>
	<li>Remove GADPCTL parameter from USB_OTG_GlobalTypeDef() structure</li>
	<li>Remove GPWRDN parameter from USB_OTG_GlobalTypeDef5° STRUCTURE</li>
	</ul></li>
	<li>DFSDM
	<ul>
	<li>Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF–> DFSDM_FLTICR_CLRSCDF</li>
	</ul></li>
	<li>CEC
	<ul>
	<li>Align Bit naming for CEC_RXDR register: CEC_TXDR_RXD–> CEC_RXDR_RXD</li>
	</ul></li>
	<li>QSPI
	<ul>
	<li>Update FLEVEL field in QuadSPI Status register definition to be compliant with user manual</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_2_3" aria-hidden="true"> <label for="collapse-section1_2_3" aria-hidden="true"><strong>V1.2.3 / 29-June-2018</strong></label>
	<div>
	<h2 id="main-changes-2">Main Changes</h2>
	<ul>
	<li>Add the support of <strong>STM32F730xx and STM32F750xx</strong> devices
	<ul>
	<li>Add “stm32f730xx.h” and “stm32f750xx.h” header files</li>
	<li>Add startup files “startup_stm32f730xx.s” and “startup_stm32f750xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
	<li>Add Linker files “stm32f730xx_flash.icf”, “stm32f730xx_sram.icf” and “stm32f730xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f750xx_flash.icf”, “stm32f750xx_sram.icf” and “stm32f750xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_2_2" aria-hidden="true"> <label for="collapse-section1_2_2" aria-hidden="true"><strong>V1.2.2 / 26-December-2017</strong></label>
	<div>
	<h2 id="main-changes-3">Main Changes</h2>
	<ul>
	<li>Update bits definition for USBPHYC_PLL1 and USBPHYC_LDO registers to be inline with products documentation.</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true"><strong>V1.2.1 / 25-August-2017</strong></label>
	<div>
	<h2 id="main-changes-4">Main Changes</h2>
	<ul>
	<li>Update FLASHSIZE_BASE and UID_BASE defined values for STM32F72x and STM32F73x devices.</li>
	<li>Update stm32f7xx.h to include stm32f7xx_hal.h file instead of stm32f7xx_hal_conf.h file</li>
	<li>Remove Date and Version from header files</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true"><strong>V1.2.0 / 30-December-2016</strong></label>
	<div>
	<h2 id="main-changes-5">Main Changes</h2>
	<ul>
	<li>Add the support of <strong>STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx</strong> devices
	<ul>
	<li>Add “stm32f722xx.h”, “stm32f723xx.h”, “stm32f732xx.h” and “stm32f733xx.h” header files</li>
	<li>Add startup files “startup_stm32f722xx.s”, “startup_stm32f723xx.s”, “startup_stm32f732xx.s” and “startup_stm32f733xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
	<li>Add Linker files “stm32f722xx_flash.icf”, “stm32f722xx_sram.icf” and “stm32f722xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f723xx_flash.icf”, “stm32f723xx_sram.icf” and “stm32f723xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f732xx_flash.icf”, “stm32f732xx_sram.icf” and “stm32f732xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f733xx_flash.icf”, “stm32f733xx_sram.icf” and “stm32f733xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	</ul></li>
	<li>All devices header files
	<ul>
	<li>Use _Pos and _Mask macro for all Bit Definitions</li>
	<li>Use DAC1 instance instead of DAC</li>
	<li>Add IS_SMBUS_ALL_INSTANCE macro</li>
	<li>Add ADC123_COMMON instance</li>
	<li>Add DMA_SxPAR_PA, DMA_SxM0AR_M0A and DMA_SxM1AR_M1A registers Bits Definition</li>
	<li>Add DBGMCU_APB1_FZ_DBG_LPTIM1_STOP and DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT Bits Definition</li>
	<li>Add FLASH_OTP_BASE and FLASH_OTP_END defines</li>
	<li>Add MACDBGR register Bits Definition</li>
	<li>Add GPIO_AFRL and GPIO_AFRH registers Bits Definition</li>
	<li>Add TIM2_OR, TIM5_OR and TIM11_OR registers Bits Definition</li>
	<li>Add TIM1_AF1_BKINP Bit Definition for TIM1_AF1 register</li>
	<li>Add IS_TIM_32B_COUNTER_INSTANCE, IS_TIM_BREAK_INSTANCE, IS_TIM_BREAKSOURCE_INSTANCE and IS_TIM_BKIN2_INSTANCE, IS_TIM_CLOCK_DIVISION_INSTANCE, IS_TIM_REPETITION_COUNTER_INSTANCE, IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE, IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE, IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE and IS_TIM_COMMUTATION_EVENT_INSTANCE macros</li>
	<li>Add IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE, IS_UART_HALFDUPLEX_INSTANCE and IS_UART_LIN_INSTANCE macros</li>
	<li>Remove TIM_SMCR_OCCS Bit Definition for TIM_SMCR register</li>
	<li>Remove USART_ISR_WUF and USART_ISR_REACK Bits Definition from USART_ISR register</li>
	<li>Rename USART_CR1_M_0 / USART_CR1_M_1 defines to USART_CR1_M0 / USART_CR1_M1</li>
	<li>Rename PACKAGESIZE_BASE define to PACKAGE_BASE</li>
	<li>Rename RTC_OR_ALARMTYPE Bit Definition to RTC_OR_ALARMOUTTYPE</li>
	<li>Rename RTC_CR_BCK Bit Definition to RTC_CR_BKP in RTC_CR register</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_1_1" aria-hidden="true"> <label for="collapse-section1_1_1" aria-hidden="true"><strong>V1.1.1 / 01-July-2016</strong></label>
	<div>
	<h2 id="main-changes-6">Main Changes</h2>
	<ul>
	<li>stm32f7xx.h
	<ul>
	<li>update to respectively associate STM32F778xx and STM32F768xx devices to STM32F779xx and STM32F769xx devices</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true"><strong>V1.1.0 / 22-April-2016</strong></label>
	<div>
	<h2 id="main-changes-7">Main Changes</h2>
	<ul>
	<li>Add the support of <strong>STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx</strong> devices
	<ul>
	<li>Add “stm32f765xx.h”, “stm32f767xx.h”, “stm32f769xx.h”, “stm32f777xx.h” and “stm32f779xx.h” header files</li>
	<li>Add startup files “startup_stm32f765xx.s”, “startup_stm32f767xx.s”, “startup_stm32f769xx.s”, “startup_stm32f777xx.s” and “startup_stm32f779xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains</li>
	<li>Add Linker files “stm32f765xx_flash.icf”, “stm32f765xx_sram.icf” and “stm32f765xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f767xx_flash.icf”, “stm32f767xx_sram.icf” and “stm32f767xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f769xx_flash.icf”, “stm32f769xx_sram.icf” and “stm32f769xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f777xx_flash.icf”, “stm32f777xx_sram.icf” and “stm32f777xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>Add Linker files “stm32f779xx_flash.icf”, “stm32f779xx_sram.icf” and “stm32f779xx_ITCM_flash.icf” used within EWARM Workspaces</li>
	<li>STM32F768xx cmsis files are associated with STM32F767xx ones, as there is no difference between these devices on HAL side</li>
	<li>STM32F778xx cmsis files are associated with STM32F777xx ones, as there is no difference between these devices on HAL side</li>
	</ul></li>
	<li>All devices header files
	<ul>
	<li>Update Bit Definition names in DCMI_RISR / DCMI_IER registers</li>
	<li>Update Bit Definition names in DMA2D_CR / DMA2D_FGPFCCR / DMA2D_BGPFCCR / DMA2D_OPFCCR registers</li>
	<li>Update QUADSPI_CR_FTHRES Bit Definition in QUADSPI_CR register</li>
	<li>Rename SAI_xFRCR_FSPO to SAI_xFRCR_FSPOL in SAI_xFRCR register</li>
	<li>Rename ADC_CSR_DOVRx Bit Definition to ADC_CSR_OVRx in ADC_CSR register</li>
	<li>Rename LTDC_GCR_DTEN Bit Definition to LTDC_GCR_DEN in LTDC_GCR register</li>
	<li>Rename PWR_CSR1_UDSWRDY Bit Definition to PWR_CSR1_UDRDY in PWR_CSR1 register</li>
	<li>Rename RTC_TAMPCR_TAMPx_TRG Bit Definition to RTC_TAMPCR_TAMPxTRG in RTC_TAMPCR register</li>
	<li>Rename USART_ISR_LBD Bit Definition to USART_ISR_LBDF in USART_ISR register</li>
	<li>Rename IS_SAI_BLOCK_PERIPH macro to IS_SAI_ALL_INSTANCE</li>
	<li>Rename DCMI_ICR_OVF_ISC Bit Definition to DCMI_ICR_OVR_ISC</li>
	<li>Rename DMA2D_IFSR register to DMA2D_IFCR</li>
	<li>Rename EXTI_IMR_MRx Bit Definition to EXTI_IMR_IM0x</li>
	<li>Rename EXTI_EMR_MRx Bit Definition to EXTI_EMR_EMx</li>
	<li>Fix LPTIM_CR_SNGSTRT Bit Definition value in LPTIM_CR register</li>
	<li>Fix mask incorrect naming in DBGMCU_APB2_FZ register</li>
	<li>Fix Bits Definition for SYSCFG_EXTICR4_EXTI13_PI and SYSCFG_EXTICR4_EXTI13_PJ</li>
	<li>Add DAC_CR_DMAUDRIEx Bit Definition in DAC_CR register</li>
	<li>Add a new mask EXTI_IMR_IM in EXTI bits definition: Interrupt Mask All</li>
	<li>Add UID_BASE define for Unique ID register base address</li>
	<li>Add FLASHSIZE_BASE define for register base address</li>
	<li>Add PACKAGESIZE_BASE define for register base address</li>
	<li>Add FLASH_SECTOR_TOTAL define for total Flash sector number</li>
	<li>Add Bits Definition for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE and DCMI_DR registers</li>
	<li>Add PWR_CSR1_EIWUP Bit Definition in PWR_CSR1 register</li>
	<li>Add IP version define for QSPI: QSPI_V1_0</li>
	<li>Add IS_UART_DRIVER_ENABLE_INSTANCE macro</li>
	<li>Apply an ‘U’ suffix to all constants of ‘unsigned’ type (MISRA-C 2004 rule 10.6)</li>
	<li>Remove uint32_t cast in all defines</li>
	<li>Remove DMA_SxCR_ACK Bit Definition in DMA_SxCR register</li>
	<li>Remove I2C_CR1_SWRST / I2C_CR1_WUPEN Bit Definitions in I2C_CR1 register</li>
	<li>Keep the same DCMI register names (RISR, MISR, CWSTRTR and CWSIZER) as F4 family</li>
	</ul></li>
	<li>system_stm32f7xx.c/.h files
	<ul>
	<li>Remove external memories configuration from the system_stm32f7xx.c common file (moved to Template Projects)</li>
	<li>Add declaration of AHBPrescTable / APBPrescTable constant tables</li>
	</ul></li>
	<li>stm32f7xx.h
	<ul>
	<li>Rename __STM32F7xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F7_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_0_3" aria-hidden="true"> <label for="collapse-section1_0_3" aria-hidden="true"><strong>V1.0.3 / 13-November-2015</strong></label>
	<div>
	<h2 id="main-changes-8">Main Changes</h2>
	<ul>
	<li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
	<ul>
	<li>update __CM7_REV with proper Cortex M7 core revision</li>
	<li>update SAI_xCR2_CPL bit definition</li>
	<li>update WWDG bits naming to be aligned with reference manual</li>
	<li>rename I2C_CR1_DFN bit to I2C_CR1_DNF</li>
	<li>remove OR register definition from LPTIM_TypeDef structure</li>
	</ul></li>
	<li>system_stm32f7xx.c
	<ul>
	<li>update SystemInit_ExtMemCtl() function implementation to allow simultaneous use of SDRAM and SRAM external memories</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_0_2" aria-hidden="true"> <label for="collapse-section1_0_2" aria-hidden="true"><strong>V1.0.2 / 21-September-2015</strong></label>
	<div>
	<h2 id="main-changes-9">Main Changes</h2>
	<ul>
	<li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
	<ul>
	<li>add new define USB_OTG_DOEPMSK_OTEPSPRM</li>
	<li>add new define USB_OTG_DOEPINT_OTEPSPR</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1_0_1" aria-hidden="true"> <label for="collapse-section1_0_1" aria-hidden="true"><strong>V1.0.1 / 25-June-2015</strong></label>
	<div>
	<h2 id="main-changes-10">Main Changes</h2>
	<ul>
	<li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
	<ul>
	<li>update IDR field declaration in CRC_TypeDef sructure</li>
	<li>add I2C Own address 2 mask bits defininition in the I2C_OAR2 register</li>
	<li>update SAI_xSR_FLVL_2 bit definition</li>
	</ul></li>
	<li>stm32f756xx.h file
	<ul>
	<li>rename HASH_STR_NBWx bits definition to HASH_STR_NBLWx</li>
	<li>rename HASH_IMR_DINIM bit definition to HASH_IMR_DINIE</li>
	<li>rename HASH_IMR_DCIM bit definition to HASH_IMR_DCIE</li>
	</ul></li>
	</ul>
	</div>
	</div>
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	<input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true"><strong>V1.0.0 / 12-April-2019</strong></label>
	<div>
	<h2 id="main-changes-11">Main Changes</h2>
	<h3 id="first-release">First release</h3>
	<p>First official release for <strong>STM32F756xx/746xx/745xx</strong> devices</p>
	</div>
	</div>
	</div>
	</div>
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