| /** |
| ****************************************************************************** |
| * @file stm32f769xx.h |
| * @author MCD Application Team |
| * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. |
| * |
| * This file contains: |
| * - Data structures and the address mapping for all peripherals |
| * - Peripheral's registers declarations and bits definition |
| * - Macros to access peripheralÂ’s registers hardware |
| * |
| ****************************************************************************** |
| * @attention |
| * |
| * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| * |
| * Redistribution and use in source and binary forms, with or without modification, |
| * are permitted provided that the following conditions are met: |
| * 1. Redistributions of source code must retain the above copyright notice, |
| * this list of conditions and the following disclaimer. |
| * 2. Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| * may be used to endorse or promote products derived from this software |
| * without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| * |
| ****************************************************************************** |
| */ |
| |
| /** @addtogroup CMSIS_Device |
| * @{ |
| */ |
| |
| /** @addtogroup stm32f769xx |
| * @{ |
| */ |
| |
| #ifndef __STM32F769xx_H |
| #define __STM32F769xx_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif /* __cplusplus */ |
| |
| /** @addtogroup Configuration_section_for_CMSIS |
| * @{ |
| */ |
| |
| /** |
| * @brief STM32F7xx Interrupt Number Definition, according to the selected device |
| * in @ref Library_configuration_section |
| */ |
| typedef enum |
| { |
| /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ |
| NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ |
| BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ |
| UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ |
| SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ |
| DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ |
| PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ |
| SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ |
| /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ |
| FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ |
| DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ |
| DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ |
| DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ |
| DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ |
| DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ |
| DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ |
| ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ |
| CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ |
| CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ |
| CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ |
| TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ |
| TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
| TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ |
| TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ |
| TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ |
| TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
| TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ |
| FMC_IRQn = 48, /*!< FMC global Interrupt */ |
| SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ |
| TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ |
| TIM7_IRQn = 55, /*!< TIM7 global interrupt */ |
| DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ |
| DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ |
| DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ |
| DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ |
| DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ |
| ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
| ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
| CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
| CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
| CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
| CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
| OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ |
| DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ |
| DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ |
| DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ |
| USART6_IRQn = 71, /*!< USART6 global interrupt */ |
| I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ |
| I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ |
| OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ |
| OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ |
| OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ |
| OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ |
| DCMI_IRQn = 78, /*!< DCMI global interrupt */ |
| RNG_IRQn = 80, /*!< RNG global interrupt */ |
| FPU_IRQn = 81, /*!< FPU global interrupt */ |
| UART7_IRQn = 82, /*!< UART7 global interrupt */ |
| UART8_IRQn = 83, /*!< UART8 global interrupt */ |
| SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ |
| SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ |
| SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ |
| SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ |
| LTDC_IRQn = 88, /*!< LTDC global Interrupt */ |
| LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ |
| DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ |
| SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ |
| QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ |
| LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ |
| CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ |
| I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ |
| I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ |
| SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ |
| DSI_IRQn = 98, /*!< DSI global Interrupt */ |
| DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */ |
| DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */ |
| DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */ |
| DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */ |
| SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */ |
| CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */ |
| CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */ |
| CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */ |
| CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */ |
| JPEG_IRQn = 108, /*!< JPEG global Interrupt */ |
| MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */ |
| } IRQn_Type; |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @brief Configuration of the Cortex-M7 Processor and Core Peripherals |
| */ |
| #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ |
| #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ |
| #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ |
| #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| #define __FPU_PRESENT 1 /*!< FPU present */ |
| #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ |
| #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ |
| #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ |
| |
| |
| #include "system_stm32f7xx.h" |
| #include <stdint.h> |
| |
| /** @addtogroup Peripheral_registers_structures |
| * @{ |
| */ |
| |
| /** |
| * @brief Analog to Digital Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ |
| __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ |
| __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ |
| __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ |
| __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ |
| __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ |
| __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ |
| __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ |
| __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ |
| __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ |
| __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ |
| __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ |
| __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ |
| __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ |
| __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ |
| __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ |
| __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ |
| __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ |
| __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ |
| __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ |
| } ADC_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ |
| __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ |
| __IO uint32_t CDR; /*!< ADC common regular data register for dual |
| AND triple modes, Address offset: ADC1 base address + 0x308 */ |
| } ADC_Common_TypeDef; |
| |
| |
| /** |
| * @brief Controller Area Network TxMailBox |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| } CAN_TxMailBox_TypeDef; |
| |
| /** |
| * @brief Controller Area Network FIFOMailBox |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| } CAN_FIFOMailBox_TypeDef; |
| |
| /** |
| * @brief Controller Area Network FilterRegister |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| } CAN_FilterRegister_TypeDef; |
| |
| /** |
| * @brief Controller Area Network |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| } CAN_TypeDef; |
| |
| /** |
| * @brief HDMI-CEC |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ |
| __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ |
| __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ |
| __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ |
| __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ |
| __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ |
| }CEC_TypeDef; |
| |
| /** |
| * @brief CRC calculation unit |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
| } CRC_TypeDef; |
| |
| /** |
| * @brief Digital to Analog Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| } DAC_TypeDef; |
| |
| /** |
| * @brief DFSDM module registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ |
| __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ |
| __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ |
| __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ |
| __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ |
| __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ |
| __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ |
| __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ |
| __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ |
| __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ |
| __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ |
| __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ |
| __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ |
| __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ |
| __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ |
| } DFSDM_Filter_TypeDef; |
| |
| /** |
| * @brief DFSDM channel configuration registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ |
| __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ |
| __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and |
| short circuit detector register, Address offset: 0x08 */ |
| __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ |
| __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ |
| } DFSDM_Channel_TypeDef; |
| |
| /** |
| * @brief Debug MCU |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| }DBGMCU_TypeDef; |
| |
| /** |
| * @brief DCMI |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ |
| __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ |
| __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ |
| __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ |
| __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ |
| __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ |
| __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ |
| __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ |
| __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ |
| __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ |
| } DCMI_TypeDef; |
| |
| /** |
| * @brief DMA Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DMA stream x configuration register */ |
| __IO uint32_t NDTR; /*!< DMA stream x number of data register */ |
| __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ |
| __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ |
| __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ |
| __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ |
| } DMA_Stream_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ |
| __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ |
| __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ |
| __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ |
| } DMA_TypeDef; |
| |
| /** |
| * @brief DMA2D Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ |
| __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ |
| __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ |
| __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ |
| __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ |
| __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ |
| __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ |
| __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ |
| __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ |
| __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ |
| __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ |
| __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ |
| __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ |
| __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ |
| __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ |
| __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ |
| __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ |
| __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ |
| __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ |
| __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ |
| uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ |
| __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ |
| __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ |
| } DMA2D_TypeDef; |
| |
| |
| /** |
| * @brief Ethernet MAC |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MACCR; |
| __IO uint32_t MACFFR; |
| __IO uint32_t MACHTHR; |
| __IO uint32_t MACHTLR; |
| __IO uint32_t MACMIIAR; |
| __IO uint32_t MACMIIDR; |
| __IO uint32_t MACFCR; |
| __IO uint32_t MACVLANTR; /* 8 */ |
| uint32_t RESERVED0[2]; |
| __IO uint32_t MACRWUFFR; /* 11 */ |
| __IO uint32_t MACPMTCSR; |
| uint32_t RESERVED1; |
| __IO uint32_t MACDBGR; |
| __IO uint32_t MACSR; /* 15 */ |
| __IO uint32_t MACIMR; |
| __IO uint32_t MACA0HR; |
| __IO uint32_t MACA0LR; |
| __IO uint32_t MACA1HR; |
| __IO uint32_t MACA1LR; |
| __IO uint32_t MACA2HR; |
| __IO uint32_t MACA2LR; |
| __IO uint32_t MACA3HR; |
| __IO uint32_t MACA3LR; /* 24 */ |
| uint32_t RESERVED2[40]; |
| __IO uint32_t MMCCR; /* 65 */ |
| __IO uint32_t MMCRIR; |
| __IO uint32_t MMCTIR; |
| __IO uint32_t MMCRIMR; |
| __IO uint32_t MMCTIMR; /* 69 */ |
| uint32_t RESERVED3[14]; |
| __IO uint32_t MMCTGFSCCR; /* 84 */ |
| __IO uint32_t MMCTGFMSCCR; |
| uint32_t RESERVED4[5]; |
| __IO uint32_t MMCTGFCR; |
| uint32_t RESERVED5[10]; |
| __IO uint32_t MMCRFCECR; |
| __IO uint32_t MMCRFAECR; |
| uint32_t RESERVED6[10]; |
| __IO uint32_t MMCRGUFCR; |
| uint32_t RESERVED7[334]; |
| __IO uint32_t PTPTSCR; |
| __IO uint32_t PTPSSIR; |
| __IO uint32_t PTPTSHR; |
| __IO uint32_t PTPTSLR; |
| __IO uint32_t PTPTSHUR; |
| __IO uint32_t PTPTSLUR; |
| __IO uint32_t PTPTSAR; |
| __IO uint32_t PTPTTHR; |
| __IO uint32_t PTPTTLR; |
| __IO uint32_t RESERVED8; |
| __IO uint32_t PTPTSSR; |
| uint32_t RESERVED9[565]; |
| __IO uint32_t DMABMR; |
| __IO uint32_t DMATPDR; |
| __IO uint32_t DMARPDR; |
| __IO uint32_t DMARDLAR; |
| __IO uint32_t DMATDLAR; |
| __IO uint32_t DMASR; |
| __IO uint32_t DMAOMR; |
| __IO uint32_t DMAIER; |
| __IO uint32_t DMAMFBOCR; |
| __IO uint32_t DMARSWTR; |
| uint32_t RESERVED10[8]; |
| __IO uint32_t DMACHTDR; |
| __IO uint32_t DMACHRDR; |
| __IO uint32_t DMACHTBAR; |
| __IO uint32_t DMACHRBAR; |
| } ETH_TypeDef; |
| |
| /** |
| * @brief External Interrupt/Event Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ |
| __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ |
| __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ |
| __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ |
| __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ |
| __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ |
| } EXTI_TypeDef; |
| |
| /** |
| * @brief FLASH Registers |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ |
| __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ |
| __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ |
| __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ |
| __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ |
| } FLASH_TypeDef; |
| |
| |
| |
| /** |
| * @brief Flexible Memory Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| } FMC_Bank1_TypeDef; |
| |
| /** |
| * @brief Flexible Memory Controller Bank1E |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| } FMC_Bank1E_TypeDef; |
| |
| /** |
| * @brief Flexible Memory Controller Bank3 |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ |
| __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ |
| __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ |
| __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ |
| uint32_t RESERVED0; /*!< Reserved, 0x90 */ |
| __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ |
| } FMC_Bank3_TypeDef; |
| |
| /** |
| * @brief Flexible Memory Controller Bank5_6 |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ |
| __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ |
| __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ |
| __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ |
| __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ |
| } FMC_Bank5_6_TypeDef; |
| |
| |
| /** |
| * @brief General Purpose I/O |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ |
| __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| } GPIO_TypeDef; |
| |
| /** |
| * @brief System configuration controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
| __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ |
| __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| uint32_t RESERVED; /*!< Reserved, 0x18 */ |
| __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */ |
| __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ |
| } SYSCFG_TypeDef; |
| |
| /** |
| * @brief Inter-integrated Circuit Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| } I2C_TypeDef; |
| |
| /** |
| * @brief Independent WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| } IWDG_TypeDef; |
| |
| |
| /** |
| * @brief LCD-TFT Display Controller |
| */ |
| |
| typedef struct |
| { |
| uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ |
| __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ |
| __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ |
| __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ |
| __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ |
| __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ |
| uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ |
| __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ |
| uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ |
| __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ |
| uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ |
| __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ |
| __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ |
| __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ |
| __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ |
| __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ |
| __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ |
| } LTDC_TypeDef; |
| |
| /** |
| * @brief LCD-TFT Display layer x Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ |
| __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ |
| __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ |
| __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ |
| __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ |
| __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ |
| __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ |
| __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ |
| uint32_t RESERVED0[2]; /*!< Reserved */ |
| __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ |
| __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ |
| __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ |
| uint32_t RESERVED1[3]; /*!< Reserved */ |
| __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ |
| |
| } LTDC_Layer_TypeDef; |
| |
| /** |
| * @brief Power Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ |
| __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ |
| __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ |
| __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ |
| } PWR_TypeDef; |
| |
| |
| /** |
| * @brief Reset and Clock Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ |
| __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ |
| __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ |
| __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ |
| __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ |
| __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ |
| uint32_t RESERVED0; /*!< Reserved, 0x1C */ |
| __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ |
| __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ |
| uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ |
| __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ |
| __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ |
| __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x3C */ |
| __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ |
| __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ |
| uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ |
| __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ |
| __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ |
| __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ |
| uint32_t RESERVED4; /*!< Reserved, 0x5C */ |
| __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ |
| __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ |
| uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ |
| __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ |
| __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ |
| uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ |
| __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ |
| __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ |
| __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ |
| __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ |
| __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ |
| |
| } RCC_TypeDef; |
| |
| /** |
| * @brief Real-Time Clock |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| uint32_t reserved; /*!< Reserved */ |
| __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ |
| __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ |
| __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
| __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
| __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
| __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
| __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ |
| __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ |
| __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ |
| __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ |
| __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ |
| __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ |
| __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ |
| __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ |
| __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ |
| __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ |
| __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ |
| __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ |
| } RTC_TypeDef; |
| |
| |
| /** |
| * @brief Serial Audio Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ |
| } SAI_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ |
| __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ |
| __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ |
| __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ |
| __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ |
| __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ |
| __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ |
| __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ |
| } SAI_Block_TypeDef; |
| |
| /** |
| * @brief SPDIF-RX Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ |
| __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ |
| __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ |
| __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ |
| __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ |
| __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ |
| } SPDIFRX_TypeDef; |
| |
| /** |
| * @brief SD host Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ |
| __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ |
| __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ |
| __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ |
| __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ |
| __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ |
| __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ |
| __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ |
| __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ |
| __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ |
| __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ |
| __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ |
| __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ |
| __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ |
| __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ |
| __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ |
| uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ |
| __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ |
| uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ |
| __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ |
| } SDMMC_TypeDef; |
| |
| /** |
| * @brief Serial Peripheral Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ |
| __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ |
| __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ |
| __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ |
| __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| } SPI_TypeDef; |
| |
| /** |
| * @brief QUAD Serial Peripheral Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ |
| __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ |
| __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ |
| __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ |
| __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ |
| __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ |
| __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ |
| __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ |
| __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ |
| __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ |
| __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ |
| __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ |
| } QUADSPI_TypeDef; |
| |
| /** |
| * @brief TIM |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ |
| __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ |
| __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ |
| __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ |
| __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ |
| |
| } TIM_TypeDef; |
| |
| /** |
| * @brief LPTIMIMER |
| */ |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ |
| __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ |
| __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ |
| __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ |
| __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ |
| __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ |
| __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ |
| __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ |
| } LPTIM_TypeDef; |
| |
| |
| /** |
| * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| } USART_TypeDef; |
| |
| |
| /** |
| * @brief Window WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| } WWDG_TypeDef; |
| |
| |
| /** |
| * @brief RNG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ |
| __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ |
| __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ |
| } RNG_TypeDef; |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @brief USB_OTG_Core_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ |
| __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ |
| __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ |
| __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ |
| __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ |
| __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ |
| __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ |
| __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ |
| __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ |
| __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ |
| __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ |
| __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ |
| uint32_t Reserved30[2]; /*!< Reserved 030h */ |
| __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ |
| __IO uint32_t CID; /*!< User ID Register 03Ch */ |
| uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ |
| __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ |
| uint32_t Reserved6; /*!< Reserved 050h */ |
| __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ |
| uint32_t Reserved7; /*!< Reserved 058h */ |
| __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ |
| uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */ |
| __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ |
| __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ |
| } USB_OTG_GlobalTypeDef; |
| |
| |
| /** |
| * @brief USB_OTG_device_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ |
| __IO uint32_t DCTL; /*!< dev Control Register 804h */ |
| __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ |
| uint32_t Reserved0C; /*!< Reserved 80Ch */ |
| __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ |
| __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ |
| __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ |
| __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ |
| uint32_t Reserved20; /*!< Reserved 820h */ |
| uint32_t Reserved9; /*!< Reserved 824h */ |
| __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ |
| __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ |
| __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ |
| __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ |
| __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ |
| __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ |
| uint32_t Reserved40; /*!< dedicated EP mask 840h */ |
| __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ |
| uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ |
| __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ |
| } USB_OTG_DeviceTypeDef; |
| |
| |
| /** |
| * @brief USB_OTG_IN_Endpoint-Specific_Register |
| */ |
| typedef struct |
| { |
| __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ |
| uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ |
| __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ |
| uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ |
| __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ |
| __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ |
| __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ |
| uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ |
| } USB_OTG_INEndpointTypeDef; |
| |
| |
| /** |
| * @brief USB_OTG_OUT_Endpoint-Specific_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ |
| uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ |
| __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ |
| uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ |
| __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ |
| __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ |
| uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ |
| } USB_OTG_OUTEndpointTypeDef; |
| |
| |
| /** |
| * @brief USB_OTG_Host_Mode_Register_Structures |
| */ |
| typedef struct |
| { |
| __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ |
| __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ |
| __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ |
| uint32_t Reserved40C; /*!< Reserved 40Ch */ |
| __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ |
| __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ |
| __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ |
| } USB_OTG_HostTypeDef; |
| |
| /** |
| * @brief USB_OTG_Host_Channel_Specific_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ |
| __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ |
| __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ |
| __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ |
| __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ |
| __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ |
| uint32_t Reserved[2]; /*!< Reserved */ |
| } USB_OTG_HostChannelTypeDef; |
| /** |
| * @} |
| */ |
| |
| /** |
| * @brief JPEG Codec |
| */ |
| typedef struct |
| { |
| __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ |
| __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ |
| __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ |
| __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ |
| __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ |
| __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ |
| __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ |
| __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ |
| uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ |
| __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ |
| __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ |
| __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ |
| uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ |
| __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ |
| __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ |
| uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ |
| __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ |
| __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ |
| __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ |
| __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ |
| __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ |
| __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ |
| __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ |
| __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ |
| uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ |
| __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */ |
| __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */ |
| __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */ |
| __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */ |
| |
| } JPEG_TypeDef; |
| |
| /** |
| * @brief MDIOS |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */ |
| __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */ |
| __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */ |
| __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ |
| __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ |
| __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */ |
| __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ |
| uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ |
| __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ |
| __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ |
| __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ |
| __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ |
| __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ |
| __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ |
| __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ |
| __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ |
| __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ |
| __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ |
| __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ |
| __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ |
| __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ |
| __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ |
| __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ |
| __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ |
| __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ |
| __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ |
| __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ |
| __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ |
| __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ |
| __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ |
| __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ |
| __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ |
| __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ |
| __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ |
| __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ |
| __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ |
| __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ |
| __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ |
| __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ |
| __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ |
| __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ |
| __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ |
| __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ |
| __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ |
| __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ |
| __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ |
| __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ |
| __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */ |
| __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */ |
| __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */ |
| __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */ |
| __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */ |
| __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */ |
| __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */ |
| __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */ |
| __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */ |
| __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */ |
| __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */ |
| __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */ |
| __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */ |
| __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */ |
| __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */ |
| __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */ |
| __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */ |
| __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */ |
| __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */ |
| __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */ |
| __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */ |
| __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */ |
| __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */ |
| __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */ |
| __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */ |
| } MDIOS_TypeDef; |
| |
| /** |
| * @brief DSI Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ |
| __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ |
| __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ |
| __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ |
| __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ |
| __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ |
| uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ |
| __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ |
| __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ |
| __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ |
| __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ |
| __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ |
| __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ |
| __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ |
| __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ |
| __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ |
| __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ |
| __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ |
| __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ |
| __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ |
| __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ |
| __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ |
| __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ |
| __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ |
| __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ |
| __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ |
| __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ |
| __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ |
| __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ |
| __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ |
| __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ |
| __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ |
| __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ |
| __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ |
| __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ |
| __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ |
| uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ |
| __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ |
| __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ |
| uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ |
| __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ |
| uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ |
| __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ |
| uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ |
| __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ |
| __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ |
| uint32_t RESERVED5; /*!< Reserved, 0x114 */ |
| __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ |
| uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ |
| __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ |
| __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ |
| __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ |
| __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ |
| __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ |
| __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ |
| __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ |
| __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ |
| __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ |
| __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ |
| __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ |
| uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ |
| __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ |
| uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ |
| __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ |
| __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ |
| __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ |
| __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ |
| __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ |
| uint32_t RESERVED9; /*!< Reserved, 0x414 */ |
| __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ |
| uint32_t RESERVED10; /*!< Reserved, 0x42C */ |
| __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ |
| } DSI_TypeDef; |
| |
| /** @addtogroup Peripheral_memory_map |
| * @{ |
| */ |
| #define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ |
| #define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ |
| #define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ |
| #define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 128KB system data RAM accessible over DTCM */ |
| #define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */ |
| #define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */ |
| #define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */ |
| #define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */ |
| #define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */ |
| #define SRAM1_BASE 0x20020000UL /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */ |
| #define SRAM2_BASE 0x2007C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ |
| #define FLASH_END 0x081FFFFFUL /*!< FLASH end address */ |
| #define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ |
| #define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ |
| |
| /* Legacy define */ |
| #define FLASH_BASE FLASHAXI_BASE |
| |
| /*!< Peripheral memory map */ |
| #define APB1PERIPH_BASE PERIPH_BASE |
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
| |
| /*!< APB1 peripherals */ |
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) |
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) |
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) |
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) |
| #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) |
| #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) |
| #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) |
| #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) |
| #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) |
| #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) |
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) |
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) |
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) |
| #define CAN3_BASE (APB1PERIPH_BASE + 0x3400UL) |
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) |
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) |
| #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) |
| #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) |
| #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) |
| #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) |
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) |
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) |
| #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) |
| #define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL) |
| #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) |
| #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) |
| #define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) |
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) |
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) |
| #define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) |
| #define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) |
| |
| /*!< APB2 peripherals */ |
| #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) |
| #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) |
| #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) |
| #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) |
| #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL) |
| #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) |
| #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) |
| #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) |
| #define ADC_BASE (APB2PERIPH_BASE + 0x2300UL) |
| #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL) |
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) |
| #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) |
| #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) |
| #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) |
| #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) |
| #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) |
| #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) |
| #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) |
| #define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL) |
| #define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) |
| #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) |
| #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) |
| #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) |
| #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) |
| #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) |
| #define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL) |
| #define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) |
| #define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) |
| #define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL) |
| #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400UL) |
| #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) |
| #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) |
| #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) |
| #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) |
| #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) |
| #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) |
| #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) |
| #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) |
| #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) |
| #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) |
| #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) |
| #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) |
| #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800UL) |
| /*!< AHB1 peripherals */ |
| #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) |
| #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) |
| #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) |
| #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) |
| #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) |
| #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) |
| #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) |
| #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) |
| #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) |
| #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL) |
| #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL) |
| #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) |
| #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) |
| #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) |
| #define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */ |
| #define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */ |
| #define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */ |
| /* Legacy define */ |
| #define PACKAGESIZE_BASE PACKAGE_BASE |
| |
| #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) |
| #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) |
| #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) |
| #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) |
| #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) |
| #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) |
| #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) |
| #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) |
| #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) |
| #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) |
| #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) |
| #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) |
| #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) |
| #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) |
| #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) |
| #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) |
| #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) |
| #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) |
| #define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) |
| #define ETH_MAC_BASE (ETH_BASE) |
| #define ETH_MMC_BASE (ETH_BASE + 0x0100UL) |
| #define ETH_PTP_BASE (ETH_BASE + 0x0700UL) |
| #define ETH_DMA_BASE (ETH_BASE + 0x1000UL) |
| #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) |
| /*!< AHB2 peripherals */ |
| #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) |
| #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000UL) |
| #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) |
| /*!< FMC Bankx registers base address */ |
| #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) |
| #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) |
| #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) |
| #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) |
| |
| /* Debug MCU registers base address */ |
| #define DBGMCU_BASE 0xE0042000UL |
| |
| /*!< USB registers base address */ |
| #define USB_OTG_HS_PERIPH_BASE 0x40040000UL |
| #define USB_OTG_FS_PERIPH_BASE 0x50000000UL |
| |
| #define USB_OTG_GLOBAL_BASE 0x0000UL |
| #define USB_OTG_DEVICE_BASE 0x0800UL |
| #define USB_OTG_IN_ENDPOINT_BASE 0x0900UL |
| #define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL |
| #define USB_OTG_EP_REG_SIZE 0x0020UL |
| #define USB_OTG_HOST_BASE 0x0400UL |
| #define USB_OTG_HOST_PORT_BASE 0x0440UL |
| #define USB_OTG_HOST_CHANNEL_BASE 0x0500UL |
| #define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL |
| #define USB_OTG_PCGCCTL_BASE 0x0E00UL |
| #define USB_OTG_FIFO_BASE 0x1000UL |
| #define USB_OTG_FIFO_SIZE 0x1000UL |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_declaration |
| * @{ |
| */ |
| #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| #define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
| #define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
| #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
| #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) |
| #define RTC ((RTC_TypeDef *) RTC_BASE) |
| #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) |
| #define USART2 ((USART_TypeDef *) USART2_BASE) |
| #define USART3 ((USART_TypeDef *) USART3_BASE) |
| #define UART4 ((USART_TypeDef *) UART4_BASE) |
| #define UART5 ((USART_TypeDef *) UART5_BASE) |
| #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
| #define I2C4 ((I2C_TypeDef *) I2C4_BASE) |
| #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
| #define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
| #define CEC ((CEC_TypeDef *) CEC_BASE) |
| #define PWR ((PWR_TypeDef *) PWR_BASE) |
| #define DAC1 ((DAC_TypeDef *) DAC_BASE) |
| #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ |
| #define UART7 ((USART_TypeDef *) UART7_BASE) |
| #define UART8 ((USART_TypeDef *) UART8_BASE) |
| #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| #define USART1 ((USART_TypeDef *) USART1_BASE) |
| #define USART6 ((USART_TypeDef *) USART6_BASE) |
| #define ADC ((ADC_Common_TypeDef *) ADC_BASE) |
| #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
| #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
| #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) |
| #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) |
| #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| #define SPI4 ((SPI_TypeDef *) SPI4_BASE) |
| #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
| #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
| #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
| #define SPI5 ((SPI_TypeDef *) SPI5_BASE) |
| #define SPI6 ((SPI_TypeDef *) SPI6_BASE) |
| #define SAI1 ((SAI_TypeDef *) SAI1_BASE) |
| #define SAI2 ((SAI_TypeDef *) SAI2_BASE) |
| #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
| #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
| #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) |
| #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) |
| #define LTDC ((LTDC_TypeDef *)LTDC_BASE) |
| #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) |
| #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) |
| #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
| #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
| #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) |
| #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) |
| #define CRC ((CRC_TypeDef *) CRC_BASE) |
| #define RCC ((RCC_TypeDef *) RCC_BASE) |
| #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
| #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
| #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
| #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
| #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
| #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
| #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
| #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
| #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
| #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
| #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
| #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
| #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
| #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
| #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
| #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
| #define ETH ((ETH_TypeDef *) ETH_BASE) |
| #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) |
| #define DCMI ((DCMI_TypeDef *) DCMI_BASE) |
| #define RNG ((RNG_TypeDef *) RNG_BASE) |
| #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
| #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
| #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) |
| #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) |
| #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) |
| #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
| #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) |
| #define CAN3 ((CAN_TypeDef *) CAN3_BASE) |
| #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) |
| #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) |
| #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) |
| #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) |
| #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) |
| #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) |
| #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) |
| #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) |
| #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) |
| #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) |
| #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) |
| #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) |
| #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) |
| #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) |
| #define JPEG ((JPEG_TypeDef *) JPEG_BASE) |
| #define DSI ((DSI_TypeDef *)DSI_BASE) |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Exported_constants |
| * @{ |
| */ |
| |
| /** @addtogroup Peripheral_Registers_Bits_Definition |
| * @{ |
| */ |
| |
| /******************************************************************************/ |
| /* Peripheral Registers_Bits_Definition */ |
| /******************************************************************************/ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Analog to Digital Converter */ |
| /* */ |
| /******************************************************************************/ |
| /******************** Bit definition for ADC_SR register ********************/ |
| #define ADC_SR_AWD_Pos (0U) |
| #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
| #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */ |
| #define ADC_SR_EOC_Pos (1U) |
| #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */ |
| #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */ |
| #define ADC_SR_JEOC_Pos (2U) |
| #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */ |
| #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */ |
| #define ADC_SR_JSTRT_Pos (3U) |
| #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
| #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */ |
| #define ADC_SR_STRT_Pos (4U) |
| #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
| #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */ |
| #define ADC_SR_OVR_Pos (5U) |
| #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */ |
| #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */ |
| |
| /******************* Bit definition for ADC_CR1 register ********************/ |
| #define ADC_CR1_AWDCH_Pos (0U) |
| #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
| #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
| #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
| #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
| #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
| #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
| #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
| #define ADC_CR1_EOCIE_Pos (5U) |
| #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */ |
| #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */ |
| #define ADC_CR1_AWDIE_Pos (6U) |
| #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
| #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */ |
| #define ADC_CR1_JEOCIE_Pos (7U) |
| #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */ |
| #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */ |
| #define ADC_CR1_SCAN_Pos (8U) |
| #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
| #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */ |
| #define ADC_CR1_AWDSGL_Pos (9U) |
| #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
| #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */ |
| #define ADC_CR1_JAUTO_Pos (10U) |
| #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
| #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */ |
| #define ADC_CR1_DISCEN_Pos (11U) |
| #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
| #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */ |
| #define ADC_CR1_JDISCEN_Pos (12U) |
| #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
| #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */ |
| #define ADC_CR1_DISCNUM_Pos (13U) |
| #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
| #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
| #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
| #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
| #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
| #define ADC_CR1_JAWDEN_Pos (22U) |
| #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
| #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */ |
| #define ADC_CR1_AWDEN_Pos (23U) |
| #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
| #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */ |
| #define ADC_CR1_RES_Pos (24U) |
| #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */ |
| #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */ |
| #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */ |
| #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */ |
| #define ADC_CR1_OVRIE_Pos (26U) |
| #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ |
| #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */ |
| |
| /******************* Bit definition for ADC_CR2 register ********************/ |
| #define ADC_CR2_ADON_Pos (0U) |
| #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
| #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */ |
| #define ADC_CR2_CONT_Pos (1U) |
| #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
| #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */ |
| #define ADC_CR2_DMA_Pos (8U) |
| #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
| #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */ |
| #define ADC_CR2_DDS_Pos (9U) |
| #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ |
| #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */ |
| #define ADC_CR2_EOCS_Pos (10U) |
| #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ |
| #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */ |
| #define ADC_CR2_ALIGN_Pos (11U) |
| #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
| #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */ |
| #define ADC_CR2_JEXTSEL_Pos (16U) |
| #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ |
| #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */ |
| #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ |
| #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ |
| #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ |
| #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ |
| #define ADC_CR2_JEXTEN_Pos (20U) |
| #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ |
| #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ |
| #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ |
| #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ |
| #define ADC_CR2_JSWSTART_Pos (22U) |
| #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ |
| #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */ |
| #define ADC_CR2_EXTSEL_Pos (24U) |
| #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ |
| #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ |
| #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ |
| #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ |
| #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ |
| #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ |
| #define ADC_CR2_EXTEN_Pos (28U) |
| #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ |
| #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ |
| #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ |
| #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ |
| #define ADC_CR2_SWSTART_Pos (30U) |
| #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ |
| #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */ |
| |
| /****************** Bit definition for ADC_SMPR1 register *******************/ |
| #define ADC_SMPR1_SMP10_Pos (0U) |
| #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
| #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ |
| #define ADC_SMPR1_SMP11_Pos (3U) |
| #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ |
| #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
| #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ |
| #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ |
| #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ |
| #define ADC_SMPR1_SMP12_Pos (6U) |
| #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ |
| #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
| #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ |
| #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ |
| #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ |
| #define ADC_SMPR1_SMP13_Pos (9U) |
| #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ |
| #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
| #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ |
| #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ |
| #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ |
| #define ADC_SMPR1_SMP14_Pos (12U) |
| #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ |
| #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
| #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ |
| #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ |
| #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ |
| #define ADC_SMPR1_SMP15_Pos (15U) |
| #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ |
| #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
| #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ |
| #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ |
| #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ |
| #define ADC_SMPR1_SMP16_Pos (18U) |
| #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ |
| #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
| #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ |
| #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ |
| #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ |
| #define ADC_SMPR1_SMP17_Pos (21U) |
| #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ |
| #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
| #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ |
| #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ |
| #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ |
| #define ADC_SMPR1_SMP18_Pos (24U) |
| #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */ |
| #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ |
| #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */ |
| #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */ |
| #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */ |
| |
| /****************** Bit definition for ADC_SMPR2 register *******************/ |
| #define ADC_SMPR2_SMP0_Pos (0U) |
| #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
| #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ |
| #define ADC_SMPR2_SMP1_Pos (3U) |
| #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ |
| #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
| #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ |
| #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ |
| #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ |
| #define ADC_SMPR2_SMP2_Pos (6U) |
| #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ |
| #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
| #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ |
| #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ |
| #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ |
| #define ADC_SMPR2_SMP3_Pos (9U) |
| #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ |
| #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
| #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ |
| #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ |
| #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ |
| #define ADC_SMPR2_SMP4_Pos (12U) |
| #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ |
| #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
| #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ |
| #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ |
| #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ |
| #define ADC_SMPR2_SMP5_Pos (15U) |
| #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ |
| #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
| #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ |
| #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ |
| #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ |
| #define ADC_SMPR2_SMP6_Pos (18U) |
| #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ |
| #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
| #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ |
| #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ |
| #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ |
| #define ADC_SMPR2_SMP7_Pos (21U) |
| #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ |
| #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
| #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ |
| #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ |
| #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ |
| #define ADC_SMPR2_SMP8_Pos (24U) |
| #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ |
| #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
| #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ |
| #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ |
| #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ |
| #define ADC_SMPR2_SMP9_Pos (27U) |
| #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ |
| #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
| #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ |
| #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ |
| #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ |
| |
| /****************** Bit definition for ADC_JOFR1 register *******************/ |
| #define ADC_JOFR1_JOFFSET1_Pos (0U) |
| #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */ |
| |
| /****************** Bit definition for ADC_JOFR2 register *******************/ |
| #define ADC_JOFR2_JOFFSET2_Pos (0U) |
| #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */ |
| |
| /****************** Bit definition for ADC_JOFR3 register *******************/ |
| #define ADC_JOFR3_JOFFSET3_Pos (0U) |
| #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */ |
| |
| /****************** Bit definition for ADC_JOFR4 register *******************/ |
| #define ADC_JOFR4_JOFFSET4_Pos (0U) |
| #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */ |
| |
| /******************* Bit definition for ADC_HTR register ********************/ |
| #define ADC_HTR_HT_Pos (0U) |
| #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
| #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */ |
| |
| /******************* Bit definition for ADC_LTR register ********************/ |
| #define ADC_LTR_LT_Pos (0U) |
| #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
| #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */ |
| |
| /******************* Bit definition for ADC_SQR1 register *******************/ |
| #define ADC_SQR1_SQ13_Pos (0U) |
| #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ |
| #define ADC_SQR1_SQ14_Pos (5U) |
| #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ |
| #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ |
| #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR1_SQ15_Pos (10U) |
| #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ |
| #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ |
| #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ |
| #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR1_SQ16_Pos (15U) |
| #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ |
| #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ |
| #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ |
| #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR1_L_Pos (20U) |
| #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ |
| #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */ |
| #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
| #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
| |
| /******************* Bit definition for ADC_SQR2 register *******************/ |
| #define ADC_SQR2_SQ7_Pos (0U) |
| #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ |
| #define ADC_SQR2_SQ8_Pos (5U) |
| #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ |
| #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ |
| #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR2_SQ9_Pos (10U) |
| #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ |
| #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ |
| #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ |
| #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR2_SQ10_Pos (15U) |
| #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ |
| #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ |
| #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ |
| #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR2_SQ11_Pos (20U) |
| #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ |
| #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ |
| #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ |
| #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ |
| #define ADC_SQR2_SQ12_Pos (25U) |
| #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ |
| #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ |
| #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ |
| #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ |
| #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ |
| #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ |
| |
| /******************* Bit definition for ADC_SQR3 register *******************/ |
| #define ADC_SQR3_SQ1_Pos (0U) |
| #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
| #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ |
| #define ADC_SQR3_SQ2_Pos (5U) |
| #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ |
| #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
| #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ |
| #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR3_SQ3_Pos (10U) |
| #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ |
| #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
| #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ |
| #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ |
| #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR3_SQ4_Pos (15U) |
| #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ |
| #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
| #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ |
| #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ |
| #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR3_SQ5_Pos (20U) |
| #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ |
| #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
| #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ |
| #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ |
| #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ |
| #define ADC_SQR3_SQ6_Pos (25U) |
| #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ |
| #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
| #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ |
| #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ |
| #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ |
| #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ |
| #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ |
| |
| /******************* Bit definition for ADC_JSQR register *******************/ |
| #define ADC_JSQR_JSQ1_Pos (0U) |
| #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
| #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
| #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
| #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
| #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
| #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
| #define ADC_JSQR_JSQ2_Pos (5U) |
| #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
| #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
| #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
| #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
| #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
| #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
| #define ADC_JSQR_JSQ3_Pos (10U) |
| #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
| #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
| #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
| #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
| #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
| #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
| #define ADC_JSQR_JSQ4_Pos (15U) |
| #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
| #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
| #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
| #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
| #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
| #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
| #define ADC_JSQR_JL_Pos (20U) |
| #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
| #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */ |
| #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
| #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
| |
| /******************* Bit definition for ADC_JDR1 register *******************/ |
| #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */ |
| |
| /******************* Bit definition for ADC_JDR2 register *******************/ |
| #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */ |
| |
| /******************* Bit definition for ADC_JDR3 register *******************/ |
| #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */ |
| |
| /******************* Bit definition for ADC_JDR4 register *******************/ |
| #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */ |
| |
| /******************** Bit definition for ADC_DR register ********************/ |
| #define ADC_DR_DATA_Pos (0U) |
| #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */ |
| #define ADC_DR_ADC2DATA_Pos (16U) |
| #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ |
| #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */ |
| |
| /******************* Bit definition for ADC_CSR register ********************/ |
| #define ADC_CSR_AWD1_Pos (0U) |
| #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ |
| #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */ |
| #define ADC_CSR_EOC1_Pos (1U) |
| #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */ |
| #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */ |
| #define ADC_CSR_JEOC1_Pos (2U) |
| #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */ |
| #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */ |
| #define ADC_CSR_JSTRT1_Pos (3U) |
| #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ |
| #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */ |
| #define ADC_CSR_STRT1_Pos (4U) |
| #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ |
| #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */ |
| #define ADC_CSR_OVR1_Pos (5U) |
| #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ |
| #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */ |
| #define ADC_CSR_AWD2_Pos (8U) |
| #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */ |
| #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */ |
| #define ADC_CSR_EOC2_Pos (9U) |
| #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */ |
| #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */ |
| #define ADC_CSR_JEOC2_Pos (10U) |
| #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */ |
| #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */ |
| #define ADC_CSR_JSTRT2_Pos (11U) |
| #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */ |
| #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */ |
| #define ADC_CSR_STRT2_Pos (12U) |
| #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */ |
| #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */ |
| #define ADC_CSR_OVR2_Pos (13U) |
| #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */ |
| #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */ |
| #define ADC_CSR_AWD3_Pos (16U) |
| #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */ |
| #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */ |
| #define ADC_CSR_EOC3_Pos (17U) |
| #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */ |
| #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */ |
| #define ADC_CSR_JEOC3_Pos (18U) |
| #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */ |
| #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */ |
| #define ADC_CSR_JSTRT3_Pos (19U) |
| #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */ |
| #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */ |
| #define ADC_CSR_STRT3_Pos (20U) |
| #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */ |
| #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */ |
| #define ADC_CSR_OVR3_Pos (21U) |
| #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */ |
| #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */ |
| |
| /* Legacy defines */ |
| #define ADC_CSR_DOVR1 ADC_CSR_OVR1 |
| #define ADC_CSR_DOVR2 ADC_CSR_OVR2 |
| #define ADC_CSR_DOVR3 ADC_CSR_OVR3 |
| |
| |
| /******************* Bit definition for ADC_CCR register ********************/ |
| #define ADC_CCR_MULTI_Pos (0U) |
| #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */ |
| #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ |
| #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */ |
| #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */ |
| #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */ |
| #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */ |
| #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */ |
| #define ADC_CCR_DELAY_Pos (8U) |
| #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ |
| #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ |
| #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ |
| #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ |
| #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ |
| #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ |
| #define ADC_CCR_DDS_Pos (13U) |
| #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */ |
| #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */ |
| #define ADC_CCR_DMA_Pos (14U) |
| #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */ |
| #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ |
| #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */ |
| #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */ |
| #define ADC_CCR_ADCPRE_Pos (16U) |
| #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ |
| #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */ |
| #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ |
| #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ |
| #define ADC_CCR_VBATE_Pos (22U) |
| #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */ |
| #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */ |
| #define ADC_CCR_TSVREFE_Pos (23U) |
| #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ |
| #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */ |
| |
| /******************* Bit definition for ADC_CDR register ********************/ |
| #define ADC_CDR_DATA1_Pos (0U) |
| #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */ |
| #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */ |
| #define ADC_CDR_DATA2_Pos (16U) |
| #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */ |
| #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */ |
| |
| /* Legacy defines */ |
| #define ADC_CDR_RDATA_MST ADC_CDR_DATA1 |
| #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2 |
| |
| /******************************************************************************/ |
| /* */ |
| /* Controller Area Network */ |
| /* */ |
| /******************************************************************************/ |
| /*!<CAN control and status registers */ |
| /******************* Bit definition for CAN_MCR register ********************/ |
| #define CAN_MCR_INRQ_Pos (0U) |
| #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
| #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ |
| #define CAN_MCR_SLEEP_Pos (1U) |
| #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
| #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ |
| #define CAN_MCR_TXFP_Pos (2U) |
| #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
| #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ |
| #define CAN_MCR_RFLM_Pos (3U) |
| #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
| #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ |
| #define CAN_MCR_NART_Pos (4U) |
| #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
| #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ |
| #define CAN_MCR_AWUM_Pos (5U) |
| #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
| #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ |
| #define CAN_MCR_ABOM_Pos (6U) |
| #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
| #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ |
| #define CAN_MCR_TTCM_Pos (7U) |
| #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
| #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ |
| #define CAN_MCR_RESET_Pos (15U) |
| #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
| #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ |
| |
| /******************* Bit definition for CAN_MSR register ********************/ |
| #define CAN_MSR_INAK_Pos (0U) |
| #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
| #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ |
| #define CAN_MSR_SLAK_Pos (1U) |
| #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
| #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ |
| #define CAN_MSR_ERRI_Pos (2U) |
| #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
| #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ |
| #define CAN_MSR_WKUI_Pos (3U) |
| #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
| #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ |
| #define CAN_MSR_SLAKI_Pos (4U) |
| #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
| #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ |
| #define CAN_MSR_TXM_Pos (8U) |
| #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
| #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ |
| #define CAN_MSR_RXM_Pos (9U) |
| #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
| #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ |
| #define CAN_MSR_SAMP_Pos (10U) |
| #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
| #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ |
| #define CAN_MSR_RX_Pos (11U) |
| #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
| #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ |
| |
| /******************* Bit definition for CAN_TSR register ********************/ |
| #define CAN_TSR_RQCP0_Pos (0U) |
| #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
| #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ |
| #define CAN_TSR_TXOK0_Pos (1U) |
| #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
| #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ |
| #define CAN_TSR_ALST0_Pos (2U) |
| #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
| #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ |
| #define CAN_TSR_TERR0_Pos (3U) |
| #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
| #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ |
| #define CAN_TSR_ABRQ0_Pos (7U) |
| #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
| #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ |
| #define CAN_TSR_RQCP1_Pos (8U) |
| #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
| #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ |
| #define CAN_TSR_TXOK1_Pos (9U) |
| #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
| #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ |
| #define CAN_TSR_ALST1_Pos (10U) |
| #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
| #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ |
| #define CAN_TSR_TERR1_Pos (11U) |
| #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
| #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ |
| #define CAN_TSR_ABRQ1_Pos (15U) |
| #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
| #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ |
| #define CAN_TSR_RQCP2_Pos (16U) |
| #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
| #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ |
| #define CAN_TSR_TXOK2_Pos (17U) |
| #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
| #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ |
| #define CAN_TSR_ALST2_Pos (18U) |
| #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
| #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ |
| #define CAN_TSR_TERR2_Pos (19U) |
| #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
| #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ |
| #define CAN_TSR_ABRQ2_Pos (23U) |
| #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
| #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ |
| #define CAN_TSR_CODE_Pos (24U) |
| #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
| #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ |
| |
| #define CAN_TSR_TME_Pos (26U) |
| #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
| #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ |
| #define CAN_TSR_TME0_Pos (26U) |
| #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
| #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ |
| #define CAN_TSR_TME1_Pos (27U) |
| #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
| #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ |
| #define CAN_TSR_TME2_Pos (28U) |
| #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
| #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ |
| |
| #define CAN_TSR_LOW_Pos (29U) |
| #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
| #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ |
| #define CAN_TSR_LOW0_Pos (29U) |
| #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
| #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ |
| #define CAN_TSR_LOW1_Pos (30U) |
| #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
| #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ |
| #define CAN_TSR_LOW2_Pos (31U) |
| #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
| #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ |
| |
| /******************* Bit definition for CAN_RF0R register *******************/ |
| #define CAN_RF0R_FMP0_Pos (0U) |
| #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
| #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ |
| #define CAN_RF0R_FULL0_Pos (3U) |
| #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
| #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ |
| #define CAN_RF0R_FOVR0_Pos (4U) |
| #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
| #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ |
| #define CAN_RF0R_RFOM0_Pos (5U) |
| #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
| #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ |
| |
| /******************* Bit definition for CAN_RF1R register *******************/ |
| #define CAN_RF1R_FMP1_Pos (0U) |
| #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
| #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ |
| #define CAN_RF1R_FULL1_Pos (3U) |
| #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
| #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ |
| #define CAN_RF1R_FOVR1_Pos (4U) |
| #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
| #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ |
| #define CAN_RF1R_RFOM1_Pos (5U) |
| #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
| #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ |
| |
| /******************** Bit definition for CAN_IER register *******************/ |
| #define CAN_IER_TMEIE_Pos (0U) |
| #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
| #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ |
| #define CAN_IER_FMPIE0_Pos (1U) |
| #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
| #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| #define CAN_IER_FFIE0_Pos (2U) |
| #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
| #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ |
| #define CAN_IER_FOVIE0_Pos (3U) |
| #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
| #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ |
| #define CAN_IER_FMPIE1_Pos (4U) |
| #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
| #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| #define CAN_IER_FFIE1_Pos (5U) |
| #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
| #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ |
| #define CAN_IER_FOVIE1_Pos (6U) |
| #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
| #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ |
| #define CAN_IER_EWGIE_Pos (8U) |
| #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
| #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ |
| #define CAN_IER_EPVIE_Pos (9U) |
| #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
| #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ |
| #define CAN_IER_BOFIE_Pos (10U) |
| #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
| #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ |
| #define CAN_IER_LECIE_Pos (11U) |
| #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
| #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ |
| #define CAN_IER_ERRIE_Pos (15U) |
| #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
| #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ |
| #define CAN_IER_WKUIE_Pos (16U) |
| #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
| #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ |
| #define CAN_IER_SLKIE_Pos (17U) |
| #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
| #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ |
| |
| /******************** Bit definition for CAN_ESR register *******************/ |
| #define CAN_ESR_EWGF_Pos (0U) |
| #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
| #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ |
| #define CAN_ESR_EPVF_Pos (1U) |
| #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
| #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ |
| #define CAN_ESR_BOFF_Pos (2U) |
| #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
| #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ |
| |
| #define CAN_ESR_LEC_Pos (4U) |
| #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
| #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ |
| #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
| #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
| #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
| |
| #define CAN_ESR_TEC_Pos (16U) |
| #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
| #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
| #define CAN_ESR_REC_Pos (24U) |
| #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
| #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ |
| |
| /******************* Bit definition for CAN_BTR register ********************/ |
| #define CAN_BTR_BRP_Pos (0U) |
| #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
| #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
| #define CAN_BTR_TS1_Pos (16U) |
| #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
| #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
| #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
| #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
| #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
| #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
| #define CAN_BTR_TS2_Pos (20U) |
| #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
| #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
| #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
| #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
| #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
| #define CAN_BTR_SJW_Pos (24U) |
| #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
| #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
| #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
| #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
| #define CAN_BTR_LBKM_Pos (30U) |
| #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
| #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
| #define CAN_BTR_SILM_Pos (31U) |
| #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
| #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
| |
| /*!<Mailbox registers */ |
| /****************** Bit definition for CAN_TI0R register ********************/ |
| #define CAN_TI0R_TXRQ_Pos (0U) |
| #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
| #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| #define CAN_TI0R_RTR_Pos (1U) |
| #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
| #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ |
| #define CAN_TI0R_IDE_Pos (2U) |
| #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
| #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ |
| #define CAN_TI0R_EXID_Pos (3U) |
| #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ |
| #define CAN_TI0R_STID_Pos (21U) |
| #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
| #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| |
| /****************** Bit definition for CAN_TDT0R register *******************/ |
| #define CAN_TDT0R_DLC_Pos (0U) |
| #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
| #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ |
| #define CAN_TDT0R_TGT_Pos (8U) |
| #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
| #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ |
| #define CAN_TDT0R_TIME_Pos (16U) |
| #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ |
| |
| /****************** Bit definition for CAN_TDL0R register *******************/ |
| #define CAN_TDL0R_DATA0_Pos (0U) |
| #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ |
| #define CAN_TDL0R_DATA1_Pos (8U) |
| #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ |
| #define CAN_TDL0R_DATA2_Pos (16U) |
| #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ |
| #define CAN_TDL0R_DATA3_Pos (24U) |
| #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ |
| |
| /****************** Bit definition for CAN_TDH0R register *******************/ |
| #define CAN_TDH0R_DATA4_Pos (0U) |
| #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ |
| #define CAN_TDH0R_DATA5_Pos (8U) |
| #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
|