Release v1.8.0
diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index c790bd5..18d5a4f 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -2,7 +2,7 @@ ### Contributor License Agreement (CLA) * The Pull Request feature will be considered by STMicroelectronics after the signature of a **Contributor License Agreement (CLA)** by the submiter. -* If you have not signed such agreement, please follow the rules mentioned in the CONTRIBUTING.md file. +* If you have not signed such agreement, please follow the rules mentioned in the [CONTRIBUTING.md](https://github.com/STMicroelectronics/cmsis_device_h7/blob/master/CONTRIBUTING.md) file.
diff --git a/Include/stm32h742xx.h b/Include/stm32h742xx.h index 309aebb..8238908 100644 --- a/Include/stm32h742xx.h +++ b/Include/stm32h742xx.h
@@ -8403,6 +8403,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -14529,12 +14532,6 @@ #define RCC_AHB2ENR_DCMIEN_Pos (0U) #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk -#define RCC_AHB2ENR_CRYPEN_Pos (4U) -#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk -#define RCC_AHB2ENR_HASHEN_Pos (5U) -#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk #define RCC_AHB2ENR_RNGEN_Pos (6U) #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk @@ -14848,12 +14845,6 @@ #define RCC_AHB2RSTR_DCMIRST_Pos (0U) #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */ #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk -#define RCC_AHB2RSTR_CRYPRST_Pos (4U) -#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */ -#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk -#define RCC_AHB2RSTR_HASHRST_Pos (5U) -#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */ -#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk #define RCC_AHB2RSTR_RNGRST_Pos (6U) #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk @@ -15223,12 +15214,6 @@ #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk -#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U) -#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk -#define RCC_AHB2LPENR_HASHLPEN_Pos (5U) -#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk @@ -20369,6 +20354,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h743xx.h b/Include/stm32h743xx.h index 09f4191..d6b54eb 100644 --- a/Include/stm32h743xx.h +++ b/Include/stm32h743xx.h
@@ -8498,6 +8498,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -15162,12 +15165,6 @@ #define RCC_AHB2ENR_DCMIEN_Pos (0U) #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk -#define RCC_AHB2ENR_CRYPEN_Pos (4U) -#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk -#define RCC_AHB2ENR_HASHEN_Pos (5U) -#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk #define RCC_AHB2ENR_RNGEN_Pos (6U) #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk @@ -15487,12 +15484,6 @@ #define RCC_AHB2RSTR_DCMIRST_Pos (0U) #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */ #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk -#define RCC_AHB2RSTR_CRYPRST_Pos (4U) -#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */ -#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk -#define RCC_AHB2RSTR_HASHRST_Pos (5U) -#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */ -#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk #define RCC_AHB2RSTR_RNGRST_Pos (6U) #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk @@ -15868,12 +15859,6 @@ #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk -#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U) -#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk -#define RCC_AHB2LPENR_HASHLPEN_Pos (5U) -#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk @@ -21017,6 +21002,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h745xx.h b/Include/stm32h745xx.h index 1028f36..f90d1ff 100644 --- a/Include/stm32h745xx.h +++ b/Include/stm32h745xx.h
@@ -8601,6 +8601,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -15753,12 +15756,6 @@ #define RCC_AHB2ENR_DCMIEN_Pos (0U) #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk -#define RCC_AHB2ENR_CRYPEN_Pos (4U) -#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk -#define RCC_AHB2ENR_HASHEN_Pos (5U) -#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk #define RCC_AHB2ENR_RNGEN_Pos (6U) #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk @@ -16084,12 +16081,6 @@ #define RCC_AHB2RSTR_DCMIRST_Pos (0U) #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */ #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk -#define RCC_AHB2RSTR_CRYPRST_Pos (4U) -#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */ -#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk -#define RCC_AHB2RSTR_HASHRST_Pos (5U) -#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */ -#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk #define RCC_AHB2RSTR_RNGRST_Pos (6U) #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk @@ -16477,12 +16468,6 @@ #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk -#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U) -#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk -#define RCC_AHB2LPENR_HASHLPEN_Pos (5U) -#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk @@ -21671,6 +21656,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h747xx.h b/Include/stm32h747xx.h index ee6ff53..d234685 100644 --- a/Include/stm32h747xx.h +++ b/Include/stm32h747xx.h
@@ -8684,6 +8684,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -18913,12 +18916,6 @@ #define RCC_AHB2ENR_DCMIEN_Pos (0U) #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk -#define RCC_AHB2ENR_CRYPEN_Pos (4U) -#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk -#define RCC_AHB2ENR_HASHEN_Pos (5U) -#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk #define RCC_AHB2ENR_RNGEN_Pos (6U) #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk @@ -19247,12 +19244,6 @@ #define RCC_AHB2RSTR_DCMIRST_Pos (0U) #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */ #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk -#define RCC_AHB2RSTR_CRYPRST_Pos (4U) -#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */ -#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk -#define RCC_AHB2RSTR_HASHRST_Pos (5U) -#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */ -#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk #define RCC_AHB2RSTR_RNGRST_Pos (6U) #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk @@ -19643,12 +19634,6 @@ #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk -#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U) -#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk -#define RCC_AHB2LPENR_HASHLPEN_Pos (5U) -#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk @@ -24844,6 +24829,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h750xx.h b/Include/stm32h750xx.h index fa6b4a3..ca5d576 100644 --- a/Include/stm32h750xx.h +++ b/Include/stm32h750xx.h
@@ -8691,6 +8691,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -21285,6 +21288,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h753xx.h b/Include/stm32h753xx.h index 03a6221..2d7fc92 100644 --- a/Include/stm32h753xx.h +++ b/Include/stm32h753xx.h
@@ -8691,6 +8691,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -21286,6 +21289,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h755xx.h b/Include/stm32h755xx.h index 998c799..fc0c2a5 100644 --- a/Include/stm32h755xx.h +++ b/Include/stm32h755xx.h
@@ -8794,6 +8794,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -21940,6 +21943,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h757xx.h b/Include/stm32h757xx.h index 4477b8e..a5b7a5a 100644 --- a/Include/stm32h757xx.h +++ b/Include/stm32h757xx.h
@@ -8877,6 +8877,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -25113,6 +25116,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x450UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h7a3xx.h b/Include/stm32h7a3xx.h index 6d8d749..ec58aec 100644 --- a/Include/stm32h7a3xx.h +++ b/Include/stm32h7a3xx.h
@@ -874,11 +874,7 @@ __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ - __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ - __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ - __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ - __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ } GFXMMU_TypeDef; @@ -1821,7 +1817,7 @@ typedef struct { __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ } OCTOSPIM_TypeDef; /** @@ -6497,6 +6493,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -9463,29 +9462,6 @@ #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */ #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */ -/****************** Bits definition for GFXMMU_HWCFGR register ****************/ -#define GFXMMU_HWCFGR_TBD_Pos (0U) -#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */ - -/****************** Bits definition for GFXMMU_VERR register ******************/ -#define GFXMMU_VERR_MINREV_Pos (0U) -#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define GFXMMU_VERR_MAJREV_Pos (4U) -#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - -/****************** Bits definition for GFXMMU_IPIDR register *****************/ -#define GFXMMU_IPIDR_ID_Pos (0U) -#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */ - -/****************** Bits definition for GFXMMU_SIDR register ******************/ -#define GFXMMU_SIDR_SID_Pos (0U) -#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */ - /****************** Bits definition for GFXMMU_LUTxL register *****************/ #define GFXMMU_LUTxL_EN_Pos (0U) #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */ @@ -13342,12 +13318,6 @@ #define RCC_AHB2ENR_HSEMEN_Pos (2U) #define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00000004 */ #define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk -#define RCC_AHB2ENR_CRYPEN_Pos (4U) -#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk -#define RCC_AHB2ENR_HASHEN_Pos (5U) -#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk #define RCC_AHB2ENR_RNGEN_Pos (6U) #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk @@ -13663,12 +13633,6 @@ #define RCC_AHB2RSTR_HSEMRST_Pos (2U) #define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00000004 */ #define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk -#define RCC_AHB2RSTR_CRYPRST_Pos (4U) -#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */ -#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk -#define RCC_AHB2RSTR_HASHRST_Pos (5U) -#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */ -#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk #define RCC_AHB2RSTR_RNGRST_Pos (6U) #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk @@ -14096,12 +14060,6 @@ #define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U) #define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk -#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U) -#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk -#define RCC_AHB2LPENR_HASHLPEN_Pos (5U) -#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk @@ -18949,39 +18907,48 @@ /* OCTOSPIM */ /* */ /******************************************************************************/ + +/*************** Bit definition for OCTOSPIM_CR register ********************/ +#define OCTOSPIM_CR_MUXEN_Pos (0U) +#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */ +#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */ +#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U) +#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */ +#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */ + /*************** Bit definition for OCTOSPIM_PCR register *******************/ #define OCTOSPIM_PCR_CLKEN_Pos (0U) #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */ -#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ +#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ #define OCTOSPIM_PCR_CLKSRC_Pos (1U) #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */ -#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ +#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ #define OCTOSPIM_PCR_DQSEN_Pos (4U) #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */ -#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ +#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ #define OCTOSPIM_PCR_DQSSRC_Pos (5U) #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */ -#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ +#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ #define OCTOSPIM_PCR_NCSEN_Pos (8U) #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */ -#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ +#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ #define OCTOSPIM_PCR_NCSSRC_Pos (9U) #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */ -#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ +#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ #define OCTOSPIM_PCR_IOLEN_Pos (16U) #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */ -#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ +#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ #define OCTOSPIM_PCR_IOLSRC_Pos (17U) #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */ -#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ +#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */ #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */ #define OCTOSPIM_PCR_IOHEN_Pos (24U) #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */ -#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ +#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ #define OCTOSPIM_PCR_IOHSRC_Pos (25U) #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */ -#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ +#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */ #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */ /******************************************************************************/ @@ -19751,6 +19718,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x480UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h7a3xxq.h b/Include/stm32h7a3xxq.h index 1b428cc..db771ad 100644 --- a/Include/stm32h7a3xxq.h +++ b/Include/stm32h7a3xxq.h
@@ -875,11 +875,7 @@ __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ - __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ - __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ - __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ - __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ } GFXMMU_TypeDef; @@ -1822,7 +1818,7 @@ typedef struct { __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ } OCTOSPIM_TypeDef; /** @@ -6498,6 +6494,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -9464,29 +9463,6 @@ #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */ #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */ -/****************** Bits definition for GFXMMU_HWCFGR register ****************/ -#define GFXMMU_HWCFGR_TBD_Pos (0U) -#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */ - -/****************** Bits definition for GFXMMU_VERR register ******************/ -#define GFXMMU_VERR_MINREV_Pos (0U) -#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define GFXMMU_VERR_MAJREV_Pos (4U) -#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - -/****************** Bits definition for GFXMMU_IPIDR register *****************/ -#define GFXMMU_IPIDR_ID_Pos (0U) -#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */ - -/****************** Bits definition for GFXMMU_SIDR register ******************/ -#define GFXMMU_SIDR_SID_Pos (0U) -#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */ - /****************** Bits definition for GFXMMU_LUTxL register *****************/ #define GFXMMU_LUTxL_EN_Pos (0U) #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */ @@ -13354,12 +13330,6 @@ #define RCC_AHB2ENR_HSEMEN_Pos (2U) #define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00000004 */ #define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk -#define RCC_AHB2ENR_CRYPEN_Pos (4U) -#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk -#define RCC_AHB2ENR_HASHEN_Pos (5U) -#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk #define RCC_AHB2ENR_RNGEN_Pos (6U) #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk @@ -13675,12 +13645,6 @@ #define RCC_AHB2RSTR_HSEMRST_Pos (2U) #define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00000004 */ #define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk -#define RCC_AHB2RSTR_CRYPRST_Pos (4U) -#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */ -#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk -#define RCC_AHB2RSTR_HASHRST_Pos (5U) -#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */ -#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk #define RCC_AHB2RSTR_RNGRST_Pos (6U) #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk @@ -14108,12 +14072,6 @@ #define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U) #define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk -#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U) -#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */ -#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk -#define RCC_AHB2LPENR_HASHLPEN_Pos (5U) -#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */ -#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk @@ -18961,39 +18919,48 @@ /* OCTOSPIM */ /* */ /******************************************************************************/ + +/*************** Bit definition for OCTOSPIM_CR register ********************/ +#define OCTOSPIM_CR_MUXEN_Pos (0U) +#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */ +#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */ +#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U) +#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */ +#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */ + /*************** Bit definition for OCTOSPIM_PCR register *******************/ #define OCTOSPIM_PCR_CLKEN_Pos (0U) #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */ -#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ +#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ #define OCTOSPIM_PCR_CLKSRC_Pos (1U) #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */ -#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ +#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ #define OCTOSPIM_PCR_DQSEN_Pos (4U) #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */ -#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ +#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ #define OCTOSPIM_PCR_DQSSRC_Pos (5U) #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */ -#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ +#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ #define OCTOSPIM_PCR_NCSEN_Pos (8U) #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */ -#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ +#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ #define OCTOSPIM_PCR_NCSSRC_Pos (9U) #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */ -#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ +#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ #define OCTOSPIM_PCR_IOLEN_Pos (16U) #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */ -#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ +#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ #define OCTOSPIM_PCR_IOLSRC_Pos (17U) #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */ -#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ +#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */ #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */ #define OCTOSPIM_PCR_IOHEN_Pos (24U) #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */ -#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ +#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ #define OCTOSPIM_PCR_IOHSRC_Pos (25U) #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */ -#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ +#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */ #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */ /******************************************************************************/ @@ -19763,6 +19730,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x480UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h7b0xx.h b/Include/stm32h7b0xx.h index baeac34..b3593bb 100644 --- a/Include/stm32h7b0xx.h +++ b/Include/stm32h7b0xx.h
@@ -877,11 +877,7 @@ __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ - __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ - __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ - __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ - __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ } GFXMMU_TypeDef; @@ -1893,7 +1889,7 @@ typedef struct { __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ } OCTOSPIM_TypeDef; /** @@ -6751,6 +6747,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -9716,29 +9715,6 @@ #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */ #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */ -/****************** Bits definition for GFXMMU_HWCFGR register ****************/ -#define GFXMMU_HWCFGR_TBD_Pos (0U) -#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */ - -/****************** Bits definition for GFXMMU_VERR register ******************/ -#define GFXMMU_VERR_MINREV_Pos (0U) -#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define GFXMMU_VERR_MAJREV_Pos (4U) -#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - -/****************** Bits definition for GFXMMU_IPIDR register *****************/ -#define GFXMMU_IPIDR_ID_Pos (0U) -#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */ - -/****************** Bits definition for GFXMMU_SIDR register ******************/ -#define GFXMMU_SIDR_SID_Pos (0U) -#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */ - /****************** Bits definition for GFXMMU_LUTxL register *****************/ #define GFXMMU_LUTxL_EN_Pos (0U) #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */ @@ -19417,39 +19393,48 @@ /* OCTOSPIM */ /* */ /******************************************************************************/ + +/*************** Bit definition for OCTOSPIM_CR register ********************/ +#define OCTOSPIM_CR_MUXEN_Pos (0U) +#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */ +#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */ +#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U) +#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */ +#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */ + /*************** Bit definition for OCTOSPIM_PCR register *******************/ #define OCTOSPIM_PCR_CLKEN_Pos (0U) #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */ -#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ +#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ #define OCTOSPIM_PCR_CLKSRC_Pos (1U) #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */ -#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ +#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ #define OCTOSPIM_PCR_DQSEN_Pos (4U) #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */ -#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ +#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ #define OCTOSPIM_PCR_DQSSRC_Pos (5U) #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */ -#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ +#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ #define OCTOSPIM_PCR_NCSEN_Pos (8U) #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */ -#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ +#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ #define OCTOSPIM_PCR_NCSSRC_Pos (9U) #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */ -#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ +#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ #define OCTOSPIM_PCR_IOLEN_Pos (16U) #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */ -#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ +#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ #define OCTOSPIM_PCR_IOLSRC_Pos (17U) #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */ -#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ +#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */ #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */ #define OCTOSPIM_PCR_IOHEN_Pos (24U) #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */ -#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ +#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ #define OCTOSPIM_PCR_IOHSRC_Pos (25U) #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */ -#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ +#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */ #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */ /******************************************************************************/ @@ -20219,6 +20204,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x480UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h7b0xxq.h b/Include/stm32h7b0xxq.h index 056f02f..cfb25a2 100644 --- a/Include/stm32h7b0xxq.h +++ b/Include/stm32h7b0xxq.h
@@ -878,11 +878,7 @@ __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ - __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ - __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ - __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ - __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ } GFXMMU_TypeDef; @@ -1894,7 +1890,7 @@ typedef struct { __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ } OCTOSPIM_TypeDef; /** @@ -6752,6 +6748,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -9717,29 +9716,6 @@ #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */ #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */ -/****************** Bits definition for GFXMMU_HWCFGR register ****************/ -#define GFXMMU_HWCFGR_TBD_Pos (0U) -#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */ - -/****************** Bits definition for GFXMMU_VERR register ******************/ -#define GFXMMU_VERR_MINREV_Pos (0U) -#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define GFXMMU_VERR_MAJREV_Pos (4U) -#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - -/****************** Bits definition for GFXMMU_IPIDR register *****************/ -#define GFXMMU_IPIDR_ID_Pos (0U) -#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */ - -/****************** Bits definition for GFXMMU_SIDR register ******************/ -#define GFXMMU_SIDR_SID_Pos (0U) -#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */ - /****************** Bits definition for GFXMMU_LUTxL register *****************/ #define GFXMMU_LUTxL_EN_Pos (0U) #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */ @@ -19429,39 +19405,48 @@ /* OCTOSPIM */ /* */ /******************************************************************************/ + +/*************** Bit definition for OCTOSPIM_CR register ********************/ +#define OCTOSPIM_CR_MUXEN_Pos (0U) +#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */ +#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */ +#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U) +#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */ +#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */ + /*************** Bit definition for OCTOSPIM_PCR register *******************/ #define OCTOSPIM_PCR_CLKEN_Pos (0U) #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */ -#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ +#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ #define OCTOSPIM_PCR_CLKSRC_Pos (1U) #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */ -#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ +#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ #define OCTOSPIM_PCR_DQSEN_Pos (4U) #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */ -#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ +#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ #define OCTOSPIM_PCR_DQSSRC_Pos (5U) #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */ -#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ +#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ #define OCTOSPIM_PCR_NCSEN_Pos (8U) #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */ -#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ +#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ #define OCTOSPIM_PCR_NCSSRC_Pos (9U) #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */ -#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ +#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ #define OCTOSPIM_PCR_IOLEN_Pos (16U) #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */ -#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ +#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ #define OCTOSPIM_PCR_IOLSRC_Pos (17U) #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */ -#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ +#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */ #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */ #define OCTOSPIM_PCR_IOHEN_Pos (24U) #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */ -#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ +#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ #define OCTOSPIM_PCR_IOHSRC_Pos (25U) #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */ -#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ +#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */ #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */ /******************************************************************************/ @@ -20231,6 +20216,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x480UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h7b3xx.h b/Include/stm32h7b3xx.h index 210f959..873f429 100644 --- a/Include/stm32h7b3xx.h +++ b/Include/stm32h7b3xx.h
@@ -877,11 +877,7 @@ __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ - __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ - __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ - __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ - __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ } GFXMMU_TypeDef; @@ -1893,7 +1889,7 @@ typedef struct { __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ } OCTOSPIM_TypeDef; /** @@ -6751,6 +6747,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -9717,29 +9716,6 @@ #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */ #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */ -/****************** Bits definition for GFXMMU_HWCFGR register ****************/ -#define GFXMMU_HWCFGR_TBD_Pos (0U) -#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */ - -/****************** Bits definition for GFXMMU_VERR register ******************/ -#define GFXMMU_VERR_MINREV_Pos (0U) -#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define GFXMMU_VERR_MAJREV_Pos (4U) -#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - -/****************** Bits definition for GFXMMU_IPIDR register *****************/ -#define GFXMMU_IPIDR_ID_Pos (0U) -#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */ - -/****************** Bits definition for GFXMMU_SIDR register ******************/ -#define GFXMMU_SIDR_SID_Pos (0U) -#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */ - /****************** Bits definition for GFXMMU_LUTxL register *****************/ #define GFXMMU_LUTxL_EN_Pos (0U) #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */ @@ -19418,39 +19394,48 @@ /* OCTOSPIM */ /* */ /******************************************************************************/ + +/*************** Bit definition for OCTOSPIM_CR register ********************/ +#define OCTOSPIM_CR_MUXEN_Pos (0U) +#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */ +#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */ +#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U) +#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */ +#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */ + /*************** Bit definition for OCTOSPIM_PCR register *******************/ #define OCTOSPIM_PCR_CLKEN_Pos (0U) #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */ -#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ +#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ #define OCTOSPIM_PCR_CLKSRC_Pos (1U) #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */ -#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ +#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ #define OCTOSPIM_PCR_DQSEN_Pos (4U) #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */ -#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ +#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ #define OCTOSPIM_PCR_DQSSRC_Pos (5U) #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */ -#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ +#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ #define OCTOSPIM_PCR_NCSEN_Pos (8U) #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */ -#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ +#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ #define OCTOSPIM_PCR_NCSSRC_Pos (9U) #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */ -#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ +#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ #define OCTOSPIM_PCR_IOLEN_Pos (16U) #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */ -#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ +#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ #define OCTOSPIM_PCR_IOLSRC_Pos (17U) #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */ -#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ +#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */ #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */ #define OCTOSPIM_PCR_IOHEN_Pos (24U) #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */ -#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ +#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ #define OCTOSPIM_PCR_IOHSRC_Pos (25U) #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */ -#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ +#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */ #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */ /******************************************************************************/ @@ -20220,6 +20205,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x480UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h7b3xxq.h b/Include/stm32h7b3xxq.h index 9ce85ed..b8eccca 100644 --- a/Include/stm32h7b3xxq.h +++ b/Include/stm32h7b3xxq.h
@@ -878,11 +878,7 @@ __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ - uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ - __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ - __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ - __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ - __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ } GFXMMU_TypeDef; @@ -1894,7 +1890,7 @@ typedef struct { __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ } OCTOSPIM_TypeDef; /** @@ -6752,6 +6748,9 @@ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */ #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */ @@ -9718,29 +9717,6 @@ #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */ #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */ -/****************** Bits definition for GFXMMU_HWCFGR register ****************/ -#define GFXMMU_HWCFGR_TBD_Pos (0U) -#define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */ - -/****************** Bits definition for GFXMMU_VERR register ******************/ -#define GFXMMU_VERR_MINREV_Pos (0U) -#define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define GFXMMU_VERR_MAJREV_Pos (4U) -#define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - -/****************** Bits definition for GFXMMU_IPIDR register *****************/ -#define GFXMMU_IPIDR_ID_Pos (0U) -#define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */ - -/****************** Bits definition for GFXMMU_SIDR register ******************/ -#define GFXMMU_SIDR_SID_Pos (0U) -#define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ -#define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */ - /****************** Bits definition for GFXMMU_LUTxL register *****************/ #define GFXMMU_LUTxL_EN_Pos (0U) #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */ @@ -19430,39 +19406,48 @@ /* OCTOSPIM */ /* */ /******************************************************************************/ + +/*************** Bit definition for OCTOSPIM_CR register ********************/ +#define OCTOSPIM_CR_MUXEN_Pos (0U) +#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */ +#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk /*!< Multiplexed mode enable */ +#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U) +#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */ +#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK time */ + /*************** Bit definition for OCTOSPIM_PCR register *******************/ #define OCTOSPIM_PCR_CLKEN_Pos (0U) #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */ -#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ +#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ #define OCTOSPIM_PCR_CLKSRC_Pos (1U) #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */ -#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ +#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ #define OCTOSPIM_PCR_DQSEN_Pos (4U) #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */ -#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ +#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ #define OCTOSPIM_PCR_DQSSRC_Pos (5U) #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */ -#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ +#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ #define OCTOSPIM_PCR_NCSEN_Pos (8U) #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */ -#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ +#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ #define OCTOSPIM_PCR_NCSSRC_Pos (9U) #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */ -#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ +#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ #define OCTOSPIM_PCR_IOLEN_Pos (16U) #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */ -#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ +#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ #define OCTOSPIM_PCR_IOLSRC_Pos (17U) #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */ -#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ +#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */ #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */ #define OCTOSPIM_PCR_IOHEN_Pos (24U) #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */ -#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ +#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ #define OCTOSPIM_PCR_IOHSRC_Pos (25U) #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */ -#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ +#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */ #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */ /******************************************************************************/ @@ -20232,6 +20217,8 @@ /* DBG */ /* */ /******************************************************************************/ +/********************************* DEVICE ID ********************************/ +#define STM32H7_DEV_ID 0x480UL /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
diff --git a/Include/stm32h7xx.h b/Include/stm32h7xx.h index 0319859..67aefac 100644 --- a/Include/stm32h7xx.h +++ b/Include/stm32h7xx.h
@@ -60,7 +60,7 @@ #if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \ !defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \ - !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) + !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) /* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */ /* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */ /* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */ @@ -94,10 +94,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.7.0 + * @brief CMSIS Device version number V1.8.0 */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ @@ -167,8 +167,8 @@ typedef enum { - ERROR = 0, - SUCCESS = !ERROR + SUCCESS = 0, + ERROR = !SUCCESS } ErrorStatus; /**
diff --git a/README.md b/README.md index a6d6c25..c12e081 100644 --- a/README.md +++ b/README.md
@@ -19,14 +19,19 @@ This **cmsis_device_h7** MCU component repo is one element of the STM32CubeH7 MCU embedded software package, providing the **cmsis device** part. +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_h7/blob/master/Release_Notes.html). + ## Compatibility information In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: CMSIS Device H7 | CMSIS Core | Was delivered in the full MCU package --------------- | ---------- | ------------------------------------- -Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next new tag) -Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next new tag) +Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next CMSIS tag) +Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next CMSIS tag) +Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next CMSIS tag) The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7).
diff --git a/Release_Notes.html b/Release_Notes.html index a4f13ee..5b9b489 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -38,10 +38,32 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history"><strong>Update History</strong></h1> <div class="collapse"> -<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label> +<input type="checkbox" id="collapse-section10" checked aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label> <div> <h2 id="main-changes">Main Changes</h2> <ul> +<li>General updates to align Bits and registers definitions with the STM32H7 reference manual<br /> +</li> +<li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li> +<li>Add definition of DMA_SxCR_TRBUFF bit field of DMA SxCR register allowing to enabled/disable bufferable transfers</li> +<li>Remove RCC_AHB2ENR_CRYPEN/RCC_AHB2RSTR_CRYPRST/RCC_AHB2LPENR_CRYPLPEN and RCC_AHB2ENR_HASHEN/RCC_AHB2RSTR_HASHRST/RCC_AHB2LPENR_HASHLPEN from H7 devices that doesn’t support CRYP/HASH (STM32H742/43/45/47/A3)</li> +<li>Add STM32H7_DEV_ID define allowing to identfy the H7 Device ID</li> +<li>Update OCTOSPIM_TypeDef structure definition with 3 PCR registers instead of 8 (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li> +<li>Add definition for OCTOSPIM_CR_MUXEN and OCTOSPIM_CR_REQ2ACK_TIME in order to support OctoSPI IO Manager multiplexed mode feature (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li> +<li>Update system_stm32h7xx.c to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li> +<li>Add EWARM linker files for STM32H7A3 devices with reduced Flash size to 1MB: +<ul> +<li>stm32h7a3xg_flash.icf, stm32h7a3xg_flash_rw_sram1.icf, stm32h7a3xg_flash_rw_sram2.icf.</li> +<li>stm32h7a3xgq_flash.icf, stm32h7a3xgq_flash_rw_sram1.icf, stm32h7a3xgq_flash_rw_sram2.icf.</li> +</ul></li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<ul> <li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li> <li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: <ul> @@ -70,7 +92,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <ul> <li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li> <li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li> @@ -85,7 +107,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label> <div> -<h2 id="main-changes-2">Main Changes</h2> +<h2 id="main-changes-3">Main Changes</h2> <ul> <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li> <li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li> @@ -149,7 +171,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label> <div> -<h2 id="main-changes-3">Main Changes</h2> +<h2 id="main-changes-4">Main Changes</h2> <ul> <li><strong>Patch Release on top of V1.3.0</strong></li> <li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -162,7 +184,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <ul> <li>STM32H7xx include files: <ul> @@ -207,7 +229,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <ul> <li>Add support for stm32h750xx value line devices: <ul> @@ -220,7 +242,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <ul> <li>Update FDCAN bit definition</li> <li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li> @@ -230,7 +252,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <ul> <li>Update USB OTG bit definition</li> <li>Adjust PLL fractional computation</li> @@ -240,7 +262,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label> <div> -<h2 id="main-changes-8">Main Changes</h2> +<h2 id="main-changes-9">Main Changes</h2> <ul> <li>First official release for <strong>STM32H743xx/753xx</strong> devices</li> </ul>
diff --git a/Source/Templates/iar/linker/stm32h7a3xg_flash.icf b/Source/Templates/iar/linker/stm32h7a3xg_flash.icf new file mode 100644 index 0000000..abe80d2 --- /dev/null +++ b/Source/Templates/iar/linker/stm32h7a3xg_flash.icf
@@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_bank1_start__ = 0x08000000; +define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_bank2_start__ = 0x08100000; +define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf b/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf new file mode 100644 index 0000000..62cbc7d --- /dev/null +++ b/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf
@@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_bank1_start__ = 0x08000000; +define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_bank2_start__ = 0x08100000; +define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf b/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf new file mode 100644 index 0000000..4c440f9 --- /dev/null +++ b/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf
@@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_bank1_start__ = 0x08000000; +define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_bank2_start__ = 0x08100000; +define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x30000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf b/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf new file mode 100644 index 0000000..abe80d2 --- /dev/null +++ b/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf
@@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_bank1_start__ = 0x08000000; +define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_bank2_start__ = 0x08100000; +define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf b/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf new file mode 100644 index 0000000..62cbc7d --- /dev/null +++ b/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf
@@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_bank1_start__ = 0x08000000; +define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_bank2_start__ = 0x08100000; +define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF; + +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf b/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf new file mode 100644 index 0000000..5e6d3e2 --- /dev/null +++ b/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf
@@ -0,0 +1,35 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_bank1_start__ = 0x08000000; +define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_bank2_start__ = 0x08100000; +define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF; + + +define symbol __ICFEDIT_region_RAM_start__ = 0x30000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file
diff --git a/Source/Templates/system_stm32h7xx.c b/Source/Templates/system_stm32h7xx.c index d7ed005..641b606 100644 --- a/Source/Templates/system_stm32h7xx.c +++ b/Source/Templates/system_stm32h7xx.c
@@ -10,7 +10,7 @@ * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * - SystemCoreClock variable: Contains the core clock, it can be used * by the user application to setup the SysTick * timer or configure other parameters. * @@ -204,13 +204,25 @@ /* Disable all interrupts */ RCC->CIER = 0x00000000; +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } +#endif + #if defined (DATA_IN_D2_SRAM) - /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock ((AHB SRAM clock) */ -#if defined(RCC_AHB2ENR_D2SRAM1EN) + /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); #else RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); -#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#endif /* RCC_AHB2ENR_D2SRAM3EN */ tmpreg = RCC->AHB2ENR; (void) tmpreg; @@ -225,17 +237,10 @@ #endif /* VECT_TAB_SRAM */ #else - /* dual core CM7 or single core line */ - if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) - { - /* if stm32h7 revY*/ - /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ - *((__IO uint32_t*)0x51008108) = 0x000000001U; - } /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */ + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ #else SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif @@ -284,22 +289,24 @@ void SystemCoreClockUpdate (void) { uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; float_t fracn1, pllvco; + /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; + common_system_clock = HSE_VALUE; break; case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ @@ -336,16 +343,16 @@ break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); } else { - SystemCoreClock = 0U; + common_system_clock = 0U; } break; default: - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; } @@ -353,22 +360,28 @@ #if defined (RCC_D1CFGR_D1CPRE) tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; - /* SystemCoreClock frequency : CM7 CPU frequency */ - SystemCoreClock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; - /* SystemCoreClock frequency : CM7 CPU frequency */ - SystemCoreClock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); #endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ }
diff --git a/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c index e5b7993..69b6b5d 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c
@@ -13,7 +13,7 @@ * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * - SystemCoreClock variable: Contains the core clock, it can be used * by the user application to setup the SysTick * timer or configure other parameters. * @@ -276,6 +276,7 @@ void SystemCoreClockUpdate (void) { uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; float_t fracn1, pllvco; /* Get SYSCLK source -------------------------------------------------------*/ @@ -283,16 +284,15 @@ switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); - + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; + common_system_clock = HSE_VALUE; break; case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ @@ -329,28 +329,33 @@ break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); } else { - SystemCoreClock = 0U; + common_system_clock = 0U; } break; default: - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; } /* Compute SystemClock frequency --------------------------------------------------*/ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; - /* SystemCoreClock frequency : CM7 CPU frequency */ - SystemCoreClock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ }
diff --git a/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c index 64961d3..1f78560 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c +++ b/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c
@@ -16,7 +16,7 @@ * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * - SystemCoreClock variable: Contains the core clock, it can be used * by the user application to setup the SysTick * timer or configure other parameters. * @@ -274,6 +274,7 @@ void SystemCoreClockUpdate (void) { uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; float_t fracn1, pllvco; /* Get SYSCLK source -------------------------------------------------------*/ @@ -281,16 +282,15 @@ switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); - + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; + common_system_clock = HSE_VALUE; break; case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ @@ -327,28 +327,33 @@ break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); } else { - SystemCoreClock = 0U; + common_system_clock = 0U; } break; default: - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; } /* Compute SystemClock frequency --------------------------------------------------*/ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; - /* SystemCoreClock frequency : CM7 CPU frequency */ - SystemCoreClock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ } /**
diff --git a/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c index 987e09e..a4d65ce 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c +++ b/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c
@@ -16,7 +16,7 @@ * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * - SystemCoreClock variable: Contains the core clock, it can be used * by the user application to setup the SysTick * timer or configure other parameters. * @@ -272,6 +272,7 @@ void SystemCoreClockUpdate (void) { uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; float_t fracn1, pllvco; /* Get SYSCLK source -------------------------------------------------------*/ @@ -279,16 +280,15 @@ switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); - + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; + common_system_clock = HSE_VALUE; break; case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ @@ -325,28 +325,33 @@ break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); } else { - SystemCoreClock = 0U; + common_system_clock = 0U; } break; default: - SystemCoreClock = CSI_VALUE; + common_system_clock = CSI_VALUE; break; } /* Compute SystemClock frequency --------------------------------------------------*/ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; - /* SystemCoreClock frequency : CM7 CPU frequency */ - SystemCoreClock >>= tmp; + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ } /**
diff --git a/Source/Templates/system_stm32h7xx_singlecore.c b/Source/Templates/system_stm32h7xx_singlecore.c index d0b0ee0..b8e2af1 100644 --- a/Source/Templates/system_stm32h7xx_singlecore.c +++ b/Source/Templates/system_stm32h7xx_singlecore.c
@@ -80,7 +80,7 @@ */ /************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM */ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ /* #define DATA_IN_D2_SRAM */ /*!< Uncomment the following line if you need to relocate your vector Table in @@ -160,6 +160,7 @@ /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; +#if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; @@ -168,7 +169,16 @@ /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x00000000; @@ -197,23 +207,32 @@ /* Disable all interrupts */ RCC->CIER = 0x00000000; +#if (STM32H7_DEV_ID == 0x450UL) + /* single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; } +#endif #if defined (DATA_IN_D2_SRAM) - /* in case of initialized data in D2 SRAM , enable the D2 SRAM clock */ + /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ tmpreg = RCC->AHB2ENR; (void) tmpreg; #endif /* DATA_IN_D2_SRAM */ /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ #else SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif @@ -328,6 +347,7 @@ } /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; /* SystemCoreClock frequency : CM7 CPU frequency */ @@ -335,6 +355,13 @@ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + SystemCoreClock >>= tmp; + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif } /**