Release v2.3.2
diff --git a/Include/stm32l100xb.h b/Include/stm32l100xb.h
index 13f0d6b..9b5af5d 100644
--- a/Include/stm32l100xb.h
+++ b/Include/stm32l100xb.h
@@ -710,6 +710,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2741,6 +2750,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT1
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5167,8 +5180,6 @@
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
/**
* @brief EXTI1 configuration
@@ -5179,8 +5190,6 @@
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
/**
* @brief EXTI2 configuration
@@ -5191,8 +5200,6 @@
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
/**
* @brief EXTI3 configuration
@@ -5202,8 +5209,6 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5227,8 +5232,6 @@
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
/**
* @brief EXTI5 configuration
@@ -5238,8 +5241,6 @@
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
/**
* @brief EXTI6 configuration
@@ -5249,8 +5250,6 @@
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
/**
* @brief EXTI7 configuration
@@ -5260,8 +5259,6 @@
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
@@ -5285,8 +5282,6 @@
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
/**
* @brief EXTI9 configuration
@@ -5296,8 +5291,6 @@
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
/**
* @brief EXTI10 configuration
@@ -5307,8 +5300,6 @@
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
/**
* @brief EXTI11 configuration
@@ -5318,8 +5309,6 @@
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
@@ -5343,8 +5332,6 @@
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
/**
* @brief EXTI13 configuration
@@ -5354,8 +5341,6 @@
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
/**
* @brief EXTI14 configuration
@@ -5365,8 +5350,6 @@
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
/**
* @brief EXTI15 configuration
@@ -5376,9 +5359,7 @@
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l100xba.h b/Include/stm32l100xba.h
index 0bc4056..8f80f90 100644
--- a/Include/stm32l100xba.h
+++ b/Include/stm32l100xba.h
@@ -710,6 +710,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2744,6 +2753,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT2
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5315,8 +5328,6 @@
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
/**
* @brief EXTI1 configuration
@@ -5327,8 +5338,6 @@
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
/**
* @brief EXTI2 configuration
@@ -5339,8 +5348,6 @@
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
/**
* @brief EXTI3 configuration
@@ -5350,8 +5357,6 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5375,8 +5380,6 @@
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
/**
* @brief EXTI5 configuration
@@ -5386,8 +5389,6 @@
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
/**
* @brief EXTI6 configuration
@@ -5397,8 +5398,6 @@
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
/**
* @brief EXTI7 configuration
@@ -5408,8 +5407,6 @@
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
@@ -5433,8 +5430,6 @@
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
/**
* @brief EXTI9 configuration
@@ -5444,8 +5439,6 @@
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
/**
* @brief EXTI10 configuration
@@ -5455,8 +5448,6 @@
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
/**
* @brief EXTI11 configuration
@@ -5466,8 +5457,6 @@
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
@@ -5491,8 +5480,6 @@
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
/**
* @brief EXTI13 configuration
@@ -5502,8 +5489,6 @@
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
/**
* @brief EXTI14 configuration
@@ -5513,8 +5498,6 @@
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
/**
* @brief EXTI15 configuration
@@ -5524,9 +5507,7 @@
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l100xc.h b/Include/stm32l100xc.h
index e3f0193..f0cd00b 100644
--- a/Include/stm32l100xc.h
+++ b/Include/stm32l100xc.h
@@ -752,6 +752,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2840,6 +2849,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT3
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5523,8 +5536,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5699,7 +5712,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l151xb.h b/Include/stm32l151xb.h
index 7c93776..161dbdd 100644
--- a/Include/stm32l151xb.h
+++ b/Include/stm32l151xb.h
@@ -710,6 +710,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2742,6 +2751,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT1
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5119,8 +5132,6 @@
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
/**
* @brief EXTI1 configuration
@@ -5131,8 +5142,6 @@
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
/**
* @brief EXTI2 configuration
@@ -5143,8 +5152,6 @@
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
/**
* @brief EXTI3 configuration
@@ -5154,8 +5161,6 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5179,8 +5184,6 @@
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
/**
* @brief EXTI5 configuration
@@ -5190,8 +5193,6 @@
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
/**
* @brief EXTI6 configuration
@@ -5201,8 +5202,6 @@
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
/**
* @brief EXTI7 configuration
@@ -5212,8 +5211,6 @@
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
@@ -5237,8 +5234,6 @@
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
/**
* @brief EXTI9 configuration
@@ -5248,8 +5243,6 @@
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
/**
* @brief EXTI10 configuration
@@ -5259,8 +5252,6 @@
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
/**
* @brief EXTI11 configuration
@@ -5270,8 +5261,6 @@
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
@@ -5295,8 +5284,6 @@
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
/**
* @brief EXTI13 configuration
@@ -5306,8 +5293,6 @@
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
/**
* @brief EXTI14 configuration
@@ -5317,8 +5302,6 @@
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
/**
* @brief EXTI15 configuration
@@ -5328,9 +5311,7 @@
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l151xba.h b/Include/stm32l151xba.h
index dbb04af..69ea9c2 100644
--- a/Include/stm32l151xba.h
+++ b/Include/stm32l151xba.h
@@ -710,6 +710,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2745,6 +2754,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT2
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5195,8 +5208,6 @@
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
/**
* @brief EXTI1 configuration
@@ -5207,8 +5218,6 @@
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
/**
* @brief EXTI2 configuration
@@ -5219,8 +5228,6 @@
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
/**
* @brief EXTI3 configuration
@@ -5230,8 +5237,6 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5255,8 +5260,6 @@
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
/**
* @brief EXTI5 configuration
@@ -5266,8 +5269,6 @@
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
/**
* @brief EXTI6 configuration
@@ -5277,8 +5278,6 @@
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
/**
* @brief EXTI7 configuration
@@ -5288,8 +5287,6 @@
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
@@ -5313,8 +5310,6 @@
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
/**
* @brief EXTI9 configuration
@@ -5324,8 +5319,6 @@
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
/**
* @brief EXTI10 configuration
@@ -5335,8 +5328,6 @@
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
/**
* @brief EXTI11 configuration
@@ -5346,8 +5337,6 @@
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
@@ -5371,8 +5360,6 @@
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
/**
* @brief EXTI13 configuration
@@ -5382,8 +5369,6 @@
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
/**
* @brief EXTI14 configuration
@@ -5393,8 +5378,6 @@
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
/**
* @brief EXTI15 configuration
@@ -5404,9 +5387,7 @@
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l151xc.h b/Include/stm32l151xc.h
index 9b61674..9e04ae2 100644
--- a/Include/stm32l151xc.h
+++ b/Include/stm32l151xc.h
@@ -788,6 +788,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2985,6 +2994,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT3
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5691,8 +5704,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5867,7 +5880,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l151xca.h b/Include/stm32l151xca.h
index 8279679..b3427af 100644
--- a/Include/stm32l151xca.h
+++ b/Include/stm32l151xca.h
@@ -792,6 +792,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3028,6 +3037,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT3
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5746,8 +5759,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5922,7 +5935,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l151xd.h b/Include/stm32l151xd.h
index 1074112..f09b8e2 100644
--- a/Include/stm32l151xd.h
+++ b/Include/stm32l151xd.h
@@ -677,6 +677,7 @@
#define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */
#define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
+#define FLASH_END (0x0805FFFFUL) /*!< Program end FLASH address for Cat4 */
#define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */
@@ -865,6 +866,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3143,6 +3153,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT4
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -3335,6 +3349,12 @@
#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
#define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CPSIZE_Pos (16U)
+#define FSMC_BCRx_CPSIZE_Msk (0x7UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCRx_CPSIZE FSMC_BCRx_CPSIZE_Msk /*!< Cellular RAM page size */
+#define FSMC_BCRx_CPSIZE_0 (0x1UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCRx_CPSIZE_1 (0x2UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCRx_CPSIZE_2 (0x4UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FSMC_BCRx_CBURSTRW_Pos (19U)
#define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
@@ -6439,8 +6459,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6615,7 +6635,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l151xdx.h b/Include/stm32l151xdx.h
index f02fec7..5583b59 100644
--- a/Include/stm32l151xdx.h
+++ b/Include/stm32l151xdx.h
@@ -635,6 +635,7 @@
#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0806FFFFUL) /*!< Program end FLASH BANK2 address */
+#define FLASH_END (0x0806FFFFUL) /*!< Program end FLASH address for Cat6 */
#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */
/*!< Peripheral memory map */
@@ -808,6 +809,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3044,6 +3054,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT6
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5810,8 +5824,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5986,7 +6000,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l151xe.h b/Include/stm32l151xe.h
index 58ece57..6985398 100644
--- a/Include/stm32l151xe.h
+++ b/Include/stm32l151xe.h
@@ -635,6 +635,7 @@
#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */
+#define FLASH_END (0x0807FFFFUL) /*!< Program end FLASH address for Cat5 */
#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */
/*!< Peripheral memory map */
@@ -808,6 +809,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3044,6 +3054,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT5
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5810,8 +5824,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5986,7 +6000,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l152xb.h b/Include/stm32l152xb.h
index d6be6bd..a4cf861 100644
--- a/Include/stm32l152xb.h
+++ b/Include/stm32l152xb.h
@@ -727,6 +727,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2759,6 +2768,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT1
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5269,8 +5282,6 @@
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
/**
* @brief EXTI1 configuration
@@ -5281,8 +5292,6 @@
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
/**
* @brief EXTI2 configuration
@@ -5293,8 +5302,6 @@
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
/**
* @brief EXTI3 configuration
@@ -5304,8 +5311,6 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5329,8 +5334,6 @@
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
/**
* @brief EXTI5 configuration
@@ -5340,8 +5343,6 @@
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
/**
* @brief EXTI6 configuration
@@ -5351,8 +5352,6 @@
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
/**
* @brief EXTI7 configuration
@@ -5362,8 +5361,6 @@
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
@@ -5387,8 +5384,6 @@
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
/**
* @brief EXTI9 configuration
@@ -5398,8 +5393,6 @@
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
/**
* @brief EXTI10 configuration
@@ -5409,8 +5402,6 @@
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
/**
* @brief EXTI11 configuration
@@ -5420,8 +5411,6 @@
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
@@ -5445,8 +5434,6 @@
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
/**
* @brief EXTI13 configuration
@@ -5456,8 +5443,6 @@
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
/**
* @brief EXTI14 configuration
@@ -5467,8 +5452,6 @@
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
/**
* @brief EXTI15 configuration
@@ -5478,9 +5461,7 @@
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l152xba.h b/Include/stm32l152xba.h
index e71cc6a..12f15e1 100644
--- a/Include/stm32l152xba.h
+++ b/Include/stm32l152xba.h
@@ -712,6 +712,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2747,6 +2756,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT2
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5330,8 +5343,6 @@
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
/**
* @brief EXTI1 configuration
@@ -5342,8 +5353,6 @@
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
/**
* @brief EXTI2 configuration
@@ -5354,8 +5363,6 @@
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
/**
* @brief EXTI3 configuration
@@ -5365,8 +5372,6 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -5390,8 +5395,6 @@
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
/**
* @brief EXTI5 configuration
@@ -5401,8 +5404,6 @@
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
/**
* @brief EXTI6 configuration
@@ -5412,8 +5413,6 @@
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
/**
* @brief EXTI7 configuration
@@ -5423,8 +5422,6 @@
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
@@ -5448,8 +5445,6 @@
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
/**
* @brief EXTI9 configuration
@@ -5459,8 +5454,6 @@
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
/**
* @brief EXTI10 configuration
@@ -5470,8 +5463,6 @@
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
/**
* @brief EXTI11 configuration
@@ -5481,8 +5472,6 @@
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
@@ -5506,8 +5495,6 @@
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
/**
* @brief EXTI13 configuration
@@ -5517,8 +5504,6 @@
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
/**
* @brief EXTI14 configuration
@@ -5528,8 +5513,6 @@
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
/**
* @brief EXTI15 configuration
@@ -5539,9 +5522,7 @@
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l152xc.h b/Include/stm32l152xc.h
index 85b034a..b659ccc 100644
--- a/Include/stm32l152xc.h
+++ b/Include/stm32l152xc.h
@@ -805,6 +805,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3002,6 +3011,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT3
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5841,8 +5854,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6017,7 +6030,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l152xca.h b/Include/stm32l152xca.h
index 4b1c460..701532d 100644
--- a/Include/stm32l152xca.h
+++ b/Include/stm32l152xca.h
@@ -809,6 +809,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3045,6 +3054,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT3
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5896,8 +5909,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6072,7 +6085,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l152xd.h b/Include/stm32l152xd.h
index 4ab18c4..bb0ad24 100644
--- a/Include/stm32l152xd.h
+++ b/Include/stm32l152xd.h
@@ -692,6 +692,7 @@
#define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */
#define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
+#define FLASH_END (0x0805FFFFUL) /*!< Program end FLASH address for Cat4 */
#define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */
@@ -882,6 +883,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3160,6 +3170,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT4
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -3352,6 +3366,12 @@
#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
#define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CPSIZE_Pos (16U)
+#define FSMC_BCRx_CPSIZE_Msk (0x7UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCRx_CPSIZE FSMC_BCRx_CPSIZE_Msk /*!< Cellular RAM page size */
+#define FSMC_BCRx_CPSIZE_0 (0x1UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCRx_CPSIZE_1 (0x2UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCRx_CPSIZE_2 (0x4UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FSMC_BCRx_CBURSTRW_Pos (19U)
#define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
@@ -6589,8 +6609,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6765,7 +6785,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l152xdx.h b/Include/stm32l152xdx.h
index 56ad742..1eaf3af 100644
--- a/Include/stm32l152xdx.h
+++ b/Include/stm32l152xdx.h
@@ -650,6 +650,7 @@
#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0806FFFFUL) /*!< Program end FLASH BANK2 address */
+#define FLASH_END (0x0806FFFFUL) /*!< Program end FLASH address for Cat6 */
#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */
/*!< Peripheral memory map */
@@ -825,6 +826,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3061,6 +3071,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT6
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5960,8 +5974,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6136,7 +6150,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l152xe.h b/Include/stm32l152xe.h
index 89f2e37..9589a79 100644
--- a/Include/stm32l152xe.h
+++ b/Include/stm32l152xe.h
@@ -650,6 +650,7 @@
#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */
+#define FLASH_END (0x0807FFFFUL) /*!< Program end FLASH address for Cat5 */
#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */
/*!< Peripheral memory map */
@@ -825,6 +826,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3061,6 +3071,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT5
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5960,8 +5974,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6136,7 +6150,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l162xc.h b/Include/stm32l162xc.h
index 524562b..7ae05e8 100644
--- a/Include/stm32l162xc.h
+++ b/Include/stm32l162xc.h
@@ -828,6 +828,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3132,6 +3141,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT3
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -5980,8 +5993,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6156,7 +6169,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l162xca.h b/Include/stm32l162xca.h
index 9126134..3944173 100644
--- a/Include/stm32l162xca.h
+++ b/Include/stm32l162xca.h
@@ -832,6 +832,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3175,6 +3184,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT3
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -6035,8 +6048,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6211,7 +6224,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l162xd.h b/Include/stm32l162xd.h
index 51c2fed..f86f329 100644
--- a/Include/stm32l162xd.h
+++ b/Include/stm32l162xd.h
@@ -713,6 +713,7 @@
#define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */
#define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
+#define FLASH_END (0x0805FFFFUL) /*!< Program end FLASH address for Cat4 */
#define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */
@@ -905,6 +906,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3290,6 +3300,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT4
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -3482,6 +3496,12 @@
#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
#define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CPSIZE_Pos (16U)
+#define FSMC_BCRx_CPSIZE_Msk (0x7UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
+#define FSMC_BCRx_CPSIZE FSMC_BCRx_CPSIZE_Msk /*!< Cellular RAM page size */
+#define FSMC_BCRx_CPSIZE_0 (0x1UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
+#define FSMC_BCRx_CPSIZE_1 (0x2UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
+#define FSMC_BCRx_CPSIZE_2 (0x4UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FSMC_BCRx_CBURSTRW_Pos (19U)
#define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
@@ -6728,8 +6748,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6904,7 +6924,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l162xdx.h b/Include/stm32l162xdx.h
index 0ec12e8..eda15e0 100644
--- a/Include/stm32l162xdx.h
+++ b/Include/stm32l162xdx.h
@@ -671,6 +671,7 @@
#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0806FFFFUL) /*!< Program end FLASH BANK2 address */
+#define FLASH_END (0x0806FFFFUL) /*!< Program end FLASH address for Cat6 */
#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */
/*!< Peripheral memory map */
@@ -848,6 +849,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3191,6 +3201,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT6
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -6099,8 +6113,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6275,7 +6289,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l162xe.h b/Include/stm32l162xe.h
index 95f56e1..689cfce 100644
--- a/Include/stm32l162xe.h
+++ b/Include/stm32l162xe.h
@@ -671,6 +671,7 @@
#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */
+#define FLASH_END (0x0807FFFFUL) /*!< Program end FLASH address for Cat5 */
#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */
/*!< Peripheral memory map */
@@ -848,6 +849,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -3191,6 +3201,10 @@
/* (FLASH, DATA_EEPROM, OB) */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
+ */
+#define FLASH_CUT5
/******************* Bit definition for FLASH_ACR register ******************/
#define FLASH_ACR_LATENCY_Pos (0U)
@@ -6099,8 +6113,8 @@
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
@@ -6275,7 +6289,7 @@
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
-
+
/******************************************************************************/
/* */
/* Routing Interface (RI) */
diff --git a/Include/stm32l1xx.h b/Include/stm32l1xx.h
index 4db5261..b4f7889 100644
--- a/Include/stm32l1xx.h
+++ b/Include/stm32l1xx.h
@@ -70,19 +70,19 @@
/* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
/* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
/* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
- /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */
+ /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */
/* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
/* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
/* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
/* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
/* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
/* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */
- /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */
+ /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */
/* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
/* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */
/* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
/* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
- /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */
+ /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */
/* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
#endif
@@ -100,11 +100,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.1
+ * @brief CMSIS Device version number V2.3.2
*/
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
@@ -215,6 +215,61 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
diff --git a/README.md b/README.md
index 9d7c7e1..da8a0a4 100644
--- a/README.md
+++ b/README.md
@@ -31,6 +31,7 @@
--------------- | ---------- | -------------------------------------
Tag v2.3.0 | Tag v5.4.0_cm3 | Tag v1.9.0 (and following, if any, till next new tag)
Tag v2.3.1 | Tag v5.4.0_cm3 | Tag v1.10.0 (and following, if any, till next new tag)
+Tag v2.3.2 | Tag v5.4.0_cm3 | Tag v1.10.0 (and following, if any, till next new tag)
The full **STM32CubeL1** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL1).
diff --git a/Release_Notes.html b/Release_Notes.html
index f095a8f..97c7930 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -29,9 +29,6 @@
</center>
</div>
</div>
-<h1 id="license">License</h1>
-<p>Licensed by ST under Apache-2.0 license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
-<p><a href="../../../LICENSE.txt">Apache License v2.0</a></p>
<h1 id="purpose">Purpose</h1>
<p>This driver provides the CMSIS device for the stm32l1xx products. This covers:</p>
<ul>
@@ -51,12 +48,29 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.3.1 / 24-June-2020</label>
+<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V2.3.2 / 21-May-2021</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<h2 id="contents">Contents</h2>
<ul>
+<li>Improve GCC startup files robustness.</li>
+<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
+<li>Add atomic register access macros.</li>
+<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li>
+<li>Remove bit definition related to PF and PG ports from unsupported devices (L1xxxB devices).</li>
+<li>Fix SYSCFG_EXTICR1_EXTI3_PF and SYSCFG_EXTICR1_EXTI3_PG defines values.</li>
+<li>Update the hal_flash.h file to correctly support the FLASH_SIZE of cat.2 devices.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.3.1 / 24-June-2020</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-1">Maintenance release</h3>
+<h2 id="contents-1">Contents</h2>
+<ul>
<li>All header files
<ul>
<li>Remove NVIC CMSIS bits definitions to avoid duplication with CMSIS Core V5.x</li>
@@ -80,9 +94,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V2.3.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance release</h3>
-<h2 id="contents-1">Contents</h2>
+<h2 id="main-changes-2">Main Changes</h2>
+<h3 id="maintenance-release-2">Maintenance release</h3>
+<h2 id="contents-2">Contents</h2>
<ul>
<li>stm32l0xx.h
<ul>
@@ -109,9 +123,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V2.2.3 / 12-January-2018</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<h3 id="patch-release">Patch release</h3>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<ul>
<li>Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.</li>
</ul>
@@ -120,9 +134,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V2.2.2 / 25-August-2017</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance release</h3>
-<h2 id="contents-3">Contents</h2>
+<h2 id="main-changes-4">Main Changes</h2>
+<h3 id="maintenance-release-3">Maintenance release</h3>
+<h2 id="contents-4">Contents</h2>
<ul>
<li>Removed DATE and VERSION fields from header files.</li>
</ul>
@@ -131,9 +145,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V2.2.1 / 21-April-2017</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance release</h3>
-<h2 id="contents-4">Contents</h2>
+<h2 id="main-changes-5">Main Changes</h2>
+<h3 id="maintenance-release-4">Maintenance release</h3>
+<h2 id="contents-5">Contents</h2>
<ul>
<li>Update CMSIS Devices compliancy with MISRA C 2004 rules:
<ul>
@@ -149,9 +163,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V2.2.0 / 01-July-2016</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
-<h3 id="maintenance-release-4">Maintenance release</h3>
-<h2 id="contents-5">Contents</h2>
+<h2 id="main-changes-6">Main Changes</h2>
+<h3 id="maintenance-release-5">Maintenance release</h3>
+<h2 id="contents-6">Contents</h2>
<ul>
<li>Add macros _Pos and _Msk for each constants.
<ul>
@@ -179,9 +193,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V2.1.3 / 04-March-2016</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
-<h3 id="maintenance-release-5">Maintenance release</h3>
-<h2 id="contents-6">Contents</h2>
+<h2 id="main-changes-7">Main Changes</h2>
+<h3 id="maintenance-release-6">Maintenance release</h3>
+<h2 id="contents-7">Contents</h2>
<ul>
<li>Add HardFault_IRQn.</li>
<li>Add BKP5R to BKP19R for RTC_TypeDef for stm32l151xba.</li>
@@ -218,9 +232,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V2.1.2 / 09-October-2015</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
-<h3 id="maintenance-release-6">Maintenance release</h3>
-<h2 id="contents-7">Contents</h2>
+<h2 id="main-changes-8">Main Changes</h2>
+<h3 id="maintenance-release-7">Maintenance release</h3>
+<h2 id="contents-8">Contents</h2>
<ul>
<li>Removing the __IO attribute for PLLMulTable and AHBPrescTable. This was leading to issue during C++ initialisation.</li>
<li>IDR field of CRC_TypeDef changed from uint32_t to uint8_t to comply with register structure.</li>
@@ -233,9 +247,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V2.1.1 / 31-March-2015</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
-<h3 id="maintenance-release-7">Maintenance release</h3>
-<h2 id="contents-8">Contents</h2>
+<h2 id="main-changes-9">Main Changes</h2>
+<h3 id="maintenance-release-8">Maintenance release</h3>
+<h2 id="contents-9">Contents</h2>
<ul>
<li>Ensure compliancy w/ C++</li>
<li>Minor update on Timer assert.</li>
@@ -246,9 +260,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V2.1.0 / 06-February-2015</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
-<h3 id="maintenance-release-8">Maintenance release</h3>
-<h2 id="contents-9">Contents</h2>
+<h2 id="main-changes-10">Main Changes</h2>
+<h3 id="maintenance-release-9">Maintenance release</h3>
+<h2 id="contents-10">Contents</h2>
<ul>
<li>Add CMSIS files for new STM32L1 e<strong>X</strong>tended Devices : <strong>STM32L151xDX, STM32L152xDX and STM32L162xDX</strong></li>
</ul>
@@ -257,9 +271,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V2.0.0 / 05-September-2014</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
-<h3 id="maintenance-release-9">Maintenance release</h3>
-<h2 id="contents-10">Contents</h2>
+<h2 id="main-changes-11">Main Changes</h2>
+<h3 id="maintenance-release-10">Maintenance release</h3>
+<h2 id="contents-11">Contents</h2>
<ul>
<li>Update based on STM32Cube specification</li>
</ul>
diff --git a/Source/Templates/gcc/startup_stm32l100xb.s b/Source/Templates/gcc/startup_stm32l100xb.s
index 87b4d67..3e93a42 100644
--- a/Source/Templates/gcc/startup_stm32l100xb.s
+++ b/Source/Templates/gcc/startup_stm32l100xb.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l100xba.s b/Source/Templates/gcc/startup_stm32l100xba.s
index 5b94999..bba696e 100644
--- a/Source/Templates/gcc/startup_stm32l100xba.s
+++ b/Source/Templates/gcc/startup_stm32l100xba.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l100xc.s b/Source/Templates/gcc/startup_stm32l100xc.s
index a55982c..82fdaaf 100644
--- a/Source/Templates/gcc/startup_stm32l100xc.s
+++ b/Source/Templates/gcc/startup_stm32l100xc.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l151xb.s b/Source/Templates/gcc/startup_stm32l151xb.s
index 6c3b5bd..e6671c4 100644
--- a/Source/Templates/gcc/startup_stm32l151xb.s
+++ b/Source/Templates/gcc/startup_stm32l151xb.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l151xba.s b/Source/Templates/gcc/startup_stm32l151xba.s
index d6c0e0f..2610867 100644
--- a/Source/Templates/gcc/startup_stm32l151xba.s
+++ b/Source/Templates/gcc/startup_stm32l151xba.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l151xc.s b/Source/Templates/gcc/startup_stm32l151xc.s
index 4facad4..3f14248 100644
--- a/Source/Templates/gcc/startup_stm32l151xc.s
+++ b/Source/Templates/gcc/startup_stm32l151xc.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l151xca.s b/Source/Templates/gcc/startup_stm32l151xca.s
index d741421..81da7a7 100644
--- a/Source/Templates/gcc/startup_stm32l151xca.s
+++ b/Source/Templates/gcc/startup_stm32l151xca.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l151xd.s b/Source/Templates/gcc/startup_stm32l151xd.s
index eace310..fb105c7 100644
--- a/Source/Templates/gcc/startup_stm32l151xd.s
+++ b/Source/Templates/gcc/startup_stm32l151xd.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l151xdx.s b/Source/Templates/gcc/startup_stm32l151xdx.s
index 0c6f575..58c9ddf 100644
--- a/Source/Templates/gcc/startup_stm32l151xdx.s
+++ b/Source/Templates/gcc/startup_stm32l151xdx.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l151xe.s b/Source/Templates/gcc/startup_stm32l151xe.s
index 653c27e..cb7ca7f 100644
--- a/Source/Templates/gcc/startup_stm32l151xe.s
+++ b/Source/Templates/gcc/startup_stm32l151xe.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l152xb.s b/Source/Templates/gcc/startup_stm32l152xb.s
index fd17704..75d70aa 100644
--- a/Source/Templates/gcc/startup_stm32l152xb.s
+++ b/Source/Templates/gcc/startup_stm32l152xb.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l152xba.s b/Source/Templates/gcc/startup_stm32l152xba.s
index 22ec7cf..e9636b5 100644
--- a/Source/Templates/gcc/startup_stm32l152xba.s
+++ b/Source/Templates/gcc/startup_stm32l152xba.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l152xc.s b/Source/Templates/gcc/startup_stm32l152xc.s
index d07e510..9ff967a 100644
--- a/Source/Templates/gcc/startup_stm32l152xc.s
+++ b/Source/Templates/gcc/startup_stm32l152xc.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l152xca.s b/Source/Templates/gcc/startup_stm32l152xca.s
index 13d7c1a..49f8c29 100644
--- a/Source/Templates/gcc/startup_stm32l152xca.s
+++ b/Source/Templates/gcc/startup_stm32l152xca.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l152xd.s b/Source/Templates/gcc/startup_stm32l152xd.s
index 155b61f..5ec40ed 100644
--- a/Source/Templates/gcc/startup_stm32l152xd.s
+++ b/Source/Templates/gcc/startup_stm32l152xd.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l152xdx.s b/Source/Templates/gcc/startup_stm32l152xdx.s
index 68aed35..ab001d6 100644
--- a/Source/Templates/gcc/startup_stm32l152xdx.s
+++ b/Source/Templates/gcc/startup_stm32l152xdx.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l152xe.s b/Source/Templates/gcc/startup_stm32l152xe.s
index 39307f4..6b9b75a 100644
--- a/Source/Templates/gcc/startup_stm32l152xe.s
+++ b/Source/Templates/gcc/startup_stm32l152xe.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l162xc.s b/Source/Templates/gcc/startup_stm32l162xc.s
index 1fb4d4c..aabd5d3 100644
--- a/Source/Templates/gcc/startup_stm32l162xc.s
+++ b/Source/Templates/gcc/startup_stm32l162xc.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l162xca.s b/Source/Templates/gcc/startup_stm32l162xca.s
index 8a205a5..8013eab 100644
--- a/Source/Templates/gcc/startup_stm32l162xca.s
+++ b/Source/Templates/gcc/startup_stm32l162xca.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l162xd.s b/Source/Templates/gcc/startup_stm32l162xd.s
index 1e2a2cd..ef8188b 100644
--- a/Source/Templates/gcc/startup_stm32l162xd.s
+++ b/Source/Templates/gcc/startup_stm32l162xd.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l162xdx.s b/Source/Templates/gcc/startup_stm32l162xdx.s
index 378b4d7..47e0939 100644
--- a/Source/Templates/gcc/startup_stm32l162xdx.s
+++ b/Source/Templates/gcc/startup_stm32l162xdx.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/gcc/startup_stm32l162xe.s b/Source/Templates/gcc/startup_stm32l162xe.s
index b869ba9..72ad12f 100644
--- a/Source/Templates/gcc/startup_stm32l162xe.s
+++ b/Source/Templates/gcc/startup_stm32l162xe.s
@@ -62,31 +62,34 @@
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
+ adds r4, r0, r3
+ cmp r4, r1
bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+
/* Zero fill the bss segment. */
-FillZerobss:
+ ldr r2, =_sbss
+ ldr r4, =_ebss
movs r3, #0
- str r3, [r2], #4
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
+ cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
diff --git a/Source/Templates/system_stm32l1xx.c b/Source/Templates/system_stm32l1xx.c
index c3d397d..42f02a1 100644
--- a/Source/Templates/system_stm32l1xx.c
+++ b/Source/Templates/system_stm32l1xx.c
@@ -75,11 +75,31 @@
on STM32L152D_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
/**
* @}
*/
@@ -143,11 +163,10 @@
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#endif /* USER_VECT_TAB_ADDRESS */
}
/**
diff --git a/md2html.sh b/md2html.sh
deleted file mode 100644
index b996e7a..0000000
--- a/md2html.sh
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/bash
-
-# How to use Pandoc
-# To convert your existing HTML release notes into Markdown (useful to build your history), type the following command in your bash window:
- # pandoc --from html --to markdown Release_Notes.html > Release_Notes.md
-# To convert a .md file into an HTML one, type the following command in your bash window:
- # pandoc -s -r markdown -t html5 -c "_htmresc/mini-st.css" Release_Notes.md > Release_Notes.html
-
-pandoc -s -r markdown -t html5 -c "_htmresc/mini-st.css" Release_Notes.md > Release_Notes.html
-
-read -n1 -r -p "Press any key to continue..." key
