Release v11.2.0_20250620
diff --git a/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Source/CMSIS_RTOS_V2/cmsis_os2.c
index 85d90fd..5469c12 100644
--- a/Source/CMSIS_RTOS_V2/cmsis_os2.c
+++ b/Source/CMSIS_RTOS_V2/cmsis_os2.c
@@ -1,5 +1,5 @@
/* --------------------------------------------------------------------------
- * Copyright (c) 2013-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -19,6 +19,7 @@
* Purpose: CMSIS RTOS2 wrapper for FreeRTOS
*
*---------------------------------------------------------------------------*/
+
#include <string.h>
#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core
@@ -175,24 +176,6 @@
#endif
#endif /* SysTick */
-/*
- Setup SVC to reset value.
-*/
-__STATIC_INLINE void SVC_Setup (void) {
-#if (__ARM_ARCH_7A__ == 0U)
- /* Service Call interrupt might be configured before kernel start */
- /* and when its priority is lower or equal to BASEPRI, svc instruction */
- /* causes a Hard Fault. */
- NVIC_SetPriority (SVCall_IRQn, 0U);
-#endif
-}
-
-/*
- Function macro used to retrieve semaphore count from ISR
-*/
-#ifndef uxSemaphoreGetCountFromISR
-#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )
-#endif
/*
Determine if CPU executes from interrupt context or if interrupts are masked.
@@ -362,8 +345,6 @@
/* Start scheduler if initialized and not started before */
if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelReady)) {
- /* Ensure SVC priority is at the reset value */
- SVC_Setup();
/* Change state to ensure correct API flow */
KernelState = osKernelRunning;
/* Start the kernel scheduler */
@@ -390,6 +371,8 @@
else {
switch (xTaskGetSchedulerState()) {
case taskSCHEDULER_SUSPENDED:
+ /* Suspend scheduler or increment nesting level */
+ vTaskSuspendAll();
lock = 1;
break;
@@ -422,12 +405,8 @@
switch (xTaskGetSchedulerState()) {
case taskSCHEDULER_SUSPENDED:
lock = 1;
-
- if (xTaskResumeAll() != pdTRUE) {
- if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) {
- lock = (int32_t)osError;
- }
- }
+ /* Resume scheduler or decrement nesting level */
+ (void)xTaskResumeAll();
break;
case taskSCHEDULER_RUNNING:
@@ -456,21 +435,26 @@
else {
switch (xTaskGetSchedulerState()) {
case taskSCHEDULER_SUSPENDED:
+ if (lock == 0) {
+ /* Resume scheduler or decrement nesting level */
+ (void)xTaskResumeAll();
+ }
+ else {
+ if (lock != 1) {
+ lock = (int32_t)osError;
+ }
+ }
+ break;
+
case taskSCHEDULER_RUNNING:
if (lock == 1) {
+ /* Suspend scheduler or increment nesting level */
vTaskSuspendAll();
}
else {
if (lock != 0) {
lock = (int32_t)osError;
}
- else {
- if (xTaskResumeAll() != pdTRUE) {
- if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) {
- lock = (int32_t)osError;
- }
- }
- }
}
break;
@@ -528,7 +512,9 @@
val0 = OS_Tick_GetCount();
#endif
- __disable_irq();
+ if (irqmask == 0U) {
+ __disable_irq();
+ }
ticks = xTaskGetTickCount();
val = OS_Tick_GetCount();
@@ -580,6 +566,9 @@
TaskHandle_t hTask;
UBaseType_t prio;
int32_t mem;
+#if (configUSE_OS2_CPU_AFFINITY == 1)
+ UBaseType_t core_aff = tskNO_AFFINITY;
+#endif
hTask = NULL;
@@ -620,6 +609,12 @@
mem = 0;
}
}
+
+ #if (configUSE_OS2_CPU_AFFINITY == 1)
+ if (attr->affinity_mask != 0U) {
+ core_aff = attr->affinity_mask;
+ }
+ #endif
}
else {
mem = 0;
@@ -627,16 +622,49 @@
if (mem == 1) {
#if (configSUPPORT_STATIC_ALLOCATION == 1)
- hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
- (StaticTask_t *)attr->cb_mem);
+ #if (configUSE_OS2_CPU_AFFINITY == 0)
+ hTask = xTaskCreateStatic ((TaskFunction_t)func,
+ name,
+ stack,
+ argument,
+ prio - 1U,
+ (StackType_t *)attr->stack_mem,
+ (StaticTask_t *)attr->cb_mem);
+ #else
+ hTask = xTaskCreateStaticAffinitySet ((TaskFunction_t)func,
+ name,
+ stack,
+ argument,
+ prio - 1U,
+ (StackType_t *)attr->stack_mem,
+ (StaticTask_t *)attr->cb_mem,
+ core_aff);
+ #endif
#endif
}
else {
if (mem == 0) {
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
- if (xTaskCreate ((TaskFunction_t)func, name, (configSTACK_DEPTH_TYPE)stack, argument, prio, &hTask) != pdPASS) {
- hTask = NULL;
- }
+ #if (configUSE_OS2_CPU_AFFINITY == 0)
+ if (xTaskCreate ((TaskFunction_t )func,
+ name,
+ (configSTACK_DEPTH_TYPE)stack,
+ argument,
+ prio - 1U,
+ &hTask) != pdPASS) {
+ hTask = NULL;
+ }
+ #else
+ if (xTaskCreateAffinitySet ((TaskFunction_t )func,
+ name,
+ (configSTACK_DEPTH_TYPE)stack,
+ argument,
+ prio - 1U,
+ core_aff,
+ &hTask) != pdPASS) {
+ hTask = NULL;
+ }
+ #endif
#endif
}
}
@@ -653,9 +681,15 @@
TaskHandle_t hTask = (TaskHandle_t)thread_id;
const char *name;
- if ((IRQ_Context() != 0U) || (hTask == NULL)) {
+ if (hTask == NULL) {
name = NULL;
- } else {
+ }
+ else if (IRQ_Context() != 0U) {
+ /* Retrieve the name even though the function is not allowed to be called from ISR */
+ /* Function implementation allows this therefore we make an exception. */
+ name = pcTaskGetName (hTask);
+ }
+ else {
name = pcTaskGetName (hTask);
}
@@ -733,7 +767,7 @@
}
else {
stat = osOK;
- vTaskPrioritySet (hTask, (UBaseType_t)priority);
+ vTaskPrioritySet (hTask, (UBaseType_t)priority - 1U);
}
/* Return execution status */
@@ -750,7 +784,7 @@
if ((IRQ_Context() != 0U) || (hTask == NULL)) {
prio = osPriorityError;
} else {
- prio = (osPriority_t)((int32_t)uxTaskPriorityGet (hTask));
+ prio = (osPriority_t)(uxTaskPriorityGet (hTask) + 1U);
}
/* Return current thread priority */
@@ -803,6 +837,7 @@
osStatus_t osThreadResume (osThreadId_t thread_id) {
TaskHandle_t hTask = (TaskHandle_t)thread_id;
osStatus_t stat;
+ eTaskState tstate;
if (IRQ_Context() != 0U) {
stat = osErrorISR;
@@ -811,8 +846,22 @@
stat = osErrorParameter;
}
else {
- stat = osOK;
- vTaskResume (hTask);
+ tstate = eTaskGetState (hTask);
+
+ if (tstate == eSuspended) {
+ /* Thread is suspended */
+ stat = osOK;
+ vTaskResume (hTask);
+ } else {
+ /* Not suspended, might be blocked */
+ if (xTaskAbortDelay(hTask) == pdPASS) {
+ /* Thread was unblocked */
+ stat = osOK;
+ } else {
+ /* Thread was not blocked */
+ stat = osErrorResource;
+ }
+ }
}
/* Return execution status */
@@ -916,6 +965,50 @@
}
#endif /* (configUSE_OS2_THREAD_ENUMERATE == 1) */
+#if (configUSE_OS2_CPU_AFFINITY == 1)
+/*
+ Set processor affinity mask of a thread.
+*/
+osStatus_t osThreadSetAffinityMask (osThreadId_t thread_id, uint32_t affinity_mask) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ osStatus_t stat;
+
+ if (IRQ_Context() != 0U) {
+ stat = osErrorISR;
+ }
+ else if (hTask == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ stat = osOK;
+ vTaskCoreAffinitySet (hTask, (UBaseType_t)affinity_mask);
+ }
+
+ /* Return execution status */
+ return (stat);
+}
+
+/*
+ Get current processor affinity mask of a thread.
+*/
+uint32_t osThreadGetAffinityMask (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ UBaseType_t affinity_mask;
+
+ if (IRQ_Context() != 0U) {
+ affinity_mask = 0U;
+ }
+ else if (hTask == NULL) {
+ affinity_mask = 0U;
+ }
+ else {
+ affinity_mask = vTaskCoreAffinityGet (hTask);
+ }
+
+ /* Return current processor affinity mask */
+ return ((uint32_t)affinity_mask);
+}
+#endif /* (configUSE_OS2_CPU_AFFINITY == 1) */
/* ==== Thread Flags Functions ==== */
@@ -1010,10 +1103,12 @@
Wait for one or more Thread Flags of the current running thread to become signaled.
*/
uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
+ TaskHandle_t hTask;
uint32_t rflags, nval;
uint32_t clear;
TickType_t t0, td, tout;
BaseType_t rval;
+ BaseType_t notify = pdFALSE;
if (IRQ_Context() != 0U) {
rflags = (uint32_t)osErrorISR;
@@ -1039,6 +1134,11 @@
rflags &= flags;
rflags |= nval;
+ if ((rflags & ~flags) != 0) {
+ /* Other flags already set, notify task to change its state */
+ notify = pdTRUE;
+ }
+
if ((options & osFlagsWaitAll) == osFlagsWaitAll) {
if ((flags & rflags) == flags) {
break;
@@ -1080,6 +1180,15 @@
while (rval != pdFAIL);
}
+ if (notify == pdTRUE) {
+ hTask = xTaskGetCurrentTaskHandle();
+
+ /* Ensure task is already notified without changing existing flags */
+ if (xTaskNotify(hTask, 0, eNoAction) != pdPASS) {
+ rflags = (uint32_t)osError;
+ }
+ }
+
/* Return flags before clearing */
return (rflags);
}
@@ -1276,9 +1385,15 @@
TimerHandle_t hTimer = (TimerHandle_t)timer_id;
const char *p;
- if ((IRQ_Context() != 0U) || (hTimer == NULL)) {
+ if (hTimer == NULL) {
p = NULL;
- } else {
+ }
+ else if (IRQ_Context() != 0U) {
+ /* Retrieve the name even though the function is not allowed to be called from ISR */
+ /* Function implementation allows this therefore we make an exception. */
+ p = pcTimerGetName (hTimer);
+ }
+ else {
p = pcTimerGetName (hTimer);
}
@@ -1948,7 +2063,7 @@
#endif
}
}
-
+
#if (configQUEUE_REGISTRY_SIZE > 0)
if (hSemaphore != NULL) {
if ((attr != NULL) && (attr->name != NULL)) {
@@ -2252,14 +2367,13 @@
Get maximum number of messages in a Message Queue.
*/
uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
- StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
uint32_t capacity;
- if (mq == NULL) {
+ if (hQueue == NULL) {
capacity = 0U;
} else {
- /* capacity = pxQueue->uxLength */
- capacity = mq->uxDummy4[1];
+ capacity = uxQueueGetQueueLength (hQueue);
}
/* Return maximum number of messages */
@@ -2270,14 +2384,13 @@
Get maximum message size in a Message Queue.
*/
uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
- StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
uint32_t size;
- if (mq == NULL) {
+ if (hQueue == NULL) {
size = 0U;
} else {
- /* size = pxQueue->uxItemSize */
- size = mq->uxDummy4[2];
+ size = uxQueueGetQueueItemSize (hQueue);
}
/* Return maximum message size */
@@ -2309,23 +2422,22 @@
Get number of available slots for messages in a Message Queue.
*/
uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {
- StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
uint32_t space;
uint32_t isrm;
- if (mq == NULL) {
+ if (hQueue == NULL) {
space = 0U;
}
else if (IRQ_Context() != 0U) {
isrm = taskENTER_CRITICAL_FROM_ISR();
- /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */
- space = mq->uxDummy4[1] - mq->uxDummy4[0];
+ space = uxQueueGetQueueLength (hQueue) - uxQueueMessagesWaiting (hQueue);
taskEXIT_CRITICAL_FROM_ISR(isrm);
}
else {
- space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq);
+ space = (uint32_t)uxQueueSpacesAvailable (hQueue);
}
/* Return number of available slots */
@@ -2521,11 +2633,11 @@
MemPool_t *mp = (osMemoryPoolId_t)mp_id;
const char *p;
- if (IRQ_Context() != 0U) {
+ if (mp_id == NULL) {
p = NULL;
}
- else if (mp_id == NULL) {
- p = NULL;
+ else if (IRQ_Context() != 0U) {
+ p = mp->name;
}
else {
p = mp->name;
@@ -2924,34 +3036,3 @@
configASSERT(0);
}
#endif
-
-/*---------------------------------------------------------------------------*/
-#if (configSUPPORT_STATIC_ALLOCATION == 1)
-/*
- vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
- equals to 1 and is required for static memory allocation support.
-*/
-__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
- /* Idle task control block and stack */
- static StaticTask_t Idle_TCB;
- static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
-
- *ppxIdleTaskTCBBuffer = &Idle_TCB;
- *ppxIdleTaskStackBuffer = &Idle_Stack[0];
- *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
-}
-
-/*
- vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
- equals to 1 and is required for static memory allocation support.
-*/
-__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
- /* Timer task control block and stack */
- static StaticTask_t Timer_TCB;
- static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
-
- *ppxTimerTaskTCBBuffer = &Timer_TCB;
- *ppxTimerTaskStackBuffer = &Timer_Stack[0];
- *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
-}
-#endif
diff --git a/Source/CMSIS_RTOS_V2/freertos_os2.h b/Source/CMSIS_RTOS_V2/freertos_os2.h
index ddb4aa1..af83da9 100644
--- a/Source/CMSIS_RTOS_V2/freertos_os2.h
+++ b/Source/CMSIS_RTOS_V2/freertos_os2.h
@@ -1,5 +1,5 @@
/* --------------------------------------------------------------------------
- * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -30,7 +30,7 @@
#include CMSIS_device_header
- /*
+/*
CMSIS-RTOS2 FreeRTOS image size optimization definitions.
Note: Definitions configUSE_OS2 can be used to optimize FreeRTOS image size when
@@ -84,6 +84,12 @@
#define configUSE_OS2_MUTEX configUSE_MUTEXES
#endif
+/*
+ Option to exclude CMSIS-RTOS2 Processor Affinity API functions from the application image.
+*/
+#ifndef configUSE_OS2_CPU_AFFINITY
+#define configUSE_OS2_CPU_AFFINITY configUSE_CORE_AFFINITY
+#endif
/*
CMSIS-RTOS2 FreeRTOS configuration check (FreeRTOSConfig.h).
@@ -241,6 +247,26 @@
#endif
#endif
+#if (configUSE_CORE_AFFINITY == 0)
+ /*
+ CMSIS-RTOS2 Processor Affinity API functions require FreeRTOS kernel support for
+ Symmetric Multiprocessing (SMP). In case if this functionality is not available
+ and the functions are not used in the application image, compiler will optimize
+ them away.
+ Set #define configUSE_CORE_AFFINITY 1 to fix this error.
+ Note: SMP is only available when #define configNUMBER_OF_CORES > 1
+
+ Alternatively, if the application does not use processor affinity functions they
+ can be excluded from the image code by setting:
+ #define configUSE_OS2_CPU_AFFINITY 0 (in FreeRTOSConfig.h)
+ */
+
+ #if (configUSE_OS2_CPU_AFFINITY == 1)
+ #error "Definitions configNUMBER_OF_CORES and configUSE_CORE_AFFINITY must equal 1 to implement Processor Affinity API."
+ #endif
+#endif
+
+
#if (configUSE_COUNTING_SEMAPHORES == 0)
/*
CMSIS-RTOS2 Memory Pool functions use FreeRTOS function xSemaphoreCreateCounting
diff --git a/Source/History.txt b/Source/History.txt
index 87e7952..7df76e1 100644
--- a/Source/History.txt
+++ b/Source/History.txt
@@ -1,5 +1,309 @@
Documentation and download available at https://www.FreeRTOS.org/
+Changes between FreeRTOS V11.1.0 and FreeRTOS V11.2.0 released March 04, 2025
+
+ + Add CC-RH port for Renesas F1Kx devices. We thank @TrongNguyenR for their
+ contribution.
+ + Add Pointer Authentication (PAC) and Branch Target Identification (BTI)
+ support to the ARMv8-M ports. We thank @AhmedIsmail02 for their
+ contribution.
+ + Add Floating Point Unit (FPU) support to the ARM_AARCH64 port. We thank
+ @StefanBalt for their contribution.
+ + Add FPU Safe Application IRQ Handler suport to the ARM_AARCH64_SRE port.
+ We thank @GhMarwen for their contribution.
+ + Add Privileged eXecute Never MPU attribute support to the ARMv8-M ports.
+ We thank @AhmedIsmail02 for their contribution.
+ + Update XMOS xcore.ai port to be compatible with FreeRTOS Kernel version
+ 11. We thank @ACascarino for their contribution.
+ + ARM_CRx_No_GIC port updates:
+ - Remove inline assembly and move assembly code to separate portASM.S
+ file.
+ - Add support for Floating Point Unit (FPU).
+ - Add support to allow the application writer to handle SVC calls raised
+ from the application code.
+ - Add support for vApplicationFPUSafeIRQHandler.
+ + POSIX port updates:
+ - Set PTHREAD_MUTEX_ROBUST attribute on the mutex to prevent application
+ hangs when a thread dies while holding a mutex.
+ - Avoid calling pthread_sigmask on non-FreeROS threads when
+ vPortEndScheduler is called from a non-FreeRTOS thread. We thank
+ @johnboiles for their contribution.
+ - Remove unnecessary call to pthread_attr_setstacksize. We thank
+ @hollinsky for their contribution.
+ - Add an assert to catch if vPortYield is called from a non-FreeRTOS
+ thread. We thank @johnboiles for their contribution.
+ - Fix Posix port compilation on FreeBSD. We thank @tymmej for their
+ contribution.
+ + Update the Xtensa port and move it to the Partner-Supported-Ports
+ repository. We thank @ianstcdns for their contribution.
+ + Add vPortGenerateSimulatedInterruptFromWindowsThread API in the MSVC-MingW
+ port to enable native windows thread to synchronize with FreeRTOS task
+ through simulated interrupt.
+ + Update Windows port to use Waitable Timer instead of Sleep to improve tick
+ accuracy. We thank @bknicholls and @leegeth for their contribution.
+ + Update the value of queueQUEUE_TYPE_SET to a unique value (5) to allow
+ tracers to differentiate between queues and queue sets. We thank @schilkp
+ for their contribution.
+ + Add traceSTARTING_SCHEDULER tracing hook to enable tracers to run code on
+ startup. We thank @schilkp for their contribution.
+ + Define vApplicationGetTimerTaskMemory only when configUSE_TIMERS is set to
+ 1. We thank @HazardyKnusperkeks for their contribution.
+ + Reset xNextTaskUnblockTime in task notify FromISR APIs to allow the core
+ to enter sleep mode at the earliest possible time when using tickless
+ idle.
+ + Optimize xTaskIncrementTick for SMP by removing xYieldRequiredForCore. We
+ thank @cymizer for their contribution.
+ + Update the SMP scheduler to re-select a core to yield when the core
+ affinity of a ready task is changed.
+ + Update xEventGroupSetBits to read the event bits value to be returned to
+ the caller while the scheduler is suspended. This fixes dereference after
+ the event group is deleted by higher priority task. We thank @skotopes for
+ their contribution.
+ + Optimize certain getter APIs by removing unnecessary calls to
+ task{ENTER|EXIT}_CRITICAL() when the data access is atomic. We thank
+ @GuilhermeGiacomoSimoes for their contribution.
+ + Optimize xTaskNotifyWait and ulTaskNotifyTake APIs to suspend the
+ scheduler only if the task is not already notified, and the caller is
+ willing to wait for the notification. We thank @jefftenney for
+ their contribution.
+ + Fix error checking of prvCreateIdleTasks. We thank @kakkoko for their
+ contribution.
+ + Update SMP lock macros and critical nesting macros to pass core ID as an
+ argument. This reduces the number of accesses to a peripheral register to
+ query core ID. We thank @felixvanoost for their contribution.
+ + Add stack pointer bounds check when configCHECK_FOR_STACK_OVERFLOW is set
+ to 2 to improve reliability of stack overflow detection. We thank
+ @jiladahe1997 for their contribution.
+ + Update run-time stats to include time elapsed since the last context
+ switch for the currently running task.
+ + Add xQueueCreateSetStatic API for static creation of Queue Sets. We thank
+ @kzorer for their contribution.
+ + Update the traceMALLOC() macro to pass the actual size of the allocated
+ block for secure_heap, heap_2, heap_4 and heap_5. We thank @DazzlingOkami
+ for their contribution.
+ + Update heap_1 to use heapADD_WILL_OVERFLOW macro to improve readability.
+ We thank @wdfk-prog for their contribution.
+ + Add pointer protection to the pxNextFreeBlock member of the allocated
+ block's metadata in heap_4 and heap_5 when configENABLE_HEAP_PROTECTOR is
+ set to 1. We thank @Saiiijchan for their contribution.
+ + Allow the application writer to override pointer validation for heap_5
+ when configENABLE_HEAP_PROTECTOR is used. We thank @Saiiijchan for their
+ contribution.
+ + Add xPortResetHeapMinimumEverFreeHeapSize to heap_4.c and heap_5.c.
+ We thank @TomasGalbickaNXP for their contribution.
+ + Add NULL check in the event_create function in the POSIX port. We thank
+ @laroche for their contribution.
+ + Use _GNU_SOURCE macro instead of __USE_GNU in the Posix port. We thank
+ @maxiaogood for their contribution.
+ + Use the new __ARM_FP macro instead of the deprectred __VFP_FP__ macro in
+ GCC/ARM_CM7, GCC/ARM_CM4_MPU, and GCC/ARM_CM4F ports. We thank @haydenridd
+ for their contribution.
+ + Add portMEMORY_BARRIER definition to the Xtensa port. We thank @superroc
+ for their contribution.
+ + Move the hardware include msp430.h to port.c from portmacro.h. We thank
+ @mayl for their contribution.
+ + Update ARM assembly syntax for Cortex-M ports. We thank @laroche for their
+ contribution.
+ + Update the Windows port to records a pending yield in
+ vPortCloseRunningThread to ensure that the next tick interrupt schedules
+ the next task regardless of the value of configUSE_PREEMPTION.
+ + Fix the context switch issue in the RL78 port. We thank @KeitaKashima for
+ their contribution.
+ + Fix compilation issue in ARM CM0 port when using Keil MDK. We thank
+ @TomasGalbickaNXP for their contribution.
+ + Fix IA32 port compilation when configUSE_COMMON_INTERRUPT_ENTRY_POINT is
+ set to 0. We thank @Ryzee119 for their contribution.
+ + Store configMTIMECMP_BASE_ADDRESS in a 64-bit integer for the RISC-V port.
+ We thank @vishwamartur for their contribution.
+ + Fix nested interrupt handling and optimize FPU related context switching
+ for the F1Kx port. We thank @TrongNguyenR for their contribution.
+ + Update the RP2040 port to add support for Raspberry Pi Pico SDK 2.0.0.
+ We thank @kilograham for their contribution.
+ + Fix the return value of portYIELD_FROM_ISR macro for the MSVC-MingW port.
+ We thank @wwhheerree for their contribution.
+ + Optimize vApplicationFPUSafeIRQHandler for the Coretex-A9 port by
+ removing the unnecessarily preserved callee saved registers. We thank
+ @Saiiijchan for their contribution.
+ + Fix the context array size for MPU ports to ensure the saved context
+ location falls within the reserved context area rather than overlapping
+ with the next MPU_SETTINGS structure member.
+ + Update CMake files for RP2040 port to fetch the port from the
+ Community-Supported-Ports repo. We thank @kilograham for their
+ contribution.
+ + Fix CMake file for the GCC ARM_CM0 port to include MPU files. We thank
+ @0mhu for their contribution.
+ + Add an example of human readable table generated by vTaskListTasks() in
+ the function documentation. We thank @wwhheerree for their contribution.
+
+Changes between FreeRTOS V11.0.1 and FreeRTOS V11.1.0 released April 22, 2024
+
+ + Add ARMv7-R port with Memory Protection Unit (MPU) support.
+ + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
+ + Add stream batching buffer. A stream batching buffer differs from a stream
+ buffer when a task reads from a non-empty buffer:
+ - The task reading from a non-empty stream buffer returns immediately
+ regardless of the amount of data in the buffer.
+ - The task reading from a non-empty steam batching buffer blocks until the
+ amount of data in the buffer exceeds the trigger level or the block time
+ expires.
+ We thank @cperkulator for their contribution.
+ + Add the ability to change task notification index for stream buffers. We
+ thank @glemco for their contribution.
+ + Add xStreamBufferResetFromISR and xMessageBufferResetFromISR APIs to reset
+ stream buffer and message buffer from an Interrupt Service Routine (ISR).
+ We thank @HagaiMoshe for their contribution.
+ + Update all the FreeRTOS APIs to use configSTACK_DEPTH_TYPE for stack type.
+ We thank @feilipu for their contribution.
+ + Update vTaskEndScheduler to delete the timer and idle tasks,
+ once the scheduler is stopped.
+ + Make xTaskGetCurrentTaskHandleForCore() available to the single core
+ scheduler. We thank @Dazza0 for their contribution.
+ + Update uxTaskGetSystemState to not use the pxIndex member of the List_t
+ structure while iterating ready tasks list. The reason is that pxIndex
+ member must only used to select next ready task to run. We thank
+ @gemarcano for their inputs.
+ + Add a config option to the FreeRTOS SMP Kernel to set the default core
+ affinity mask for tasks created without an affinity mask. We thank @go2sh
+ for their contribution.
+ + Add configUSE_EVENT_GROUPS and configUSE_STREAM_BUFFERS configuration
+ constants to control the inclusion of event group and stream buffer
+ functionalities.
+ + Code changes to comply with MISRA C 2012.
+ + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
+ and @josesimoes for their contributions.
+ + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
+ thank @mubinsyed for their contribution.
+ + Add support for MSP430 Embedded Application Binary Interface (EABI) to
+ the MSP430F449 port to make it work with both MSP430 GCC and MSPGCC
+ compilers. We thank @Forty-Bot for their contribution.
+ + Update xPortIsAuthorizedToAccessBuffer() on FreeRTOS ports with MPU
+ support to grant an unprivileged task access to all the memory before the
+ scheduler is started.
+ + Update the POSIX port to pass the FreeRTOS task name to pthread for
+ readable output in debuggers. We thank @Mixaill for their contribution.
+ + Update the POSIX port to ignore the user specified stack memory and only
+ pass the stack size to the pthread API to avoid errors caused when stack size
+ is smaller than the minimum. We thank @cmorgnaBE for their
+ contribution.
+ + Update the POSIX port to use a timer thread for tick interrupts instead of
+ POSIX timers to address issues with signal handling in non-FreeRTOS
+ pthreads. We thank @cmorgnaBE for their contribution.
+ + Update ARM_TFM port to support TF-Mv2.0.0 release of trusted-firmware-m.
+ We thanks @urutva for their contribution.
+ + Remove redundant constant pools in ARMv8 ports. We thank @urutva for their
+ contribution.
+ + Add APIs to reset the internal state of kernel modules. These APIs are
+ primarily intended to be used in the testing frameworks that restart the
+ scheduler.
+ + Use kernel provided implementations of vApplicationGetIdleTaskMemory() and
+ vApplicationGetTimerTaskMemory() in the RP2040 port. We thank @dpslwk for
+ their contribution.
+ + Fix atomic enter/exit critical section macro definitions in atomic.h for
+ ports that support nested interrupts. We thank @sebunger for their
+ contribution.
+ + Fix compiler warnings in the MSP430F449 port when compiled with the
+ MSP430 GCC compiler. We thank @Forty-Bot for their contribution.
+ + Update the scheduler suspension usage in ulTaskGenericNotifyTake and
+ xTaskGenericNotifyWait() to enhance code readability. We thank @Dazza0 for
+ their contribution.
+ + Add support for latest version of MPU wrappers( mpu_wrappers_v2) in CMake.
+ We thank @IsaacDynamo for their contribution.
+ + Update CMake support to create only one static library containing both the
+ kernel common code and the kernel port code. We thank @barnatahmed for
+ their contribution.
+
+Changes between FreeRTOS V11.0.0 and FreeRTOS V11.0.1 released December 21, 2023
+
+ + Updated the SBOM file.
+
+Changes between FreeRTOS V10.6.2 and FreeRTOS V11.0.0 released December 18, 2023
+
+ + SMP merged into the mainline: While FreeRTOS introduced Asymmetric
+ Multiprocessing (AMP) support in 2017, FreeRTOS Version 11.0.0 is the
+ first to merge Symmetric Multiprocessing (SMP) support into the mainline
+ release. SMP enables one instance of the FreeRTOS Kernel to schedule tasks
+ across multiple identical processor cores. We thank Mike Bruno and Jerry
+ McCarthy of XMOS and, Darian Liang, Sudeep Mohanty and Zim Kalinowski of
+ Espressif Systems for their contributions.
+ + Switch MISRA compliance checking from PC Lint to Coverity, and update from
+ MISRA C:2004 to MISRA C:2012.
+ + Add a template FreeRTOSConfig.h, inclusive of an abbreviated explanation of
+ each configuration item. Application writers can use this template as a
+ starting point to create the FreeRTOSConfig.h file for their application.
+ + Add a template FreeRTOS port which can be used as a starting point for
+ developing a new FreeRTOS port.
+ + Add bounds checking and obfuscation to internal heap block pointers in
+ heap_4.c and heap_5.c to help catch pointer corruptions. The application can
+ enable these checks by setting configENABLE_HEAP_PROTECTOR to 1 in their
+ FreeRTOSConfig.h. We thank @oliverlavery for their contribution.
+ + Update vTaskList and vTaskGetRunTimeStats APIs to replace the use of sprintf
+ with snprintf.
+ + Add trace macros to ports that enable tracing the interaction of ISRs with
+ scheduler events. We thank @conara for their contribution.
+ + Add trace macros that enable tracing of entering and exiting all APIs. We
+ thank @Techcore123 for their contribution.
+ + Add uxTaskBasePriorityGet and uxTaskBasePriorityGetFromISR APIs to get the
+ base priority of a task. The base priority of a task is the priority that
+ was last assigned to the task - which due to priority inheritance, may not
+ be the current priority of the task.
+ + Add pdTICKS_TO_MS macro to convert time in FreeRTOS ticks to time in
+ milliseconds. We thank @Dazza0 for their contribution.
+ + Add default implementations of vApplicationGetIdleTaskMemory and
+ vApplicationGetTimerTaskMemory. The application can enable these default
+ implementations by setting configKERNEL_PROVIDED_STATIC_MEMORY to 1 in their
+ FreeRTOSConfig.h. We thank @mdnr-g for their contribution.
+ + Update vTaskGetInfo to include start and end of the stack whenever both
+ values are available. We thank @vinceburns for their contribution.
+ + Prevent tasks waiting for a notification from being resumed by calls to
+ vTaskResume or vTaskResumeFromISR. We thank @Moral-Hao for their
+ contribution.
+ + Add asserts to validate that the application has correctly installed
+ FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices.
+ We thank @jefftenney for their contribution.
+ + Rename ARM_CA53_64_BIT and ARM_CA53_64_BIT_SRE ports to Arm_AARCH64 and
+ Arm_AARCH64_SRE respectively as these ports are applicable to all AArch64
+ architecture. We thank @urutva for their contribution.
+ + Add CMake support to allow the application writer to select the RISC-V
+ chip extension. We thank @JoeBenczarski for their contribution.
+ + Add CMake support to allow the application writer to build an application
+ with static allocation only. We thank @conara for their contribution.
+ + Make taskYIELD available to unprivileged tasks for ARMv8-M ports.
+ + Update Cortex-M23 ports to not use PSPLIM_NS. We thank @urutva for their
+ contribution.
+ + Update the SysTick setup code for ARMv8-M ports to first configure the clock
+ source and then enable SysTick. This is needed to address a bug in QEMU
+ versions older than 7.0.0, which causes an emulation error if SysTick is
+ enabled without first selecting a valid clock source. We thank @jefftenney
+ for their contribution.
+ + Add the port-optimized task selection algorithm optionally available for
+ ARMv7-M ports to the ARMv8-M ports. We thank @jefftenney for their
+ contribution.
+ + Improve the speed of pvPortMalloc in heap_4.c and heap_5.c by removing
+ unnecessary steps while splitting a large memory block into two. We thank
+ @Moral-Hao for their contribution.
+ + Shorten the critical section in pvPortMalloc in heap_2.c, heap_4.c and
+ heap_5.c by moving the size calculation out of the critical section. We thank
+ @Moral-Hao for their contribution.
+ + Update xTaskNotifyWait and ulTaskNotifyTake to remove the non-deterministic
+ operation of traversing a linked link from a critical section. We thank
+ @karver8 for their contribution.
+ + Fix stack end and stack size computation in POSIX port to meet the stack
+ alignment requirements on MacOS. We thank @tegimeki for their contribution.
+ + Update the vTaskPrioritySet implementation to use the new priority when the
+ task has inherited priority from a mutex it is holding, and the new priority
+ is bigger than the inherited priority. We thank @Moral-Hao for their
+ contribution.
+ + Add stack alignment adjustment if stack grows upwards. We thank @ivq for
+ their contribution.
+ + Fix pxTopOfStack calculation in configINIT_TLS_BLOCK when picolib C is
+ selected as the C library implementation to ensure that
+ pxPortInitialiseStack does not overwrite the data in the TLS block portion
+ of the stack. We thank @bebebib-rs for their contribution.
+ + Fix vPortEndScheduler() for the MSVC port so that the function
+ prvProcessSimulatedInterrupts is not stuck in an infinite loop when the
+ scheduler is stopped. We thank @Ju1He1 for their contribution.
+ + Add the Pull Request (PR) Process explaining the stages a PR goes through.
+
Changes between FreeRTOS V10.6.1 and FreeRTOS V10.6.2 released November 29, 2023
+ Add the following improvements to the new MPU wrapper (mpu_wrappers_v2.c)
@@ -26,7 +330,7 @@
- Xinhui Shao, Yumeng Wei, Huaiyu Yan, Zhen Ling of School of
Computer Science and Engineering, Southeast University, China.
-Changes between FreeRTOS V10.5.1 and FreeRTOS V10.6.0 released July 13, 2023
+Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023
+ Add a new MPU wrapper that places additional restrictions on unprivileged
tasks. The following is the list of changes introduced with the new MPU
@@ -87,8 +391,8 @@
China.
- Xinwen Fu of Department of Computer Science, University of
Massachusetts Lowell, USA.
- - Yuequi Chen, Zicheng Wang, Minghao Lin of University of Colorado
- Boulder, USA.
+ - Yueqi Chen, Zicheng Wang, Minghao Lin, Jiahe Wang of University of
+ Colorado Boulder, USA.
+ Add Cortex-M35P port. Contributed by @urutva.
+ Add embedded extension (RV32E) support to the IAR RISC-V port.
+ Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent APIs. Contributed by
@@ -359,7 +663,7 @@
in more files.
+ Other minor updates include adding additional configASSERT() checks and
correcting and improving code comments.
- + Go look at the smp branch to see the progress towards the Symetric
+ + Go look at the smp branch to see the progress towards the Symmetric
Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp
Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
@@ -1846,7 +2150,7 @@
Embedded Workbench.
+ Added a new port for the MSP430X core using the IAR Embedded Workbench.
+ Updated all the RX62N demo projects that target the Renesas Demonstration
- Kit (RDK) to take into account the revered LED wiring on later hardware
+ Kit (RDK) to take into account the reversed LED wiring on later hardware
revisions, and the new J-Link debug interface DLL.
+ Updated all the RX62N demo projects so the IO page served by the example
embedded web server works with all web browsers.
@@ -3005,7 +3309,7 @@
xSerialPortInitMinimal() and the function xPortInit() has been renamed
to xSerialPortInit().
+ The function sSerialPutChar() has been renamed cSerialPutChar() and
- the function return type chaned to portCHAR.
+ the function return type changed to portCHAR.
+ The integer and flop tasks now include calls to tskYIELD(), allowing
them to be used with the cooperative scheduler.
+ All the demo applications now use the integer and comtest tasks when the
@@ -3139,7 +3443,7 @@
ports to allocate a different maximum number of priorities.
+ By default the trace facility is off, previously USE_TRACE_FACILITY
was defined.
- + comtest.c now uses a psuedo random delay between sends. This allows for
+ + comtest.c now uses a pseudo random delay between sends. This allows for
better testing as the interrupts do not arrive at regular intervals.
+ Minor change to the Flashlite serial port driver. The driver is written
to demonstrate the scheduler and is not written to be efficient.
diff --git a/Source/README.md b/Source/README.md
index dd79eee..a6d383a 100644
--- a/Source/README.md
+++ b/Source/README.md
@@ -1,18 +1,45 @@
[](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++)
[](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
+
## Getting started
-This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory.
-The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects. That way you will have the correct FreeRTOS source files included, and the correct include paths configured. Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files. See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
+This repository contains FreeRTOS kernel source/header files and kernel
+ports only. This repository is referenced as a submodule in
+[FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS)
+repository, which contains pre-configured demo application projects under
+```FreeRTOS/Demo``` directory.
-Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo
+application projects. That way you will have the correct FreeRTOS source files
+included, and the correct include paths configured. Once a demo application is
+building and executing you can remove the demo application files, and start to
+add in your own application source files. See the
+[FreeRTOS Kernel Quick Start Guide](https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide)
+for detailed instructions and other useful links.
+
+Additionally, for FreeRTOS kernel feature information refer to the
+[Developer Documentation](https://www.freertos.org/Documentation/02-Kernel/02-Kernel-features/00-Developer-docs),
+and [API Reference](https://www.freertos.org/Documentation/02-Kernel/04-API-references/01-Task-creation/00-TaskHandle).
+
+Also for contributing and creating a Pull Request please refer to
+[the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request).
+
+**FreeRTOS-Kernel V11.1.0
+[source code](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/V11.1.0) is part
+of the
+[FreeRTOS 202406.00 LTS](https://github.com/FreeRTOS/FreeRTOS-LTS/tree/202406-LTS)
+release.**
### Getting help
-If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).
+
+If you have any questions or need assistance troubleshooting your FreeRTOS project,
+we have an active community that can help on the
+[FreeRTOS Community Support Forum](https://forums.freertos.org).
## To consume FreeRTOS-Kernel
### Consume with CMake
+
If using CMake, it is recommended to use this repository using FetchContent.
Add the following into your project's main or a subdirectory's `CMakeLists.txt`:
@@ -25,8 +52,16 @@
)
```
+In case you prefer to add it as a git submodule, do:
+
+```bash
+git submodule add https://github.com/FreeRTOS/FreeRTOS-Kernel.git <path of the submodule>
+git submodule update --init
+```
+
- Add a freertos_config library (typically an INTERFACE library) The following assumes the directory structure:
- `include/FreeRTOSConfig.h`
+
```cmake
add_library(freertos_config INTERFACE)
@@ -41,6 +76,12 @@
)
```
+In case you installed FreeRTOS-Kernel as a submodule, you will have to add it as a subdirectory:
+
+```cmake
+add_subdirectory(${FREERTOS_PATH})
+```
+
- Configure the FreeRTOS-Kernel and make it available
- this particular example supports a native and cross-compiled build option.
@@ -56,18 +97,29 @@
FetchContent_MakeAvailable(freertos_kernel)
```
+- In case of cross compilation, you should also add the following to `freertos_config`:
+
+```cmake
+target_compile_definitions(freertos_config INTERFACE ${definitions})
+target_compile_options(freertos_config INTERFACE ${options})
+```
+
### Consuming stand-alone - Cloning this repository
To clone using HTTPS:
+
```
git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git
```
+
Using SSH:
+
```
git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git
```
## Repository structure
+
- The root of this repository contains the three files that are common to
every port - list.c, queue.c and tasks.c. The kernel is contained within these
three files. croutine.c implements the optional co-routine functionality - which
@@ -78,23 +130,63 @@
- The ```./include``` directory contains the real time kernel header files.
+- The ```./template_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project.
+See the [FreeRTOSConfig.h](examples/template_configuration/FreeRTOSConfig.h) file for instructions.
+
### Code Formatting
-FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [.github/uncrustify.cfg](.github/uncrustify.cfg) file.
+
+FreeRTOS files are formatted using the
+"[uncrustify](https://github.com/uncrustify/uncrustify)" tool.
+The configuration file used by uncrustify can be found in the
+[FreeRTOS/CI-CD-GitHub-Actions's](https://github.com/FreeRTOS/CI-CD-Github-Actions)
+[uncrustify.cfg](https://github.com/FreeRTOS/CI-CD-Github-Actions/tree/main/formatting)
+file.
### Line Endings
-File checked into the FreeRTOS-Kernel repository use unix-style LF line endings for the best compatbility with git.
-For optmial compatibility with Microsoft Windows tools, it is best to enable the git autocrlf feature. You can eanble this setting for the current repository using the following command:
+File checked into the FreeRTOS-Kernel repository use unix-style LF line endings
+for the best compatibility with git.
+
+For optimal compatibility with Microsoft Windows tools, it is best to enable
+the git autocrlf feature. You can enable this setting for the current
+repository using the following command:
+
```
git config core.autocrlf true
```
### Git History Optimizations
-Some commits in this repository perform large refactors which touch many lines and lead to unwanted behavior when using the `git blame` command. You can configure git to ignore the list of large refactor commits in this repository with the followig command:
+
+Some commits in this repository perform large refactors which touch many lines
+and lead to unwanted behavior when using the `git blame` command. You can
+configure git to ignore the list of large refactor commits in this repository
+with the following command:
+
```
git config blame.ignoreRevsFile .git-blame-ignore-revs
```
-### Spelling
-*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*.
-Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.
+### Spelling and Formatting
+
+We recommend using [Visual Studio Code](https://code.visualstudio.com),
+commonly referred to as VSCode, when working on the FreeRTOS-Kernel.
+The FreeRTOS-Kernel also uses [cSpell](https://cspell.org/) as part of its
+spelling check. The config file for which can be found at [cspell.config.yaml](cspell.config.yaml)
+There is additionally a
+[cSpell plugin for VSCode](https://marketplace.visualstudio.com/items?itemName=streetsidesoftware.code-spell-checker)
+that can be used as well.
+*[.cSpellWords.txt](.github/.cSpellWords.txt)* contains words that are not
+traditionally found in an English dictionary. It is used by the spellchecker
+to verify the various jargon, variable names, and other odd words used in the
+FreeRTOS code base are correct. If your pull request fails to pass the spelling
+and you believe this is a mistake, then add the word to
+*[.cSpellWords.txt](.github/.cSpellWords.txt)*. When adding a word please
+then sort the list, which can be done by running the bash command:
+`sort -u .cSpellWords.txt -o .cSpellWords.txt`
+Note that only the FreeRTOS-Kernel Source Files, [include](include),
+[portable/MemMang](portable/MemMang), and [portable/Common](portable/Common)
+files are checked for proper spelling, and formatting at this time.
+
+## Third Party Tools
+Visit [this link](.github/third_party_tools.md) for detailed information about
+third-party tools with FreeRTOS support.
diff --git a/Source/croutine.c b/Source/croutine.c
index 559276c..99aa0dc 100644
--- a/Source/croutine.c
+++ b/Source/croutine.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@
#include "task.h"
#include "croutine.h"
-/* Remove the whole file is co-routines are not being used. */
+/* Remove the whole file if co-routines are not being used. */
#if ( configUSE_CO_ROUTINES != 0 )
/*
@@ -43,17 +43,19 @@
/* Lists for ready and blocked co-routines. --------------------*/
- static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
- static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */
- static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
- static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */
- static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
- static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+ static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /**< Prioritised ready co-routines. */
+ static List_t xDelayedCoRoutineList1; /**< Delayed co-routines. */
+ static List_t xDelayedCoRoutineList2; /**< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+ static List_t * pxDelayedCoRoutineList = NULL; /**< Points to the delayed co-routine list currently being used. */
+ static List_t * pxOverflowDelayedCoRoutineList = NULL; /**< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+ static List_t xPendingReadyCoRoutineList; /**< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
/* Other file private variables. --------------------------------*/
CRCB_t * pxCurrentCoRoutine = NULL;
- static UBaseType_t uxTopCoRoutineReadyPriority = 0;
- static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+ static UBaseType_t uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
+ static TickType_t xCoRoutineTickCount = ( TickType_t ) 0U;
+ static TickType_t xLastTickCount = ( TickType_t ) 0U;
+ static TickType_t xPassedTicks = ( TickType_t ) 0U;
/* The initial state of the co-routine when it is created. */
#define corINITIAL_STATE ( 0 )
@@ -107,7 +109,12 @@
BaseType_t xReturn;
CRCB_t * pxCoRoutine;
+ traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex );
+
/* Allocate the memory that will store the co-routine control block. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
if( pxCoRoutine )
@@ -156,6 +163,8 @@
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
}
+ traceRETURN_xCoRoutineCreate( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -165,6 +174,8 @@
{
TickType_t xTimeToWake;
+ traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList );
+
/* Calculate the time to wake - this may overflow but this is
* not a problem. */
xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
@@ -196,6 +207,8 @@
* function must be called with interrupts disabled. */
vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
}
+
+ traceRETURN_vCoRoutineAddToDelayedList();
}
/*-----------------------------------------------------------*/
@@ -283,6 +296,8 @@
void vCoRoutineSchedule( void )
{
+ traceENTER_vCoRoutineSchedule();
+
/* Only run a co-routine after prvInitialiseCoRoutineLists() has been
* called. prvInitialiseCoRoutineLists() is called automatically when a
* co-routine is created. */
@@ -313,6 +328,8 @@
/* Call the co-routine. */
( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
}
+
+ traceRETURN_vCoRoutineSchedule();
}
/*-----------------------------------------------------------*/
@@ -341,6 +358,8 @@
CRCB_t * pxUnblockedCRCB;
BaseType_t xReturn;
+ traceENTER_xCoRoutineRemoveFromEventList( pxEventList );
+
/* This function is called from within an interrupt. It can only access
* event lists and the pending ready list. This function assumes that a
* check has already been made to ensure pxEventList is not empty. */
@@ -357,7 +376,30 @@
xReturn = pdFALSE;
}
+ traceRETURN_xCoRoutineRemoveFromEventList( xReturn );
+
return xReturn;
}
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+ void vCoRoutineResetState( void )
+ {
+ /* Lists for ready and blocked co-routines. */
+ pxDelayedCoRoutineList = NULL;
+ pxOverflowDelayedCoRoutineList = NULL;
+
+ /* Other file private variables. */
+ pxCurrentCoRoutine = NULL;
+ uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
+ xCoRoutineTickCount = ( TickType_t ) 0U;
+ xLastTickCount = ( TickType_t ) 0U;
+ xPassedTicks = ( TickType_t ) 0U;
+ }
+/*-----------------------------------------------------------*/
#endif /* configUSE_CO_ROUTINES == 0 */
diff --git a/Source/event_groups.c b/Source/event_groups.c
index e337f13..09f2ec0 100644
--- a/Source/event_groups.c
+++ b/Source/event_groups.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -30,7 +30,7 @@
#include <stdlib.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
+ * all the API functions to use the MPU wrappers. That should only be done when
* task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -40,25 +40,30 @@
#include "timers.h"
#include "event_groups.h"
-/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
* for the header files above, but not in this file, in order to generate the
* correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-typedef struct EventGroupDef_t
-{
- EventBits_t uxEventBits;
- List_t xTasksWaitingForBits; /**< List of tasks waiting for a bit to be set. */
+/* This entire source file will be skipped if the application is not configured
+ * to include event groups functionality. This #if is closed at the very bottom
+ * of this file. If you want to include event groups then ensure
+ * configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_EVENT_GROUPS == 1 )
- #if ( configUSE_TRACE_FACILITY == 1 )
- UBaseType_t uxEventGroupNumber;
- #endif
+ typedef struct EventGroupDef_t
+ {
+ EventBits_t uxEventBits;
+ List_t xTasksWaitingForBits; /**< List of tasks waiting for a bit to be set. */
- #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
- #endif
-} EventGroup_t;
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxEventGroupNumber;
+ #endif
+
+ #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+ #endif
+ } EventGroup_t;
/*-----------------------------------------------------------*/
@@ -70,356 +75,207 @@
* wait condition is met if any of the bits set in uxBitsToWait for are also set
* in uxCurrentEventBits.
*/
-static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
- const EventBits_t uxBitsToWaitFor,
- const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
- {
- EventGroup_t * pxEventBits;
-
- /* A StaticEventGroup_t object must be provided. */
- configASSERT( pxEventGroupBuffer );
-
- #if ( configASSERT_DEFINED == 1 )
+ EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
{
- /* Sanity check that the size of the structure used to declare a
- * variable of type StaticEventGroup_t equals the size of the real
- * event group structure. */
- volatile size_t xSize = sizeof( StaticEventGroup_t );
- configASSERT( xSize == sizeof( EventGroup_t ) );
- } /*lint !e529 xSize is referenced if configASSERT() is defined. */
- #endif /* configASSERT_DEFINED */
+ EventGroup_t * pxEventBits;
- /* The user has provided a statically allocated event group - use it. */
- pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+ traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer );
- if( pxEventBits != NULL )
- {
- pxEventBits->uxEventBits = 0;
- vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+ /* A StaticEventGroup_t object must be provided. */
+ configASSERT( pxEventGroupBuffer );
- #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #if ( configASSERT_DEFINED == 1 )
{
- /* Both static and dynamic allocation can be used, so note that
- * this event group was created statically in case the event group
- * is later deleted. */
- pxEventBits->ucStaticallyAllocated = pdTRUE;
+ /* Sanity check that the size of the structure used to declare a
+ * variable of type StaticEventGroup_t equals the size of the real
+ * event group structure. */
+ volatile size_t xSize = sizeof( StaticEventGroup_t );
+ configASSERT( xSize == sizeof( EventGroup_t ) );
}
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ #endif /* configASSERT_DEFINED */
- traceEVENT_GROUP_CREATE( pxEventBits );
- }
- else
- {
- /* xEventGroupCreateStatic should only ever be called with
- * pxEventGroupBuffer pointing to a pre-allocated (compile time
- * allocated) StaticEventGroup_t variable. */
- traceEVENT_GROUP_CREATE_FAILED();
- }
+ /* The user has provided a statically allocated event group - use it. */
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer;
- return pxEventBits;
- }
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
- EventGroupHandle_t xEventGroupCreate( void )
- {
- EventGroup_t * pxEventBits;
-
- /* Allocate the event group. Justification for MISRA deviation as
- * follows: pvPortMalloc() always ensures returned memory blocks are
- * aligned per the requirements of the MCU stack. In this case
- * pvPortMalloc() must return a pointer that is guaranteed to meet the
- * alignment requirements of the EventGroup_t structure - which (if you
- * follow it through) is the alignment requirements of the TickType_t type
- * (EventBits_t being of TickType_t itself). Therefore, whenever the
- * stack alignment requirements are greater than or equal to the
- * TickType_t alignment requirements the cast is safe. In other cases,
- * where the natural word size of the architecture is less than
- * sizeof( TickType_t ), the TickType_t variables will be accessed in two
- * or more reads operations, and the alignment requirements is only that
- * of each individual read. */
- pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
-
- if( pxEventBits != NULL )
- {
- pxEventBits->uxEventBits = 0;
- vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
-
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ if( pxEventBits != NULL )
{
- /* Both static and dynamic allocation can be used, so note this
- * event group was allocated statically in case the event group is
- * later deleted. */
- pxEventBits->ucStaticallyAllocated = pdFALSE;
- }
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ pxEventBits->uxEventBits = 0;
+ vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
- traceEVENT_GROUP_CREATE( pxEventBits );
- }
- else
- {
- traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
- }
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* Both static and dynamic allocation can be used, so note that
+ * this event group was created statically in case the event group
+ * is later deleted. */
+ pxEventBits->ucStaticallyAllocated = pdTRUE;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
- return pxEventBits;
- }
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait )
-{
- EventBits_t uxOriginalBitValue, uxReturn;
- EventGroup_t * pxEventBits = xEventGroup;
- BaseType_t xAlreadyYielded;
- BaseType_t xTimeoutOccurred = pdFALSE;
-
- configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
- configASSERT( uxBitsToWaitFor != 0 );
- #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
- #endif
-
- vTaskSuspendAll();
- {
- uxOriginalBitValue = pxEventBits->uxEventBits;
-
- ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
-
- if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
- {
- /* All the rendezvous bits are now set - no need to block. */
- uxReturn = ( uxOriginalBitValue | uxBitsToSet );
-
- /* Rendezvous always clear the bits. They will have been cleared
- * already unless this is the only task in the rendezvous. */
- pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
-
- xTicksToWait = 0;
- }
- else
- {
- if( xTicksToWait != ( TickType_t ) 0 )
- {
- traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
-
- /* Store the bits that the calling task is waiting for in the
- * task's event list item so the kernel knows when a match is
- * found. Then enter the blocked state. */
- vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
-
- /* This assignment is obsolete as uxReturn will get set after
- * the task unblocks, but some compilers mistakenly generate a
- * warning about uxReturn being returned without being set if the
- * assignment is omitted. */
- uxReturn = 0;
+ traceEVENT_GROUP_CREATE( pxEventBits );
}
else
{
- /* The rendezvous bits were not set, but no block time was
- * specified - just return the current event bit value. */
- uxReturn = pxEventBits->uxEventBits;
- xTimeoutOccurred = pdTRUE;
+ /* xEventGroupCreateStatic should only ever be called with
+ * pxEventGroupBuffer pointing to a pre-allocated (compile time
+ * allocated) StaticEventGroup_t variable. */
+ traceEVENT_GROUP_CREATE_FAILED();
}
- }
- }
- xAlreadyYielded = xTaskResumeAll();
- if( xTicksToWait != ( TickType_t ) 0 )
- {
- if( xAlreadyYielded == pdFALSE )
- {
- portYIELD_WITHIN_API();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
+ traceRETURN_xEventGroupCreateStatic( pxEventBits );
+
+ return pxEventBits;
}
- /* The task blocked to wait for its required bits to be set - at this
- * point either the required bits were set or the block time expired. If
- * the required bits were set they will have been stored in the task's
- * event list item, and they should now be retrieved then cleared. */
- uxReturn = uxTaskResetEventItemValue();
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
- if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+ EventGroupHandle_t xEventGroupCreate( void )
{
- /* The task timed out, just return the current event bit value. */
- taskENTER_CRITICAL();
+ EventGroup_t * pxEventBits;
+
+ traceENTER_xEventGroupCreate();
+
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
+
+ if( pxEventBits != NULL )
{
- uxReturn = pxEventBits->uxEventBits;
+ pxEventBits->uxEventBits = 0;
+ vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
- /* Although the task got here because it timed out before the
- * bits it was waiting for were set, it is possible that since it
- * unblocked another task has set the bits. If this is the case
- * then it needs to clear the bits before exiting. */
- if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
{
- pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+ /* Both static and dynamic allocation can be used, so note this
+ * event group was allocated statically in case the event group is
+ * later deleted. */
+ pxEventBits->ucStaticallyAllocated = pdFALSE;
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ traceEVENT_GROUP_CREATE( pxEventBits );
+ }
+ else
+ {
+ traceEVENT_GROUP_CREATE_FAILED();
+ }
+
+ traceRETURN_xEventGroupCreate( pxEventBits );
+
+ return pxEventBits;
+ }
+
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait )
+ {
+ EventBits_t uxOriginalBitValue, uxReturn;
+ EventGroup_t * pxEventBits = xEventGroup;
+ BaseType_t xAlreadyYielded;
+ BaseType_t xTimeoutOccurred = pdFALSE;
+
+ traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+
+ configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+ configASSERT( uxBitsToWaitFor != 0 );
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+ vTaskSuspendAll();
+ {
+ uxOriginalBitValue = pxEventBits->uxEventBits;
+
+ ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+ if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+ {
+ /* All the rendezvous bits are now set - no need to block. */
+ uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+ /* Rendezvous always clear the bits. They will have been cleared
+ * already unless this is the only task in the rendezvous. */
+ pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+ xTicksToWait = 0;
+ }
+ else
+ {
+ if( xTicksToWait != ( TickType_t ) 0 )
+ {
+ traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+ /* Store the bits that the calling task is waiting for in the
+ * task's event list item so the kernel knows when a match is
+ * found. Then enter the blocked state. */
+ vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+ /* This assignment is obsolete as uxReturn will get set after
+ * the task unblocks, but some compilers mistakenly generate a
+ * warning about uxReturn being returned without being set if the
+ * assignment is omitted. */
+ uxReturn = 0;
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ /* The rendezvous bits were not set, but no block time was
+ * specified - just return the current event bit value. */
+ uxReturn = pxEventBits->uxEventBits;
+ xTimeoutOccurred = pdTRUE;
}
}
- taskEXIT_CRITICAL();
-
- xTimeoutOccurred = pdTRUE;
}
- else
+ xAlreadyYielded = xTaskResumeAll();
+
+ if( xTicksToWait != ( TickType_t ) 0 )
{
- /* The task unblocked because the bits were set. */
- }
-
- /* Control bits might be set as the task had blocked should not be
- * returned. */
- uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
- }
-
- traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
-
- /* Prevent compiler warnings when trace macros are not used. */
- ( void ) xTimeoutOccurred;
-
- return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToWaitFor,
- const BaseType_t xClearOnExit,
- const BaseType_t xWaitForAllBits,
- TickType_t xTicksToWait )
-{
- EventGroup_t * pxEventBits = xEventGroup;
- EventBits_t uxReturn, uxControlBits = 0;
- BaseType_t xWaitConditionMet, xAlreadyYielded;
- BaseType_t xTimeoutOccurred = pdFALSE;
-
- /* Check the user is not attempting to wait on the bits used by the kernel
- * itself, and that at least one bit is being requested. */
- configASSERT( xEventGroup );
- configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
- configASSERT( uxBitsToWaitFor != 0 );
- #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
- #endif
-
- vTaskSuspendAll();
- {
- const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
-
- /* Check to see if the wait condition is already met or not. */
- xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
-
- if( xWaitConditionMet != pdFALSE )
- {
- /* The wait condition has already been met so there is no need to
- * block. */
- uxReturn = uxCurrentEventBits;
- xTicksToWait = ( TickType_t ) 0;
-
- /* Clear the wait bits if requested to do so. */
- if( xClearOnExit != pdFALSE )
+ if( xAlreadyYielded == pdFALSE )
{
- pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else if( xTicksToWait == ( TickType_t ) 0 )
- {
- /* The wait condition has not been met, but no block time was
- * specified, so just return the current value. */
- uxReturn = uxCurrentEventBits;
- xTimeoutOccurred = pdTRUE;
- }
- else
- {
- /* The task is going to block to wait for its required bits to be
- * set. uxControlBits are used to remember the specified behaviour of
- * this call to xEventGroupWaitBits() - for use when the event bits
- * unblock the task. */
- if( xClearOnExit != pdFALSE )
- {
- uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+ taskYIELD_WITHIN_API();
}
else
{
mtCOVERAGE_TEST_MARKER();
}
- if( xWaitForAllBits != pdFALSE )
- {
- uxControlBits |= eventWAIT_FOR_ALL_BITS;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* The task blocked to wait for its required bits to be set - at this
+ * point either the required bits were set or the block time expired. If
+ * the required bits were set they will have been stored in the task's
+ * event list item, and they should now be retrieved then cleared. */
+ uxReturn = uxTaskResetEventItemValue();
- /* Store the bits that the calling task is waiting for in the
- * task's event list item so the kernel knows when a match is
- * found. Then enter the blocked state. */
- vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
-
- /* This is obsolete as it will get set after the task unblocks, but
- * some compilers mistakenly generate a warning about the variable
- * being returned without being set if it is not done. */
- uxReturn = 0;
-
- traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
- }
- }
- xAlreadyYielded = xTaskResumeAll();
-
- if( xTicksToWait != ( TickType_t ) 0 )
- {
- if( xAlreadyYielded == pdFALSE )
- {
- portYIELD_WITHIN_API();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* The task blocked to wait for its required bits to be set - at this
- * point either the required bits were set or the block time expired. If
- * the required bits were set they will have been stored in the task's
- * event list item, and they should now be retrieved then cleared. */
- uxReturn = uxTaskResetEventItemValue();
-
- if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
- {
- taskENTER_CRITICAL();
+ if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
{
/* The task timed out, just return the current event bit value. */
- uxReturn = pxEventBits->uxEventBits;
-
- /* It is possible that the event bits were updated between this
- * task leaving the Blocked state and running again. */
- if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+ taskENTER_CRITICAL();
{
- if( xClearOnExit != pdFALSE )
+ uxReturn = pxEventBits->uxEventBits;
+
+ /* Although the task got here because it timed out before the
+ * bits it was waiting for were set, it is possible that since it
+ * unblocked another task has set the bits. If this is the case
+ * then it needs to clear the bits before exiting. */
+ if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
{
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
}
@@ -428,372 +284,604 @@
mtCOVERAGE_TEST_MARKER();
}
}
+ taskEXIT_CRITICAL();
+
+ xTimeoutOccurred = pdTRUE;
+ }
+ else
+ {
+ /* The task unblocked because the bits were set. */
+ }
+
+ /* Control bits might be set as the task had blocked should not be
+ * returned. */
+ uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+ }
+
+ traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xTimeoutOccurred;
+
+ traceRETURN_xEventGroupSync( uxReturn );
+
+ return uxReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xClearOnExit,
+ const BaseType_t xWaitForAllBits,
+ TickType_t xTicksToWait )
+ {
+ EventGroup_t * pxEventBits = xEventGroup;
+ EventBits_t uxReturn, uxControlBits = 0;
+ BaseType_t xWaitConditionMet, xAlreadyYielded;
+ BaseType_t xTimeoutOccurred = pdFALSE;
+
+ traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+
+ /* Check the user is not attempting to wait on the bits used by the kernel
+ * itself, and that at least one bit is being requested. */
+ configASSERT( xEventGroup );
+ configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+ configASSERT( uxBitsToWaitFor != 0 );
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+ vTaskSuspendAll();
+ {
+ const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+ /* Check to see if the wait condition is already met or not. */
+ xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+ if( xWaitConditionMet != pdFALSE )
+ {
+ /* The wait condition has already been met so there is no need to
+ * block. */
+ uxReturn = uxCurrentEventBits;
+ xTicksToWait = ( TickType_t ) 0;
+
+ /* Clear the wait bits if requested to do so. */
+ if( xClearOnExit != pdFALSE )
+ {
+ pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* The wait condition has not been met, but no block time was
+ * specified, so just return the current value. */
+ uxReturn = uxCurrentEventBits;
+ xTimeoutOccurred = pdTRUE;
+ }
+ else
+ {
+ /* The task is going to block to wait for its required bits to be
+ * set. uxControlBits are used to remember the specified behaviour of
+ * this call to xEventGroupWaitBits() - for use when the event bits
+ * unblock the task. */
+ if( xClearOnExit != pdFALSE )
+ {
+ uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+ }
else
{
mtCOVERAGE_TEST_MARKER();
}
- xTimeoutOccurred = pdTRUE;
- }
- taskEXIT_CRITICAL();
- }
- else
- {
- /* The task unblocked because the bits were set. */
- }
-
- /* The task blocked so control bits may have been set. */
- uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
- }
-
- traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
-
- /* Prevent compiler warnings when trace macros are not used. */
- ( void ) xTimeoutOccurred;
-
- return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear )
-{
- EventGroup_t * pxEventBits = xEventGroup;
- EventBits_t uxReturn;
-
- /* Check the user is not attempting to clear the bits used by the kernel
- * itself. */
- configASSERT( xEventGroup );
- configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-
- taskENTER_CRITICAL();
- {
- traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
-
- /* The value returned is the event group value prior to the bits being
- * cleared. */
- uxReturn = pxEventBits->uxEventBits;
-
- /* Clear the bits. */
- pxEventBits->uxEventBits &= ~uxBitsToClear;
- }
- taskEXIT_CRITICAL();
-
- return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-
- BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear )
- {
- BaseType_t xReturn;
-
- traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
- xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
-
- return xReturn;
- }
-
-#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
-{
- UBaseType_t uxSavedInterruptStatus;
- EventGroup_t const * const pxEventBits = xEventGroup;
- EventBits_t uxReturn;
-
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- uxReturn = pxEventBits->uxEventBits;
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
- return uxReturn;
-} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
-/*-----------------------------------------------------------*/
-
-EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet )
-{
- ListItem_t * pxListItem;
- ListItem_t * pxNext;
- ListItem_t const * pxListEnd;
- List_t const * pxList;
- EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
- EventGroup_t * pxEventBits = xEventGroup;
- BaseType_t xMatchFound = pdFALSE;
-
- /* Check the user is not attempting to set the bits used by the kernel
- * itself. */
- configASSERT( xEventGroup );
- configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
-
- pxList = &( pxEventBits->xTasksWaitingForBits );
- pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
- vTaskSuspendAll();
- {
- traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
-
- pxListItem = listGET_HEAD_ENTRY( pxList );
-
- /* Set the bits. */
- pxEventBits->uxEventBits |= uxBitsToSet;
-
- /* See if the new bit value should unblock any tasks. */
- while( pxListItem != pxListEnd )
- {
- pxNext = listGET_NEXT( pxListItem );
- uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
- xMatchFound = pdFALSE;
-
- /* Split the bits waited for from the control bits. */
- uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
- uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
-
- if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
- {
- /* Just looking for single bit being set. */
- if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+ if( xWaitForAllBits != pdFALSE )
{
+ uxControlBits |= eventWAIT_FOR_ALL_BITS;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Store the bits that the calling task is waiting for in the
+ * task's event list item so the kernel knows when a match is
+ * found. Then enter the blocked state. */
+ vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+ /* This is obsolete as it will get set after the task unblocks, but
+ * some compilers mistakenly generate a warning about the variable
+ * being returned without being set if it is not done. */
+ uxReturn = 0;
+
+ traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+ }
+ }
+ xAlreadyYielded = xTaskResumeAll();
+
+ if( xTicksToWait != ( TickType_t ) 0 )
+ {
+ if( xAlreadyYielded == pdFALSE )
+ {
+ taskYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The task blocked to wait for its required bits to be set - at this
+ * point either the required bits were set or the block time expired. If
+ * the required bits were set they will have been stored in the task's
+ * event list item, and they should now be retrieved then cleared. */
+ uxReturn = uxTaskResetEventItemValue();
+
+ if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* The task timed out, just return the current event bit value. */
+ uxReturn = pxEventBits->uxEventBits;
+
+ /* It is possible that the event bits were updated between this
+ * task leaving the Blocked state and running again. */
+ if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+ {
+ if( xClearOnExit != pdFALSE )
+ {
+ pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xTimeoutOccurred = pdTRUE;
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ /* The task unblocked because the bits were set. */
+ }
+
+ /* The task blocked so control bits may have been set. */
+ uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+ }
+
+ traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xTimeoutOccurred;
+
+ traceRETURN_xEventGroupWaitBits( uxReturn );
+
+ return uxReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear )
+ {
+ EventGroup_t * pxEventBits = xEventGroup;
+ EventBits_t uxReturn;
+
+ traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear );
+
+ /* Check the user is not attempting to clear the bits used by the kernel
+ * itself. */
+ configASSERT( xEventGroup );
+ configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+ taskENTER_CRITICAL();
+ {
+ traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+ /* The value returned is the event group value prior to the bits being
+ * cleared. */
+ uxReturn = pxEventBits->uxEventBits;
+
+ /* Clear the bits. */
+ pxEventBits->uxEventBits &= ~uxBitsToClear;
+ }
+ taskEXIT_CRITICAL();
+
+ traceRETURN_xEventGroupClearBits( uxReturn );
+
+ return uxReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+ BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear )
+ {
+ BaseType_t xReturn;
+
+ traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );
+
+ traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+ xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
+
+ traceRETURN_xEventGroupClearBitsFromISR( xReturn );
+
+ return xReturn;
+ }
+
+ #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+ {
+ UBaseType_t uxSavedInterruptStatus;
+ EventGroup_t const * const pxEventBits = xEventGroup;
+ EventBits_t uxReturn;
+
+ traceENTER_xEventGroupGetBitsFromISR( xEventGroup );
+
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+ {
+ uxReturn = pxEventBits->uxEventBits;
+ }
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xEventGroupGetBitsFromISR( uxReturn );
+
+ return uxReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet )
+ {
+ ListItem_t * pxListItem;
+ ListItem_t * pxNext;
+ ListItem_t const * pxListEnd;
+ List_t const * pxList;
+ EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits, uxReturnBits;
+ EventGroup_t * pxEventBits = xEventGroup;
+ BaseType_t xMatchFound = pdFALSE;
+
+ traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+ /* Check the user is not attempting to set the bits used by the kernel
+ * itself. */
+ configASSERT( xEventGroup );
+ configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+ pxList = &( pxEventBits->xTasksWaitingForBits );
+ pxListEnd = listGET_END_MARKER( pxList );
+ vTaskSuspendAll();
+ {
+ traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+ pxListItem = listGET_HEAD_ENTRY( pxList );
+
+ /* Set the bits. */
+ pxEventBits->uxEventBits |= uxBitsToSet;
+
+ /* See if the new bit value should unblock any tasks. */
+ while( pxListItem != pxListEnd )
+ {
+ pxNext = listGET_NEXT( pxListItem );
+ uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+ xMatchFound = pdFALSE;
+
+ /* Split the bits waited for from the control bits. */
+ uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+ uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+ if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+ {
+ /* Just looking for single bit being set. */
+ if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+ {
+ xMatchFound = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+ {
+ /* All bits are set. */
xMatchFound = pdTRUE;
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ /* Need all bits to be set, but not all the bits were set. */
}
- }
- else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
- {
- /* All bits are set. */
- xMatchFound = pdTRUE;
- }
- else
- {
- /* Need all bits to be set, but not all the bits were set. */
- }
- if( xMatchFound != pdFALSE )
- {
- /* The bits match. Should the bits be cleared on exit? */
- if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+ if( xMatchFound != pdFALSE )
{
- uxBitsToClear |= uxBitsWaitedFor;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
+ /* The bits match. Should the bits be cleared on exit? */
+ if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+ {
+ uxBitsToClear |= uxBitsWaitedFor;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Store the actual event flag value in the task's event list
+ * item before removing the task from the event list. The
+ * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+ * that is was unblocked due to its required bits matching, rather
+ * than because it timed out. */
+ vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
}
- /* Store the actual event flag value in the task's event list
- * item before removing the task from the event list. The
- * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
- * that is was unblocked due to its required bits matching, rather
- * than because it timed out. */
- vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+ /* Move onto the next list item. Note pxListItem->pxNext is not
+ * used here as the list item may have been removed from the event list
+ * and inserted into the ready/pending reading list. */
+ pxListItem = pxNext;
}
- /* Move onto the next list item. Note pxListItem->pxNext is not
- * used here as the list item may have been removed from the event list
- * and inserted into the ready/pending reading list. */
- pxListItem = pxNext;
+ /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+ * bit was set in the control word. */
+ pxEventBits->uxEventBits &= ~uxBitsToClear;
+
+ /* Snapshot resulting bits. */
+ uxReturnBits = pxEventBits->uxEventBits;
}
+ ( void ) xTaskResumeAll();
- /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
- * bit was set in the control word. */
- pxEventBits->uxEventBits &= ~uxBitsToClear;
+ traceRETURN_xEventGroupSetBits( uxReturnBits );
+
+ return uxReturnBits;
}
- ( void ) xTaskResumeAll();
-
- return pxEventBits->uxEventBits;
-}
/*-----------------------------------------------------------*/
-void vEventGroupDelete( EventGroupHandle_t xEventGroup )
-{
- EventGroup_t * pxEventBits = xEventGroup;
- const List_t * pxTasksWaitingForBits;
-
- configASSERT( pxEventBits );
-
- pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
-
- vTaskSuspendAll();
+ void vEventGroupDelete( EventGroupHandle_t xEventGroup )
{
- traceEVENT_GROUP_DELETE( xEventGroup );
-
- while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
- {
- /* Unblock the task, returning 0 as the event list is being deleted
- * and cannot therefore have any bits set. */
- configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
- vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
- }
- }
- ( void ) xTaskResumeAll();
-
- #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
- {
- /* The event group can only have been allocated dynamically - free
- * it again. */
- vPortFree( pxEventBits );
- }
- #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
- {
- /* The event group could have been allocated statically or
- * dynamically, so check before attempting to free the memory. */
- if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
- {
- vPortFree( pxEventBits );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-}
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
- StaticEventGroup_t ** ppxEventGroupBuffer )
- {
- BaseType_t xReturn;
EventGroup_t * pxEventBits = xEventGroup;
+ const List_t * pxTasksWaitingForBits;
+
+ traceENTER_vEventGroupDelete( xEventGroup );
configASSERT( pxEventBits );
- configASSERT( ppxEventGroupBuffer );
- #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+ vTaskSuspendAll();
{
- /* Check if the event group was statically allocated. */
- if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
+ traceEVENT_GROUP_DELETE( xEventGroup );
+
+ while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
{
- *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
- xReturn = pdTRUE;
+ /* Unblock the task, returning 0 as the event list is being deleted
+ * and cannot therefore have any bits set. */
+ configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+ vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+ }
+ }
+ ( void ) xTaskResumeAll();
+
+ #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+ {
+ /* The event group can only have been allocated dynamically - free
+ * it again. */
+ vPortFree( pxEventBits );
+ }
+ #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ {
+ /* The event group could have been allocated statically or
+ * dynamically, so check before attempting to free the memory. */
+ if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+ {
+ vPortFree( pxEventBits );
}
else
{
- xReturn = pdFALSE;
+ mtCOVERAGE_TEST_MARKER();
}
}
- #else /* configSUPPORT_DYNAMIC_ALLOCATION */
- {
- /* Event group must have been statically allocated. */
- *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
- xReturn = pdTRUE;
- }
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
- return xReturn;
+ traceRETURN_vEventGroupDelete();
}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
+ StaticEventGroup_t ** ppxEventGroupBuffer )
+ {
+ BaseType_t xReturn;
+ EventGroup_t * pxEventBits = xEventGroup;
+
+ traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer );
+
+ configASSERT( pxEventBits );
+ configASSERT( ppxEventGroupBuffer );
+
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* Check if the event group was statically allocated. */
+ if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
+ {
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ #else /* configSUPPORT_DYNAMIC_ALLOCATION */
+ {
+ /* Event group must have been statically allocated. */
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
+ xReturn = pdTRUE;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+ traceRETURN_xEventGroupGetStaticBuffer( xReturn );
+
+ return xReturn;
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
/* For internal use only - execute a 'set bits' command that was pended from
* an interrupt. */
-void vEventGroupSetBitsCallback( void * pvEventGroup,
- const uint32_t ulBitsToSet )
-{
- ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
-}
+ void vEventGroupSetBitsCallback( void * pvEventGroup,
+ uint32_t ulBitsToSet )
+ {
+ traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );
+
+ /* MISRA Ref 11.5.4 [Callback function parameter] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
+
+ traceRETURN_vEventGroupSetBitsCallback();
+ }
/*-----------------------------------------------------------*/
/* For internal use only - execute a 'clear bits' command that was pended from
* an interrupt. */
-void vEventGroupClearBitsCallback( void * pvEventGroup,
- const uint32_t ulBitsToClear )
-{
- ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
-}
+ void vEventGroupClearBitsCallback( void * pvEventGroup,
+ uint32_t ulBitsToClear )
+ {
+ traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );
+
+ /* MISRA Ref 11.5.4 [Callback function parameter] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
+
+ traceRETURN_vEventGroupClearBitsCallback();
+ }
/*-----------------------------------------------------------*/
-static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
- const EventBits_t uxBitsToWaitFor,
- const BaseType_t xWaitForAllBits )
-{
- BaseType_t xWaitConditionMet = pdFALSE;
-
- if( xWaitForAllBits == pdFALSE )
+ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xWaitForAllBits )
{
- /* Task only has to wait for one bit within uxBitsToWaitFor to be
- * set. Is one already set? */
- if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+ BaseType_t xWaitConditionMet = pdFALSE;
+
+ if( xWaitForAllBits == pdFALSE )
{
- xWaitConditionMet = pdTRUE;
+ /* Task only has to wait for one bit within uxBitsToWaitFor to be
+ * set. Is one already set? */
+ if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+ {
+ xWaitConditionMet = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+ * Are they set already? */
+ if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+ {
+ xWaitConditionMet = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- }
- else
- {
- /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
- * Are they set already? */
- if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
- {
- xWaitConditionMet = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- return xWaitConditionMet;
-}
+ return xWaitConditionMet;
+ }
/*-----------------------------------------------------------*/
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+ #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
- BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- BaseType_t * pxHigherPriorityTaskWoken )
- {
- BaseType_t xReturn;
-
- traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
- xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
-
- return xReturn;
- }
-
-#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
- {
- UBaseType_t xReturn;
- EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
-
- if( xEventGroup == NULL )
+ BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ BaseType_t * pxHigherPriorityTaskWoken )
{
- xReturn = 0;
- }
- else
- {
- xReturn = pxEventBits->uxEventGroupNumber;
+ BaseType_t xReturn;
+
+ traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );
+
+ traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+ xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
+
+ traceRETURN_xEventGroupSetBitsFromISR( xReturn );
+
+ return xReturn;
}
- return xReturn;
- }
-
-#endif /* configUSE_TRACE_FACILITY */
+ #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/
-#if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( configUSE_TRACE_FACILITY == 1 )
- void vEventGroupSetNumber( void * xEventGroup,
- UBaseType_t uxEventGroupNumber )
- {
- ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
- }
+ UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
+ {
+ UBaseType_t xReturn;
-#endif /* configUSE_TRACE_FACILITY */
+ /* MISRA Ref 11.5.2 [Opaque pointer] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup;
+
+ traceENTER_uxEventGroupGetNumber( xEventGroup );
+
+ if( xEventGroup == NULL )
+ {
+ xReturn = 0;
+ }
+ else
+ {
+ xReturn = pxEventBits->uxEventGroupNumber;
+ }
+
+ traceRETURN_uxEventGroupGetNumber( xReturn );
+
+ return xReturn;
+ }
+
+ #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vEventGroupSetNumber( void * xEventGroup,
+ UBaseType_t uxEventGroupNumber )
+ {
+ traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber );
+
+ /* MISRA Ref 11.5.2 [Opaque pointer] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;
+
+ traceRETURN_vEventGroupSetNumber();
+ }
+
+ #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+ * to include event groups functionality. If you want to include event groups
+ * then ensure configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_EVENT_GROUPS == 1 */
diff --git a/Source/include/FreeRTOS.h b/Source/include/FreeRTOS.h
index 4a19f93..75459a9 100644
--- a/Source/include/FreeRTOS.h
+++ b/Source/include/FreeRTOS.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -49,12 +49,6 @@
*/
#include <stdint.h> /* READ COMMENT ABOVE. */
-/* *INDENT-OFF* */
-#ifdef __cplusplus
- extern "C" {
-#endif
-/* *INDENT-ON* */
-
/* Acceptable values for configTICK_TYPE_WIDTH_IN_BITS. */
#define TICK_TYPE_WIDTH_16_BITS 0
#define TICK_TYPE_WIDTH_32_BITS 1
@@ -91,6 +85,22 @@
#define configENABLE_ACCESS_CONTROL_LIST 0
#endif
+/* Set default value of configNUMBER_OF_CORES to 1 to use single core FreeRTOS. */
+#ifndef configNUMBER_OF_CORES
+ #define configNUMBER_OF_CORES 1
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+ #define configUSE_MALLOC_FAILED_HOOK 0
+#endif
+
+#ifndef configASSERT
+ #define configASSERT( x )
+ #define configASSERT_DEFINED 0
+#else
+ #define configASSERT_DEFINED 1
+#endif
+
/* Basic FreeRTOS definitions. */
#include "projdefs.h"
@@ -120,6 +130,12 @@
#endif /* if ( configUSE_PICOLIBC_TLS == 1 ) */
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* *INDENT-ON* */
+
#ifndef configUSE_C_RUNTIME_TLS_SUPPORT
#define configUSE_C_RUNTIME_TLS_SUPPORT 0
#endif
@@ -169,6 +185,12 @@
#error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
#endif
+#if ( configNUMBER_OF_CORES > 1 )
+ #ifndef configUSE_PASSIVE_IDLE_HOOK
+ #error Missing definition: configUSE_PASSIVE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+ #endif
+#endif
+
#ifndef configUSE_TICK_HOOK
#error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
#endif
@@ -283,10 +305,6 @@
#endif
#endif
-#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
- #define configUSE_DAEMON_TASK_STARTUP_HOOK 0
-#endif
-
#ifndef configUSE_APPLICATION_TASK_TAG
#define configUSE_APPLICATION_TASK_TAG 0
#endif
@@ -307,10 +325,32 @@
#define configUSE_TIMERS 0
#endif
+#ifndef configUSE_EVENT_GROUPS
+ #define configUSE_EVENT_GROUPS 1
+#endif
+
+#ifndef configUSE_STREAM_BUFFERS
+ #define configUSE_STREAM_BUFFERS 1
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+ #define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+#endif
+
+#if ( configUSE_DAEMON_TASK_STARTUP_HOOK != 0 )
+ #if ( configUSE_TIMERS == 0 )
+ #error configUSE_DAEMON_TASK_STARTUP_HOOK is set, but the daemon task is not created because configUSE_TIMERS is 0.
+ #endif
+#endif
+
#ifndef configUSE_COUNTING_SEMAPHORES
#define configUSE_COUNTING_SEMAPHORES 0
#endif
+#ifndef configUSE_TASK_PREEMPTION_DISABLE
+ #define configUSE_TASK_PREEMPTION_DISABLE 0
+#endif
+
#ifndef configUSE_ALTERNATIVE_API
#define configUSE_ALTERNATIVE_API 0
#endif
@@ -331,13 +371,6 @@
#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
#endif
-#ifndef configASSERT
- #define configASSERT( x )
- #define configASSERT_DEFINED 0
-#else
- #define configASSERT_DEFINED 1
-#endif
-
/* configPRECONDITION should be defined as configASSERT.
* The CBMC proofs need a way to track assumptions and assertions.
* A configPRECONDITION statement should express an implicit invariant or
@@ -350,6 +383,17 @@
#define configPRECONDITION_DEFINED 1
#endif
+#ifndef configCHECK_HANDLER_INSTALLATION
+ #define configCHECK_HANDLER_INSTALLATION 1
+#else
+
+/* The application has explicitly defined configCHECK_HANDLER_INSTALLATION
+ * to 1. The checks requires configASSERT() to be defined. */
+ #if ( ( configCHECK_HANDLER_INSTALLATION == 1 ) && ( configASSERT_DEFINED == 0 ) )
+ #error You must define configASSERT() when configCHECK_HANDLER_INSTALLATION is 1.
+ #endif
+#endif
+
#ifndef portMEMORY_BARRIER
#define portMEMORY_BARRIER()
#endif
@@ -358,6 +402,116 @@
#define portSOFTWARE_BARRIER()
#endif
+#ifndef configRUN_MULTIPLE_PRIORITIES
+ #define configRUN_MULTIPLE_PRIORITIES 0
+#endif
+
+#ifndef portGET_CORE_ID
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define portGET_CORE_ID() 0
+ #else
+ #error configNUMBER_OF_CORES is set to more than 1 then portGET_CORE_ID must also be defined.
+ #endif /* configNUMBER_OF_CORES */
+
+#endif /* portGET_CORE_ID */
+
+#ifndef portYIELD_CORE
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define portYIELD_CORE( x ) portYIELD()
+ #else
+ #error configNUMBER_OF_CORES is set to more than 1 then portYIELD_CORE must also be defined.
+ #endif /* configNUMBER_OF_CORES */
+
+#endif /* portYIELD_CORE */
+
+#ifndef portSET_INTERRUPT_MASK
+
+ #if ( configNUMBER_OF_CORES > 1 )
+ #error portSET_INTERRUPT_MASK is required in SMP
+ #endif
+
+#endif /* portSET_INTERRUPT_MASK */
+
+#ifndef portCLEAR_INTERRUPT_MASK
+
+ #if ( configNUMBER_OF_CORES > 1 )
+ #error portCLEAR_INTERRUPT_MASK is required in SMP
+ #endif
+
+#endif /* portCLEAR_INTERRUPT_MASK */
+
+#ifndef portRELEASE_TASK_LOCK
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define portRELEASE_TASK_LOCK( xCoreID )
+ #else
+ #error portRELEASE_TASK_LOCK is required in SMP
+ #endif
+
+#endif /* portRELEASE_TASK_LOCK */
+
+#ifndef portGET_TASK_LOCK
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define portGET_TASK_LOCK( xCoreID )
+ #else
+ #error portGET_TASK_LOCK is required in SMP
+ #endif
+
+#endif /* portGET_TASK_LOCK */
+
+#ifndef portRELEASE_ISR_LOCK
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define portRELEASE_ISR_LOCK( xCoreID )
+ #else
+ #error portRELEASE_ISR_LOCK is required in SMP
+ #endif
+
+#endif /* portRELEASE_ISR_LOCK */
+
+#ifndef portGET_ISR_LOCK
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define portGET_ISR_LOCK( xCoreID )
+ #else
+ #error portGET_ISR_LOCK is required in SMP
+ #endif
+
+#endif /* portGET_ISR_LOCK */
+
+#ifndef portENTER_CRITICAL_FROM_ISR
+
+ #if ( configNUMBER_OF_CORES > 1 )
+ #error portENTER_CRITICAL_FROM_ISR is required in SMP
+ #endif
+
+#endif
+
+#ifndef portEXIT_CRITICAL_FROM_ISR
+
+ #if ( configNUMBER_OF_CORES > 1 )
+ #error portEXIT_CRITICAL_FROM_ISR is required in SMP
+ #endif
+
+#endif
+
+#ifndef configUSE_CORE_AFFINITY
+ #define configUSE_CORE_AFFINITY 0
+#endif /* configUSE_CORE_AFFINITY */
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ #ifndef configTASK_DEFAULT_CORE_AFFINITY
+ #define configTASK_DEFAULT_CORE_AFFINITY tskNO_AFFINITY
+ #endif
+#endif
+
+#ifndef configUSE_PASSIVE_IDLE_HOOK
+ #define configUSE_PASSIVE_IDLE_HOOK 0
+#endif /* configUSE_PASSIVE_IDLE_HOOK */
+
/* The timers module relies on xTaskGetSchedulerState(). */
#if configUSE_TIMERS == 1
@@ -373,14 +527,42 @@
#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
#endif /* configTIMER_TASK_STACK_DEPTH */
+ #ifndef portTIMER_CALLBACK_ATTRIBUTE
+ #define portTIMER_CALLBACK_ATTRIBUTE
+ #endif /* portTIMER_CALLBACK_ATTRIBUTE */
+
#endif /* configUSE_TIMERS */
+#ifndef portHAS_NESTED_INTERRUPTS
+ #if defined( portSET_INTERRUPT_MASK_FROM_ISR ) && defined( portCLEAR_INTERRUPT_MASK_FROM_ISR )
+ #define portHAS_NESTED_INTERRUPTS 1
+ #else
+ #define portHAS_NESTED_INTERRUPTS 0
+ #endif
+#endif
+
#ifndef portSET_INTERRUPT_MASK_FROM_ISR
- #define portSET_INTERRUPT_MASK_FROM_ISR() 0
+ #if ( portHAS_NESTED_INTERRUPTS == 1 )
+ #error portSET_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
+ #else
+ #define portSET_INTERRUPT_MASK_FROM_ISR() 0
+ #endif
+#else
+ #if ( portHAS_NESTED_INTERRUPTS == 0 )
+ #error portSET_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
+ #endif
#endif
#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) ( uxSavedStatusValue )
+ #if ( portHAS_NESTED_INTERRUPTS == 1 )
+ #error portCLEAR_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
+ #else
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) ( uxSavedStatusValue )
+ #endif
+#else
+ #if ( portHAS_NESTED_INTERRUPTS == 0 )
+ #error portCLEAR_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
+ #endif
#endif
#ifndef portCLEAN_UP_TCB
@@ -395,6 +577,10 @@
#define portSETUP_TCB( pxTCB ) ( void ) ( pxTCB )
#endif
+#ifndef portTASK_SWITCH_HOOK
+ #define portTASK_SWITCH_HOOK( pxTCB ) ( void ) ( pxTCB )
+#endif
+
#ifndef configQUEUE_REGISTRY_SIZE
#define configQUEUE_REGISTRY_SIZE 0U
#endif
@@ -435,6 +621,13 @@
#define traceTASK_SWITCHED_IN()
#endif
+#ifndef traceSTARTING_SCHEDULER
+
+/* Called after all idle tasks and timer task (if enabled) have been created
+ * successfully, just before the scheduler is started. */
+ #define traceSTARTING_SCHEDULER( xIdleTaskHandles )
+#endif
+
#ifndef traceINCREASE_TICK_COUNT
/* Called before stepping the tick count after waking from tickless idle
@@ -527,6 +720,14 @@
#define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
#endif
+#ifndef traceMOVED_TASK_TO_DELAYED_LIST
+ #define traceMOVED_TASK_TO_DELAYED_LIST()
+#endif
+
+#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST
+ #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST()
+#endif
+
#ifndef traceQUEUE_CREATE
#define traceQUEUE_CREATE( pxNewQueue )
#endif
@@ -775,16 +976,28 @@
#define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify )
#endif
+#ifndef traceISR_EXIT_TO_SCHEDULER
+ #define traceISR_EXIT_TO_SCHEDULER()
+#endif
+
+#ifndef traceISR_EXIT
+ #define traceISR_EXIT()
+#endif
+
+#ifndef traceISR_ENTER
+ #define traceISR_ENTER()
+#endif
+
#ifndef traceSTREAM_BUFFER_CREATE_FAILED
- #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+ #define traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType )
#endif
#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
- #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+ #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType )
#endif
#ifndef traceSTREAM_BUFFER_CREATE
- #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+ #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType )
#endif
#ifndef traceSTREAM_BUFFER_DELETE
@@ -795,6 +1008,10 @@
#define traceSTREAM_BUFFER_RESET( xStreamBuffer )
#endif
+#ifndef traceSTREAM_BUFFER_RESET_FROM_ISR
+ #define traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer )
+#endif
+
#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
#endif
@@ -827,6 +1044,1634 @@
#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
#endif
+#ifndef traceENTER_xEventGroupCreateStatic
+ #define traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer )
+#endif
+
+#ifndef traceRETURN_xEventGroupCreateStatic
+ #define traceRETURN_xEventGroupCreateStatic( pxEventBits )
+#endif
+
+#ifndef traceENTER_xEventGroupCreate
+ #define traceENTER_xEventGroupCreate()
+#endif
+
+#ifndef traceRETURN_xEventGroupCreate
+ #define traceRETURN_xEventGroupCreate( pxEventBits )
+#endif
+
+#ifndef traceENTER_xEventGroupSync
+ #define traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xEventGroupSync
+ #define traceRETURN_xEventGroupSync( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupWaitBits
+ #define traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xEventGroupWaitBits
+ #define traceRETURN_xEventGroupWaitBits( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupClearBits
+ #define traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceRETURN_xEventGroupClearBits
+ #define traceRETURN_xEventGroupClearBits( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupClearBitsFromISR
+ #define traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceRETURN_xEventGroupClearBitsFromISR
+ #define traceRETURN_xEventGroupClearBitsFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupGetBitsFromISR
+ #define traceENTER_xEventGroupGetBitsFromISR( xEventGroup )
+#endif
+
+#ifndef traceRETURN_xEventGroupGetBitsFromISR
+ #define traceRETURN_xEventGroupGetBitsFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_xEventGroupSetBits
+ #define traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceRETURN_xEventGroupSetBits
+ #define traceRETURN_xEventGroupSetBits( uxEventBits )
+#endif
+
+#ifndef traceENTER_vEventGroupDelete
+ #define traceENTER_vEventGroupDelete( xEventGroup )
+#endif
+
+#ifndef traceRETURN_vEventGroupDelete
+ #define traceRETURN_vEventGroupDelete()
+#endif
+
+#ifndef traceENTER_xEventGroupGetStaticBuffer
+ #define traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer )
+#endif
+
+#ifndef traceRETURN_xEventGroupGetStaticBuffer
+ #define traceRETURN_xEventGroupGetStaticBuffer( xReturn )
+#endif
+
+#ifndef traceENTER_vEventGroupSetBitsCallback
+ #define traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet )
+#endif
+
+#ifndef traceRETURN_vEventGroupSetBitsCallback
+ #define traceRETURN_vEventGroupSetBitsCallback()
+#endif
+
+#ifndef traceENTER_vEventGroupClearBitsCallback
+ #define traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear )
+#endif
+
+#ifndef traceRETURN_vEventGroupClearBitsCallback
+ #define traceRETURN_vEventGroupClearBitsCallback()
+#endif
+
+#ifndef traceENTER_xEventGroupSetBitsFromISR
+ #define traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xEventGroupSetBitsFromISR
+ #define traceRETURN_xEventGroupSetBitsFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxEventGroupGetNumber
+ #define traceENTER_uxEventGroupGetNumber( xEventGroup )
+#endif
+
+#ifndef traceRETURN_uxEventGroupGetNumber
+ #define traceRETURN_uxEventGroupGetNumber( xReturn )
+#endif
+
+#ifndef traceENTER_vEventGroupSetNumber
+ #define traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber )
+#endif
+
+#ifndef traceRETURN_vEventGroupSetNumber
+ #define traceRETURN_vEventGroupSetNumber()
+#endif
+
+#ifndef traceENTER_xQueueGenericReset
+ #define traceENTER_xQueueGenericReset( xQueue, xNewQueue )
+#endif
+
+#ifndef traceRETURN_xQueueGenericReset
+ #define traceRETURN_xQueueGenericReset( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericCreateStatic
+ #define traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueGenericCreateStatic
+ #define traceRETURN_xQueueGenericCreateStatic( pxNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueGenericGetStaticBuffers
+ #define traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueGenericGetStaticBuffers
+ #define traceRETURN_xQueueGenericGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericCreate
+ #define traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueGenericCreate
+ #define traceRETURN_xQueueGenericCreate( pxNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueCreateMutex
+ #define traceENTER_xQueueCreateMutex( ucQueueType )
+#endif
+
+#ifndef traceRETURN_xQueueCreateMutex
+ #define traceRETURN_xQueueCreateMutex( xNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueCreateMutexStatic
+ #define traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueCreateMutexStatic
+ #define traceRETURN_xQueueCreateMutexStatic( xNewQueue )
+#endif
+
+#ifndef traceENTER_xQueueGetMutexHolder
+ #define traceENTER_xQueueGetMutexHolder( xSemaphore )
+#endif
+
+#ifndef traceRETURN_xQueueGetMutexHolder
+ #define traceRETURN_xQueueGetMutexHolder( pxReturn )
+#endif
+
+#ifndef traceENTER_xQueueGetMutexHolderFromISR
+ #define traceENTER_xQueueGetMutexHolderFromISR( xSemaphore )
+#endif
+
+#ifndef traceRETURN_xQueueGetMutexHolderFromISR
+ #define traceRETURN_xQueueGetMutexHolderFromISR( pxReturn )
+#endif
+
+#ifndef traceENTER_xQueueGiveMutexRecursive
+ #define traceENTER_xQueueGiveMutexRecursive( xMutex )
+#endif
+
+#ifndef traceRETURN_xQueueGiveMutexRecursive
+ #define traceRETURN_xQueueGiveMutexRecursive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueTakeMutexRecursive
+ #define traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueTakeMutexRecursive
+ #define traceRETURN_xQueueTakeMutexRecursive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCreateCountingSemaphoreStatic
+ #define traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue )
+#endif
+
+#ifndef traceRETURN_xQueueCreateCountingSemaphoreStatic
+ #define traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle )
+#endif
+
+#ifndef traceENTER_xQueueCreateCountingSemaphore
+ #define traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount )
+#endif
+
+#ifndef traceRETURN_xQueueCreateCountingSemaphore
+ #define traceRETURN_xQueueCreateCountingSemaphore( xHandle )
+#endif
+
+#ifndef traceENTER_xQueueGenericSend
+ #define traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition )
+#endif
+
+#ifndef traceRETURN_xQueueGenericSend
+ #define traceRETURN_xQueueGenericSend( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGenericSendFromISR
+ #define traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition )
+#endif
+
+#ifndef traceRETURN_xQueueGenericSendFromISR
+ #define traceRETURN_xQueueGenericSendFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueGiveFromISR
+ #define traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xQueueGiveFromISR
+ #define traceRETURN_xQueueGiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueReceive
+ #define traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueReceive
+ #define traceRETURN_xQueueReceive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSemaphoreTake
+ #define traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueSemaphoreTake
+ #define traceRETURN_xQueueSemaphoreTake( xReturn )
+#endif
+
+#ifndef traceENTER_xQueuePeek
+ #define traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueuePeek
+ #define traceRETURN_xQueuePeek( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueReceiveFromISR
+ #define traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xQueueReceiveFromISR
+ #define traceRETURN_xQueueReceiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueuePeekFromISR
+ #define traceENTER_xQueuePeekFromISR( xQueue, pvBuffer )
+#endif
+
+#ifndef traceRETURN_xQueuePeekFromISR
+ #define traceRETURN_xQueuePeekFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxQueueMessagesWaiting
+ #define traceENTER_uxQueueMessagesWaiting( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueMessagesWaiting
+ #define traceRETURN_uxQueueMessagesWaiting( uxReturn )
+#endif
+
+#ifndef traceENTER_uxQueueSpacesAvailable
+ #define traceENTER_uxQueueSpacesAvailable( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueSpacesAvailable
+ #define traceRETURN_uxQueueSpacesAvailable( uxReturn )
+#endif
+
+#ifndef traceENTER_uxQueueMessagesWaitingFromISR
+ #define traceENTER_uxQueueMessagesWaitingFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueMessagesWaitingFromISR
+ #define traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_vQueueDelete
+ #define traceENTER_vQueueDelete( xQueue )
+#endif
+
+#ifndef traceRETURN_vQueueDelete
+ #define traceRETURN_vQueueDelete()
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueNumber
+ #define traceENTER_uxQueueGetQueueNumber( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueNumber
+ #define traceRETURN_uxQueueGetQueueNumber( uxQueueNumber )
+#endif
+
+#ifndef traceENTER_vQueueSetQueueNumber
+ #define traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber )
+#endif
+
+#ifndef traceRETURN_vQueueSetQueueNumber
+ #define traceRETURN_vQueueSetQueueNumber()
+#endif
+
+#ifndef traceENTER_ucQueueGetQueueType
+ #define traceENTER_ucQueueGetQueueType( xQueue )
+#endif
+
+#ifndef traceRETURN_ucQueueGetQueueType
+ #define traceRETURN_ucQueueGetQueueType( ucQueueType )
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueItemSize
+ #define traceENTER_uxQueueGetQueueItemSize( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueItemSize
+ #define traceRETURN_uxQueueGetQueueItemSize( uxItemSize )
+#endif
+
+#ifndef traceENTER_uxQueueGetQueueLength
+ #define traceENTER_uxQueueGetQueueLength( xQueue )
+#endif
+
+#ifndef traceRETURN_uxQueueGetQueueLength
+ #define traceRETURN_uxQueueGetQueueLength( uxLength )
+#endif
+
+#ifndef traceENTER_xQueueIsQueueEmptyFromISR
+ #define traceENTER_xQueueIsQueueEmptyFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_xQueueIsQueueEmptyFromISR
+ #define traceRETURN_xQueueIsQueueEmptyFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueIsQueueFullFromISR
+ #define traceENTER_xQueueIsQueueFullFromISR( xQueue )
+#endif
+
+#ifndef traceRETURN_xQueueIsQueueFullFromISR
+ #define traceRETURN_xQueueIsQueueFullFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRSend
+ #define traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueCRSend
+ #define traceRETURN_xQueueCRSend( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRReceive
+ #define traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueCRReceive
+ #define traceRETURN_xQueueCRReceive( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueCRSendFromISR
+ #define traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken )
+#endif
+
+#ifndef traceRETURN_xQueueCRSendFromISR
+ #define traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken )
+#endif
+
+#ifndef traceENTER_xQueueCRReceiveFromISR
+ #define traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken )
+#endif
+
+#ifndef traceRETURN_xQueueCRReceiveFromISR
+ #define traceRETURN_xQueueCRReceiveFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_vQueueAddToRegistry
+ #define traceENTER_vQueueAddToRegistry( xQueue, pcQueueName )
+#endif
+
+#ifndef traceRETURN_vQueueAddToRegistry
+ #define traceRETURN_vQueueAddToRegistry()
+#endif
+
+#ifndef traceENTER_pcQueueGetName
+ #define traceENTER_pcQueueGetName( xQueue )
+#endif
+
+#ifndef traceRETURN_pcQueueGetName
+ #define traceRETURN_pcQueueGetName( pcReturn )
+#endif
+
+#ifndef traceENTER_vQueueUnregisterQueue
+ #define traceENTER_vQueueUnregisterQueue( xQueue )
+#endif
+
+#ifndef traceRETURN_vQueueUnregisterQueue
+ #define traceRETURN_vQueueUnregisterQueue()
+#endif
+
+#ifndef traceENTER_vQueueWaitForMessageRestricted
+ #define traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely )
+#endif
+
+#ifndef traceRETURN_vQueueWaitForMessageRestricted
+ #define traceRETURN_vQueueWaitForMessageRestricted()
+#endif
+
+#ifndef traceENTER_xQueueCreateSet
+ #define traceENTER_xQueueCreateSet( uxEventQueueLength )
+#endif
+
+#ifndef traceRETURN_xQueueCreateSet
+ #define traceRETURN_xQueueCreateSet( pxQueue )
+#endif
+
+#ifndef traceENTER_xQueueCreateSetStatic
+ #define traceENTER_xQueueCreateSetStatic( uxEventQueueLength )
+#endif
+
+#ifndef traceRETURN_xQueueCreateSetStatic
+ #define traceRETURN_xQueueCreateSetStatic( pxQueue )
+#endif
+
+#ifndef traceENTER_xQueueAddToSet
+ #define traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueAddToSet
+ #define traceRETURN_xQueueAddToSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueRemoveFromSet
+ #define traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueRemoveFromSet
+ #define traceRETURN_xQueueRemoveFromSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSelectFromSet
+ #define traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xQueueSelectFromSet
+ #define traceRETURN_xQueueSelectFromSet( xReturn )
+#endif
+
+#ifndef traceENTER_xQueueSelectFromSetFromISR
+ #define traceENTER_xQueueSelectFromSetFromISR( xQueueSet )
+#endif
+
+#ifndef traceRETURN_xQueueSelectFromSetFromISR
+ #define traceRETURN_xQueueSelectFromSetFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerCreateTimerTask
+ #define traceENTER_xTimerCreateTimerTask()
+#endif
+
+#ifndef traceRETURN_xTimerCreateTimerTask
+ #define traceRETURN_xTimerCreateTimerTask( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerCreate
+ #define traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction )
+#endif
+
+#ifndef traceRETURN_xTimerCreate
+ #define traceRETURN_xTimerCreate( pxNewTimer )
+#endif
+
+#ifndef traceENTER_xTimerCreateStatic
+ #define traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer )
+#endif
+
+#ifndef traceRETURN_xTimerCreateStatic
+ #define traceRETURN_xTimerCreateStatic( pxNewTimer )
+#endif
+
+#ifndef traceENTER_xTimerGenericCommandFromTask
+ #define traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerGenericCommandFromTask
+ #define traceRETURN_xTimerGenericCommandFromTask( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGenericCommandFromISR
+ #define traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerGenericCommandFromISR
+ #define traceRETURN_xTimerGenericCommandFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetTimerDaemonTaskHandle
+ #define traceENTER_xTimerGetTimerDaemonTaskHandle()
+#endif
+
+#ifndef traceRETURN_xTimerGetTimerDaemonTaskHandle
+ #define traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle )
+#endif
+
+#ifndef traceENTER_xTimerGetPeriod
+ #define traceENTER_xTimerGetPeriod( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetPeriod
+ #define traceRETURN_xTimerGetPeriod( xTimerPeriodInTicks )
+#endif
+
+#ifndef traceENTER_vTimerSetReloadMode
+ #define traceENTER_vTimerSetReloadMode( xTimer, xAutoReload )
+#endif
+
+#ifndef traceRETURN_vTimerSetReloadMode
+ #define traceRETURN_vTimerSetReloadMode()
+#endif
+
+#ifndef traceENTER_xTimerGetReloadMode
+ #define traceENTER_xTimerGetReloadMode( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetReloadMode
+ #define traceRETURN_xTimerGetReloadMode( xReturn )
+#endif
+
+#ifndef traceENTER_uxTimerGetReloadMode
+ #define traceENTER_uxTimerGetReloadMode( xTimer )
+#endif
+
+#ifndef traceRETURN_uxTimerGetReloadMode
+ #define traceRETURN_uxTimerGetReloadMode( uxReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetExpiryTime
+ #define traceENTER_xTimerGetExpiryTime( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerGetExpiryTime
+ #define traceRETURN_xTimerGetExpiryTime( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerGetStaticBuffer
+ #define traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer )
+#endif
+
+#ifndef traceRETURN_xTimerGetStaticBuffer
+ #define traceRETURN_xTimerGetStaticBuffer( xReturn )
+#endif
+
+#ifndef traceENTER_pcTimerGetName
+ #define traceENTER_pcTimerGetName( xTimer )
+#endif
+
+#ifndef traceRETURN_pcTimerGetName
+ #define traceRETURN_pcTimerGetName( pcTimerName )
+#endif
+
+#ifndef traceENTER_xTimerIsTimerActive
+ #define traceENTER_xTimerIsTimerActive( xTimer )
+#endif
+
+#ifndef traceRETURN_xTimerIsTimerActive
+ #define traceRETURN_xTimerIsTimerActive( xReturn )
+#endif
+
+#ifndef traceENTER_pvTimerGetTimerID
+ #define traceENTER_pvTimerGetTimerID( xTimer )
+#endif
+
+#ifndef traceRETURN_pvTimerGetTimerID
+ #define traceRETURN_pvTimerGetTimerID( pvReturn )
+#endif
+
+#ifndef traceENTER_vTimerSetTimerID
+ #define traceENTER_vTimerSetTimerID( xTimer, pvNewID )
+#endif
+
+#ifndef traceRETURN_vTimerSetTimerID
+ #define traceRETURN_vTimerSetTimerID()
+#endif
+
+#ifndef traceENTER_xTimerPendFunctionCallFromISR
+ #define traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xTimerPendFunctionCallFromISR
+ #define traceRETURN_xTimerPendFunctionCallFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTimerPendFunctionCall
+ #define traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTimerPendFunctionCall
+ #define traceRETURN_xTimerPendFunctionCall( xReturn )
+#endif
+
+#ifndef traceENTER_uxTimerGetTimerNumber
+ #define traceENTER_uxTimerGetTimerNumber( xTimer )
+#endif
+
+#ifndef traceRETURN_uxTimerGetTimerNumber
+ #define traceRETURN_uxTimerGetTimerNumber( uxTimerNumber )
+#endif
+
+#ifndef traceENTER_vTimerSetTimerNumber
+ #define traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber )
+#endif
+
+#ifndef traceRETURN_vTimerSetTimerNumber
+ #define traceRETURN_vTimerSetTimerNumber()
+#endif
+
+#ifndef traceENTER_xTaskCreateStatic
+ #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer )
+#endif
+
+#ifndef traceRETURN_xTaskCreateStatic
+ #define traceRETURN_xTaskCreateStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateStaticAffinitySet
+ #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateStaticAffinitySet
+ #define traceRETURN_xTaskCreateStaticAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestrictedStatic
+ #define traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedStatic
+ #define traceRETURN_xTaskCreateRestrictedStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestrictedStaticAffinitySet
+ #define traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedStaticAffinitySet
+ #define traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestricted
+ #define traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestricted
+ #define traceRETURN_xTaskCreateRestricted( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateRestrictedAffinitySet
+ #define traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateRestrictedAffinitySet
+ #define traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreate
+ #define traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreate
+ #define traceRETURN_xTaskCreate( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCreateAffinitySet
+ #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask )
+#endif
+
+#ifndef traceRETURN_xTaskCreateAffinitySet
+ #define traceRETURN_xTaskCreateAffinitySet( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskDelete
+ #define traceENTER_vTaskDelete( xTaskToDelete )
+#endif
+
+#ifndef traceRETURN_vTaskDelete
+ #define traceRETURN_vTaskDelete()
+#endif
+
+#ifndef traceENTER_xTaskDelayUntil
+ #define traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )
+#endif
+
+#ifndef traceRETURN_xTaskDelayUntil
+ #define traceRETURN_xTaskDelayUntil( xShouldDelay )
+#endif
+
+#ifndef traceENTER_vTaskDelay
+ #define traceENTER_vTaskDelay( xTicksToDelay )
+#endif
+
+#ifndef traceRETURN_vTaskDelay
+ #define traceRETURN_vTaskDelay()
+#endif
+
+#ifndef traceENTER_eTaskGetState
+ #define traceENTER_eTaskGetState( xTask )
+#endif
+
+#ifndef traceRETURN_eTaskGetState
+ #define traceRETURN_eTaskGetState( eReturn )
+#endif
+
+#ifndef traceENTER_uxTaskPriorityGet
+ #define traceENTER_uxTaskPriorityGet( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskPriorityGet
+ #define traceRETURN_uxTaskPriorityGet( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskPriorityGetFromISR
+ #define traceENTER_uxTaskPriorityGetFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskPriorityGetFromISR
+ #define traceRETURN_uxTaskPriorityGetFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskBasePriorityGet
+ #define traceENTER_uxTaskBasePriorityGet( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskBasePriorityGet
+ #define traceRETURN_uxTaskBasePriorityGet( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskBasePriorityGetFromISR
+ #define traceENTER_uxTaskBasePriorityGetFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskBasePriorityGetFromISR
+ #define traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn )
+#endif
+
+#ifndef traceENTER_vTaskPrioritySet
+ #define traceENTER_vTaskPrioritySet( xTask, uxNewPriority )
+#endif
+
+#ifndef traceRETURN_vTaskPrioritySet
+ #define traceRETURN_vTaskPrioritySet()
+#endif
+
+#ifndef traceENTER_vTaskCoreAffinitySet
+ #define traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask )
+#endif
+
+#ifndef traceRETURN_vTaskCoreAffinitySet
+ #define traceRETURN_vTaskCoreAffinitySet()
+#endif
+
+#ifndef traceENTER_vTaskCoreAffinityGet
+ #define traceENTER_vTaskCoreAffinityGet( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskCoreAffinityGet
+ #define traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask )
+#endif
+
+#ifndef traceENTER_vTaskPreemptionDisable
+ #define traceENTER_vTaskPreemptionDisable( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskPreemptionDisable
+ #define traceRETURN_vTaskPreemptionDisable()
+#endif
+
+#ifndef traceENTER_vTaskPreemptionEnable
+ #define traceENTER_vTaskPreemptionEnable( xTask )
+#endif
+
+#ifndef traceRETURN_vTaskPreemptionEnable
+ #define traceRETURN_vTaskPreemptionEnable()
+#endif
+
+#ifndef traceENTER_vTaskSuspend
+ #define traceENTER_vTaskSuspend( xTaskToSuspend )
+#endif
+
+#ifndef traceRETURN_vTaskSuspend
+ #define traceRETURN_vTaskSuspend()
+#endif
+
+#ifndef traceENTER_vTaskResume
+ #define traceENTER_vTaskResume( xTaskToResume )
+#endif
+
+#ifndef traceRETURN_vTaskResume
+ #define traceRETURN_vTaskResume()
+#endif
+
+#ifndef traceENTER_xTaskResumeFromISR
+ #define traceENTER_xTaskResumeFromISR( xTaskToResume )
+#endif
+
+#ifndef traceRETURN_xTaskResumeFromISR
+ #define traceRETURN_xTaskResumeFromISR( xYieldRequired )
+#endif
+
+#ifndef traceENTER_vTaskStartScheduler
+ #define traceENTER_vTaskStartScheduler()
+#endif
+
+#ifndef traceRETURN_vTaskStartScheduler
+ #define traceRETURN_vTaskStartScheduler()
+#endif
+
+#ifndef traceENTER_vTaskEndScheduler
+ #define traceENTER_vTaskEndScheduler()
+#endif
+
+#ifndef traceRETURN_vTaskEndScheduler
+ #define traceRETURN_vTaskEndScheduler()
+#endif
+
+#ifndef traceENTER_vTaskSuspendAll
+ #define traceENTER_vTaskSuspendAll()
+#endif
+
+#ifndef traceRETURN_vTaskSuspendAll
+ #define traceRETURN_vTaskSuspendAll()
+#endif
+
+#ifndef traceENTER_xTaskResumeAll
+ #define traceENTER_xTaskResumeAll()
+#endif
+
+#ifndef traceRETURN_xTaskResumeAll
+ #define traceRETURN_xTaskResumeAll( xAlreadyYielded )
+#endif
+
+#ifndef traceENTER_xTaskGetTickCount
+ #define traceENTER_xTaskGetTickCount()
+#endif
+
+#ifndef traceRETURN_xTaskGetTickCount
+ #define traceRETURN_xTaskGetTickCount( xTicks )
+#endif
+
+#ifndef traceENTER_xTaskGetTickCountFromISR
+ #define traceENTER_xTaskGetTickCountFromISR()
+#endif
+
+#ifndef traceRETURN_xTaskGetTickCountFromISR
+ #define traceRETURN_xTaskGetTickCountFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetNumberOfTasks
+ #define traceENTER_uxTaskGetNumberOfTasks()
+#endif
+
+#ifndef traceRETURN_uxTaskGetNumberOfTasks
+ #define traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks )
+#endif
+
+#ifndef traceENTER_pcTaskGetName
+ #define traceENTER_pcTaskGetName( xTaskToQuery )
+#endif
+
+#ifndef traceRETURN_pcTaskGetName
+ #define traceRETURN_pcTaskGetName( pcTaskName )
+#endif
+
+#ifndef traceENTER_xTaskGetHandle
+ #define traceENTER_xTaskGetHandle( pcNameToQuery )
+#endif
+
+#ifndef traceRETURN_xTaskGetHandle
+ #define traceRETURN_xTaskGetHandle( pxTCB )
+#endif
+
+#ifndef traceENTER_xTaskGetStaticBuffers
+ #define traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer )
+#endif
+
+#ifndef traceRETURN_xTaskGetStaticBuffers
+ #define traceRETURN_xTaskGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetSystemState
+ #define traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime )
+#endif
+
+#ifndef traceRETURN_uxTaskGetSystemState
+ #define traceRETURN_uxTaskGetSystemState( uxTask )
+#endif
+
+#if ( configNUMBER_OF_CORES == 1 )
+ #ifndef traceENTER_xTaskGetIdleTaskHandle
+ #define traceENTER_xTaskGetIdleTaskHandle()
+ #endif
+#endif
+
+#if ( configNUMBER_OF_CORES == 1 )
+ #ifndef traceRETURN_xTaskGetIdleTaskHandle
+ #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle )
+ #endif
+#endif
+
+#ifndef traceENTER_xTaskGetIdleTaskHandleForCore
+ #define traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID )
+#endif
+
+#ifndef traceRETURN_xTaskGetIdleTaskHandleForCore
+ #define traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandle )
+#endif
+
+#ifndef traceENTER_vTaskStepTick
+ #define traceENTER_vTaskStepTick( xTicksToJump )
+#endif
+
+#ifndef traceRETURN_vTaskStepTick
+ #define traceRETURN_vTaskStepTick()
+#endif
+
+#ifndef traceENTER_xTaskCatchUpTicks
+ #define traceENTER_xTaskCatchUpTicks( xTicksToCatchUp )
+#endif
+
+#ifndef traceRETURN_xTaskCatchUpTicks
+ #define traceRETURN_xTaskCatchUpTicks( xYieldOccurred )
+#endif
+
+#ifndef traceENTER_xTaskAbortDelay
+ #define traceENTER_xTaskAbortDelay( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskAbortDelay
+ #define traceRETURN_xTaskAbortDelay( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskIncrementTick
+ #define traceENTER_xTaskIncrementTick()
+#endif
+
+#ifndef traceRETURN_xTaskIncrementTick
+ #define traceRETURN_xTaskIncrementTick( xSwitchRequired )
+#endif
+
+#ifndef traceENTER_vTaskSetApplicationTaskTag
+ #define traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction )
+#endif
+
+#ifndef traceRETURN_vTaskSetApplicationTaskTag
+ #define traceRETURN_vTaskSetApplicationTaskTag()
+#endif
+
+#ifndef traceENTER_xTaskGetApplicationTaskTag
+ #define traceENTER_xTaskGetApplicationTaskTag( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetApplicationTaskTag
+ #define traceRETURN_xTaskGetApplicationTaskTag( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetApplicationTaskTagFromISR
+ #define traceENTER_xTaskGetApplicationTaskTagFromISR( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetApplicationTaskTagFromISR
+ #define traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskCallApplicationTaskHook
+ #define traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter )
+#endif
+
+#ifndef traceRETURN_xTaskCallApplicationTaskHook
+ #define traceRETURN_xTaskCallApplicationTaskHook( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskSwitchContext
+ #define traceENTER_vTaskSwitchContext()
+#endif
+
+#ifndef traceRETURN_vTaskSwitchContext
+ #define traceRETURN_vTaskSwitchContext()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnEventList
+ #define traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnEventList
+ #define traceRETURN_vTaskPlaceOnEventList()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnUnorderedEventList
+ #define traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnUnorderedEventList
+ #define traceRETURN_vTaskPlaceOnUnorderedEventList()
+#endif
+
+#ifndef traceENTER_vTaskPlaceOnEventListRestricted
+ #define traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely )
+#endif
+
+#ifndef traceRETURN_vTaskPlaceOnEventListRestricted
+ #define traceRETURN_vTaskPlaceOnEventListRestricted()
+#endif
+
+#ifndef traceENTER_xTaskRemoveFromEventList
+ #define traceENTER_xTaskRemoveFromEventList( pxEventList )
+#endif
+
+#ifndef traceRETURN_xTaskRemoveFromEventList
+ #define traceRETURN_xTaskRemoveFromEventList( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskRemoveFromUnorderedEventList
+ #define traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue )
+#endif
+
+#ifndef traceRETURN_vTaskRemoveFromUnorderedEventList
+ #define traceRETURN_vTaskRemoveFromUnorderedEventList()
+#endif
+
+#ifndef traceENTER_vTaskSetTimeOutState
+ #define traceENTER_vTaskSetTimeOutState( pxTimeOut )
+#endif
+
+#ifndef traceRETURN_vTaskSetTimeOutState
+ #define traceRETURN_vTaskSetTimeOutState()
+#endif
+
+#ifndef traceENTER_vTaskInternalSetTimeOutState
+ #define traceENTER_vTaskInternalSetTimeOutState( pxTimeOut )
+#endif
+
+#ifndef traceRETURN_vTaskInternalSetTimeOutState
+ #define traceRETURN_vTaskInternalSetTimeOutState()
+#endif
+
+#ifndef traceENTER_xTaskCheckForTimeOut
+ #define traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTaskCheckForTimeOut
+ #define traceRETURN_xTaskCheckForTimeOut( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskMissedYield
+ #define traceENTER_vTaskMissedYield()
+#endif
+
+#ifndef traceRETURN_vTaskMissedYield
+ #define traceRETURN_vTaskMissedYield()
+#endif
+
+#ifndef traceENTER_uxTaskGetTaskNumber
+ #define traceENTER_uxTaskGetTaskNumber( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetTaskNumber
+ #define traceRETURN_uxTaskGetTaskNumber( uxReturn )
+#endif
+
+#ifndef traceENTER_vTaskSetTaskNumber
+ #define traceENTER_vTaskSetTaskNumber( xTask, uxHandle )
+#endif
+
+#ifndef traceRETURN_vTaskSetTaskNumber
+ #define traceRETURN_vTaskSetTaskNumber()
+#endif
+
+#ifndef traceENTER_eTaskConfirmSleepModeStatus
+ #define traceENTER_eTaskConfirmSleepModeStatus()
+#endif
+
+#ifndef traceRETURN_eTaskConfirmSleepModeStatus
+ #define traceRETURN_eTaskConfirmSleepModeStatus( eReturn )
+#endif
+
+#ifndef traceENTER_vTaskSetThreadLocalStoragePointer
+ #define traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue )
+#endif
+
+#ifndef traceRETURN_vTaskSetThreadLocalStoragePointer
+ #define traceRETURN_vTaskSetThreadLocalStoragePointer()
+#endif
+
+#ifndef traceENTER_pvTaskGetThreadLocalStoragePointer
+ #define traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex )
+#endif
+
+#ifndef traceRETURN_pvTaskGetThreadLocalStoragePointer
+ #define traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn )
+#endif
+
+#ifndef traceENTER_vTaskAllocateMPURegions
+ #define traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions )
+#endif
+
+#ifndef traceRETURN_vTaskAllocateMPURegions
+ #define traceRETURN_vTaskAllocateMPURegions()
+#endif
+
+#ifndef traceENTER_vTaskGetInfo
+ #define traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState )
+#endif
+
+#ifndef traceRETURN_vTaskGetInfo
+ #define traceRETURN_vTaskGetInfo()
+#endif
+
+#ifndef traceENTER_uxTaskGetStackHighWaterMark2
+ #define traceENTER_uxTaskGetStackHighWaterMark2( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetStackHighWaterMark2
+ #define traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn )
+#endif
+
+#ifndef traceENTER_uxTaskGetStackHighWaterMark
+ #define traceENTER_uxTaskGetStackHighWaterMark( xTask )
+#endif
+
+#ifndef traceRETURN_uxTaskGetStackHighWaterMark
+ #define traceRETURN_uxTaskGetStackHighWaterMark( uxReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetCurrentTaskHandle
+ #define traceENTER_xTaskGetCurrentTaskHandle()
+#endif
+
+#ifndef traceRETURN_xTaskGetCurrentTaskHandle
+ #define traceRETURN_xTaskGetCurrentTaskHandle( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetCurrentTaskHandleForCore
+ #define traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID )
+#endif
+
+#ifndef traceRETURN_xTaskGetCurrentTaskHandleForCore
+ #define traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetSchedulerState
+ #define traceENTER_xTaskGetSchedulerState()
+#endif
+
+#ifndef traceRETURN_xTaskGetSchedulerState
+ #define traceRETURN_xTaskGetSchedulerState( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskPriorityInherit
+ #define traceENTER_xTaskPriorityInherit( pxMutexHolder )
+#endif
+
+#ifndef traceRETURN_xTaskPriorityInherit
+ #define traceRETURN_xTaskPriorityInherit( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskPriorityDisinherit
+ #define traceENTER_xTaskPriorityDisinherit( pxMutexHolder )
+#endif
+
+#ifndef traceRETURN_xTaskPriorityDisinherit
+ #define traceRETURN_xTaskPriorityDisinherit( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskPriorityDisinheritAfterTimeout
+ #define traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask )
+#endif
+
+#ifndef traceRETURN_vTaskPriorityDisinheritAfterTimeout
+ #define traceRETURN_vTaskPriorityDisinheritAfterTimeout()
+#endif
+
+#ifndef traceENTER_vTaskYieldWithinAPI
+ #define traceENTER_vTaskYieldWithinAPI()
+#endif
+
+#ifndef traceRETURN_vTaskYieldWithinAPI
+ #define traceRETURN_vTaskYieldWithinAPI()
+#endif
+
+#ifndef traceENTER_vTaskEnterCritical
+ #define traceENTER_vTaskEnterCritical()
+#endif
+
+#ifndef traceRETURN_vTaskEnterCritical
+ #define traceRETURN_vTaskEnterCritical()
+#endif
+
+#ifndef traceENTER_vTaskEnterCriticalFromISR
+ #define traceENTER_vTaskEnterCriticalFromISR()
+#endif
+
+#ifndef traceRETURN_vTaskEnterCriticalFromISR
+ #define traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus )
+#endif
+
+#ifndef traceENTER_vTaskExitCritical
+ #define traceENTER_vTaskExitCritical()
+#endif
+
+#ifndef traceRETURN_vTaskExitCritical
+ #define traceRETURN_vTaskExitCritical()
+#endif
+
+#ifndef traceENTER_vTaskExitCriticalFromISR
+ #define traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus )
+#endif
+
+#ifndef traceRETURN_vTaskExitCriticalFromISR
+ #define traceRETURN_vTaskExitCriticalFromISR()
+#endif
+
+#ifndef traceENTER_vTaskListTasks
+ #define traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength )
+#endif
+
+#ifndef traceRETURN_vTaskListTasks
+ #define traceRETURN_vTaskListTasks()
+#endif
+
+#ifndef traceENTER_vTaskGetRunTimeStatistics
+ #define traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength )
+#endif
+
+#ifndef traceRETURN_vTaskGetRunTimeStatistics
+ #define traceRETURN_vTaskGetRunTimeStatistics()
+#endif
+
+#ifndef traceENTER_uxTaskResetEventItemValue
+ #define traceENTER_uxTaskResetEventItemValue()
+#endif
+
+#ifndef traceRETURN_uxTaskResetEventItemValue
+ #define traceRETURN_uxTaskResetEventItemValue( uxReturn )
+#endif
+
+#ifndef traceENTER_pvTaskIncrementMutexHeldCount
+ #define traceENTER_pvTaskIncrementMutexHeldCount()
+#endif
+
+#ifndef traceRETURN_pvTaskIncrementMutexHeldCount
+ #define traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB )
+#endif
+
+#ifndef traceENTER_ulTaskGenericNotifyTake
+ #define traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_ulTaskGenericNotifyTake
+ #define traceRETURN_ulTaskGenericNotifyTake( ulReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyWait
+ #define traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyWait
+ #define traceRETURN_xTaskGenericNotifyWait( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotify
+ #define traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotify
+ #define traceRETURN_xTaskGenericNotify( xReturn )
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyFromISR
+ #define traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyFromISR
+ #define traceRETURN_xTaskGenericNotifyFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_vTaskGenericNotifyGiveFromISR
+ #define traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_vTaskGenericNotifyGiveFromISR
+ #define traceRETURN_vTaskGenericNotifyGiveFromISR()
+#endif
+
+#ifndef traceENTER_xTaskGenericNotifyStateClear
+ #define traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear )
+#endif
+
+#ifndef traceRETURN_xTaskGenericNotifyStateClear
+ #define traceRETURN_xTaskGenericNotifyStateClear( xReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGenericNotifyValueClear
+ #define traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear )
+#endif
+
+#ifndef traceRETURN_ulTaskGenericNotifyValueClear
+ #define traceRETURN_ulTaskGenericNotifyValueClear( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetRunTimeCounter
+ #define traceENTER_ulTaskGetRunTimeCounter( xTask )
+#endif
+
+#ifndef traceRETURN_ulTaskGetRunTimeCounter
+ #define traceRETURN_ulTaskGetRunTimeCounter( ulRunTimeCounter )
+#endif
+
+#ifndef traceENTER_ulTaskGetRunTimePercent
+ #define traceENTER_ulTaskGetRunTimePercent( xTask )
+#endif
+
+#ifndef traceRETURN_ulTaskGetRunTimePercent
+ #define traceRETURN_ulTaskGetRunTimePercent( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetIdleRunTimeCounter
+ #define traceENTER_ulTaskGetIdleRunTimeCounter()
+#endif
+
+#ifndef traceRETURN_ulTaskGetIdleRunTimeCounter
+ #define traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn )
+#endif
+
+#ifndef traceENTER_ulTaskGetIdleRunTimePercent
+ #define traceENTER_ulTaskGetIdleRunTimePercent()
+#endif
+
+#ifndef traceRETURN_ulTaskGetIdleRunTimePercent
+ #define traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn )
+#endif
+
+#ifndef traceENTER_xTaskGetMPUSettings
+ #define traceENTER_xTaskGetMPUSettings( xTask )
+#endif
+
+#ifndef traceRETURN_xTaskGetMPUSettings
+ #define traceRETURN_xTaskGetMPUSettings( xMPUSettings )
+#endif
+
+#ifndef traceENTER_xStreamBufferGenericCreate
+ #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGenericCreate
+ #define traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory )
+#endif
+
+#ifndef traceENTER_xStreamBufferGenericCreateStatic
+ #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGenericCreateStatic
+ #define traceRETURN_xStreamBufferGenericCreateStatic( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferGetStaticBuffers
+ #define traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferGetStaticBuffers
+ #define traceRETURN_xStreamBufferGetStaticBuffers( xReturn )
+#endif
+
+#ifndef traceENTER_vStreamBufferDelete
+ #define traceENTER_vStreamBufferDelete( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_vStreamBufferDelete
+ #define traceRETURN_vStreamBufferDelete()
+#endif
+
+#ifndef traceENTER_xStreamBufferReset
+ #define traceENTER_xStreamBufferReset( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReset
+ #define traceRETURN_xStreamBufferReset( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferResetFromISR
+ #define traceENTER_xStreamBufferResetFromISR( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferResetFromISR
+ #define traceRETURN_xStreamBufferResetFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSetTriggerLevel
+ #define traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSetTriggerLevel
+ #define traceRETURN_xStreamBufferSetTriggerLevel( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSpacesAvailable
+ #define traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSpacesAvailable
+ #define traceRETURN_xStreamBufferSpacesAvailable( xSpace )
+#endif
+
+#ifndef traceENTER_xStreamBufferBytesAvailable
+ #define traceENTER_xStreamBufferBytesAvailable( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferBytesAvailable
+ #define traceRETURN_xStreamBufferBytesAvailable( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSend
+ #define traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSend
+ #define traceRETURN_xStreamBufferSend( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSendFromISR
+ #define traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSendFromISR
+ #define traceRETURN_xStreamBufferSendFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceive
+ #define traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceive
+ #define traceRETURN_xStreamBufferReceive( xReceivedLength )
+#endif
+
+#ifndef traceENTER_xStreamBufferNextMessageLengthBytes
+ #define traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferNextMessageLengthBytes
+ #define traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceiveFromISR
+ #define traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceiveFromISR
+ #define traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength )
+#endif
+
+#ifndef traceENTER_xStreamBufferIsEmpty
+ #define traceENTER_xStreamBufferIsEmpty( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferIsEmpty
+ #define traceRETURN_xStreamBufferIsEmpty( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferIsFull
+ #define traceENTER_xStreamBufferIsFull( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_xStreamBufferIsFull
+ #define traceRETURN_xStreamBufferIsFull( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferSendCompletedFromISR
+ #define traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferSendCompletedFromISR
+ #define traceRETURN_xStreamBufferSendCompletedFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_xStreamBufferReceiveCompletedFromISR
+ #define traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
+#endif
+
+#ifndef traceRETURN_xStreamBufferReceiveCompletedFromISR
+ #define traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn )
+#endif
+
+#ifndef traceENTER_uxStreamBufferGetStreamBufferNotificationIndex
+ #define traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex
+ #define traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( uxNotificationIndex )
+#endif
+
+#ifndef traceENTER_vStreamBufferSetStreamBufferNotificationIndex
+ #define traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex )
+#endif
+
+#ifndef traceRETURN_vStreamBufferSetStreamBufferNotificationIndex
+ #define traceRETURN_vStreamBufferSetStreamBufferNotificationIndex()
+#endif
+
+#ifndef traceENTER_uxStreamBufferGetStreamBufferNumber
+ #define traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_uxStreamBufferGetStreamBufferNumber
+ #define traceRETURN_uxStreamBufferGetStreamBufferNumber( uxStreamBufferNumber )
+#endif
+
+#ifndef traceENTER_vStreamBufferSetStreamBufferNumber
+ #define traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber )
+#endif
+
+#ifndef traceRETURN_vStreamBufferSetStreamBufferNumber
+ #define traceRETURN_vStreamBufferSetStreamBufferNumber()
+#endif
+
+#ifndef traceENTER_ucStreamBufferGetStreamBufferType
+ #define traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer )
+#endif
+
+#ifndef traceRETURN_ucStreamBufferGetStreamBufferType
+ #define traceRETURN_ucStreamBufferGetStreamBufferType( ucStreamBufferType )
+#endif
+
+#ifndef traceENTER_vListInitialise
+ #define traceENTER_vListInitialise( pxList )
+#endif
+
+#ifndef traceRETURN_vListInitialise
+ #define traceRETURN_vListInitialise()
+#endif
+
+#ifndef traceENTER_vListInitialiseItem
+ #define traceENTER_vListInitialiseItem( pxItem )
+#endif
+
+#ifndef traceRETURN_vListInitialiseItem
+ #define traceRETURN_vListInitialiseItem()
+#endif
+
+#ifndef traceENTER_vListInsertEnd
+ #define traceENTER_vListInsertEnd( pxList, pxNewListItem )
+#endif
+
+#ifndef traceRETURN_vListInsertEnd
+ #define traceRETURN_vListInsertEnd()
+#endif
+
+#ifndef traceENTER_vListInsert
+ #define traceENTER_vListInsert( pxList, pxNewListItem )
+#endif
+
+#ifndef traceRETURN_vListInsert
+ #define traceRETURN_vListInsert()
+#endif
+
+#ifndef traceENTER_uxListRemove
+ #define traceENTER_uxListRemove( pxItemToRemove )
+#endif
+
+#ifndef traceRETURN_uxListRemove
+ #define traceRETURN_uxListRemove( uxNumberOfItems )
+#endif
+
+#ifndef traceENTER_xCoRoutineCreate
+ #define traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex )
+#endif
+
+#ifndef traceRETURN_xCoRoutineCreate
+ #define traceRETURN_xCoRoutineCreate( xReturn )
+#endif
+
+#ifndef traceENTER_vCoRoutineAddToDelayedList
+ #define traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList )
+#endif
+
+#ifndef traceRETURN_vCoRoutineAddToDelayedList
+ #define traceRETURN_vCoRoutineAddToDelayedList()
+#endif
+
+#ifndef traceENTER_vCoRoutineSchedule
+ #define traceENTER_vCoRoutineSchedule()
+#endif
+
+#ifndef traceRETURN_vCoRoutineSchedule
+ #define traceRETURN_vCoRoutineSchedule()
+#endif
+
+#ifndef traceENTER_xCoRoutineRemoveFromEventList
+ #define traceENTER_xCoRoutineRemoveFromEventList( pxEventList )
+#endif
+
+#ifndef traceRETURN_xCoRoutineRemoveFromEventList
+ #define traceRETURN_xCoRoutineRemoveFromEventList( xReturn )
+#endif
+
#ifndef configGENERATE_RUN_TIME_STATS
#define configGENERATE_RUN_TIME_STATS 0
#endif
@@ -849,10 +2694,6 @@
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#endif
-#ifndef configUSE_MALLOC_FAILED_HOOK
- #define configUSE_MALLOC_FAILED_HOOK 0
-#endif
-
#ifndef portPRIVILEGE_BIT
#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
#endif
@@ -945,6 +2786,10 @@
#define configAPPLICATION_ALLOCATED_HEAP 0
#endif
+#ifndef configENABLE_HEAP_PROTECTOR
+ #define configENABLE_HEAP_PROTECTOR 0
+#endif
+
#ifndef configUSE_TASK_NOTIFICATIONS
#define configUSE_TASK_NOTIFICATIONS 1
#endif
@@ -976,6 +2821,10 @@
#define configSUPPORT_STATIC_ALLOCATION 0
#endif
+#ifndef configKERNEL_PROVIDED_STATIC_MEMORY
+ #define configKERNEL_PROVIDED_STATIC_MEMORY 0
+#endif
+
#ifndef configSUPPORT_DYNAMIC_ALLOCATION
/* Defaults to 1 for backward compatibility. */
#define configSUPPORT_DYNAMIC_ALLOCATION 1
@@ -991,11 +2840,15 @@
#endif
#endif
+#ifndef configSTATS_BUFFER_MAX_LENGTH
+ #define configSTATS_BUFFER_MAX_LENGTH 0xFFFF
+#endif
+
#ifndef configSTACK_DEPTH_TYPE
-/* Defaults to uint16_t for backward compatibility, but can be overridden
- * in FreeRTOSConfig.h if uint16_t is too restrictive. */
- #define configSTACK_DEPTH_TYPE uint16_t
+/* Defaults to StackType_t for backward compatibility, but can be overridden
+ * in FreeRTOSConfig.h if StackType_t is too restrictive. */
+ #define configSTACK_DEPTH_TYPE StackType_t
#endif
#ifndef configRUN_TIME_COUNTER_TYPE
@@ -1023,6 +2876,26 @@
#error configUSE_MUTEXES must be set to 1 to use recursive mutexes
#endif
+#if ( ( configRUN_MULTIPLE_PRIORITIES == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+ #error configRUN_MULTIPLE_PRIORITIES must be set to 1 to use task preemption disable
+#endif
+
+#if ( ( configUSE_PREEMPTION == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+ #error configUSE_PREEMPTION must be set to 1 to use task preemption disable
+#endif
+
+#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
+ #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS
+#endif
+
+#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_CORE_AFFINITY != 0 ) )
+ #error configUSE_CORE_AFFINITY is not supported in single core FreeRTOS
+#endif
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PORT_OPTIMISED_TASK_SELECTION != 0 ) )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION is not supported in SMP FreeRTOS
+#endif
+
#ifndef configINITIAL_TICK_COUNT
#define configINITIAL_TICK_COUNT 0
#endif
@@ -1161,6 +3034,21 @@
#define configRUN_ADDITIONAL_TESTS 0
#endif
+/* The following config allows infinite loop control. For example, control the
+ * infinite loop in idle task function when performing unit tests. */
+#ifndef configCONTROL_INFINITE_LOOP
+ #define configCONTROL_INFINITE_LOOP()
+#endif
+
+/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
+ * support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
+#ifndef configENABLE_PAC
+ #define configENABLE_PAC 0
+#endif
+
+#ifndef configENABLE_BTI
+ #define configENABLE_BTI 0
+#endif
/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
* dynamically allocated RAM, in which case when any task is deleted it is known
@@ -1279,10 +3167,20 @@
#if ( portUSING_MPU_WRAPPERS == 1 )
xMPU_SETTINGS xDummy2;
#endif
+ #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+ UBaseType_t uxDummy26;
+ #endif
StaticListItem_t xDummy3[ 2 ];
UBaseType_t uxDummy5;
void * pxDummy6;
+ #if ( configNUMBER_OF_CORES > 1 )
+ BaseType_t xDummy23;
+ UBaseType_t uxDummy24;
+ #endif
uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];
+ #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+ BaseType_t xDummy25;
+ #endif
#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
void * pxDummy8;
#endif
@@ -1446,6 +3344,7 @@
#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
void * pvDummy5[ 2 ];
#endif
+ UBaseType_t uxDummy6;
} StaticStreamBuffer_t;
/* Message buffers are built on stream buffers. */
diff --git a/Source/include/FreeRTOSConfig_template.h b/Source/include/FreeRTOSConfig_template.h
index e34e976..4df0001 100644
--- a/Source/include/FreeRTOSConfig_template.h
+++ b/Source/include/FreeRTOSConfig_template.h
@@ -1,184 +1,665 @@
/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
+ * SPDX-License-Identifier: MIT
*
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
+/*******************************************************************************
+ * This file provides an example FreeRTOSConfig.h header file, inclusive of an
+ * abbreviated explanation of each configuration item. Online and reference
+ * documentation provides more information.
+ * https://www.freertos.org/a00110.html
+ *
+ * Constant values enclosed in square brackets ('[' and ']') must be completed
+ * before this file will build.
+ *
+ * Use the FreeRTOSConfig.h supplied with the RTOS port in use rather than this
+ * generic file, if one is available.
+ ******************************************************************************/
+
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
-/*-----------------------------------------------------------
- * this is a template configuration files
+/******************************************************************************/
+/* Hardware description related definitions. **********************************/
+/******************************************************************************/
+
+/* In most cases, configCPU_CLOCK_HZ must be set to the frequency of the clock
+ * that drives the peripheral used to generate the kernels periodic tick
+ * interrupt. The default value is set to 20MHz and matches the QEMU demo
+ * settings. Your application will certainly need a different value so set this
+ * correctly. This is very often, but not always, equal to the main system clock
+ * frequency. */
+#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 )
+
+/* configSYSTICK_CLOCK_HZ is an optional parameter for ARM Cortex-M ports only.
*
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
+ * By default ARM Cortex-M ports generate the RTOS tick interrupt from the
+ * Cortex-M SysTick timer. Most Cortex-M MCUs run the SysTick timer at the same
+ * frequency as the MCU itself - when that is the case configSYSTICK_CLOCK_HZ is
+ * not needed and should be left undefined. If the SysTick timer is clocked at a
+ * different frequency to the MCU core then set configCPU_CLOCK_HZ to the MCU
+ * clock frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock
+ * frequency. Not used if left undefined.
+ * The default value is undefined (commented out). If you need this value bring
+ * it back and set it to a suitable value. */
+
+/*
+ #define configSYSTICK_CLOCK_HZ [Platform specific]
+ */
+
+/******************************************************************************/
+/* Scheduling behaviour related definitions. **********************************/
+/******************************************************************************/
+
+/* configTICK_RATE_HZ sets frequency of the tick interrupt in Hz, normally
+ * calculated from the configCPU_CLOCK_HZ value. */
+#define configTICK_RATE_HZ 100
+
+/* Set configUSE_PREEMPTION to 1 to use pre-emptive scheduling. Set
+ * configUSE_PREEMPTION to 0 to use co-operative scheduling.
+ * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html. */
+#define configUSE_PREEMPTION 1
+
+/* Set configUSE_TIME_SLICING to 1 to have the scheduler switch between Ready
+ * state tasks of equal priority on every tick interrupt. Set
+ * configUSE_TIME_SLICING to 0 to prevent the scheduler switching between Ready
+ * state tasks just because there was a tick interrupt. See
+ * https://freertos.org/single-core-amp-smp-rtos-scheduling.html. */
+#define configUSE_TIME_SLICING 0
+
+/* Set configUSE_PORT_OPTIMISED_TASK_SELECTION to 1 to select the next task to
+ * run using an algorithm optimised to the instruction set of the target
+ * hardware - normally using a count leading zeros assembly instruction. Set to
+ * 0 to select the next task to run using a generic C algorithm that works for
+ * all FreeRTOS ports. Not all FreeRTOS ports have this option. Defaults to 0
+ * if left undefined. */
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+
+/* Set configUSE_TICKLESS_IDLE to 1 to use the low power tickless mode. Set to
+ * 0 to keep the tick interrupt running at all times. Not all FreeRTOS ports
+ * support tickless mode. See
+ * https://www.freertos.org/low-power-tickless-rtos.html Defaults to 0 if left
+ * undefined. */
+#define configUSE_TICKLESS_IDLE 0
+
+/* configMAX_PRIORITIES Sets the number of available task priorities. Tasks can
+ * be assigned priorities of 0 to (configMAX_PRIORITIES - 1). Zero is the
+ * lowest priority. */
+#define configMAX_PRIORITIES 5
+
+/* configMINIMAL_STACK_SIZE defines the size of the stack used by the Idle task
+ * (in words, not in bytes!). The kernel does not use this constant for any
+ * other purpose. Demo applications use the constant to make the demos somewhat
+ * portable across hardware architectures. */
+#define configMINIMAL_STACK_SIZE 128
+
+/* configMAX_TASK_NAME_LEN sets the maximum length (in characters) of a task's
+ * human readable name. Includes the NULL terminator. */
+#define configMAX_TASK_NAME_LEN 16
+
+/* Time is measured in 'ticks' - which is the number of times the tick interrupt
+ * has executed since the RTOS kernel was started.
+ * The tick count is held in a variable of type TickType_t.
*
- * These parameters and more are described within the 'configuration' section of the
- * FreeRTOS API documentation available on the FreeRTOS.org web site.
+ * configTICK_TYPE_WIDTH_IN_BITS controls the type (and therefore bit-width) of
+ * TickType_t:
*
- * See http://www.freertos.org/a00110.html
- *----------------------------------------------------------*/
-
-/* Ensure stdint is only used by the compiler, and not the assembler. */
-#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
- #include <stdint.h>
- extern uint32_t SystemCoreClock;
-#endif
-
-/*-------------------- specific defines -------------------*/
-#ifndef CMSIS_device_header
-#define CMSIS_device_header "stm32XXxx.h"
-#endif /* CMSIS_device_header */
-
- /* If No secure feature is used the configENABLE_TRUSTZONE should be set to 0
- *
- */
-#define configENABLE_TRUSTZONE 0
-#define configENABLE_FPU 1
-#define configENABLE_MPU 0
-
-/*-----------------------------------------------------------------*/
-
-#define configUSE_PREEMPTION 1
-#define configUSE_IDLE_HOOK 0
-#define configUSE_TICK_HOOK 0
-#define configMAX_PRIORITIES (7)
-#define configCPU_CLOCK_HZ (SystemCoreClock)
-#define configTICK_RATE_HZ ((TickType_t)1000)
-#define configMINIMAL_STACK_SIZE ((uint16_t)128)
-#define configTOTAL_HEAP_SIZE ((size_t)(15 * 1024))
-#define configMAX_TASK_NAME_LEN (16)
-#define configUSE_TRACE_FACILITY 1
-#define configUSE_16_BIT_TICKS 0
-#define configIDLE_SHOULD_YIELD 1
-#define configUSE_MUTEXES 1
-#define configQUEUE_REGISTRY_SIZE 8
-#define configCHECK_FOR_STACK_OVERFLOW 0
-#define configUSE_RECURSIVE_MUTEXES 1
-#define configUSE_MALLOC_FAILED_HOOK 0
-#define configUSE_APPLICATION_TASK_TAG 0
-#define configUSE_COUNTING_SEMAPHORES 1
-#define configGENERATE_RUN_TIME_STATS 0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 0
-#define configMAX_CO_ROUTINE_PRIORITIES (2)
-
-/* Software timer definitions. */
-#define configUSE_TIMERS 1
-#define configTIMER_TASK_PRIORITY (2)
-#define configTIMER_QUEUE_LENGTH 10
-#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
-
-/* ARMv8-M secure side port related definitions. */
-/* #define secureconfigMAX_SECURE_CONTEXTS 5 */
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-#define INCLUDE_vTaskPrioritySet 1
-#define INCLUDE_uxTaskPriorityGet 1
-#define INCLUDE_vTaskDelete 1
-#define INCLUDE_vTaskCleanUpResources 1
-#define INCLUDE_vTaskSuspend 1
-#define INCLUDE_xTaskDelayUntil 0
-#define INCLUDE_vTaskDelay 1
-#define INCLUDE_xTaskGetSchedulerState 1
-
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_xQueueGetMutexHolder 1
-#define INCLUDE_eTaskGetState 1
-#define INCLUDE_uxTaskGetStackHighWaterMark 1
-#define INCLUDE_xTimerPendFunctionCall 1
-#define INCLUDE_xTaskGetCurrentTaskHandle 1
-
-/*------------- CMSIS-RTOS V2 specific defines -----------*/
-/* When using CMSIS-RTOSv2 set configSUPPORT_STATIC_ALLOCATION to 1
- * is mandatory to avoid compile errors.
- * CMSIS-RTOS V2 implmentation requires the following defines
-*/
-#define configSUPPORT_STATIC_ALLOCATION 1 /* cmsis_os threads are created using xTaskCreateStatic() API */
-#define configMAX_PRIORITIES (56) /* Priority range in CMSIS-RTOS V2 is [0 .. 56] */
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 /* when set to 1, configMAX_PRIORITIES can't be more than 32 which is not suitable for the new CMSIS-RTOS v2 priority range */
-
-
-/* the CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
- * by the application thus the correct define need to be enabled from the list
- * below
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_16_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 16-bit type.
*
-//define USE_FreeRTOS_HEAP_1
-//define USE_FreeRTOS_HEAP_2
-//define USE_FreeRTOS_HEAP_3
-//define USE_FreeRTOS_HEAP_4
-//define USE_FreeRTOS_HEAP_5
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_32_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 32-bit type.
+ *
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_64_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 64-bit type. */
+#define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_64_BITS
-*/
+/* Set configIDLE_SHOULD_YIELD to 1 to have the Idle task yield to an
+ * application task if there is an Idle priority (priority 0) application task
+ * that can run. Set to 0 to have the Idle task use all of its timeslice.
+ * Default to 1 if left undefined. */
+#define configIDLE_SHOULD_YIELD 1
+/* Each task has an array of task notifications.
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array. See https://www.freertos.org/RTOS-task-notifications.html Defaults to
+ * 1 if left undefined. */
+#define configTASK_NOTIFICATION_ARRAY_ENTRIES 1
-/* Cortex-M specific definitions. */
-#ifdef __NVIC_PRIO_BITS
- /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
- #define configPRIO_BITS __NVIC_PRIO_BITS
-#else
- #define configPRIO_BITS 4 /* 15 priority levels */
-#endif
+/* configQUEUE_REGISTRY_SIZE sets the maximum number of queues and semaphores
+ * that can be referenced from the queue registry. Only required when using a
+ * kernel aware debugger. Defaults to 0 if left undefined. */
+#define configQUEUE_REGISTRY_SIZE 0
-/* The lowest interrupt priority that can be used in a call to a "set priority"
-function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
+/* Set configENABLE_BACKWARD_COMPATIBILITY to 1 to map function names and
+ * datatypes from old version of FreeRTOS to their latest equivalent. Defaults
+ * to 1 if left undefined. */
+#define configENABLE_BACKWARD_COMPATIBILITY 0
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+/* Each task has its own array of pointers that can be used as thread local
+ * storage. configNUM_THREAD_LOCAL_STORAGE_POINTERS set the number of indexes
+ * in the array. See
+ * https://www.freertos.org/thread-local-storage-pointers.html Defaults to 0 if
+ * left undefined. */
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
-/* Interrupt priorities used by the kernel port layer itself. These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* When configUSE_MINI_LIST_ITEM is set to 0, MiniListItem_t and ListItem_t are
+ * both the same. When configUSE_MINI_LIST_ITEM is set to 1, MiniListItem_t
+ * contains 3 fewer fields than ListItem_t which saves some RAM at the cost of
+ * violating strict aliasing rules which some compilers depend on for
+ * optimization. Defaults to 1 if left undefined. */
+#define configUSE_MINI_LIST_ITEM 1
-/* Normal assert() semantics without relying on the provision of an assert.h
-header file. */
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+/* Sets the type used by the parameter to xTaskCreate() that specifies the stack
+ * size of the task being created. The same type is used to return information
+ * about stack usage in various other API calls. Defaults to size_t if left
+ * undefined. */
+#define configSTACK_DEPTH_TYPE size_t
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
- standard names. */
-#define vPortSVCHandler SVC_Handler
-#define xPortPendSVHandler PendSV_Handler
+/* configMESSAGE_BUFFER_LENGTH_TYPE sets the type used to store the length of
+ * each message written to a FreeRTOS message buffer (the length is also written
+ * to the message buffer. Defaults to size_t if left undefined - but that may
+ * waste space if messages never go above a length that could be held in a
+ * uint8_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
-/* IMPORTANT: xPortSysTickHandler define MUST be commented, when used with STM32Cube firmware,
- * to prevent overwriting SysTick_Handler defined within STM32Cube HAL, for all cores
- * #define xPortSysTickHandler SysTick_Handler
- * except for CM33, the following define should be added
- * #define SysTick_Handler xPortSysTickHandler */
+/* If configHEAP_CLEAR_MEMORY_ON_FREE is set to 1, then blocks of memory
+ * allocated using pvPortMalloc() will be cleared (i.e. set to zero) when freed
+ * using vPortFree(). Defaults to 0 if left undefined. */
+#define configHEAP_CLEAR_MEMORY_ON_FREE 1
+/* vTaskList and vTaskGetRunTimeStats APIs take a buffer as a parameter and
+ * assume that the length of the buffer is configSTATS_BUFFER_MAX_LENGTH.
+ * Defaults to 0xFFFF if left undefined. New applications are recommended to use
+ * vTaskListTasks and vTaskGetRunTimeStatistics APIs instead and supply the
+ * length of the buffer explicitly to avoid memory corruption. */
+#define configSTATS_BUFFER_MAX_LENGTH 0xFFFF
+
+/* Set configUSE_NEWLIB_REENTRANT to 1 to have a newlib reent structure
+ * allocated for each task. Set to 0 to not support newlib reent structures.
+ * Default to 0 if left undefined.
+ *
+ * Note Newlib support has been included by popular demand, but is not used or
+ * tested by the FreeRTOS maintainers themselves. FreeRTOS is not responsible
+ * for resulting newlib operation. User must be familiar with newlib and must
+ * provide system-wide implementations of the necessary stubs. Note that (at the
+ * time of writing) the current newlib design implements a system-wide malloc()
+ * that must be provided with locks. */
+#define configUSE_NEWLIB_REENTRANT 0
+
+/******************************************************************************/
+/* Software timer related definitions. ****************************************/
+/******************************************************************************/
+
+/* Set configUSE_TIMERS to 1 to include software timer functionality in the
+ * build. Set to 0 to exclude software timer functionality from the build. The
+ * FreeRTOS/source/timers.c source file must be included in the build if
+ * configUSE_TIMERS is set to 1. Default to 0 if left undefined. See
+ * https://www.freertos.org/RTOS-software-timer.html. */
+#define configUSE_TIMERS 1
+
+/* configTIMER_TASK_PRIORITY sets the priority used by the timer task. Only
+ * used if configUSE_TIMERS is set to 1. The timer task is a standard FreeRTOS
+ * task, so its priority is set like any other task. See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only
+ * used if configUSE_TIMERS is set to 1. */
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+
+/* configTIMER_TASK_STACK_DEPTH sets the size of the stack allocated to the
+ * timer task (in words, not in bytes!). The timer task is a standard FreeRTOS
+ * task. See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only
+ * used if configUSE_TIMERS is set to 1. */
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* configTIMER_QUEUE_LENGTH sets the length of the queue (the number of discrete
+ * items the queue can hold) used to send commands to the timer task. See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only
+ * used if configUSE_TIMERS is set to 1. */
+#define configTIMER_QUEUE_LENGTH 10
+
+/******************************************************************************/
+/* Event Group related definitions. *******************************************/
+/******************************************************************************/
+
+/* Set configUSE_EVENT_GROUPS to 1 to include event group functionality in the
+ * build. Set to 0 to exclude event group functionality from the build. The
+ * FreeRTOS/source/event_groups.c source file must be included in the build if
+ * configUSE_EVENT_GROUPS is set to 1. Defaults to 1 if left undefined. */
+
+#define configUSE_EVENT_GROUPS 1
+
+/******************************************************************************/
+/* Stream Buffer related definitions. *****************************************/
+/******************************************************************************/
+
+/* Set configUSE_STREAM_BUFFERS to 1 to include stream buffer functionality in
+ * the build. Set to 0 to exclude event group functionality from the build. The
+ * FreeRTOS/source/stream_buffer.c source file must be included in the build if
+ * configUSE_STREAM_BUFFERS is set to 1. Defaults to 1 if left undefined. */
+
+#define configUSE_STREAM_BUFFERS 1
+
+/******************************************************************************/
+/* Memory allocation related definitions. *************************************/
+/******************************************************************************/
+
+/* Set configSUPPORT_STATIC_ALLOCATION to 1 to include FreeRTOS API functions
+ * that create FreeRTOS objects (tasks, queues, etc.) using statically allocated
+ * memory in the build. Set to 0 to exclude the ability to create statically
+ * allocated objects from the build. Defaults to 0 if left undefined. See
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */
+#define configSUPPORT_STATIC_ALLOCATION 1
+
+/* Set configSUPPORT_DYNAMIC_ALLOCATION to 1 to include FreeRTOS API functions
+ * that create FreeRTOS objects (tasks, queues, etc.) using dynamically
+ * allocated memory in the build. Set to 0 to exclude the ability to create
+ * dynamically allocated objects from the build. Defaults to 1 if left
+ * undefined. See
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Sets the total size of the FreeRTOS heap, in bytes, when heap_1.c, heap_2.c
+ * or heap_4.c are included in the build. This value is defaulted to 4096 bytes
+ * but it must be tailored to each application. Note the heap will appear in
+ * the .bss section. See https://www.freertos.org/a00111.html. */
+#define configTOTAL_HEAP_SIZE 4096
+
+/* Set configAPPLICATION_ALLOCATED_HEAP to 1 to have the application allocate
+ * the array used as the FreeRTOS heap. Set to 0 to have the linker allocate
+ * the array used as the FreeRTOS heap. Defaults to 0 if left undefined. */
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Set configSTACK_ALLOCATION_FROM_SEPARATE_HEAP to 1 to have task stacks
+ * allocated from somewhere other than the FreeRTOS heap. This is useful if you
+ * want to ensure stacks are held in fast memory. Set to 0 to have task stacks
+ * come from the standard FreeRTOS heap. The application writer must provide
+ * implementations for pvPortMallocStack() and vPortFreeStack() if set to 1.
+ * Defaults to 0 if left undefined. */
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+/* Set configENABLE_HEAP_PROTECTOR to 1 to enable bounds checking and
+ * obfuscation to internal heap block pointers in heap_4.c and heap_5.c to help
+ * catch pointer corruptions. Defaults to 0 if left undefined. */
+#define configENABLE_HEAP_PROTECTOR 0
+
+/******************************************************************************/
+/* Interrupt nesting behaviour configuration. *********************************/
+/******************************************************************************/
+
+/* configKERNEL_INTERRUPT_PRIORITY sets the priority of the tick and context
+ * switch performing interrupts. Not supported by all FreeRTOS ports. See
+ * https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to
+ * ARM Cortex-M devices. */
+#define configKERNEL_INTERRUPT_PRIORITY 0
+
+/* configMAX_SYSCALL_INTERRUPT_PRIORITY sets the interrupt priority above which
+ * FreeRTOS API calls must not be made. Interrupts above this priority are
+ * never disabled, so never delayed by RTOS activity. The default value is set
+ * to the highest interrupt priority (0). Not supported by all FreeRTOS ports.
+ * See https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific
+ * to ARM Cortex-M devices. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0
+
+/* Another name for configMAX_SYSCALL_INTERRUPT_PRIORITY - the name used depends
+ * on the FreeRTOS port. */
+#define configMAX_API_CALL_INTERRUPT_PRIORITY 0
+
+/******************************************************************************/
+/* Hook and callback function related definitions. ****************************/
+/******************************************************************************/
+
+/* Set the following configUSE_* constants to 1 to include the named hook
+ * functionality in the build. Set to 0 to exclude the hook functionality from
+ * the build. The application writer is responsible for providing the hook
+ * function for any set to 1. See https://www.freertos.org/a00016.html. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Set configUSE_SB_COMPLETED_CALLBACK to 1 to have send and receive completed
+ * callbacks for each instance of a stream buffer or message buffer. When the
+ * option is set to 1, APIs xStreamBufferCreateWithCallback() and
+ * xStreamBufferCreateStaticWithCallback() (and likewise APIs for message
+ * buffer) can be used to create a stream buffer or message buffer instance
+ * with application provided callbacks. Defaults to 0 if left undefined. */
+#define configUSE_SB_COMPLETED_CALLBACK 0
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 1 or 2 for FreeRTOS to check for a
+ * stack overflow at the time of a context switch. Set to 0 to not look for a
+ * stack overflow. If configCHECK_FOR_STACK_OVERFLOW is 1 then the check only
+ * looks for the stack pointer being out of bounds when a task's context is
+ * saved to its stack - this is fast but somewhat ineffective. If
+ * configCHECK_FOR_STACK_OVERFLOW is 2 then the check looks for a pattern
+ * written to the end of a task's stack having been overwritten. This is
+ * slower, but will catch most (but not all) stack overflows. The application
+ * writer must provide the stack overflow callback when
+ * configCHECK_FOR_STACK_OVERFLOW is set to 1. See
+ * https://www.freertos.org/Stacks-and-stack-overflow-checking.html Defaults to
+ * 0 if left undefined. */
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/******************************************************************************/
+/* Run time and task stats gathering related definitions. *********************/
+/******************************************************************************/
+
+/* Set configGENERATE_RUN_TIME_STATS to 1 to have FreeRTOS collect data on the
+ * processing time used by each task. Set to 0 to not collect the data. The
+ * application writer needs to provide a clock source if set to 1. Defaults to
+ * 0 if left undefined. See https://www.freertos.org/rtos-run-time-stats.html.
+ */
+#define configGENERATE_RUN_TIME_STATS 0
+
+/* Set configUSE_TRACE_FACILITY to include additional task structure members
+ * are used by trace and visualisation functions and tools. Set to 0 to exclude
+ * the additional information from the structures. Defaults to 0 if left
+ * undefined. */
+#define configUSE_TRACE_FACILITY 0
+
+/* Set to 1 to include the vTaskList() and vTaskGetRunTimeStats() functions in
+ * the build. Set to 0 to exclude these functions from the build. These two
+ * functions introduce a dependency on string formatting functions that would
+ * otherwise not exist - hence they are kept separate. Defaults to 0 if left
+ * undefined. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/******************************************************************************/
+/* Co-routine related definitions. ********************************************/
+/******************************************************************************/
+
+/* Set configUSE_CO_ROUTINES to 1 to include co-routine functionality in the
+ * build, or 0 to omit co-routine functionality from the build. To include
+ * co-routines, croutine.c must be included in the project. Defaults to 0 if
+ * left undefined. */
+#define configUSE_CO_ROUTINES 0
+
+/* configMAX_CO_ROUTINE_PRIORITIES defines the number of priorities available
+ * to the application co-routines. Any number of co-routines can share the same
+ * priority. Defaults to 0 if left undefined. */
+#define configMAX_CO_ROUTINE_PRIORITIES 1
+
+/******************************************************************************/
+/* Debugging assistance. ******************************************************/
+/******************************************************************************/
+
+/* configASSERT() has the same semantics as the standard C assert(). It can
+ * either be defined to take an action when the assertion fails, or not defined
+ * at all (i.e. comment out or delete the definitions) to completely remove
+ * assertions. configASSERT() can be defined to anything you want, for example
+ * you can call a function if an assert fails that passes the filename and line
+ * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__
+ * )" or it can simple disable interrupts and sit in a loop to halt all
+ * execution on the failing line for viewing in a debugger. */
+#define configASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ taskDISABLE_INTERRUPTS(); \
+ for( ; ; ) \
+ ; \
+ }
+
+/******************************************************************************/
+/* FreeRTOS MPU specific definitions. *****************************************/
+/******************************************************************************/
+
+/* If configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS is set to 1 then
+ * the application writer can provide functions that execute in privileged mode.
+ * See:
+ * https://www.freertos.org/a00110.html#configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+ * Defaults to 0 if left undefined. Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
+#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
+
+/* Set configTOTAL_MPU_REGIONS to the number of MPU regions implemented on your
+ * target hardware. Normally 8 or 16. Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. Defaults to 8 if left
+ * undefined. */
+#define configTOTAL_MPU_REGIONS 8
+
+/* configTEX_S_C_B_FLASH allows application writers to override the default
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits
+ * for the MPU region covering Flash. Defaults to 0x07UL (which means TEX=000,
+ * S=1, C=1, B=1) if left undefined. Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
+#define configTEX_S_C_B_FLASH 0x07UL
+
+/* configTEX_S_C_B_SRAM allows application writers to override the default
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits
+ * for the MPU region covering RAM. Defaults to 0x07UL (which means TEX=000,
+ * S=1, C=1, B=1) if left undefined. Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
+#define configTEX_S_C_B_SRAM 0x07UL
+
+/* Set configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY to 0 to prevent any privilege
+ * escalations originating from outside of the kernel code itself. Set to 1 to
+ * allow application tasks to raise privilege. Defaults to 1 if left undefined.
+ * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M
+ * Cortex-M port. */
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1
+
+/* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged
+ * tasks enter critical sections (effectively mask interrupts). Set to 0 to
+ * prevent unprivileged tasks entering critical sections. Defaults to 1 if left
+ * undefined. Only used by the FreeRTOS Cortex-M MPU ports, not the standard
+ * ARMv7-M Cortex-M port. */
+#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0
+
+/* FreeRTOS Kernel version 10.6.0 introduced a new v2 MPU wrapper, namely
+ * mpu_wrappers_v2.c. Set configUSE_MPU_WRAPPERS_V1 to 0 to use the new v2 MPU
+ * wrapper. Set configUSE_MPU_WRAPPERS_V1 to 1 to use the old v1 MPU wrapper
+ * (mpu_wrappers.c). Defaults to 0 if left undefined. */
+#define configUSE_MPU_WRAPPERS_V1 0
+
+/* When using the v2 MPU wrapper, set configPROTECTED_KERNEL_OBJECT_POOL_SIZE to
+ * the total number of kernel objects, which includes tasks, queues, semaphores,
+ * mutexes, event groups, timers, stream buffers and message buffers, in your
+ * application. The application will not be able to have more than
+ * configPROTECTED_KERNEL_OBJECT_POOL_SIZE kernel objects at any point of
+ * time. */
+#define configPROTECTED_KERNEL_OBJECT_POOL_SIZE 10
+
+/* When using the v2 MPU wrapper, set configSYSTEM_CALL_STACK_SIZE to the size
+ * of the system call stack in words. Each task has a statically allocated
+ * memory buffer of this size which is used as the stack to execute system
+ * calls. For example, if configSYSTEM_CALL_STACK_SIZE is defined as 128 and
+ * there are 10 tasks in the application, the total amount of memory used for
+ * system call stacks is 128 * 10 = 1280 words. */
+#define configSYSTEM_CALL_STACK_SIZE 128
+
+/* When using the v2 MPU wrapper, set configENABLE_ACCESS_CONTROL_LIST to 1 to
+ * enable Access Control List (ACL) feature. When ACL is enabled, an
+ * unprivileged task by default does not have access to any kernel object other
+ * than itself. The application writer needs to explicitly grant the
+ * unprivileged task access to the kernel objects it needs using the APIs
+ * provided for the same. Defaults to 0 if left undefined. */
+#define configENABLE_ACCESS_CONTROL_LIST 1
+
+/******************************************************************************/
+/* SMP( Symmetric MultiProcessing ) Specific Configuration definitions. *******/
+/******************************************************************************/
+
+/* Set configNUMBER_OF_CORES to the number of available processor cores.
+ * Defaults to 1 if left undefined. */
+
+/*
+ #define configNUMBER_OF_CORES [Num of available cores]
+ */
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configRUN_MULTIPLE_PRIORITIES to 0 to allow multiple tasks to run
+ * simultaneously only if they do not have equal priority, thereby maintaining
+ * the paradigm of a lower priority task never running if a higher priority task
+ * is able to run. If configRUN_MULTIPLE_PRIORITIES is set to 1, multiple tasks
+ * with different priorities may run simultaneously - so a higher and lower
+ * priority task may run on different cores at the same time. */
+#define configRUN_MULTIPLE_PRIORITIES 0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configUSE_CORE_AFFINITY to 1 to enable core affinity feature. When core
+ * affinity feature is enabled, the vTaskCoreAffinitySet and
+ * vTaskCoreAffinityGet APIs can be used to set and retrieve which cores a task
+ * can run on. If configUSE_CORE_AFFINITY is set to 0 then the FreeRTOS
+ * scheduler is free to run any task on any available core. */
+#define configUSE_CORE_AFFINITY 0
+
+/* When using SMP with core affinity feature enabled, set
+ * configTASK_DEFAULT_CORE_AFFINITY to change the default core affinity mask for
+ * tasks created without an affinity mask specified. Setting the define to 1
+ * would make such tasks run on core 0 and setting it to (1 <<
+ * portGET_CORE_ID()) would make such tasks run on the current core. This config
+ * value is useful, if swapping tasks between cores is not supported (e.g.
+ * Tricore) or if legacy code should be controlled. Defaults to tskNO_AFFINITY
+ * if left undefined. */
+#define configTASK_DEFAULT_CORE_AFFINITY tskNO_AFFINITY
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), if
+ * configUSE_TASK_PREEMPTION_DISABLE is set to 1, individual tasks can be set to
+ * either pre-emptive or co-operative mode using the vTaskPreemptionDisable and
+ * vTaskPreemptionEnable APIs. */
+#define configUSE_TASK_PREEMPTION_DISABLE 0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configUSE_PASSIVE_IDLE_HOOK to 1 to allow the application writer to use
+ * the passive idle task hook to add background functionality without the
+ * overhead of a separate task. Defaults to 0 if left undefined. */
+#define configUSE_PASSIVE_IDLE_HOOK 0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one),
+ * configTIMER_SERVICE_TASK_CORE_AFFINITY allows the application writer to set
+ * the core affinity of the RTOS Daemon/Timer Service task. Defaults to
+ * tskNO_AFFINITY if left undefined. */
+#define configTIMER_SERVICE_TASK_CORE_AFFINITY tskNO_AFFINITY
+
+/******************************************************************************/
+/* ARMv8-M secure side port related definitions. ******************************/
+/******************************************************************************/
+
+/* secureconfigMAX_SECURE_CONTEXTS define the maximum number of tasks that can
+ * call into the secure side of an ARMv8-M chip. Not used by any other ports.
+ */
+#define secureconfigMAX_SECURE_CONTEXTS 5
+
+/* Defines the kernel provided implementation of
+ * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Idle task and Timer task
+ * respectively. The application can provide it's own implementation of
+ * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() by
+ * setting configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. */
+#define configKERNEL_PROVIDED_STATIC_MEMORY 1
+
+/******************************************************************************/
+/* ARMv8-M port Specific Configuration definitions. ***************************/
+/******************************************************************************/
+
+/* Set configENABLE_TRUSTZONE to 1 when running FreeRTOS on the non-secure side
+ * to enable the TrustZone support in FreeRTOS ARMv8-M ports which allows the
+ * non-secure FreeRTOS tasks to call the (non-secure callable) functions
+ * exported from secure side. */
+#define configENABLE_TRUSTZONE 1
+
+/* If the application writer does not want to use TrustZone, but the hardware
+ * does not support disabling TrustZone then the entire application (including
+ * the FreeRTOS scheduler) can run on the secure side without ever branching to
+ * the non-secure side. To do that, in addition to setting
+ * configENABLE_TRUSTZONE to 0, also set configRUN_FREERTOS_SECURE_ONLY to 1. */
+#define configRUN_FREERTOS_SECURE_ONLY 1
+
+/* Set configENABLE_MPU to 1 to enable the Memory Protection Unit (MPU), or 0
+ * to leave the Memory Protection Unit disabled. */
+#define configENABLE_MPU 1
+
+/* Set configENABLE_FPU to 1 to enable the Floating Point Unit (FPU), or 0
+ * to leave the Floating Point Unit disabled. */
+#define configENABLE_FPU 1
+
+/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE)
+ * support, or 0 to leave the MVE support disabled. This option is only
+ * applicable to Cortex-M55 and Cortex-M85 ports as M-Profile Vector Extension
+ * (MVE) is available only on these architectures. configENABLE_MVE must be left
+ * undefined, or defined to 0 for the Cortex-M23,Cortex-M33 and Cortex-M35P
+ * ports. */
+#define configENABLE_MVE 1
+
+/******************************************************************************/
+/* ARMv7-M and ARMv8-M port Specific Configuration definitions. ***************/
+/******************************************************************************/
+
+/* Set configCHECK_HANDLER_INSTALLATION to 1 to enable additional asserts to
+ * verify that the application has correctly installed FreeRTOS interrupt
+ * handlers.
+ *
+ * An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVC call and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVC call and PendSV
+ * interrupts and route program control from those
+ * handlers to vPortSVCHandler and xPortPendSVHandler functions. The
+ * applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0.
+ *
+ * Defaults to 1 if left undefined. */
+#define configCHECK_HANDLER_INSTALLATION 1
+
+/******************************************************************************/
+/* Definitions that include or exclude functionality. *************************/
+/******************************************************************************/
+
+/* Set the following configUSE_* constants to 1 to include the named feature in
+ * the build, or 0 to exclude the named feature from the build. */
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_QUEUE_SETS 0
+#define configUSE_APPLICATION_TASK_TAG 0
+
+/* USE_POSIX_ERRNO enables the task global FreeRTOS_errno variable which will
+ * contain the most recent error for that task. */
+#define configUSE_POSIX_ERRNO 0
+
+/* Set the following INCLUDE_* constants to 1 to include the named API function,
+ * or 0 to exclude the named API function. Most linkers will remove unused
+ * functions even when the constant is 1. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 0
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
#endif /* FREERTOS_CONFIG_H */
-
-/* IMPORTANT: xPortSysTickHandler define MUST be commented, when used with STM32Cube firmware,
- to prevent overwriting SysTick_Handler defined within STM32Cube HAL, for all cores */
-xPortSysTickHandler
\ No newline at end of file
diff --git a/Source/include/StackMacros.h b/Source/include/StackMacros.h
index 006068c..a500ccb 100644
--- a/Source/include/StackMacros.h
+++ b/Source/include/StackMacros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/include/atomic.h b/Source/include/atomic.h
index 033edce..0a75b94 100644
--- a/Source/include/atomic.h
+++ b/Source/include/atomic.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -33,6 +33,14 @@
* This file implements atomic functions by disabling interrupts globally.
* Implementations with architecture specific atomic instructions can be
* provided under each compiler directory.
+ *
+ * The atomic interface can be used in FreeRTOS tasks on all FreeRTOS ports. It
+ * can also be used in Interrupt Service Routines (ISRs) on FreeRTOS ports that
+ * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1). The
+ * atomic interface must not be used in ISRs on FreeRTOS ports that do not
+ * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
+ * because ISRs on these ports cannot be interrupted and therefore, do not need
+ * atomics in ISRs.
*/
#ifndef ATOMIC_H
@@ -59,7 +67,7 @@
* ATOMIC_ENTER_CRITICAL().
*
*/
-#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
+#if ( portHAS_NESTED_INTERRUPTS == 1 )
/* Nested interrupt scheme is supported in this port. */
#define ATOMIC_ENTER_CRITICAL() \
diff --git a/Source/include/croutine.h b/Source/include/croutine.h
index df50f87..b9aa577 100644
--- a/Source/include/croutine.h
+++ b/Source/include/croutine.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,8 +47,8 @@
typedef void * CoRoutineHandle_t;
/* Defines the prototype to which co-routine functions must conform. */
-typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,
- UBaseType_t );
+typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t xHandle,
+ UBaseType_t uxIndex );
typedef struct corCoRoutineControlBlock
{
@@ -746,6 +746,13 @@
*/
BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
+
+/*
+ * This function resets the internal state of the coroutine module. It must be
+ * called by the application before restarting the scheduler.
+ */
+void vCoRoutineResetState( void ) PRIVILEGED_FUNCTION;
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/include/deprecated_definitions.h b/Source/include/deprecated_definitions.h
index 6a25d06..1718a32 100644
--- a/Source/include/deprecated_definitions.h
+++ b/Source/include/deprecated_definitions.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/include/event_groups.h b/Source/include/event_groups.h
index a5c723d..ef14e78 100644
--- a/Source/include/event_groups.h
+++ b/Source/include/event_groups.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -40,20 +40,20 @@
* item value. It is important they don't clash with the
* taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U
- #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U
- #define eventWAIT_FOR_ALL_BITS 0x0400U
- #define eventEVENT_BITS_CONTROL_BYTES 0xff00U
+ #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint16_t ) 0x0100U )
+ #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint16_t ) 0x0200U )
+ #define eventWAIT_FOR_ALL_BITS ( ( uint16_t ) 0x0400U )
+ #define eventEVENT_BITS_CONTROL_BYTES ( ( uint16_t ) 0xff00U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL
- #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL
- #define eventWAIT_FOR_ALL_BITS 0x04000000UL
- #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL
+ #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint32_t ) 0x01000000U )
+ #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint32_t ) 0x02000000U )
+ #define eventWAIT_FOR_ALL_BITS ( ( uint32_t ) 0x04000000U )
+ #define eventEVENT_BITS_CONTROL_BYTES ( ( uint32_t ) 0xff000000U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
- #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100000000000000ULL
- #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200000000000000ULL
- #define eventWAIT_FOR_ALL_BITS 0x0400000000000000ULL
- #define eventEVENT_BITS_CONTROL_BYTES 0xff00000000000000ULL
+ #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint64_t ) 0x0100000000000000U )
+ #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint64_t ) 0x0200000000000000U )
+ #define eventWAIT_FOR_ALL_BITS ( ( uint64_t ) 0x0400000000000000U )
+ #define eventEVENT_BITS_CONTROL_BYTES ( ( uint64_t ) 0xff00000000000000U )
#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
/* *INDENT-OFF* */
@@ -139,6 +139,9 @@
* each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type
* is used to store event bits within an event group.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreate()
+ * to be available.
+ *
* @return If the event group was created then a handle to the event group is
* returned. If there was insufficient FreeRTOS heap available to create the
* event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html
@@ -196,6 +199,9 @@
* each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type
* is used to store event bits within an event group.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreateStatic()
+ * to be available.
+ *
* @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
* StaticEventGroup_t, which will be then be used to hold the event group's data
* structures, removing the need for the memory to be allocated dynamically.
@@ -238,6 +244,9 @@
*
* This function cannot be called from an interrupt.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupWaitBits()
+ * to be available.
+ *
* @param xEventGroup The event group in which the bits are being tested. The
* event group must have previously been created using a call to
* xEventGroupCreate().
@@ -331,6 +340,9 @@
* Clear bits within an event group. This function cannot be called from an
* interrupt.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupClearBits()
+ * to be available.
+ *
* @param xEventGroup The event group in which the bits are to be cleared.
*
* @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
@@ -461,6 +473,9 @@
* Setting bits in an event group will automatically unblock tasks that are
* blocked waiting for the bits.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSetBits()
+ * to be available.
+ *
* @param xEventGroup The event group in which the bits are to be set.
*
* @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
@@ -468,14 +483,11 @@
* and bit 0 set uxBitsToSet to 0x09.
*
* @return The value of the event group at the time the call to
- * xEventGroupSetBits() returns. There are two reasons why the returned value
- * might have the bits specified by the uxBitsToSet parameter cleared. First,
- * if setting a bit results in a task that was waiting for the bit leaving the
- * blocked state then it is possible the bit will be cleared automatically
- * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any
- * unblocked (or otherwise Ready state) task that has a priority above that of
- * the task that called xEventGroupSetBits() will execute and may change the
- * event group value before the call to xEventGroupSetBits() returns.
+ * xEventGroupSetBits() returns. Returned value might have the bits specified
+ * by the uxBitsToSet parameter cleared if setting a bit results in a task
+ * that was waiting for the bit leaving the blocked state then it is possible
+ * the bit will be cleared automatically (see the xClearBitOnExit parameter
+ * of xEventGroupWaitBits()).
*
* Example usage:
* @code{c}
@@ -625,6 +637,9 @@
* this case all the bits specified by uxBitsToWait will be automatically
* cleared before the function returns.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSync()
+ * to be available.
+ *
* @param xEventGroup The event group in which the bits are being tested. The
* event group must have previously been created using a call to
* xEventGroupCreate().
@@ -743,6 +758,9 @@
* Returns the current value of the bits in an event group. This function
* cannot be used from an interrupt.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBits()
+ * to be available.
+ *
* @param xEventGroup The event group being queried.
*
* @return The event group bits at the time xEventGroupGetBits() was called.
@@ -760,6 +778,9 @@
*
* A version of xEventGroupGetBits() that can be called from an ISR.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBitsFromISR()
+ * to be available.
+ *
* @param xEventGroup The event group being queried.
*
* @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
@@ -779,6 +800,9 @@
* xEventGroupCreate(). Tasks that are blocked on the event group will be
* unblocked and obtain 0 as the event group's value.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for vEventGroupDelete()
+ * to be available.
+ *
* @param xEventGroup The event group being deleted.
*/
void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
@@ -793,6 +817,9 @@
* Retrieve a pointer to a statically created event groups's data structure
* buffer. It is the same buffer that is supplied at the time of creation.
*
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetStaticBuffer()
+ * to be available.
+ *
* @param xEventGroup The event group for which to retrieve the buffer.
*
* @param ppxEventGroupBuffer Used to return a pointer to the event groups's
@@ -807,9 +834,9 @@
/* For internal use only. */
void vEventGroupSetBitsCallback( void * pvEventGroup,
- const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+ uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
void vEventGroupClearBitsCallback( void * pvEventGroup,
- const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+ uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
#if ( configUSE_TRACE_FACILITY == 1 )
diff --git a/Source/include/list.h b/Source/include/list.h
index 62c6238..7de4d36 100644
--- a/Source/include/list.h
+++ b/Source/include/list.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -151,7 +151,7 @@
struct xLIST * configLIST_VOLATILE pxContainer; /**< Pointer to the list in which this list item is placed (if any). */
listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
};
-typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */
+typedef struct xLIST_ITEM ListItem_t;
#if ( configUSE_MINI_LIST_ITEM == 1 )
struct xMINI_LIST_ITEM
@@ -172,7 +172,7 @@
typedef struct xLIST
{
listFIRST_LIST_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
- volatile UBaseType_t uxNumberOfItems;
+ configLIST_VOLATILE UBaseType_t uxNumberOfItems;
ListItem_t * configLIST_VOLATILE pxIndex; /**< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
MiniListItem_t xListEnd; /**< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
listSECOND_LIST_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
@@ -282,7 +282,8 @@
* \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
* \ingroup LinkedList
*/
-#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \
+#if ( configNUMBER_OF_CORES == 1 )
+ #define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \
do { \
List_t * const pxConstList = ( pxList ); \
/* Increment the index to the next item and return the item, ensuring */ \
@@ -294,6 +295,13 @@
} \
( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \
} while( 0 )
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+/* This function is not required in SMP. FreeRTOS SMP scheduler doesn't use
+ * pxIndex and it should always point to the xListEnd. Not defining this macro
+ * here to prevent updating pxIndex.
+ */
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
/*
* Version of uxListRemove() that does not return a value. Provided as a slight
@@ -314,19 +322,19 @@
#define listREMOVE_ITEM( pxItemToRemove ) \
do { \
/* The list item knows which list it is in. Obtain the list from the list \
- * item. */ \
- List_t * const pxList = ( pxItemToRemove )->pxContainer; \
- \
- ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \
- ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; \
- /* Make sure the index is left pointing to a valid item. */ \
- if( pxList->pxIndex == ( pxItemToRemove ) ) \
- { \
- pxList->pxIndex = ( pxItemToRemove )->pxPrevious; \
- } \
- \
- ( pxItemToRemove )->pxContainer = NULL; \
- ( pxList->uxNumberOfItems )--; \
+ * item. */ \
+ List_t * const pxList = ( pxItemToRemove )->pxContainer; \
+ \
+ ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \
+ ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; \
+ /* Make sure the index is left pointing to a valid item. */ \
+ if( pxList->pxIndex == ( pxItemToRemove ) ) \
+ { \
+ pxList->pxIndex = ( pxItemToRemove )->pxPrevious; \
+ } \
+ \
+ ( pxItemToRemove )->pxContainer = NULL; \
+ ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) - 1U ); \
} while( 0 )
/*
@@ -363,17 +371,17 @@
\
/* Insert a new list item into ( pxList ), but rather than sort the list, \
* makes the new list item the last item to be removed by a call to \
- * listGET_OWNER_OF_NEXT_ENTRY(). */ \
- ( pxNewListItem )->pxNext = pxIndex; \
- ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \
- \
- pxIndex->pxPrevious->pxNext = ( pxNewListItem ); \
- pxIndex->pxPrevious = ( pxNewListItem ); \
- \
- /* Remember which list the item is in. */ \
- ( pxNewListItem )->pxContainer = ( pxList ); \
- \
- ( ( pxList )->uxNumberOfItems )++; \
+ * listGET_OWNER_OF_NEXT_ENTRY(). */ \
+ ( pxNewListItem )->pxNext = pxIndex; \
+ ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \
+ \
+ pxIndex->pxPrevious->pxNext = ( pxNewListItem ); \
+ pxIndex->pxPrevious = ( pxNewListItem ); \
+ \
+ /* Remember which list the item is in. */ \
+ ( pxNewListItem )->pxContainer = ( pxList ); \
+ \
+ ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) + 1U ); \
} while( 0 )
/*
diff --git a/Source/include/message_buffer.h b/Source/include/message_buffer.h
index 136445d..5c4d15b 100644
--- a/Source/include/message_buffer.h
+++ b/Source/include/message_buffer.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -43,12 +43,12 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * timeout to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Message buffers hold variable length messages. To enable that, when a
* message is written to the message buffer an additional sizeof( size_t ) bytes
@@ -100,6 +100,8 @@
*
* configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
* FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferCreate() to be available.
*
* @param xBufferSizeBytes The total number of bytes (not messages) the message
* buffer will be able to hold at any one time. When a message is written to
@@ -156,11 +158,11 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferCreate( xBufferSizeBytes ) \
- xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL )
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, NULL, NULL )
#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
#define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
- xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif
/**
@@ -168,12 +170,15 @@
*
* @code{c}
* MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
- * uint8_t *pucMessageBufferStorageArea,
- * StaticMessageBuffer_t *pxStaticMessageBuffer );
+ * uint8_t *pucMessageBufferStorageArea,
+ * StaticMessageBuffer_t *pxStaticMessageBuffer );
* @endcode
* Creates a new message buffer using statically allocated memory. See
* xMessageBufferCreate() for a version that uses dynamically allocated memory.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferCreateStatic() to be available.
+ *
* @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
* pucMessageBufferStorageArea parameter. When a message is written to the
* message buffer an additional sizeof( size_t ) bytes are also written to store
@@ -238,11 +243,11 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
- xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
#define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
- xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif
/**
@@ -258,6 +263,9 @@
* buffer and storage area buffer. These are the same buffers that are supplied
* at the time of creation.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferGetStaticBuffers() to be available.
+ *
* @param xMessageBuffer The message buffer for which to retrieve the buffers.
*
* @param ppucMessageBufferStorageArea Used to return a pointer to the
@@ -281,9 +289,9 @@
*
* @code{c}
* size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
- * const void *pvTxData,
- * size_t xDataLengthBytes,
- * TickType_t xTicksToWait );
+ * const void *pvTxData,
+ * size_t xDataLengthBytes,
+ * TickType_t xTicksToWait );
* @endcode
*
* Sends a discrete message to the message buffer. The message can be any
@@ -298,17 +306,20 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Use xMessageBufferSend() to write to a message buffer from a task. Use
* xMessageBufferSendFromISR() to write to a message buffer from an interrupt
* service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSend() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer to which a message is
* being sent.
*
@@ -381,9 +392,9 @@
*
* @code{c}
* size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
- * const void *pvTxData,
- * size_t xDataLengthBytes,
- * BaseType_t *pxHigherPriorityTaskWoken );
+ * const void *pvTxData,
+ * size_t xDataLengthBytes,
+ * BaseType_t *pxHigherPriorityTaskWoken );
* @endcode
*
* Interrupt safe version of the API function that sends a discrete message to
@@ -398,17 +409,20 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Use xMessageBufferSend() to write to a message buffer from a task. Use
* xMessageBufferSendFromISR() to write to a message buffer from an interrupt
* service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSendFromISR() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer to which a message is
* being sent.
*
@@ -486,9 +500,9 @@
*
* @code{c}
* size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
- * void *pvRxData,
- * size_t xBufferLengthBytes,
- * TickType_t xTicksToWait );
+ * void *pvRxData,
+ * size_t xBufferLengthBytes,
+ * TickType_t xTicksToWait );
* @endcode
*
* Receives a discrete message from a message buffer. Messages can be of
@@ -502,17 +516,20 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Use xMessageBufferReceive() to read from a message buffer from a task. Use
* xMessageBufferReceiveFromISR() to read from a message buffer from an
* interrupt service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceive() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer from which a message
* is being received.
*
@@ -576,9 +593,9 @@
*
* @code{c}
* size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
- * void *pvRxData,
- * size_t xBufferLengthBytes,
- * BaseType_t *pxHigherPriorityTaskWoken );
+ * void *pvRxData,
+ * size_t xBufferLengthBytes,
+ * BaseType_t *pxHigherPriorityTaskWoken );
* @endcode
*
* An interrupt safe version of the API function that receives a discrete
@@ -593,17 +610,20 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Use xMessageBufferReceive() to read from a message buffer from a task. Use
* xMessageBufferReceiveFromISR() to read from a message buffer from an
* interrupt service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceiveFromISR() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer from which a message
* is being received.
*
@@ -687,6 +707,9 @@
* A message buffer handle must not be used after the message buffer has been
* deleted.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vMessageBufferDelete() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer to be deleted.
*
*/
@@ -703,6 +726,9 @@
* cannot accept any more messages, of any size, until space is made available
* by a message being removed from the message buffer.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferIsFull() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer being queried.
*
* @return If the message buffer referenced by xMessageBuffer is full then
@@ -719,6 +745,9 @@
*
* Tests to see if a message buffer is empty (does not contain any messages).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferIsEmpty() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer being queried.
*
* @return If the message buffer referenced by xMessageBuffer is empty then
@@ -739,6 +768,13 @@
*
* A message buffer can only be reset if there are no tasks blocked on it.
*
+ * Use xMessageBufferReset() to reset a message buffer from a task.
+ * Use xMessageBufferResetFromISR() to reset a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReset() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer being reset.
*
* @return If the message buffer was reset then pdPASS is returned. If the
@@ -756,10 +792,45 @@
/**
* message_buffer.h
* @code{c}
+ * BaseType_t xMessageBufferResetFromISR( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that resets the message buffer.
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * Use xMessageBufferReset() to reset a message buffer from a task.
+ * Use xMessageBufferResetFromISR() to reset a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferResetFromISR() to be available.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned. If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferResetFromISR xMessageBufferResetFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferResetFromISR( xMessageBuffer ) \
+ xStreamBufferResetFromISR( xMessageBuffer )
+
+/**
+ * message_buffer.h
+ * @code{c}
* size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer );
* @endcode
* Returns the number of bytes of free space in the message buffer.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSpaceAvailable() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer being queried.
*
* @return The number of bytes that can be written to the message buffer before
@@ -786,6 +857,9 @@
* Useful if xMessageBufferReceive() returned 0 because the size of the buffer
* passed into xMessageBufferReceive() was too small to hold the next message.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferNextLengthBytes() to be available.
+ *
* @param xMessageBuffer The handle of the message buffer being queried.
*
* @return The length (in bytes) of the next message in the message buffer, or 0
@@ -795,7 +869,7 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
- xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION;
+ xStreamBufferNextMessageLengthBytes( xMessageBuffer )
/**
* message_buffer.h
@@ -817,6 +891,9 @@
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
* additional information.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSendCompletedFromISR() to be available.
+ *
* @param xMessageBuffer The handle of the stream buffer to which data was
* written.
*
@@ -858,6 +935,9 @@
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
* additional information.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceiveCompletedFromISR() to be available.
+ *
* @param xMessageBuffer The handle of the stream buffer from which data was
* read.
*
diff --git a/Source/include/mpu_prototypes.h b/Source/include/mpu_prototypes.h
index 574f1da..3a2bff5 100644
--- a/Source/include/mpu_prototypes.h
+++ b/Source/include/mpu_prototypes.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -56,14 +56,14 @@
TickType_t xTicksToWait;
} xTaskGenericNotifyWaitParams_t;
-typedef struct xTimerGenericCommandParams
+typedef struct xTimerGenericCommandFromTaskParams
{
TimerHandle_t xTimer;
BaseType_t xCommandID;
TickType_t xOptionalValue;
BaseType_t * pxHigherPriorityTaskWoken;
TickType_t xTicksToWait;
-} xTimerGenericCommandParams_t;
+} xTimerGenericCommandFromTaskParams_t;
typedef struct xEventGroupWaitBitsParams
{
@@ -89,7 +89,6 @@
void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
@@ -141,25 +140,27 @@
BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
const char * const pcName,
- const uint16_t usStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
const char * const pcName,
- const uint32_t ulStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskPrioritySet( TaskHandle_t xTask,
- UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+ UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
- void * pvParameter ) FREERTOS_SYSTEM_CALL;
- void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
- void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+ void * pvParameter ) FREERTOS_SYSTEM_CALL;
+ void MPU_vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+ size_t uxBufferLength ) FREERTOS_SYSTEM_CALL;
+ void MPU_vTaskListTasks( char * pcWriteBuffer,
+ size_t uxBufferLength ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
@@ -168,13 +169,13 @@
BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
const char * const pcName,
- const uint16_t usStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
const char * const pcName,
- const uint32_t ulStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
@@ -188,16 +189,19 @@
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
-void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
- const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+ const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask,
StackType_t ** ppuxStackBuffer,
StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;
UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
@@ -265,6 +269,9 @@
StaticQueue_t * pxStaticQueue,
const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+ QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+ uint8_t * pucQueueStorage,
+ StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
@@ -290,6 +297,9 @@
StaticQueue_t * pxStaticQueue,
const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+ QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+ uint8_t * pucQueueStorage,
+ StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
@@ -323,15 +333,15 @@
void * pvNewID ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
- const BaseType_t xCommandID,
- const TickType_t xOptionalValue,
- BaseType_t * const pxHigherPriorityTaskWoken,
- const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
@@ -342,17 +352,22 @@
* with all the APIs. */
TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction,
StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer,
StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
/* MPU versions of event_group.h API functions. */
EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
@@ -472,5 +487,6 @@
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
#endif /* MPU_PROTOTYPES_H */
diff --git a/Source/include/mpu_syscall_numbers.h b/Source/include/mpu_syscall_numbers.h
index 03c3ebd..7203a3a 100644
--- a/Source/include/mpu_syscall_numbers.h
+++ b/Source/include/mpu_syscall_numbers.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -32,7 +32,7 @@
/* Numbers assigned to various system calls. */
#define SYSTEM_CALL_xTaskGenericNotify 0
#define SYSTEM_CALL_xTaskGenericNotifyWait 1
-#define SYSTEM_CALL_xTimerGenericCommand 2
+#define SYSTEM_CALL_xTimerGenericCommandFromTask 2
#define SYSTEM_CALL_xEventGroupWaitBits 3
#define SYSTEM_CALL_xTaskDelayUntil 4
#define SYSTEM_CALL_xTaskAbortDelay 5
@@ -45,62 +45,61 @@
#define SYSTEM_CALL_vTaskResume 12
#define SYSTEM_CALL_xTaskGetTickCount 13
#define SYSTEM_CALL_uxTaskGetNumberOfTasks 14
-#define SYSTEM_CALL_pcTaskGetName 15
-#define SYSTEM_CALL_ulTaskGetRunTimeCounter 16
-#define SYSTEM_CALL_ulTaskGetRunTimePercent 17
-#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent 18
-#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter 19
-#define SYSTEM_CALL_vTaskSetApplicationTaskTag 20
-#define SYSTEM_CALL_xTaskGetApplicationTaskTag 21
-#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer 22
-#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer 23
-#define SYSTEM_CALL_uxTaskGetSystemState 24
-#define SYSTEM_CALL_uxTaskGetStackHighWaterMark 25
-#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2 26
-#define SYSTEM_CALL_xTaskGetCurrentTaskHandle 27
-#define SYSTEM_CALL_xTaskGetSchedulerState 28
-#define SYSTEM_CALL_vTaskSetTimeOutState 29
-#define SYSTEM_CALL_xTaskCheckForTimeOut 30
-#define SYSTEM_CALL_ulTaskGenericNotifyTake 31
-#define SYSTEM_CALL_xTaskGenericNotifyStateClear 32
-#define SYSTEM_CALL_ulTaskGenericNotifyValueClear 33
-#define SYSTEM_CALL_xQueueGenericSend 34
-#define SYSTEM_CALL_uxQueueMessagesWaiting 35
-#define SYSTEM_CALL_uxQueueSpacesAvailable 36
-#define SYSTEM_CALL_xQueueReceive 37
-#define SYSTEM_CALL_xQueuePeek 38
-#define SYSTEM_CALL_xQueueSemaphoreTake 39
-#define SYSTEM_CALL_xQueueGetMutexHolder 40
-#define SYSTEM_CALL_xQueueTakeMutexRecursive 41
-#define SYSTEM_CALL_xQueueGiveMutexRecursive 42
-#define SYSTEM_CALL_xQueueSelectFromSet 43
-#define SYSTEM_CALL_xQueueAddToSet 44
-#define SYSTEM_CALL_vQueueAddToRegistry 45
-#define SYSTEM_CALL_vQueueUnregisterQueue 46
-#define SYSTEM_CALL_pcQueueGetName 47
-#define SYSTEM_CALL_pvTimerGetTimerID 48
-#define SYSTEM_CALL_vTimerSetTimerID 49
-#define SYSTEM_CALL_xTimerIsTimerActive 50
-#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle 51
-#define SYSTEM_CALL_pcTimerGetName 52
-#define SYSTEM_CALL_vTimerSetReloadMode 53
-#define SYSTEM_CALL_xTimerGetReloadMode 54
-#define SYSTEM_CALL_uxTimerGetReloadMode 55
-#define SYSTEM_CALL_xTimerGetPeriod 56
-#define SYSTEM_CALL_xTimerGetExpiryTime 57
-#define SYSTEM_CALL_xEventGroupClearBits 58
-#define SYSTEM_CALL_xEventGroupSetBits 59
-#define SYSTEM_CALL_xEventGroupSync 60
-#define SYSTEM_CALL_uxEventGroupGetNumber 61
-#define SYSTEM_CALL_vEventGroupSetNumber 62
-#define SYSTEM_CALL_xStreamBufferSend 63
-#define SYSTEM_CALL_xStreamBufferReceive 64
-#define SYSTEM_CALL_xStreamBufferIsFull 65
-#define SYSTEM_CALL_xStreamBufferIsEmpty 66
-#define SYSTEM_CALL_xStreamBufferSpacesAvailable 67
-#define SYSTEM_CALL_xStreamBufferBytesAvailable 68
-#define SYSTEM_CALL_xStreamBufferSetTriggerLevel 69
-#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes 70
-#define NUM_SYSTEM_CALLS 71 /* Total number of system calls. */
+#define SYSTEM_CALL_ulTaskGetRunTimeCounter 15
+#define SYSTEM_CALL_ulTaskGetRunTimePercent 16
+#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent 17
+#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter 18
+#define SYSTEM_CALL_vTaskSetApplicationTaskTag 19
+#define SYSTEM_CALL_xTaskGetApplicationTaskTag 20
+#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer 21
+#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer 22
+#define SYSTEM_CALL_uxTaskGetSystemState 23
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark 24
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2 25
+#define SYSTEM_CALL_xTaskGetCurrentTaskHandle 26
+#define SYSTEM_CALL_xTaskGetSchedulerState 27
+#define SYSTEM_CALL_vTaskSetTimeOutState 28
+#define SYSTEM_CALL_xTaskCheckForTimeOut 29
+#define SYSTEM_CALL_ulTaskGenericNotifyTake 30
+#define SYSTEM_CALL_xTaskGenericNotifyStateClear 31
+#define SYSTEM_CALL_ulTaskGenericNotifyValueClear 32
+#define SYSTEM_CALL_xQueueGenericSend 33
+#define SYSTEM_CALL_uxQueueMessagesWaiting 34
+#define SYSTEM_CALL_uxQueueSpacesAvailable 35
+#define SYSTEM_CALL_xQueueReceive 36
+#define SYSTEM_CALL_xQueuePeek 37
+#define SYSTEM_CALL_xQueueSemaphoreTake 38
+#define SYSTEM_CALL_xQueueGetMutexHolder 39
+#define SYSTEM_CALL_xQueueTakeMutexRecursive 40
+#define SYSTEM_CALL_xQueueGiveMutexRecursive 41
+#define SYSTEM_CALL_xQueueSelectFromSet 42
+#define SYSTEM_CALL_xQueueAddToSet 43
+#define SYSTEM_CALL_vQueueAddToRegistry 44
+#define SYSTEM_CALL_vQueueUnregisterQueue 45
+#define SYSTEM_CALL_pcQueueGetName 46
+#define SYSTEM_CALL_pvTimerGetTimerID 47
+#define SYSTEM_CALL_vTimerSetTimerID 48
+#define SYSTEM_CALL_xTimerIsTimerActive 49
+#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle 50
+#define SYSTEM_CALL_pcTimerGetName 51
+#define SYSTEM_CALL_vTimerSetReloadMode 52
+#define SYSTEM_CALL_xTimerGetReloadMode 53
+#define SYSTEM_CALL_uxTimerGetReloadMode 54
+#define SYSTEM_CALL_xTimerGetPeriod 55
+#define SYSTEM_CALL_xTimerGetExpiryTime 56
+#define SYSTEM_CALL_xEventGroupClearBits 57
+#define SYSTEM_CALL_xEventGroupSetBits 58
+#define SYSTEM_CALL_xEventGroupSync 59
+#define SYSTEM_CALL_uxEventGroupGetNumber 60
+#define SYSTEM_CALL_vEventGroupSetNumber 61
+#define SYSTEM_CALL_xStreamBufferSend 62
+#define SYSTEM_CALL_xStreamBufferReceive 63
+#define SYSTEM_CALL_xStreamBufferIsFull 64
+#define SYSTEM_CALL_xStreamBufferIsEmpty 65
+#define SYSTEM_CALL_xStreamBufferSpacesAvailable 66
+#define SYSTEM_CALL_xStreamBufferBytesAvailable 67
+#define SYSTEM_CALL_xStreamBufferSetTriggerLevel 68
+#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes 69
+#define NUM_SYSTEM_CALLS 70 /* Total number of system calls. */
#endif /* MPU_SYSCALL_NUMBERS_H */
diff --git a/Source/include/mpu_wrappers.h b/Source/include/mpu_wrappers.h
index e61514f..1bad3a2 100644
--- a/Source/include/mpu_wrappers.h
+++ b/Source/include/mpu_wrappers.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -57,7 +57,6 @@
#define vTaskResume MPU_vTaskResume
#define xTaskGetTickCount MPU_xTaskGetTickCount
#define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks
- #define pcTaskGetName MPU_pcTaskGetName
#define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark
#define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2
#define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag
@@ -87,11 +86,12 @@
* the application can use opaque handles maintained in mpu_wrappers.c
* with all the APIs. */
#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
- /* These are not needed in v2 because they do not take a task
- * handle and therefore, no lookup is needed. Needed in v1 because
- * these are available as system calls in v1. */
- #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats
- #define vTaskList MPU_vTaskList
+
+/* These are not needed in v2 because they do not take a task
+ * handle and therefore, no lookup is needed. Needed in v1 because
+ * these are available as system calls in v1. */
+ #define vTaskGetRunTimeStatistics MPU_vTaskGetRunTimeStatistics
+ #define vTaskListTasks MPU_vTaskListTasks
#define vTaskSuspendAll MPU_vTaskSuspendAll
#define xTaskCatchUpTicks MPU_xTaskCatchUpTicks
#define xTaskResumeAll MPU_xTaskResumeAll
@@ -105,11 +105,14 @@
#define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ #define pcTaskGetName MPU_pcTaskGetName
#define xTaskCreateRestricted MPU_xTaskCreateRestricted
#define xTaskCreateRestrictedStatic MPU_xTaskCreateRestrictedStatic
#define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions
#define xTaskGetStaticBuffers MPU_xTaskGetStaticBuffers
#define uxTaskPriorityGetFromISR MPU_uxTaskPriorityGetFromISR
+ #define uxTaskBasePriorityGet MPU_uxTaskBasePriorityGet
+ #define uxTaskBasePriorityGetFromISR MPU_uxTaskBasePriorityGetFromISR
#define xTaskResumeFromISR MPU_xTaskResumeFromISR
#define xTaskGetApplicationTaskTagFromISR MPU_xTaskGetApplicationTaskTagFromISR
#define xTaskGenericNotifyFromISR MPU_xTaskGenericNotifyFromISR
@@ -147,6 +150,7 @@
#define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic
#define xQueueGenericReset MPU_xQueueGenericReset
#define xQueueCreateSet MPU_xQueueCreateSet
+ #define xQueueCreateSetStatic MPU_xQueueCreateSetStatic
#define xQueueRemoveFromSet MPU_xQueueRemoveFromSet
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -167,7 +171,7 @@
#define vTimerSetTimerID MPU_vTimerSetTimerID
#define xTimerIsTimerActive MPU_xTimerIsTimerActive
#define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle
- #define xTimerGenericCommand MPU_xTimerGenericCommand
+ #define xTimerGenericCommandFromTask MPU_xTimerGenericCommandFromTask
#define pcTimerGetName MPU_pcTimerGetName
#define vTimerSetReloadMode MPU_vTimerSetReloadMode
#define uxTimerGetReloadMode MPU_uxTimerGetReloadMode
@@ -182,9 +186,10 @@
* the application can use opaque handles maintained in mpu_wrappers.c
* with all the APIs. */
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
- #define xTimerCreate MPU_xTimerCreate
- #define xTimerCreateStatic MPU_xTimerCreateStatic
- #define xTimerGetStaticBuffer MPU_xTimerGetStaticBuffer
+ #define xTimerCreate MPU_xTimerCreate
+ #define xTimerCreateStatic MPU_xTimerCreateStatic
+ #define xTimerGetStaticBuffer MPU_xTimerGetStaticBuffer
+ #define xTimerGenericCommandFromISR MPU_xTimerGenericCommandFromISR
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/* Map standard event_group.h API functions to the MPU equivalents. */
@@ -238,16 +243,9 @@
#define xStreamBufferReceiveFromISR MPU_xStreamBufferReceiveFromISR
#define xStreamBufferSendCompletedFromISR MPU_xStreamBufferSendCompletedFromISR
#define xStreamBufferReceiveCompletedFromISR MPU_xStreamBufferReceiveCompletedFromISR
+ #define xStreamBufferResetFromISR MPU_xStreamBufferResetFromISR
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
-/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
- * macro so applications can place data in privileged access sections
- * (useful when using statically allocated objects). */
- #define PRIVILEGED_FUNCTION
- #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) )
- #define FREERTOS_SYSTEM_CALL
-
-
#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
#define vGrantAccessToTask( xTask, xTaskToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToGrantAccess ) )
@@ -276,15 +274,12 @@
#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
- #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-/* Ensure API functions go in the privileged execution section. */
- #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) )
- #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) )
- #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) )
-
#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+ #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) )
+ #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) )
+ #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) )
+
#else /* portUSING_MPU_WRAPPERS */
#define PRIVILEGED_FUNCTION
diff --git a/Source/include/newlib-freertos.h b/Source/include/newlib-freertos.h
index b6911c9..3aa344a 100644
--- a/Source/include/newlib-freertos.h
+++ b/Source/include/newlib-freertos.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/include/picolibc-freertos.h b/Source/include/picolibc-freertos.h
index 63f6927..677205d 100644
--- a/Source/include/picolibc-freertos.h
+++ b/Source/include/picolibc-freertos.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -58,18 +58,19 @@
#endif
/* Allocate thread local storage block off the end of the
-* stack. The _tls_size() function returns the size (in
-* bytes) of the total TLS area used by the application */
+ * stack. The picolibcTLS_SIZE macro returns the size (in
+ * bytes) of the total TLS area used by the application.
+ * Calculate the top of stack address. */
#if ( portSTACK_GROWTH < 0 )
- #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \
- do { \
- pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) \
- - picolibcTLS_SIZE ) & ~ \
- configMAX( picolibcSTACK_ALIGNMENT_MASK, \
- picolibcTLS_ALIGNMENT_MASK ) ); \
- xTLSBlock = pxTopOfStack; \
- _init_tls( xTLSBlock ); \
+ #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \
+ do { \
+ xTLSBlock = ( void * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) - \
+ picolibcTLS_SIZE ) & \
+ ~picolibcTLS_ALIGNMENT_MASK ); \
+ pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) - 1 ) & \
+ ~picolibcSTACK_ALIGNMENT_MASK ); \
+ _init_tls( xTLSBlock ); \
} while( 0 )
#else /* portSTACK_GROWTH */
#define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \
diff --git a/Source/include/portable.h b/Source/include/portable.h
index ec11f0f..601062a 100644
--- a/Source/include/portable.h
+++ b/Source/include/portable.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -85,19 +85,31 @@
#define portARCH_NAME NULL
#endif
+#ifndef portBASE_TYPE_ENTER_CRITICAL
+ #define portBASE_TYPE_ENTER_CRITICAL() taskENTER_CRITICAL()
+#endif
+
+#ifndef portBASE_TYPE_EXIT_CRITICAL
+ #define portBASE_TYPE_EXIT_CRITICAL() taskEXIT_CRITICAL()
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+ #define configSTACK_DEPTH_TYPE StackType_t
+#endif
+
#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP
/* Defaults to 0 for backward compatibility. */
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
#endif
+#include "mpu_wrappers.h"
+
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
-#include "mpu_wrappers.h"
-
/*
* Setup the stack of a new task so it is ready to be placed under the
* scheduler control. The registers have to be placed on the stack in
@@ -174,13 +186,14 @@
/*
* Map to the memory management routines required for the port.
*/
-void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void * pvPortMalloc( size_t xWantedSize ) PRIVILEGED_FUNCTION;
void * pvPortCalloc( size_t xNum,
size_t xSize ) PRIVILEGED_FUNCTION;
void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+void xPortResetHeapMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 )
void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION;
@@ -190,6 +203,12 @@
#define vPortFreeStack vPortFree
#endif
+/*
+ * This function resets the internal state of the heap module. It must be called
+ * by the application before restarting the scheduler.
+ */
+void vPortHeapResetState( void ) PRIVILEGED_FUNCTION;
+
#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
/**
@@ -200,7 +219,7 @@
*
* This hook function is called when allocation failed.
*/
- void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+ void vApplicationMallocFailedHook( void );
#endif
/*
@@ -228,7 +247,7 @@
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+ configSTACK_DEPTH_TYPE uxStackDepth ) PRIVILEGED_FUNCTION;
#endif
/**
diff --git a/Source/include/projdefs.h b/Source/include/projdefs.h
index 4c46333..c9ac64a 100644
--- a/Source/include/projdefs.h
+++ b/Source/include/projdefs.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -33,13 +33,20 @@
* Defines the prototype to which task functions must conform. Defined in this
* file to ensure the type is known before portable.h is included.
*/
-typedef void (* TaskFunction_t)( void * );
+typedef void (* TaskFunction_t)( void * arg );
/* Converts a time in milliseconds to a time in ticks. This macro can be
* overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
* definition here is not suitable for your application. */
#ifndef pdMS_TO_TICKS
- #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
+ #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInMs ) * ( uint64_t ) configTICK_RATE_HZ ) / ( uint64_t ) 1000U ) )
+#endif
+
+/* Converts a time in ticks to a time in milliseconds. This macro can be
+ * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+ * definition here is not suitable for your application. */
+#ifndef pdTICKS_TO_MS
+ #define pdTICKS_TO_MS( xTimeInTicks ) ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInTicks ) * ( uint64_t ) 1000U ) / ( uint64_t ) configTICK_RATE_HZ ) )
#endif
#define pdFALSE ( ( BaseType_t ) 0 )
diff --git a/Source/include/queue.h b/Source/include/queue.h
index 836adf5..7c8e0de 100644
--- a/Source/include/queue.h
+++ b/Source/include/queue.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -34,14 +34,14 @@
#error "include FreeRTOS.h" must appear in source files before "include queue.h"
#endif
+#include "task.h"
+
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
-#include "task.h"
-
/**
* Type by which queues are referenced. For example, a call to xQueueCreate()
* returns an QueueHandle_t variable that can then be used as a parameter to
@@ -71,11 +71,11 @@
/* For internal use only. These definitions *must* match those in queue.c. */
#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U )
#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U )
#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U )
#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U )
#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U )
+#define queueQUEUE_TYPE_SET ( ( uint8_t ) 5U )
/**
* queue. h
@@ -109,7 +109,7 @@
* the same size.
*
* @return If the queue is successfully create then a handle to the newly
- * created queue is returned. If the queue cannot be created then 0 is
+ * created queue is returned. If the queue cannot be created then NULL is
* returned.
*
* Example usage:
@@ -126,7 +126,7 @@
*
* // Create a queue capable of containing 10 uint32_t values.
* xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- * if( xQueue1 == 0 )
+ * if( xQueue1 == NULL )
* {
* // Queue was not created and must not be used.
* }
@@ -134,7 +134,7 @@
* // Create a queue capable of containing 10 pointers to AMessage structures.
* // These should be passed by pointer as they contain a lot of data.
* xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- * if( xQueue2 == 0 )
+ * if( xQueue2 == NULL )
* {
* // Queue was not created and must not be used.
* }
@@ -267,7 +267,7 @@
/**
* queue. h
* @code{c}
- * BaseType_t xQueueSendToToFront(
+ * BaseType_t xQueueSendToFront(
* QueueHandle_t xQueue,
* const void *pvItemToQueue,
* TickType_t xTicksToWait
@@ -292,7 +292,7 @@
* queue is full. The time is defined in tick periods so the constant
* portTICK_PERIOD_MS should be used to convert to real time if this is required.
*
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
*
* Example usage:
* @code{c}
@@ -302,7 +302,7 @@
* char ucData[ 20 ];
* } xMessage;
*
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
*
* void vATask( void *pvParameters )
* {
@@ -375,7 +375,7 @@
* is full. The time is defined in tick periods so the constant
* portTICK_PERIOD_MS should be used to convert to real time if this is required.
*
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
*
* Example usage:
* @code{c}
@@ -385,7 +385,7 @@
* char ucData[ 20 ];
* } xMessage;
*
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
*
* void vATask( void *pvParameters )
* {
@@ -460,7 +460,7 @@
* queue is full. The time is defined in tick periods so the constant
* portTICK_PERIOD_MS should be used to convert to real time if this is required.
*
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
*
* Example usage:
* @code{c}
@@ -470,7 +470,7 @@
* char ucData[ 20 ];
* } xMessage;
*
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
*
* void vATask( void *pvParameters )
* {
@@ -633,7 +633,7 @@
* item at the back of the queue, or queueSEND_TO_FRONT to place the item
* at the front of the queue (for high priority messages).
*
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
*
* Example usage:
* @code{c}
@@ -643,7 +643,7 @@
* char ucData[ 20 ];
* } xMessage;
*
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
*
* void vATask( void *pvParameters )
* {
@@ -723,8 +723,8 @@
* xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
* is empty.
*
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise errQUEUE_EMPTY.
*
* Example usage:
* @code{c}
@@ -811,8 +811,8 @@
* @param pvBuffer Pointer to the buffer into which the received item will
* be copied.
*
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise pdFAIL.
*
* \defgroup xQueuePeekFromISR xQueuePeekFromISR
* \ingroup QueueManagement
@@ -852,8 +852,8 @@
* constant portTICK_PERIOD_MS should be used to convert to real time if this is
* required.
*
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise errQUEUE_EMPTY.
*
* Example usage:
* @code{c}
@@ -995,10 +995,10 @@
* @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
* *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
* to unblock, and the unblocked task has a priority higher than the currently
- * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * running task. If xQueueSendToFrontFromISR() sets this value to pdTRUE then
* a context switch should be requested before the interrupt is exited.
*
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
* errQUEUE_FULL.
*
* Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1070,7 +1070,7 @@
* running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then
* a context switch should be requested before the interrupt is exited.
*
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
* errQUEUE_FULL.
*
* Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1185,9 +1185,12 @@
* {
* // Writing to the queue caused a task to unblock and the unblocked task
* // has a priority higher than or equal to the priority of the currently
- * // executing task (the task this interrupt interrupted). Perform a context
+ * // executing task (the task this interrupt interrupted). Perform a context
* // switch so this interrupt returns directly to the unblocked task.
- * portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ * // The macro used is port specific and will be either
+ * // portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to the documentation
+ * // page for the port being used.
+ * portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
* }
* }
* @endcode
@@ -1232,7 +1235,7 @@
* running task. If xQueueSendFromISR() sets this value to pdTRUE then
* a context switch should be requested before the interrupt is exited.
*
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
* errQUEUE_FULL.
*
* Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1260,8 +1263,11 @@
* // Now the buffer is empty we can switch context if necessary.
* if( xHigherPriorityTaskWoken )
* {
- * // Actual macro used here is port specific.
- * portYIELD_FROM_ISR ();
+ * // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ * // switch should be requested. The macro used is port specific and
+ * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ * // refer to the documentation page for the port being used.
+ * portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
* }
* }
* @endcode
@@ -1312,7 +1318,7 @@
* item at the back of the queue, or queueSEND_TO_FRONT to place the item
* at the front of the queue (for high priority messages).
*
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
* errQUEUE_FULL.
*
* Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1337,11 +1343,14 @@
*
* } while( portINPUT_BYTE( BUFFER_COUNT ) );
*
- * // Now the buffer is empty we can switch context if necessary. Note that the
- * // name of the yield function required is port specific.
+ * // Now the buffer is empty we can switch context if necessary.
* if( xHigherPriorityTaskWokenByPost )
* {
- * portYIELD_FROM_ISR();
+ * // As xHigherPriorityTaskWokenByPost is now set to pdTRUE then a context
+ * // switch should be requested. The macro used is port specific and
+ * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ * // refer to the documentation page for the port being used.
+ * portYIELD_FROM_ISR( xHigherPriorityTaskWokenByPost );
* }
* }
* @endcode
@@ -1380,8 +1389,8 @@
* to unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
* remain unchanged.
*
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise pdFAIL.
*
* Example usage:
* @code{c}
@@ -1455,6 +1464,8 @@
BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#if ( configUSE_CO_ROUTINES == 1 )
+
/*
* The functions defined above are for passing data to and from tasks. The
* functions below are the equivalents for passing data to and from
@@ -1464,18 +1475,20 @@
* should not be called directly from application code. Instead use the macro
* wrappers defined within croutine.h.
*/
-BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
- const void * pvItemToQueue,
- BaseType_t xCoRoutinePreviouslyWoken );
-BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
- void * pvBuffer,
- BaseType_t * pxTaskWoken );
-BaseType_t xQueueCRSend( QueueHandle_t xQueue,
- const void * pvItemToQueue,
- TickType_t xTicksToWait );
-BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
- void * pvBuffer,
- TickType_t xTicksToWait );
+ BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ BaseType_t xCoRoutinePreviouslyWoken );
+ BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
+ void * pvBuffer,
+ BaseType_t * pxTaskWoken );
+ BaseType_t xQueueCRSend( QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ TickType_t xTicksToWait );
+ BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
+ void * pvBuffer,
+ TickType_t xTicksToWait );
+
+#endif /* if ( configUSE_CO_ROUTINES == 1 ) */
/*
* For internal use only. Use xSemaphoreCreateMutex(),
@@ -1483,21 +1496,34 @@
* these functions directly.
*/
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
- StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
- const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
- const UBaseType_t uxInitialCount,
- StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
+ StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_COUNTING_SEMAPHORES == 1 )
+ QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+ const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+ const UBaseType_t uxInitialCount,
+ StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+ TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+ TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+#endif
/*
- * For internal use only. Use xSemaphoreTakeMutexRecursive() or
- * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ * For internal use only. Use xSemaphoreTakeRecursive() or
+ * xSemaphoreGiveRecursive() instead of calling these functions directly.
*/
BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
@@ -1537,7 +1563,7 @@
*/
#if ( configQUEUE_REGISTRY_SIZE > 0 )
void vQueueAddToRegistry( QueueHandle_t xQueue,
- const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcQueueName ) PRIVILEGED_FUNCTION;
#endif
/*
@@ -1566,7 +1592,7 @@
* returned.
*/
#if ( configQUEUE_REGISTRY_SIZE > 0 )
- const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
#endif
/*
@@ -1612,14 +1638,14 @@
* See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
* function.
*
- * A queue set must be explicitly created using a call to xQueueCreateSet()
- * before it can be used. Once created, standard FreeRTOS queues and semaphores
- * can be added to the set using calls to xQueueAddToSet().
- * xQueueSelectFromSet() is then used to determine which, if any, of the queues
- * or semaphores contained in the set is in a state where a queue read or
- * semaphore take operation would be successful.
+ * A queue set must be explicitly created using a call to xQueueCreateSet() or
+ * xQueueCreateSetStatic() before it can be used. Once created, standard
+ * FreeRTOS queues and semaphores can be added to the set using calls to
+ * xQueueAddToSet(). xQueueSelectFromSet() is then used to determine which, if
+ * any, of the queues or semaphores contained in the set is in a state where a
+ * queue read or semaphore take operation would be successful.
*
- * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * Note 1: See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
* for reasons why queue sets are very rarely needed in practice as there are
* simpler methods of blocking on multiple objects.
*
@@ -1653,11 +1679,73 @@
* @return If the queue set is created successfully then a handle to the created
* queue set is returned. Otherwise NULL is returned.
*/
-QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * or xQueueCreateSetStatic() before it can be used. Once created, standard
+ * FreeRTOS queues and semaphores can be added to the set using calls to
+ * xQueueAddToSet(). xQueueSelectFromSet() is then used to determine which, if
+ * any, of the queues or semaphores contained in the set is in a state where a
+ * queue read or semaphore take operation would be successful.
+ *
+ * Note 1: See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2: Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3: An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set. Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4: A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set. uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once. To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value. Examples:
+ * + If a queue set is to hold a queue of length 5, another queue of length 12,
+ * and a binary semaphore, then uxEventQueueLength should be set to
+ * (5 + 12 + 1), or 18.
+ * + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ * should be set to (1 + 1 + 1 ), or 3.
+ * + If a queue set is to hold a counting semaphore that has a maximum count of
+ * 5, and a counting semaphore that has a maximum count of 3, then
+ * uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @param pucQueueStorage pucQueueStorage must point to a uint8_t array that is
+ * at least large enough to hold uxEventQueueLength events.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned. If pxQueueBuffer is NULL then NULL is returned.
+ */
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ QueueSetHandle_t xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+ uint8_t * pucQueueStorage,
+ StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
/*
* Adds a queue or semaphore to a queue set that was previously created by a
- * call to xQueueCreateSet().
+ * call to xQueueCreateSet() or xQueueCreateSetStatic().
*
* See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
* function.
@@ -1677,8 +1765,10 @@
* queue set because it is already a member of a different queue set then pdFAIL
* is returned.
*/
-BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
- QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+ BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
/*
* Removes a queue or semaphore from a queue set. A queue or semaphore can only
@@ -1697,8 +1787,10 @@
* then pdPASS is returned. If the queue was not in the queue set, or the
* queue (or semaphore) was not empty, then pdFAIL is returned.
*/
-BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
- QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
/*
* xQueueSelectFromSet() selects from the members of a queue set a queue or
@@ -1710,7 +1802,7 @@
* See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
* function.
*
- * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * Note 1: See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
* for reasons why queue sets are very rarely needed in practice as there are
* simpler methods of blocking on multiple objects.
*
@@ -1734,13 +1826,17 @@
* in the queue set that is available, or NULL if no such queue or semaphore
* exists before before the specified block time expires.
*/
-QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
- const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+ QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
/*
* A version of xQueueSelectFromSet() that can be used from an ISR.
*/
-QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+ QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
/* Not public API functions. */
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
@@ -1748,10 +1844,20 @@
const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
-void vQueueSetQueueNumber( QueueHandle_t xQueue,
- UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+ void vQueueSetQueueNumber( QueueHandle_t xQueue,
+ UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+ uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
diff --git a/Source/include/semphr.h b/Source/include/semphr.h
index 46ac85a..4767514 100644
--- a/Source/include/semphr.h
+++ b/Source/include/semphr.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -1193,7 +1193,8 @@
/**
* semphr.h
* @code{c}
- * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore );
+ * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore,
+ * StaticSemaphore_t ** ppxSemaphoreBuffer );
* @endcode
*
* Retrieve pointer to a statically created binary semaphore, counting semaphore,
diff --git a/Source/include/stack_macros.h b/Source/include/stack_macros.h
index 354400d..20acaf3 100644
--- a/Source/include/stack_macros.h
+++ b/Source/include/stack_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,60 +53,78 @@
#define portSTACK_LIMIT_PADDING 0
#endif
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+/* Stack overflow check is not straight forward to implement for MPU ports
+ * because of the following reasons:
+ * 1. The context is stored in TCB and as a result, pxTopOfStack member points
+ * to the context location in TCB.
+ * 2. System calls are executed on a separate privileged only stack.
+ *
+ * It is still okay because an MPU region is used to protect task stack which
+ * means task stack overflow will trigger an MPU fault for unprivileged tasks.
+ * Additionally, architectures with hardware stack overflow checking support
+ * (such as Armv8-M) will trigger a fault when a task's stack overflows.
+ */
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
/* Only the current stack state is to be checked. */
- #define taskCHECK_FOR_STACK_OVERFLOW() \
- do { \
- /* Is the currently saved stack pointer within the stack limit? */ \
- if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \
- { \
- vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
- } \
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ do \
+ { \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \
+ { \
+ char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+ } \
} while( 0 )
#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
/* Only the current stack state is to be checked. */
- #define taskCHECK_FOR_STACK_OVERFLOW() \
- do { \
- \
- /* Is the currently saved stack pointer within the stack limit? */ \
- if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
- { \
- vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
- } \
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ do \
+ { \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
+ { \
+ char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+ } \
} while( 0 )
#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
- #define taskCHECK_FOR_STACK_OVERFLOW() \
- do { \
- const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
- const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \
- \
- if( ( pulStack[ 0 ] != ulCheckValue ) || \
- ( pulStack[ 1 ] != ulCheckValue ) || \
- ( pulStack[ 2 ] != ulCheckValue ) || \
- ( pulStack[ 3 ] != ulCheckValue ) ) \
- { \
- vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
- } \
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ do \
+ { \
+ const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
+ const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U; \
+ \
+ if( ( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) || \
+ ( pulStack[ 0 ] != ulCheckValue ) || \
+ ( pulStack[ 1 ] != ulCheckValue ) || \
+ ( pulStack[ 2 ] != ulCheckValue ) || \
+ ( pulStack[ 3 ] != ulCheckValue ) ) \
+ { \
+ char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+ } \
} while( 0 )
#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
/*-----------------------------------------------------------*/
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
#define taskCHECK_FOR_STACK_OVERFLOW() \
- do { \
+ do \
+ { \
int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \
static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
@@ -114,13 +132,13 @@
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
\
- \
pcEndOfStack -= sizeof( ucExpectedStackBytes ); \
\
- /* Has the extremity of the task stack ever been written over? */ \
- if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
+ if( ( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) || \
+ ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) ) \
{ \
- vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
} \
} while( 0 )
diff --git a/Source/include/stdint.readme b/Source/include/stdint.readme
index 11664f3..517a77e 100644
--- a/Source/include/stdint.readme
+++ b/Source/include/stdint.readme
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/include/stream_buffer.h b/Source/include/stream_buffer.h
index 48ca266..b257b82 100644
--- a/Source/include/stream_buffer.h
+++ b/Source/include/stream_buffer.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -40,12 +40,12 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section section and set the
- * receive block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
*/
@@ -63,6 +63,13 @@
/* *INDENT-ON* */
/**
+ * Type of stream buffer. For internal use only.
+ */
+#define sbTYPE_STREAM_BUFFER ( ( BaseType_t ) 0 )
+#define sbTYPE_MESSAGE_BUFFER ( ( BaseType_t ) 1 )
+#define sbTYPE_STREAM_BATCHING_BUFFER ( ( BaseType_t ) 2 )
+
+/**
* Type by which stream buffers are referenced. For example, a call to
* xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
* then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
@@ -91,6 +98,8 @@
*
* configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
* FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferCreate() to be available.
*
* @param xBufferSizeBytes The total number of bytes the stream buffer will be
* able to hold at any one time.
@@ -155,11 +164,11 @@
*/
#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
- xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL )
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, NULL, NULL )
#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
#define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
- xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif
/**
@@ -167,15 +176,17 @@
*
* @code{c}
* StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
- * size_t xTriggerLevelBytes,
- * uint8_t *pucStreamBufferStorageArea,
- * StaticStreamBuffer_t *pxStaticStreamBuffer );
+ * size_t xTriggerLevelBytes,
+ * uint8_t *pucStreamBufferStorageArea,
+ * StaticStreamBuffer_t *pxStaticStreamBuffer );
* @endcode
* Creates a new stream buffer using statically allocated memory. See
* xStreamBufferCreate() for a version that uses dynamically allocated memory.
*
* configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
- * xStreamBufferCreateStatic() to be available.
+ * xStreamBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS must be
+ * set to 1 in for FreeRTOSConfig.h for xStreamBufferCreateStatic() to be
+ * available.
*
* @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
* pucStreamBufferStorageArea parameter.
@@ -253,11 +264,199 @@
*/
#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
- xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
#define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
- xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBatchingBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ * @endcode
+ *
+ * Creates a new stream batching buffer using dynamically allocated memory. See
+ * xStreamBatchingBufferCreateStatic() for a version that uses statically
+ * allocated memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBatchingBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBatchingBufferCreate() to be available.
+ *
+ * The difference between a stream buffer and a stream batching buffer is when
+ * a task performs read on a non-empty buffer:
+ * - The task reading from a non-empty stream buffer returns immediately
+ * regardless of the amount of data in the buffer.
+ * - The task reading from a non-empty steam batching buffer blocks until the
+ * amount of data in the buffer exceeds the trigger level or the block time
+ * expires.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream batching buffer
+ * will be able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * batching buffer to unblock a task calling xStreamBufferReceive before the
+ * block time expires.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least
+ * equal to trigger level is sent to the stream batching buffer. If the
+ * parameter is NULL, it will use the default implementation provided by
+ * sbSEND_COMPLETED macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK
+ * must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
+ * are read from a stream batching buffer. If the parameter is NULL, it will use
+ * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
+ * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
+ * FreeRTOSConfig.h.
+ *
+ * @return If NULL is returned, then the stream batching buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream batching buffer data structures and storage area. A non-NULL value
+ * being returned indicates that the stream batching buffer has been created
+ * successfully - the returned value should be stored as the handle to the
+ * created stream batching buffer.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBatchingBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ * // Create a stream batching buffer that can hold 100 bytes. The memory used
+ * // to hold both the stream batching buffer structure and the data in the stream
+ * // batching buffer is allocated dynamically.
+ * xStreamBatchingBuffer = xStreamBatchingBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ * if( xStreamBatchingBuffer == NULL )
+ * {
+ * // There was not enough heap memory space available to create the
+ * // stream batching buffer.
+ * }
+ * else
+ * {
+ * // The stream batching buffer was created successfully and can now be used.
+ * }
+ * }
+ * @endcode
+ * \defgroup xStreamBatchingBufferCreate xStreamBatchingBufferCreate
+ * \ingroup StreamBatchingBufferManagement
+ */
+
+#define xStreamBatchingBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define xStreamBatchingBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBatchingBufferCreateStatic( size_t xBufferSizeBytes,
+ * size_t xTriggerLevelBytes,
+ * uint8_t *pucStreamBufferStorageArea,
+ * StaticStreamBuffer_t *pxStaticStreamBuffer );
+ * @endcode
+ * Creates a new stream batching buffer using statically allocated memory. See
+ * xStreamBatchingBufferCreate() for a version that uses dynamically allocated
+ * memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBatchingBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS
+ * must be set to 1 in for FreeRTOSConfig.h for xStreamBatchingBufferCreateStatic()
+ * to be available.
+ *
+ * The difference between a stream buffer and a stream batching buffer is when
+ * a task performs read on a non-empty buffer:
+ * - The task reading from a non-empty stream buffer returns immediately
+ * regardless of the amount of data in the buffer.
+ * - The task reading from a non-empty steam batching buffer blocks until the
+ * amount of data in the buffer exceeds the trigger level or the block time
+ * expires.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * batching buffer to unblock a task calling xStreamBufferReceive before the
+ * block time expires.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes big. This is the array to which streams are
+ * copied when they are written to the stream batching buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream batching buffer's
+ * data structure.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least
+ * equal to trigger level is sent to the stream batching buffer. If the parameter
+ * is NULL, it will use the default implementation provided by sbSEND_COMPLETED
+ * macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK must be set to
+ * 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
+ * are read from a stream batching buffer. If the parameter is NULL, it will use
+ * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
+ * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
+ * FreeRTOSConfig.h.
+ *
+ * @return If the stream batching buffer is created successfully then a handle
+ * to the created stream batching buffer is returned. If either pucStreamBufferStorageArea
+ * or pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * // Used to dimension the array used to hold the streams. The available space
+ * // will actually be one less than this, so 999.
+ * #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // batching buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream batching buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBatchingBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ * xStreamBatchingBuffer = xStreamBatchingBufferCreateStatic( sizeof( ucStorageBuffer ),
+ * xTriggerLevel,
+ * ucStorageBuffer,
+ * &xStreamBufferStruct );
+ *
+ * // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ * // parameters were NULL, xStreamBatchingBuffer will not be NULL, and can be
+ * // used to reference the created stream batching buffer in other stream
+ * // buffer API calls.
+ *
+ * // Other code that uses the stream batching buffer can go here.
+ * }
+ *
+ * @endcode
+ * \defgroup xStreamBatchingBufferCreateStatic xStreamBatchingBufferCreateStatic
+ * \ingroup StreamBatchingBufferManagement
+ */
+
+#define xStreamBatchingBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define xStreamBatchingBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif
/**
@@ -273,6 +472,9 @@
* buffer and storage area buffer. These are the same buffers that are supplied
* at the time of creation.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferGetStaticBuffers() to be available.
+ *
* @param xStreamBuffer The stream buffer for which to retrieve the buffers.
*
* @param ppucStreamBufferStorageArea Used to return a pointer to the stream
@@ -297,9 +499,9 @@
*
* @code{c}
* size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- * const void *pvTxData,
- * size_t xDataLengthBytes,
- * TickType_t xTicksToWait );
+ * const void *pvTxData,
+ * size_t xDataLengthBytes,
+ * TickType_t xTicksToWait );
* @endcode
*
* Sends bytes to a stream buffer. The bytes are copied into the stream buffer.
@@ -312,17 +514,20 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Use xStreamBufferSend() to write to a stream buffer from a task. Use
* xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
* service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSend() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer to which a stream is
* being sent.
*
@@ -394,9 +599,9 @@
*
* @code{c}
* size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
- * const void *pvTxData,
- * size_t xDataLengthBytes,
- * BaseType_t *pxHigherPriorityTaskWoken );
+ * const void *pvTxData,
+ * size_t xDataLengthBytes,
+ * BaseType_t *pxHigherPriorityTaskWoken );
* @endcode
*
* Interrupt safe version of the API function that sends a stream of bytes to
@@ -410,17 +615,20 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Use xStreamBufferSend() to write to a stream buffer from a task. Use
* xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
* service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSendFromISR() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer to which a stream is
* being sent.
*
@@ -495,9 +703,9 @@
*
* @code{c}
* size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- * void *pvRxData,
- * size_t xBufferLengthBytes,
- * TickType_t xTicksToWait );
+ * void *pvRxData,
+ * size_t xBufferLengthBytes,
+ * TickType_t xTicksToWait );
* @endcode
*
* Receives bytes from a stream buffer.
@@ -510,17 +718,20 @@
* writer and reader to be different tasks or interrupts, but, unlike other
* FreeRTOS objects, it is not safe to have multiple different writers or
* multiple different readers. If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0. Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()). Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()). One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
*
* Use xStreamBufferReceive() to read from a stream buffer from a task. Use
* xStreamBufferReceiveFromISR() to read from a stream buffer from an
* interrupt service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceive() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer from which bytes are to
* be received.
*
@@ -584,9 +795,9 @@
*
* @code{c}
* size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
- * void *pvRxData,
- * size_t xBufferLengthBytes,
- * BaseType_t *pxHigherPriorityTaskWoken );
+ * void *pvRxData,
+ * size_t xBufferLengthBytes,
+ * BaseType_t *pxHigherPriorityTaskWoken );
* @endcode
*
* An interrupt safe version of the API function that receives bytes from a
@@ -596,6 +807,9 @@
* Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
* interrupt service routine (ISR).
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceiveFromISR() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer from which a stream
* is being received.
*
@@ -680,6 +894,9 @@
* A stream buffer handle must not be used after the stream buffer has been
* deleted.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vStreamBufferDelete() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer to be deleted.
*
* \defgroup vStreamBufferDelete vStreamBufferDelete
@@ -697,6 +914,9 @@
* Queries a stream buffer to see if it is full. A stream buffer is full if it
* does not have any free space, and therefore cannot accept any more data.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferIsFull() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer being queried.
*
* @return If the stream buffer is full then pdTRUE is returned. Otherwise
@@ -717,6 +937,9 @@
* Queries a stream buffer to see if it is empty. A stream buffer is empty if
* it does not contain any data.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferIsEmpty() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer being queried.
*
* @return If the stream buffer is empty then pdTRUE is returned. Otherwise
@@ -739,6 +962,13 @@
* are no tasks blocked waiting to either send to or receive from the stream
* buffer.
*
+ * Use xStreamBufferReset() to reset a stream buffer from a task.
+ * Use xStreamBufferResetFromISR() to reset a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReset() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer being reset.
*
* @return If the stream buffer is reset then pdPASS is returned. If there was
@@ -754,6 +984,38 @@
* stream_buffer.h
*
* @code{c}
+ * BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that resets the stream buffer.
+ *
+ * Resets a stream buffer to its initial, empty, state. Any data that was in
+ * the stream buffer is discarded. A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * Use xStreamBufferReset() to reset a stream buffer from a task.
+ * Use xStreamBufferResetFromISR() to reset a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferResetFromISR() to be available.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned. If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferResetFromISR xStreamBufferResetFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
* size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
* @endcode
*
@@ -761,6 +1023,9 @@
* equal to the amount of data that can be sent to the stream buffer before it
* is full.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSpacesAvailable() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer being queried.
*
* @return The number of bytes that can be written to the stream buffer before
@@ -782,6 +1047,9 @@
* the number of bytes that can be read from the stream buffer before the stream
* buffer would be empty.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferBytesAvailable() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer being queried.
*
* @return The number of bytes that can be read from the stream buffer before
@@ -816,6 +1084,9 @@
* A trigger level is set when the stream buffer is created, and can be modified
* using xStreamBufferSetTriggerLevel().
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSetTriggerLevel() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer being updated.
*
* @param xTriggerLevel The new trigger level for the stream buffer.
@@ -850,6 +1121,9 @@
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
* additional information.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSendCompletedFromISR() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer to which data was
* written.
*
@@ -891,6 +1165,9 @@
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
* additional information.
*
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceiveCompletedFromISR() to be available.
+ *
* @param xStreamBuffer The handle of the stream buffer from which data was
* read.
*
@@ -911,21 +1188,79 @@
BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Get the task notification index used for the supplied stream buffer which can
+ * be set using vStreamBufferSetStreamBufferNotificationIndex. If the task
+ * notification index for the stream buffer is not changed using
+ * vStreamBufferSetStreamBufferNotificationIndex, this function returns the
+ * default value (tskDEFAULT_INDEX_TO_NOTIFY).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * uxStreamBufferGetStreamBufferNotificationIndex() to be available.
+ *
+ * @param xStreamBuffer The handle of the stream buffer for which the task
+ * notification index is retrieved.
+ *
+ * @return The task notification index for the stream buffer.
+ *
+ * \defgroup uxStreamBufferGetStreamBufferNotificationIndex uxStreamBufferGetStreamBufferNotificationIndex
+ * \ingroup StreamBufferManagement
+ */
+UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * void vStreamBufferSetStreamBufferNotificationIndex ( StreamBuffer_t xStreamBuffer, UBaseType_t uxNotificationIndex );
+ * @endcode
+ *
+ * Set the task notification index used for the supplied stream buffer.
+ * Successive calls to stream buffer APIs (like xStreamBufferSend or
+ * xStreamBufferReceive) for this stream buffer will use this new index for
+ * their task notifications.
+ *
+ * If this function is not called, the default index (tskDEFAULT_INDEX_TO_NOTIFY)
+ * is used for task notifications. It is recommended to call this function
+ * before attempting to send or receive data from the stream buffer to avoid
+ * inconsistencies.
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vStreamBufferSetStreamBufferNotificationIndex() to be available.
+ *
+ * @param xStreamBuffer The handle of the stream buffer for which the task
+ * notification index is set.
+ *
+ * @param uxNotificationIndex The task notification index to set.
+ *
+ * \defgroup vStreamBufferSetStreamBufferNotificationIndex vStreamBufferSetStreamBufferNotificationIndex
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer,
+ UBaseType_t uxNotificationIndex ) PRIVILEGED_FUNCTION;
+
/* Functions below here are not part of the public API. */
StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
+ BaseType_t xStreamBufferType,
StreamBufferCallbackFunction_t pxSendCompletedCallback,
StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
-
-StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
- size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
- uint8_t * const pucStreamBufferStorageArea,
- StaticStreamBuffer_t * const pxStaticStreamBuffer,
- StreamBufferCallbackFunction_t pxSendCompletedCallback,
- StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ BaseType_t xStreamBufferType,
+ uint8_t * const pucStreamBufferStorageArea,
+ StaticStreamBuffer_t * const pxStaticStreamBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+#endif
size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
diff --git a/Source/include/task.h b/Source/include/task.h
index 1207e18..b910197 100644
--- a/Source/include/task.h
+++ b/Source/include/task.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,30 +53,33 @@
* The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
* values will reflect the last released version number.
*/
-#define tskKERNEL_VERSION_NUMBER "V10.6.2"
-#define tskKERNEL_VERSION_MAJOR 10
-#define tskKERNEL_VERSION_MINOR 6
-#define tskKERNEL_VERSION_BUILD 2
+#define tskKERNEL_VERSION_NUMBER "V11.2.0"
+#define tskKERNEL_VERSION_MAJOR 11
+#define tskKERNEL_VERSION_MINOR 2
+#define tskKERNEL_VERSION_BUILD 0
/* MPU region parameters passed in ulParameters
* of MemoryRegion_t struct. */
-#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL )
-#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL )
-#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL )
-#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL )
-#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL )
+#define tskMPU_REGION_READ_ONLY ( 1U << 0U )
+#define tskMPU_REGION_READ_WRITE ( 1U << 1U )
+#define tskMPU_REGION_EXECUTE_NEVER ( 1U << 2U )
+#define tskMPU_REGION_NORMAL_MEMORY ( 1U << 3U )
+#define tskMPU_REGION_DEVICE_MEMORY ( 1U << 4U )
+#if defined( portARMV8M_MINOR_VERSION ) && ( portARMV8M_MINOR_VERSION >= 1 )
+ #define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ( 1U << 5U )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* MPU region permissions stored in MPU settings to
* authorize access requests. */
-#define tskMPU_READ_PERMISSION ( 1UL << 0UL )
-#define tskMPU_WRITE_PERMISSION ( 1UL << 1UL )
+#define tskMPU_READ_PERMISSION ( 1U << 0U )
+#define tskMPU_WRITE_PERMISSION ( 1U << 1U )
/* The direct to task notification feature used to have only a single notification
* per task. Now there is an array of notifications per task that is dimensioned by
* configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the
* original direct to task notification defaults to using the first index in the
* array. */
-#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 )
+#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 )
/**
* task. h
@@ -89,13 +92,14 @@
* \ingroup Tasks
*/
struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tskTaskControlBlock * TaskHandle_t;
+typedef struct tskTaskControlBlock * TaskHandle_t;
+typedef const struct tskTaskControlBlock * ConstTaskHandle_t;
/*
* Defines the prototype to which the application task hook function must
* conform.
*/
-typedef BaseType_t (* TaskHookFunction_t)( void * );
+typedef BaseType_t (* TaskHookFunction_t)( void * arg );
/* Task states returned by eTaskGetState. */
typedef enum
@@ -143,7 +147,7 @@
typedef struct xTASK_PARAMETERS
{
TaskFunction_t pvTaskCode;
- const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcName;
configSTACK_DEPTH_TYPE usStackDepth;
void * pvParameters;
UBaseType_t uxPriority;
@@ -159,26 +163,30 @@
typedef struct xTASK_STATUS
{
TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */
- const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- UBaseType_t xTaskNumber; /* A number unique to the task. */
+ const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */
+ UBaseType_t xTaskNumber; /* A number unique to the task. Note that this is not the task number that may be modified using vTaskSetTaskNumber() and uxTaskGetTaskNumber(), but a separate TCB-specific and unique identifier automatically assigned on task generation. */
eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */
UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */
UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */
- #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
StackType_t * pxTopOfStack; /* Points to the top address of the task's stack area. */
StackType_t * pxEndOfStack; /* Points to the end address of the task's stack area. */
#endif
configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */
+ #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+ UBaseType_t uxCoreAffinityMask; /* The core affinity mask for the task */
+ #endif
} TaskStatus_t;
/* Possible return values for eTaskConfirmSleepModeStatus(). */
typedef enum
{
- eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
- eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */
+ eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+ eStandardSleep /* Enter a sleep mode that will not last any longer than the expected idle time. */
#if ( INCLUDE_vTaskSuspend == 1 )
+ ,
eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
#endif /* INCLUDE_vTaskSuspend */
} eSleepModeStatus;
@@ -191,6 +199,13 @@
#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U )
/**
+ * Defines affinity to all available cores.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskNO_AFFINITY ( ( UBaseType_t ) -1 )
+
+/**
* task. h
*
* Macro for forcing a context switch.
@@ -198,7 +213,7 @@
* \defgroup taskYIELD taskYIELD
* \ingroup SchedulerControl
*/
-#define taskYIELD() portYIELD()
+#define taskYIELD() portYIELD()
/**
* task. h
@@ -212,8 +227,12 @@
* \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
* \ingroup SchedulerControl
*/
-#define taskENTER_CRITICAL() portENTER_CRITICAL()
-#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+#define taskENTER_CRITICAL() portENTER_CRITICAL()
+#if ( configNUMBER_OF_CORES == 1 )
+ #define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+#else
+ #define taskENTER_CRITICAL_FROM_ISR() portENTER_CRITICAL_FROM_ISR()
+#endif
/**
* task. h
@@ -227,8 +246,12 @@
* \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
* \ingroup SchedulerControl
*/
-#define taskEXIT_CRITICAL() portEXIT_CRITICAL()
-#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+#define taskEXIT_CRITICAL() portEXIT_CRITICAL()
+#if ( configNUMBER_OF_CORES == 1 )
+ #define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+#else
+ #define taskEXIT_CRITICAL_FROM_ISR( x ) portEXIT_CRITICAL_FROM_ISR( x )
+#endif
/**
* task. h
@@ -238,7 +261,7 @@
* \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
* \ingroup SchedulerControl
*/
-#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()
+#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()
/**
* task. h
@@ -248,7 +271,7 @@
* \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
* \ingroup SchedulerControl
*/
-#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()
+#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()
/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is
* 0 to generate more optimal code when configASSERT() is defined as the constant
@@ -257,6 +280,8 @@
#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 )
#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 )
+/* Checks if core ID is valid. */
+#define taskVALID_CORE_ID( xCoreID ) ( ( ( ( ( BaseType_t ) 0 <= ( xCoreID ) ) && ( ( xCoreID ) < ( BaseType_t ) configNUMBER_OF_CORES ) ) ) ? ( pdTRUE ) : ( pdFALSE ) )
/*-----------------------------------------------------------
* TASK CREATION API
@@ -267,8 +292,8 @@
* @code{c}
* BaseType_t xTaskCreate(
* TaskFunction_t pxTaskCode,
- * const char *pcName,
- * configSTACK_DEPTH_TYPE usStackDepth,
+ * const char * const pcName,
+ * const configSTACK_DEPTH_TYPE uxStackDepth,
* void *pvParameters,
* UBaseType_t uxPriority,
* TaskHandle_t *pxCreatedTask
@@ -302,9 +327,9 @@
* facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default
* is 16.
*
- * @param usStackDepth The size of the task stack specified as the number of
+ * @param uxStackDepth The size of the task stack specified as the number of
* variables the stack can hold - not the number of bytes. For example, if
- * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * the stack is 16 bits wide and uxStackDepth is defined as 100, 200 bytes
* will be allocated for stack storage.
*
* @param pvParameters Pointer that will be used as the parameter for the task
@@ -358,19 +383,29 @@
*/
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
- const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- const configSTACK_DEPTH_TYPE usStackDepth,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ UBaseType_t uxCoreAffinityMask,
+ TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
/**
* task. h
* @code{c}
* TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
- * const char *pcName,
- * uint32_t ulStackDepth,
+ * const char * const pcName,
+ * const configSTACK_DEPTH_TYPE uxStackDepth,
* void *pvParameters,
* UBaseType_t uxPriority,
* StackType_t *puxStackBuffer,
@@ -396,9 +431,9 @@
* facilitate debugging. The maximum length of the string is defined by
* configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
*
- * @param ulStackDepth The size of the task stack specified as the number of
+ * @param uxStackDepth The size of the task stack specified as the number of
* variables the stack can hold - not the number of bytes. For example, if
- * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * the stack is 32-bits wide and uxStackDepth is defined as 100 then 400 bytes
* will be allocated for stack storage.
*
* @param pvParameters Pointer that will be used as the parameter for the task
@@ -407,7 +442,7 @@
* @param uxPriority The priority at which the task will run.
*
* @param puxStackBuffer Must point to a StackType_t array that has at least
- * ulStackDepth indexes - the array will then be used as the task's stack,
+ * uxStackDepth indexes - the array will then be used as the task's stack,
* removing the need for the stack to be allocated dynamically.
*
* @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
@@ -441,7 +476,7 @@
* {
* // The parameter value is expected to be 1 as 1 is passed in the
* // pvParameters value in the call to xTaskCreateStatic().
- * configASSERT( ( uint32_t ) pvParameters == 1UL );
+ * configASSERT( ( uint32_t ) pvParameters == 1U );
*
* for( ;; )
* {
@@ -475,14 +510,25 @@
*/
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
- const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- const uint32_t ulStackDepth,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
#endif /* configSUPPORT_STATIC_ALLOCATION */
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer,
+ UBaseType_t uxCoreAffinityMask ) PRIVILEGED_FUNCTION;
+#endif
+
/**
* task. h
* @code{c}
@@ -519,9 +565,9 @@
* {
* vATask, // pvTaskCode - the function that implements the task.
* "ATask", // pcName - just a text name for the task to assist debugging.
- * 100, // usStackDepth - the stack size DEFINED IN WORDS.
+ * 100, // uxStackDepth - the stack size DEFINED IN WORDS.
* NULL, // pvParameters - passed into the task function as the function parameters.
- * ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ * ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
* cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
*
* // xRegions - Allocate up to three separate memory regions for access by
@@ -561,6 +607,12 @@
TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+ UBaseType_t uxCoreAffinityMask,
+ TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
/**
* task. h
* @code{c}
@@ -607,9 +659,9 @@
* {
* vATask, // pvTaskCode - the function that implements the task.
* "ATask", // pcName - just a text name for the task to assist debugging.
- * 100, // usStackDepth - the stack size DEFINED IN WORDS.
+ * 100, // uxStackDepth - the stack size DEFINED IN WORDS.
* NULL, // pvParameters - passed into the task function as the function parameters.
- * ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ * ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
* cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
*
* // xRegions - Allocate up to three separate memory regions for access by
@@ -651,6 +703,12 @@
TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+ UBaseType_t uxCoreAffinityMask,
+ TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
/**
* task. h
* @code{c}
@@ -661,7 +719,7 @@
* a call to xTaskCreateRestricted(). These regions can be redefined using
* vTaskAllocateMPURegions().
*
- * @param xTask The handle of the task being updated.
+ * @param xTaskToModify The handle of the task being updated.
*
* @param[in] pxRegions A pointer to a MemoryRegion_t structure that contains the
* new memory region definitions.
@@ -698,8 +756,10 @@
* \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions
* \ingroup Tasks
*/
-void vTaskAllocateMPURegions( TaskHandle_t xTask,
- const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+#if ( portUSING_MPU_WRAPPERS == 1 )
+ void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+ const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -906,7 +966,9 @@
* \defgroup xTaskAbortDelay xTaskAbortDelay
* \ingroup TaskCtrl
*/
-BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -970,6 +1032,37 @@
/**
* task. h
* @code{c}
+ * UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * INCLUDE_uxTaskPriorityGet and configUSE_MUTEXES must be defined as 1 for this
+ * function to be available. See the configuration section for more information.
+ *
+ * Obtain the base priority of any task.
+ *
+ * @param xTask Handle of the task to be queried. Passing a NULL
+ * handle results in the base priority of the calling task being returned.
+ *
+ * @return The base priority of xTask.
+ *
+ * \defgroup uxTaskPriorityGet uxTaskBasePriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
+ * UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask );
+ * @endcode
+ *
+ * A version of uxTaskBasePriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * @code{c}
* eTaskState eTaskGetState( TaskHandle_t xTask );
* @endcode
*
@@ -985,7 +1078,9 @@
* state of the task might change between the function being called, and the
* functions return value being tested by the calling task.
*/
-eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+ eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -1043,10 +1138,12 @@
* \defgroup vTaskGetInfo vTaskGetInfo
* \ingroup TaskCtrl
*/
-void vTaskGetInfo( TaskHandle_t xTask,
- TaskStatus_t * pxTaskStatus,
- BaseType_t xGetFreeStackSpace,
- eTaskState eState ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+ void vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -1228,6 +1325,164 @@
*/
BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+#if ( configUSE_CORE_AFFINITY == 1 )
+
+/**
+ * @brief Sets the core affinity mask for a task.
+ *
+ * It sets the cores on which a task can run. configUSE_CORE_AFFINITY must
+ * be defined as 1 for this function to be available.
+ *
+ * @param xTask The handle of the task to set the core affinity mask for.
+ * Passing NULL will set the core affinity mask for the calling task.
+ *
+ * @param uxCoreAffinityMask A bitwise value that indicates the cores on
+ * which the task can run. Cores are numbered from 0 to configNUMBER_OF_CORES - 1.
+ * For example, to ensure that a task can run on core 0 and core 1, set
+ * uxCoreAffinityMask to 0x03.
+ *
+ * Example usage:
+ *
+ * // The function that creates task.
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * UBaseType_t uxCoreAffinityMask;
+ *
+ * // Create a task, storing the handle.
+ * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
+ *
+ * // Define the core affinity mask such that this task can only run
+ * // on core 0 and core 2.
+ * uxCoreAffinityMask = ( ( 1 << 0 ) | ( 1 << 2 ) );
+ *
+ * //Set the core affinity mask for the task.
+ * vTaskCoreAffinitySet( xHandle, uxCoreAffinityMask );
+ * }
+ */
+ void vTaskCoreAffinitySet( const TaskHandle_t xTask,
+ UBaseType_t uxCoreAffinityMask );
+#endif
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+
+/**
+ * @brief Gets the core affinity mask for a task.
+ *
+ * configUSE_CORE_AFFINITY must be defined as 1 for this function to be
+ * available.
+ *
+ * @param xTask The handle of the task to get the core affinity mask for.
+ * Passing NULL will get the core affinity mask for the calling task.
+ *
+ * @return The core affinity mask which is a bitwise value that indicates
+ * the cores on which a task can run. Cores are numbered from 0 to
+ * configNUMBER_OF_CORES - 1. For example, if a task can run on core 0 and core 1,
+ * the core affinity mask is 0x03.
+ *
+ * Example usage:
+ *
+ * // Task handle of the networking task - it is populated elsewhere.
+ * TaskHandle_t xNetworkingTaskHandle;
+ *
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * UBaseType_t uxNetworkingCoreAffinityMask;
+ *
+ * // Create a task, storing the handle.
+ * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
+ *
+ * //Get the core affinity mask for the networking task.
+ * uxNetworkingCoreAffinityMask = vTaskCoreAffinityGet( xNetworkingTaskHandle );
+ *
+ * // Here is a hypothetical scenario, just for the example. Assume that we
+ * // have 2 cores - Core 0 and core 1. We want to pin the application task to
+ * // the core different than the networking task to ensure that the
+ * // application task does not interfere with networking.
+ * if( ( uxNetworkingCoreAffinityMask & ( 1 << 0 ) ) != 0 )
+ * {
+ * // The networking task can run on core 0, pin our task to core 1.
+ * vTaskCoreAffinitySet( xHandle, ( 1 << 1 ) );
+ * }
+ * else
+ * {
+ * // Otherwise, pin our task to core 0.
+ * vTaskCoreAffinitySet( xHandle, ( 1 << 0 ) );
+ * }
+ * }
+ */
+ UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask );
+#endif
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+/**
+ * @brief Disables preemption for a task.
+ *
+ * @param xTask The handle of the task to disable preemption. Passing NULL
+ * disables preemption for the calling task.
+ *
+ * Example usage:
+ *
+ * void vTaskCode( void *pvParameters )
+ * {
+ * // Silence warnings about unused parameters.
+ * ( void ) pvParameters;
+ *
+ * for( ;; )
+ * {
+ * // ... Perform some function here.
+ *
+ * // Disable preemption for this task.
+ * vTaskPreemptionDisable( NULL );
+ *
+ * // The task will not be preempted when it is executing in this portion ...
+ *
+ * // ... until the preemption is enabled again.
+ * vTaskPreemptionEnable( NULL );
+ *
+ * // The task can be preempted when it is executing in this portion.
+ * }
+ * }
+ */
+ void vTaskPreemptionDisable( const TaskHandle_t xTask );
+#endif
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+/**
+ * @brief Enables preemption for a task.
+ *
+ * @param xTask The handle of the task to enable preemption. Passing NULL
+ * enables preemption for the calling task.
+ *
+ * Example usage:
+ *
+ * void vTaskCode( void *pvParameters )
+ * {
+ * // Silence warnings about unused parameters.
+ * ( void ) pvParameters;
+ *
+ * for( ;; )
+ * {
+ * // ... Perform some function here.
+ *
+ * // Disable preemption for this task.
+ * vTaskPreemptionDisable( NULL );
+ *
+ * // The task will not be preempted when it is executing in this portion ...
+ *
+ * // ... until the preemption is enabled again.
+ * vTaskPreemptionEnable( NULL );
+ *
+ * // The task can be preempted when it is executing in this portion.
+ * }
+ * }
+ */
+ void vTaskPreemptionEnable( const TaskHandle_t xTask );
+#endif
+
/*-----------------------------------------------------------
* SCHEDULER CONTROL
*----------------------------------------------------------*/
@@ -1494,7 +1749,7 @@
* \defgroup pcTaskGetName pcTaskGetName
* \ingroup TaskUtils
*/
-char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
/**
* task. h
@@ -1512,7 +1767,9 @@
* \defgroup pcTaskGetHandle pcTaskGetHandle
* \ingroup TaskUtils
*/
-TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+ TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -1571,7 +1828,9 @@
* actual spaces on the stack rather than bytes) since the task referenced by
* xTask was created.
*/
-UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
/**
* task.h
@@ -1600,7 +1859,9 @@
* actual spaces on the stack rather than bytes) since the task referenced by
* xTask was created.
*/
-configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
/* When using trace macros it is sometimes necessary to include task.h before
* FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined,
@@ -1679,6 +1940,9 @@
* @param xTask the task that just exceeded its stack boundaries.
* @param pcTaskName A character string containing the name of the offending task.
*/
+ /* MISRA Ref 8.6.1 [External linkage] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+ /* coverity[misra_c_2012_rule_8_6_violation] */
void vApplicationStackOverflowHook( TaskHandle_t xTask,
char * pcTaskName );
@@ -1697,6 +1961,9 @@
* the overhead of a separate task.
* NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK.
*/
+ /* MISRA Ref 8.6.1 [External linkage] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+ /* coverity[misra_c_2012_rule_8_6_violation] */
void vApplicationIdleHook( void );
#endif
@@ -1712,7 +1979,10 @@
*
* This hook function is called in the system tick handler after any OS work is completed.
*/
- void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+ /* MISRA Ref 8.6.1 [External linkage] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+ /* coverity[misra_c_2012_rule_8_6_violation] */
+ void vApplicationTickHook( void );
#endif
@@ -1721,7 +1991,7 @@
/**
* task.h
* @code{c}
- * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+ * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize )
* @endcode
*
* This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB. This function is required when
@@ -1729,12 +1999,43 @@
*
* @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
* @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
- * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
*/
void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
StackType_t ** ppxIdleTaskStackBuffer,
- uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
-#endif
+ configSTACK_DEPTH_TYPE * puxIdleTaskStackSize );
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize, BaseType_t xCoreID )
+ * @endcode
+ *
+ * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB. This function is required when
+ * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
+ *
+ * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
+ * 1. 1 Active idle task which does all the housekeeping.
+ * 2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
+ * These idle tasks are created to ensure that each core has an idle task to run when
+ * no other task is available to run.
+ *
+ * The function vApplicationGetPassiveIdleTaskMemory is called with passive idle
+ * task index 0, 1 ... ( configNUMBER_OF_CORES - 2 ) to get memory for passive idle
+ * tasks.
+ *
+ * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
+ * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
+ * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param xPassiveIdleTaskIndex The passive idle task index of the idle task buffer
+ */
+ #if ( configNUMBER_OF_CORES > 1 )
+ void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+ StackType_t ** ppxIdleTaskStackBuffer,
+ configSTACK_DEPTH_TYPE * puxIdleTaskStackSize,
+ BaseType_t xPassiveIdleTaskIndex );
+ #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/**
* task.h
@@ -1749,17 +2050,35 @@
* wants. The return value is the value returned by the task hook function
* registered by the user.
*/
-BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
- void * pvParameter ) PRIVILEGED_FUNCTION;
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+ void * pvParameter ) PRIVILEGED_FUNCTION;
+#endif
/**
* xTaskGetIdleTaskHandle() is only available if
* INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
*
- * Simply returns the handle of the idle task. It is not valid to call
- * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ * In single-core FreeRTOS, this function simply returns the handle of the idle
+ * task. It is not valid to call xTaskGetIdleTaskHandle() before the scheduler
+ * has been started.
+ *
+ * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
+ * 1. 1 Active idle task which does all the housekeeping.
+ * 2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
+ * These idle tasks are created to ensure that each core has an idle task to run when
+ * no other task is available to run. Call xTaskGetIdleTaskHandle() or
+ * xTaskGetIdleTaskHandleForCore() with xCoreID set to 0 to get the Active
+ * idle task handle. Call xTaskGetIdleTaskHandleForCore() with xCoreID set to
+ * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task handles.
*/
-TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+ #if ( configNUMBER_OF_CORES == 1 )
+ TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif /* #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
/**
* configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
@@ -1823,7 +2142,7 @@
* uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
*
* // For percentage calculations.
- * ulTotalRunTime /= 100UL;
+ * ulTotalRunTime /= 100U;
*
* // Avoid divide by zero errors.
* if( ulTotalRunTime > 0 )
@@ -1837,7 +2156,7 @@
* // ulTotalRunTimeDiv100 has already been divided by 100.
* ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
*
- * if( ulStatsAsPercentage > 0UL )
+ * if( ulStatsAsPercentage > 0U )
* {
* sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
* }
@@ -1858,14 +2177,16 @@
* }
* @endcode
*/
-UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
- const UBaseType_t uxArraySize,
- configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+ const UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
* @code{c}
- * void vTaskList( char *pcWriteBuffer );
+ * void vTaskListTasks( char *pcWriteBuffer, size_t uxBufferLength );
* @endcode
*
* configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
@@ -1878,8 +2199,77 @@
* Lists all the current tasks, along with their current state and stack
* usage high water mark.
*
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
+ * Tasks are reported as running ('X'), blocked ('B'), ready ('R'), deleted ('D')
+ * or suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications. Do not consider it to be part of the scheduler.
+ *
+ * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * information in the following format:
+ * Task Name, Task State, Task Priority, Task Stack High Watermak, Task Number.
+ *
+ * The following is a sample output:
+ * Task A X 2 67 2
+ * Task B R 1 67 3
+ * IDLE R 0 67 5
+ * Tmr Svc B 6 137 6
+ *
+ * Stack usage specified as the number of unused StackType_t words stack can hold
+ * on top of stack - not the number of bytes.
+ *
+ * vTaskListTasks() has a dependency on the snprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms. An alternative, tiny, third party, and limited
+ * functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskListTasks().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form. This buffer is assumed to be large
+ * enough to contain the generated report. Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * @param uxBufferLength Length of the pcWriteBuffer.
+ *
+ * \defgroup vTaskListTasks vTaskListTasks
+ * \ingroup TaskUtils
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+ void vTaskListTasks( char * pcWriteBuffer,
+ size_t uxBufferLength ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskList( char *pcWriteBuffer );
+ * @endcode
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available. See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * WARN: This function assumes that the pcWriteBuffer is of length
+ * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
+ * backward compatibility. New applications are recommended to
+ * use vTaskListTasks and supply the length of the pcWriteBuffer explicitly.
+ *
+ * NOTE 1: This function will disable interrupts for its duration. It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as running ('X'), blocked ('B'), ready ('R'), deleted ('D')
+ * or suspended ('S').
*
* PLEASE NOTE:
*
@@ -1887,15 +2277,23 @@
* demo applications. Do not consider it to be part of the scheduler.
*
* vTaskList() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays task:
- * names, states, priority, stack usage and task number.
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * information in the following format:
+ * Task Name, Task State, Task Priority, Task Stack High Watermak, Task Number.
+ *
+ * The following is a sample output:
+ * Task A X 2 67 2
+ * Task B R 1 67 3
+ * IDLE R 0 67 5
+ * Tmr Svc B 6 137 6
+ *
* Stack usage specified as the number of unused StackType_t words stack can hold
* on top of stack - not the number of bytes.
*
- * vTaskList() has a dependency on the sprintf() C library function that might
+ * vTaskList() has a dependency on the snprintf() C library function that might
* bloat the code size, use a lot of stack, and provide different results on
* different platforms. An alternative, tiny, third party, and limited
- * functionality implementation of sprintf() is provided in many of the
+ * functionality implementation of snprintf() is provided in many of the
* FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
* printf-stdarg.c does not provide a full snprintf() implementation!).
*
@@ -1911,7 +2309,68 @@
* \defgroup vTaskList vTaskList
* \ingroup TaskUtils
*/
-void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#define vTaskList( pcWriteBuffer ) vTaskListTasks( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH )
+
+/**
+ * task. h
+ * @code{c}
+ * void vTaskGetRunTimeStatistics( char *pcWriteBuffer, size_t uxBufferLength );
+ * @endcode
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available. The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively. The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration. It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task. The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStatistics() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications. Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part of
+ * the uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms. An alternative, tiny, third party, and
+ * limited functionality implementation of snprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStatistics().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form. This buffer is assumed to be large enough to
+ * contain the generated report. Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * @param uxBufferLength Length of the pcWriteBuffer.
+ *
+ * \defgroup vTaskGetRunTimeStatistics vTaskGetRunTimeStatistics
+ * \ingroup TaskUtils
+ */
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
+ void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+ size_t uxBufferLength ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -1927,6 +2386,12 @@
* value respectively. The counter should be at least 10 times the frequency of
* the tick count.
*
+ * WARN: This function assumes that the pcWriteBuffer is of length
+ * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
+ * backward compatibility. New applications are recommended to use
+ * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer
+ * explicitly.
+ *
* NOTE 1: This function will disable interrupts for its duration. It is
* not intended for normal application runtime use but as a debug aid.
*
@@ -1948,10 +2413,10 @@
* amount of time each task has spent in the Running state in both absolute and
* percentage terms.
*
- * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * vTaskGetRunTimeStats() has a dependency on the snprintf() C library function
* that might bloat the code size, use a lot of stack, and provide different
* results on different platforms. An alternative, tiny, third party, and
- * limited functionality implementation of sprintf() is provided in many of the
+ * limited functionality implementation of snprintf() is provided in many of the
* FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
* printf-stdarg.c does not provide a full snprintf() implementation!).
*
@@ -1967,7 +2432,7 @@
* \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
* \ingroup TaskUtils
*/
-void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#define vTaskGetRunTimeStats( pcWriteBuffer ) vTaskGetRunTimeStatistics( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH )
/**
* task. h
@@ -2002,8 +2467,10 @@
* \defgroup ulTaskGetRunTimeCounter ulTaskGetRunTimeCounter
* \ingroup TaskUtils
*/
-configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+ configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+ configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -2042,8 +2509,10 @@
* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
* \ingroup TaskUtils
*/
-configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
-configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION;
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+ configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+ configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION;
+#endif
/**
* task. h
@@ -2413,7 +2882,7 @@
* will be cleared in the calling task's notification value before the task
* checks to see if any notifications are pending, and optionally blocks if no
* notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if
- * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * limits.h is included) or 0xffffffffU (if limits.h is not included) will have
* the effect of resetting the task's notification value to 0. Setting
* ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
*
@@ -2989,11 +3458,31 @@
*/
BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+/**
+ * task.h
+ * @code{c}
+ * void vTaskResetState( void );
+ * @endcode
+ *
+ * This function resets the internal state of the task. It must be called by the
+ * application before restarting the scheduler.
+ *
+ * \defgroup vTaskResetState vTaskResetState
+ * \ingroup SchedulerControl
+ */
+void vTaskResetState( void ) PRIVILEGED_FUNCTION;
+
/*-----------------------------------------------------------
* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
*----------------------------------------------------------*/
+#if ( configNUMBER_OF_CORES == 1 )
+ #define taskYIELD_WITHIN_API() portYIELD_WITHIN_API()
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ #define taskYIELD_WITHIN_API() vTaskYieldWithinAPI()
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
/*
* THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY
* INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
@@ -3099,7 +3588,11 @@
* Sets the pointer to the current TCB to the TCB of the highest priority task
* that is ready to run.
*/
-portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+#if ( configNUMBER_OF_CORES == 1 )
+ portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+#else
+ portDONT_DISCARD void vTaskSwitchContext( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+#endif
/*
* THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY
@@ -3113,6 +3606,11 @@
TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
/*
+ * Return the handle of the task running on specified core.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
+
+/*
* Shortcut used by the queue implementation to prevent unnecessary call to
* taskYIELD();
*/
@@ -3150,14 +3648,18 @@
/*
* Get the uxTaskNumber assigned to the task referenced by the xTask parameter.
*/
-UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
/*
* Set the uxTaskNumber of the task referenced by the xTask parameter to
* uxHandle.
*/
-void vTaskSetTaskNumber( TaskHandle_t xTask,
- const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+ void vTaskSetTaskNumber( TaskHandle_t xTask,
+ const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+#endif
/*
* Only available when configUSE_TICKLESS_IDLE is set to 1.
@@ -3167,7 +3669,9 @@
* to date with the actual execution time by being skipped forward by a time
* equal to the idle period.
*/
-void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TICKLESS_IDLE != 0 )
+ void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+#endif
/*
* Only available when configUSE_TICKLESS_IDLE is set to 1.
@@ -3183,7 +3687,9 @@
* critical section between the timer being stopped and the sleep mode being
* entered to ensure it is ok to proceed into the sleep mode.
*/
-eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TICKLESS_IDLE != 0 )
+ eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+#endif
/*
* For internal use only. Increment the mutex held count when a mutex is
@@ -3197,6 +3703,58 @@
*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+/*
+ * For internal use only. Same as portYIELD_WITHIN_API() in single core FreeRTOS.
+ * For SMP this is not defined by the port.
+ */
+#if ( configNUMBER_OF_CORES > 1 )
+ void vTaskYieldWithinAPI( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
+ * is greater than 1. This function can be used in the implementation of portENTER_CRITICAL
+ * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
+ * It should be used in the implementation of portENTER_CRITICAL if port is running a
+ * multiple core FreeRTOS.
+ */
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
+ void vTaskEnterCritical( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
+ * is greater than 1. This function can be used in the implementation of portEXIT_CRITICAL
+ * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
+ * It should be used in the implementation of portEXIT_CRITICAL if port is running a
+ * multiple core FreeRTOS.
+ */
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
+ void vTaskExitCritical( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when configNUMBER_OF_CORES is greater than 1. This function
+ * should be used in the implementation of portENTER_CRITICAL_FROM_ISR if port is
+ * running a multiple core FreeRTOS.
+ */
+#if ( configNUMBER_OF_CORES > 1 )
+ UBaseType_t vTaskEnterCriticalFromISR( void );
+#endif
+
+/*
+ * This function is only intended for use when implementing a port of the scheduler
+ * and is only available when configNUMBER_OF_CORES is greater than 1. This function
+ * should be used in the implementation of portEXIT_CRITICAL_FROM_ISR if port is
+ * running a multiple core FreeRTOS.
+ */
+#if ( configNUMBER_OF_CORES > 1 )
+ void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
+#endif
+
#if ( portUSING_MPU_WRAPPERS == 1 )
/*
diff --git a/Source/include/timers.h b/Source/include/timers.h
index 0900edb..2e809c0 100644
--- a/Source/include/timers.h
+++ b/Source/include/timers.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -34,10 +34,8 @@
#error "include FreeRTOS.h must appear in source files before include timers.h"
#endif
-/*lint -save -e537 This headers are only multiply included if the application code
- * happens to also be including task.h. */
#include "task.h"
-/*lint -restore */
+
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -88,8 +86,8 @@
* Defines the prototype to which functions used with the
* xTimerPendFunctionCallFromISR() function must conform.
*/
-typedef void (* PendedFunction_t)( void *,
- uint32_t );
+typedef void (* PendedFunction_t)( void * arg1,
+ uint32_t arg2 );
/**
* TimerHandle_t xTimerCreate( const char * const pcTimerName,
@@ -229,7 +227,7 @@
* @endverbatim
*/
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ TimerHandle_t xTimerCreate( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
const BaseType_t xAutoReload,
void * const pvTimerID,
@@ -359,7 +357,7 @@
* @endverbatim
*/
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
const BaseType_t xAutoReload,
void * const pvTimerID,
@@ -739,14 +737,18 @@
* // The key press event handler.
* void vKeyPressEventHandler( char cKey )
* {
- * // Ensure the LCD back-light is on, then reset the timer that is
- * // responsible for turning the back-light off after 5 seconds of
- * // key inactivity. Wait 10 ticks for the command to be successfully sent
- * // if it cannot be sent immediately.
- * vSetBacklightState( BACKLIGHT_ON );
- * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ * // Reset the timer that is responsible for turning the back-light off after
+ * // 5 seconds of key inactivity. Wait 10 ticks for the command to be
+ * // successfully sent if it cannot be sent immediately.
+ * if( xTimerReset( xBacklightTimer, 10 ) == pdPASS )
* {
- * // The reset command was not executed successfully. Take appropriate
+ * // Turn on the LCD back-light. It will be turned off in the
+ * // vBacklightTimerCallback after 5 seconds of key inactivity.
+ * vSetBacklightState( BACKLIGHT_ON );
+ * }
+ * else
+ * {
+ * // The reset command was not executed successfully. Take appropriate
* // action here.
* }
*
@@ -755,16 +757,15 @@
*
* void main( void )
* {
- * int32_t x;
*
* // Create then start the one-shot timer that is responsible for turning
* // the back-light off if no keys are pressed within a 5 second period.
* xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel.
- * ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ * pdMS_TO_TICKS( 5000 ), // The timer period in ticks.
* pdFALSE, // The timer is a one-shot timer.
* 0, // The id is not used by the callback so can take any value.
* vBacklightTimerCallback // The callback function that switches the LCD back-light off.
- * );
+ * );
*
* if( xBacklightTimer == NULL )
* {
@@ -1198,10 +1199,12 @@
* }
* @endverbatim
*/
-BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
- void * pvParameter1,
- uint32_t ulParameter2,
- BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+ BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ void * pvParameter1,
+ uint32_t ulParameter2,
+ BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#endif
/**
* BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
@@ -1235,10 +1238,12 @@
* timer daemon task, otherwise pdFALSE is returned.
*
*/
-BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
- void * pvParameter1,
- uint32_t ulParameter2,
- TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+ void * pvParameter1,
+ uint32_t ulParameter2,
+ TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
/**
* const char * const pcTimerGetName( TimerHandle_t xTimer );
@@ -1249,7 +1254,7 @@
*
* @return The name assigned to the timer specified by the xTimer parameter.
*/
-const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
/**
* void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload );
@@ -1348,12 +1353,29 @@
* for use by the kernel only.
*/
BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
- const BaseType_t xCommandID,
- const TickType_t xOptionalValue,
- BaseType_t * const pxHigherPriorityTaskWoken,
- const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+/*
+ * Splitting the xTimerGenericCommand into two sub functions and making it a macro
+ * removes a recursion path when called from ISRs. This is primarily for the XCore
+ * XCC port which detects the recursion path and throws an error during compilation
+ * when this is not split.
+ */
+BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#define xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) \
+ ( ( xCommandID ) < tmrFIRST_FROM_ISR_COMMAND ? \
+ xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) : \
+ xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) )
#if ( configUSE_TRACE_FACILITY == 1 )
void vTimerSetTimerNumber( TimerHandle_t xTimer,
UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
@@ -1365,7 +1387,7 @@
/**
* task.h
* @code{c}
- * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+ * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, configSTACK_DEPTH_TYPE * puxTimerTaskStackSize )
* @endcode
*
* This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB. This function is required when
@@ -1373,11 +1395,11 @@
*
* @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer
* @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
- * @param pulTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param puxTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
*/
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
StackType_t ** ppxTimerTaskStackBuffer,
- uint32_t * pulTimerTaskStackSize );
+ configSTACK_DEPTH_TYPE * puxTimerTaskStackSize );
#endif
@@ -1391,10 +1413,19 @@
*
* This hook function is called form the timer task once when the task starts running.
*/
+ /* MISRA Ref 8.6.1 [External linkage] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+ /* coverity[misra_c_2012_rule_8_6_violation] */
void vApplicationDaemonTaskStartupHook( void );
#endif
+/*
+ * This function resets the internal state of the timer module. It must be called
+ * by the application before restarting the scheduler.
+ */
+void vTimerResetState( void ) PRIVILEGED_FUNCTION;
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/list.c b/Source/list.c
index 6129aff..b390c5a 100644
--- a/Source/list.c
+++ b/Source/list.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -37,11 +37,10 @@
#include "FreeRTOS.h"
#include "list.h"
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
* defined for the header files above, but not in this file, in order to
* generate the correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
@@ -49,10 +48,12 @@
void vListInitialise( List_t * const pxList )
{
+ traceENTER_vListInitialise( pxList );
+
/* The list structure contains a list item which is used to mark the
* end of the list. To initialise the list the list end is inserted
* as the only list entry. */
- pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
@@ -62,8 +63,8 @@
/* The list end next and previous pointers point to itself so we know
* when the list is empty. */
- pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
- pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );
+ pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );
/* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
#if ( configUSE_MINI_LIST_ITEM == 0 )
@@ -80,11 +81,15 @@
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+
+ traceRETURN_vListInitialise();
}
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
+ traceENTER_vListInitialiseItem( pxItem );
+
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
@@ -92,6 +97,8 @@
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+
+ traceRETURN_vListInitialiseItem();
}
/*-----------------------------------------------------------*/
@@ -100,6 +107,8 @@
{
ListItem_t * const pxIndex = pxList->pxIndex;
+ traceENTER_vListInsertEnd( pxList, pxNewListItem );
+
/* Only effective when configASSERT() is also defined, these tests may catch
* the list data structures being overwritten in memory. They will not catch
* data errors caused by incorrect configuration or use of FreeRTOS. */
@@ -121,7 +130,9 @@
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
- ( pxList->uxNumberOfItems )++;
+ ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );
+
+ traceRETURN_vListInsertEnd();
}
/*-----------------------------------------------------------*/
@@ -131,6 +142,8 @@
ListItem_t * pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+ traceENTER_vListInsert( pxList, pxNewListItem );
+
/* Only effective when configASSERT() is also defined, these tests may catch
* the list data structures being overwritten in memory. They will not catch
* data errors caused by incorrect configuration or use of FreeRTOS. */
@@ -153,7 +166,7 @@
{
/* *** NOTE ***********************************************************
* If you find your application is crashing here then likely causes are
- * listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for
+ * listed below. In addition see https://www.freertos.org/Why-FreeRTOS/FAQs for
* more tips, and ensure configASSERT() is defined!
* https://www.FreeRTOS.org/a00110.html#configASSERT
*
@@ -176,10 +189,12 @@
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
**********************************************************************/
- for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
{
/* There is nothing to do here, just iterating to the wanted
- * insertion position. */
+ * insertion position.
+ * IF YOU FIND YOUR CODE STUCK HERE, SEE THE NOTE JUST ABOVE.
+ */
}
}
@@ -192,16 +207,21 @@
* item later. */
pxNewListItem->pxContainer = pxList;
- ( pxList->uxNumberOfItems )++;
+ ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );
+
+ traceRETURN_vListInsert();
}
/*-----------------------------------------------------------*/
+
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
-/* The list item knows which list it is in. Obtain the list from the list
- * item. */
+ /* The list item knows which list it is in. Obtain the list from the list
+ * item. */
List_t * const pxList = pxItemToRemove->pxContainer;
+ traceENTER_uxListRemove( pxItemToRemove );
+
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
@@ -219,7 +239,9 @@
}
pxItemToRemove->pxContainer = NULL;
- ( pxList->uxNumberOfItems )--;
+ ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems - 1U );
+
+ traceRETURN_uxListRemove( pxList->uxNumberOfItems );
return pxList->uxNumberOfItems;
}
diff --git a/Source/portable/Common/mpu_wrappers.c b/Source/portable/Common/mpu_wrappers.c
index 17efcdb..a26021b 100644
--- a/Source/portable/Common/mpu_wrappers.c
+++ b/Source/portable/Common/mpu_wrappers.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -57,7 +57,7 @@
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
const char * const pcName,
- uint16_t usStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
@@ -72,7 +72,7 @@
uxPriority = uxPriority & ~( portPRIVILEGE_BIT );
portMEMORY_BARRIER();
- xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+ xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@@ -80,7 +80,7 @@
}
else
{
- xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+ xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
}
return xReturn;
@@ -91,7 +91,7 @@
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
const char * const pcName,
- const uint32_t ulStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
@@ -107,7 +107,7 @@
uxPriority = uxPriority & ~( portPRIVILEGE_BIT );
portMEMORY_BARRIER();
- xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+ xReturn = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@@ -115,7 +115,7 @@
}
else
{
- xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+ xReturn = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
}
return xReturn;
@@ -481,30 +481,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
- {
- char * pcReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
-
- pcReturn = pcTaskGetName( xTaskToQuery );
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- pcReturn = pcTaskGetName( xTaskToQuery );
- }
-
- return pcReturn;
- }
-/*-----------------------------------------------------------*/
-
#if ( INCLUDE_xTaskGetHandle == 1 )
TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
{
@@ -532,14 +508,15 @@
/*-----------------------------------------------------------*/
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+ void MPU_vTaskListTasks( char * pcWriteBuffer,
+ size_t uxBufferLength ) /* FREERTOS_SYSTEM_CALL */
{
if( portIS_PRIVILEGED() == pdFALSE )
{
portRAISE_PRIVILEGE();
portMEMORY_BARRIER();
- vTaskList( pcWriteBuffer );
+ vTaskListTasks( pcWriteBuffer, uxBufferLength );
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@@ -547,21 +524,22 @@
}
else
{
- vTaskList( pcWriteBuffer );
+ vTaskListTasks( pcWriteBuffer, uxBufferLength );
}
}
#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+ void MPU_vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+ size_t uxBufferLength ) /* FREERTOS_SYSTEM_CALL */
{
if( portIS_PRIVILEGED() == pdFALSE )
{
portRAISE_PRIVILEGE();
portMEMORY_BARRIER();
- vTaskGetRunTimeStats( pcWriteBuffer );
+ vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@@ -569,7 +547,7 @@
}
else
{
- vTaskGetRunTimeStats( pcWriteBuffer );
+ vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
}
}
#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
@@ -858,7 +836,7 @@
#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
/*-----------------------------------------------------------*/
- #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) )
TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
{
TaskHandle_t xReturn;
@@ -880,7 +858,7 @@
return xReturn;
}
- #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+ #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetSchedulerState == 1 )
@@ -1546,6 +1524,34 @@
#endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
+ #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+ uint8_t * pucQueueStorage,
+ StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueSetHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
#if ( configUSE_QUEUE_SETS == 1 )
QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
@@ -1821,14 +1827,14 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* FREERTOS_SYSTEM_CALL */
{
if( portIS_PRIVILEGED() == pdFALSE )
{
portRAISE_PRIVILEGE();
portMEMORY_BARRIER();
- vTimerSetReloadMode( xTimer, uxAutoReload );
+ vTimerSetReloadMode( xTimer, xAutoReload );
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@@ -1836,7 +1842,7 @@
}
else
{
- vTimerSetReloadMode( xTimer, uxAutoReload );
+ vTimerSetReloadMode( xTimer, xAutoReload );
}
}
#endif /* if ( configUSE_TIMERS == 1 ) */
@@ -1947,11 +1953,11 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
- const BaseType_t xCommandID,
- const TickType_t xOptionalValue,
- BaseType_t * const pxHigherPriorityTaskWoken,
- const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
@@ -1960,7 +1966,7 @@
portRAISE_PRIVILEGE();
portMEMORY_BARRIER();
- xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+ xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
portMEMORY_BARRIER();
portRESET_PRIVILEGE();
@@ -1968,7 +1974,7 @@
}
else
{
- xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+ xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
}
return xReturn;
@@ -1976,7 +1982,7 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
{
EventGroupHandle_t xReturn;
@@ -1999,10 +2005,10 @@
return xReturn;
}
- #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
{
EventGroupHandle_t xReturn;
@@ -2025,387 +2031,417 @@
return xReturn;
}
- #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ #if ( configUSE_EVENT_GROUPS == 1 )
+ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xClearOnExit,
+ const BaseType_t xWaitForAllBits,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventBits_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventBits_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+ }
+
+ return xReturn;
+ }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventBits_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+ }
+
+ return xReturn;
+ }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
const EventBits_t uxBitsToWaitFor,
- const BaseType_t xClearOnExit,
- const BaseType_t xWaitForAllBits,
TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- EventBits_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ EventBits_t xReturn;
- xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
- {
- EventBits_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_EVENT_GROUPS == 1 )
+ void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
- portMEMORY_BARRIER();
+ vEventGroupDelete( xEventGroup );
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vEventGroupDelete( xEventGroup );
+ }
}
- else
- {
- xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
- {
- EventBits_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ size_t xReturn;
- xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- EventBits_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ size_t xReturn;
- xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
- {
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ size_t xReturn;
- vEventGroupDelete( xEventGroup );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+ }
+
+ return xReturn;
}
- else
- {
- vEventGroupDelete( xEventGroup );
- }
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- size_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
- portMEMORY_BARRIER();
+ vStreamBufferDelete( xStreamBuffer );
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vStreamBufferDelete( xStreamBuffer );
+ }
}
- else
- {
- xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- size_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ BaseType_t xReturn;
- xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferIsFull( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferIsFull( xStreamBuffer );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- size_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ BaseType_t xReturn;
- xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ BaseType_t xReturn;
- vStreamBufferDelete( xStreamBuffer );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferReset( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferReset( xStreamBuffer );
+ }
+
+ return xReturn;
}
- else
- {
- vStreamBufferDelete( xStreamBuffer );
- }
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ size_t xReturn;
- xReturn = xStreamBufferIsFull( xStreamBuffer );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xStreamBufferIsFull( xStreamBuffer );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ size_t xReturn;
- xReturn = xStreamBufferIsEmpty( xStreamBuffer );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xStreamBufferIsEmpty( xStreamBuffer );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
{
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
+ BaseType_t xReturn;
- xReturn = xStreamBufferReset( xStreamBuffer );
- portMEMORY_BARRIER();
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
+ xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+ }
+
+ return xReturn;
}
- else
- {
- xReturn = xStreamBufferReset( xStreamBuffer );
- }
-
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- size_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
- xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
- }
-
- return xReturn;
- }
-/*-----------------------------------------------------------*/
-
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- size_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
-
- xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
- }
-
- return xReturn;
- }
-/*-----------------------------------------------------------*/
-
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn;
-
- if( portIS_PRIVILEGED() == pdFALSE )
- {
- portRAISE_PRIVILEGE();
- portMEMORY_BARRIER();
-
- xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
- portMEMORY_BARRIER();
-
- portRESET_PRIVILEGE();
- portMEMORY_BARRIER();
- }
- else
- {
- xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
- }
-
- return xReturn;
- }
-/*-----------------------------------------------------------*/
-
- #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
+ BaseType_t xStreamBufferType,
StreamBufferCallbackFunction_t pxSendCompletedCallback,
StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */
{
StreamBufferHandle_t xReturn;
/**
- * Streambuffer application level callback functionality is disabled for MPU
+ * Stream buffer application level callback functionality is disabled for MPU
* enabled ports.
*/
configASSERT( ( pxSendCompletedCallback == NULL ) &&
@@ -2421,7 +2457,7 @@
xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer,
+ xStreamBufferType,
NULL,
NULL );
portMEMORY_BARRIER();
@@ -2433,26 +2469,26 @@
{
xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer,
+ xStreamBufferType,
NULL,
NULL );
}
}
else
{
- traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType );
xReturn = NULL;
}
return xReturn;
}
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
+ BaseType_t xStreamBufferType,
uint8_t * const pucStreamBufferStorageArea,
StaticStreamBuffer_t * const pxStaticStreamBuffer,
StreamBufferCallbackFunction_t pxSendCompletedCallback,
@@ -2461,7 +2497,7 @@
StreamBufferHandle_t xReturn;
/**
- * Streambuffer application level callback functionality is disabled for MPU
+ * Stream buffer application level callback functionality is disabled for MPU
* enabled ports.
*/
configASSERT( ( pxSendCompletedCallback == NULL ) &&
@@ -2477,7 +2513,7 @@
xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer,
+ xStreamBufferType,
pucStreamBufferStorageArea,
pxStaticStreamBuffer,
NULL,
@@ -2491,7 +2527,7 @@
{
xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer,
+ xStreamBufferType,
pucStreamBufferStorageArea,
pxStaticStreamBuffer,
NULL,
@@ -2500,13 +2536,13 @@
}
else
{
- traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType );
xReturn = NULL;
}
return xReturn;
}
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
/*-----------------------------------------------------------*/
diff --git a/Source/portable/Common/mpu_wrappers_v2.c b/Source/portable/Common/mpu_wrappers_v2.c
index f82762d..ac1159b 100644
--- a/Source/portable/Common/mpu_wrappers_v2.c
+++ b/Source/portable/Common/mpu_wrappers_v2.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -92,16 +92,16 @@
/**
* @brief Checks whether an external index is valid or not.
*/
- #define IS_EXTERNAL_INDEX_VALID( lIndex ) \
- ( ( ( lIndex ) >= INDEX_OFFSET ) && \
- ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) )
+ #define IS_EXTERNAL_INDEX_VALID( lIndex ) \
+ ( ( ( ( lIndex ) >= INDEX_OFFSET ) && \
+ ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) ) ? pdTRUE : pdFALSE )
/**
* @brief Checks whether an internal index is valid or not.
*/
- #define IS_INTERNAL_INDEX_VALID( lIndex ) \
- ( ( ( lIndex ) >= 0 ) && \
- ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) )
+ #define IS_INTERNAL_INDEX_VALID( lIndex ) \
+ ( ( ( ( lIndex ) >= 0 ) && \
+ ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) ) ? pdTRUE : pdFALSE )
/**
* @brief Converts an internal index into external.
@@ -197,46 +197,51 @@
/*
* Wrappers to keep all the casting in one place.
*/
- #define MPU_StoreQueueHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_QUEUE )
- #define MPU_GetQueueHandleAtIndex( lIndex ) ( QueueHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_QUEUE )
+ #define MPU_StoreQueueHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE )
+ #define MPU_GetQueueHandleAtIndex( lIndex ) ( QueueHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE )
#if ( configUSE_QUEUE_SETS == 1 )
- #define MPU_StoreQueueSetHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_QUEUE )
- #define MPU_GetQueueSetHandleAtIndex( lIndex ) ( QueueSetHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_QUEUE )
- #define MPU_StoreQueueSetMemberHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_QUEUE )
- #define MPU_GetQueueSetMemberHandleAtIndex( lIndex ) ( QueueSetMemberHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_QUEUE )
- #define MPU_GetIndexForQueueSetMemberHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_QUEUE )
+ #define MPU_StoreQueueSetHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE )
+ #define MPU_GetQueueSetHandleAtIndex( lIndex ) ( QueueSetHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE )
+ #define MPU_StoreQueueSetMemberHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE )
+ #define MPU_GetQueueSetMemberHandleAtIndex( lIndex ) ( QueueSetMemberHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE )
+ #define MPU_GetIndexForQueueSetMemberHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_QUEUE )
#endif
/*
* Wrappers to keep all the casting in one place for Task APIs.
*/
- #define MPU_StoreTaskHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_TASK )
- #define MPU_GetTaskHandleAtIndex( lIndex ) ( TaskHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_TASK )
- #define MPU_GetIndexForTaskHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_TASK )
+ #define MPU_StoreTaskHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_TASK )
+ #define MPU_GetTaskHandleAtIndex( lIndex ) ( TaskHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_TASK )
+ #define MPU_GetIndexForTaskHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_TASK )
+ #if ( configUSE_EVENT_GROUPS == 1 )
/*
* Wrappers to keep all the casting in one place for Event Group APIs.
*/
- #define MPU_StoreEventGroupHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_EVENT_GROUP )
- #define MPU_GetEventGroupHandleAtIndex( lIndex ) ( EventGroupHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_EVENT_GROUP )
- #define MPU_GetIndexForEventGroupHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_EVENT_GROUP )
+ #define MPU_StoreEventGroupHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_EVENT_GROUP )
+ #define MPU_GetEventGroupHandleAtIndex( lIndex ) ( EventGroupHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
+ #define MPU_GetIndexForEventGroupHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_EVENT_GROUP )
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
/*
* Wrappers to keep all the casting in one place for Stream Buffer APIs.
*/
- #define MPU_StoreStreamBufferHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, NULL, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
- #define MPU_GetStreamBufferHandleAtIndex( lIndex ) ( StreamBufferHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
- #define MPU_GetIndexForStreamBufferHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+ #define MPU_StoreStreamBufferHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle), NULL, KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+ #define MPU_GetStreamBufferHandleAtIndex( lIndex ) ( StreamBufferHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+ #define MPU_GetIndexForStreamBufferHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_STREAM_BUFFER )
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
#if ( configUSE_TIMERS == 1 )
-
/*
* Wrappers to keep all the casting in one place for Timer APIs.
*/
- #define MPU_StoreTimerHandleAtIndex( lIndex, xHandle, pxApplicationCallback ) MPU_StoreHandleAndDataAtIndex( lIndex, ( OpaqueObjectHandle_t ) xHandle, ( void * ) pxApplicationCallback, KERNEL_OBJECT_TYPE_TIMER )
- #define MPU_GetTimerHandleAtIndex( lIndex ) ( TimerHandle_t ) MPU_GetHandleAtIndex( lIndex, KERNEL_OBJECT_TYPE_TIMER )
- #define MPU_GetIndexForTimerHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) xHandle, KERNEL_OBJECT_TYPE_TIMER )
+ #define MPU_StoreTimerHandleAtIndex( lIndex, xHandle, pxApplicationCallback ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), ( void * ) ( pxApplicationCallback ), KERNEL_OBJECT_TYPE_TIMER )
+ #define MPU_GetTimerHandleAtIndex( lIndex ) ( TimerHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_TIMER )
+ #define MPU_GetIndexForTimerHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_TIMER )
#endif /* #if ( configUSE_TIMERS == 1 ) */
@@ -245,7 +250,7 @@
/**
* @brief Kernel object pool.
*/
- PRIVILEGED_DATA static KernelObject_t xKernelObjectPool[ configPROTECTED_KERNEL_OBJECT_POOL_SIZE ] = { NULL };
+ PRIVILEGED_DATA static KernelObject_t xKernelObjectPool[ configPROTECTED_KERNEL_OBJECT_POOL_SIZE ] = { 0 };
/*-----------------------------------------------------------*/
static int32_t MPU_GetFreeIndexInKernelObjectPool( void ) /* PRIVILEGED_FUNCTION */
@@ -263,13 +268,13 @@
if( xKernelObjectPool[ i ].xInternalObjectHandle == NULL )
{
/* Mark this index as not free. */
- xKernelObjectPool[ i ].xInternalObjectHandle = ( OpaqueObjectHandle_t ) ( ~0 );
+ xKernelObjectPool[ i ].xInternalObjectHandle = ( OpaqueObjectHandle_t ) ( ~0U );
lFreeIndex = i;
break;
}
}
}
- xTaskResumeAll();
+ ( void ) xTaskResumeAll();
return lFreeIndex;
}
@@ -763,37 +768,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetNameImpl( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
-
- char * MPU_pcTaskGetNameImpl( TaskHandle_t xTaskToQuery ) /* PRIVILEGED_FUNCTION */
- {
- char * pcReturn = NULL;
- int32_t lIndex;
- TaskHandle_t xInternalTaskHandle = NULL;
-
- if( xTaskToQuery == NULL )
- {
- pcReturn = pcTaskGetName( xTaskToQuery );
- }
- else
- {
- lIndex = ( int32_t ) xTaskToQuery;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
- {
- xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
- if( xInternalTaskHandle != NULL )
- {
- pcReturn = pcTaskGetName( xInternalTaskHandle );
- }
- }
- }
-
- return pcReturn;
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounterImpl( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
@@ -1198,7 +1172,7 @@
#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
/*-----------------------------------------------------------*/
- #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) )
TaskHandle_t MPU_xTaskGetCurrentTaskHandleImpl( void ) PRIVILEGED_FUNCTION;
@@ -1223,7 +1197,7 @@
return xExternalTaskHandle;
}
- #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+ #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetSchedulerState == 1 )
@@ -1572,7 +1546,7 @@
BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
const char * const pcName,
- uint16_t usStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * pxCreatedTask ) /* PRIVILEGED_FUNCTION */
@@ -1588,7 +1562,7 @@
/* xTaskCreate() can only be used to create privileged tasks in MPU port. */
if( ( uxPriority & portPRIVILEGE_BIT ) != 0 )
{
- xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, &( xInternalTaskHandle ) );
+ xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, &( xInternalTaskHandle ) );
if( ( xReturn == pdPASS ) && ( xInternalTaskHandle != NULL ) )
{
@@ -1616,7 +1590,7 @@
TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
const char * const pcName,
- const uint32_t ulStackDepth,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
@@ -1630,7 +1604,7 @@
if( lIndex != -1 )
{
- xInternalTaskHandle = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+ xInternalTaskHandle = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
if( xInternalTaskHandle != NULL )
{
@@ -1672,12 +1646,12 @@
xInternalTaskHandle = xTaskGetCurrentTaskHandle();
lIndex = MPU_GetIndexForTaskHandle( xInternalTaskHandle );
- vTaskDelete( xInternalTaskHandle );
-
if( lIndex != -1 )
{
MPU_SetIndexFreeInKernelObjectPool( lIndex );
}
+
+ vTaskDelete( xInternalTaskHandle );
}
else
{
@@ -1689,8 +1663,8 @@
if( xInternalTaskHandle != NULL )
{
- vTaskDelete( xInternalTaskHandle );
MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ vTaskDelete( xInternalTaskHandle );
}
}
}
@@ -1947,6 +1921,35 @@
#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/
+ char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* PRIVILEGED_FUNCTION */
+ {
+ char * pcReturn = NULL;
+ int32_t lIndex;
+ TaskHandle_t xInternalTaskHandle = NULL;
+
+ if( xTaskToQuery == NULL )
+ {
+ pcReturn = pcTaskGetName( xTaskToQuery );
+ }
+ else
+ {
+ lIndex = ( int32_t ) xTaskToQuery;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ {
+ xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalTaskHandle != NULL )
+ {
+ pcReturn = pcTaskGetName( xInternalTaskHandle );
+ }
+ }
+ }
+
+ return pcReturn;
+ }
+/*-----------------------------------------------------------*/
+
#if ( INCLUDE_uxTaskPriorityGet == 1 )
UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */
@@ -1980,6 +1983,72 @@
#endif /* #if ( INCLUDE_uxTaskPriorityGet == 1 ) */
/*-----------------------------------------------------------*/
+ #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+ UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */
+ {
+ UBaseType_t uxReturn = configMAX_PRIORITIES;
+ int32_t lIndex;
+ TaskHandle_t xInternalTaskHandle = NULL;
+
+ if( xTask == NULL )
+ {
+ uxReturn = uxTaskBasePriorityGet( xTask );
+ }
+ else
+ {
+ lIndex = ( int32_t ) xTask;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ {
+ xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalTaskHandle != NULL )
+ {
+ uxReturn = uxTaskBasePriorityGet( xInternalTaskHandle );
+ }
+ }
+ }
+
+ return uxReturn;
+ }
+
+ #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+ UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */
+ {
+ UBaseType_t uxReturn = configMAX_PRIORITIES;
+ int32_t lIndex;
+ TaskHandle_t xInternalTaskHandle = NULL;
+
+ if( xTask == NULL )
+ {
+ uxReturn = uxTaskBasePriorityGetFromISR( xTask );
+ }
+ else
+ {
+ lIndex = ( int32_t ) xTask;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ {
+ xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalTaskHandle != NULL )
+ {
+ uxReturn = uxTaskBasePriorityGetFromISR( xInternalTaskHandle );
+ }
+ }
+ }
+
+ return uxReturn;
+ }
+
+ #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) /* PRIVILEGED_FUNCTION */
@@ -2133,14 +2202,14 @@
if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) &&
( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+ && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
if( pvItemToQueue != NULL )
{
xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue,
- uxQueueGetQueueItemSize( xInternalQueueHandle ),
+ uxQueueItemSize,
tskMPU_READ_PERMISSION );
}
@@ -2248,12 +2317,12 @@
if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+ && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
- uxQueueGetQueueItemSize( xInternalQueueHandle ),
+ uxQueueItemSize,
tskMPU_WRITE_PERMISSION );
if( xIsReceiveBufferWritable == pdTRUE )
@@ -2300,12 +2369,12 @@
if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+ && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer,
- uxQueueGetQueueItemSize( xInternalQueueHandle ),
+ uxQueueItemSize,
tskMPU_WRITE_PERMISSION );
if( xIsReceiveBufferWritable == pdTRUE )
@@ -2347,9 +2416,9 @@
{
uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
- if( ( uxQueueItemSize == 0 )
+ if( ( uxQueueItemSize == 0U )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
+ && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
@@ -2900,7 +2969,7 @@
QueueHandle_t xInternalQueueHandle = NULL;
BaseType_t xReturn = pdFAIL;
- lIndex = ( uint32_t ) xQueue;
+ lIndex = ( int32_t ) xQueue;
if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
@@ -2947,6 +3016,39 @@
#endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
+ #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+ QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+ uint8_t * pucQueueStorage,
+ StaticQueue_t * pxStaticQueue ) /* PRIVILEGED_FUNCTION */
+ {
+ QueueSetHandle_t xInternalQueueSetHandle = NULL;
+ QueueSetHandle_t xExternalQueueSetHandle = NULL;
+ int32_t lIndex;
+
+ lIndex = MPU_GetFreeIndexInKernelObjectPool();
+
+ if( lIndex != -1 )
+ {
+ xInternalQueueSetHandle = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue );
+
+ if( xInternalQueueSetHandle != NULL )
+ {
+ MPU_StoreQueueSetHandleAtIndex( lIndex, xInternalQueueSetHandle );
+ xExternalQueueSetHandle = ( QueueSetHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex );
+ }
+ else
+ {
+ MPU_SetIndexFreeInKernelObjectPool( lIndex );
+ }
+ }
+
+ return xExternalQueueSetHandle;
+ }
+
+ #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
#if ( configUSE_QUEUE_SETS == 1 )
BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
@@ -3370,14 +3472,14 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
- const BaseType_t xCommandID,
- const TickType_t xOptionalValue,
- BaseType_t * const pxHigherPriorityTaskWoken,
- const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn = pdFALSE;
- xTimerGenericCommandParams_t xParams;
+ xTimerGenericCommandFromTaskParams_t xParams;
xParams.xTimer = xTimer;
xParams.xCommandID = xCommandID;
@@ -3385,14 +3487,14 @@
xParams.pxHigherPriorityTaskWoken = pxHigherPriorityTaskWoken;
xParams.xTicksToWait = xTicksToWait;
- xReturn = MPU_xTimerGenericCommandEntry( &( xParams ) );
+ xReturn = MPU_xTimerGenericCommandFromTaskEntry( &( xParams ) );
return xReturn;
}
- BaseType_t MPU_xTimerGenericCommandImpl( const xTimerGenericCommandParams_t * pxParams ) PRIVILEGED_FUNCTION;
+ BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) PRIVILEGED_FUNCTION;
- BaseType_t MPU_xTimerGenericCommandImpl( const xTimerGenericCommandParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
+ BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
{
BaseType_t xReturn = pdFALSE;
TimerHandle_t xInternalTimerHandle = NULL;
@@ -3404,39 +3506,42 @@
if( pxParams != NULL )
{
xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
- sizeof( xTimerGenericCommandParams_t ),
+ sizeof( xTimerGenericCommandFromTaskParams_t ),
tskMPU_READ_PERMISSION );
}
if( xAreParamsReadable == pdTRUE )
{
- if( pxParams->pxHigherPriorityTaskWoken != NULL )
+ if( pxParams->xCommandID < tmrFIRST_FROM_ISR_COMMAND )
{
- xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pxHigherPriorityTaskWoken,
- sizeof( BaseType_t ),
- tskMPU_WRITE_PERMISSION );
- }
-
- if( ( pxParams->pxHigherPriorityTaskWoken == NULL ) ||
- ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
- {
- lIndex = ( int32_t ) ( pxParams->xTimer );
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ if( pxParams->pxHigherPriorityTaskWoken != NULL )
{
- xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pxHigherPriorityTaskWoken,
+ sizeof( BaseType_t ),
+ tskMPU_WRITE_PERMISSION );
+ }
- if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
+ if( ( pxParams->pxHigherPriorityTaskWoken == NULL ) ||
+ ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) )
+ {
+ lIndex = ( int32_t ) ( pxParams->xTimer );
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalTimerHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE )
{
- xReturn = xTimerGenericCommand( xInternalTimerHandle,
- pxParams->xCommandID,
- pxParams->xOptionalValue,
- pxParams->pxHigherPriorityTaskWoken,
- pxParams->xTicksToWait );
+ xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalTimerHandle != NULL )
+ {
+ xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle,
+ pxParams->xCommandID,
+ pxParams->xOptionalValue,
+ pxParams->pxHigherPriorityTaskWoken,
+ pxParams->xTicksToWait );
+ }
}
}
}
@@ -3446,36 +3551,6 @@
return xReturn;
}
- BaseType_t MPU_xTimerGenericCommandPrivImpl( const xTimerGenericCommandParams_t * pxParams ) PRIVILEGED_FUNCTION;
-
- BaseType_t MPU_xTimerGenericCommandPrivImpl( const xTimerGenericCommandParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
- {
- BaseType_t xReturn = pdFALSE;
- TimerHandle_t xInternalTimerHandle = NULL;
- int32_t lIndex;
-
- if( pxParams != NULL )
- {
- lIndex = ( int32_t ) ( pxParams->xTimer );
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
- {
- xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
- if( xInternalTimerHandle != NULL )
- {
- xReturn = xTimerGenericCommand( xInternalTimerHandle,
- pxParams->xCommandID,
- pxParams->xOptionalValue,
- pxParams->pxHigherPriorityTaskWoken,
- pxParams->xTicksToWait );
- }
- }
- }
-
- return xReturn;
- }
-
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
@@ -3516,10 +3591,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer,
- const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+ const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION;
void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer,
- const UBaseType_t uxAutoReload ) /* PRIVILEGED_FUNCTION */
+ const BaseType_t xAutoReload ) /* PRIVILEGED_FUNCTION */
{
TimerHandle_t xInternalTimerHandle = NULL;
int32_t lIndex;
@@ -3537,7 +3612,7 @@
if( xInternalTimerHandle != NULL )
{
- vTimerSetReloadMode( xInternalTimerHandle, uxAutoReload );
+ vTimerSetReloadMode( xInternalTimerHandle, xAutoReload );
}
}
}
@@ -3691,7 +3766,7 @@
TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction ) /* PRIVILEGED_FUNCTION */
{
@@ -3703,7 +3778,7 @@
if( lIndex != -1 )
{
- xInternalTimerHandle = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, MPU_TimerCallback );
+ xInternalTimerHandle = xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback );
if( xInternalTimerHandle != NULL )
{
@@ -3726,7 +3801,7 @@
TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction,
StaticTimer_t * pxTimerBuffer ) /* PRIVILEGED_FUNCTION */
@@ -3739,7 +3814,7 @@
if( lIndex != -1 )
{
- xInternalTimerHandle = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, MPU_TimerCallback, pxTimerBuffer );
+ xInternalTimerHandle = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback, pxTimerBuffer );
if( xInternalTimerHandle != NULL )
{
@@ -3785,57 +3860,133 @@
#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xReturn = pdFALSE;
+ TimerHandle_t xInternalTimerHandle = NULL;
+ int32_t lIndex;
+
+ lIndex = ( int32_t ) xTimer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ {
+ xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalTimerHandle != NULL )
+ {
+ xReturn = xTimerGenericCommandFromISR( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+ }
+ }
+
+ return xReturn;
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
/*-----------------------------------------------------------*/
/* MPU wrappers for event group APIs. */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToWaitFor,
- const BaseType_t xClearOnExit,
- const BaseType_t xWaitForAllBits,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- EventBits_t xReturn = 0;
- xEventGroupWaitBitsParams_t xParams;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- xParams.xEventGroup = xEventGroup;
- xParams.uxBitsToWaitFor = uxBitsToWaitFor;
- xParams.xClearOnExit = xClearOnExit;
- xParams.xWaitForAllBits = xWaitForAllBits;
- xParams.xTicksToWait = xTicksToWait;
-
- xReturn = MPU_xEventGroupWaitBitsEntry( &( xParams ) );
-
- return xReturn;
- }
-
- EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) PRIVILEGED_FUNCTION;
-
- EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
- {
- EventBits_t xReturn = 0;
- EventGroupHandle_t xInternalEventGroupHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
- BaseType_t xAreParamsReadable = pdFALSE;
-
- if( pxParams != NULL )
+ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xClearOnExit,
+ const BaseType_t xWaitForAllBits,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
- xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
- sizeof( xEventGroupWaitBitsParams_t ),
- tskMPU_READ_PERMISSION );
+ EventBits_t xReturn = 0;
+ xEventGroupWaitBitsParams_t xParams;
+
+ xParams.xEventGroup = xEventGroup;
+ xParams.uxBitsToWaitFor = uxBitsToWaitFor;
+ xParams.xClearOnExit = xClearOnExit;
+ xParams.xWaitForAllBits = xWaitForAllBits;
+ xParams.xTicksToWait = xTicksToWait;
+
+ xReturn = MPU_xEventGroupWaitBitsEntry( &( xParams ) );
+
+ return xReturn;
}
- if( xAreParamsReadable == pdTRUE )
+ EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) PRIVILEGED_FUNCTION;
+
+ EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) /* PRIVILEGED_FUNCTION */
{
- if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
- ( pxParams->uxBitsToWaitFor != 0 )
- #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0 ) ) )
- #endif
- )
+ EventBits_t xReturn = 0;
+ EventGroupHandle_t xInternalEventGroupHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+ BaseType_t xAreParamsReadable = pdFALSE;
+
+ if( pxParams != NULL )
{
- lIndex = ( int32_t ) ( pxParams->xEventGroup );
+ xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams,
+ sizeof( xEventGroupWaitBitsParams_t ),
+ tskMPU_READ_PERMISSION );
+ }
+
+ if( xAreParamsReadable == pdTRUE )
+ {
+ if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
+ ( pxParams->uxBitsToWaitFor != 0U )
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0U ) ) )
+ #endif
+ )
+ {
+ lIndex = ( int32_t ) ( pxParams->xEventGroup );
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ {
+ xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
+ {
+ xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalEventGroupHandle != NULL )
+ {
+ xReturn = xEventGroupWaitBits( xInternalEventGroupHandle,
+ pxParams->uxBitsToWaitFor,
+ pxParams->xClearOnExit,
+ pxParams->xWaitForAllBits,
+ pxParams->xTicksToWait );
+ }
+ }
+ }
+ }
+ }
+
+ return xReturn;
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_EVENT_GROUPS == 1 )
+
+ EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+ EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */
+ {
+ EventBits_t xReturn = 0;
+ EventGroupHandle_t xInternalEventGroupHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+
+ if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
+ {
+ lIndex = ( int32_t ) xEventGroup;
if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
@@ -3847,136 +3998,106 @@
if( xInternalEventGroupHandle != NULL )
{
- xReturn = xEventGroupWaitBits( xInternalEventGroupHandle,
- pxParams->uxBitsToWaitFor,
- pxParams->xClearOnExit,
- pxParams->xWaitForAllBits,
- pxParams->xTicksToWait );
+ xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
}
}
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */
- {
- EventBits_t xReturn = 0;
- EventGroupHandle_t xInternalEventGroupHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+ EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
- if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
+ EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* PRIVILEGED_FUNCTION */
{
- lIndex = ( int32_t ) xEventGroup;
+ EventBits_t xReturn = 0;
+ EventGroupHandle_t xInternalEventGroupHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
{
- xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ lIndex = ( int32_t ) xEventGroup;
- if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalEventGroupHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
{
- xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear );
+ xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalEventGroupHandle != NULL )
+ {
+ xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+ }
}
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* PRIVILEGED_FUNCTION */
- {
- EventBits_t xReturn = 0;
- EventGroupHandle_t xInternalEventGroupHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
+ EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
- if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
+ EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
{
- lIndex = ( int32_t ) xEventGroup;
+ EventBits_t xReturn = 0;
+ EventGroupHandle_t xInternalEventGroupHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
+ ( uxBitsToWaitFor != 0U )
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
+ #endif
+ )
{
- xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ lIndex = ( int32_t ) xEventGroup;
- if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalEventGroupHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
{
- xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet );
+ xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalEventGroupHandle != NULL )
+ {
+ xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+ }
}
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
- EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
- {
- EventBits_t xReturn = 0;
- EventGroupHandle_t xInternalEventGroupHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
-
- if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
- ( uxBitsToWaitFor != 0 )
- #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
- #endif
- )
- {
- lIndex = ( int32_t ) xEventGroup;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
- {
- xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
- if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE )
- {
- xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
- if( xInternalEventGroupHandle != NULL )
- {
- xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
- }
- }
- }
- }
-
- return xReturn;
- }
-/*-----------------------------------------------------------*/
-
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumberImpl( void * xEventGroup ) PRIVILEGED_FUNCTION;
@@ -4007,10 +4128,10 @@
return xReturn;
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumberImpl( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
@@ -4040,7 +4161,7 @@
}
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
/* Privileged only wrappers for Event Group APIs. These are needed so that
@@ -4048,7 +4169,7 @@
* with all the APIs. */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
EventGroupHandle_t MPU_xEventGroupCreate( void ) /* PRIVILEGED_FUNCTION */
{
@@ -4076,10 +4197,10 @@
return xExternalEventGroupHandle;
}
- #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* PRIVILEGED_FUNCTION */
{
@@ -4107,30 +4228,34 @@
return xExternalEventGroupHandle;
}
- #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
/*-----------------------------------------------------------*/
- void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
- {
- EventGroupHandle_t xInternalEventGroupHandle = NULL;
- int32_t lIndex;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- lIndex = ( int32_t ) xEventGroup;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
{
- xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ EventGroupHandle_t xInternalEventGroupHandle = NULL;
+ int32_t lIndex;
- if( xInternalEventGroupHandle != NULL )
+ lIndex = ( int32_t ) xEventGroup;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- vEventGroupDelete( xInternalEventGroupHandle );
- MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalEventGroupHandle != NULL )
+ {
+ vEventGroupDelete( xInternalEventGroupHandle );
+ MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ }
}
}
- }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) )
BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
StaticEventGroup_t ** ppxEventGroupBuffer ) /* PRIVILEGED_FUNCTION */
@@ -4154,10 +4279,10 @@
return xReturn;
}
- #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */
@@ -4181,10 +4306,10 @@
return xReturn;
}
- #endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet,
@@ -4209,309 +4334,345 @@
return xReturn;
}
- #endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
- {
- EventBits_t xReturn = 0;
- EventGroupHandle_t xInternalEventGroupHandle = NULL;
- int32_t lIndex;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- lIndex = ( int32_t ) xEventGroup;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */
{
- xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ EventBits_t xReturn = 0;
+ EventGroupHandle_t xInternalEventGroupHandle = NULL;
+ int32_t lIndex;
- if( xInternalEventGroupHandle != NULL )
+ lIndex = ( int32_t ) xEventGroup;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xReturn = xEventGroupGetBitsFromISR( xInternalEventGroupHandle );
+ xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalEventGroupHandle != NULL )
+ {
+ xReturn = xEventGroupGetBitsFromISR( xInternalEventGroupHandle );
+ }
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/
/* MPU wrappers for stream buffer APIs. */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
- {
- size_t xReturn = 0;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xIsTxDataBufferReadable = pdFALSE;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
- if( pvTxData != NULL )
+ size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
{
- xIsTxDataBufferReadable = xPortIsAuthorizedToAccessBuffer( pvTxData,
- xDataLengthBytes,
- tskMPU_READ_PERMISSION );
+ size_t xReturn = 0;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xIsTxDataBufferReadable = pdFALSE;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xIsTxDataBufferReadable == pdTRUE )
+ if( pvTxData != NULL )
{
- lIndex = ( int32_t ) xStreamBuffer;
+ xIsTxDataBufferReadable = xPortIsAuthorizedToAccessBuffer( pvTxData,
+ xDataLengthBytes,
+ tskMPU_READ_PERMISSION );
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ if( xIsTxDataBufferReadable == pdTRUE )
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ lIndex = ( int32_t ) xStreamBuffer;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait );
+ }
}
}
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
- {
- size_t xReturn = 0;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xIsRxDataBufferWriteable = pdFALSE;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
- if( pvRxData != NULL )
+ size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */
{
- xIsRxDataBufferWriteable = xPortIsAuthorizedToAccessBuffer( pvRxData,
- xBufferLengthBytes,
- tskMPU_WRITE_PERMISSION );
+ size_t xReturn = 0;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xIsRxDataBufferWriteable = pdFALSE;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xIsRxDataBufferWriteable == pdTRUE )
+ if( pvRxData != NULL )
{
- lIndex = ( int32_t ) xStreamBuffer;
+ xIsRxDataBufferWriteable = xPortIsAuthorizedToAccessBuffer( pvRxData,
+ xBufferLengthBytes,
+ tskMPU_WRITE_PERMISSION );
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ if( xIsRxDataBufferWriteable == pdTRUE )
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ lIndex = ( int32_t ) xStreamBuffer;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait );
+ }
}
}
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
- {
- BaseType_t xReturn = pdFALSE;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ BaseType_t xReturn = pdFALSE;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferIsFull( xInternalStreamBufferHandle );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferIsFull( xInternalStreamBufferHandle );
+ }
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
- {
- BaseType_t xReturn = pdFALSE;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ BaseType_t xReturn = pdFALSE;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferIsEmpty( xInternalStreamBufferHandle );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferIsEmpty( xInternalStreamBufferHandle );
+ }
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
- {
- size_t xReturn = 0;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ size_t xReturn = 0;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferSpacesAvailable( xInternalStreamBufferHandle );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferSpacesAvailable( xInternalStreamBufferHandle );
+ }
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
- {
- size_t xReturn = 0;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ size_t xReturn = 0;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferBytesAvailable( xInternalStreamBufferHandle );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferBytesAvailable( xInternalStreamBufferHandle );
+ }
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* PRIVILEGED_FUNCTION */
- {
- BaseType_t xReturn = pdFALSE;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* PRIVILEGED_FUNCTION */
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ BaseType_t xReturn = pdFALSE;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferSetTriggerLevel( xInternalStreamBufferHandle, xTriggerLevel );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferSetTriggerLevel( xInternalStreamBufferHandle, xTriggerLevel );
+ }
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
- {
- size_t xReturn = 0;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
- BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
+ size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
{
- xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ size_t xReturn = 0;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+ BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE;
- if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- if( xInternalStreamBufferHandle != NULL )
+ if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE )
{
- xReturn = xStreamBufferNextMessageLengthBytes( xInternalStreamBufferHandle );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferNextMessageLengthBytes( xInternalStreamBufferHandle );
+ }
}
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
/* Privileged only wrappers for Stream Buffer APIs. These are needed so that
@@ -4519,11 +4680,11 @@
* with all the APIs. */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
+ BaseType_t xStreamBufferType,
StreamBufferCallbackFunction_t pxSendCompletedCallback,
StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* PRIVILEGED_FUNCTION */
{
@@ -4547,7 +4708,7 @@
{
xInternalStreamBufferHandle = xStreamBufferGenericCreate( xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer,
+ xStreamBufferType,
NULL,
NULL );
@@ -4564,21 +4725,21 @@
}
else
{
- traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType );
xExternalStreamBufferHandle = NULL;
}
return xExternalStreamBufferHandle;
}
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
+ BaseType_t xStreamBufferType,
uint8_t * const pucStreamBufferStorageArea,
StaticStreamBuffer_t * const pxStaticStreamBuffer,
StreamBufferCallbackFunction_t pxSendCompletedCallback,
@@ -4604,7 +4765,7 @@
{
xInternalStreamBufferHandle = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer,
+ xStreamBufferType,
pucStreamBufferStorageArea,
pxStaticStreamBuffer,
NULL,
@@ -4623,60 +4784,68 @@
}
else
{
- traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType );
xExternalStreamBufferHandle = NULL;
}
return xExternalStreamBufferHandle;
}
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
/*-----------------------------------------------------------*/
- void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
- {
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
- if( xInternalStreamBufferHandle != NULL )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- vStreamBufferDelete( xInternalStreamBufferHandle );
- }
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
- }
- }
-/*-----------------------------------------------------------*/
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ vStreamBufferDelete( xInternalStreamBufferHandle );
+ }
- BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
- {
- BaseType_t xReturn = pdFALSE;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
-
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
- {
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
-
- if( xInternalStreamBufferHandle != NULL )
- {
- xReturn = xStreamBufferReset( xInternalStreamBufferHandle );
+ MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
}
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xReturn = pdFALSE;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ {
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferReset( xInternalStreamBufferHandle );
+ }
+ }
+
+ return xReturn;
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) )
BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers,
uint8_t * ppucStreamBufferStorageArea,
@@ -4701,9 +4870,11 @@
return xReturn;
}
- #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */
/*-----------------------------------------------------------*/
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
const void * pvTxData,
size_t xDataLengthBytes,
@@ -4727,8 +4898,12 @@
return xReturn;
}
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
void * pvRxData,
size_t xBufferLengthBytes,
@@ -4752,52 +4927,89 @@
return xReturn;
}
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
- BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */
- {
- BaseType_t xReturn = pdFALSE;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+ BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ BaseType_t xReturn = pdFALSE;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
- if( xInternalStreamBufferHandle != NULL )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xReturn = xStreamBufferSendCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferSendCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+ }
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
- BaseType_t * pxHigherPriorityTaskWoken ) /*PRIVILEGED_FUNCTION */
- {
- BaseType_t xReturn = pdFALSE;
- StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
- int32_t lIndex;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- lIndex = ( int32_t ) xStreamBuffer;
-
- if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+ BaseType_t * pxHigherPriorityTaskWoken ) /*PRIVILEGED_FUNCTION */
{
- xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+ BaseType_t xReturn = pdFALSE;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
- if( xInternalStreamBufferHandle != NULL )
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
{
- xReturn = xStreamBufferReceiveCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferReceiveCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken );
+ }
}
+
+ return xReturn;
}
- return xReturn;
- }
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
+
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+
+ BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) /*PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xReturn = pdFAIL;
+ StreamBufferHandle_t xInternalStreamBufferHandle = NULL;
+ int32_t lIndex;
+
+ lIndex = ( int32_t ) xStreamBuffer;
+
+ if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE )
+ {
+ xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) );
+
+ if( xInternalStreamBufferHandle != NULL )
+ {
+ xReturn = xStreamBufferResetFromISR( xInternalStreamBufferHandle );
+ }
+ }
+
+ return xReturn;
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
@@ -4818,235 +5030,258 @@
PRIVILEGED_DATA UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ] =
{
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- ( UBaseType_t ) MPU_xTaskGenericNotifyImpl, /* SYSTEM_CALL_xTaskGenericNotify. */
- ( UBaseType_t ) MPU_xTaskGenericNotifyWaitImpl, /* SYSTEM_CALL_xTaskGenericNotifyWait. */
+ ( UBaseType_t ) MPU_xTaskGenericNotifyImpl, /* SYSTEM_CALL_xTaskGenericNotify. */
+ ( UBaseType_t ) MPU_xTaskGenericNotifyWaitImpl, /* SYSTEM_CALL_xTaskGenericNotifyWait. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotify. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyWait. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotify. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyWait. */
#endif
#if ( configUSE_TIMERS == 1 )
- ( UBaseType_t ) MPU_xTimerGenericCommandImpl, /* SYSTEM_CALL_xTimerGenericCommand. */
+ ( UBaseType_t ) MPU_xTimerGenericCommandFromTaskImpl, /* SYSTEM_CALL_xTimerGenericCommandFromTask. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGenericCommand. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGenericCommandFromTask. */
#endif
- ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl, /* SYSTEM_CALL_xEventGroupWaitBits. */
+ #if ( configUSE_EVENT_GROUPS == 1 )
+ ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl, /* SYSTEM_CALL_xEventGroupWaitBits. */
+ #else
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupWaitBits. */
+ #endif
/* The system calls above this line take 5 parameters. */
#if ( INCLUDE_xTaskDelayUntil == 1 )
- ( UBaseType_t ) MPU_xTaskDelayUntilImpl, /* SYSTEM_CALL_xTaskDelayUntil. */
+ ( UBaseType_t ) MPU_xTaskDelayUntilImpl, /* SYSTEM_CALL_xTaskDelayUntil. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskDelayUntil. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskDelayUntil. */
#endif
#if ( INCLUDE_xTaskAbortDelay == 1 )
- ( UBaseType_t ) MPU_xTaskAbortDelayImpl, /* SYSTEM_CALL_xTaskAbortDelay. */
+ ( UBaseType_t ) MPU_xTaskAbortDelayImpl, /* SYSTEM_CALL_xTaskAbortDelay. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskAbortDelay. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskAbortDelay. */
#endif
#if ( INCLUDE_vTaskDelay == 1 )
- ( UBaseType_t ) MPU_vTaskDelayImpl, /* SYSTEM_CALL_vTaskDelay. */
+ ( UBaseType_t ) MPU_vTaskDelayImpl, /* SYSTEM_CALL_vTaskDelay. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskDelay. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskDelay. */
#endif
#if ( INCLUDE_uxTaskPriorityGet == 1 )
- ( UBaseType_t ) MPU_uxTaskPriorityGetImpl, /* SYSTEM_CALL_uxTaskPriorityGet. */
+ ( UBaseType_t ) MPU_uxTaskPriorityGetImpl, /* SYSTEM_CALL_uxTaskPriorityGet. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskPriorityGet. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskPriorityGet. */
#endif
#if ( INCLUDE_eTaskGetState == 1 )
- ( UBaseType_t ) MPU_eTaskGetStateImpl, /* SYSTEM_CALL_eTaskGetState. */
+ ( UBaseType_t ) MPU_eTaskGetStateImpl, /* SYSTEM_CALL_eTaskGetState. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_eTaskGetState. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_eTaskGetState. */
#endif
#if ( configUSE_TRACE_FACILITY == 1 )
- ( UBaseType_t ) MPU_vTaskGetInfoImpl, /* SYSTEM_CALL_vTaskGetInfo. */
+ ( UBaseType_t ) MPU_vTaskGetInfoImpl, /* SYSTEM_CALL_vTaskGetInfo. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskGetInfo. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskGetInfo. */
#endif
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
- ( UBaseType_t ) MPU_xTaskGetIdleTaskHandleImpl, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */
+ ( UBaseType_t ) MPU_xTaskGetIdleTaskHandleImpl, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
- ( UBaseType_t ) MPU_vTaskSuspendImpl, /* SYSTEM_CALL_vTaskSuspend. */
- ( UBaseType_t ) MPU_vTaskResumeImpl, /* SYSTEM_CALL_vTaskResume. */
+ ( UBaseType_t ) MPU_vTaskSuspendImpl, /* SYSTEM_CALL_vTaskSuspend. */
+ ( UBaseType_t ) MPU_vTaskResumeImpl, /* SYSTEM_CALL_vTaskResume. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSuspend. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskResume. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSuspend. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskResume. */
#endif
- ( UBaseType_t ) MPU_xTaskGetTickCountImpl, /* SYSTEM_CALL_xTaskGetTickCount. */
- ( UBaseType_t ) MPU_uxTaskGetNumberOfTasksImpl, /* SYSTEM_CALL_uxTaskGetNumberOfTasks. */
- ( UBaseType_t ) MPU_pcTaskGetNameImpl, /* SYSTEM_CALL_pcTaskGetName. */
+ ( UBaseType_t ) MPU_xTaskGetTickCountImpl, /* SYSTEM_CALL_xTaskGetTickCount. */
+ ( UBaseType_t ) MPU_uxTaskGetNumberOfTasksImpl, /* SYSTEM_CALL_uxTaskGetNumberOfTasks. */
#if ( configGENERATE_RUN_TIME_STATS == 1 )
- ( UBaseType_t ) MPU_ulTaskGetRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */
- ( UBaseType_t ) MPU_ulTaskGetRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */
+ ( UBaseType_t ) MPU_ulTaskGetRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */
+ ( UBaseType_t ) MPU_ulTaskGetRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */
#endif
#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
- ( UBaseType_t ) MPU_ulTaskGetIdleRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */
- ( UBaseType_t ) MPU_ulTaskGetIdleRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */
+ ( UBaseType_t ) MPU_ulTaskGetIdleRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */
+ ( UBaseType_t ) MPU_ulTaskGetIdleRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */
#endif
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
- ( UBaseType_t ) MPU_vTaskSetApplicationTaskTagImpl, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */
- ( UBaseType_t ) MPU_xTaskGetApplicationTaskTagImpl, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */
+ ( UBaseType_t ) MPU_vTaskSetApplicationTaskTagImpl, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */
+ ( UBaseType_t ) MPU_xTaskGetApplicationTaskTagImpl, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */
#endif
#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
- ( UBaseType_t ) MPU_vTaskSetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */
- ( UBaseType_t ) MPU_pvTaskGetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */
+ ( UBaseType_t ) MPU_vTaskSetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */
+ ( UBaseType_t ) MPU_pvTaskGetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */
#endif
#if ( configUSE_TRACE_FACILITY == 1 )
- ( UBaseType_t ) MPU_uxTaskGetSystemStateImpl, /* SYSTEM_CALL_uxTaskGetSystemState. */
+ ( UBaseType_t ) MPU_uxTaskGetSystemStateImpl, /* SYSTEM_CALL_uxTaskGetSystemState. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetSystemState. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetSystemState. */
#endif
#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
- ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMarkImpl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */
+ ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMarkImpl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */
#endif
#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
- ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMark2Impl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */
+ ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMark2Impl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */
#endif
#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
- ( UBaseType_t ) MPU_xTaskGetCurrentTaskHandleImpl, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */
+ ( UBaseType_t ) MPU_xTaskGetCurrentTaskHandleImpl, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */
#endif
#if ( INCLUDE_xTaskGetSchedulerState == 1 )
- ( UBaseType_t ) MPU_xTaskGetSchedulerStateImpl, /* SYSTEM_CALL_xTaskGetSchedulerState. */
+ ( UBaseType_t ) MPU_xTaskGetSchedulerStateImpl, /* SYSTEM_CALL_xTaskGetSchedulerState. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetSchedulerState. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetSchedulerState. */
#endif
- ( UBaseType_t ) MPU_vTaskSetTimeOutStateImpl, /* SYSTEM_CALL_vTaskSetTimeOutState. */
- ( UBaseType_t ) MPU_xTaskCheckForTimeOutImpl, /* SYSTEM_CALL_xTaskCheckForTimeOut. */
+ ( UBaseType_t ) MPU_vTaskSetTimeOutStateImpl, /* SYSTEM_CALL_vTaskSetTimeOutState. */
+ ( UBaseType_t ) MPU_xTaskCheckForTimeOutImpl, /* SYSTEM_CALL_xTaskCheckForTimeOut. */
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- ( UBaseType_t ) MPU_ulTaskGenericNotifyTakeImpl, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */
- ( UBaseType_t ) MPU_xTaskGenericNotifyStateClearImpl, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */
- ( UBaseType_t ) MPU_ulTaskGenericNotifyValueClearImpl, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */
+ ( UBaseType_t ) MPU_ulTaskGenericNotifyTakeImpl, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */
+ ( UBaseType_t ) MPU_xTaskGenericNotifyStateClearImpl, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */
+ ( UBaseType_t ) MPU_ulTaskGenericNotifyValueClearImpl, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */
#endif
- ( UBaseType_t ) MPU_xQueueGenericSendImpl, /* SYSTEM_CALL_xQueueGenericSend. */
- ( UBaseType_t ) MPU_uxQueueMessagesWaitingImpl, /* SYSTEM_CALL_uxQueueMessagesWaiting. */
- ( UBaseType_t ) MPU_uxQueueSpacesAvailableImpl, /* SYSTEM_CALL_uxQueueSpacesAvailable. */
- ( UBaseType_t ) MPU_xQueueReceiveImpl, /* SYSTEM_CALL_xQueueReceive. */
- ( UBaseType_t ) MPU_xQueuePeekImpl, /* SYSTEM_CALL_xQueuePeek. */
- ( UBaseType_t ) MPU_xQueueSemaphoreTakeImpl, /* SYSTEM_CALL_xQueueSemaphoreTake. */
+ ( UBaseType_t ) MPU_xQueueGenericSendImpl, /* SYSTEM_CALL_xQueueGenericSend. */
+ ( UBaseType_t ) MPU_uxQueueMessagesWaitingImpl, /* SYSTEM_CALL_uxQueueMessagesWaiting. */
+ ( UBaseType_t ) MPU_uxQueueSpacesAvailableImpl, /* SYSTEM_CALL_uxQueueSpacesAvailable. */
+ ( UBaseType_t ) MPU_xQueueReceiveImpl, /* SYSTEM_CALL_xQueueReceive. */
+ ( UBaseType_t ) MPU_xQueuePeekImpl, /* SYSTEM_CALL_xQueuePeek. */
+ ( UBaseType_t ) MPU_xQueueSemaphoreTakeImpl, /* SYSTEM_CALL_xQueueSemaphoreTake. */
#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
- ( UBaseType_t ) MPU_xQueueGetMutexHolderImpl, /* SYSTEM_CALL_xQueueGetMutexHolder. */
+ ( UBaseType_t ) MPU_xQueueGetMutexHolderImpl, /* SYSTEM_CALL_xQueueGetMutexHolder. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGetMutexHolder. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGetMutexHolder. */
#endif
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
- ( UBaseType_t ) MPU_xQueueTakeMutexRecursiveImpl, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */
- ( UBaseType_t ) MPU_xQueueGiveMutexRecursiveImpl, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */
+ ( UBaseType_t ) MPU_xQueueTakeMutexRecursiveImpl, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */
+ ( UBaseType_t ) MPU_xQueueGiveMutexRecursiveImpl, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */
#endif
#if ( configUSE_QUEUE_SETS == 1 )
- ( UBaseType_t ) MPU_xQueueSelectFromSetImpl, /* SYSTEM_CALL_xQueueSelectFromSet. */
- ( UBaseType_t ) MPU_xQueueAddToSetImpl, /* SYSTEM_CALL_xQueueAddToSet. */
+ ( UBaseType_t ) MPU_xQueueSelectFromSetImpl, /* SYSTEM_CALL_xQueueSelectFromSet. */
+ ( UBaseType_t ) MPU_xQueueAddToSetImpl, /* SYSTEM_CALL_xQueueAddToSet. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueSelectFromSet. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueAddToSet. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueSelectFromSet. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueAddToSet. */
#endif
#if configQUEUE_REGISTRY_SIZE > 0
- ( UBaseType_t ) MPU_vQueueAddToRegistryImpl, /* SYSTEM_CALL_vQueueAddToRegistry. */
- ( UBaseType_t ) MPU_vQueueUnregisterQueueImpl, /* SYSTEM_CALL_vQueueUnregisterQueue. */
- ( UBaseType_t ) MPU_pcQueueGetNameImpl, /* SYSTEM_CALL_pcQueueGetName. */
+ ( UBaseType_t ) MPU_vQueueAddToRegistryImpl, /* SYSTEM_CALL_vQueueAddToRegistry. */
+ ( UBaseType_t ) MPU_vQueueUnregisterQueueImpl, /* SYSTEM_CALL_vQueueUnregisterQueue. */
+ ( UBaseType_t ) MPU_pcQueueGetNameImpl, /* SYSTEM_CALL_pcQueueGetName. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueAddToRegistry. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueUnregisterQueue. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_pcQueueGetName. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueAddToRegistry. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueUnregisterQueue. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_pcQueueGetName. */
#endif
#if ( configUSE_TIMERS == 1 )
- ( UBaseType_t ) MPU_pvTimerGetTimerIDImpl, /* SYSTEM_CALL_pvTimerGetTimerID. */
- ( UBaseType_t ) MPU_vTimerSetTimerIDImpl, /* SYSTEM_CALL_vTimerSetTimerID. */
- ( UBaseType_t ) MPU_xTimerIsTimerActiveImpl, /* SYSTEM_CALL_xTimerIsTimerActive. */
- ( UBaseType_t ) MPU_xTimerGetTimerDaemonTaskHandleImpl, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */
- ( UBaseType_t ) MPU_pcTimerGetNameImpl, /* SYSTEM_CALL_pcTimerGetName. */
- ( UBaseType_t ) MPU_vTimerSetReloadModeImpl, /* SYSTEM_CALL_vTimerSetReloadMode. */
- ( UBaseType_t ) MPU_xTimerGetReloadModeImpl, /* SYSTEM_CALL_xTimerGetReloadMode. */
- ( UBaseType_t ) MPU_uxTimerGetReloadModeImpl, /* SYSTEM_CALL_uxTimerGetReloadMode. */
- ( UBaseType_t ) MPU_xTimerGetPeriodImpl, /* SYSTEM_CALL_xTimerGetPeriod. */
- ( UBaseType_t ) MPU_xTimerGetExpiryTimeImpl, /* SYSTEM_CALL_xTimerGetExpiryTime. */
- #else /* if ( configUSE_TIMERS == 1 ) */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTimerGetTimerID. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetTimerID. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerIsTimerActive. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_pcTimerGetName. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetReloadMode. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetReloadMode. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTimerGetReloadMode. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetPeriod. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetExpiryTime. */
- #endif /* if ( configUSE_TIMERS == 1 ) */
-
- ( UBaseType_t ) MPU_xEventGroupClearBitsImpl, /* SYSTEM_CALL_xEventGroupClearBits. */
- ( UBaseType_t ) MPU_xEventGroupSetBitsImpl, /* SYSTEM_CALL_xEventGroupSetBits. */
- ( UBaseType_t ) MPU_xEventGroupSyncImpl, /* SYSTEM_CALL_xEventGroupSync. */
-
- #if ( configUSE_TRACE_FACILITY == 1 )
- ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl, /* SYSTEM_CALL_uxEventGroupGetNumber. */
- ( UBaseType_t ) MPU_vEventGroupSetNumberImpl, /* SYSTEM_CALL_vEventGroupSetNumber. */
+ ( UBaseType_t ) MPU_pvTimerGetTimerIDImpl, /* SYSTEM_CALL_pvTimerGetTimerID. */
+ ( UBaseType_t ) MPU_vTimerSetTimerIDImpl, /* SYSTEM_CALL_vTimerSetTimerID. */
+ ( UBaseType_t ) MPU_xTimerIsTimerActiveImpl, /* SYSTEM_CALL_xTimerIsTimerActive. */
+ ( UBaseType_t ) MPU_xTimerGetTimerDaemonTaskHandleImpl, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */
+ ( UBaseType_t ) MPU_pcTimerGetNameImpl, /* SYSTEM_CALL_pcTimerGetName. */
+ ( UBaseType_t ) MPU_vTimerSetReloadModeImpl, /* SYSTEM_CALL_vTimerSetReloadMode. */
+ ( UBaseType_t ) MPU_xTimerGetReloadModeImpl, /* SYSTEM_CALL_xTimerGetReloadMode. */
+ ( UBaseType_t ) MPU_uxTimerGetReloadModeImpl, /* SYSTEM_CALL_uxTimerGetReloadMode. */
+ ( UBaseType_t ) MPU_xTimerGetPeriodImpl, /* SYSTEM_CALL_xTimerGetPeriod. */
+ ( UBaseType_t ) MPU_xTimerGetExpiryTimeImpl, /* SYSTEM_CALL_xTimerGetExpiryTime. */
#else
- ( UBaseType_t ) 0, /* SYSTEM_CALL_uxEventGroupGetNumber. */
- ( UBaseType_t ) 0, /* SYSTEM_CALL_vEventGroupSetNumber. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTimerGetTimerID. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetTimerID. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerIsTimerActive. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_pcTimerGetName. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetReloadMode. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetReloadMode. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTimerGetReloadMode. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetPeriod. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetExpiryTime. */
#endif
- ( UBaseType_t ) MPU_xStreamBufferSendImpl, /* SYSTEM_CALL_xStreamBufferSend. */
- ( UBaseType_t ) MPU_xStreamBufferReceiveImpl, /* SYSTEM_CALL_xStreamBufferReceive. */
- ( UBaseType_t ) MPU_xStreamBufferIsFullImpl, /* SYSTEM_CALL_xStreamBufferIsFull. */
- ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl, /* SYSTEM_CALL_xStreamBufferIsEmpty. */
- ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl, /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */
- ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl, /* SYSTEM_CALL_xStreamBufferBytesAvailable. */
- ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl, /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */
- ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */
+ #if ( configUSE_EVENT_GROUPS == 1 )
+ ( UBaseType_t ) MPU_xEventGroupClearBitsImpl, /* SYSTEM_CALL_xEventGroupClearBits. */
+ ( UBaseType_t ) MPU_xEventGroupSetBitsImpl, /* SYSTEM_CALL_xEventGroupSetBits. */
+ ( UBaseType_t ) MPU_xEventGroupSyncImpl, /* SYSTEM_CALL_xEventGroupSync. */
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl, /* SYSTEM_CALL_uxEventGroupGetNumber. */
+ ( UBaseType_t ) MPU_vEventGroupSetNumberImpl, /* SYSTEM_CALL_vEventGroupSetNumber. */
+ #else
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_uxEventGroupGetNumber. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vEventGroupSetNumber. */
+ #endif
+ #else
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupClearBits. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupSetBits. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupSync. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_uxEventGroupGetNumber. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_vEventGroupSetNumber. */
+ #endif
+
+ #if ( configUSE_STREAM_BUFFERS == 1 )
+ ( UBaseType_t ) MPU_xStreamBufferSendImpl, /* SYSTEM_CALL_xStreamBufferSend. */
+ ( UBaseType_t ) MPU_xStreamBufferReceiveImpl, /* SYSTEM_CALL_xStreamBufferReceive. */
+ ( UBaseType_t ) MPU_xStreamBufferIsFullImpl, /* SYSTEM_CALL_xStreamBufferIsFull. */
+ ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl, /* SYSTEM_CALL_xStreamBufferIsEmpty. */
+ ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl, /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */
+ ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl, /* SYSTEM_CALL_xStreamBufferBytesAvailable. */
+ ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl, /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */
+ ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */
+ #else
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferSend. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferReceive. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferIsFull. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferIsEmpty. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferBytesAvailable. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */
+ ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */
+ #endif
+
};
/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CA9/port.c b/Source/portable/GCC/ARM_CA9/port.c
index 79fa32d..cb724d0 100644
--- a/Source/portable/GCC/ARM_CA9/port.c
+++ b/Source/portable/GCC/ARM_CA9/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -35,123 +35,123 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #if ( configMAX_PRIORITIES > 32 )
+ #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
#endif
/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
+ * portmacro.h. */
#ifndef configCLEAR_TICK_INTERRUPT
#define configCLEAR_TICK_INTERRUPT()
#endif
/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created. A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+ * floating point context after they have been created. A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+ * point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* The critical section macros only mask interrupts up to an application
-determined priority level. Sometimes it is necessary to turn interrupt off in
-the CPU itself before modifying certain hardware registers. */
-#define portCPU_IRQ_DISABLE() \
- __asm volatile ( "CPSID i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
+ * determined priority level. Sometimes it is necessary to turn interrupt off in
+ * the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE() \
+ __asm volatile ( "CPSID i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
__asm volatile ( "ISB" );
-#define portCPU_IRQ_ENABLE() \
- __asm volatile ( "CPSIE i" ::: "memory" ); \
- __asm volatile ( "DSB" ); \
+#define portCPU_IRQ_ENABLE() \
+ __asm volatile ( "CPSIE i" ::: "memory" ); \
+ __asm volatile ( "DSB" ); \
__asm volatile ( "ISB" );
/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
-{ \
- portCPU_IRQ_DISABLE(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm volatile ( "DSB \n" \
- "ISB \n" ); \
- portCPU_IRQ_ENABLE(); \
-}
+#define portCLEAR_INTERRUPT_MASK() \
+ { \
+ portCPU_IRQ_DISABLE(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm volatile ( "DSB \n" \
+ "ISB \n" ); \
+ portCPU_IRQ_ENABLE(); \
+ }
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portBIT_0_SET ( ( uint8_t ) 0x01 )
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )
/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* The space on the stack required to hold the FPU registers. This is 32 64-bit
-registers, plus a 32-bit status register. */
-#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
+ * registers, plus a 32-bit status register. */
+#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
/*-----------------------------------------------------------*/
@@ -185,47 +185,49 @@
* FPU registers to be saved on interrupt entry their IRQ handler must be
* called vApplicationIRQHandler().
*/
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) );
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts. As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts. As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
+ * a floating point context must be saved and restored for the task. */
volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
volatile uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
volatile uint32_t ulPortInterruptNesting = 0UL;
/* Used in the asm file. */
-__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+__attribute__( ( used ) ) const uint32_t ulICCIARAddress = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCEOIRAddress = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCPMRAddress = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro.
-
- The fist real value on the stack is the status register, which is set for
- system mode, with interrupts enabled. A few NULLs are added first to ensure
- GDB does not try decoding a non-existent return address. */
+ * expected by the portRESTORE_CONTEXT() macro.
+ *
+ * The fist real value on the stack is the status register, which is set for
+ * system mode, with interrupts enabled. A few NULLs are added first to ensure
+ * GDB does not try decoding a non-existent return address. */
*pxTopOfStack = ( StackType_t ) NULL;
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) NULL;
@@ -247,51 +249,51 @@
pxTopOfStack--;
/* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
- enabled. */
+ * enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
- #if( configUSE_TASK_FPU_SUPPORT == 1 )
+ #if ( configUSE_TASK_FPU_SUPPORT == 1 )
{
/* The task will start without a floating point context. A task that
- uses the floating point hardware must call vPortTaskUsesFPU() before
- executing any floating point instructions. */
+ * uses the floating point hardware must call vPortTaskUsesFPU() before
+ * executing any floating point instructions. */
pxTopOfStack--;
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
}
- #elif( configUSE_TASK_FPU_SUPPORT == 2 )
+ #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
{
/* The task will start with a floating point context. Leave enough
- space for the registers - and ensure they are initialised to 0. */
+ * space for the registers - and ensure they are initialised to 0. */
pxTopOfStack -= portFPU_REGISTER_WORDS;
memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
@@ -299,11 +301,11 @@
*pxTopOfStack = pdTRUE;
ulPortTaskHasFPUContext = pdTRUE;
}
- #else
+ #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
{
- #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
+ #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
}
- #endif
+ #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
return pxTopOfStack;
}
@@ -312,34 +314,37 @@
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
- its caller as there is nothing to return to. If a task wants to exit it
- should instead call vTaskDelete( NULL ).
-
- Artificially force an assert() to be triggered if configASSERT() is
- defined, then stop here so application writers can catch the error. */
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
configASSERT( ulPortInterruptNesting == ~0UL );
portDISABLE_INTERRUPTS();
- for( ;; );
+
+ for( ; ; )
+ {
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
-uint32_t ulAPSR;
+ uint32_t ulAPSR;
- #if( configASSERT_DEFINED == 1 )
+ #if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
volatile uint8_t ucMaxPriorityValue;
/* Determine how many priority bits are implemented in the GIC.
-
- Save the interrupt priority value that is about to be clobbered. */
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
ucOriginalPriority = *pucFirstUserPriorityRegister;
/* Determine the number of priority bits available. First write to
- all possible bits. */
+ * all possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
/* Read the value back to see how many bits stuck. */
@@ -352,35 +357,35 @@
}
/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
- value. */
+ * value. */
configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
/* Restore the clobbered interrupt priority register to its original
- value. */
+ * value. */
*pucFirstUserPriorityRegister = ucOriginalPriority;
}
#endif /* configASSERT_DEFINED */
/* Only continue if the CPU is not in User mode. The CPU must be in a
- Privileged mode for the scheduler to start. */
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+ * Privileged mode for the scheduler to start. */
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE );
if( ulAPSR != portAPSR_USER_MODE )
{
/* Only continue if the binary point value is set to its lowest possible
- setting. See the comments in vPortValidateInterruptPriority() below for
- more information. */
+ * setting. See the comments in vPortValidateInterruptPriority() below for
+ * more information. */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
{
/* Interrupts are turned off in the CPU itself to ensure tick does
- not execute while the scheduler is being started. Interrupts are
- automatically turned back on in the CPU when the first task starts
- executing. */
+ * not execute while the scheduler is being started. Interrupts are
+ * automatically turned back on in the CPU when the first task starts
+ * executing. */
portCPU_IRQ_DISABLE();
/* Start the timer that generates the tick ISR. */
@@ -392,10 +397,10 @@
}
/* Will only get here if vTaskStartScheduler() was called with the CPU in
- a non-privileged mode or the binary point register was not set to its lowest
- possible value. prvTaskExitError() is referenced to prevent a compiler
- warning about it being defined but not referenced in the case that the user
- defines their own exit address. */
+ * a non-privileged mode or the binary point register was not set to its lowest
+ * possible value. prvTaskExitError() is referenced to prevent a compiler
+ * warning about it being defined but not referenced in the case that the user
+ * defines their own exit address. */
( void ) prvTaskExitError;
return 0;
}
@@ -404,7 +409,7 @@
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
+ * Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@@ -414,16 +419,16 @@
/* Mask interrupts up to the max syscall interrupt priority. */
ulPortSetInterruptMask();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
+ /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+ * directly. Increment ulCriticalNesting to keep a count of how many times
+ * portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
- assert() if it is being called from an interrupt context. Only API
- functions that end in "FromISR" can be used in an interrupt. Only assert if
- the critical nesting count is 1 to protect against recursive calls if the
- assert function also uses a critical section. */
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
if( ulCriticalNesting == 1 )
{
configASSERT( ulPortInterruptNesting == 0 );
@@ -436,15 +441,15 @@
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
- exited. */
+ * exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
+ * priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
+ * should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@@ -454,14 +459,14 @@
void FreeRTOS_Tick_Handler( void )
{
/* Set interrupt mask before altering scheduler structures. The tick
- handler runs at the lowest priority, so interrupts cannot already be masked,
- so there is no need to save and restore the current mask value. It is
- necessary to turn off interrupts in the CPU itself while the ICCPMR is being
- updated. */
+ * handler runs at the lowest priority, so interrupts cannot already be masked,
+ * so there is no need to save and restore the current mask value. It is
+ * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+ * updated. */
portCPU_IRQ_DISABLE();
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n" ::: "memory" );
+ __asm volatile ( "dsb \n"
+ "isb \n" ::: "memory" );
portCPU_IRQ_ENABLE();
/* Increment the RTOS tick. */
@@ -476,18 +481,18 @@
}
/*-----------------------------------------------------------*/
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
void vPortTaskUsesFPU( void )
{
- uint32_t ulInitialFPSCR = 0;
+ uint32_t ulInitialFPSCR = 0;
/* A task is registering the fact that it needs an FPU context. Set the
- FPU flag (which is saved as part of the task context). */
+ * FPU flag (which is saved as part of the task context). */
ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */
- __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+ __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
}
#endif /* configUSE_TASK_FPU_SUPPORT */
@@ -504,11 +509,12 @@
uint32_t ulPortSetInterruptMask( void )
{
-uint32_t ulReturn;
+ uint32_t ulReturn;
/* Interrupt in the CPU must be turned off while the ICCPMR is being
- updated. */
+ * updated. */
portCPU_IRQ_DISABLE();
+
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@@ -518,45 +524,46 @@
{
ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm volatile ( "dsb \n"
- "isb \n" ::: "memory" );
+ __asm volatile ( "dsb \n"
+ "isb \n" ::: "memory" );
}
+
portCPU_IRQ_ENABLE();
return ulReturn;
}
/*-----------------------------------------------------------*/
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
- an interrupt that has been assigned a priority above
- configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- function. ISR safe FreeRTOS API functions must *only* be called
- from interrupts that have been assigned a priority at or below
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- Numerically low interrupt priority numbers represent logically high
- interrupt priorities, therefore the priority of the interrupt must
- be set to a value equal to or numerically *higher* than
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- FreeRTOS maintains separate thread and ISR API functions to ensure
- interrupt entry is as fast and simple as possible. */
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible. */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
- that define each interrupt's priority to be split between bits that
- define the interrupt's pre-emption priority bits and bits that define
- the interrupt's sub-priority. For simplicity all bits must be defined
- to be pre-emption priority bits. The following assertion will fail if
- this is not the case (if some bits represent a sub-priority).
-
- The priority grouping is configured by the GIC's binary point register
- (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- possible value (which may be above 0). */
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * The priority grouping is configured by the GIC's binary point register
+ * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
+ * possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}
diff --git a/Source/portable/GCC/ARM_CA9/portASM.S b/Source/portable/GCC/ARM_CA9/portASM.S
index c9eb16d..61caf27 100644
--- a/Source/portable/GCC/ARM_CA9/portASM.S
+++ b/Source/portable/GCC/ARM_CA9/portASM.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -33,10 +33,10 @@
.set SVC_MODE, 0x13
.set IRQ_MODE, 0x12
- /* Hardware registers. */
- .extern ulICCIAR
- .extern ulICCEOIR
- .extern ulICCPMR
+ /* Hardware registers addresses. */
+ .extern ulICCIARAddress
+ .extern ulICCEOIRAddress
+ .extern ulICCPMRAddress
/* Variables and functions. */
.extern ulMaxAPIPriorityMask
@@ -75,9 +75,9 @@
/* Save the floating point context, if any. */
FMRXNE R1, FPSCR
+ PUSHNE {R1}
VPUSHNE {D0-D15}
VPUSHNE {D16-D31}
- PUSHNE {R1}
/* Save ulPortTaskHasFPUContext itself. */
PUSH {R3}
@@ -106,9 +106,9 @@
CMP R1, #0
/* Restore the floating point context, if any. */
- POPNE {R0}
VPOPNE {D16-D31}
VPOPNE {D0-D15}
+ POPNE {R0}
VMSRNE FPSCR, R0
/* Restore the critical section nesting depth. */
@@ -145,8 +145,15 @@
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
+
+ /* Ensure bit 2 of the stack pointer is clear. */
+ MOV r2, sp
+ AND r2, r2, #4
+ SUB sp, sp, r2
+
LDR R0, vTaskSwitchContextConst
BLX R0
+
portRESTORE_CONTEXT
@@ -239,7 +246,7 @@
MOVS PC, LR
switch_before_exit:
- /* A context swtich is to be performed. Clear the context switch pending
+ /* A context switch is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
@@ -256,7 +263,13 @@
/* Call the function that selects the new task to execute.
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
instructions, or 8 byte aligned stack allocated data. LR does not need
- saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+ saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+ Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
+ future use. */
+ MOV r2, sp
+ AND r2, r2, #4
+ SUB sp, sp, r2
+
LDR R0, vTaskSwitchContextConst
BLX R0
@@ -289,7 +302,7 @@
vApplicationIRQHandler:
PUSH {LR}
FMRX R1, FPSCR
- VPUSH {D0-D15}
+ VPUSH {D0-D7}
VPUSH {D16-D31}
PUSH {R1}
@@ -298,15 +311,15 @@
POP {R0}
VPOP {D16-D31}
- VPOP {D0-D15}
+ VPOP {D0-D7}
VMSR FPSCR, R0
POP {PC}
-ulICCIARConst: .word ulICCIAR
-ulICCEOIRConst: .word ulICCEOIR
-ulICCPMRConst: .word ulICCPMR
+ulICCIARConst: .word ulICCIARAddress
+ulICCEOIRConst: .word ulICCEOIRAddress
+ulICCPMRConst: .word ulICCPMRAddress
pxCurrentTCBConst: .word pxCurrentTCB
ulCriticalNestingConst: .word ulCriticalNesting
ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
diff --git a/Source/portable/GCC/ARM_CA9/portmacro.h b/Source/portable/GCC/ARM_CA9/portmacro.h
index a88b3d8..76255db 100644
--- a/Source/portable/GCC/ARM_CA9/portmacro.h
+++ b/Source/portable/GCC/ARM_CA9/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -46,54 +46,54 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
+ * not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{ \
-extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ { \
+ extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+ }
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
@@ -102,105 +102,106 @@
extern void vPortInstallFreeRTOSVectorTable( void );
/* These macros do not globally disable/enable interrupts. They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
-created without an FPU context and must call vPortTaskUsesFPU() to give
-themselves an FPU context before using any FPU instructions. If
-configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
-by default. */
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
+ * created without an FPU context and must call vPortTaskUsesFPU() to give
+ * themselves an FPU context before using any FPU instructions. If
+ * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+ * by default. */
+#if ( configUSE_TASK_FPU_SUPPORT != 2 )
void vPortTaskUsesFPU( void );
#else
- /* Each task has an FPU context already, so define this function away to
- nothing to prevent it being called accidentally. */
+
+/* Each task has an FPU context already, so define this function away to
+ * nothing to prevent it being called accidentally. */
#define vPortTaskUsesFPU()
#endif
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
/* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
- /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif /* configASSERT */
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
+#define portNOP() __asm volatile ( "NOP" )
+#define portINLINE __inline
/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
-#else
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
new file mode 100644
index 0000000..2a7af2e
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
@@ -0,0 +1,2217 @@
+/*
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+#include "mpu_prototypes.h"
+#include "mpu_syscall_numbers.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( INCLUDE_xTaskDelayUntil == 1 )
+
+ BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+ const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+ const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskDelayUntilImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskDelayUntil_Unpriv \n"
+ " MPU_xTaskDelayUntil_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskDelayUntilImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskDelayUntil_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskAbortDelay == 1 )
+
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskAbortDelayImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskAbortDelay_Unpriv \n"
+ " MPU_xTaskAbortDelay_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskAbortDelayImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskAbortDelay_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskDelay == 1 )
+
+ void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskDelayImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTaskDelay_Unpriv \n"
+ " MPU_vTaskDelay_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTaskDelayImpl \n"
+ " pop {pc} \n"
+ " MPU_vTaskDelay_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskPriorityGetImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxTaskPriorityGet_Unpriv \n"
+ " MPU_uxTaskPriorityGet_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxTaskPriorityGetImpl \n"
+ " pop {pc} \n"
+ " MPU_uxTaskPriorityGet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+
+ eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_eTaskGetStateImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_eTaskGetState_Unpriv \n"
+ " MPU_eTaskGetState_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_eTaskGetStateImpl \n"
+ " pop {pc} \n"
+ " MPU_eTaskGetState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ void MPU_vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskGetInfoImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTaskGetInfo_Unpriv \n"
+ " MPU_vTaskGetInfo_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTaskGetInfoImpl \n"
+ " pop {pc} \n"
+ " MPU_vTaskGetInfo_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetIdleTaskHandleImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
+ " MPU_xTaskGetIdleTaskHandle_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGetIdleTaskHandleImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+
+ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSuspendImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTaskSuspend_Unpriv \n"
+ " MPU_vTaskSuspend_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTaskSuspendImpl \n"
+ " pop {pc} \n"
+ " MPU_vTaskSuspend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+
+ void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskResumeImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTaskResume_Unpriv \n"
+ " MPU_vTaskResume_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTaskResumeImpl \n"
+ " pop {pc} \n"
+ " MPU_vTaskResume_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetTickCountImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGetTickCount_Unpriv \n"
+ " MPU_xTaskGetTickCount_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGetTickCountImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGetTickCount_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetNumberOfTasksImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
+ " MPU_uxTaskGetNumberOfTasks_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxTaskGetNumberOfTasksImpl \n"
+ " pop {pc} \n"
+ " MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetRunTimeCounterImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
+ " MPU_ulTaskGetRunTimeCounter_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_ulTaskGetRunTimeCounterImpl \n"
+ " pop {pc} \n"
+ " MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetRunTimePercentImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
+ " MPU_ulTaskGetRunTimePercent_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_ulTaskGetRunTimePercentImpl \n"
+ " pop {pc} \n"
+ " MPU_ulTaskGetRunTimePercent_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
+ " MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_ulTaskGetIdleRunTimePercentImpl \n"
+ " pop {pc} \n"
+ " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
+ " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_ulTaskGetIdleRunTimeCounterImpl \n"
+ " pop {pc} \n"
+ " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+ TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+ TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetApplicationTaskTagImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
+ " MPU_vTaskSetApplicationTaskTag_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTaskSetApplicationTaskTagImpl \n"
+ " pop {pc} \n"
+ " MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetApplicationTaskTagImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
+ " MPU_xTaskGetApplicationTaskTag_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGetApplicationTaskTagImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+ BaseType_t xIndex,
+ void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+ BaseType_t xIndex,
+ void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
+ " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTaskSetThreadLocalStoragePointerImpl \n"
+ " pop {pc} \n"
+ " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
+ );
+ }
+
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+ BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+ BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
+ " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
+ " pop {pc} \n"
+ " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
+ );
+ }
+
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+ const UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+ const UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetSystemStateImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxTaskGetSystemState_Unpriv \n"
+ " MPU_uxTaskGetSystemState_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxTaskGetSystemStateImpl \n"
+ " pop {pc} \n"
+ " MPU_uxTaskGetSystemState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
+ " MPU_uxTaskGetStackHighWaterMark_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxTaskGetStackHighWaterMarkImpl \n"
+ " pop {pc} \n"
+ " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
+ " MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxTaskGetStackHighWaterMark2Impl \n"
+ " pop {pc} \n"
+ " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetCurrentTaskHandleImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
+ " MPU_xTaskGetCurrentTaskHandle_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGetCurrentTaskHandleImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+
+ BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGetSchedulerStateImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGetSchedulerState_Unpriv \n"
+ " MPU_xTaskGetSchedulerState_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGetSchedulerStateImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGetSchedulerState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
+ );
+ }
+
+ #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTaskSetTimeOutStateImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTaskSetTimeOutState_Unpriv \n"
+ " MPU_vTaskSetTimeOutState_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTaskSetTimeOutStateImpl \n"
+ " pop {pc} \n"
+ " MPU_vTaskSetTimeOutState_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+ TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+ TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskCheckForTimeOutImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskCheckForTimeOut_Unpriv \n"
+ " MPU_xTaskCheckForTimeOut_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskCheckForTimeOutImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskCheckForTimeOut_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGenericNotify_Unpriv \n"
+ " MPU_xTaskGenericNotify_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGenericNotifyImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGenericNotify_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyWaitImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGenericNotifyWait_Unpriv \n"
+ " MPU_xTaskGenericNotifyWait_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGenericNotifyWaitImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGenericNotifyWait_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+ BaseType_t xClearCountOnExit,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+ BaseType_t xClearCountOnExit,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGenericNotifyTakeImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
+ " MPU_ulTaskGenericNotifyTake_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_ulTaskGenericNotifyTakeImpl \n"
+ " pop {pc} \n"
+ " MPU_ulTaskGenericNotifyTake_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTaskGenericNotifyStateClearImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
+ " MPU_xTaskGenericNotifyStateClear_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTaskGenericNotifyStateClearImpl \n"
+ " pop {pc} \n"
+ " MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear,
+ uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear,
+ uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_ulTaskGenericNotifyValueClearImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
+ " MPU_ulTaskGenericNotifyValueClear_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_ulTaskGenericNotifyValueClearImpl \n"
+ " pop {pc} \n"
+ " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+ const void * const pvItemToQueue,
+ TickType_t xTicksToWait,
+ const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+ const void * const pvItemToQueue,
+ TickType_t xTicksToWait,
+ const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGenericSendImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueGenericSend_Unpriv \n"
+ " MPU_xQueueGenericSend_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueGenericSendImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueGenericSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxQueueMessagesWaitingImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxQueueMessagesWaiting_Unpriv \n"
+ " MPU_uxQueueMessagesWaiting_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxQueueMessagesWaitingImpl \n"
+ " pop {pc} \n"
+ " MPU_uxQueueMessagesWaiting_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxQueueSpacesAvailableImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxQueueSpacesAvailable_Unpriv \n"
+ " MPU_uxQueueSpacesAvailable_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxQueueSpacesAvailableImpl \n"
+ " pop {pc} \n"
+ " MPU_uxQueueSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueReceiveImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueReceive_Unpriv \n"
+ " MPU_xQueueReceive_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueReceiveImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueuePeekImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueuePeek_Unpriv \n"
+ " MPU_xQueuePeek_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueuePeekImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueuePeek_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueSemaphoreTakeImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueSemaphoreTake_Unpriv \n"
+ " MPU_xQueueSemaphoreTake_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueSemaphoreTakeImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueSemaphoreTake_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGetMutexHolderImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueGetMutexHolder_Unpriv \n"
+ " MPU_xQueueGetMutexHolder_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueGetMutexHolderImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueGetMutexHolder_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
+ );
+ }
+
+ #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueTakeMutexRecursiveImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
+ " MPU_xQueueTakeMutexRecursive_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueTakeMutexRecursiveImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueTakeMutexRecursive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueGiveMutexRecursiveImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
+ " MPU_xQueueGiveMutexRecursive_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueGiveMutexRecursiveImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueGiveMutexRecursive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueSelectFromSetImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueSelectFromSet_Unpriv \n"
+ " MPU_xQueueSelectFromSet_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueSelectFromSetImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueSelectFromSet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xQueueAddToSetImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xQueueAddToSet_Unpriv \n"
+ " MPU_xQueueAddToSet_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xQueueAddToSetImpl \n"
+ " pop {pc} \n"
+ " MPU_xQueueAddToSet_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+ const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+ const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vQueueAddToRegistryImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vQueueAddToRegistry_Unpriv \n"
+ " MPU_vQueueAddToRegistry_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vQueueAddToRegistryImpl \n"
+ " pop {pc} \n"
+ " MPU_vQueueAddToRegistry_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vQueueUnregisterQueueImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vQueueUnregisterQueue_Unpriv \n"
+ " MPU_vQueueUnregisterQueue_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vQueueUnregisterQueueImpl \n"
+ " pop {pc} \n"
+ " MPU_vQueueUnregisterQueue_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pcQueueGetNameImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_pcQueueGetName_Unpriv \n"
+ " MPU_pcQueueGetName_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_pcQueueGetNameImpl \n"
+ " pop {pc} \n"
+ " MPU_pcQueueGetName_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
+ );
+ }
+
+ #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pvTimerGetTimerIDImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_pvTimerGetTimerID_Unpriv \n"
+ " MPU_pvTimerGetTimerID_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_pvTimerGetTimerIDImpl \n"
+ " pop {pc} \n"
+ " MPU_pvTimerGetTimerID_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+ void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+ void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTimerSetTimerIDImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTimerSetTimerID_Unpriv \n"
+ " MPU_vTimerSetTimerID_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTimerSetTimerIDImpl \n"
+ " pop {pc} \n"
+ " MPU_vTimerSetTimerID_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerIsTimerActiveImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerIsTimerActive_Unpriv \n"
+ " MPU_xTimerIsTimerActive_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTimerIsTimerActiveImpl \n"
+ " pop {pc} \n"
+ " MPU_xTimerIsTimerActive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
+ " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
+ " pop {pc} \n"
+ " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTimerGenericCommandFromTaskImpl \n"
+ " pop {pc} \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_pcTimerGetNameImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_pcTimerGetName_Unpriv \n"
+ " MPU_pcTimerGetName_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_pcTimerGetNameImpl \n"
+ " pop {pc} \n"
+ " MPU_pcTimerGetName_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vTimerSetReloadModeImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vTimerSetReloadMode_Unpriv \n"
+ " MPU_vTimerSetReloadMode_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vTimerSetReloadModeImpl \n"
+ " pop {pc} \n"
+ " MPU_vTimerSetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetReloadModeImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerGetReloadMode_Unpriv \n"
+ " MPU_xTimerGetReloadMode_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTimerGetReloadModeImpl \n"
+ " pop {pc} \n"
+ " MPU_xTimerGetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxTimerGetReloadModeImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxTimerGetReloadMode_Unpriv \n"
+ " MPU_uxTimerGetReloadMode_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxTimerGetReloadModeImpl \n"
+ " pop {pc} \n"
+ " MPU_uxTimerGetReloadMode_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetPeriodImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerGetPeriod_Unpriv \n"
+ " MPU_xTimerGetPeriod_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTimerGetPeriodImpl \n"
+ " pop {pc} \n"
+ " MPU_xTimerGetPeriod_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xTimerGetExpiryTimeImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerGetExpiryTime_Unpriv \n"
+ " MPU_xTimerGetExpiryTime_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xTimerGetExpiryTimeImpl \n"
+ " pop {pc} \n"
+ " MPU_xTimerGetExpiryTime_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
+ );
+ }
+
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xEventGroupWaitBitsImpl \n"
+ " pop {pc} \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xEventGroupClearBitsImpl \n"
+ " pop {pc} \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xEventGroupSetBitsImpl \n"
+ " pop {pc} \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xEventGroupSyncImpl \n"
+ " pop {pc} \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_uxEventGroupGetNumberImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_uxEventGroupGetNumber_Unpriv \n"
+ " MPU_uxEventGroupGetNumber_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_uxEventGroupGetNumberImpl \n"
+ " pop {pc} \n"
+ " MPU_uxEventGroupGetNumber_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
+ );
+ }
+
+ #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+
+ void MPU_vEventGroupSetNumber( void * xEventGroup,
+ UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ void MPU_vEventGroupSetNumber( void * xEventGroup,
+ UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_vEventGroupSetNumberImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_vEventGroupSetNumber_Unpriv \n"
+ " MPU_vEventGroupSetNumber_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_vEventGroupSetNumberImpl \n"
+ " pop {pc} \n"
+ " MPU_vEventGroupSetNumber_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
+ );
+ }
+
+ #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferSendImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferReceiveImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferIsFullImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferIsEmptyImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferSpacesAvailableImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferBytesAvailableImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " push {lr} \n"
+ " blx MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " pop {pc} \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+/*-----------------------------------------------------------*/
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM0/port.c b/Source/portable/GCC/ARM_CM0/port.c
index 063a33e..e9ef847 100644
--- a/Source/portable/GCC/ARM_CM0/port.c
+++ b/Source/portable/GCC/ARM_CM0/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -26,47 +26,195 @@
*
*/
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM0 port.
-*----------------------------------------------------------*/
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
-/* Constants required to manipulate the NVIC. */
+/* MPU includes. */
+#include "mpu_wrappers.h"
+#include "mpu_syscall_numbers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000 )
+/*-----------------------------------------------------------*/
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#ifndef portMISSED_COUNTS_FACTOR
- #define portMISSED_COUNTS_FACTOR ( 94UL )
-#endif
+/*-----------------------------------------------------------*/
-/* Let the user override the default SysTick clock rate. If defined by the
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used during system call enter and exit.
+ */
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Offsets in the stack to the parameters when inside the SVC handler.
+ */
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RASR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+/* MPU Region Attribute and Size Register (RASR) bitmasks. */
+#define portMPU_RASR_AP_BITMASK ( 0x7UL << 24UL )
+#define portMPU_RASR_S_C_B_BITMASK ( 0x7UL )
+#define portMPU_RASR_S_C_B_LOCATION ( 16UL )
+#define portMPU_RASR_SIZE_BITMASK ( 0x1FUL << 1UL )
+#define portMPU_RASR_REGION_ENABLE_BITMASK ( 0x1UL )
+
+/* MPU Region Base Address Register (RBAR) bitmasks. */
+#define portMPU_RBAR_ADDRESS_BITMASK ( 0xFFFFFF00UL )
+#define portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ( 0x1UL << 4UL )
+#define portMPU_RBAR_REGION_NUMBER_BITMASK ( 0x0000000FUL )
+
+/* MPU Control Register (MPU_CTRL) bitmasks. */
+#define portMPU_CTRL_ENABLE_BITMASK ( 0x1UL )
+#define portMPU_CTRL_PRIV_BACKGROUND_ENABLE_BITMASK ( 0x1UL << 2UL ) /* PRIVDEFENA bit. */
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 0x8UL << 8UL ) /* 8 DREGION unified. */
+
+/* Extract first address of the MPU region as encoded in the
+ * RBAR (Region Base Address Register) value. */
+#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
+ ( ( rbar ) & portMPU_RBAR_ADDRESS_BITMASK )
+
+/* Extract size of the MPU region as encoded in the
+ * RASR (Region Attribute and Size Register) value. */
+#define portEXTRACT_REGION_SIZE_FROM_RASR( rasr ) \
+ ( 1 << ( ( ( ( rasr ) & portMPU_RASR_SIZE_BITMASK ) >> 1 )+ 1 ) )
+
+/* Does addr lies within [start, end] address range? */
+#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
+ ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
+
+/* Is the access request satisfied by the available permissions? */
+#define portIS_AUTHORIZED( accessRequest, permissions ) \
+ ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
+
+/* Max value that fits in a uint32_t type. */
+#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> Reserved, 1.
+ */
+#define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
* user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
- * configuration register. */
+ * configuration register.
+ */
#ifndef configSYSTICK_CLOCK_HZ
#define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
/* Ensure the SysTick is clocked at the same frequency as the core. */
@@ -76,340 +224,169 @@
#define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
#endif
-/* Let the user override the pre-loading of the initial LR with the address of
- * prvTaskExitError() in case it messes up unwinding of the stack in the
- * debugger. */
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
#define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
*/
-void vPortSetupTimerInterrupt( void );
+#define portPRELOAD_REGISTERS 1
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
+/*-----------------------------------------------------------*/
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
*/
static void prvTaskExitError( void );
-/*-----------------------------------------------------------*/
+#if ( configENABLE_MPU == 1 )
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
+#endif /* configENABLE_MPU */
-/*
- * The number of SysTick increments that make up one tick period.
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
*/
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
*/
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+BaseType_t xPortIsInsideInterrupt( void );
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
+/**
+ * @brief Yield the processor.
*/
-#if ( configUSE_TICKLESS_IDLE == 1 )
- static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
+/**
+ * @brief Enter critical section.
*/
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 8; /* R11..R4. */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-static void prvTaskExitError( void )
-{
- volatile uint32_t ulDummy = 0UL;
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
- /* A function that implements a task must not exit or attempt to return to
- * its caller as there is nothing to return to. If a task wants to exit it
- * should instead call vTaskDelete( NULL ).
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the system call stack so that upon returning from
+ * SVC, the system call stack is used.
*
- * Artificially force an assert() to be triggered if configASSERT() is
- * defined, then stop here so application writers can catch the error. */
- configASSERT( uxCriticalNesting == ~0UL );
- portDISABLE_INTERRUPTS();
+ * @param pulTaskStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ * @param ucSystemCallNumber The system call number of the system call.
+ */
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
- while( ulDummy == 0 )
- {
- /* This file calls prvTaskExitError() after the scheduler has been
- * started to remove a compiler warning about the function being defined
- * but never called. ulDummy is used purely to quieten other warnings
- * about code appearing after this function is called - making ulDummy
- * volatile makes the compiler think the function could return and
- * therefore not output an 'unreachable code' warning for code that appears
- * after it. */
- }
-}
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Raise SVC for exiting from a system call.
+ */
+ void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ /**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) PRIVILEGED_FUNCTION;
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
+
+#endif /* configENABLE_MPU == 1 */
+
/*-----------------------------------------------------------*/
-void vPortSVCHandler( void )
-{
- /* This function is no longer used, but retained for backward
- * compatibility. */
-}
-/*-----------------------------------------------------------*/
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
-void vPortStartFirstTask( void )
-{
- /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
- * table offset register that can be used to locate the initial stack value.
- * Not all M0 parts have the application vector table at address 0. */
- __asm volatile (
- " .syntax unified \n"
- " ldr r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */
- " ldr r3, [r2] \n"
- " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " adds r0, #32 \n"/* Discard everything up to r0. */
- " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
- " movs r0, #2 \n"/* Switch to the psp stack. */
- " msr CONTROL, r0 \n"
- " isb \n"
- " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */
- " mov lr, r5 \n"/* lr is now in r5. */
- " pop {r3} \n"/* Return address is now in r3. */
- " pop {r2} \n"/* Pop and discard XPSR. */
- " cpsie i \n"/* The first task has its context and interrupts can be enabled. */
- " bx r3 \n"/* Finally, jump to the user defined task code. */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB "
- );
-}
-/*-----------------------------------------------------------*/
+ /**
+ * @brief This variable is set to pdTRUE when the scheduler is started.
+ */
+ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-/*
- * See header file for description.
+#endif
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
*/
-BaseType_t xPortStartScheduler( void )
-{
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
+#if ( configUSE_TICKLESS_IDLE == 1 )
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
+ /**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+ PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
- /* Start the first task. */
- vPortStartFirstTask();
+ /**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+ PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
- /* Should never get here as the tasks will now be executing! Call the task
- * exit error function to prevent compiler warnings about a static function
- * not being called in the case that the application writer overrides this
- * functionality by defining configTASK_RETURN_ADDRESS. Call
- * vTaskSwitchContext() so link time optimisation does not remove the
- * symbol. */
- vTaskSwitchContext();
- prvTaskExitError();
+ /**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+ PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
+#endif /* configUSE_TICKLESS_IDLE */
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortYield( void )
-{
- /* Set a PendSV to request a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
- /* Barriers are normally not required but do ensure the code is completely
- * within the specified behaviour for the architecture. */
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void )
-{
- __asm volatile (
- " mrs r0, PRIMASK \n"
- " cpsid i \n"
- " bx lr "
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
-{
- __asm volatile (
- " msr PRIMASK, r0 \n"
- " bx lr "
- ::: "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " .syntax unified \n"
- " mrs r0, psp \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */
- " str r0, [r2] \n"/* Save the new top of stack. */
- " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */
- " mov r4, r8 \n"/* Store the high registers. */
- " mov r5, r9 \n"
- " mov r6, r10 \n"
- " mov r7, r11 \n"
- " stmia r0!, {r4-r7} \n"
- " \n"
- " push {r3, r14} \n"
- " cpsid i \n"
- " bl vTaskSwitchContext \n"
- " cpsie i \n"
- " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */
- " \n"
- " ldr r1, [r2] \n"
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " adds r0, r0, #16 \n"/* Move to the high registers. */
- " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */
- " mov r8, r4 \n"
- " mov r9, r5 \n"
- " mov r10, r6 \n"
- " mov r11, r7 \n"
- " \n"
- " msr psp, r0 \n"/* Remember the new top of stack for the task. */
- " \n"
- " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */
- " ldmia r0!, {r4-r7} \n"/* Pop low registers. */
- " \n"
- " bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB "
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- uint32_t ulPreviousMask;
-
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Calculate the constants required to configure the tick interrupt. */
- #if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
- #endif /* configUSE_TICKLESS_IDLE */
-
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -631,3 +608,1058 @@
}
#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if ( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+ {
+ uint32_t ulRegionSize, ulReturnValue = 7UL;
+
+ /* 256 is the smallest region size, 31 is the largest valid value for
+ * ulReturnValue. */
+ for( ulRegionSize = 256UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+ {
+ if( ulActualSizeInBytes <= ulRegionSize )
+ {
+ break;
+ }
+ else
+ {
+ ulReturnValue++;
+ }
+ }
+
+ /* Shift the code by one before returning so it can be written directly
+ * into the the correct bit position of the attribute register. */
+ return( ulReturnValue << 1UL );
+ }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __FLASH_segment_start__;
+ extern uint32_t * __FLASH_segment_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+
+ #else /* if defined( __ARMCC_VERSION ) */
+
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __FLASH_segment_start__[];
+ extern uint32_t __FLASH_segment_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Ensure that the MPU is present. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+ ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+ ( portPRIVILEGED_FLASH_REGION ) );
+
+ portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RO_UNPRIV_NA ) |
+ ( ( configS_C_B_FLASH & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+ ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+ ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+ ( portUNPRIVILEGED_FLASH_REGION ) );
+
+ portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RO_UNPRIV_RO ) |
+ ( ( configS_C_B_FLASH & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+ ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RBAR_REG = ( ( uint32_t ) __privileged_sram_start__ ) | /* Base address. */
+ ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+ ( portPRIVILEGED_RAM_REGION );
+
+ portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RW_UNPRIV_NA ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+ prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_sram_end__ - ( uint32_t ) __privileged_sram_start__ ) |
+ ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_CTRL_PRIV_BACKGROUND_ENABLE_BITMASK |
+ portMPU_CTRL_ENABLE_BITMASK );
+ }
+ }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile ( "dsb" ::: "memory" );
+ __asm volatile ( "isb" );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+ uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+
+ traceISR_ENTER();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ traceISR_EXIT_TO_SCHEDULER();
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ else
+ {
+ traceISR_EXIT();
+ }
+ }
+
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+
+ #else
+
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ uint32_t ulPC;
+ uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ];
+ ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ case portSVC_START_SCHEDULER:
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ break;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+
+ case portSVC_RAISE_PRIVILEGE:
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+
+ #endif /* configENABLE_MPU == 1 */
+
+ default:
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallEnter( uint32_t * pulTaskStack,
+ uint32_t ulLR,
+ uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulSystemCallStack;
+ uint32_t ulSystemCallLocation, i;
+ const uint32_t ulStackFrameSize = 8;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+
+ #else
+
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the system call section (i.e. application is
+ * not raising SVC directly).
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
+ * it is non-NULL only during the execution of a system call (i.e.
+ * between system call enter and exit).
+ * 3. System call is not for a kernel API disabled by the configuration
+ * in FreeRTOSConfig.h.
+ * 4. We do not need to check that ucSystemCallNumber is within range
+ * because the assembly SVC handler checks that before calling
+ * this function.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
+ ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
+ {
+ pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
+
+ /* Make space on the system call stack for the stack frame. */
+ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulStackFrameSize; i++ )
+ {
+ pulSystemCallStack[ i ] = pulTaskStack[ i ];
+ }
+
+ /* Store the value of the Link Register before the SVC was raised.
+ * It contains the address of the caller of the System Call entry
+ * point (i.e. the caller of the MPU_<API>). We need to restore it
+ * when we exit from the system call. */
+ pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
+
+ /* Use the pulSystemCallStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
+
+ /* Start executing the system call upon returning from this handler. */
+ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
+
+ /* Raise a request to exit from the system call upon finishing the
+ * system call. */
+ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
+
+ /* Remember the location where we should copy the stack frame when we exit from
+ * the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
+
+ /* Record if the hardware used padding to force the stack pointer
+ * to be double word aligned. */
+ if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
+ {
+ pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
+ }
+ else
+ {
+ pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
+ }
+
+ /* We ensure in pxPortInitialiseStack that the system call stack is
+ * double word aligned and therefore, there is no need of padding.
+ * Clear the bit[9] of stacked xPSR. */
+ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+
+ /* Raise the privilege for the duration of the system call. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void vSystemCallExit( uint32_t * pulSystemCallStack,
+ uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
+ {
+ extern TaskHandle_t pxCurrentTCB;
+ xMPU_SETTINGS * pxMpuSettings;
+ uint32_t * pulTaskStack;
+ uint32_t ulSystemCallLocation, i;
+ const uint32_t ulStackFrameSize = 8;
+
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+
+ #else
+
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+
+ #endif /* #if defined( __ARMCC_VERSION ) */
+
+ ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
+ pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
+
+ /* Checks:
+ * 1. SVC is raised from the privileged code (i.e. application is not
+ * raising SVC directly). This SVC is only raised from
+ * vRequestSystemCallExit which is in the privileged code section.
+ * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
+ * this means that we previously entered a system call and the
+ * application is not attempting to exit without entering a system
+ * call.
+ */
+ if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
+ ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
+ ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
+ {
+ pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
+
+ /* Make space on the task stack for the stack frame. */
+ pulTaskStack = pulTaskStack - ulStackFrameSize;
+
+ /* Copy the stack frame. */
+ for( i = 0; i < ulStackFrameSize; i++ )
+ {
+ pulTaskStack[ i ] = pulSystemCallStack[ i ];
+ }
+
+ /* Use the pulTaskStack in thread mode. */
+ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
+
+ /* Return to the caller of the System Call entry point (i.e. the
+ * caller of the MPU_<API>). */
+ pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+ /* Ensure that LR has a valid value.*/
+ pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
+
+ /* If the hardware used padding to force the stack pointer
+ * to be double word aligned, set the stacked xPSR bit[9],
+ * otherwise clear it. */
+ if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
+ }
+ else
+ {
+ pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
+ }
+
+ /* This is not NULL only for the duration of the system call. */
+ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+
+ /* Drop the privilege before returning to the thread mode. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " mrs r0, control \n" /* Obtain current control value. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* Set nPRIV bit. */
+ " msr control, r0 \n" /* Write back new control value. */
+ ::: "r0", "r1", "memory"
+ );
+ }
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
+ {
+ BaseType_t xTaskIsPrivileged = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xTaskIsPrivileged = pdTRUE;
+ }
+
+ return xTaskIsPrivileged;
+ }
+
+#endif /* configENABLE_MPU == 1 */
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters,
+ BaseType_t xRunPrivileged,
+ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
+ {
+ xMPUSettings->ulContext[ 0 ] = 0x04040404; /* r4. */
+ xMPUSettings->ulContext[ 1 ] = 0x05050505; /* r5. */
+ xMPUSettings->ulContext[ 2 ] = 0x06060606; /* r6. */
+ xMPUSettings->ulContext[ 3 ] = 0x07070707; /* r7. */
+ xMPUSettings->ulContext[ 4 ] = 0x08080808; /* r8. */
+ xMPUSettings->ulContext[ 5 ] = 0x09090909; /* r9. */
+ xMPUSettings->ulContext[ 6 ] = 0x10101010; /* r10. */
+ xMPUSettings->ulContext[ 7 ] = 0x11111111; /* r11. */
+
+ xMPUSettings->ulContext[ 8 ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ 9 ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ 10 ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ 11 ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ 12 ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ 13 ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ xMPUSettings->ulContext[ 14 ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ 15 ] = portINITIAL_XPSR; /* xPSR. */
+
+ xMPUSettings->ulContext[ 16 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ if( xRunPrivileged == pdTRUE )
+ {
+ xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
+ xMPUSettings->ulContext[ 17 ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ }
+ else
+ {
+ xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulContext[ 17 ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ }
+ xMPUSettings->ulContext[ 18 ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ {
+ /* Ensure that the system call stack is double word aligned. */
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
+ xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
+ ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
+
+ /* This is not NULL only for the duration of a system call. */
+ xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
+ }
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ return &( xMPUSettings->ulContext[ 19 ] );
+ }
+
+#else /* configENABLE_MPU */
+
+ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters ) /* PRIVILEGED_FUNCTION */
+ {
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+ }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+ {
+ xSchedulerRunning = pdTRUE;
+ }
+ #endif
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+ const struct xMEMORY_REGION * const xRegions,
+ StackType_t * pxBottomOfStack,
+ configSTACK_DEPTH_TYPE uxStackDepth )
+ {
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __SRAM_segment_start__;
+ extern uint32_t * __SRAM_segment_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __SRAM_segment_start__[];
+ extern uint32_t __SRAM_segment_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ int32_t lIndex;
+ uint32_t ul;
+
+ if( xRegions == NULL )
+ {
+ /* No MPU regions are specified so allow access to all RAM. */
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =
+ ( ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+ ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+ ( portSTACK_REGION ) ); /* Region number. */
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRASR =
+ ( ( portMPU_REGION_PRIV_RW_UNPRIV_RW ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+ ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+ ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+
+
+ /* Invalidate user configurable regions. */
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ xMPUSettings->xRegionsSettings[ ul ].ulRBAR = ( ( ul - 1UL ) | portMPU_RBAR_REGION_NUMBER_VALID_BITMASK );
+ xMPUSettings->xRegionsSettings[ ul ].ulRASR = 0UL;
+ }
+ }
+ else
+ {
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that the
+ * stack region has already been configured. */
+ if( uxStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =
+ ( ( ( uint32_t ) pxBottomOfStack ) |
+ ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+ ( portSTACK_REGION ) ); /* Region number. */
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRASR =
+ ( ( portMPU_REGION_PRIV_RW_UNPRIV_RW ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
+ ( prvGetMPURegionSizeSetting( uxStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+ ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) |
+ ( portMPU_RASR_REGION_ENABLE_BITMASK ) );
+ }
+
+ lIndex = 0;
+
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ {
+ if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+ {
+ /* Translate the generic region definition contained in
+ * xRegions into the CM0+ specific MPU settings that are then
+ * stored in xMPUSettings. */
+ xMPUSettings->xRegionsSettings[ ul ].ulRBAR =
+ ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+ ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) |
+ ( ul - 1UL ); /* Region number. */
+
+ xMPUSettings->xRegionsSettings[ ul ].ulRASR =
+ ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+ ( xRegions[ lIndex ].ulParameters ) |
+ ( portMPU_RASR_REGION_ENABLE_BITMASK );
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ul ].ulRBAR = ( ( ul - 1UL ) | portMPU_RBAR_REGION_NUMBER_VALID_BITMASK );
+ xMPUSettings->xRegionsSettings[ ul ].ulRASR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+}
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+
+ {
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ uint32_t ulRegionStart, ulRegionSize, ulRegionEnd;
+ uint32_t ulMPURegionAccessPermissions;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ {
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS; i++ )
+ {
+ /* Is the MPU region enabled? */
+ if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRASR &
+ portMPU_RASR_REGION_ENABLE_BITMASK ) == portMPU_RASR_REGION_ENABLE_BITMASK )
+ {
+ ulRegionStart = portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR );
+ ulRegionSize = portEXTRACT_REGION_SIZE_FROM_RASR( xTaskMpuSettings->xRegionsSettings[ i ].ulRASR );
+ ulRegionEnd = ulRegionStart + ulRegionSize;
+
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ ulRegionStart,
+ ulRegionEnd ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ ulRegionStart,
+ ulRegionEnd ) )
+ {
+ ulMPURegionAccessPermissions = xTaskMpuSettings->xRegionsSettings[ i ].ulRASR &
+ portMPU_RASR_AP_BITMASK;
+
+ if( ulAccessRequested == tskMPU_READ_PERMISSION ) /* RO. */
+ {
+ if( ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RO ) ||
+ ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RO_UNPRIV_RO ) ||
+ ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RW ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
+ }
+ else if( ( ulAccessRequested & tskMPU_WRITE_PERMISSION ) != 0UL ) /* W or RW. */
+ {
+ if( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RW )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. Interrupt Program
+ * Status Register (IPSR) holds the exception number of the currently-executing
+ * exception or zero for Thread mode.*/
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+
+ void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
+ int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ xMPU_SETTINGS * xTaskMpuSettings;
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
+
+ xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
+ }
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
+ ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
+
+ if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ }
+ }
+
+ return xAccessGranted;
+ }
+
+ #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+ BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
+ {
+ ( void ) lInternalIndexOfKernelObject;
+
+ /* If Access Control List feature is not used, all the tasks have
+ * access to all the kernel objects. */
+ return pdTRUE;
+ }
+
+ #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
+
+#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
+
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM0/portasm.c b/Source/portable/GCC/ARM_CM0/portasm.c
new file mode 100644
index 0000000..2280ec8
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM0/portasm.c
@@ -0,0 +1,526 @@
+/*
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_MPU == 1 )
+
+ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .extern pxCurrentTCB \n"
+ " .syntax unified \n"
+ " \n"
+ " program_mpu_first_task: \n"
+ " \n"
+ " ldr r3, =pxCurrentTCB \n" /* r3 = &pxCurrentTCB. */
+ " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
+ " adds r0, #4 \n" /* r0 = Second item in the TCB which is xMPUSettings. */
+ " \n"
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " movs r3, #1 \n" /* r3 = 1. */
+ " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+ " str r2, [r1] \n" /* Disable MPU. */
+ " \n"
+ " ldr r1, =0xe000ed9c \n" /* r1 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000eda0 \n" /* r2 = 0xe000eda0 [Location of RASR]. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read first set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read second set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read third set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read fourth set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read fifth set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " movs r3, #1 \n" /* r3 = 1. */
+ " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+ " str r2, [r1] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ " \n"
+ " restore_context_first_task: \n"
+ " ldr r2, =pxCurrentTCB \n" /* r2 = &pxCurrentTCB. */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
+ " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
+ " \n"
+ " restore_special_regs_first_task: \n"
+ " subs r1, #12 \n"
+ " ldmia r1!, {r2-r4} \n" /* r2 = original PSP, r3 = CONTROL, r4 = LR. */
+ " subs r1, #12 \n"
+ " msr psp, r2 \n"
+ " msr control, r3 \n"
+ " mov lr, r4 \n"
+ " \n"
+ " restore_general_regs_first_task: \n"
+ " subs r1, #32 \n"
+ " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
+ " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
+ " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
+ " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
+ " subs r1, #48 \n"
+ " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
+ " mov r8, r4 \n" /* r8 = r4. */
+ " mov r9, r5 \n" /* r9 = r5. */
+ " mov r10, r6 \n" /* r10 = r6. */
+ " mov r11, r7 \n" /* r11 = r7. */
+ " subs r1, #32 \n"
+ " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
+ " subs r1, #16 \n"
+ " \n"
+ " restore_context_done_first_task: \n"
+ " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+ }
+
+#else /* configENABLE_MPU */
+
+ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .extern pxCurrentTCB \n"
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* r2 = &pxCurrentTCB. */
+ " ldr r1, [r2] \n" /* r1 = pxCurrentTCB.*/
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ " ldm r0!, {r2} \n" /* Read from stack - r2 = EXC_RETURN. */
+ " movs r1, #2 \n" /* r1 = 2. */
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */
+ " \n"
+ " .align 4 \n"
+ );
+ }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+ " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
+ " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " bx lr \n" /* Return. */
+ " running_privileged: \n"
+ " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "r1", "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* Read the CONTROL register. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear the bit 0. */
+ " msr control, r0 \n" /* Write back the new CONTROL value. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* r0 = r0 | r1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ /* Don't reset the MSP stack as is done on CM3/4 devices. The reason is that
+ * the Vector Table Offset Register (VTOR) is optional in CM0+ architecture
+ * and therefore, may not be available on all the devices. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " cpsie i \n" /* Globally enable interrupts. */
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n" /* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " msr PRIMASK, r0 \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .extern pxCurrentTCB \n"
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
+ " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
+ " mrs r2, psp \n" /* r2 = PSP. */
+ " \n"
+ " save_general_regs: \n"
+ " stmia r1!, {r4-r7} \n" /* Store r4-r7. */
+ " mov r4, r8 \n" /* r4 = r8. */
+ " mov r5, r9 \n" /* r5 = r9. */
+ " mov r6, r10 \n" /* r6 = r10. */
+ " mov r7, r11 \n" /* r7 = r11. */
+ " stmia r1!, {r4-r7} \n" /* Store r8-r11. */
+ " ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */
+ " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
+ " ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */
+ " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
+ " \n"
+ " save_special_regs: \n"
+ " mrs r2, psp \n" /* r2 = PSP. */
+ " mrs r3, control \n" /* r3 = CONTROL. */
+ " mov r4, lr \n" /* r4 = LR. */
+ " stmia r1!, {r2-r4} \n" /* Store original PSP (after hardware has saved context), CONTROL and LR. */
+ " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
+ " \n"
+ " select_next_task: \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " program_mpu: \n"
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
+ " adds r0, #4 \n" /* r0 = Second item in the TCB which is xMPUSettings. */
+ " \n"
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " movs r3, #1 \n" /* r3 = 1. */
+ " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+ " str r2, [r1] \n" /* Disable MPU */
+ " \n"
+ " ldr r1, =0xe000ed9c \n" /* r1 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000eda0 \n" /* r2 = 0xe000eda0 [Location of RASR]. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read first set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read second set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read third set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read fourth set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldmia r0!, {r3-r4} \n" /* Read fifth set of RBAR/RASR registers from TCB. */
+ " str r3, [r1] \n" /* Program RBAR. */
+ " str r4, [r2] \n" /* Program RASR. */
+ " \n"
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
+ " movs r3, #1 \n" /* r3 = 1. */
+ " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+ " str r2, [r1] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ " \n"
+ " restore_context: \n"
+ " ldr r2, =pxCurrentTCB \n" /* r2 = &pxCurrentTCB. */
+ " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
+ " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
+ " \n"
+ " restore_special_regs: \n"
+ " subs r1, #12 \n"
+ " ldmia r1!, {r2-r4} \n" /* r2 = original PSP, r3 = CONTROL, r4 = LR. */
+ " subs r1, #12 \n"
+ " msr psp, r2 \n"
+ " msr control, r3 \n"
+ " mov lr, r4 \n"
+ " \n"
+ " restore_general_regs: \n"
+ " subs r1, #32 \n"
+ " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
+ " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
+ " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
+ " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
+ " subs r1, #48 \n"
+ " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
+ " mov r8, r4 \n" /* r8 = r4. */
+ " mov r9, r5 \n" /* r9 = r5. */
+ " mov r10, r6 \n" /* r10 = r6. */
+ " mov r11, r7 \n" /* r11 = r7. */
+ " subs r1, #32 \n"
+ " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
+ " subs r1, #16 \n"
+ " \n"
+ " restore_context_done: \n"
+ " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ );
+ }
+
+#else /* configENABLE_MPU */
+
+ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .extern pxCurrentTCB \n"
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n" /* Read PSP in r0. */
+ " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* r1 = pxCurrentTCB. */
+ " subs r0, r0, #36 \n" /* Make space for LR and the remaining registers on the stack. */
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */
+ " \n"
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmia r0!, {r3-r7} \n" /* Store on the stack - LR and low registers that are not automatically saved. */
+ " mov r4, r8 \n" /* r4 = r8. */
+ " mov r5, r9 \n" /* r5 = r9. */
+ " mov r6, r10 \n" /* r6 = r10. */
+ " mov r7, r11 \n" /* r7 = r11. */
+ " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
+ " \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* r1 = pxCurrentTCB. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
+ " adds r0, r0, #20 \n" /* Move to the high registers. */
+ " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
+ " mov r8, r4 \n" /* r8 = r4. */
+ " mov r9, r5 \n" /* r9 = r5. */
+ " mov r10, r6 \n" /* r10 = r6. */
+ " mov r11, r7 \n" /* r11 = r7. */
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */
+ " subs r0, r0, #36 \n" /* Move to the starting of the saved context. */
+ " ldmia r0!, {r3-r7} \n" /* Read from stack - r3 = LR and r4-r7 restored. */
+ " bx r3 \n"
+ " \n"
+ " .align 4 \n"
+ );
+ }
+
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+ void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern vPortSVCHandler_C \n"
+ " .extern vSystemCallEnter \n"
+ " .extern vSystemCallExit \n"
+ " .extern pxCurrentTCB \n"
+ " \n"
+ " movs r0, #4 \n"
+ " mov r1, lr \n"
+ " tst r0, r1 \n"
+ " beq stack_on_msp \n"
+ " \n"
+ " stack_on_psp: \n"
+ " mrs r0, psp \n"
+ " b route_svc \n"
+ " \n"
+ " stack_on_msp: \n"
+ " mrs r0, msp \n"
+ " b route_svc \n"
+ " \n"
+ " route_svc: \n"
+ " ldr r3, [r0, #24] \n"
+ " subs r3, #2 \n"
+ " ldrb r2, [r3, #0] \n"
+ " ldr r3, =%0 \n"
+ " cmp r2, r3 \n"
+ " blt system_call_enter \n"
+ " ldr r3, =%1 \n"
+ " cmp r2, r3 \n"
+ " beq system_call_exit \n"
+ " ldr r3, =vPortSVCHandler_C \n"
+ " bx r3 \n"
+ " \n"
+ " system_call_enter: \n"
+ " push {lr} \n"
+ " bl vSystemCallEnter \n"
+ " pop {pc} \n"
+ " \n"
+ " system_call_exit: \n"
+ " push {lr} \n"
+ " bl vSystemCallExit \n"
+ " pop {pc} \n"
+ " \n"
+ " .align 4 \n"
+ " \n"
+ : /* No outputs. */
+ : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+ : "r0", "r1", "r2", "r3", "memory"
+ );
+ }
+
+#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+ void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern vPortSVCHandler_C \n"
+ " \n"
+ " movs r0, #4 \n"
+ " mov r1, lr \n"
+ " tst r0, r1 \n"
+ " beq stacking_used_msp \n"
+ " \n"
+ " stacking_used_psp: \n"
+ " mrs r0, psp \n"
+ " ldr r3, =vPortSVCHandler_C \n"
+ " bx r3 \n"
+ " \n"
+ " stacking_used_msp: \n"
+ " mrs r0, msp \n"
+ " ldr r3, =vPortSVCHandler_C \n"
+ " bx r3 \n"
+ " \n"
+ " .align 4 \n"
+ );
+ }
+
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM0/portasm.h b/Source/portable/GCC/ARM_CM0/portasm.h
new file mode 100644
index 0000000..ce0f3aa
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM0/portasm.h
@@ -0,0 +1,99 @@
+/*
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kernel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/GCC/ARM_CM0/portmacro.h b/Source/portable/GCC/ARM_CM0/portmacro.h
index 46f308d..97e8450 100644
--- a/Source/portable/GCC/ARM_CM0/portmacro.h
+++ b/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -26,7 +26,6 @@
*
*/
-
#ifndef PORTMACRO_H
#define PORTMACRO_H
@@ -36,17 +35,25 @@
#endif
/* *INDENT-ON* */
-/*-----------------------------------------------------------
+/*------------------------------------------------------------------------------
* Port specific definitions.
*
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
*
* These settings should not be altered.
- *-----------------------------------------------------------
+ *------------------------------------------------------------------------------
*/
-/* Type definitions. */
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
@@ -60,99 +67,317 @@
typedef unsigned long UBaseType_t;
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#else
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
#endif
/*-----------------------------------------------------------*/
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portDONT_DISCARD __attribute__( ( used ) )
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M0+"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
+/**
+ * @brief Extern declarations.
+ */
+extern BaseType_t xPortIsInsideInterrupt( void );
-/* Scheduler utilities. */
-extern void vPortYield( void );
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+/* Shareable (S), Cacheable (C) and Bufferable (B) bits for flash region. */
+#ifndef configS_C_B_FLASH
+ #define configS_C_B_FLASH ( 0x07UL )
+#endif
+
+/* Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM region. */
+#ifndef configS_C_B_SRAM
+ #define configS_C_B_SRAM ( 0x07UL )
+#endif
+
+/* MPU regions. */
+#define portPRIVILEGED_RAM_REGION ( 7UL )
+#define portPRIVILEGED_FLASH_REGION ( 6UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 5UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 0UL )
+#define portLAST_CONFIGURABLE_REGION ( 3UL )
+#define portNUM_CONFIGURABLE_REGIONS ( 4UL )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1UL ) /* Plus one to make space for the stack region. */
+
+/* MPU region sizes. This information is encoded in the SIZE bits of the MPU
+ * Region Attribute and Size Register (RASR). */
+#define portMPU_REGION_SIZE_256B ( 0x07UL << 1UL )
+#define portMPU_REGION_SIZE_512B ( 0x08UL << 1UL )
+#define portMPU_REGION_SIZE_1KB ( 0x09UL << 1UL )
+#define portMPU_REGION_SIZE_2KB ( 0x0AUL << 1UL )
+#define portMPU_REGION_SIZE_4KB ( 0x0BUL << 1UL )
+#define portMPU_REGION_SIZE_8KB ( 0x0CUL << 1UL )
+#define portMPU_REGION_SIZE_16KB ( 0x0DUL << 1UL )
+#define portMPU_REGION_SIZE_32KB ( 0x0EUL << 1UL )
+#define portMPU_REGION_SIZE_64KB ( 0x0FUL << 1UL )
+#define portMPU_REGION_SIZE_128KB ( 0x10UL << 1UL )
+#define portMPU_REGION_SIZE_256KB ( 0x11UL << 1UL )
+#define portMPU_REGION_SIZE_512KB ( 0x12UL << 1UL )
+#define portMPU_REGION_SIZE_1MB ( 0x13UL << 1UL )
+#define portMPU_REGION_SIZE_2MB ( 0x14UL << 1UL )
+#define portMPU_REGION_SIZE_4MB ( 0x15UL << 1UL )
+#define portMPU_REGION_SIZE_8MB ( 0x16UL << 1UL )
+#define portMPU_REGION_SIZE_16MB ( 0x17UL << 1UL )
+#define portMPU_REGION_SIZE_32MB ( 0x18UL << 1UL )
+#define portMPU_REGION_SIZE_64MB ( 0x19UL << 1UL )
+#define portMPU_REGION_SIZE_128MB ( 0x1AUL << 1UL )
+#define portMPU_REGION_SIZE_256MB ( 0x1BUL << 1UL )
+#define portMPU_REGION_SIZE_512MB ( 0x1CUL << 1UL )
+#define portMPU_REGION_SIZE_1GB ( 0x1DUL << 1UL )
+#define portMPU_REGION_SIZE_2GB ( 0x1EUL << 1UL )
+#define portMPU_REGION_SIZE_4GB ( 0x1FUL << 1UL )
+
+/* MPU memory types. This information is encoded in the S ( Shareable), C
+ * (Cacheable) and B (Bufferable) bits of the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x0UL << 16UL ) /* S=NA, C=0, B=0. */
+#define portMPU_REGION_DEVICE_SHAREABLE ( 0x1UL << 16UL ) /* S=NA, C=0, B=1. */
+#define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x2UL << 16UL ) /* S=0, C=1, B=0. */
+#define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x6UL << 16UL ) /* S=1, C=1, B=0. */
+#define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x3UL << 16UL ) /* S=0, C=1, B=1.*/
+#define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x7UL << 16UL ) /* S=1, C=1, B=1.*/
+
+/* MPU access permissions. This information is encoded in the AP and XN bits of
+ * the MPU Region Attribute and Size Register (RASR). */
+#define portMPU_REGION_PRIV_NA_UNPRIV_NA ( 0x0UL << 24UL )
+#define portMPU_REGION_PRIV_RW_UNPRIV_NA ( 0x1UL << 24UL )
+#define portMPU_REGION_PRIV_RW_UNPRIV_RO ( 0x2UL << 24UL )
+#define portMPU_REGION_PRIV_RW_UNPRIV_RW ( 0x3UL << 24UL )
+#define portMPU_REGION_PRIV_RO_UNPRIV_NA ( 0x5UL << 24UL )
+#define portMPU_REGION_PRIV_RO_UNPRIV_RO ( 0x6UL << 24UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 0x1UL << 28UL )
+
+#if ( configENABLE_MPU == 1 )
+
+ /**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< MPU Region Base Address Register (RBAR) for the region. */
+ uint32_t ulRASR; /**< MPU Region Attribute and Size Register (RASR) for the region. */
+ } MPURegionSettings_t;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+ #ifndef configSYSTEM_CALL_STACK_SIZE
+ #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #endif
+
+ /**
+ * @brief System call stack.
+ */
+ typedef struct SYSTEM_CALL_STACK_INFO
+ {
+ uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+ uint32_t * pulSystemCallStack;
+ uint32_t * pulTaskStack;
+ uint32_t ulLinkRegisterAtSystemCallEntry;
+ } xSYSTEM_CALL_STACK_INFO;
+
+ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+
+ /**
+ * @brief MPU settings as stored in the TCB.
+ */
+
+ /*
+ * +----------+-----------------+---------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, CONTROL | |
+ * | | PC, xPSR | EXC_RETURN | |
+ * +----------+-----------------+---------------+-----+
+ *
+ * <---------><----------------><---------------><---->
+ * 8 8 3 1
+ */
+ #define CONTEXT_SIZE 20
+
+ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+
+ /* Size of an Access Control List (ACL) entry in bits. */
+ #define portACL_ENTRY_SIZE_BITS ( 32U )
+
+ typedef struct MPU_SETTINGS
+ {
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ uint32_t ulContext[ CONTEXT_SIZE ];
+ uint32_t ulTaskFlags;
+
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+ xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+ #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+ uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+ #endif
+ #endif
+ } xMPU_SETTINGS;
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_START_SCHEDULER 100
+#define portSVC_RAISE_PRIVILEGE 101
+#define portSVC_SYSTEM_CALL_EXIT 102
+#define portSVC_YIELD 103
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portYIELD() vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) );
-
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
-/* Tickless idle/low power functionality. */
+/**
+ * @brief Tickless idle/low power functionality.
+ */
#ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
#endif
/*-----------------------------------------------------------*/
-/* Task function macros as described on the FreeRTOS.org WEB site. */
+/**
+ * @brief Task function macros as described on the FreeRTOS.org website.
+ */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#define portNOP()
-
-#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
-#endif
-
/*-----------------------------------------------------------*/
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
+#if ( configENABLE_MPU == 1 )
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
- return xReturn;
-}
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+
+ extern BaseType_t xPortIsTaskPrivileged( void );
+
+ /**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+
+#endif /* configENABLE_MPU == 1 */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
index b8164a0..a195dbf 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -63,12 +63,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -93,12 +92,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -123,12 +121,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -153,12 +150,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -183,12 +179,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -219,12 +214,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -249,12 +243,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -279,12 +272,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -309,12 +301,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -337,12 +328,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -363,12 +353,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -376,32 +365,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -417,12 +380,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -447,12 +409,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -477,12 +438,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -507,12 +467,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -539,12 +498,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -569,12 +527,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -603,12 +560,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -635,12 +591,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -669,12 +624,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -699,12 +653,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -729,12 +682,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -759,12 +711,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -789,12 +740,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -817,12 +767,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -845,12 +794,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -873,12 +821,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -903,12 +850,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -937,12 +883,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -969,12 +914,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -1003,12 +947,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1037,12 +980,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1063,12 +1005,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1089,12 +1030,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1119,12 +1059,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1149,12 +1088,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1177,12 +1115,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1205,12 +1142,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1237,12 +1173,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1267,12 +1202,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1299,12 +1233,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1331,12 +1264,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1363,12 +1295,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1393,12 +1324,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1423,12 +1353,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1453,12 +1382,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1485,12 +1413,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1515,12 +1442,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1545,12 +1471,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1562,31 +1487,27 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0, r1} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0, r1} \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1608,12 +1529,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1626,10 +1546,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1640,12 +1560,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1670,12 +1589,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1700,12 +1618,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1730,12 +1647,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1760,12 +1676,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1775,121 +1690,133 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1904,22 +1831,21 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1936,241 +1862,264 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/port.c b/Source/portable/GCC/ARM_CM23/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
index b23defe..bfc061e 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -56,11 +56,11 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -68,34 +68,34 @@
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
" movs r3, #5 \n" /* r3 = 5. */
" str r3, [r1] \n" /* Program RNR = 5. */
" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
" movs r3, #6 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 6. */
" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
" movs r3, #7 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 7. */
" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -103,7 +103,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
@@ -112,10 +112,9 @@
" ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
" subs r2, #20 \n"
" msr psp, r3 \n"
- " msr psplim, r4 \n"
" msr control, r5 \n"
" mov lr, r6 \n"
- " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" \n"
" restore_general_regs_first_task: \n"
@@ -137,14 +136,6 @@
" restore_context_done_first_task: \n"
" str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xSecureContextConst2: .word xSecureContext \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -156,24 +147,19 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r3, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
" ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
+ " ldr r4, =xSecureContext \n"
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
- " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
" movs r1, #2 \n" /* r1 = 2. */
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" bx r3 \n" /* Finally, branch to EXC_RETURN. */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
);
}
@@ -195,8 +181,6 @@
" running_privileged: \n"
" movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "r1", "memory"
);
}
@@ -240,7 +224,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -249,9 +233,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -294,9 +275,9 @@
" .extern SecureContext_SaveContext \n"
" .extern SecureContext_LoadContext \n"
" \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
" ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
" \n"
@@ -327,7 +308,7 @@
" \n"
" save_special_regs: \n"
" mrs r3, psp \n" /* r3 = PSP. */
- " mrs r4, psplim \n" /* r4 = PSPLIM. */
+ " movs r4, #0 \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */
" mrs r5, control \n" /* r5 = CONTROL. */
" mov r6, lr \n" /* r6 = LR. */
" stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -339,11 +320,11 @@
" cpsie i \n"
" \n"
" program_mpu: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -351,34 +332,34 @@
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
" movs r3, #5 \n" /* r3 = 5. */
" str r3, [r1] \n" /* Program RNR = 5. */
" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
" movs r3, #6 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 6. */
" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
" movs r3, #7 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 7. */
" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -386,7 +367,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
@@ -395,10 +376,9 @@
" ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
" subs r2, #20 \n"
" msr psp, r3 \n"
- " msr psplim, r4 \n"
" msr control, r5 \n"
" mov lr, r6 \n"
- " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" cbz r0, restore_ns_context \n" /* No secure context to restore. */
" \n"
@@ -432,14 +412,6 @@
" restore_context_done: \n"
" str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xSecureContextConst: .word xSecureContext \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
);
}
@@ -453,9 +425,9 @@
" .extern SecureContext_SaveContext \n"
" .extern SecureContext_LoadContext \n"
" \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
" mrs r2, psp \n" /* Read PSP in r2. */
" \n"
@@ -466,21 +438,21 @@
" mov lr, r3 \n" /* LR = r3. */
" lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
" bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
" subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
" str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
+ " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
" stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
" b select_next_task \n"
" \n"
" save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
" subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
" str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
+ " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
" stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
" mov r4, r8 \n" /* r4 = r8. */
@@ -494,17 +466,16 @@
" bl vTaskSwitchContext \n"
" cpsie i \n"
" \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
" ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
" \n"
" ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
" mov lr, r4 \n" /* LR = r4. */
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r3] \n" /* Restore the task's xSecureContext. */
" cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB. */
" push {r2, r4} \n"
" bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
@@ -526,10 +497,6 @@
" subs r2, r2, #32 \n" /* Go back to the low registers. */
" ldmia r2!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
);
}
@@ -592,15 +559,12 @@
" tst r0, r1 \n"
" beq stacking_used_msp \n"
" mrs r0, psp \n"
- " ldr r2, svchandler_address_const \n"
+ " ldr r2, =vPortSVCHandler_C \n"
" bx r2 \n"
" stacking_used_msp: \n"
" mrs r0, msp \n"
- " ldr r2, svchandler_address_const \n"
+ " ldr r2, =vPortSVCHandler_C \n"
" bx r2 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
index d8dab92..728e77d 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,9 +48,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portHAS_BASEPRI 0
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION 0
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
+
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
/*-----------------------------------------------------------*/
/**
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/Source/portable/GCC/ARM_CM23/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_context.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/Source/portable/GCC/ARM_CM23/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_context.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
index ce35340..d10c7f3 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/Source/portable/GCC/ARM_CM23/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_init.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/Source/portable/GCC/ARM_CM23/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_init.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
index b8164a0..a195dbf 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -63,12 +63,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -93,12 +92,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -123,12 +121,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -153,12 +150,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -183,12 +179,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -219,12 +214,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -249,12 +243,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -279,12 +272,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -309,12 +301,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -337,12 +328,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -363,12 +353,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -376,32 +365,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -417,12 +380,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -447,12 +409,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -477,12 +438,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -507,12 +467,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -539,12 +498,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -569,12 +527,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -603,12 +560,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -635,12 +591,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -669,12 +624,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -699,12 +653,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -729,12 +682,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -759,12 +711,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -789,12 +740,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -817,12 +767,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -845,12 +794,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -873,12 +821,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -903,12 +850,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -937,12 +883,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -969,12 +914,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -1003,12 +947,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1037,12 +980,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1063,12 +1005,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1089,12 +1030,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1119,12 +1059,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1149,12 +1088,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1177,12 +1115,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1205,12 +1142,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1237,12 +1173,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1267,12 +1202,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1299,12 +1233,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1331,12 +1264,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1363,12 +1295,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1393,12 +1324,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1423,12 +1353,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1453,12 +1382,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1485,12 +1413,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1515,12 +1442,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1545,12 +1471,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1562,31 +1487,27 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0, r1} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0, r1} \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1608,12 +1529,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1626,10 +1546,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1640,12 +1560,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1670,12 +1589,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1700,12 +1618,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1730,12 +1647,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1760,12 +1676,11 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1775,121 +1690,133 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1904,22 +1831,21 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1936,241 +1862,264 @@
" mrs r0, control \n"
" movs r1, #1 \n"
" tst r0, r1 \n"
+ " pop {r0, r1} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0, r1} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0, r1} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0, r1} \n"
- " mrs r0, control \n"
- " movs r1, #1 \n"
- " tst r0, r1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0, r1} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0, r1} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0, r1} \n"
+ " mrs r0, control \n"
+ " movs r1, #1 \n"
+ " tst r0, r1 \n"
+ " pop {r0, r1} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index b90da71..3bf4e27 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -56,11 +56,11 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -68,34 +68,34 @@
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
" movs r3, #5 \n" /* r3 = 5. */
" str r3, [r1] \n" /* Program RNR = 5. */
" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
" movs r3, #6 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 6. */
" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
" movs r3, #7 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 7. */
" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -103,7 +103,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
@@ -112,7 +112,9 @@
" ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
" subs r1, #16 \n"
" msr psp, r2 \n"
- " msr psplim, r3 \n"
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ " msr psplim, r3 \n"
+ #endif
" msr control, r4 \n"
" mov lr, r5 \n"
" \n"
@@ -135,13 +137,6 @@
" restore_context_done_first_task: \n"
" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -153,21 +148,20 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
- " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
+ #endif
" movs r1, #2 \n" /* r1 = 2. */
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" bx r2 \n" /* Finally, branch to EXC_RETURN. */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
@@ -189,8 +183,6 @@
" running_privileged: \n"
" movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "r1", "memory"
);
}
@@ -234,7 +226,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -243,9 +235,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -286,7 +275,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
" mrs r2, psp \n" /* r2 = PSP. */
@@ -305,7 +294,11 @@
" \n"
" save_special_regs: \n"
" mrs r2, psp \n" /* r2 = PSP. */
- " mrs r3, psplim \n" /* r3 = PSPLIM. */
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ " mrs r3, psplim \n" /* r3 = PSPLIM. */
+ #else
+ " movs r3, #0 \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */
+ #endif
" mrs r4, control \n" /* r4 = CONTROL. */
" mov r5, lr \n" /* r5 = LR. */
" stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -317,11 +310,11 @@
" cpsie i \n"
" \n"
" program_mpu: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
@@ -329,34 +322,34 @@
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
" movs r3, #5 \n" /* r3 = 5. */
" str r3, [r1] \n" /* Program RNR = 5. */
" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
" movs r3, #6 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 6. */
" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
" movs r3, #7 \n" /* r3 = 6. */
" str r3, [r1] \n" /* Program RNR = 7. */
" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" movs r3, #1 \n" /* r3 = 1. */
" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
@@ -364,7 +357,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
@@ -373,7 +366,9 @@
" ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
" subs r1, #16 \n"
" msr psp, r2 \n"
- " msr psplim, r3 \n"
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ " msr psplim, r3 \n"
+ #endif
" msr control, r4 \n"
" mov lr, r5 \n"
" \n"
@@ -396,13 +391,6 @@
" restore_context_done: \n"
" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
);
}
@@ -415,11 +403,15 @@
" .syntax unified \n"
" \n"
" mrs r0, psp \n" /* Read PSP in r0. */
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
" str r0, [r1] \n" /* Save the new top of stack in TCB. */
- " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ #else
+ " movs r2, #0 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */
+ #endif
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
" stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
" mov r4, r8 \n" /* r4 = r8. */
@@ -432,7 +424,7 @@
" bl vTaskSwitchContext \n"
" cpsie i \n"
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
" \n"
@@ -445,11 +437,10 @@
" msr psp, r0 \n" /* Remember the new top of stack for the task. */
" subs r0, r0, #40 \n" /* Move to the starting of the saved context. */
" ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ #endif
" bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
);
}
@@ -512,15 +503,12 @@
" tst r0, r1 \n"
" beq stacking_used_msp \n"
" mrs r0, psp \n"
- " ldr r2, svchandler_address_const \n"
+ " ldr r2, =vPortSVCHandler_C \n"
" bx r2 \n"
" stacking_used_msp: \n"
" mrs r0, msp \n"
- " ldr r2, svchandler_address_const \n"
+ " ldr r2, =vPortSVCHandler_C \n"
" bx r2 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index d8dab92..728e77d 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,9 +48,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portHAS_BASEPRI 0
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION 0
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
+
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
/*-----------------------------------------------------------*/
/**
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM3/port.c b/Source/portable/GCC/ARM_CM3/port.c
index cae2c53..fb32128 100644
--- a/Source/portable/GCC/ARM_CM3/port.c
+++ b/Source/portable/GCC/ARM_CM3/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -34,10 +34,14 @@
#include "FreeRTOS.h"
#include "task.h"
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
@@ -52,6 +56,11 @@
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -219,19 +228,18 @@
void vPortSVCHandler( void )
{
__asm volatile (
- " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
- " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
- " msr psp, r0 \n"/* Restore the task stack pointer. */
+ " ldr r3, =pxCurrentTCB \n" /* Restore the context. */
+ " ldr r1, [r3] \n" /* Get the pxCurrentTCB address. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+ " msr psp, r0 \n" /* Restore the task stack pointer. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"
" orr r14, #0xd \n"
" bx r14 \n"
" \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ " .ltorg \n"
);
}
/*-----------------------------------------------------------*/
@@ -239,15 +247,15 @@
static void prvPortStartFirstTask( void )
{
__asm volatile (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"
" ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " cpsie i \n"/* Globally enable interrupts. */
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
" cpsie f \n"
" dsb \n"
" isb \n"
- " svc 0 \n"/* System call to start first task. */
+ " svc 0 \n" /* System call to start first task. */
" nop \n"
" .ltorg \n"
);
@@ -259,6 +267,40 @@
*/
BaseType_t xPortStartScheduler( void )
{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -308,22 +350,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -343,9 +385,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the lowest priority interrupts. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
@@ -417,11 +461,11 @@
" mrs r0, psp \n"
" isb \n"
" \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
+ " ldr r3, =pxCurrentTCB \n" /* Get the location of the current TCB. */
" ldr r2, [r3] \n"
" \n"
- " stmdb r0!, {r4-r11} \n"/* Save the remaining registers. */
- " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
+ " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
" \n"
" stmdb sp!, {r3, r14} \n"
" mov r0, %0 \n"
@@ -430,16 +474,15 @@
" mov r0, #0 \n"
" msr basepri, r0 \n"
" ldmia sp!, {r3, r14} \n"
- " \n"/* Restore the context, including the critical nesting count. */
+ " \n" /* Restore the context, including the critical nesting count. */
" ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
- " ldmia r0!, {r4-r11} \n"/* Pop the registers. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */
" msr psp, r0 \n"
" isb \n"
" bx r14 \n"
" \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ " .ltorg \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -452,14 +495,21 @@
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portENABLE_INTERRUPTS();
}
@@ -749,7 +799,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -769,4 +819,4 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* configASSERT_DEFINED */
\ No newline at end of file
+#endif /* configASSERT_DEFINED */
diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h
index bdedf5a..1d0d009 100644
--- a/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -47,42 +47,42 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -93,156 +93,168 @@
__asm volatile ( "isb" ); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
- return ucReturn;
- }
+ return ucReturn;
+ }
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
/*-----------------------------------------------------------*/
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
}
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
+ return xReturn;
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI;
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
+ __asm volatile
+ (
+ " mov %0, %1 \n" \
+ " msr basepri, %0 \n" \
+ " isb \n" \
+ " dsb \n" \
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
/*-----------------------------------------------------------*/
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n" \
+ " mov %1, %2 \n" \
+ " msr basepri, %1 \n" \
+ " isb \n" \
+ " dsb \n" \
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+}
/*-----------------------------------------------------------*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+ __asm volatile
+ (
+ " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
index d247c92..9c3e8c7 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,31 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1557,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1575,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1588,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1617,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1646,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1675,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1704,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1719,117 +1634,130 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1843,22 +1771,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1874,233 +1801,256 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/port.c b/Source/portable/GCC/ARM_CM33/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
index 7431c98..bdee088 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -52,23 +54,23 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -86,23 +88,31 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
" restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
" msr psp, r3 \n"
" msr psplim, r4 \n"
" msr control, r5 \n"
- " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" \n"
" restore_general_regs_first_task: \n"
@@ -115,14 +125,6 @@
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xSecureContextConst2: .word xSecureContext \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -134,25 +136,32 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r3, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
+ " ldr r4, =xSecureContext \n"
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
- " movs r1, #2 \n" /* r1 = 2. */
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx r3 \n" /* Finally, branch to EXC_RETURN. */
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
);
}
@@ -171,8 +180,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -214,7 +221,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +231,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -240,7 +244,7 @@
" \n"
" mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bx lr \n" /* Return. */
@@ -274,9 +278,9 @@
" .extern SecureContext_SaveContext \n"
" .extern SecureContext_LoadContext \n"
" \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
" ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
" \n"
@@ -293,7 +297,6 @@
" \n"
" save_general_regs: \n"
" mrs r3, psp \n"
- " \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
" add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */
" tst lr, #0x10 \n"
@@ -303,7 +306,6 @@
" vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */
" sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
" stmia r2!, {r4-r11} \n" /* Store r4-r11. */
" ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
" stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */
@@ -313,11 +315,19 @@
" mrs r4, psplim \n" /* r4 = PSPLIM. */
" mrs r5, control \n" /* r5 = CONTROL. */
" stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
- " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_1 \n"
+ " mrs r5, PAC_KEY_P_2 \n"
+ " mrs r6, PAC_KEY_P_3 \n"
+ " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
" \n"
" select_next_task: \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
@@ -325,23 +335,23 @@
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
" program_mpu: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -359,23 +369,31 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
" restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
" msr psp, r3 \n"
" msr psplim, r4 \n"
" msr control, r5 \n"
- " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" cbz r0, restore_ns_context \n" /* No secure context to restore. */
" \n"
@@ -404,14 +422,6 @@
" restore_context_done: \n"
" str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xSecureContextConst: .word xSecureContext \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -422,93 +432,99 @@
{
__asm volatile
(
- " .syntax unified \n"
- " .extern SecureContext_SaveContext \n"
- " .extern SecureContext_LoadContext \n"
- " \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
- " mrs r2, psp \n" /* Read PSP in r2. */
- " \n"
- " cbz r0, save_ns_context \n" /* No secure context to save. */
- " push {r0-r2, r14} \n"
- " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r0-r3} \n" /* LR is now in r3. */
- " mov lr, r3 \n" /* LR = r3. */
- " lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB.*/
- " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
- " str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
- " b select_next_task \n"
- " \n"
- " save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " mrs r2, psp \n" /* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n" /* No secure context to save. */
+ " save_s_context: \n"
+ " push {r0-r2, lr} \n"
+ " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r2, lr} \n"
+ " \n"
+ " save_ns_context: \n"
+ " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
+ " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+ " \n"
+ " save_general_regs: \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- " str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " adds r2, r2, #12 \n" /* r2 = r2 + 12. */
- " stm r2, {r4-r11} \n" /* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
- " subs r2, r2, #12 \n" /* r2 = r2 - 12. */
- " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
- " \n"
- " select_next_task: \n"
- " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n" /* r0 = 0. */
- " msr basepri, r0 \n" /* Enable interrupts. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
- " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- " \n"
- " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
- " mov lr, r4 \n" /* LR = r4. */
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n" /* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n" /* LR = r4. */
- " lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n" /* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " restore_ns_context: \n"
- " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
+ " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */
+ " \n"
+ " save_special_regs: \n"
+ " mrs r3, psplim \n" /* r3 = PSPLIM. */
+ " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_1 \n"
+ " mrs r6, PAC_KEY_P_0 \n"
+ " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " str r2, [r1] \n" /* Save the new top of stack in TCB. */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
+ " \n"
+ " restore_context: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
+ " restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_1, r5 \n"
+ " msr PAC_KEY_P_0, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " \n"
+ " restore_s_context: \n"
+ " push {r1-r3, lr} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r1-r3, lr} \n"
+ " \n"
+ " restore_ns_context: \n"
+ " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
+ " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+ " \n"
+ " restore_general_regs: \n"
+ " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " msr psp, r2 \n" /* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
+ " \n"
+ " restore_context_done: \n"
+ " msr psp, r2 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -566,11 +582,8 @@
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
+ " ldr r1, =vPortSVCHandler_C \n"
" bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
index cc79870..a57d2e6 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,20 +48,28 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M33"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/Source/portable/GCC/ARM_CM33/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_context.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/Source/portable/GCC/ARM_CM33/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_context.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
index d70822c..11d8e1b 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/Source/portable/GCC/ARM_CM33/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_init.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/Source/portable/GCC/ARM_CM33/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_init.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
index d247c92..8504ddd 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,31 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1557,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1575,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1588,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1617,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1646,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1675,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1704,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1719,117 +1634,129 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1843,22 +1770,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1874,233 +1800,256 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index b3f6a0a..51ec476 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -52,23 +54,23 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -86,18 +88,26 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
" restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
" msr psp, r2 \n"
" msr psplim, r3 \n"
@@ -113,13 +123,6 @@
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -131,23 +134,30 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
- " movs r1, #2 \n" /* r1 = 2. */
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx r2 \n" /* Finally, branch to EXC_RETURN. */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
@@ -166,8 +176,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -209,7 +217,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +227,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -235,7 +240,7 @@
" \n"
" mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bx lr \n" /* Return. */
@@ -267,7 +272,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
" mrs r2, psp \n" /* r2 = PSP. */
@@ -282,7 +287,6 @@
" vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
" sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
" stmia r1!, {r4-r11} \n" /* Store r4-r11. */
" ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
" stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */
@@ -291,11 +295,19 @@
" mrs r3, psplim \n" /* r3 = PSPLIM. */
" mrs r4, control \n" /* r4 = CONTROL. */
" stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_3 \n"
+ " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
" \n"
" select_next_task: \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
@@ -303,23 +315,23 @@
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
" program_mpu: \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -337,18 +349,26 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
" restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
" msr psp, r2 \n"
" msr psplim, r3 \n"
@@ -369,13 +389,6 @@
" restore_context_done: \n"
" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -400,22 +413,40 @@
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
" stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r2, PAC_KEY_P_2 \n"
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_0 \n"
+ " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" str r0, [r1] \n" /* Save the new top of stack in TCB. */
" \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
" mov r0, #0 \n" /* r0 = 0. */
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r3 \n"
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_0, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
" \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -427,9 +458,6 @@
" msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
" msr psp, r0 \n" /* Remember the new top of stack for the task. */
" bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -487,11 +515,8 @@
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
+ " ldr r1, =vPortSVCHandler_C \n"
" bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index cc79870..a57d2e6 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,20 +48,28 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M33"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
index 7aa8166..0e0abee 100644
--- a/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,30 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1556,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1574,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1587,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1616,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1645,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1674,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1703,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1718,117 +1634,133 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1842,22 +1774,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1873,233 +1804,264 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/Source/portable/GCC/ARM_CM3_MPU/port.c b/Source/portable/GCC/ARM_CM3_MPU/port.c
index f99acf5..af25ed6 100644
--- a/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ b/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -58,6 +58,9 @@
#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to access and manipulate the NVIC. */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -87,7 +90,6 @@
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000 )
@@ -95,6 +97,11 @@
#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -187,6 +194,11 @@
void vResetPrivilege( void ) __attribute__( ( naked ) );
/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
+/**
* @brief Enter critical section.
*/
#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
@@ -229,12 +241,12 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack ) PRIVILEGED_FUNCTION;
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
@@ -252,14 +264,14 @@
* switches can only occur when uxCriticalNesting is zero. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
/*
* This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@@ -289,28 +301,29 @@
}
else
{
- xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
}
- xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
- xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
- xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
- xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
- xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
- xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
- xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
- xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
- xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
- xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
- xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
- xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
- xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
- xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
- xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
- xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+ xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
+ xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
+ xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
+ xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
+ xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
+ xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
+ xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
+ xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
+ xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+
+ xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
- xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
@@ -365,13 +378,13 @@
/* Assumes psp was in use. */
__asm volatile
(
- #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
+ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
#else
- " mrs r0, psp \n"
+ " mrs r0, psp \n"
#endif
" b %0 \n"
::"i" ( vSVCHandler_C ) : "r0", "memory"
@@ -388,6 +401,7 @@
#if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -407,7 +421,6 @@
switch( ucSVCNumber )
{
case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
prvRestoreContextOfFirstTask();
break;
@@ -519,13 +532,12 @@
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r1, control \n" /* Obtain current control value. */
" bic r1, #1 \n" /* Clear nPRIV bit. */
" msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory"
- );
+ );
/* Remember the location where we should copy the stack frame when we exit from
* the system call. */
@@ -539,7 +551,6 @@
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
-
/* Raise a request to exit from the system call upon finishing the
* system call. */
pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -627,13 +638,12 @@
__asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r1, control \n" /* Obtain current control value. */
" orr r1, #1 \n" /* Set nPRIV bit. */
" msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory"
- );
+ );
/* Return to the caller of the System Call entry point (i.e. the
* caller of the MPU_<API>). */
@@ -685,7 +695,7 @@
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
" \n"
/*------------ Program MPU. ------------ */
- " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
" \n"
@@ -696,8 +706,8 @@
" str r3, [r0] \n" /* Disable MPU. */
" \n"
" ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
" \n"
" ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
" ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
@@ -706,7 +716,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
/*---------- Restore Context. ---------- */
- " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
" \n"
@@ -722,8 +732,6 @@
" bx lr \n"
" \n"
" .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
/*-----------------------------------------------------------*/
@@ -733,6 +741,40 @@
*/
BaseType_t xPortStartScheduler( void )
{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -817,11 +859,12 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the same priority as the kernel, and the SVC
- * handler higher priority so it can be used to exit a critical section (where
- * lower priorities are masked). */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
/* Configure the regions in the MPU that are common to all tasks. */
prvSetupMPU();
@@ -833,15 +876,14 @@
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
- #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/* Start the first task. */
- __asm volatile
- (
+ __asm volatile (
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"
" ldr r0, [r0] \n"
@@ -853,8 +895,7 @@
" svc %0 \n" /* System call to start first task. */
" nop \n"
" .ltorg \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
/* Should not get here! */
return 0;
@@ -945,7 +986,7 @@
__asm volatile
(
- " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" ldr r1, [r2] \n" /* r1 = Location where the context should be saved. */
" \n"
@@ -969,7 +1010,7 @@
" msr basepri, r0 \n"
" \n"
/*------------ Program MPU. ------------ */
- " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
" \n"
@@ -980,8 +1021,8 @@
" str r3, [r0] \n" /* Disable MPU. */
" \n"
" ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
" \n"
" ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
" ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
@@ -990,7 +1031,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
/*---------- Restore Context. ---------- */
- " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
" \n"
@@ -1004,8 +1045,6 @@
" bx lr \n"
" \n"
" .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -1016,13 +1055,19 @@
uint32_t ulDummy;
ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
}
@@ -1046,12 +1091,28 @@
static void prvSetupMPU( void )
{
- extern uint32_t __privileged_functions_start__[];
- extern uint32_t __privileged_functions_end__[];
- extern uint32_t __FLASH_segment_start__[];
- extern uint32_t __FLASH_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __FLASH_segment_start__;
+ extern uint32_t * __FLASH_segment_end__;
+ extern uint32_t * __privileged_data_start__;
+ extern uint32_t * __privileged_data_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __FLASH_segment_start__[];
+ extern uint32_t __FLASH_segment_end__[];
+ extern uint32_t __privileged_data_start__[];
+ extern uint32_t __privileged_data_end__[];
+ #endif /* if defined( __ARMCC_VERSION ) */
+
+ /* Ensure that the device has the expected MPU type */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check the expected MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
@@ -1142,8 +1203,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -1162,15 +1221,40 @@
}
/*-----------------------------------------------------------*/
+void vPortSwitchToUserMode( void )
+{
+ /* Load the current task's MPU settings from its TCB. */
+ xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+ /* Mark the task as unprivileged. */
+ xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+ /* Lower the processor's privilege level. */
+ vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
- extern uint32_t __SRAM_segment_start__[];
- extern uint32_t __SRAM_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
+ #if defined( __ARMCC_VERSION )
+
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __SRAM_segment_start__;
+ extern uint32_t * __SRAM_segment_end__;
+ extern uint32_t * __privileged_data_start__;
+ extern uint32_t * __privileged_data_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __SRAM_segment_start__[];
+ extern uint32_t __SRAM_segment_end__[];
+ extern uint32_t __privileged_data_start__[];
+ extern uint32_t __privileged_data_end__[];
+ #endif /* if defined( __ARMCC_VERSION ) */
+
int32_t lIndex;
uint32_t ul;
@@ -1180,7 +1264,7 @@
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
+ ( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
@@ -1210,7 +1294,7 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that the
* stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1221,12 +1305,12 @@
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+ ( prvGetMPURegionSizeSetting ( ( uint32_t ) ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( portMPU_REGION_ENABLE );
xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
- ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+ ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
tskMPU_WRITE_PERMISSION );
}
@@ -1281,45 +1365,57 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
- uint32_t ulBufferLength,
- uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-{
- uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
- BaseType_t xAccessGranted = pdFALSE;
- const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
- xAccessGranted = pdTRUE;
- }
- else
- {
- if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
{
- ulBufferStartAddress = ( uint32_t ) pvBuffer;
- ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
- for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
{
- if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
{
- xAccessGranted = pdTRUE;
- break;
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
}
}
}
+
+ return xAccessGranted;
}
- return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
#if ( configASSERT_DEFINED == 1 )
@@ -1360,7 +1456,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1376,7 +1472,7 @@
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
* scheduler. Note however that some vendor specific peripheral libraries
* assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredicable behaviour. */
+ * of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
diff --git a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
index 170a58c..3d8d604 100644
--- a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,101 +47,107 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
+#define portUSING_MPU_WRAPPERS 1
+#define portPRIVILEGE_BIT ( 0x80000000UL )
- #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
- #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
- #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
- #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
- #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
+#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- #define portGENERAL_PERIPHERALS_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 5UL )
- #define portPRIVILEGED_FLASH_REGION ( 6UL )
- #define portPRIVILEGED_RAM_REGION ( 7UL )
- #define portFIRST_CONFIGURABLE_REGION ( 0UL )
- #define portLAST_CONFIGURABLE_REGION ( 2UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portSTACK_REGION ( 3UL )
+#define portGENERAL_PERIPHERALS_REGION ( 4UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 5UL )
+#define portPRIVILEGED_FLASH_REGION ( 6UL )
+#define portPRIVILEGED_RAM_REGION ( 7UL )
+#define portFIRST_CONFIGURABLE_REGION ( 0UL )
+#define portLAST_CONFIGURABLE_REGION ( 2UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
- #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+typedef struct MPU_REGION_REGISTERS
+{
+ uint32_t ulRegionBaseAddress;
+ uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
- typedef struct MPU_REGION_REGISTERS
+typedef struct MPU_REGION_SETTINGS
+{
+ uint32_t ulRegionStartAddress;
+ uint32_t ulRegionEndAddress;
+ uint32_t ulRegionPermissions;
+} xMPU_REGION_SETTINGS;
+
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+
+ #ifndef configSYSTEM_CALL_STACK_SIZE
+ #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #endif
+
+ typedef struct SYSTEM_CALL_STACK_INFO
{
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
- } xMPU_REGION_REGISTERS;
+ uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
+ uint32_t * pulSystemCallStack;
+ uint32_t * pulTaskStack;
+ uint32_t ulLinkRegisterAtSystemCallEntry;
+ } xSYSTEM_CALL_STACK_INFO;
- typedef struct MPU_REGION_SETTINGS
- {
- uint32_t ulRegionStartAddress;
- uint32_t ulRegionEndAddress;
- uint32_t ulRegionPermissions;
- } xMPU_REGION_SETTINGS;
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
- #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-
- #ifndef configSYSTEM_CALL_STACK_SIZE
- #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
- #endif
-
- typedef struct SYSTEM_CALL_STACK_INFO
- {
- uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
- uint32_t * pulSystemCallStack;
- uint32_t * pulTaskStack;
- uint32_t ulLinkRegisterAtSystemCallEntry;
- } xSYSTEM_CALL_STACK_INFO;
-
- #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
-
+/*
+ * +------------------------------+-------------------------------+-----+
+ * | CONTROL, r4-r11, EXC_RETURN | PSP, r0-r3, r12, LR, PC, xPSR | |
+ * +------------------------------+-------------------------------+-----+
+ *
+ * <-----------------------------><-------------------------------><---->
+ * 10 9 1
+ */
#define MAX_CONTEXT_SIZE ( 20 )
/* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
- /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
+#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
- typedef struct MPU_SETTINGS
- {
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
- xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
- uint32_t ulContext[ MAX_CONTEXT_SIZE ];
- uint32_t ulTaskFlags;
+typedef struct MPU_SETTINGS
+{
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
+ xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
+ uint32_t ulContext[ MAX_CONTEXT_SIZE ];
+ uint32_t ulTaskFlags;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
@@ -152,10 +158,10 @@
} xMPU_SETTINGS;
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* SVC numbers for various services. */
@@ -166,8 +172,8 @@
/* Scheduler utilities. */
- #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
- #define portYIELD_WITHIN_API() \
+#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -178,185 +184,206 @@
__asm volatile ( "isb" ); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
- return ucReturn;
- }
+ return ucReturn;
+ }
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
/*-----------------------------------------------------------*/
- extern BaseType_t xIsPrivileged( void );
- extern void vResetPrivilege( void );
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
- #define portIS_PRIVILEGED() xIsPrivileged()
+#define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
*/
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
- #define portRESET_PRIVILEGE() vResetPrivilege()
+#define portRESET_PRIVILEGE() vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
/*-----------------------------------------------------------*/
- extern BaseType_t xPortIsTaskPrivileged( void );
+extern BaseType_t xPortIsTaskPrivileged( void );
/**
* @brief Checks whether or not the calling task is privileged.
*
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
*/
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
/*-----------------------------------------------------------*/
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
}
-/*-----------------------------------------------------------*/
-
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
+ return xReturn;
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI;
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
+ __asm volatile
+ (
+ " mov %0, %1 \n" \
+ " msr basepri, %0 \n" \
+ " isb \n" \
+ " dsb \n" \
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
/*-----------------------------------------------------------*/
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n" \
+ " mov %1, %2 \n" \
+ " msr basepri, %1 \n" \
+ " isb \n" \
+ " dsb \n" \
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+}
/*-----------------------------------------------------------*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+ __asm volatile
+ (
+ " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
- #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. *www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
- #endif
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. *www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+ #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
+#endif
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM4F/port.c b/Source/portable/GCC/ARM_CM4F/port.c
index 73430b5..df7027a 100644
--- a/Source/portable/GCC/ARM_CM4F/port.c
+++ b/Source/portable/GCC/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -34,14 +34,18 @@
#include "FreeRTOS.h"
#include "task.h"
-#ifndef __VFP_FP__
+#ifndef __ARM_FP
#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
@@ -62,6 +66,11 @@
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -251,8 +260,8 @@
void vPortSVCHandler( void )
{
__asm volatile (
- " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
- " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r3, =pxCurrentTCB \n" /* Restore the context. */
+ " ldr r1, [r3] \n" /* Get the pxCurrentTCB address. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n" /* Restore the task stack pointer. */
@@ -261,8 +270,7 @@
" msr basepri, r0 \n"
" bx r14 \n"
" \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ " .ltorg \n"
);
}
/*-----------------------------------------------------------*/
@@ -302,6 +310,40 @@
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -351,22 +393,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -386,9 +428,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the lowest priority interrupts. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
@@ -466,7 +510,7 @@
" mrs r0, psp \n"
" isb \n"
" \n"
- " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
+ " ldr r3, =pxCurrentTCB \n" /* Get the location of the current TCB. */
" ldr r2, [r3] \n"
" \n"
" tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
@@ -507,8 +551,7 @@
" \n"
" bx r14 \n"
" \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ " .ltorg \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -521,14 +564,21 @@
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portENABLE_INTERRUPTS();
}
@@ -834,7 +884,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/GCC/ARM_CM4F/portmacro.h b/Source/portable/GCC/ARM_CM4F/portmacro.h
index ec9cfc9..f555ef8 100644
--- a/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -47,45 +47,45 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
- typedef uint64_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+ typedef uint64_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL
+#else /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -96,154 +96,166 @@
__asm volatile ( "isb" ); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
- return ucReturn;
- }
+ return ucReturn;
+ }
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
}
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI;
- __asm volatile
- (
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
+ __asm volatile
+ (
+ " mov %0, %1 \n" \
+ " msr basepri, %0 \n" \
+ " isb \n" \
+ " dsb \n" \
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
+ __asm volatile
+ (
+ " mrs %0, basepri \n" \
+ " mov %1, %2 \n" \
+ " msr basepri, %1 \n" \
+ " isb \n" \
+ " dsb \n" \
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+ __asm volatile
+ (
+ " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+ );
+}
/*-----------------------------------------------------------*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 7aa8166..0e0abee 100644
--- a/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,30 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1556,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1574,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1587,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1616,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1645,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1674,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1703,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1718,117 +1634,133 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1842,22 +1774,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1873,233 +1804,264 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " pop {r0} \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " pop {r0} \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/Source/portable/GCC/ARM_CM4_MPU/port.c b/Source/portable/GCC/ARM_CM4_MPU/port.c
index 575c5ac..9ff846e 100644
--- a/Source/portable/GCC/ARM_CM4_MPU/port.c
+++ b/Source/portable/GCC/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -40,7 +40,7 @@
#include "task.h"
#include "mpu_syscall_numbers.h"
-#ifndef __VFP_FP__
+#ifndef __ARM_FP
#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif
@@ -62,6 +62,9 @@
#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to access and manipulate the NVIC. */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -97,7 +100,6 @@
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
/* Constants required to manipulate the VFP. */
#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
@@ -109,6 +111,11 @@
#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -131,7 +138,7 @@
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
/* Does addr lie within [start, end] address range? */
#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
@@ -208,6 +215,11 @@
void vResetPrivilege( void ) __attribute__( ( naked ) );
/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
+/**
* @brief Enter critical section.
*/
#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
@@ -252,13 +264,13 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -277,14 +289,14 @@
* switches can only occur when uxCriticalNesting is zero. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
/*
* This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@@ -315,28 +327,29 @@
}
else
{
- xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
}
- xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
- xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
- xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
- xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
- xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
- xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
- xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
- xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
- xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
- xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
- xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
- xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
- xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
- xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
- xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
- xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+ xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
+ xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
+ xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
+ xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
+ xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
+ xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
+ xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
+ xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
+ xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+
+ xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
- xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
@@ -399,13 +412,13 @@
/* Assumes psp was in use. */
__asm volatile
(
- #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
+ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
#else
- " mrs r0, psp \n"
+ " mrs r0, psp \n"
#endif
" b %0 \n"
::"i" ( vSVCHandler_C ) : "r0", "memory"
@@ -422,6 +435,7 @@
#if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -441,7 +455,6 @@
switch( ucSVCNumber )
{
case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
prvRestoreContextOfFirstTask();
break;
@@ -544,12 +557,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -570,13 +582,12 @@
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r1, control \n" /* Obtain current control value. */
" bic r1, #1 \n" /* Clear nPRIV bit. */
" msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory"
- );
+ );
/* Remember the location where we should copy the stack frame when we exit from
* the system call. */
@@ -590,7 +601,6 @@
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
-
/* Raise a request to exit from the system call upon finishing the
* system call. */
pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -669,12 +679,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -695,13 +704,12 @@
__asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r1, control \n" /* Obtain current control value. */
" orr r1, #1 \n" /* Set nPRIV bit. */
" msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory"
- );
+ );
/* Return to the caller of the System Call entry point (i.e. the
* caller of the MPU_<API>). */
@@ -753,7 +761,7 @@
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
" \n"
/*------------ Program MPU. ------------ */
- " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
" \n"
@@ -764,15 +772,15 @@
" str r3, [r0] \n" /* Disable MPU. */
" \n"
" ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
" \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* configTOTAL_MPU_REGIONS == 16. */
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 8]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 8]. */
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 9 - 12]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 9 - 12]. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
" \n"
" ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
" ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
@@ -781,7 +789,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
/*---------- Restore Context. ---------- */
- " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
" \n"
@@ -797,8 +805,6 @@
" bx lr \n"
" \n"
" .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB\n"
);
}
/*-----------------------------------------------------------*/
@@ -813,6 +819,7 @@
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
#else
+
/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
* configENABLE_ERRATA_837070_WORKAROUND to 1 in your
* FreeRTOSConfig.h. */
@@ -820,6 +827,40 @@
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#endif
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -904,11 +945,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the same priority as the kernel, and the SVC
- * handler higher priority so it can be used to exit a critical section (where
- * lower priorities are masked). */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Configure the regions in the MPU that are common to all tasks. */
prvSetupMPU();
@@ -920,11 +961,11 @@
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
- #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
@@ -936,8 +977,7 @@
* in use in case the FPU was used before the scheduler was started - which
* would otherwise result in the unnecessary leaving of space in the SVC stack
* for lazy saving of FPU registers. */
- __asm volatile
- (
+ __asm volatile (
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"
" ldr r0, [r0] \n"
@@ -951,8 +991,7 @@
" svc %0 \n" /* System call to start first task. */
" nop \n"
" .ltorg \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory"
- );
+ ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
/* Should not get here! */
return 0;
@@ -1043,7 +1082,7 @@
__asm volatile
(
- " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" ldr r1, [r2] \n" /* r1 = Location where the context should be saved. */
" \n"
@@ -1067,21 +1106,21 @@
" \n"
/*---------- Select next task. --------- */
" mov r0, %0 \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
" msr basepri, r0 \n"
" dsb \n"
" isb \n"
- #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
- #endif
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
" bl vTaskSwitchContext \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"
" \n"
/*------------ Program MPU. ------------ */
- " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
" \n"
@@ -1092,15 +1131,15 @@
" str r3, [r0] \n" /* Disable MPU. */
" \n"
" ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
" \n"
- #if ( configTOTAL_MPU_REGIONS == 16 )
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* configTOTAL_MPU_REGIONS == 16. */
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
+ " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+ " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
" \n"
" ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
" ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
@@ -1109,7 +1148,7 @@
" dsb \n" /* Force memory writes before continuing. */
" \n"
/*---------- Restore Context. ---------- */
- " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
+ " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */
" ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
" ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
" \n"
@@ -1129,8 +1168,6 @@
" bx lr \n"
" \n"
" .ltorg \n" /* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -1141,13 +1178,19 @@
uint32_t ulDummy;
ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
}
@@ -1188,6 +1231,7 @@
static void prvSetupMPU( void )
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1301,8 +1345,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -1321,12 +1363,26 @@
}
/*-----------------------------------------------------------*/
+void vPortSwitchToUserMode( void )
+{
+ /* Load the current task's MPU settings from its TCB. */
+ xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+ /* Mark the task as unprivileged. */
+ xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+ /* Lower the processor's privilege level. */
+ vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __SRAM_segment_start__;
@@ -1350,7 +1406,7 @@
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
+ ( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
@@ -1380,7 +1436,7 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that the
* stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1391,13 +1447,13 @@
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+ ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( portMPU_REGION_ENABLE );
xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
- ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+ ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
tskMPU_WRITE_PERMISSION );
}
@@ -1452,45 +1508,57 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
- uint32_t ulBufferLength,
- uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-{
- uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
- BaseType_t xAccessGranted = pdFALSE;
- const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
- xAccessGranted = pdTRUE;
- }
- else
- {
- if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
{
- ulBufferStartAddress = ( uint32_t ) pvBuffer;
- ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
- for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
{
- if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
{
- xAccessGranted = pdTRUE;
- break;
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
}
}
}
+
+ return xAccessGranted;
}
- return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
#if ( configASSERT_DEFINED == 1 )
@@ -1531,7 +1599,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1547,7 +1615,7 @@
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
* scheduler. Note however that some vendor specific peripheral libraries
* assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredicable behaviour. */
+ * of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
diff --git a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
index e76c687..1ba44d1 100644
--- a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -63,7 +63,7 @@
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
@@ -71,9 +71,14 @@
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+ #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
#endif
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+ #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@@ -93,7 +98,7 @@
#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -175,8 +180,8 @@
#define configTEX_S_C_B_SRAM ( 0x07UL )
#endif
-#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
-#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
+#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL )
+#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL )
#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
@@ -185,8 +190,6 @@
#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
typedef struct MPU_REGION_REGISTERS
{
uint32_t ulRegionBaseAddress;
@@ -203,7 +206,7 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
#ifndef configSYSTEM_CALL_STACK_SIZE
- #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
#endif
typedef struct SYSTEM_CALL_STACK_INFO
@@ -216,14 +219,23 @@
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-#define MAX_CONTEXT_SIZE ( 52 )
+/*
+ * +---------+---------------+-----------------+-----------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 | |
+ * | | | EXC_RETURN | LR, PC, xPSR | |
+ * +---------+---------------+-----------------+-----------------+-----+
+ *
+ * <--------><---------------><----------------><----------------><---->
+ * 16 17 10 9 1
+ */
+#define MAX_CONTEXT_SIZE ( 53 )
/* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
-#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
typedef struct MPU_SETTINGS
{
@@ -255,7 +267,7 @@
/* Scheduler utilities. */
-#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" )
#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
@@ -269,8 +281,20 @@
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
@@ -311,7 +335,7 @@
/* Check the configuration. */
#if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
/* Store/clear the ready priorities in a bit map. */
@@ -326,7 +350,7 @@
/*-----------------------------------------------------------*/
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -343,24 +367,33 @@
extern BaseType_t xIsPrivileged( void );
extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
-#define portIS_PRIVILEGED() xIsPrivileged()
+#define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
*/
-#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
-#define portRESET_PRIVILEGE() vResetPrivilege()
+#define portRESET_PRIVILEGE() vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
/*-----------------------------------------------------------*/
extern BaseType_t xPortIsTaskPrivileged( void );
@@ -370,7 +403,7 @@
*
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
*/
-#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
/*-----------------------------------------------------------*/
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -403,13 +436,13 @@
(
" mov %0, %1 \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
" msr basepri, %0 \n"
" isb \n"
" dsb \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
@@ -426,13 +459,13 @@
" mrs %0, basepri \n"
" mov %1, %2 \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
" msr basepri, %1 \n"
" isb \n"
" dsb \n"
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
@@ -447,7 +480,7 @@
{
__asm volatile
(
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
+ " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
);
}
/*-----------------------------------------------------------*/
@@ -455,7 +488,7 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
#endif
/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
index d247c92..9c3e8c7 100644
--- a/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,31 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1557,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1575,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1588,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1617,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1646,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1675,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1704,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1719,117 +1634,130 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1843,22 +1771,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1874,233 +1801,256 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM55/non_secure/port.c b/Source/portable/GCC/ARM_CM55/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM55/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM55/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portasm.c b/Source/portable/GCC/ARM_CM55/non_secure/portasm.c
index 7431c98..bdee088 100644
--- a/Source/portable/GCC/ARM_CM55/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM55/non_secure/portasm.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -52,23 +54,23 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -86,23 +88,31 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
" restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
" msr psp, r3 \n"
" msr psplim, r4 \n"
" msr control, r5 \n"
- " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" \n"
" restore_general_regs_first_task: \n"
@@ -115,14 +125,6 @@
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xSecureContextConst2: .word xSecureContext \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -134,25 +136,32 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r3, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
+ " ldr r4, =xSecureContext \n"
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
- " movs r1, #2 \n" /* r1 = 2. */
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx r3 \n" /* Finally, branch to EXC_RETURN. */
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
);
}
@@ -171,8 +180,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -214,7 +221,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +231,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -240,7 +244,7 @@
" \n"
" mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bx lr \n" /* Return. */
@@ -274,9 +278,9 @@
" .extern SecureContext_SaveContext \n"
" .extern SecureContext_LoadContext \n"
" \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
" ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
" \n"
@@ -293,7 +297,6 @@
" \n"
" save_general_regs: \n"
" mrs r3, psp \n"
- " \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
" add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */
" tst lr, #0x10 \n"
@@ -303,7 +306,6 @@
" vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */
" sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
" stmia r2!, {r4-r11} \n" /* Store r4-r11. */
" ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
" stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */
@@ -313,11 +315,19 @@
" mrs r4, psplim \n" /* r4 = PSPLIM. */
" mrs r5, control \n" /* r5 = CONTROL. */
" stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
- " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_1 \n"
+ " mrs r5, PAC_KEY_P_2 \n"
+ " mrs r6, PAC_KEY_P_3 \n"
+ " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
" \n"
" select_next_task: \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
@@ -325,23 +335,23 @@
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
" program_mpu: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -359,23 +369,31 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
" restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
" msr psp, r3 \n"
" msr psplim, r4 \n"
" msr control, r5 \n"
- " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" cbz r0, restore_ns_context \n" /* No secure context to restore. */
" \n"
@@ -404,14 +422,6 @@
" restore_context_done: \n"
" str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xSecureContextConst: .word xSecureContext \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -422,93 +432,99 @@
{
__asm volatile
(
- " .syntax unified \n"
- " .extern SecureContext_SaveContext \n"
- " .extern SecureContext_LoadContext \n"
- " \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
- " mrs r2, psp \n" /* Read PSP in r2. */
- " \n"
- " cbz r0, save_ns_context \n" /* No secure context to save. */
- " push {r0-r2, r14} \n"
- " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r0-r3} \n" /* LR is now in r3. */
- " mov lr, r3 \n" /* LR = r3. */
- " lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB.*/
- " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
- " str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
- " b select_next_task \n"
- " \n"
- " save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " mrs r2, psp \n" /* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n" /* No secure context to save. */
+ " save_s_context: \n"
+ " push {r0-r2, lr} \n"
+ " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r2, lr} \n"
+ " \n"
+ " save_ns_context: \n"
+ " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
+ " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+ " \n"
+ " save_general_regs: \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- " str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " adds r2, r2, #12 \n" /* r2 = r2 + 12. */
- " stm r2, {r4-r11} \n" /* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
- " subs r2, r2, #12 \n" /* r2 = r2 - 12. */
- " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
- " \n"
- " select_next_task: \n"
- " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n" /* r0 = 0. */
- " msr basepri, r0 \n" /* Enable interrupts. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
- " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- " \n"
- " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
- " mov lr, r4 \n" /* LR = r4. */
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n" /* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n" /* LR = r4. */
- " lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n" /* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " restore_ns_context: \n"
- " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
+ " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */
+ " \n"
+ " save_special_regs: \n"
+ " mrs r3, psplim \n" /* r3 = PSPLIM. */
+ " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_1 \n"
+ " mrs r6, PAC_KEY_P_0 \n"
+ " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " str r2, [r1] \n" /* Save the new top of stack in TCB. */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
+ " \n"
+ " restore_context: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
+ " restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_1, r5 \n"
+ " msr PAC_KEY_P_0, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " \n"
+ " restore_s_context: \n"
+ " push {r1-r3, lr} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r1-r3, lr} \n"
+ " \n"
+ " restore_ns_context: \n"
+ " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
+ " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+ " \n"
+ " restore_general_regs: \n"
+ " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " msr psp, r2 \n" /* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
+ " \n"
+ " restore_context_done: \n"
+ " msr psp, r2 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -566,11 +582,8 @@
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
+ " ldr r1, =vPortSVCHandler_C \n"
" bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portasm.h b/Source/portable/GCC/ARM_CM55/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM55/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM55/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h
index 880205c..11a2777 100644
--- a/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM55/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M55"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_context.c b/Source/portable/GCC/ARM_CM55/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_context.c
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_context.h b/Source/portable/GCC/ARM_CM55/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_context.h
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c
index d70822c..11d8e1b 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_context_port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_heap.c b/Source/portable/GCC/ARM_CM55/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_heap.c
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_heap.h b/Source/portable/GCC/ARM_CM55/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_heap.h
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_init.c b/Source/portable/GCC/ARM_CM55/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_init.c
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_init.h b/Source/portable/GCC/ARM_CM55/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_init.h
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h
+++ b/Source/portable/GCC/ARM_CM55/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
index d247c92..8504ddd 100644
--- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,31 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1557,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1575,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1588,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1617,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1646,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1675,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1704,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1719,117 +1634,129 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1843,22 +1770,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1874,233 +1800,256 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
index b3f6a0a..51ec476 100644
--- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -52,23 +54,23 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -86,18 +88,26 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
" restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
" msr psp, r2 \n"
" msr psplim, r3 \n"
@@ -113,13 +123,6 @@
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -131,23 +134,30 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
- " movs r1, #2 \n" /* r1 = 2. */
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx r2 \n" /* Finally, branch to EXC_RETURN. */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
@@ -166,8 +176,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -209,7 +217,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +227,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -235,7 +240,7 @@
" \n"
" mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bx lr \n" /* Return. */
@@ -267,7 +272,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
" mrs r2, psp \n" /* r2 = PSP. */
@@ -282,7 +287,6 @@
" vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
" sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
" stmia r1!, {r4-r11} \n" /* Store r4-r11. */
" ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
" stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */
@@ -291,11 +295,19 @@
" mrs r3, psplim \n" /* r3 = PSPLIM. */
" mrs r4, control \n" /* r4 = CONTROL. */
" stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_3 \n"
+ " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
" \n"
" select_next_task: \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
@@ -303,23 +315,23 @@
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
" program_mpu: \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -337,18 +349,26 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
" restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
" msr psp, r2 \n"
" msr psplim, r3 \n"
@@ -369,13 +389,6 @@
" restore_context_done: \n"
" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -400,22 +413,40 @@
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
" stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r2, PAC_KEY_P_2 \n"
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_0 \n"
+ " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" str r0, [r1] \n" /* Save the new top of stack in TCB. */
" \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
" mov r0, #0 \n" /* r0 = 0. */
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r3 \n"
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_0, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
" \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -427,9 +458,6 @@
" msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
" msr psp, r0 \n" /* Remember the new top of stack for the task. */
" bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -487,11 +515,8 @@
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
+ " ldr r1, =vPortSVCHandler_C \n"
" bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
index 880205c..11a2777 100644
--- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M55"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM7/r0p1/port.c b/Source/portable/GCC/ARM_CM7/r0p1/port.c
index afd4baa..7f689ba 100644
--- a/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -34,14 +34,18 @@
#include "FreeRTOS.h"
#include "task.h"
-#ifndef __VFP_FP__
+#ifndef __ARM_FP
#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
@@ -56,6 +60,11 @@
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -245,8 +254,8 @@
void vPortSVCHandler( void )
{
__asm volatile (
- " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
- " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r3, =pxCurrentTCB \n" /* Restore the context. */
+ " ldr r1, [r3] \n" /* Get the pxCurrentTCB address. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
" msr psp, r0 \n" /* Restore the task stack pointer. */
@@ -255,8 +264,7 @@
" msr basepri, r0 \n"
" bx r14 \n"
" \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ " .ltorg \n"
);
}
/*-----------------------------------------------------------*/
@@ -290,6 +298,40 @@
*/
BaseType_t xPortStartScheduler( void )
{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -339,22 +381,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -374,9 +416,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the lowest priority interrupts. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
@@ -454,7 +498,7 @@
" mrs r0, psp \n"
" isb \n"
" \n"
- " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
+ " ldr r3, =pxCurrentTCB \n" /* Get the location of the current TCB. */
" ldr r2, [r3] \n"
" \n"
" tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
@@ -497,8 +541,7 @@
" \n"
" bx r14 \n"
" \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ " .ltorg \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -511,14 +554,21 @@
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portENABLE_INTERRUPTS();
}
@@ -824,7 +874,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
index 8f08bd0..eeb95a9 100644
--- a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -47,42 +47,42 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portDONT_DISCARD __attribute__( ( used ) )
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -93,158 +93,170 @@
__asm volatile ( "isb" ); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
- return ucReturn;
- }
+ return ucReturn;
+ }
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
}
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI;
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI;
- __asm volatile
- (
- " mov %0, %1 \n"\
- " cpsid i \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- " cpsie i \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
- }
+ __asm volatile
+ (
+ " mov %0, %1 \n" \
+ " cpsid i \n" \
+ " msr basepri, %0 \n" \
+ " isb \n" \
+ " dsb \n" \
+ " cpsie i \n" \
+ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " cpsid i \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- " cpsie i \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
+ __asm volatile
+ (
+ " mrs %0, basepri \n" \
+ " mov %1, %2 \n" \
+ " cpsid i \n" \
+ " msr basepri, %1 \n" \
+ " isb \n" \
+ " dsb \n" \
+ " cpsie i \n" \
+ : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
- }
+ /* This return will not be reached but is necessary to prevent compiler
+ * warnings. */
+ return ulOriginalBASEPRI;
+}
/*-----------------------------------------------------------*/
- portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
- {
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
- }
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+ __asm volatile
+ (
+ " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
+ );
+}
/*-----------------------------------------------------------*/
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
index d247c92..9c3e8c7 100644
--- a/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,31 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1557,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1575,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1588,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1617,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1646,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1675,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1704,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1719,117 +1634,130 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
+
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1843,22 +1771,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1874,233 +1801,256 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM85/non_secure/port.c b/Source/portable/GCC/ARM_CM85/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM85/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM85/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portasm.c b/Source/portable/GCC/ARM_CM85/non_secure/portasm.c
index 7431c98..bdee088 100644
--- a/Source/portable/GCC/ARM_CM85/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM85/non_secure/portasm.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -52,23 +54,23 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -86,23 +88,31 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
" restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
" msr psp, r3 \n"
" msr psplim, r4 \n"
" msr control, r5 \n"
- " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" \n"
" restore_general_regs_first_task: \n"
@@ -115,14 +125,6 @@
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xSecureContextConst2: .word xSecureContext \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -134,25 +136,32 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r3, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
- " ldr r4, xSecureContextConst2 \n"
+ " ldr r4, =xSecureContext \n"
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
- " movs r1, #2 \n" /* r1 = 2. */
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx r3 \n" /* Finally, branch to EXC_RETURN. */
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- "xSecureContextConst2: .word xSecureContext \n"
);
}
@@ -171,8 +180,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -214,7 +221,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -224,9 +231,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -240,7 +244,7 @@
" \n"
" mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bx lr \n" /* Return. */
@@ -274,9 +278,9 @@
" .extern SecureContext_SaveContext \n"
" .extern SecureContext_LoadContext \n"
" \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
" ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
" \n"
@@ -293,7 +297,6 @@
" \n"
" save_general_regs: \n"
" mrs r3, psp \n"
- " \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
" add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */
" tst lr, #0x10 \n"
@@ -303,7 +306,6 @@
" vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */
" sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
" stmia r2!, {r4-r11} \n" /* Store r4-r11. */
" ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
" stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */
@@ -313,11 +315,19 @@
" mrs r4, psplim \n" /* r4 = PSPLIM. */
" mrs r5, control \n" /* r5 = CONTROL. */
" stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
- " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_1 \n"
+ " mrs r5, PAC_KEY_P_2 \n"
+ " mrs r6, PAC_KEY_P_3 \n"
+ " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
" \n"
" select_next_task: \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
@@ -325,23 +335,23 @@
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
" program_mpu: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -359,23 +369,31 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
" ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
" \n"
" restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_2, r5 \n"
+ " msr PAC_KEY_P_3, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
" ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
" msr psp, r3 \n"
" msr psplim, r4 \n"
" msr control, r5 \n"
- " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
" str r0, [r4] \n" /* Restore xSecureContext. */
" cbz r0, restore_ns_context \n" /* No secure context to restore. */
" \n"
@@ -404,14 +422,6 @@
" restore_context_done: \n"
" str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xSecureContextConst: .word xSecureContext \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -422,93 +432,99 @@
{
__asm volatile
(
- " .syntax unified \n"
- " .extern SecureContext_SaveContext \n"
- " .extern SecureContext_LoadContext \n"
- " \n"
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
- " mrs r2, psp \n" /* Read PSP in r2. */
- " \n"
- " cbz r0, save_ns_context \n" /* No secure context to save. */
- " push {r0-r2, r14} \n"
- " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r0-r3} \n" /* LR is now in r3. */
- " mov lr, r3 \n" /* LR = r3. */
- " lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB.*/
- " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
- " str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
- " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
- " b select_next_task \n"
- " \n"
- " save_ns_context: \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+ " mrs r2, psp \n" /* Read PSP in r2. */
+ " \n"
+ " cbz r0, save_ns_context \n" /* No secure context to save. */
+ " save_s_context: \n"
+ " push {r0-r2, lr} \n"
+ " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r0-r2, lr} \n"
+ " \n"
+ " save_ns_context: \n"
+ " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
+ " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+ " \n"
+ " save_general_regs: \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- " str r2, [r1] \n" /* Save the new top of stack in TCB. */
- " adds r2, r2, #12 \n" /* r2 = r2 + 12. */
- " stm r2, {r4-r11} \n" /* Store the registers that are not saved automatically. */
- " mrs r1, psplim \n" /* r1 = PSPLIM. */
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
- " subs r2, r2, #12 \n" /* r2 = r2 - 12. */
- " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
- " \n"
- " select_next_task: \n"
- " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n" /* r0 = 0. */
- " msr basepri, r0 \n" /* Enable interrupts. */
- " \n"
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
- " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- " \n"
- " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
- " mov lr, r4 \n" /* LR = r4. */
- " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
- " str r0, [r3] \n" /* Restore the task's xSecureContext. */
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
- " push {r2, r4} \n"
- " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- " pop {r2, r4} \n"
- " mov lr, r4 \n" /* LR = r4. */
- " lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- " msr psp, r2 \n" /* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " restore_ns_context: \n"
- " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
+ " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */
+ " \n"
+ " save_special_regs: \n"
+ " mrs r3, psplim \n" /* r3 = PSPLIM. */
+ " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_1 \n"
+ " mrs r6, PAC_KEY_P_0 \n"
+ " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " str r2, [r1] \n" /* Save the new top of stack in TCB. */
+ " \n"
+ " select_next_task: \n"
+ " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n" /* r0 = 0. */
+ " msr basepri, r0 \n" /* Enable interrupts. */
+ " \n"
+ " restore_context: \n"
+ " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
+ " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+ " \n"
+ " restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_1, r5 \n"
+ " msr PAC_KEY_P_0, r6 \n"
+ " clrm {r3-r6} \n" /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */
+ " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r3] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " \n"
+ " restore_s_context: \n"
+ " push {r1-r3, lr} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ " pop {r1-r3, lr} \n"
+ " \n"
+ " restore_ns_context: \n"
+ " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
+ " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+ " \n"
+ " restore_general_regs: \n"
+ " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
- " it eq \n"
- " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+ " it eq \n"
+ " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " msr psp, r2 \n" /* Remember the new top of stack for the task. */
- " bx lr \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- "xSecureContextConst: .word xSecureContext \n"
+ " \n"
+ " restore_context_done: \n"
+ " msr psp, r2 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -566,11 +582,8 @@
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
+ " ldr r1, =vPortSVCHandler_C \n"
" bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portasm.h b/Source/portable/GCC/ARM_CM85/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM85/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM85/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h
index f606f81..3386f52 100644
--- a/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM85/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M85"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_context.c b/Source/portable/GCC/ARM_CM85/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_context.c
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_context.h b/Source/portable/GCC/ARM_CM85/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_context.h
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c
index d70822c..11d8e1b 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_context_port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_heap.c b/Source/portable/GCC/ARM_CM85/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_heap.c
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_heap.h b/Source/portable/GCC/ARM_CM85/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_heap.h
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_init.c b/Source/portable/GCC/ARM_CM85/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_init.c
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_init.h b/Source/portable/GCC/ARM_CM85/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_init.h
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h
+++ b/Source/portable/GCC/ARM_CM85/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
index d247c92..8504ddd 100644
--- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
+++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,12 +62,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskDelayUntil_Unpriv \n"
" MPU_xTaskDelayUntil_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskDelayUntilImpl \n"
" MPU_xTaskDelayUntil_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory"
@@ -91,12 +90,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskAbortDelay_Unpriv \n"
" MPU_xTaskAbortDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskAbortDelayImpl \n"
" MPU_xTaskAbortDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory"
@@ -120,12 +118,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskDelay_Unpriv \n"
" MPU_vTaskDelay_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskDelayImpl \n"
" MPU_vTaskDelay_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory"
@@ -149,12 +146,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskPriorityGet_Unpriv \n"
" MPU_uxTaskPriorityGet_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskPriorityGetImpl \n"
" MPU_uxTaskPriorityGet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory"
@@ -178,12 +174,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_eTaskGetState_Unpriv \n"
" MPU_eTaskGetState_Priv: \n"
- " pop {r0} \n"
" b MPU_eTaskGetStateImpl \n"
" MPU_eTaskGetState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory"
@@ -213,12 +208,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskGetInfo_Unpriv \n"
" MPU_vTaskGetInfo_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskGetInfoImpl \n"
" MPU_vTaskGetInfo_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory"
@@ -242,12 +236,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetIdleTaskHandle_Unpriv \n"
" MPU_xTaskGetIdleTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetIdleTaskHandleImpl \n"
" MPU_xTaskGetIdleTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory"
@@ -271,12 +264,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSuspend_Unpriv \n"
" MPU_vTaskSuspend_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSuspendImpl \n"
" MPU_vTaskSuspend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory"
@@ -300,12 +292,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskResume_Unpriv \n"
" MPU_vTaskResume_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskResumeImpl \n"
" MPU_vTaskResume_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskResume ) : "memory"
@@ -327,12 +318,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetTickCount_Unpriv \n"
" MPU_xTaskGetTickCount_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetTickCountImpl \n"
" MPU_xTaskGetTickCount_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory"
@@ -352,12 +342,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetNumberOfTasks_Unpriv \n"
" MPU_uxTaskGetNumberOfTasks_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetNumberOfTasksImpl \n"
" MPU_uxTaskGetNumberOfTasks_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory"
@@ -365,31 +354,6 @@
}
/*-----------------------------------------------------------*/
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
-
- char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_pcTaskGetNameImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_pcTaskGetName_Unpriv \n"
- " MPU_pcTaskGetName_Priv: \n"
- " pop {r0} \n"
- " b MPU_pcTaskGetNameImpl \n"
- " MPU_pcTaskGetName_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_pcTaskGetName ) : "memory"
- );
- }
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -404,12 +368,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimeCounterImpl \n"
" MPU_ulTaskGetRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory"
@@ -433,12 +396,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetRunTimePercent_Unpriv \n"
" MPU_ulTaskGetRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetRunTimePercentImpl \n"
" MPU_ulTaskGetRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory"
@@ -462,12 +424,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n"
" MPU_ulTaskGetIdleRunTimePercent_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimePercentImpl \n"
" MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory"
@@ -491,12 +452,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n"
" MPU_ulTaskGetIdleRunTimeCounter_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGetIdleRunTimeCounterImpl \n"
" MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory"
@@ -522,12 +482,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetApplicationTaskTag_Unpriv \n"
" MPU_vTaskSetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetApplicationTaskTagImpl \n"
" MPU_vTaskSetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory"
@@ -551,12 +510,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetApplicationTaskTag_Unpriv \n"
" MPU_xTaskGetApplicationTaskTag_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetApplicationTaskTagImpl \n"
" MPU_xTaskGetApplicationTaskTag_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory"
@@ -584,12 +542,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n"
" MPU_vTaskSetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetThreadLocalStoragePointerImpl \n"
" MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory"
@@ -615,12 +572,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTaskGetThreadLocalStoragePointerImpl \n"
" MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory"
@@ -648,12 +604,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetSystemState_Unpriv \n"
" MPU_uxTaskGetSystemState_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetSystemStateImpl \n"
" MPU_uxTaskGetSystemState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory"
@@ -677,12 +632,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMarkImpl \n"
" MPU_uxTaskGetStackHighWaterMark_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory"
@@ -706,12 +660,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n"
" MPU_uxTaskGetStackHighWaterMark2_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTaskGetStackHighWaterMark2Impl \n"
" MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory"
@@ -735,12 +688,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n"
" MPU_xTaskGetCurrentTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetCurrentTaskHandleImpl \n"
" MPU_xTaskGetCurrentTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory"
@@ -764,12 +716,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGetSchedulerState_Unpriv \n"
" MPU_xTaskGetSchedulerState_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGetSchedulerStateImpl \n"
" MPU_xTaskGetSchedulerState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory"
@@ -791,12 +742,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTaskSetTimeOutState_Unpriv \n"
" MPU_vTaskSetTimeOutState_Priv: \n"
- " pop {r0} \n"
" b MPU_vTaskSetTimeOutStateImpl \n"
" MPU_vTaskSetTimeOutState_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory"
@@ -818,12 +768,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskCheckForTimeOut_Unpriv \n"
" MPU_xTaskCheckForTimeOut_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskCheckForTimeOutImpl \n"
" MPU_xTaskCheckForTimeOut_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory"
@@ -845,12 +794,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotify_Unpriv \n"
" MPU_xTaskGenericNotify_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyImpl \n"
" MPU_xTaskGenericNotify_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory"
@@ -874,12 +822,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyWait_Unpriv \n"
" MPU_xTaskGenericNotifyWait_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyWaitImpl \n"
" MPU_xTaskGenericNotifyWait_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory"
@@ -907,12 +854,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyTake_Unpriv \n"
" MPU_ulTaskGenericNotifyTake_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyTakeImpl \n"
" MPU_ulTaskGenericNotifyTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory"
@@ -938,12 +884,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTaskGenericNotifyStateClear_Unpriv \n"
" MPU_xTaskGenericNotifyStateClear_Priv: \n"
- " pop {r0} \n"
" b MPU_xTaskGenericNotifyStateClearImpl \n"
" MPU_xTaskGenericNotifyStateClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory"
@@ -971,12 +916,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n"
" MPU_ulTaskGenericNotifyValueClear_Priv: \n"
- " pop {r0} \n"
" b MPU_ulTaskGenericNotifyValueClearImpl \n"
" MPU_ulTaskGenericNotifyValueClear_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory"
@@ -1004,12 +948,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGenericSend_Unpriv \n"
" MPU_xQueueGenericSend_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGenericSendImpl \n"
" MPU_xQueueGenericSend_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory"
@@ -1029,12 +972,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueMessagesWaiting_Unpriv \n"
" MPU_uxQueueMessagesWaiting_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueMessagesWaitingImpl \n"
" MPU_uxQueueMessagesWaiting_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory"
@@ -1054,12 +996,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxQueueSpacesAvailable_Unpriv \n"
" MPU_uxQueueSpacesAvailable_Priv: \n"
- " pop {r0} \n"
" b MPU_uxQueueSpacesAvailableImpl \n"
" MPU_uxQueueSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory"
@@ -1083,12 +1024,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueReceive_Unpriv \n"
" MPU_xQueueReceive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueReceiveImpl \n"
" MPU_xQueueReceive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory"
@@ -1112,12 +1052,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueuePeek_Unpriv \n"
" MPU_xQueuePeek_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueuePeekImpl \n"
" MPU_xQueuePeek_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory"
@@ -1139,12 +1078,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSemaphoreTake_Unpriv \n"
" MPU_xQueueSemaphoreTake_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSemaphoreTakeImpl \n"
" MPU_xQueueSemaphoreTake_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory"
@@ -1166,12 +1104,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGetMutexHolder_Unpriv \n"
" MPU_xQueueGetMutexHolder_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGetMutexHolderImpl \n"
" MPU_xQueueGetMutexHolder_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory"
@@ -1197,12 +1134,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueTakeMutexRecursive_Unpriv \n"
" MPU_xQueueTakeMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueTakeMutexRecursiveImpl \n"
" MPU_xQueueTakeMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory"
@@ -1226,12 +1162,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueGiveMutexRecursive_Unpriv \n"
" MPU_xQueueGiveMutexRecursive_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueGiveMutexRecursiveImpl \n"
" MPU_xQueueGiveMutexRecursive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory"
@@ -1257,12 +1192,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueSelectFromSet_Unpriv \n"
" MPU_xQueueSelectFromSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueSelectFromSetImpl \n"
" MPU_xQueueSelectFromSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory"
@@ -1288,12 +1222,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xQueueAddToSet_Unpriv \n"
" MPU_xQueueAddToSet_Priv: \n"
- " pop {r0} \n"
" b MPU_xQueueAddToSetImpl \n"
" MPU_xQueueAddToSet_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory"
@@ -1319,12 +1252,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueAddToRegistry_Unpriv \n"
" MPU_vQueueAddToRegistry_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueAddToRegistryImpl \n"
" MPU_vQueueAddToRegistry_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory"
@@ -1348,12 +1280,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vQueueUnregisterQueue_Unpriv \n"
" MPU_vQueueUnregisterQueue_Priv: \n"
- " pop {r0} \n"
" b MPU_vQueueUnregisterQueueImpl \n"
" MPU_vQueueUnregisterQueue_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory"
@@ -1377,12 +1308,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcQueueGetName_Unpriv \n"
" MPU_pcQueueGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcQueueGetNameImpl \n"
" MPU_pcQueueGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory"
@@ -1406,12 +1336,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pvTimerGetTimerID_Unpriv \n"
" MPU_pvTimerGetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_pvTimerGetTimerIDImpl \n"
" MPU_pvTimerGetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory"
@@ -1437,12 +1366,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetTimerID_Unpriv \n"
" MPU_vTimerSetTimerID_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetTimerIDImpl \n"
" MPU_vTimerSetTimerID_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory"
@@ -1466,12 +1394,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerIsTimerActive_Unpriv \n"
" MPU_xTimerIsTimerActive_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerIsTimerActiveImpl \n"
" MPU_xTimerIsTimerActive_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory"
@@ -1495,12 +1422,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetTimerDaemonTaskHandleImpl \n"
" MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory"
@@ -1512,31 +1438,26 @@
#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
- BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
" .syntax unified \n"
- " .extern MPU_xTimerGenericCommandPrivImpl \n"
+ " .extern MPU_xTimerGenericCommandFromTaskImpl \n"
" \n"
" push {r0} \n"
- " mrs r0, ipsr \n"
- " cmp r0, #0 \n"
- " bne MPU_xTimerGenericCommand_Priv \n"
" mrs r0, control \n"
" tst r0, #1 \n"
- " beq MPU_xTimerGenericCommand_Priv \n"
- " MPU_xTimerGenericCommand_Unpriv: \n"
- " pop {r0} \n"
+ " pop {r0} \n"
+ " bne MPU_xTimerGenericCommandFromTask_Unpriv \n"
+ " MPU_xTimerGenericCommandFromTask_Priv: \n"
+ " b MPU_xTimerGenericCommandFromTaskImpl \n"
+ " MPU_xTimerGenericCommandFromTask_Unpriv: \n"
" svc %0 \n"
- " MPU_xTimerGenericCommand_Priv: \n"
- " pop {r0} \n"
- " b MPU_xTimerGenericCommandPrivImpl \n"
" \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xTimerGenericCommand ) : "memory"
+ : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory"
);
}
@@ -1557,12 +1478,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_pcTimerGetName_Unpriv \n"
" MPU_pcTimerGetName_Priv: \n"
- " pop {r0} \n"
" b MPU_pcTimerGetNameImpl \n"
" MPU_pcTimerGetName_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory"
@@ -1575,10 +1495,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
{
__asm volatile
(
@@ -1588,12 +1508,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vTimerSetReloadMode_Unpriv \n"
" MPU_vTimerSetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_vTimerSetReloadModeImpl \n"
" MPU_vTimerSetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory"
@@ -1617,12 +1536,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetReloadMode_Unpriv \n"
" MPU_xTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetReloadModeImpl \n"
" MPU_xTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory"
@@ -1646,12 +1564,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxTimerGetReloadMode_Unpriv \n"
" MPU_uxTimerGetReloadMode_Priv: \n"
- " pop {r0} \n"
" b MPU_uxTimerGetReloadModeImpl \n"
" MPU_uxTimerGetReloadMode_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory"
@@ -1675,12 +1592,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetPeriod_Unpriv \n"
" MPU_xTimerGetPeriod_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetPeriodImpl \n"
" MPU_xTimerGetPeriod_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory"
@@ -1704,12 +1620,11 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_xTimerGetExpiryTime_Unpriv \n"
" MPU_xTimerGetExpiryTime_Priv: \n"
- " pop {r0} \n"
" b MPU_xTimerGetExpiryTimeImpl \n"
" MPU_xTimerGetExpiryTime_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory"
@@ -1719,117 +1634,129 @@
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupWaitBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupWaitBits_Unpriv \n"
- " MPU_xEventGroupWaitBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupWaitBitsImpl \n"
- " MPU_xEventGroupWaitBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupWaitBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupWaitBits_Unpriv \n"
+ " MPU_xEventGroupWaitBits_Priv: \n"
+ " b MPU_xEventGroupWaitBitsImpl \n"
+ " MPU_xEventGroupWaitBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupClearBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupClearBits_Unpriv \n"
- " MPU_xEventGroupClearBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupClearBitsImpl \n"
- " MPU_xEventGroupClearBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupClearBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupClearBits_Unpriv \n"
+ " MPU_xEventGroupClearBits_Priv: \n"
+ " b MPU_xEventGroupClearBitsImpl \n"
+ " MPU_xEventGroupClearBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSetBitsImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSetBits_Unpriv \n"
- " MPU_xEventGroupSetBits_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSetBitsImpl \n"
- " MPU_xEventGroupSetBits_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSetBitsImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSetBits_Unpriv \n"
+ " MPU_xEventGroupSetBits_Priv: \n"
+ " b MPU_xEventGroupSetBitsImpl \n"
+ " MPU_xEventGroupSetBits_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_EVENT_GROUPS == 1 )
- EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xEventGroupSyncImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xEventGroupSync_Unpriv \n"
- " MPU_xEventGroupSync_Priv: \n"
- " pop {r0} \n"
- " b MPU_xEventGroupSyncImpl \n"
- " MPU_xEventGroupSync_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
- );
- }
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xEventGroupSyncImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xEventGroupSync_Unpriv \n"
+ " MPU_xEventGroupSync_Priv: \n"
+ " b MPU_xEventGroupSyncImpl \n"
+ " MPU_xEventGroupSync_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1843,22 +1770,21 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_uxEventGroupGetNumber_Unpriv \n"
" MPU_uxEventGroupGetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_uxEventGroupGetNumberImpl \n"
" MPU_uxEventGroupGetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- #if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
@@ -1874,233 +1800,256 @@
" push {r0} \n"
" mrs r0, control \n"
" tst r0, #1 \n"
+ " pop {r0} \n"
" bne MPU_vEventGroupSetNumber_Unpriv \n"
" MPU_vEventGroupSetNumber_Priv: \n"
- " pop {r0} \n"
" b MPU_vEventGroupSetNumberImpl \n"
" MPU_vEventGroupSetNumber_Unpriv: \n"
- " pop {r0} \n"
" svc %0 \n"
" \n"
: : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory"
);
}
- #endif /*( configUSE_TRACE_FACILITY == 1 )*/
+ #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSendImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSend_Unpriv \n"
- " MPU_xStreamBufferSend_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSendImpl \n"
- " MPU_xStreamBufferSend_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSendImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSend_Unpriv \n"
+ " MPU_xStreamBufferSend_Priv: \n"
+ " b MPU_xStreamBufferSendImpl \n"
+ " MPU_xStreamBufferSend_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferReceiveImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferReceive_Unpriv \n"
- " MPU_xStreamBufferReceive_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferReceiveImpl \n"
- " MPU_xStreamBufferReceive_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferReceiveImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferReceive_Unpriv \n"
+ " MPU_xStreamBufferReceive_Priv: \n"
+ " b MPU_xStreamBufferReceiveImpl \n"
+ " MPU_xStreamBufferReceive_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsFullImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsFull_Unpriv \n"
- " MPU_xStreamBufferIsFull_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsFullImpl \n"
- " MPU_xStreamBufferIsFull_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsFullImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsFull_Unpriv \n"
+ " MPU_xStreamBufferIsFull_Priv: \n"
+ " b MPU_xStreamBufferIsFullImpl \n"
+ " MPU_xStreamBufferIsFull_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferIsEmptyImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
- " MPU_xStreamBufferIsEmpty_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferIsEmptyImpl \n"
- " MPU_xStreamBufferIsEmpty_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferIsEmptyImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferIsEmpty_Unpriv \n"
+ " MPU_xStreamBufferIsEmpty_Priv: \n"
+ " b MPU_xStreamBufferIsEmptyImpl \n"
+ " MPU_xStreamBufferIsEmpty_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
- " MPU_xStreamBufferSpacesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSpacesAvailableImpl \n"
- " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSpacesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n"
+ " MPU_xStreamBufferSpacesAvailable_Priv: \n"
+ " b MPU_xStreamBufferSpacesAvailableImpl \n"
+ " MPU_xStreamBufferSpacesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferBytesAvailableImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
- " MPU_xStreamBufferBytesAvailable_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferBytesAvailableImpl \n"
- " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferBytesAvailableImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferBytesAvailable_Unpriv \n"
+ " MPU_xStreamBufferBytesAvailable_Priv: \n"
+ " b MPU_xStreamBufferBytesAvailableImpl \n"
+ " MPU_xStreamBufferBytesAvailable_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
- " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferSetTriggerLevelImpl \n"
- " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
- );
- }
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n"
+ " MPU_xStreamBufferSetTriggerLevel_Priv: \n"
+ " b MPU_xStreamBufferSetTriggerLevelImpl \n"
+ " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+ #if ( configUSE_STREAM_BUFFERS == 1 )
- size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
- {
- __asm volatile
- (
- " .syntax unified \n"
- " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " \n"
- " push {r0} \n"
- " mrs r0, control \n"
- " tst r0, #1 \n"
- " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
- " pop {r0} \n"
- " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
- " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
- " pop {r0} \n"
- " svc %0 \n"
- " \n"
- : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
- );
- }
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL;
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */
+ {
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " \n"
+ " push {r0} \n"
+ " mrs r0, control \n"
+ " tst r0, #1 \n"
+ " pop {r0} \n"
+ " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n"
+ " b MPU_xStreamBufferNextMessageLengthBytesImpl \n"
+ " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n"
+ " svc %0 \n"
+ " \n"
+ : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory"
+ );
+ }
+
+ #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
index b3f6a0a..51ec476 100644
--- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -52,23 +54,23 @@
" .syntax unified \n"
" \n"
" program_mpu_first_task: \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -86,18 +88,26 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context_first_task: \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
" restore_special_regs_first_task: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
" msr psp, r2 \n"
" msr psplim, r3 \n"
@@ -113,13 +123,6 @@
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst2: .word pxCurrentTCB \n"
- " xMPUCTRLConst2: .word 0xe000ed94 \n"
- " xMAIR0Const2: .word 0xe000edc0 \n"
- " xRNRConst2: .word 0xe000ed98 \n"
- " xRBARConst2: .word 0xe000ed9c \n"
);
}
@@ -131,23 +134,30 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r2 \n"
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_0, r4 \n"
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
- " movs r1, #2 \n" /* r1 = 2. */
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " mrs r1, control \n" /* Obtain current control register value. */
+ " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+ " msr control, r1 \n" /* Write back the new control register value. */
" adds r0, #32 \n" /* Discard everything up to r0. */
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
" isb \n"
" mov r0, #0 \n"
" msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
" bx r2 \n" /* Finally, branch to EXC_RETURN. */
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
@@ -166,8 +176,6 @@
" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
" bx lr \n" /* Return. */
- " \n"
- " .align 4 \n"
::: "r0", "memory"
);
}
@@ -209,7 +217,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
@@ -219,9 +227,6 @@
" isb \n"
" svc %0 \n" /* System call to start the first task. */
" nop \n"
- " \n"
- " .align 4 \n"
- "xVTORConst: .word 0xe000ed08 \n"
::"i" ( portSVC_START_SCHEDULER ) : "memory"
);
}
@@ -235,7 +240,7 @@
" \n"
" mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bx lr \n" /* Return. */
@@ -267,7 +272,7 @@
(
" .syntax unified \n"
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
" mrs r2, psp \n" /* r2 = PSP. */
@@ -282,7 +287,6 @@
" vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
" sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- " \n"
" stmia r1!, {r4-r11} \n" /* Store r4-r11. */
" ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
" stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */
@@ -291,11 +295,19 @@
" mrs r3, psplim \n" /* r3 = PSPLIM. */
" mrs r4, control \n" /* r4 = CONTROL. */
" stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_2 \n"
+ " mrs r5, PAC_KEY_P_3 \n"
+ " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
" \n"
" select_next_task: \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
@@ -303,23 +315,23 @@
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
" program_mpu: \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
" \n"
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
" str r2, [r1] \n" /* Disable MPU. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
" str r1, [r2] \n" /* Program MAIR0. */
" \n"
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
- " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+ " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
" \n"
" movs r3, #4 \n" /* r3 = 4. */
" str r3, [r1] \n" /* Program RNR = 4. */
@@ -337,18 +349,26 @@
" stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
" \n"
- " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
" orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
" str r2, [r1] \n" /* Enable MPU. */
" dsb \n" /* Force memory writes before continuing. */
" \n"
" restore_context: \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
" \n"
" restore_special_regs: \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
+ " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_1, r3 \n"
+ " msr PAC_KEY_P_2, r4 \n"
+ " msr PAC_KEY_P_3, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
" ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
" msr psp, r2 \n"
" msr psplim, r3 \n"
@@ -369,13 +389,6 @@
" restore_context_done: \n"
" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
" bx lr \n"
- " \n"
- " .align 4 \n"
- " pxCurrentTCBConst: .word pxCurrentTCB \n"
- " xMPUCTRLConst: .word 0xe000ed94 \n"
- " xMAIR0Const: .word 0xe000edc0 \n"
- " xRNRConst: .word 0xe000ed98 \n"
- " xRBARConst: .word 0xe000ed9c \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -400,22 +413,40 @@
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
" stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ #if ( configENABLE_PAC == 1 )
+ " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
+ " mrs r2, PAC_KEY_P_2 \n"
+ " mrs r3, PAC_KEY_P_1 \n"
+ " mrs r4, PAC_KEY_P_0 \n"
+ " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */
+ " clrm {r1-r4} \n" /* Clear r1-r4. */
+ #endif /* configENABLE_PAC */
+ " \n"
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" str r0, [r1] \n" /* Save the new top of stack in TCB. */
" \n"
" mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
- " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" dsb \n"
" isb \n"
" bl vTaskSwitchContext \n"
" mov r0, #0 \n" /* r0 = 0. */
" msr basepri, r0 \n" /* Enable interrupts. */
" \n"
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
" \n"
+ #if ( configENABLE_PAC == 1 )
+ " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */
+ " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+ " msr PAC_KEY_P_2, r3 \n"
+ " msr PAC_KEY_P_1, r4 \n"
+ " msr PAC_KEY_P_0, r5 \n"
+ " clrm {r2-r5} \n" /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+ " \n"
" ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
" \n"
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -427,9 +458,6 @@
" msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
" msr psp, r0 \n" /* Remember the new top of stack for the task. */
" bx r3 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
@@ -487,11 +515,8 @@
" ite eq \n"
" mrseq r0, msp \n"
" mrsne r0, psp \n"
- " ldr r1, svchandler_address_const \n"
+ " ldr r1, =vPortSVCHandler_C \n"
" bx r1 \n"
- " \n"
- " .align 4 \n"
- "svchandler_address_const: .word vPortSVCHandler_C \n"
);
}
diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
index f606f81..3386f52 100644
--- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M85"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* *INDENT-OFF* */
diff --git a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CA9/port.c b/Source/portable/IAR/ARM_CA9/port.c
index b9126a9..9940833 100644
--- a/Source/portable/IAR/ARM_CA9/port.c
+++ b/Source/portable/IAR/ARM_CA9/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -37,43 +37,43 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #if ( configMAX_PRIORITIES > 32 )
+ #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
#endif
#ifndef configCLEAR_TICK_INTERRUPT
@@ -81,45 +81,45 @@
#endif
/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created. A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+ * floating point context after they have been created. A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+ * point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
-{ \
- __disable_irq(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm( "DSB \n" \
- "ISB \n" ); \
- __enable_irq(); \
-}
+#define portCLEAR_INTERRUPT_MASK() \
+ { \
+ __disable_irq(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm( "DSB \n" \
+ "ISB \n" ); \
+ __enable_irq(); \
+ }
/*-----------------------------------------------------------*/
@@ -137,21 +137,21 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts. As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts. As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero
-then a floating point context must be saved and restored for the task. */
+ * then a floating point context must be saved and restored for the task. */
uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
uint32_t ulPortInterruptNesting = 0UL;
@@ -160,14 +160,16 @@
/*
* See header file for description.
*/
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro.
-
- The fist real value on the stack is the status register, which is set for
- system mode, with interrupts enabled. A few NULLs are added first to ensure
- GDB does not try decoding a non-existent return address. */
+ * expected by the portRESTORE_CONTEXT() macro.
+ *
+ * The fist real value on the stack is the status register, which is set for
+ * system mode, with interrupts enabled. A few NULLs are added first to ensure
+ * GDB does not try decoding a non-existent return address. */
*pxTopOfStack = NULL;
pxTopOfStack--;
*pxTopOfStack = NULL;
@@ -189,43 +191,43 @@
pxTopOfStack--;
/* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
- enabled. */
+ * enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
pxTopOfStack--;
/* The task will start without a floating point context. A task that uses
- the floating point hardware must call vPortTaskUsesFPU() before executing
- any floating point instructions. */
+ * the floating point hardware must call vPortTaskUsesFPU() before executing
+ * any floating point instructions. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
return pxTopOfStack;
@@ -235,32 +237,36 @@
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
- its caller as there is nothing to return to. If a task wants to exit it
- should instead call vTaskDelete( NULL ).
-
- Artificially force an assert() to be triggered if configASSERT() is
- defined, then stop here so application writers can catch the error. */
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
configASSERT( ulPortInterruptNesting == ~0UL );
portDISABLE_INTERRUPTS();
- for( ;; );
+
+ for( ; ; )
+ {
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
-uint32_t ulAPSR;
+ uint32_t ulAPSR;
/* Only continue if the CPU is not in User mode. The CPU must be in a
- Privileged mode for the scheduler to start. */
+ * Privileged mode for the scheduler to start. */
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+
ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE );
if( ulAPSR != portAPSR_USER_MODE )
{
/* Only continue if the binary point value is set to its lowest possible
- setting. See the comments in vPortValidateInterruptPriority() below for
- more information. */
+ * setting. See the comments in vPortValidateInterruptPriority() below for
+ * more information. */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
@@ -274,8 +280,8 @@
}
/* Will only get here if vTaskStartScheduler() was called with the CPU in
- a non-privileged mode or the binary point register was not set to its lowest
- possible value. */
+ * a non-privileged mode or the binary point register was not set to its lowest
+ * possible value. */
return 0;
}
/*-----------------------------------------------------------*/
@@ -283,7 +289,7 @@
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
+ * Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@@ -293,16 +299,16 @@
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
ulPortSetInterruptMask();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
+ /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+ * directly. Increment ulCriticalNesting to keep a count of how many times
+ * portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
- assert() if it is being called from an interrupt context. Only API
- functions that end in "FromISR" can be used in an interrupt. Only assert if
- the critical nesting count is 1 to protect against recursive calls if the
- assert function also uses a critical section. */
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
if( ulCriticalNesting == 1 )
{
configASSERT( ulPortInterruptNesting == 0 );
@@ -315,15 +321,15 @@
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
- exited. */
+ * exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
+ * priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
+ * should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@@ -333,12 +339,12 @@
void FreeRTOS_Tick_Handler( void )
{
/* Set interrupt mask before altering scheduler structures. The tick
- handler runs at the lowest priority, so interrupts cannot already be masked,
- so there is no need to save and restore the current mask value. */
+ * handler runs at the lowest priority, so interrupts cannot already be masked,
+ * so there is no need to save and restore the current mask value. */
__disable_irq();
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n" );
+ __asm( "DSB \n"
+ "ISB \n" );
__enable_irq();
/* Increment the RTOS tick. */
@@ -355,14 +361,14 @@
void vPortTaskUsesFPU( void )
{
-uint32_t ulInitialFPSCR = 0;
+ uint32_t ulInitialFPSCR = 0;
/* A task is registering the fact that it needs an FPU context. Set the
- FPU flag (which is saved as part of the task context). */
+ * FPU flag (which is saved as part of the task context). */
ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */
- __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
+ __asm( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) );
}
/*-----------------------------------------------------------*/
@@ -377,9 +383,10 @@
uint32_t ulPortSetInterruptMask( void )
{
-uint32_t ulReturn;
+ uint32_t ulReturn;
__disable_irq();
+
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@@ -389,49 +396,50 @@
{
ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n" );
+ __asm( "DSB \n"
+ "ISB \n" );
}
+
__enable_irq();
return ulReturn;
}
/*-----------------------------------------------------------*/
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
- an interrupt that has been assigned a priority above
- configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- function. ISR safe FreeRTOS API functions must *only* be called
- from interrupts that have been assigned a priority at or below
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- Numerically low interrupt priority numbers represent logically high
- interrupt priorities, therefore the priority of the interrupt must
- be set to a value equal to or numerically *higher* than
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- FreeRTOS maintains separate thread and ISR API functions to ensure
- interrupt entry is as fast and simple as possible.
-
- The following links provide detailed information:
- https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- https://www.FreeRTOS.org/FAQHelp.html */
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
- that define each interrupt's priority to be split between bits that
- define the interrupt's pre-emption priority bits and bits that define
- the interrupt's sub-priority. For simplicity all bits must be defined
- to be pre-emption priority bits. The following assertion will fail if
- this is not the case (if some bits represent a sub-priority).
-
- The priority grouping is configured by the GIC's binary point register
- (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- possible value (which may be above 0). */
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * The priority grouping is configured by the GIC's binary point register
+ * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
+ * possible value (which may be above 0). */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
}
diff --git a/Source/portable/IAR/ARM_CA9/portASM.h b/Source/portable/IAR/ARM_CA9/portASM.h
index 31229b7..2855a0c 100644
--- a/Source/portable/IAR/ARM_CA9/portASM.h
+++ b/Source/portable/IAR/ARM_CA9/portASM.h
@@ -1,6 +1,6 @@
;/*
-; * FreeRTOS Kernel V10.6.2
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; * FreeRTOS Kernel V11.2.0
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
diff --git a/Source/portable/IAR/ARM_CA9/portASM.s b/Source/portable/IAR/ARM_CA9/portASM.s
index e9c87c6..ebb86e9 100644
--- a/Source/portable/IAR/ARM_CA9/portASM.s
+++ b/Source/portable/IAR/ARM_CA9/portASM.s
@@ -1,6 +1,6 @@
;/*
-; * FreeRTOS Kernel V10.6.2
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; * FreeRTOS Kernel V11.2.0
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
diff --git a/Source/portable/IAR/ARM_CA9/portmacro.h b/Source/portable/IAR/ARM_CA9/portmacro.h
index 244fd41..f218e60 100644
--- a/Source/portable/IAR/ARM_CA9/portmacro.h
+++ b/Source/portable/IAR/ARM_CA9/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -40,127 +40,127 @@
#include <intrinsics.h>
- /*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
- /* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+/* Type definitions. */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
- /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
- /* Hardware specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+/* Hardware specifics. */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
- /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
- /* Task utilities. */
+/* Task utilities. */
- /* Called at the end of an ISR that can cause a context switch. */
- #define portEND_SWITCHING_ISR( xSwitchRequired )\
- { \
- extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
+/* Called at the end of an ISR that can cause a context switch. */
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ { \
+ extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
}
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
- #define portYIELD() __asm( "SWI 0" );
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+ #define portYIELD() __asm( "SWI 0" );
- /*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+/*-----------------------------------------------------------
+* Critical section control
+*----------------------------------------------------------*/
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
extern uint32_t ulPortSetInterruptMask( void );
extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
- /* These macros do not globally disable/enable interrupts. They do mask off
- interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
- #define portENTER_CRITICAL() vPortEnterCritical();
- #define portEXIT_CRITICAL() vPortExitCritical();
- #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
- #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+/* These macros do not globally disable/enable interrupts. They do mask off
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+ #define portENTER_CRITICAL() vPortEnterCritical();
+ #define portEXIT_CRITICAL() vPortExitCritical();
+ #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+ #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
- /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
- /* Task function macros as described on the FreeRTOS.org WEB site. These are
- not required for this port but included in case common demo code that uses these
- macros is used. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
- /* Prototype of the FreeRTOS tick handler. This must be installed as the
- handler for whichever peripheral is used to generate the RTOS tick. */
+/* Prototype of the FreeRTOS tick handler. This must be installed as the
+ * handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
- /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
- before any floating point instructions are executed. */
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+ * before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
- #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
- #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
- #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+ #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+ #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
- /* Architecture specific optimisations. */
+/* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
- /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
- #ifdef configASSERT
+ #if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif /* configASSERT */
- #define portNOP() __asm volatile( "NOP" )
+ #define portNOP() __asm volatile ( "NOP" )
- /* Suppress warnings that are generated by the IAR tools, but cannot be
- fixed in the source code because to do so would cause other compilers to
- generate warnings. */
+/* Suppress warnings that are generated by the IAR tools, but cannot be
+ * fixed in the source code because to do so would cause other compilers to
+ * generate warnings. */
#pragma diag_suppress=Pe191
#pragma diag_suppress=Pa082
@@ -168,40 +168,40 @@
/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
-#else
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM0/port.c b/Source/portable/IAR/ARM_CM0/port.c
index b9999a0..6f7c899 100644
--- a/Source/portable/IAR/ARM_CM0/port.c
+++ b/Source/portable/IAR/ARM_CM0/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -37,6 +37,9 @@
#include "FreeRTOS.h"
#include "task.h"
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the NVIC. */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -53,6 +56,10 @@
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000 )
@@ -121,6 +128,10 @@
*/
static void prvTaskExitError( void );
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void xPortPendSVHandler( void );
/*-----------------------------------------------------------*/
/*
@@ -168,6 +179,41 @@
*/
BaseType_t xPortStartScheduler( void )
{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV
+ * interrupt.
+ * 2. Indirect Routing - Install separate handler for PendSV interrupt and
+ * route program control from that handler to xPortPendSVHandler function.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ /* Point pxVectorTable to the interrupt vector table. Systems without
+ * a VTOR register provide the value zero in the VTOR register and
+ * the vector table itself is located at the address 0x00000000. */
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handler for PendSV interrupt. We do not check the installation of the
+ * SysTick handler because the application may choose to drive the RTOS
+ * tick using a timer other than the SysTick timer by overriding the
+ * weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handler. For help installing the FreeRTOS handler, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
@@ -233,13 +279,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
diff --git a/Source/portable/IAR/ARM_CM0/portasm.s b/Source/portable/IAR/ARM_CM0/portasm.s
index 8b5caf2..bc33363 100644
--- a/Source/portable/IAR/ARM_CM0/portasm.s
+++ b/Source/portable/IAR/ARM_CM0/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -91,15 +91,15 @@
vPortSVCHandler;
/* This function is no longer used, but retained for backward
- compatibility. */
+ * compatibility. */
bx lr
/*-----------------------------------------------------------*/
vPortStartFirstTask
- /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
- table offset register that can be used to locate the initial stack value.
- Not all M0 parts have the application vector table at address 0. */
+ /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table
+ * in some CM0 devices cannot be modified and thus may not hold the
+ * application's initial MSP value. */
ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
ldr r1, [r3]
diff --git a/Source/portable/IAR/ARM_CM0/portmacro.h b/Source/portable/IAR/ARM_CM0/portmacro.h
index e0ccf6b..e384e59 100644
--- a/Source/portable/IAR/ARM_CM0/portmacro.h
+++ b/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -86,9 +86,21 @@
extern void vPortYield( void );
#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
#define portNVIC_PENDSVSET 0x10000000
-#define portYIELD() vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
index 4d805f3..eaafcee 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,12 +48,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0, r1}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -63,12 +62,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0, r1}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -78,12 +76,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0, r1}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -93,12 +90,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0, r1}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -108,12 +104,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0, r1}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -123,12 +118,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0, r1}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -138,12 +132,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0, r1}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -153,12 +146,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0, r1}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -168,12 +160,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0, r1}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -183,12 +174,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0, r1}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -198,42 +188,25 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0, r1}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0, r1}
- mrs r0, control
- movs r1, #1
- tst r0, r1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0, r1}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0, r1}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0, r1}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0, r1}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -258,12 +230,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0, r1}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -273,12 +244,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0, r1}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -288,12 +258,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0, r1}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -303,12 +272,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0, r1}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -318,12 +286,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0, r1}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -333,12 +300,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0, r1}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -348,12 +314,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0, r1}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -363,12 +328,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -378,12 +342,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -393,12 +356,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0, r1}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -408,12 +370,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0, r1}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -423,12 +384,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0, r1}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -438,12 +398,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0, r1}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -453,12 +412,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0, r1}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -468,12 +426,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0, r1}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -483,12 +440,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0, r1}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -498,12 +454,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0, r1}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -513,12 +468,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0, r1}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -528,12 +482,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0, r1}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -543,12 +496,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0, r1}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -558,12 +510,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0, r1}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -573,12 +524,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0, r1}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -588,12 +538,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0, r1}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -603,12 +552,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0, r1}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -618,12 +566,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0, r1}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -633,12 +580,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0, r1}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -648,12 +594,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0, r1}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -663,12 +608,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0, r1}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -678,12 +622,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0, r1}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -693,12 +636,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0, r1}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -708,12 +650,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0, r1}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -723,12 +664,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0, r1}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -738,12 +678,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0, r1}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -753,12 +692,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0, r1}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -768,12 +706,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0, r1}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -783,34 +720,26 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0, r1}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0, r1}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
movs r1, #1
tst r0, r1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0, r1}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0, r1}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0, r1}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -819,12 +748,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0, r1}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -834,12 +762,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0, r1}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -849,12 +776,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0, r1}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -864,12 +790,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0, r1}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -879,12 +804,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0, r1}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -894,12 +818,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0, r1}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -909,12 +832,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0, r1}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -924,12 +846,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0, r1}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -939,12 +860,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0, r1}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -954,12 +874,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0, r1}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -969,12 +888,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0, r1}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -984,12 +902,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0, r1}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -999,12 +916,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0, r1}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -1014,12 +930,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0, r1}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -1029,12 +944,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0, r1}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -1044,12 +958,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0, r1}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -1059,12 +972,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0, r1}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1074,12 +986,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0, r1}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1089,12 +1000,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0, r1}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1104,12 +1014,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0, r1}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1160,10 +1069,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1316,9 +1221,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/port.c b/Source/portable/IAR/ARM_CM23/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
index 3c17889..6b25588 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -40,6 +40,7 @@
#define configUSE_MPU_WRAPPERS_V1 0
#endif
+
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
@@ -169,7 +170,6 @@
ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
subs r2, #20
msr psp, r3
- msr psplim, r4
msr control, r5
mov lr, r6
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -205,7 +205,6 @@
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
- msr psplim, r2 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
@@ -281,7 +280,7 @@
save_special_regs:
mrs r3, psp /* r3 = PSP. */
- mrs r4, psplim /* r4 = PSPLIM. */
+ movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */
mrs r5, control /* r5 = CONTROL. */
mov r6, lr /* r6 = LR. */
stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -349,7 +348,6 @@
ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
subs r2, #20
msr psp, r3
- msr psplim, r4
msr control, r5
mov lr, r6
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -408,7 +406,7 @@
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
- mrs r1, psplim /* r1 = PSPLIM. */
+ movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
@@ -419,7 +417,7 @@
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
- mrs r1, psplim /* r1 = PSPLIM. */
+ movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
mov r4, r8 /* r4 = r8. */
@@ -438,7 +436,6 @@
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- msr psplim, r1 /* Restore the PSPLIM register value for the task. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
index 19d7556..6cf50c5 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,9 +48,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portHAS_BASEPRI 0
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION 0
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
+
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
/*-----------------------------------------------------------*/
/**
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/Source/portable/IAR/ARM_CM23/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_context.c
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/Source/portable/IAR/ARM_CM23/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_context.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
index 1e4b3a5..e3ff975 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/Source/portable/IAR/ARM_CM23/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_init.c
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/Source/portable/IAR/ARM_CM23/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_init.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
index 4d805f3..eaafcee 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,12 +48,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0, r1}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -63,12 +62,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0, r1}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -78,12 +76,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0, r1}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -93,12 +90,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0, r1}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -108,12 +104,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0, r1}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -123,12 +118,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0, r1}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -138,12 +132,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0, r1}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -153,12 +146,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0, r1}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -168,12 +160,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0, r1}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -183,12 +174,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0, r1}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -198,42 +188,25 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0, r1}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0, r1}
- mrs r0, control
- movs r1, #1
- tst r0, r1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0, r1}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0, r1}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0, r1}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0, r1}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -258,12 +230,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0, r1}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -273,12 +244,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0, r1}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -288,12 +258,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0, r1}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -303,12 +272,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0, r1}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -318,12 +286,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0, r1}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -333,12 +300,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0, r1}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -348,12 +314,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0, r1}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -363,12 +328,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -378,12 +342,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -393,12 +356,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0, r1}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -408,12 +370,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0, r1}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -423,12 +384,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0, r1}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -438,12 +398,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0, r1}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -453,12 +412,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0, r1}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -468,12 +426,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0, r1}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -483,12 +440,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0, r1}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -498,12 +454,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0, r1}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -513,12 +468,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0, r1}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -528,12 +482,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0, r1}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -543,12 +496,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0, r1}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -558,12 +510,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0, r1}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -573,12 +524,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0, r1}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -588,12 +538,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0, r1}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -603,12 +552,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0, r1}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -618,12 +566,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0, r1}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -633,12 +580,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0, r1}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -648,12 +594,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0, r1}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -663,12 +608,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0, r1}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -678,12 +622,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0, r1}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -693,12 +636,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0, r1}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -708,12 +650,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0, r1}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -723,12 +664,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0, r1}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -738,12 +678,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0, r1}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -753,12 +692,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0, r1}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -768,12 +706,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0, r1}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -783,34 +720,26 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0, r1}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0, r1}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
movs r1, #1
tst r0, r1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0, r1}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0, r1}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0, r1}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -819,12 +748,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0, r1}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -834,12 +762,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0, r1}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -849,12 +776,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0, r1}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -864,12 +790,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0, r1}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -879,12 +804,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0, r1}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -894,12 +818,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0, r1}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -909,12 +832,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0, r1}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -924,12 +846,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0, r1}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -939,12 +860,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0, r1}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -954,12 +874,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0, r1}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -969,12 +888,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0, r1}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -984,12 +902,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0, r1}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -999,12 +916,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0, r1}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -1014,12 +930,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0, r1}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -1029,12 +944,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0, r1}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -1044,12 +958,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0, r1}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -1059,12 +972,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0, r1}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1074,12 +986,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0, r1}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1089,12 +1000,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0, r1}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1104,12 +1014,11 @@
mrs r0, control
movs r1, #1
tst r0, r1
+ pop {r0, r1}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0, r1}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1160,10 +1069,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1316,9 +1221,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
index cef6b8a..200751b 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -39,6 +39,10 @@
#define configUSE_MPU_WRAPPERS_V1 0
#endif
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+ #define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
@@ -159,7 +163,9 @@
ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
subs r1, #16
msr psp, r2
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r3
+ #endif
msr control, r4
mov lr, r5
@@ -191,7 +197,9 @@
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r1 /* Set this task's PSPLIM value. */
+#endif
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
@@ -255,7 +263,11 @@
save_special_regs:
mrs r2, psp /* r2 = PSP. */
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
mrs r3, psplim /* r3 = PSPLIM. */
+ #else
+ movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */
+ #endif
mrs r4, control /* r4 = CONTROL. */
mov r5, lr /* r5 = LR. */
stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -323,7 +335,9 @@
ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
subs r1, #16
msr psp, r2
+ #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r3
+ #endif
msr control, r4
mov lr, r5
@@ -356,7 +370,11 @@
subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */
str r0, [r1] /* Save the new top of stack in TCB. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
mrs r2, psplim /* r2 = PSPLIM. */
+#else
+ movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */
+#endif
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
mov r4, r8 /* r4 = r8. */
@@ -382,7 +400,9 @@
msr psp, r0 /* Remember the new top of stack for the task. */
subs r0, r0, #40 /* Move to the starting of the saved context. */
ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+#endif
bx r3
#endif /* configENABLE_MPU */
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 19d7556..6cf50c5 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,9 +48,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M23"
-#define portHAS_BASEPRI 0
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION 0
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
#if ( configTOTAL_MPU_REGIONS == 16 )
#error 16 MPU regions are not yet supported for this port.
#endif
+
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
/*-----------------------------------------------------------*/
/**
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM3/port.c b/Source/portable/IAR/ARM_CM3/port.c
index 10ce863..e706a6d 100644
--- a/Source/portable/IAR/ARM_CM3/port.c
+++ b/Source/portable/IAR/ARM_CM3/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -41,10 +41,14 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
@@ -59,6 +63,11 @@
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -121,6 +130,11 @@
*/
static void prvTaskExitError( void );
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void );
+extern void xPortPendSVHandler( void );
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
@@ -208,6 +222,40 @@
*/
BaseType_t xPortStartScheduler( void )
{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -243,7 +291,7 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@@ -257,22 +305,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -292,9 +340,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the lowest priority interrupts. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
@@ -355,14 +405,21 @@
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portENABLE_INTERRUPTS();
}
@@ -652,7 +709,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/IAR/ARM_CM3/portasm.s b/Source/portable/IAR/ARM_CM3/portasm.s
index dfaabc3..0344b9c 100644
--- a/Source/portable/IAR/ARM_CM3/portasm.s
+++ b/Source/portable/IAR/ARM_CM3/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM3/portmacro.h b/Source/portable/IAR/ARM_CM3/portmacro.h
index 3e67345..26b976a 100644
--- a/Source/portable/IAR/ARM_CM3/portmacro.h
+++ b/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -47,50 +47,50 @@
*/
/* IAR includes. */
- #include <intrinsics.h>
+#include <intrinsics.h>
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Compiler directives. */
- #define portWEAK_SYMBOL __attribute__( ( weak ) )
+#define portWEAK_SYMBOL __attribute__( ( weak ) )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -98,112 +98,124 @@
__ISB(); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() \
+#define portDISABLE_INTERRUPTS() \
{ \
__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
__DSB(); \
__ISB(); \
}
- #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
+#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
/*-----------------------------------------------------------*/
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
}
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Pe191
- #pragma diag_suppress=Pa082
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
index ef180bd..68192e4 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,12 +47,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -61,12 +60,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -75,12 +73,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -89,12 +86,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -103,12 +99,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -117,12 +112,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -131,12 +125,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -145,12 +138,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -159,12 +151,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -173,12 +164,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -187,40 +177,24 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -229,12 +203,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -257,12 +229,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -271,12 +242,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -285,12 +255,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -299,12 +268,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -313,12 +281,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -327,12 +294,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -341,12 +307,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -355,12 +320,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -369,12 +333,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -383,12 +346,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -397,12 +359,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -411,12 +372,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -425,12 +385,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -439,12 +398,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -453,12 +411,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -467,12 +424,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -481,12 +437,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -495,12 +450,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -509,12 +463,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -523,12 +476,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -537,12 +489,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -551,12 +502,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -565,12 +515,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -579,12 +528,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -593,12 +541,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -607,12 +554,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -621,12 +567,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -635,12 +580,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -649,12 +593,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -663,12 +606,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -677,12 +619,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -691,12 +632,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -705,12 +645,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -719,12 +658,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -733,33 +671,25 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -767,12 +697,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -781,12 +710,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -795,12 +723,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -809,12 +736,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -823,12 +749,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -837,12 +762,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -851,12 +775,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -865,12 +788,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -879,12 +801,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -893,12 +814,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -907,12 +827,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -921,12 +840,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -935,12 +853,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -949,12 +866,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -963,12 +879,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -977,12 +892,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -991,12 +905,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1005,12 +918,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1019,12 +931,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1033,12 +944,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1089,10 +999,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1245,9 +1151,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/port.c b/Source/portable/IAR/ARM_CM33/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
index 5309103..b5c91e5 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -150,6 +152,14 @@
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
@@ -175,12 +185,22 @@
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
- movs r1, #2 /* r1 = 2. */
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
@@ -213,7 +233,7 @@
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
@@ -268,11 +288,20 @@
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
- str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_1
+ mrs r5, PAC_KEY_P_2
+ mrs r6, PAC_KEY_P_3
+ stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -326,6 +355,14 @@
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
@@ -371,76 +408,86 @@
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
- push {r0-r2, r14}
- bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- pop {r0-r3} /* LR is now in r3. */
- mov lr, r3 /* LR = r3. */
- lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
- subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
- str r2, [r1] /* Save the new top of stack in TCB. */
- mrs r1, psplim /* r1 = PSPLIM. */
- mov r3, lr /* r3 = LR/EXC_RETURN. */
- stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
- b select_next_task
+ save_s_context:
+ push {r0-r2, lr}
+ bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ pop {r0-r2, lr}
save_ns_context:
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
+ mov r3, lr /* r3 = LR. */
+ lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+ save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- str r2, [r1] /* Save the new top of stack in TCB. */
- adds r2, r2, #12 /* r2 = r2 + 12. */
- stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
- mrs r1, psplim /* r1 = PSPLIM. */
- mov r3, lr /* r3 = LR/EXC_RETURN. */
- subs r2, r2, #12 /* r2 = r2 - 12. */
- stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */
+
+ save_special_regs:
+ mrs r3, psplim /* r3 = PSPLIM. */
+ stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_1
+ mrs r6, PAC_KEY_P_0
+ stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the new top of stack in TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
+ restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- msr psplim, r1 /* Restore the PSPLIM register value for the task. */
- mov lr, r4 /* LR = r4. */
+ restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_1, r5
+ msr PAC_KEY_P_0, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ ldmia r2!, {r0, r3, lr} /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ msr psplim, r3 /* Restore the PSPLIM register value for the task. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
- push {r2, r4}
+
+ restore_s_context:
+ push {r1-r3, lr}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- pop {r2, r4}
- mov lr, r4 /* LR = r4. */
- lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- msr psp, r2 /* Remember the new top of stack for the task. */
- bx lr
+ pop {r1-r3, lr}
restore_ns_context:
+ mov r0, lr /* r0 = LR (EXC_RETURN). */
+ lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+ restore_general_regs:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
+
+ restore_context_done:
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
index 4eb1c72..df7888d 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,20 +48,28 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M33"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/Source/portable/IAR/ARM_CM33/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_context.c
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/Source/portable/IAR/ARM_CM33/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_context.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
index 0da3e0f..5cc070e 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/Source/portable/IAR/ARM_CM33/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_init.c
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/Source/portable/IAR/ARM_CM33/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_init.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
index ef180bd..68192e4 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,12 +47,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -61,12 +60,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -75,12 +73,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -89,12 +86,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -103,12 +99,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -117,12 +112,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -131,12 +125,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -145,12 +138,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -159,12 +151,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -173,12 +164,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -187,40 +177,24 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -229,12 +203,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -257,12 +229,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -271,12 +242,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -285,12 +255,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -299,12 +268,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -313,12 +281,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -327,12 +294,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -341,12 +307,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -355,12 +320,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -369,12 +333,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -383,12 +346,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -397,12 +359,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -411,12 +372,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -425,12 +385,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -439,12 +398,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -453,12 +411,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -467,12 +424,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -481,12 +437,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -495,12 +450,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -509,12 +463,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -523,12 +476,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -537,12 +489,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -551,12 +502,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -565,12 +515,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -579,12 +528,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -593,12 +541,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -607,12 +554,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -621,12 +567,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -635,12 +580,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -649,12 +593,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -663,12 +606,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -677,12 +619,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -691,12 +632,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -705,12 +645,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -719,12 +658,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -733,33 +671,25 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -767,12 +697,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -781,12 +710,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -795,12 +723,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -809,12 +736,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -823,12 +749,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -837,12 +762,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -851,12 +775,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -865,12 +788,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -879,12 +801,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -893,12 +814,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -907,12 +827,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -921,12 +840,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -935,12 +853,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -949,12 +866,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -963,12 +879,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -977,12 +892,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -991,12 +905,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1005,12 +918,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1019,12 +931,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1033,12 +944,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1089,10 +999,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1245,9 +1151,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
index 00ee5a5..8092255 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -140,6 +142,14 @@
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
@@ -163,10 +173,20 @@
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
- movs r1, #2 /* r1 = 2. */
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
@@ -199,7 +219,7 @@
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
@@ -230,7 +250,6 @@
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
-
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
@@ -239,11 +258,20 @@
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_3
+ stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -297,6 +325,14 @@
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
@@ -332,12 +368,21 @@
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#if ( configENABLE_PAC == 1 )
+ mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r2, PAC_KEY_P_2
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_0
+ stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -348,6 +393,15 @@
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r3
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_0, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index 4eb1c72..df7888d 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -48,20 +48,28 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M33"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 0
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
#include "portmacrocommon.h"
/*-----------------------------------------------------------*/
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#elif ( configENABLE_MVE != 0 )
+ #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM4F/port.c b/Source/portable/IAR/ARM_CM4F/port.c
index 692400b..a863cac 100644
--- a/Source/portable/IAR/ARM_CM4F/port.c
+++ b/Source/portable/IAR/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -45,10 +45,14 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
@@ -69,6 +73,11 @@
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -141,6 +150,11 @@
*/
static void prvTaskExitError( void );
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void );
+extern void xPortPendSVHandler( void );
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
@@ -246,6 +260,40 @@
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -281,7 +329,7 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@@ -295,22 +343,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -330,9 +378,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the lowest priority interrupts. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
@@ -399,14 +449,21 @@
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portENABLE_INTERRUPTS();
}
@@ -696,7 +753,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/IAR/ARM_CM4F/portasm.s b/Source/portable/IAR/ARM_CM4F/portasm.s
index 89b72b2..627b1bf 100644
--- a/Source/portable/IAR/ARM_CM4F/portasm.s
+++ b/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM4F/portmacro.h b/Source/portable/IAR/ARM_CM4F/portmacro.h
index 92cb7c7..2bc2281 100644
--- a/Source/portable/IAR/ARM_CM4F/portmacro.h
+++ b/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -46,50 +46,50 @@
*/
/* IAR includes. */
- #include <intrinsics.h>
+#include <intrinsics.h>
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Compiler directives. */
- #define portWEAK_SYMBOL __attribute__( ( weak ) )
+#define portWEAK_SYMBOL __attribute__( ( weak ) )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,112 +97,124 @@
__ISB(); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() \
+#define portDISABLE_INTERRUPTS() \
{ \
__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
__DSB(); \
__ISB(); \
}
- #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
+#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
/*-----------------------------------------------------------*/
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
}
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Pe191
- #pragma diag_suppress=Pa082
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S
index 276a1cf..310636b 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -51,12 +51,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -65,12 +64,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -79,12 +77,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -93,12 +90,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -107,12 +103,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -121,12 +116,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -135,12 +129,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -149,12 +142,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -163,12 +155,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -177,12 +168,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -191,40 +181,24 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -233,12 +207,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -247,12 +220,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -261,12 +233,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -275,12 +246,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -289,12 +259,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -303,12 +272,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -317,12 +285,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -331,12 +298,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -345,12 +311,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -359,12 +324,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -373,12 +337,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -387,12 +350,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -401,12 +363,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -415,12 +376,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -429,12 +389,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -443,12 +402,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -457,12 +415,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -471,12 +428,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -485,12 +441,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -499,12 +454,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -513,12 +467,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -527,12 +480,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -541,12 +493,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -555,12 +506,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -569,12 +519,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -583,12 +532,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -597,12 +545,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -611,12 +558,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -625,12 +571,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -639,12 +584,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -653,12 +597,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -667,12 +610,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -681,12 +623,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -695,12 +636,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -709,12 +649,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -723,12 +662,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -737,33 +675,25 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -771,12 +701,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -785,12 +714,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -799,12 +727,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -813,12 +740,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -827,12 +753,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -841,12 +766,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -855,12 +779,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -869,12 +792,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -883,12 +805,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -897,12 +818,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -911,12 +831,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -925,12 +844,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -939,12 +857,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -953,12 +870,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -967,12 +883,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -981,12 +896,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -995,12 +909,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1009,12 +922,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1023,12 +935,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1037,12 +948,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1093,10 +1003,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1249,9 +1155,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM4_MPU/port.c b/Source/portable/IAR/ARM_CM4_MPU/port.c
index 518dfbc..08125a2 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/port.c
+++ b/Source/portable/IAR/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -69,6 +69,9 @@
#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -108,7 +111,11 @@
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
@@ -258,13 +265,13 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -277,20 +284,30 @@
*/
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
+extern void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
/*
* This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
@@ -321,28 +338,29 @@
}
else
{
- xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
}
- xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
- xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
- xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
- xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
- xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
- xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
- xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
- xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
- xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
- xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
- xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
- xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
- xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
- xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
- xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
- xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+ xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
+ xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
+ xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
+ xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
+ xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
+ xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
+ xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
+ xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
+ xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+
+ xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
- xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
@@ -378,7 +396,6 @@
switch( ucSVCNumber )
{
case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
vPortRestoreContextOfFirstTask();
break;
@@ -481,12 +498,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -507,13 +523,12 @@
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r1, control \n" /* Obtain current control value. */
" bic r1, #1 \n" /* Clear nPRIV bit. */
" msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory"
- );
+ );
/* Remember the location where we should copy the stack frame when we exit from
* the system call. */
@@ -528,7 +543,6 @@
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
-
/* Raise a request to exit from the system call upon finishing the
* system call. */
pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -607,12 +621,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -633,13 +646,12 @@
__asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r1, control \n" /* Obtain current control value. */
" orr r1, #1 \n" /* Set nPRIV bit. */
" msr control, r1 \n" /* Write back new control value. */
::: "r1", "memory"
- );
+ );
/* Return to the caller of the System Call entry point (i.e. the
* caller of the MPU_<API>). */
@@ -681,6 +693,19 @@
}
/*-----------------------------------------------------------*/
+void vPortSwitchToUserMode( void )
+{
+ /* Load the current task's MPU settings from its TCB. */
+ xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+ /* Mark the task as unprivileged. */
+ xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+ /* Lower the processor's privilege level. */
+ vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
/*
* See header file for description.
*/
@@ -691,6 +716,7 @@
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
#else
+
/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
* configENABLE_ERRATA_837070_WORKAROUND to 1 in your
* FreeRTOSConfig.h. */
@@ -698,6 +724,40 @@
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#endif
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -733,7 +793,7 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@@ -782,9 +842,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the lowest priority interrupts. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Configure the regions in the MPU that are common to all tasks. */
prvSetupMPU();
@@ -796,11 +858,11 @@
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
- #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
@@ -932,14 +994,21 @@
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portENABLE_INTERRUPTS();
}
@@ -1058,7 +1127,7 @@
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
extern uint32_t __SRAM_segment_start__[];
extern uint32_t __SRAM_segment_end__[];
@@ -1103,7 +1172,7 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that the
* stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1114,13 +1183,13 @@
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+ ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( portMPU_REGION_ENABLE );
xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
- ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+ ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
tskMPU_WRITE_PERMISSION );
}
@@ -1175,45 +1244,57 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
- uint32_t ulBufferLength,
- uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-{
- uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
- BaseType_t xAccessGranted = pdFALSE;
- const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
- xAccessGranted = pdTRUE;
- }
- else
- {
- if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+ if( xSchedulerRunning == pdFALSE )
{
- ulBufferStartAddress = ( uint32_t ) pvBuffer;
- ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
- for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
{
- if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
{
- xAccessGranted = pdTRUE;
- break;
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
}
}
}
+
+ return xAccessGranted;
}
- return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
@@ -1255,7 +1336,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portasm.s b/Source/portable/IAR/ARM_CM4_MPU/portasm.s
index 0da9a4f..523422a 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/portasm.s
+++ b/Source/portable/IAR/ARM_CM4_MPU/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -57,6 +57,12 @@
#define configUSE_MPU_WRAPPERS_V1 0
#endif
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+ #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
+
/* These must be in sync with portmacro.h. */
#define portSVC_START_SCHEDULER 100
#define portSVC_SYSTEM_CALL_EXIT 103
@@ -113,15 +119,15 @@
str r3, [r0] /* Disable MPU. */
ldr r0, =0xe000ed9c /* Region Base Address register. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
#ifdef configTOTAL_MPU_REGIONS
#if ( configTOTAL_MPU_REGIONS == 16 )
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* configTOTAL_MPU_REGIONS == 16. */
#endif
@@ -233,15 +239,15 @@
str r3, [r0] /* Disable MPU. */
ldr r0, =0xe000ed9c /* Region Base Address register. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
#ifdef configTOTAL_MPU_REGIONS
#if ( configTOTAL_MPU_REGIONS == 16 )
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* configTOTAL_MPU_REGIONS == 16. */
#endif
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
index cae9bcc..12e35b6 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
@@ -73,9 +73,14 @@
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+ #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
#endif
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+ #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@@ -95,7 +100,7 @@
#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -177,8 +182,8 @@
#define configTEX_S_C_B_SRAM ( 0x07UL )
#endif
-#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
-#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
+#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL )
+#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL )
#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
@@ -187,8 +192,6 @@
#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
typedef struct MPU_REGION_REGISTERS
{
uint32_t ulRegionBaseAddress;
@@ -205,7 +208,7 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
#ifndef configSYSTEM_CALL_STACK_SIZE
- #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
#endif
typedef struct SYSTEM_CALL_STACK_INFO
@@ -218,14 +221,23 @@
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
-#define MAX_CONTEXT_SIZE ( 52 )
+/*
+ * +---------+---------------+-----------------+-----------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 | |
+ * | | | EXC_RETURN | LR, PC, xPSR | |
+ * +---------+---------------+-----------------+-----------------+-----+
+ *
+ * <--------><---------------><----------------><----------------><---->
+ * 16 17 10 9 1
+ */
+#define MAX_CONTEXT_SIZE ( 53 )
/* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
-#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
typedef struct MPU_SETTINGS
{
@@ -256,7 +268,7 @@
/* Scheduler utilities. */
-#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" )
#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
@@ -267,8 +279,20 @@
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD_WITHIN_API(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
@@ -280,7 +304,7 @@
/* Check the configuration. */
#if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
/* Store/clear the ready priorities in a bit map. */
@@ -298,23 +322,23 @@
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
-#if( configENABLE_ERRATA_837070_WORKAROUND == 1 )
- #define portDISABLE_INTERRUPTS() \
- { \
- __disable_interrupt(); \
- __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
- __DSB(); \
- __ISB(); \
- __enable_interrupt(); \
- }
+#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ __disable_interrupt(); \
+ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+ __DSB(); \
+ __ISB(); \
+ __enable_interrupt(); \
+ }
#else
- #define portDISABLE_INTERRUPTS() \
- { \
- __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
- __DSB(); \
- __ISB(); \
- }
-#endif
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+ __DSB(); \
+ __ISB(); \
+ }
+#endif /* if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) */
#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
#define portENTER_CRITICAL() vPortEnterCritical()
@@ -330,7 +354,7 @@
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -371,24 +395,33 @@
extern BaseType_t xIsPrivileged( void );
extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
-#define portIS_PRIVILEGED() xIsPrivileged()
+#define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
*/
-#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
-#define portRESET_PRIVILEGE() vResetPrivilege()
+#define portRESET_PRIVILEGE() vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
/*-----------------------------------------------------------*/
extern BaseType_t xPortIsTaskPrivileged( void );
@@ -398,11 +431,11 @@
*
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
*/
-#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
/*-----------------------------------------------------------*/
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
#endif
/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
index ef180bd..68192e4 100644
--- a/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,12 +47,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -61,12 +60,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -75,12 +73,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -89,12 +86,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -103,12 +99,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -117,12 +112,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -131,12 +125,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -145,12 +138,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -159,12 +151,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -173,12 +164,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -187,40 +177,24 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -229,12 +203,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -257,12 +229,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -271,12 +242,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -285,12 +255,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -299,12 +268,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -313,12 +281,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -327,12 +294,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -341,12 +307,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -355,12 +320,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -369,12 +333,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -383,12 +346,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -397,12 +359,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -411,12 +372,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -425,12 +385,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -439,12 +398,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -453,12 +411,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -467,12 +424,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -481,12 +437,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -495,12 +450,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -509,12 +463,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -523,12 +476,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -537,12 +489,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -551,12 +502,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -565,12 +515,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -579,12 +528,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -593,12 +541,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -607,12 +554,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -621,12 +567,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -635,12 +580,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -649,12 +593,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -663,12 +606,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -677,12 +619,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -691,12 +632,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -705,12 +645,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -719,12 +658,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -733,33 +671,25 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -767,12 +697,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -781,12 +710,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -795,12 +723,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -809,12 +736,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -823,12 +749,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -837,12 +762,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -851,12 +775,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -865,12 +788,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -879,12 +801,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -893,12 +814,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -907,12 +827,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -921,12 +840,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -935,12 +853,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -949,12 +866,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -963,12 +879,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -977,12 +892,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -991,12 +905,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1005,12 +918,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1019,12 +931,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1033,12 +944,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1089,10 +999,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1245,9 +1151,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/port.c b/Source/portable/IAR/ARM_CM55/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM55/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portasm.h b/Source/portable/IAR/ARM_CM55/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM55/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM55/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portasm.s b/Source/portable/IAR/ARM_CM55/non_secure/portasm.s
index 5309103..b5c91e5 100644
--- a/Source/portable/IAR/ARM_CM55/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM55/non_secure/portasm.s
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -150,6 +152,14 @@
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
@@ -175,12 +185,22 @@
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
- movs r1, #2 /* r1 = 2. */
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
@@ -213,7 +233,7 @@
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
@@ -268,11 +288,20 @@
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
- str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_1
+ mrs r5, PAC_KEY_P_2
+ mrs r6, PAC_KEY_P_3
+ stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -326,6 +355,14 @@
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
@@ -371,76 +408,86 @@
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
- push {r0-r2, r14}
- bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- pop {r0-r3} /* LR is now in r3. */
- mov lr, r3 /* LR = r3. */
- lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
- subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
- str r2, [r1] /* Save the new top of stack in TCB. */
- mrs r1, psplim /* r1 = PSPLIM. */
- mov r3, lr /* r3 = LR/EXC_RETURN. */
- stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
- b select_next_task
+ save_s_context:
+ push {r0-r2, lr}
+ bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ pop {r0-r2, lr}
save_ns_context:
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
+ mov r3, lr /* r3 = LR. */
+ lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+ save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- str r2, [r1] /* Save the new top of stack in TCB. */
- adds r2, r2, #12 /* r2 = r2 + 12. */
- stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
- mrs r1, psplim /* r1 = PSPLIM. */
- mov r3, lr /* r3 = LR/EXC_RETURN. */
- subs r2, r2, #12 /* r2 = r2 - 12. */
- stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */
+
+ save_special_regs:
+ mrs r3, psplim /* r3 = PSPLIM. */
+ stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_1
+ mrs r6, PAC_KEY_P_0
+ stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the new top of stack in TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
+ restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- msr psplim, r1 /* Restore the PSPLIM register value for the task. */
- mov lr, r4 /* LR = r4. */
+ restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_1, r5
+ msr PAC_KEY_P_0, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ ldmia r2!, {r0, r3, lr} /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ msr psplim, r3 /* Restore the PSPLIM register value for the task. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
- push {r2, r4}
+
+ restore_s_context:
+ push {r1-r3, lr}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- pop {r2, r4}
- mov lr, r4 /* LR = r4. */
- lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- msr psp, r2 /* Remember the new top of stack for the task. */
- bx lr
+ pop {r1-r3, lr}
restore_ns_context:
+ mov r0, lr /* r0 = LR (EXC_RETURN). */
+ lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+ restore_general_regs:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
+
+ restore_context_done:
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h
index 15cb65e..0526455 100644
--- a/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M55"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context.c b/Source/portable/IAR/ARM_CM55/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_context.c
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context.h b/Source/portable/IAR/ARM_CM55/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_context.h
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s
index 0da3e0f..5cc070e 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_heap.c b/Source/portable/IAR/ARM_CM55/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_heap.c
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_heap.h b/Source/portable/IAR/ARM_CM55/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_heap.h
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_init.c b/Source/portable/IAR/ARM_CM55/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_init.c
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_init.h b/Source/portable/IAR/ARM_CM55/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_init.h
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h
+++ b/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
index ef180bd..68192e4 100644
--- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,12 +47,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -61,12 +60,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -75,12 +73,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -89,12 +86,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -103,12 +99,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -117,12 +112,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -131,12 +125,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -145,12 +138,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -159,12 +151,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -173,12 +164,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -187,40 +177,24 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -229,12 +203,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -257,12 +229,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -271,12 +242,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -285,12 +255,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -299,12 +268,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -313,12 +281,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -327,12 +294,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -341,12 +307,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -355,12 +320,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -369,12 +333,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -383,12 +346,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -397,12 +359,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -411,12 +372,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -425,12 +385,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -439,12 +398,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -453,12 +411,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -467,12 +424,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -481,12 +437,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -495,12 +450,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -509,12 +463,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -523,12 +476,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -537,12 +489,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -551,12 +502,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -565,12 +515,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -579,12 +528,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -593,12 +541,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -607,12 +554,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -621,12 +567,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -635,12 +580,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -649,12 +593,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -663,12 +606,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -677,12 +619,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -691,12 +632,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -705,12 +645,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -719,12 +658,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -733,33 +671,25 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -767,12 +697,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -781,12 +710,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -795,12 +723,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -809,12 +736,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -823,12 +749,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -837,12 +762,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -851,12 +775,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -865,12 +788,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -879,12 +801,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -893,12 +814,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -907,12 +827,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -921,12 +840,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -935,12 +853,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -949,12 +866,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -963,12 +879,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -977,12 +892,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -991,12 +905,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1005,12 +918,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1019,12 +931,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1033,12 +944,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1089,10 +999,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1245,9 +1151,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
index 00ee5a5..8092255 100644
--- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -140,6 +142,14 @@
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
@@ -163,10 +173,20 @@
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
- movs r1, #2 /* r1 = 2. */
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
@@ -199,7 +219,7 @@
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
@@ -230,7 +250,6 @@
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
-
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
@@ -239,11 +258,20 @@
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_3
+ stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -297,6 +325,14 @@
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
@@ -332,12 +368,21 @@
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#if ( configENABLE_PAC == 1 )
+ mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r2, PAC_KEY_P_2
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_0
+ stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -348,6 +393,15 @@
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r3
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_0, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
index 15cb65e..0526455 100644
--- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M55"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/port.c b/Source/portable/IAR/ARM_CM7/r0p1/port.c
index a04532b..924e27e 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -45,10 +45,14 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
@@ -63,6 +67,11 @@
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -135,6 +144,11 @@
*/
static void prvTaskExitError( void );
+/*
+ * FreeRTOS handlers implemented in assembly.
+ */
+extern void vPortSVCHandler( void );
+extern void xPortPendSVHandler( void );
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
@@ -234,6 +248,40 @@
*/
BaseType_t xPortStartScheduler( void )
{
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -269,7 +317,7 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@@ -283,22 +331,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -318,9 +366,11 @@
}
#endif /* configASSERT_DEFINED */
- /* Make PendSV and SysTick the lowest priority interrupts. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
@@ -387,14 +437,21 @@
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portENABLE_INTERRUPTS();
}
@@ -684,7 +741,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
index 19cc6cd..4d4ffaf 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
+++ b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
index f93146e..4fa219e 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -27,7 +27,7 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
/* *INDENT-OFF* */
#ifdef __cplusplus
@@ -46,50 +46,50 @@
*/
/* IAR includes. */
- #include <intrinsics.h>
+#include <intrinsics.h>
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Compiler directives. */
- #define portWEAK_SYMBOL __attribute__( ( weak ) )
+#define portWEAK_SYMBOL __attribute__( ( weak ) )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,41 +97,53 @@
__ISB(); \
}
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Architecture specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
- #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() \
+#define portDISABLE_INTERRUPTS() \
{ \
/* Errata work around. */ \
__disable_interrupt(); \
@@ -141,71 +153,71 @@
__enable_interrupt(); \
}
- #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
+#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+#endif
/*-----------------------------------------------------------*/
- portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+ if( ulCurrentInterrupt == 0 )
{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
+ xReturn = pdFALSE;
}
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Pe191
- #pragma diag_suppress=Pa082
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
index ef180bd..68192e4 100644
--- a/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,12 +47,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -61,12 +60,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -75,12 +73,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -89,12 +86,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -103,12 +99,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -117,12 +112,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -131,12 +125,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -145,12 +138,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -159,12 +151,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -173,12 +164,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -187,40 +177,24 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -229,12 +203,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -257,12 +229,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -271,12 +242,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -285,12 +255,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -299,12 +268,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -313,12 +281,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -327,12 +294,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -341,12 +307,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -355,12 +320,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -369,12 +333,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -383,12 +346,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -397,12 +359,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -411,12 +372,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -425,12 +385,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -439,12 +398,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -453,12 +411,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -467,12 +424,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -481,12 +437,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -495,12 +450,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -509,12 +463,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -523,12 +476,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -537,12 +489,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -551,12 +502,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -565,12 +515,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -579,12 +528,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -593,12 +541,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -607,12 +554,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -621,12 +567,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -635,12 +580,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -649,12 +593,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -663,12 +606,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -677,12 +619,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -691,12 +632,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -705,12 +645,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -719,12 +658,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -733,33 +671,25 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -767,12 +697,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -781,12 +710,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -795,12 +723,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -809,12 +736,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -823,12 +749,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -837,12 +762,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -851,12 +775,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -865,12 +788,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -879,12 +801,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -893,12 +814,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -907,12 +827,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -921,12 +840,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -935,12 +853,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -949,12 +866,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -963,12 +879,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -977,12 +892,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -991,12 +905,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1005,12 +918,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1019,12 +931,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1033,12 +944,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1089,10 +999,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1245,9 +1151,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/port.c b/Source/portable/IAR/ARM_CM85/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM85/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portasm.h b/Source/portable/IAR/ARM_CM85/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM85/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM85/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portasm.s b/Source/portable/IAR/ARM_CM85/non_secure/portasm.s
index 5309103..b5c91e5 100644
--- a/Source/portable/IAR/ARM_CM85/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM85/non_secure/portasm.s
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -150,6 +152,14 @@
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
@@ -175,12 +185,22 @@
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
- movs r1, #2 /* r1 = 2. */
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
@@ -213,7 +233,7 @@
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
@@ -268,11 +288,20 @@
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
- str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_1
+ mrs r5, PAC_KEY_P_2
+ mrs r6, PAC_KEY_P_3
+ stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -326,6 +355,14 @@
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_2, r5
+ msr PAC_KEY_P_3, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
@@ -371,76 +408,86 @@
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
- push {r0-r2, r14}
- bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- pop {r0-r3} /* LR is now in r3. */
- mov lr, r3 /* LR = r3. */
- lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
- subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
- str r2, [r1] /* Save the new top of stack in TCB. */
- mrs r1, psplim /* r1 = PSPLIM. */
- mov r3, lr /* r3 = LR/EXC_RETURN. */
- stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
- b select_next_task
+ save_s_context:
+ push {r0-r2, lr}
+ bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+ pop {r0-r2, lr}
save_ns_context:
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
+ mov r3, lr /* r3 = LR. */
+ lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+ save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
- subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
- str r2, [r1] /* Save the new top of stack in TCB. */
- adds r2, r2, #12 /* r2 = r2 + 12. */
- stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
- mrs r1, psplim /* r1 = PSPLIM. */
- mov r3, lr /* r3 = LR/EXC_RETURN. */
- subs r2, r2, #12 /* r2 = r2 - 12. */
- stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */
+
+ save_special_regs:
+ mrs r3, psplim /* r3 = PSPLIM. */
+ stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_1
+ mrs r6, PAC_KEY_P_0
+ stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+
+ str r2, [r1] /* Save the new top of stack in TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
+ restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
- ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
- msr psplim, r1 /* Restore the PSPLIM register value for the task. */
- mov lr, r4 /* LR = r4. */
+ restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_1, r5
+ msr PAC_KEY_P_0, r6
+ clrm {r3-r6} /* Clear r3-r6. */
+ #endif /* configENABLE_PAC */
+ ldmia r2!, {r0, r3, lr} /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+ msr psplim, r3 /* Restore the PSPLIM register value for the task. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
- ldr r1, [r3] /* Read pxCurrentTCB. */
- push {r2, r4}
+
+ restore_s_context:
+ push {r1-r3, lr}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
- pop {r2, r4}
- mov lr, r4 /* LR = r4. */
- lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
- bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
- msr psp, r2 /* Remember the new top of stack for the task. */
- bx lr
+ pop {r1-r3, lr}
restore_ns_context:
+ mov r0, lr /* r0 = LR (EXC_RETURN). */
+ lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+ restore_general_regs:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
+
+ restore_context_done:
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h
index ee5baf1..2f1676c 100644
--- a/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M85"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context.c b/Source/portable/IAR/ARM_CM85/secure/secure_context.c
index e37dd96..62bcfa1 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_context.c
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_context.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,7 +65,7 @@
* @brief Maximum number of secure contexts.
*/
#ifndef secureconfigMAX_SECURE_CONTEXTS
- #define secureconfigMAX_SECURE_CONTEXTS 8UL
+ #define secureconfigMAX_SECURE_CONTEXTS 8UL
#endif
/*-----------------------------------------------------------*/
@@ -164,15 +164,15 @@
}
#if ( configENABLE_MPU == 1 )
- {
- /* Configure thread mode to use PSP and to be unprivileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
#else /* configENABLE_MPU */
- {
- /* Configure thread mode to use PSP and to be privileged. */
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
- }
+ {
+ /* Configure thread mode to use PSP and to be privileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
#endif /* configENABLE_MPU */
}
}
@@ -207,7 +207,7 @@
* securecontextNO_STACK when no secure context is loaded. */
if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
{
- /* Ontain a free secure context. */
+ /* Obtain a free secure context. */
ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
/* Were we able to get a free context? */
@@ -219,16 +219,16 @@
if( pucStackMemory != NULL )
{
/* Since stack grows down, the starting point will be the last
- * location. Note that this location is next to the last
- * allocated byte for stack (excluding the space for seal values)
- * because the hardware decrements the stack pointer before
- * writing i.e. if stack pointer is 0x2, a push operation will
- * decrement the stack pointer to 0x1 and then write at 0x1. */
+ * location. Note that this location is next to the last
+ * allocated byte for stack (excluding the space for seal values)
+ * because the hardware decrements the stack pointer before
+ * writing i.e. if stack pointer is 0x2, a push operation will
+ * decrement the stack pointer to 0x1 and then write at 0x1. */
xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
/* Seal the created secure process stack. */
- *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
- *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+ *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
/* The stack cannot go beyond this location. This value is
* programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@
xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
#if ( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ pulCurrentStackPointer--;
+
+ if( ulIsTaskPrivileged )
{
- /* Store the correct CONTROL value for the task on the stack.
- * This value is programmed in the CONTROL register on
- * context switch. */
- pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- pulCurrentStackPointer--;
-
- if( ulIsTaskPrivileged )
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
- }
- else
- {
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
- }
-
- /* Store the current stack pointer. This value is programmed in
- * the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
}
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
#else /* configENABLE_MPU */
- {
- /* Current SP is set to the starting of the stack. This
- * value programmed in the PSP register on context switch. */
- xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
- }
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+ }
#endif /* configENABLE_MPU */
/* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint32_t ulIPSR, ulSecureContextIndex;
@@ -306,7 +307,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@
}
/*-----------------------------------------------------------*/
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle )
{
uint8_t * pucStackLimit;
uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context.h b/Source/portable/IAR/ARM_CM85/secure/secure_context.h
index 2220ea6..8b93857 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_context.h
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_context.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -38,12 +38,12 @@
/**
* @brief PSP value when no secure context is loaded.
*/
-#define securecontextNO_STACK 0x0
+#define securecontextNO_STACK 0x0
/**
* @brief Invalid context ID.
*/
-#define securecontextINVALID_CONTEXT_ID 0UL
+#define securecontextINVALID_CONTEXT_ID 0UL
/*-----------------------------------------------------------*/
/**
@@ -108,7 +108,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the
* context to be freed.
*/
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Loads the given context.
@@ -119,7 +120,8 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be loaded.
*/
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
/**
* @brief Saves the given context.
@@ -130,6 +132,7 @@
* @param[in] xSecureContextHandle Context handle corresponding to the context
* to be saved.
*/
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+ void * pvTaskHandle );
#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s
index 0da3e0f..5cc070e 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_heap.c b/Source/portable/IAR/ARM_CM85/secure/secure_heap.c
index 19f7c23..b0e83b4 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_heap.c
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,9 @@
/* Standard includes. */
#include <stdint.h>
+/* Configuration includes. */
+#include "FreeRTOSConfig.h"
+
/* Secure context heap includes. */
#include "secure_heap.h"
@@ -62,6 +65,22 @@
/* Assumes 8bit bytes! */
#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) )
+#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK )
+#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK )
/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
@@ -123,14 +142,6 @@
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
@@ -175,9 +186,6 @@
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -229,7 +237,7 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
@@ -250,6 +258,8 @@
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
@@ -262,25 +272,29 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is set.
- * The top bit of the block size member of the BlockLink_t structure is used
- * to determine who owns the block - the application or the kernel, so it
- * must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
+ /* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
xWantedSize += xHeapStructSize;
- /* Ensure that blocks are always aligned to the required number of
- * bytes. */
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
{
/* Byte alignment required. */
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK );
+
+ if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
}
else
{
@@ -289,9 +303,20 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -334,7 +359,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink;
}
else
{
@@ -352,9 +378,11 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned by
* the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ secureheapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
}
else
@@ -372,20 +400,23 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
#if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
@@ -408,16 +439,16 @@
pxLink = ( void * ) puc;
/* Check the block is actually allocated. */
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
secureportASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ secureheapFREE_BLOCK( pxLink );
secureportDISABLE_NON_SECURE_INTERRUPTS();
{
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_heap.h b/Source/portable/IAR/ARM_CM85/secure/secure_heap.h
index 75c9cb0..61a96da 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_heap.h
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_heap.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_init.c b/Source/portable/IAR/ARM_CM85/secure/secure_init.c
index f93bfce..f7f7e67 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_init.c
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_init.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -93,7 +93,7 @@
* permitted. CP11 should be programmed to the same value as CP10. */
*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures
* that we can enable/disable lazy stacking in port.c file. */
*( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_init.h b/Source/portable/IAR/ARM_CM85/secure/secure_init.h
index e6c9da0..46ffbd9 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_init.h
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_init.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h
index d7ac583..34494e1 100644
--- a/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h
+++ b/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
index ef180bd..68192e4 100644
--- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
+++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,12 +47,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
@@ -61,12 +60,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
@@ -75,12 +73,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
@@ -89,12 +86,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
@@ -103,12 +99,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
@@ -117,12 +112,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
@@ -131,12 +125,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
@@ -145,12 +138,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
@@ -159,12 +151,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
@@ -173,12 +164,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
@@ -187,40 +177,24 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
- PUBLIC MPU_pcTaskGetName
-MPU_pcTaskGetName:
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
- MPU_pcTaskGetName_Priv:
- pop {r0}
- b MPU_pcTaskGetNameImpl
- MPU_pcTaskGetName_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-/*-----------------------------------------------------------*/
-
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
@@ -229,12 +203,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
@@ -243,12 +216,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
@@ -257,12 +229,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
@@ -271,12 +242,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -285,12 +255,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
@@ -299,12 +268,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -313,12 +281,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
@@ -327,12 +294,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
@@ -341,12 +307,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
@@ -355,12 +320,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
@@ -369,12 +333,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
@@ -383,12 +346,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
@@ -397,12 +359,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
@@ -411,12 +372,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
@@ -425,12 +385,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
@@ -439,12 +398,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
@@ -453,12 +411,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
@@ -467,12 +424,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
@@ -481,12 +437,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
@@ -495,12 +450,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
@@ -509,12 +463,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
@@ -523,12 +476,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
@@ -537,12 +489,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
@@ -551,12 +502,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
@@ -565,12 +515,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
@@ -579,12 +528,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
@@ -593,12 +541,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
@@ -607,12 +554,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
@@ -621,12 +567,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
@@ -635,12 +580,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
@@ -649,12 +593,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
@@ -663,12 +606,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
@@ -677,12 +619,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
@@ -691,12 +632,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
@@ -705,12 +645,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
@@ -719,12 +658,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
@@ -733,33 +671,25 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
- PUBLIC MPU_xTimerGenericCommandEntry
-MPU_xTimerGenericCommandEntry:
+ PUBLIC MPU_xTimerGenericCommandFromTaskEntry
+MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
- /* This function can be called from ISR also and therefore, we need a check
- * to take privileged path, if called from ISR. */
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
- MPU_xTimerGenericCommand_Unpriv:
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
- MPU_xTimerGenericCommand_Priv:
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
-
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+ MPU_xTimerGenericCommandFromTask_Priv:
+ b MPU_xTimerGenericCommandFromTaskImpl
+ MPU_xTimerGenericCommandFromTask_Unpriv:
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
@@ -767,12 +697,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
@@ -781,12 +710,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
@@ -795,12 +723,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -809,12 +736,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
@@ -823,12 +749,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
@@ -837,12 +762,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
@@ -851,12 +775,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
@@ -865,12 +788,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
@@ -879,12 +801,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
@@ -893,12 +814,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
@@ -907,12 +827,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
@@ -921,12 +840,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
@@ -935,12 +853,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
@@ -949,12 +866,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
@@ -963,12 +879,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
@@ -977,12 +892,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
@@ -991,12 +905,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
@@ -1005,12 +918,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
@@ -1019,12 +931,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
@@ -1033,12 +944,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
@@ -1089,10 +999,6 @@
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
- PUBWEAK MPU_pcTaskGetNameImpl
-MPU_pcTaskGetNameImpl:
- b MPU_pcTaskGetNameImpl
-
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
@@ -1245,9 +1151,9 @@
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
- PUBWEAK MPU_xTimerGenericCommandPrivImpl
-MPU_xTimerGenericCommandPrivImpl:
- b MPU_xTimerGenericCommandPrivImpl
+ PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTaskImpl:
+ b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
index 9712ac3..f16a343 100644
--- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +56,7 @@
* The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
* i.e. the processor boots as secure and never jumps to the non-secure side.
* The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
+ * on the secure side. The following are the valid configuration settings:
*
* 1. Run FreeRTOS on the Secure Side:
* configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
@@ -68,6 +70,22 @@
#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
#endif
+
+/**
+ * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
+ * only when FreeRTOS runs on secure side.
+ */
+#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) )
+ #define portUSE_PSPLIM_REGISTER 0
+#else
+ #define portUSE_PSPLIM_REGISTER 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Prototype of all Interrupt Service Routines (ISRs).
+ */
+typedef void ( * portISR_t )( void );
/*-----------------------------------------------------------*/
/**
@@ -91,8 +109,17 @@
/**
* @brief Constants required to manipulate the SCB.
*/
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
+#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants used to check the installation of the FreeRTOS interrupt handlers.
+ */
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
/*-----------------------------------------------------------*/
/**
@@ -111,8 +138,8 @@
/**
* @brief Constants used during system call enter and exit.
*/
-#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
-#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
+#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
+#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
/*-----------------------------------------------------------*/
/**
@@ -134,72 +161,79 @@
/**
* @brief Offsets in the stack to the parameters when inside the SVC handler.
*/
-#define portOFFSET_TO_LR ( 5 )
-#define portOFFSET_TO_PC ( 6 )
-#define portOFFSET_TO_PSR ( 7 )
+#define portOFFSET_TO_LR ( 5 )
+#define portOFFSET_TO_PC ( 6 )
+#define portOFFSET_TO_PSR ( 7 )
/*-----------------------------------------------------------*/
/**
* @brief Constants required to manipulate the MPU.
*/
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
-#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
-#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
-#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
-#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
-#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
+#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL )
-#define portMPU_MAIR_ATTR0_POS ( 0UL )
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR1_POS ( 8UL )
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR2_POS ( 16UL )
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR3_POS ( 24UL )
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
-#define portMPU_MAIR_ATTR4_POS ( 0UL )
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
-#define portMPU_MAIR_ATTR5_POS ( 8UL )
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
-#define portMPU_MAIR_ATTR6_POS ( 16UL )
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
-#define portMPU_MAIR_ATTR7_POS ( 24UL )
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+#if ( portARMV8M_MINOR_VERSION >= 1 )
+
+/* Enable Privileged eXecute Never MPU attribute for the selected memory
+ * region. */
+ #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL )
+#endif /* portARMV8M_MINOR_VERSION >= 1 */
/* Enable privileged access to unmapped region. */
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL )
@@ -343,6 +377,20 @@
* any secure calls.
*/
#define portNO_SECURE_CONTEXT 0
+
+/**
+ * @brief Constants required to check and configure PACBTI security feature implementation.
+ */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
+
+ #define portCONTROL_UPAC_EN ( 1UL << 7UL )
+ #define portCONTROL_PAC_EN ( 1UL << 6UL )
+ #define portCONTROL_UBTI_EN ( 1UL << 5UL )
+ #define portCONTROL_BTI_EN ( 1UL << 4UL )
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
/*-----------------------------------------------------------*/
/**
@@ -351,7 +399,7 @@
*/
static void prvTaskExitError( void );
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief Extract MPU region's access permissions from the Region Base Address
@@ -362,7 +410,7 @@
* @return uint32_t Access permissions.
*/
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
#if ( configENABLE_MPU == 1 )
@@ -380,6 +428,26 @@
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_FPU */
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+/**
+ * @brief Configures PACBTI features.
+ *
+ * This function configures the Pointer Authentication, and Branch Target
+ * Identification security features as per the user configuration. It returns
+ * the value of the special purpose CONTROL register accordingly, and optionally
+ * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
+ * architecture based) target supports PACBTI security feature.
+ *
+ * @param xWriteControlRegister Used to control whether the special purpose
+ * CONTROL register should be updated or not.
+ *
+ * @return CONTROL register value according to the configured PACBTI option.
+ */
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
/**
* @brief Setup the timer to generate the tick interrupts.
*
@@ -448,13 +516,13 @@
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -462,24 +530,24 @@
#if ( configENABLE_MPU == 1 )
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
-#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
/**
* @brief This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/**
* @brief Each task maintains its own interrupt status in the critical nesting
@@ -501,13 +569,13 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
#if ( configUSE_TICKLESS_IDLE == 1 )
@@ -531,6 +599,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
+
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
@@ -746,6 +815,7 @@
__asm volatile ( "cpsie i" ::: "memory" );
}
}
+
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -760,8 +830,15 @@
}
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
+ /* Stop and reset SysTick.
+ *
+ * QEMU versions older than 7.0.0 contain a bug which causes an error if we
+ * enable SysTick without first selecting a valid clock source. We trigger
+ * the bug if we change clock sources from a clock with a zero clock period
+ * to one with a nonzero clock period and enable Systick at the same time.
+ * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit.
+ * This workaround avoids the bug in QEMU versions older than 7.0.0. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
@@ -795,7 +872,8 @@
}
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulAccessPermissions = 0;
@@ -812,13 +890,16 @@
return ulAccessPermissions;
}
-#endif /* configENABLE_MPU */
+
+#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
{
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -903,10 +984,12 @@
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( configENABLE_FPU == 1 )
+
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
@@ -928,6 +1011,7 @@
* LSPEN = 1 ==> Enable lazy context save of FP state. */
*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
}
+
#endif /* configENABLE_FPU */
/*-----------------------------------------------------------*/
@@ -972,13 +1056,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
@@ -988,6 +1078,7 @@
{
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1083,18 +1174,24 @@
vRestoreContextOfFirstTask();
break;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
- case portSVC_RAISE_PRIVILEGE:
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) )
+ case portSVC_RAISE_PRIVILEGE:
- /* Only raise the privilege, if the svc was raised from any of
- * the system calls. */
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- vRaisePrivilege();
- }
- break;
- #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+ ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+ {
+ vRaisePrivilege();
+ }
+ break;
+ #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+ #if ( configENABLE_MPU == 1 )
+ case portSVC_YIELD:
+ vPortYield();
+ break;
+ #endif /* configENABLE_MPU == 1 */
default:
/* Incorrect SVC call. */
@@ -1116,6 +1213,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __syscalls_flash_start__;
@@ -1154,12 +1252,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1171,7 +1268,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the system call stack for the stack frame. */
pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
@@ -1190,11 +1287,19 @@
/* Store the value of the PSPLIM register before the SVC was raised.
* We need to restore it when we exit from the system call. */
- __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* Use the pulSystemCallStack in thread mode. */
__asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) );
+ }
+ #endif
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
@@ -1224,14 +1329,13 @@
pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
/* Raise the privilege for the duration of the system call. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" bics r0, r1 \n" /* Clear nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1259,6 +1363,7 @@
uint32_t ulStackFrameSize, ulSystemCallLocation, i;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_functions_start__;
@@ -1293,12 +1398,11 @@
{
/* Extended frame i.e. FPU in use. */
ulStackFrameSize = 26;
- __asm volatile
- (
+ __asm volatile (
" vpush {s0} \n" /* Trigger lazy stacking. */
" vpop {s0} \n" /* Nullify the affect of the above instruction. */
::: "memory"
- );
+ );
}
else
{
@@ -1310,7 +1414,7 @@
{
ulStackFrameSize = 8;
}
- #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
/* Make space on the task stack for the stack frame. */
pulTaskStack = pulTaskStack - ulStackFrameSize;
@@ -1332,7 +1436,11 @@
/* Restore the PSPLIM register to what it was at the time of
* system call entry. */
- __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ #if ( portUSE_PSPLIM_REGISTER == 1 )
+ {
+ __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) );
+ }
+ #endif
/* If the hardware used padding to force the stack pointer
* to be double word aligned, set the stacked xPSR bit[9],
@@ -1350,14 +1458,13 @@
pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
/* Drop the privilege before returning to the thread mode. */
- __asm volatile
- (
+ __asm volatile (
" mrs r0, control \n" /* Obtain current control value. */
" movs r1, #1 \n" /* r1 = 1. */
" orrs r0, r1 \n" /* Set nPRIV bit. */
" msr control, r0 \n" /* Write back new control value. */
::: "r0", "r1", "memory"
- );
+ );
}
}
@@ -1392,6 +1499,7 @@
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
{
uint32_t ulIndex = 0;
+ uint32_t ulControl = 0x0;
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
ulIndex++;
@@ -1410,21 +1518,21 @@
xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */
ulIndex++;
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */
ulIndex++;
#if ( configENABLE_TRUSTZONE == 1 )
@@ -1435,20 +1543,30 @@
#endif /* configENABLE_TRUSTZONE */
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
ulIndex++;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
+ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
ulIndex++;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Check PACBTI security feature configuration before pushing the
+ * CONTROL register's value on task's TCB. */
+ ulControl = prvConfigurePACBTI( pdFALSE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+
if( xRunPrivileged == pdTRUE )
{
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
ulIndex++;
}
else
{
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
- xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
+ xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
ulIndex++;
}
+
xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */
ulIndex++;
@@ -1469,6 +1587,20 @@
}
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ];
+ ulIndex++;
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return &( xMPUSettings->ulContext[ ulIndex ] );
}
@@ -1483,7 +1615,7 @@
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1505,7 +1637,7 @@
}
#else /* portPRELOAD_REGISTERS */
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR. */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC. */
@@ -1540,7 +1672,7 @@
pxTopOfStack--;
*pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
#if ( configENABLE_TRUSTZONE == 1 )
{
@@ -1551,6 +1683,20 @@
}
#endif /* portPRELOAD_REGISTERS */
+ #if ( configENABLE_PAC == 1 )
+ {
+ uint32_t ulTaskPacKey[ 4 ], i;
+
+ vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) );
+
+ for( i = 0; i < 4; i++ )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = ulTaskPacKey[ i ];
+ }
+ }
+ #endif /* configENABLE_PAC */
+
return pxTopOfStack;
}
@@ -1559,22 +1705,52 @@
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
{
- #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler
+ * for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * SVC_Handler and PendSV_Handler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
{
- volatile uint32_t ulOriginalPriority;
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
+ #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
+ {
volatile uint32_t ulImplementedPrioBits = 0;
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = portNVIC_SHPR2_REG;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
+ * First, determine the number of priority bits available. Write to all
+ * possible bits in the priority setting for SVCall. */
portNVIC_SHPR2_REG = 0xFF000000;
/* Read the value back to see how many bits stuck. */
@@ -1593,11 +1769,10 @@
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
-
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
@@ -1635,16 +1810,22 @@
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- portNVIC_SHPR2_REG = ulOriginalPriority;
}
- #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+ #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
+ * the highest priority. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
+
+ #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+ {
+ /* Set the CONTROL register value based on PACBTI security feature
+ * configuration before starting the first task. */
+ ( void ) prvConfigurePACBTI( pdTRUE );
+ }
+ #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
#if ( configENABLE_MPU == 1 )
{
@@ -1660,11 +1841,11 @@
/* Initialize the critical nesting count ready for the first task. */
ulCriticalNesting = 0;
- #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/* Start the first task. */
vStartFirstTask();
@@ -1692,15 +1873,17 @@
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
int32_t lIndex = 0;
#if defined( __ARMCC_VERSION )
+
/* Declaration when these variable are defined in code instead of being
* exported from linker scripts. */
extern uint32_t * __privileged_sram_start__;
@@ -1719,10 +1902,10 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that
* the stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1;
/* If the stack is within the privileged SRAM, do not protect it
* using a separate MPU region. This is needed because privileged
@@ -1790,6 +1973,16 @@
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
( portMPU_RLAR_REGION_ENABLE );
+ /* PXN. */
+ #if ( portARMV8M_MINOR_VERSION >= 1 )
+ {
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER );
+ }
+ }
+ #endif /* portARMV8M_MINOR_VERSION >= 1 */
+
/* Normal memory/ Device memory. */
if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
{
@@ -1812,10 +2005,12 @@
lIndex++;
}
}
+
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
-#if ( configENABLE_MPU == 1 )
+#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
uint32_t ulBufferLength,
uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
@@ -1825,7 +2020,15 @@
BaseType_t xAccessGranted = pdFALSE;
const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ if( xSchedulerRunning == pdFALSE )
+ {
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
xAccessGranted = pdTRUE;
}
@@ -1860,7 +2063,8 @@
return xAccessGranted;
}
-#endif /* configENABLE_MPU */
+
+#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortIsInsideInterrupt( void )
@@ -1886,7 +2090,7 @@
}
/*-----------------------------------------------------------*/
-#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) )
+#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) )
void vPortValidateInterruptPriority( void )
{
@@ -1924,7 +2128,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
@@ -1944,7 +2148,7 @@
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
-#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */
+#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
@@ -2041,3 +2245,38 @@
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
/*-----------------------------------------------------------*/
+
+#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
+
+ static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
+ {
+ uint32_t ulControl = 0x0;
+
+ /* Ensure that PACBTI is implemented. */
+ configASSERT( portID_ISAR5_REG != 0x0 );
+
+ /* Enable UsageFault exception. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
+
+ #if ( configENABLE_PAC == 1 )
+ {
+ ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
+ }
+ #endif
+
+ #if ( configENABLE_BTI == 1 )
+ {
+ ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
+ }
+ #endif
+
+ if( xWriteControlRegister == pdTRUE )
+ {
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
+ }
+
+ return ulControl;
+ }
+
+#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
index f64ceb5..53b4b6e 100644
--- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,7 @@
* @brief Raises the privilege level by clearing the bit 0 of the CONTROL
* register.
*
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
* code.
*
* Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
index 00ee5a5..8092255 100644
--- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -140,6 +142,14 @@
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
@@ -163,10 +173,20 @@
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r2
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_0, r4
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
- movs r1, #2 /* r1 = 2. */
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ mrs r1, control /* Obtain current control register value. */
+ orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+ msr control, r1 /* Write back the new control register value. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
@@ -199,7 +219,7 @@
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
@@ -230,7 +250,6 @@
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
-
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
@@ -239,11 +258,20 @@
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+ #if ( configENABLE_PAC == 1 )
+ mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_2
+ mrs r5, PAC_KEY_P_3
+ stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
+
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -297,6 +325,14 @@
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
+ #if ( configENABLE_PAC == 1 )
+ ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */
+ msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_1, r3
+ msr PAC_KEY_P_2, r4
+ msr PAC_KEY_P_3, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+ #endif /* configENABLE_PAC */
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
@@ -332,12 +368,21 @@
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#if ( configENABLE_PAC == 1 )
+ mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */
+ mrs r2, PAC_KEY_P_2
+ mrs r3, PAC_KEY_P_1
+ mrs r4, PAC_KEY_P_0
+ stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */
+ clrm {r1-r4} /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+ msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
@@ -348,6 +393,15 @@
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+#if ( configENABLE_PAC == 1 )
+ ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */
+ msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */
+ msr PAC_KEY_P_2, r3
+ msr PAC_KEY_P_1, r4
+ msr PAC_KEY_P_0, r5
+ clrm {r2-r5} /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
index ee5baf1..2f1676c 100644
--- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -53,9 +53,10 @@
/**
* Architecture specifics.
*/
-#define portARCH_NAME "Cortex-M85"
-#define portHAS_BASEPRI 1
-#define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION 1
+#define portARMV8M_MINOR_VERSION 1
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
/* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
/**
* @brief Critical section management.
*/
-#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
-#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
index 6f666da..2dfac6a 100644
--- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
+++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
*
* SPDX-License-Identifier: MIT
*
@@ -117,7 +119,7 @@
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
#if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
#endif /* configENABLE_TRUSTZONE */
@@ -125,6 +127,18 @@
extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
#endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+ /**
+ * @brief Generates 128-bit task's random PAC key.
+ *
+ * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+ * filled with a 128-bit random number.
+ */
+ void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
/*-----------------------------------------------------------*/
/**
@@ -137,7 +151,7 @@
#define portPRIVILEGE_BIT ( 0x0UL )
#endif /* configENABLE_MPU */
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -193,8 +207,8 @@
*/
typedef struct MPURegionSettings
{
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
} MPURegionSettings_t;
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@
*/
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+ * 16 17 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 71
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@
* +-----------+---------------+----------+-----------------+------------------------------+-----+
*
* <-----------><--------------><---------><----------------><-----------------------------><---->
- * 16 16 8 8 5 1
+ * 16 17 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 54
+ #define MAX_CONTEXT_SIZE 55
- #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | | | PC, xPSR | EXC_RETURN | | |
+ * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+ *
+ * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+ * 16 17 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 70
+
+ #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
/*
* +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@
* +-----------+---------------+----------+-----------------+----------------------+-----+
*
* <-----------><--------------><---------><----------------><---------------------><---->
- * 16 16 8 8 4 1
+ * 16 17 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 53
+ #define MAX_CONTEXT_SIZE 54
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
- #if( configENABLE_TRUSTZONE == 1 )
+ #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+------------------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | |
+ * | | PC, xPSR | CONTROL, EXC_RETURN | | |
+ * +----------+-----------------+------------------------------+------------+-----+
+ *
+ * <---------><----------------><------------------------------><-----------><---->
+ * 8 8 5 16 1
+ */
+ #define MAX_CONTEXT_SIZE 38
+
+ #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
/*
* +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@
* <---------><----------------><------------------------------><---->
* 8 8 5 1
*/
- #define MAX_CONTEXT_SIZE 22
+ #define MAX_CONTEXT_SIZE 22
+
+ #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+ /*
+ * +----------+-----------------+----------------------+------------+-----+
+ * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | |
+ * | | PC, xPSR | EXC_RETURN | | |
+ * +----------+-----------------+----------------------+------------+-----+
+ *
+ * <---------><----------------><----------------------><-----------><---->
+ * 8 8 4 16 1
+ */
+ #define MAX_CONTEXT_SIZE 37
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
@@ -277,17 +343,17 @@
* <---------><----------------><----------------------><---->
* 8 8 4 1
*/
- #define MAX_CONTEXT_SIZE 21
+ #define MAX_CONTEXT_SIZE 21
- #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+ #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
- #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
- #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+ #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+ #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
-/* Size of an Access Control List (ACL) entry in bits. */
+ /* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
typedef struct MPU_SETTINGS
@@ -312,8 +378,8 @@
* @brief Validate priority of ISRs that are allowed to call FreeRTOS
* system calls.
*/
-#ifdef configASSERT
- #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -333,12 +399,29 @@
/**
* @brief Scheduler utilities.
*/
-#define portYIELD() vPortYield()
+#if ( configENABLE_MPU == 1 )
+ #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+ #define portYIELD_WITHIN_API() vPortYield()
+#else
+ #define portYIELD() vPortYield()
+ #define portYIELD_WITHIN_API() vPortYield()
+#endif
+
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -424,12 +507,12 @@
extern BaseType_t xPortIsTaskPrivileged( void );
- /**
- * @brief Checks whether or not the calling task is privileged.
- *
- * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
- */
- #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+ #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
#endif /* configENABLE_MPU == 1 */
/*-----------------------------------------------------------*/
@@ -440,6 +523,56 @@
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
/*-----------------------------------------------------------*/
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #else
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+ #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+ static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint32_t ulReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+ return ulReturn;
+ }
+
+/* Check the configuration. */
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+ #endif
+
+ #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+ #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+ #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/MemMang/heap_1.c b/Source/portable/MemMang/heap_1.c
index da11bfc..30f3e13 100644
--- a/Source/portable/MemMang/heap_1.c
+++ b/Source/portable/MemMang/heap_1.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -51,20 +51,28 @@
#endif
/* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/* Max value that fits in a size_t type. */
+#define heapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if adding a and b will result in overflow. */
+#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
+ * heap - probably so it can be placed in a special segment or address. */
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#else
static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#endif /* configAPPLICATION_ALLOCATED_HEAP */
/* Index into the ucHeap array. */
-static size_t xNextFreeByte = ( size_t ) 0;
+static size_t xNextFreeByte = ( size_t ) 0U;
/*-----------------------------------------------------------*/
@@ -76,12 +84,16 @@
/* Ensure that blocks are always aligned. */
#if ( portBYTE_ALIGNMENT != 1 )
{
- if( xWantedSize & portBYTE_ALIGNMENT_MASK )
+ size_t xAdditionalRequiredSize;
+
+ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
{
- /* Byte alignment required. Check for overflow. */
- if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) > xWantedSize )
+ /* Byte alignment required. */
+ xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
+
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
{
- xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+ xWantedSize += xAdditionalRequiredSize;
}
else
{
@@ -96,13 +108,14 @@
if( pucAlignedHeap == NULL )
{
/* Ensure the heap starts on a correctly aligned boundary. */
- pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+ pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &( ucHeap[ portBYTE_ALIGNMENT - 1 ] ) ) &
+ ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
}
- /* Check there is enough room left for the allocation and. */
- if( ( xWantedSize > 0 ) && /* valid size */
- ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
- ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */
+ /* Check there is enough room left for the allocation. */
+ if( ( xWantedSize > 0 ) &&
+ ( heapADD_WILL_OVERFLOW( xNextFreeByte, xWantedSize ) == 0 ) &&
+ ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) )
{
/* Return the next free byte then increment the index past this
* block. */
@@ -150,3 +163,16 @@
{
return( configADJUSTED_HEAP_SIZE - xNextFreeByte );
}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+ xNextFreeByte = ( size_t ) 0U;
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/MemMang/heap_2.c b/Source/portable/MemMang/heap_2.c
index 9f363f1..0c6f3c2 100644
--- a/Source/portable/MemMang/heap_2.c
+++ b/Source/portable/MemMang/heap_2.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -87,7 +87,7 @@
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
+ * heap - probably so it can be placed in a special segment or address. */
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#else
PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
@@ -103,8 +103,8 @@
} BlockLink_t;
-static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );
-#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
+static const size_t xHeapStructSize = ( ( sizeof( BlockLink_t ) + ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );
+#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize * 2 ) )
/* Create a couple of list links to mark the start and end of the list. */
PRIVILEGED_DATA static BlockLink_t xStart, xEnd;
@@ -113,6 +113,9 @@
* fragmentation. */
PRIVILEGED_DATA static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+/* Indicates whether the heap has been initialised or not. */
+PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE;
+
/*-----------------------------------------------------------*/
/*
@@ -155,9 +158,48 @@
BlockLink_t * pxBlock;
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
- PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE;
void * pvReturn = NULL;
size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
+
+ if( xWantedSize > 0 )
+ {
+ /* The wanted size must be increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
+ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
+
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
vTaskSuspendAll();
{
@@ -169,23 +211,6 @@
xHeapHasBeenInitialised = pdTRUE;
}
- if( xWantedSize > 0 )
- {
- /* The wanted size must be increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. Some
- * additional increment may also be needed for alignment. */
- xAdditionalRequiredSize = heapSTRUCT_SIZE + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
-
- if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
- {
- xWantedSize += xAdditionalRequiredSize;
- }
- else
- {
- xWantedSize = 0;
- }
- }
-
/* Check the block size we are trying to allocate is not so large that the
* top bit is set. The top bit of the block size member of the BlockLink_t
* structure is used to determine who owns the block - the application or
@@ -210,7 +235,7 @@
{
/* Return the memory space - jumping over the BlockLink_t structure
* at its start. */
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
/* This block is being returned for use so must be taken out of the
* list of free blocks. */
@@ -229,12 +254,16 @@
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
pxBlock->xBlockSize = xWantedSize;
- /* Insert the new block into the list of free blocks. */
+ /* Insert the new block into the list of free blocks.
+ * The list of free blocks is sorted by their size, we have to
+ * iterate to find the right place to insert new block. */
prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned
* by the application and has no "next" block. */
heapALLOCATE_BLOCK( pxBlock );
@@ -243,7 +272,10 @@
}
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
}
( void ) xTaskResumeAll();
@@ -269,7 +301,7 @@
{
/* The memory being freed will have an BlockLink_t structure immediately
* before it. */
- puc -= heapSTRUCT_SIZE;
+ puc -= xHeapStructSize;
/* This unexpected casting is to keep some compilers from issuing
* byte alignment warnings. */
@@ -287,7 +319,7 @@
heapFREE_BLOCK( pxLink );
#if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
{
- ( void ) memset( puc + heapSTRUCT_SIZE, 0, pxLink->xBlockSize - heapSTRUCT_SIZE );
+ ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
}
#endif
@@ -360,3 +392,16 @@
pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
}
/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+ xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+
+ xHeapHasBeenInitialised = pdFALSE;
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/MemMang/heap_3.c b/Source/portable/MemMang/heap_3.c
index f0ecc96..e64c89c 100644
--- a/Source/portable/MemMang/heap_3.c
+++ b/Source/portable/MemMang/heap_3.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -92,3 +92,15 @@
( void ) xTaskResumeAll();
}
}
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+ /* No state needs to be re-initialised in heap_3. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/MemMang/heap_4.c b/Source/portable/MemMang/heap_4.c
index 013364f..ef2db1c 100644
--- a/Source/portable/MemMang/heap_4.c
+++ b/Source/portable/MemMang/heap_4.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -65,10 +65,13 @@
#define heapSIZE_MAX ( ~( ( size_t ) 0 ) )
/* Check if multiplying a and b will result in overflow. */
-#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
/* Check if adding a and b will result in overflow. */
-#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* Check if the subtraction operation ( a - b ) will result in underflow. */
+#define heapSUBTRACT_WILL_UNDERFLOW( a, b ) ( ( a ) < ( b ) )
/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
* the allocation status of a block. When MSB of the xBlockSize member of
@@ -86,7 +89,7 @@
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
/* The application writer has already defined the array used for the RTOS
-* heap - probably so it can be placed in a special segment or address. */
+ * heap - probably so it can be placed in a special segment or address. */
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#else
PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
@@ -100,6 +103,38 @@
size_t xBlockSize; /**< The size of the free block. */
} BlockLink_t;
+/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers
+ * protection using an application supplied canary value to catch heap
+ * corruption should a heap buffer overflow occur.
+ */
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/**
+ * @brief Application provided function to get a random value to be used as canary.
+ *
+ * @param pxHeapCanary [out] Output parameter to return the canary value.
+ */
+ extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary );
+
+/* Canary value for protecting internal heap pointers. */
+ PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary;
+
+/* Macro to load/store BlockLink_t pointers to memory. By XORing the
+ * pointers with a random canary value, heap overflows will result
+ * in randomly unpredictable pointer values which will be caught by
+ * heapVALIDATE_BLOCK_POINTER assert. */
+ #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
+#else
+
+ #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( pxBlock )
+
+#endif /* configENABLE_HEAP_PROTECTOR */
+
+/* Assert that a heap block pointer is within the heap bounds. */
+#define heapVALIDATE_BLOCK_POINTER( pxBlock ) \
+ configASSERT( ( ( uint8_t * ) ( pxBlock ) >= &( ucHeap[ 0 ] ) ) && \
+ ( ( uint8_t * ) ( pxBlock ) <= &( ucHeap[ configTOTAL_HEAP_SIZE - 1 ] ) ) )
+
/*-----------------------------------------------------------*/
/*
@@ -128,10 +163,10 @@
/* Keeps track of the number of calls to allocate and free memory as well as the
* number of free bytes remaining, but says nothing about fragmentation. */
-PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
-PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = ( size_t ) 0U;
/*-----------------------------------------------------------*/
@@ -142,6 +177,46 @@
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
+
+ if( xWantedSize > 0 )
+ {
+ /* The wanted size must be increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
+ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
+
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xWantedSize = 0;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
vTaskSuspendAll();
{
@@ -156,45 +231,6 @@
mtCOVERAGE_TEST_MARKER();
}
- if( xWantedSize > 0 )
- {
- /* The wanted size must be increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
- {
- xWantedSize += xHeapStructSize;
-
- /* Ensure that blocks are always aligned to the required number
- * of bytes. */
- if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
- {
- /* Byte alignment required. */
- xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
-
- if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
- {
- xWantedSize += xAdditionalRequiredSize;
- }
- else
- {
- xWantedSize = 0;
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- xWantedSize = 0;
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
/* Check the block size we are trying to allocate is not so large that the
* top bit is set. The top bit of the block size member of the BlockLink_t
* structure is used to determine who owns the block - the application or
@@ -206,12 +242,14 @@
/* Traverse the list from the start (lowest address) block until
* one of adequate size is found. */
pxPreviousBlock = &xStart;
- pxBlock = xStart.pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
+ heapVALIDATE_BLOCK_POINTER( pxBlock );
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) )
{
pxPreviousBlock = pxBlock;
- pxBlock = pxBlock->pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
+ heapVALIDATE_BLOCK_POINTER( pxBlock );
}
/* If the end marker was reached then a block of adequate size
@@ -220,7 +258,8 @@
{
/* Return the memory space pointed to - jumping over the
* BlockLink_t structure at its start. */
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+ pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize );
+ heapVALIDATE_BLOCK_POINTER( pvReturn );
/* This block is being returned for use so must be taken out
* of the list of free blocks. */
@@ -228,6 +267,8 @@
/* If the block is larger than required it can be split into
* two. */
+ configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 );
+
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
{
/* This block is to be split into two. Create a new
@@ -243,7 +284,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( pxNewBlockLink );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink );
}
else
{
@@ -261,10 +303,12 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned
* by the application and has no "next" block. */
heapALLOCATE_BLOCK( pxBlock );
- pxBlock->pxNextFreeBlock = NULL;
+ pxBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
xNumberOfSuccessfulAllocations++;
}
else
@@ -282,7 +326,10 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
}
( void ) xTaskResumeAll();
@@ -318,19 +365,25 @@
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
+ heapVALIDATE_BLOCK_POINTER( pxLink );
configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
- configASSERT( pxLink->pxNextFreeBlock == NULL );
+ configASSERT( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) );
if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
- if( pxLink->pxNextFreeBlock == NULL )
+ if( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
heapFREE_BLOCK( pxLink );
#if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
{
- ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+ /* Check for underflow as this can occur if xBlockSize is
+ * overwritten in a heap block. */
+ if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 )
+ {
+ ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+ }
}
#endif
@@ -369,6 +422,12 @@
}
/*-----------------------------------------------------------*/
+void xPortResetHeapMinimumEverFreeHeapSize( void )
+{
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
void vPortInitialiseBlocks( void )
{
/* This just exists to keep the linker quiet. */
@@ -397,41 +456,44 @@
static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
{
BlockLink_t * pxFirstFreeBlock;
- uint8_t * pucAlignedHeap;
- portPOINTER_SIZE_TYPE uxAddress;
+ portPOINTER_SIZE_TYPE uxStartAddress, uxEndAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
/* Ensure the heap starts on a correctly aligned boundary. */
- uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
+ uxStartAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
- if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+ if( ( uxStartAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
{
- uxAddress += ( portBYTE_ALIGNMENT - 1 );
- uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
- xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
+ uxStartAddress += ( portBYTE_ALIGNMENT - 1 );
+ uxStartAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= ( size_t ) ( uxStartAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
}
- pucAlignedHeap = ( uint8_t * ) uxAddress;
+ #if ( configENABLE_HEAP_PROTECTOR == 1 )
+ {
+ vApplicationGetRandomHeapCanary( &( xHeapCanary ) );
+ }
+ #endif
/* xStart is used to hold a pointer to the first item in the list of free
* blocks. The void cast is used to prevent compiler warnings. */
- xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( uxStartAddress );
xStart.xBlockSize = ( size_t ) 0;
/* pxEnd is used to mark the end of the list of free blocks and is inserted
* at the end of the heap space. */
- uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize );
- uxAddress -= xHeapStructSize;
- uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
- pxEnd = ( BlockLink_t * ) uxAddress;
+ uxEndAddress = uxStartAddress + ( portPOINTER_SIZE_TYPE ) xTotalHeapSize;
+ uxEndAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
+ uxEndAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+ pxEnd = ( BlockLink_t * ) uxEndAddress;
pxEnd->xBlockSize = 0;
- pxEnd->pxNextFreeBlock = NULL;
+ pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
/* To start with there is a single free block that is sized to take up the
* entire heap space, minus the space taken by pxEnd. */
- pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
- pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
- pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+ pxFirstFreeBlock = ( BlockLink_t * ) uxStartAddress;
+ pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxEndAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
+ pxFirstFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
@@ -446,11 +508,16 @@
/* Iterate through the list until a block is found that has a higher address
* than the block being inserted. */
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
{
/* Nothing to do here, just iterate to the right position. */
}
+ if( pxIterator != &xStart )
+ {
+ heapVALIDATE_BLOCK_POINTER( pxIterator );
+ }
+
/* Do the block being inserted, and the block it is being inserted after
* make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
@@ -469,17 +536,17 @@
* make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
{
- if( pxIterator->pxNextFreeBlock != pxEnd )
+ if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd )
{
/* Form one big block from the two blocks. */
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock;
}
else
{
- pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
}
}
else
@@ -487,13 +554,13 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
if( pxIterator != pxBlockToInsert )
{
- pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert );
}
else
{
@@ -509,7 +576,7 @@
vTaskSuspendAll();
{
- pxBlock = xStart.pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
/* pxBlock will be NULL if the heap has not been initialised. The heap
* is initialised automatically when the first allocation is made. */
@@ -533,7 +600,7 @@
/* Move to the next block in the chain until the last block is
* reached. */
- pxBlock = pxBlock->pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
}
}
}
@@ -553,3 +620,19 @@
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+ pxEnd = NULL;
+
+ xFreeBytesRemaining = ( size_t ) 0U;
+ xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+ xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+ xNumberOfSuccessfulFrees = ( size_t ) 0U;
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/MemMang/heap_5.c b/Source/portable/MemMang/heap_5.c
index 79b3a8a..dcfcca7 100644
--- a/Source/portable/MemMang/heap_5.c
+++ b/Source/portable/MemMang/heap_5.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -28,7 +28,7 @@
/*
* A sample implementation of pvPortMalloc() that allows the heap to be defined
- * across multiple non-contigous blocks and combines (coalescences) adjacent
+ * across multiple non-contiguous blocks and combines (coalescences) adjacent
* memory blocks as they are freed.
*
* See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
@@ -99,10 +99,13 @@
#define heapSIZE_MAX ( ~( ( size_t ) 0 ) )
/* Check if multiplying a and b will result in overflow. */
-#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
/* Check if adding a and b will result in overflow. */
-#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* Check if the subtraction operation ( a - b ) will result in underflow. */
+#define heapSUBTRACT_WILL_UNDERFLOW( a, b ) ( ( a ) < ( b ) )
/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
* the allocation status of a block. When MSB of the xBlockSize member of
@@ -114,14 +117,48 @@
#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )
#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )
+/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers
+ * protection using an application supplied canary value to catch heap
+ * corruption should a heap buffer overflow occur.
+ */
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/* Macro to load/store BlockLink_t pointers to memory. By XORing the
+ * pointers with a random canary value, heap overflows will result
+ * in randomly unpredictable pointer values which will be caught by
+ * heapVALIDATE_BLOCK_POINTER assert. */
+ #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) )
+
+/* Assert that a heap block pointer is within the heap bounds.
+ * Setting configVALIDATE_HEAP_BLOCK_POINTER to 1 enables customized heap block pointers
+ * protection on heap_5. */
+ #ifndef configVALIDATE_HEAP_BLOCK_POINTER
+ #define heapVALIDATE_BLOCK_POINTER( pxBlock ) \
+ configASSERT( ( pucHeapHighAddress != NULL ) && \
+ ( pucHeapLowAddress != NULL ) && \
+ ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \
+ ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) )
+ #else /* ifndef configVALIDATE_HEAP_BLOCK_POINTER */
+ #define heapVALIDATE_BLOCK_POINTER( pxBlock ) \
+ configVALIDATE_HEAP_BLOCK_POINTER( pxBlock )
+ #endif /* configVALIDATE_HEAP_BLOCK_POINTER */
+
+#else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */
+
+ #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( pxBlock )
+
+ #define heapVALIDATE_BLOCK_POINTER( pxBlock )
+
+#endif /* configENABLE_HEAP_PROTECTOR */
+
/*-----------------------------------------------------------*/
/* Define the linked list structure. This is used to link free blocks in order
* of their memory address. */
typedef struct A_BLOCK_LINK
{
- struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
- size_t xBlockSize; /*<< The size of the free block. */
+ struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
} BlockLink_t;
/*-----------------------------------------------------------*/
@@ -132,7 +169,18 @@
* the block in front it and/or the block behind it if the memory blocks are
* adjacent to each other.
*/
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/**
+ * @brief Application provided function to get a random value to be used as canary.
+ *
+ * @param pxHeapCanary [out] Output parameter to return the canary value.
+ */
+ extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary );
+#endif /* configENABLE_HEAP_PROTECTOR */
/*-----------------------------------------------------------*/
@@ -141,15 +189,26 @@
static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart;
-static BlockLink_t * pxEnd = NULL;
+PRIVILEGED_DATA static BlockLink_t xStart;
+PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL;
/* Keeps track of the number of calls to allocate and free memory as well as the
* number of free bytes remaining, but says nothing about fragmentation. */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-static size_t xNumberOfSuccessfulAllocations = 0;
-static size_t xNumberOfSuccessfulFrees = 0;
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = ( size_t ) 0U;
+
+#if ( configENABLE_HEAP_PROTECTOR == 1 )
+
+/* Canary value for protecting internal heap pointers. */
+ PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary;
+
+/* Highest and lowest heap addresses used for heap block bounds checking. */
+ PRIVILEGED_DATA static uint8_t * pucHeapHighAddress = NULL;
+ PRIVILEGED_DATA static uint8_t * pucHeapLowAddress = NULL;
+
+#endif /* configENABLE_HEAP_PROTECTOR */
/*-----------------------------------------------------------*/
@@ -160,52 +219,53 @@
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
size_t xAdditionalRequiredSize;
+ size_t xAllocatedBlockSize = 0;
/* The heap must be initialised before the first call to
- * prvPortMalloc(). */
+ * pvPortMalloc(). */
configASSERT( pxEnd );
- vTaskSuspendAll();
+ if( xWantedSize > 0 )
{
- if( xWantedSize > 0 )
+ /* The wanted size must be increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
{
- /* The wanted size must be increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number
+ * of bytes. */
+ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
{
- xWantedSize += xHeapStructSize;
+ /* Byte alignment required. */
+ xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
- /* Ensure that blocks are always aligned to the required number
- * of bytes. */
- if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
{
- /* Byte alignment required. */
- xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
-
- if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
- {
- xWantedSize += xAdditionalRequiredSize;
- }
- else
- {
- xWantedSize = 0;
- }
+ xWantedSize += xAdditionalRequiredSize;
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
}
else
{
- xWantedSize = 0;
+ mtCOVERAGE_TEST_MARKER();
}
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ vTaskSuspendAll();
+ {
/* Check the block size we are trying to allocate is not so large that the
* top bit is set. The top bit of the block size member of the BlockLink_t
* structure is used to determine who owns the block - the application or
@@ -217,12 +277,14 @@
/* Traverse the list from the start (lowest address) block until
* one of adequate size is found. */
pxPreviousBlock = &xStart;
- pxBlock = xStart.pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
+ heapVALIDATE_BLOCK_POINTER( pxBlock );
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) )
{
pxPreviousBlock = pxBlock;
- pxBlock = pxBlock->pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
+ heapVALIDATE_BLOCK_POINTER( pxBlock );
}
/* If the end marker was reached then a block of adequate size
@@ -231,7 +293,8 @@
{
/* Return the memory space pointed to - jumping over the
* BlockLink_t structure at its start. */
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+ pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize );
+ heapVALIDATE_BLOCK_POINTER( pvReturn );
/* This block is being returned for use so must be taken out
* of the list of free blocks. */
@@ -239,6 +302,8 @@
/* If the block is larger than required it can be split into
* two. */
+ configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 );
+
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
{
/* This block is to be split into two. Create a new
@@ -246,6 +311,7 @@
* cast is used to prevent byte alignment warnings from the
* compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
/* Calculate the sizes of two blocks split from the
* single block. */
@@ -253,7 +319,8 @@
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+ pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock;
+ pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink );
}
else
{
@@ -271,10 +338,12 @@
mtCOVERAGE_TEST_MARKER();
}
+ xAllocatedBlockSize = pxBlock->xBlockSize;
+
/* The block is being returned - it is allocated and owned
* by the application and has no "next" block. */
heapALLOCATE_BLOCK( pxBlock );
- pxBlock->pxNextFreeBlock = NULL;
+ pxBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
xNumberOfSuccessfulAllocations++;
}
else
@@ -292,7 +361,10 @@
mtCOVERAGE_TEST_MARKER();
}
- traceMALLOC( pvReturn, xWantedSize );
+ traceMALLOC( pvReturn, xAllocatedBlockSize );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xAllocatedBlockSize;
}
( void ) xTaskResumeAll();
@@ -309,6 +381,7 @@
}
#endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
+ configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
return pvReturn;
}
/*-----------------------------------------------------------*/
@@ -327,19 +400,25 @@
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
+ heapVALIDATE_BLOCK_POINTER( pxLink );
configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
- configASSERT( pxLink->pxNextFreeBlock == NULL );
+ configASSERT( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) );
if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
- if( pxLink->pxNextFreeBlock == NULL )
+ if( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
heapFREE_BLOCK( pxLink );
#if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
{
- ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+ /* Check for underflow as this can occur if xBlockSize is
+ * overwritten in a heap block. */
+ if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 )
+ {
+ ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+ }
}
#endif
@@ -378,6 +457,12 @@
}
/*-----------------------------------------------------------*/
+void xPortResetHeapMinimumEverFreeHeapSize( void )
+{
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
void * pvPortCalloc( size_t xNum,
size_t xSize )
{
@@ -397,18 +482,23 @@
}
/*-----------------------------------------------------------*/
-static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
{
BlockLink_t * pxIterator;
uint8_t * puc;
/* Iterate through the list until a block is found that has a higher address
* than the block being inserted. */
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
{
/* Nothing to do here, just iterate to the right position. */
}
+ if( pxIterator != &xStart )
+ {
+ heapVALIDATE_BLOCK_POINTER( pxIterator );
+ }
+
/* Do the block being inserted, and the block it is being inserted after
* make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
@@ -427,17 +517,17 @@
* make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) )
{
- if( pxIterator->pxNextFreeBlock != pxEnd )
+ if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd )
{
/* Form one big block from the two blocks. */
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock;
}
else
{
- pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
}
}
else
@@ -445,13 +535,13 @@
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
- /* If the block being inserted plugged a gab, so was merged with the block
+ /* If the block being inserted plugged a gap, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
if( pxIterator != pxBlockToInsert )
{
- pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert );
}
else
{
@@ -460,7 +550,7 @@
}
/*-----------------------------------------------------------*/
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) /* PRIVILEGED_FUNCTION */
{
BlockLink_t * pxFirstFreeBlockInRegion = NULL;
BlockLink_t * pxPreviousFreeBlock;
@@ -473,6 +563,12 @@
/* Can only call once! */
configASSERT( pxEnd == NULL );
+ #if ( configENABLE_HEAP_PROTECTOR == 1 )
+ {
+ vApplicationGetRandomHeapCanary( &( xHeapCanary ) );
+ }
+ #endif
+
pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
while( pxHeapRegion->xSizeInBytes > 0 )
@@ -485,7 +581,7 @@
if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
{
xAddress += ( portBYTE_ALIGNMENT - 1 );
- xAddress &= ~portBYTE_ALIGNMENT_MASK;
+ xAddress &= ~( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK;
/* Adjust the size for the bytes lost to alignment. */
xTotalRegionSize -= ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress );
@@ -498,48 +594,68 @@
{
/* xStart is used to hold a pointer to the first item in the list of
* free blocks. The void cast is used to prevent compiler warnings. */
- xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
+ xStart.pxNextFreeBlock = ( BlockLink_t * ) heapPROTECT_BLOCK_POINTER( xAlignedHeap );
xStart.xBlockSize = ( size_t ) 0;
}
else
{
/* Should only get here if one region has already been added to the
* heap. */
- configASSERT( pxEnd != NULL );
+ configASSERT( pxEnd != heapPROTECT_BLOCK_POINTER( NULL ) );
/* Check blocks are passed in with increasing start addresses. */
- configASSERT( xAddress > ( size_t ) pxEnd );
+ configASSERT( ( size_t ) xAddress > ( size_t ) pxEnd );
}
+ #if ( configENABLE_HEAP_PROTECTOR == 1 )
+ {
+ if( ( pucHeapLowAddress == NULL ) ||
+ ( ( uint8_t * ) xAlignedHeap < pucHeapLowAddress ) )
+ {
+ pucHeapLowAddress = ( uint8_t * ) xAlignedHeap;
+ }
+ }
+ #endif /* configENABLE_HEAP_PROTECTOR */
+
/* Remember the location of the end marker in the previous region, if
* any. */
pxPreviousFreeBlock = pxEnd;
/* pxEnd is used to mark the end of the list of free blocks and is
* inserted at the end of the region space. */
- xAddress = xAlignedHeap + xTotalRegionSize;
- xAddress -= xHeapStructSize;
- xAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+ xAddress = xAlignedHeap + ( portPOINTER_SIZE_TYPE ) xTotalRegionSize;
+ xAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize;
+ xAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
pxEnd = ( BlockLink_t * ) xAddress;
pxEnd->xBlockSize = 0;
- pxEnd->pxNextFreeBlock = NULL;
+ pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL );
/* To start with there is a single free block in this region that is
* sized to take up the entire heap region minus the space taken by the
* free block structure. */
pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
pxFirstFreeBlockInRegion->xBlockSize = ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlockInRegion );
- pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
+ pxFirstFreeBlockInRegion->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd );
/* If this is not the first region that makes up the entire heap space
* then link the previous region to this region. */
if( pxPreviousFreeBlock != NULL )
{
- pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
+ pxPreviousFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxFirstFreeBlockInRegion );
}
xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
+ #if ( configENABLE_HEAP_PROTECTOR == 1 )
+ {
+ if( ( pucHeapHighAddress == NULL ) ||
+ ( ( ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize ) > pucHeapHighAddress ) )
+ {
+ pucHeapHighAddress = ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize;
+ }
+ }
+ #endif
+
/* Move onto the next HeapRegion_t structure. */
xDefinedRegions++;
pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
@@ -560,7 +676,7 @@
vTaskSuspendAll();
{
- pxBlock = xStart.pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock );
/* pxBlock will be NULL if the heap has not been initialised. The heap
* is initialised automatically when the first allocation is made. */
@@ -590,7 +706,7 @@
/* Move to the next block in the chain until the last block is
* reached. */
- pxBlock = pxBlock->pxNextFreeBlock;
+ pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock );
}
}
}
@@ -610,3 +726,24 @@
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vPortHeapResetState( void )
+{
+ pxEnd = NULL;
+
+ xFreeBytesRemaining = ( size_t ) 0U;
+ xMinimumEverFreeBytesRemaining = ( size_t ) 0U;
+ xNumberOfSuccessfulAllocations = ( size_t ) 0U;
+ xNumberOfSuccessfulFrees = ( size_t ) 0U;
+
+ #if ( configENABLE_HEAP_PROTECTOR == 1 )
+ pucHeapHighAddress = NULL;
+ pucHeapLowAddress = NULL;
+ #endif /* #if ( configENABLE_HEAP_PROTECTOR == 1 ) */
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/RVDS/ARM_CA9/port.c b/Source/portable/RVDS/ARM_CA9/port.c
index d418131..9fe6e4a 100644
--- a/Source/portable/RVDS/ARM_CA9/port.c
+++ b/Source/portable/RVDS/ARM_CA9/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -34,43 +34,43 @@
#include "task.h"
#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
- #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
- #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configUNIQUE_INTERRUPT_PRIORITIES
- #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#ifndef configSETUP_TICK_INTERRUPT
- #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif /* configSETUP_TICK_INTERRUPT */
#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
#endif
#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
- #if( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #if ( configMAX_PRIORITIES > 32 )
+ #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/* In case security extensions are implemented. */
#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
- #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+ #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
#endif
#ifndef configCLEAR_TICK_INTERRUPT
@@ -78,80 +78,80 @@
#endif
/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
+ * number of bits implemented by the interrupt controller. */
#if configUNIQUE_INTERRUPT_PRIORITIES == 16
- #define portPRIORITY_SHIFT 4
- #define portMAX_BINARY_POINT_VALUE 3
+ #define portPRIORITY_SHIFT 4
+ #define portMAX_BINARY_POINT_VALUE 3
#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
- #define portPRIORITY_SHIFT 3
- #define portMAX_BINARY_POINT_VALUE 2
+ #define portPRIORITY_SHIFT 3
+ #define portMAX_BINARY_POINT_VALUE 2
#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
- #define portPRIORITY_SHIFT 2
- #define portMAX_BINARY_POINT_VALUE 1
+ #define portPRIORITY_SHIFT 2
+ #define portMAX_BINARY_POINT_VALUE 1
#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
- #define portPRIORITY_SHIFT 1
- #define portMAX_BINARY_POINT_VALUE 0
+ #define portPRIORITY_SHIFT 1
+ #define portMAX_BINARY_POINT_VALUE 0
#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
- #define portPRIORITY_SHIFT 0
- #define portMAX_BINARY_POINT_VALUE 0
-#else
- #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
+ #define portPRIORITY_SHIFT 0
+ #define portMAX_BINARY_POINT_VALUE 0
+#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+ #error "Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware"
+#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
+ * this value. */
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE ( 0xFFUL )
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE ( 0xFFUL )
/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created. A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
+ * floating point context after they have been created. A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
+ * point is zero. */
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS ( 0x01UL )
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )
/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK ( 0x1F )
+#define portAPSR_MODE_BITS_MASK ( 0x1F )
/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE ( 0x10 )
+ * mode. */
+#define portAPSR_USER_MODE ( 0x10 )
/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK() \
-{ \
- __disable_irq(); \
- portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
- __asm( "DSB \n" \
- "ISB \n" ); \
- __enable_irq(); \
-}
+#define portCLEAR_INTERRUPT_MASK() \
+ { \
+ __disable_irq(); \
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+ __asm( "DSB \n" \
+ "ISB \n" ); \
+ __enable_irq(); \
+ }
/*-----------------------------------------------------------*/
@@ -169,29 +169,29 @@
/*-----------------------------------------------------------*/
/* A variable is used to keep track of the critical section nesting. This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts. As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts. As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
volatile uint32_t ulCriticalNesting = 9999UL;
/* Used to pass constants into the ASM code. The address at which variables are
-placed is the constant value so indirect loads in the asm code are not
-required. */
+ * placed is the constant value so indirect loads in the asm code are not
+ * required. */
uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
+ * a floating point context must be saved and restored for the task. */
uint32_t ulPortTaskHasFPUContext = pdFALSE;
/* Set to 1 to pend a context switch from an ISR. */
uint32_t ulPortYieldRequired = pdFALSE;
/* Counts the interrupt nesting depth. A context switch is only performed if
-if the nesting depth is 0. */
+ * if the nesting depth is 0. */
uint32_t ulPortInterruptNesting = 0UL;
/*-----------------------------------------------------------*/
@@ -199,14 +199,16 @@
/*
* See header file for description.
*/
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+ TaskFunction_t pxCode,
+ void * pvParameters )
{
/* Setup the initial stack of the task. The stack is set exactly as
- expected by the portRESTORE_CONTEXT() macro.
-
- The fist real value on the stack is the status register, which is set for
- system mode, with interrupts enabled. A few NULLs are added first to ensure
- GDB does not try decoding a non-existent return address. */
+ * expected by the portRESTORE_CONTEXT() macro.
+ *
+ * The fist real value on the stack is the status register, which is set for
+ * system mode, with interrupts enabled. A few NULLs are added first to ensure
+ * GDB does not try decoding a non-existent return address. */
*pxTopOfStack = NULL;
pxTopOfStack--;
*pxTopOfStack = NULL;
@@ -228,43 +230,43 @@
pxTopOfStack--;
/* Next all the registers other than the stack pointer. */
- *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack--;
/* The task will start with a critical nesting count of 0 as interrupts are
- enabled. */
+ * enabled. */
*pxTopOfStack = portNO_CRITICAL_NESTING;
pxTopOfStack--;
/* The task will start without a floating point context. A task that uses
- the floating point hardware must call vPortTaskUsesFPU() before executing
- any floating point instructions. */
+ * the floating point hardware must call vPortTaskUsesFPU() before executing
+ * any floating point instructions. */
*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
return pxTopOfStack;
@@ -274,23 +276,26 @@
static void prvTaskExitError( void )
{
/* A function that implements a task must not exit or attempt to return to
- its caller as there is nothing to return to. If a task wants to exit it
- should instead call vTaskDelete( NULL ).
-
- Artificially force an assert() to be triggered if configASSERT() is
- defined, then stop here so application writers can catch the error. */
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ).
+ *
+ * Artificially force an assert() to be triggered if configASSERT() is
+ * defined, then stop here so application writers can catch the error. */
configASSERT( ulPortInterruptNesting == ~0UL );
portDISABLE_INTERRUPTS();
- for( ;; );
+
+ for( ; ; )
+ {
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
-uint32_t ulAPSR;
+ uint32_t ulAPSR;
/* Only continue if the CPU is not in User mode. The CPU must be in a
- Privileged mode for the scheduler to start. */
+ * Privileged mode for the scheduler to start. */
__asm( "MRS ulAPSR, APSR" );
ulAPSR &= portAPSR_MODE_BITS_MASK;
configASSERT( ulAPSR != portAPSR_USER_MODE );
@@ -298,8 +303,8 @@
if( ulAPSR != portAPSR_USER_MODE )
{
/* Only continue if the binary point value is set to its lowest possible
- setting. See the comments in vPortValidateInterruptPriority() below for
- more information. */
+ * setting. See the comments in vPortValidateInterruptPriority() below for
+ * more information. */
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
@@ -313,8 +318,8 @@
}
/* Will only get here if vTaskStartScheduler() was called with the CPU in
- a non-privileged mode or the binary point register was not set to its lowest
- possible value. */
+ * a non-privileged mode or the binary point register was not set to its lowest
+ * possible value. */
return 0;
}
/*-----------------------------------------------------------*/
@@ -322,7 +327,7 @@
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
- Artificially force an assert. */
+ * Artificially force an assert. */
configASSERT( ulCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
@@ -332,16 +337,16 @@
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
ulPortSetInterruptMask();
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- directly. Increment ulCriticalNesting to keep a count of how many times
- portENTER_CRITICAL() has been called. */
+ /* Now that interrupts are disabled, ulCriticalNesting can be accessed
+ * directly. Increment ulCriticalNesting to keep a count of how many times
+ * portENTER_CRITICAL() has been called. */
ulCriticalNesting++;
/* This is not the interrupt safe version of the enter critical function so
- assert() if it is being called from an interrupt context. Only API
- functions that end in "FromISR" can be used in an interrupt. Only assert if
- the critical nesting count is 1 to protect against recursive calls if the
- assert function also uses a critical section. */
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
if( ulCriticalNesting == 1 )
{
configASSERT( ulPortInterruptNesting == 0 );
@@ -354,15 +359,15 @@
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
{
/* Decrement the nesting count as the critical section is being
- exited. */
+ * exited. */
ulCriticalNesting--;
/* If the nesting level has reached zero then all interrupt
- priorities must be re-enabled. */
+ * priorities must be re-enabled. */
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
{
/* Critical nesting has reached zero so all interrupt priorities
- should be unmasked. */
+ * should be unmasked. */
portCLEAR_INTERRUPT_MASK();
}
}
@@ -372,12 +377,12 @@
void FreeRTOS_Tick_Handler( void )
{
/* Set interrupt mask before altering scheduler structures. The tick
- handler runs at the lowest priority, so interrupts cannot already be masked,
- so there is no need to save and restore the current mask value. */
+ * handler runs at the lowest priority, so interrupts cannot already be masked,
+ * so there is no need to save and restore the current mask value. */
__disable_irq();
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n" );
+ __asm( "DSB \n"
+ "ISB \n" );
__enable_irq();
/* Increment the RTOS tick. */
@@ -394,10 +399,10 @@
void vPortTaskUsesFPU( void )
{
-uint32_t ulInitialFPSCR = 0;
+ uint32_t ulInitialFPSCR = 0;
/* A task is registering the fact that it needs an FPU context. Set the
- FPU flag (which is saved as part of the task context). */
+ * FPU flag (which is saved as part of the task context). */
ulPortTaskHasFPUContext = pdTRUE;
/* Initialise the floating point status register. */
@@ -416,9 +421,10 @@
uint32_t ulPortSetInterruptMask( void )
{
-uint32_t ulReturn;
+ uint32_t ulReturn;
__disable_irq();
+
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
{
/* Interrupts were already masked. */
@@ -428,49 +434,50 @@
{
ulReturn = pdFALSE;
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
- __asm( "DSB \n"
- "ISB \n" );
+ __asm( "DSB \n"
+ "ISB \n" );
}
+
__enable_irq();
return ulReturn;
}
/*-----------------------------------------------------------*/
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
/* The following assertion will fail if a service routine (ISR) for
- an interrupt that has been assigned a priority above
- configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- function. ISR safe FreeRTOS API functions must *only* be called
- from interrupts that have been assigned a priority at or below
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- Numerically low interrupt priority numbers represent logically high
- interrupt priorities, therefore the priority of the interrupt must
- be set to a value equal to or numerically *higher* than
- configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
- FreeRTOS maintains separate thread and ISR API functions to ensure
- interrupt entry is as fast and simple as possible.
-
- The following links provide detailed information:
- https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- https://www.FreeRTOS.org/FAQHelp.html */
+ * an interrupt that has been assigned a priority above
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ * function. ISR safe FreeRTOS API functions must *only* be called
+ * from interrupts that have been assigned a priority at or below
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * Numerically low interrupt priority numbers represent logically high
+ * interrupt priorities, therefore the priority of the interrupt must
+ * be set to a value equal to or numerically *higher* than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ *
+ * FreeRTOS maintains separate thread and ISR API functions to ensure
+ * interrupt entry is as fast and simple as possible.
+ *
+ * The following links provide detailed information:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
/* Priority grouping: The interrupt controller (GIC) allows the bits
- that define each interrupt's priority to be split between bits that
- define the interrupt's pre-emption priority bits and bits that define
- the interrupt's sub-priority. For simplicity all bits must be defined
- to be pre-emption priority bits. The following assertion will fail if
- this is not the case (if some bits represent a sub-priority).
-
- The priority grouping is configured by the GIC's binary point register
- (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
- possible value (which may be above 0). */
+ * that define each interrupt's priority to be split between bits that
+ * define the interrupt's pre-emption priority bits and bits that define
+ * the interrupt's sub-priority. For simplicity all bits must be defined
+ * to be pre-emption priority bits. The following assertion will fail if
+ * this is not the case (if some bits represent a sub-priority).
+ *
+ * The priority grouping is configured by the GIC's binary point register
+ * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
+ * possible value (which may be above 0). */
configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
}
diff --git a/Source/portable/RVDS/ARM_CA9/portASM.s b/Source/portable/RVDS/ARM_CA9/portASM.s
index bd36f2e..7184d22 100644
--- a/Source/portable/RVDS/ARM_CA9/portASM.s
+++ b/Source/portable/RVDS/ARM_CA9/portASM.s
@@ -1,6 +1,6 @@
;/*
-; * FreeRTOS Kernel V10.6.2
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; * FreeRTOS Kernel V11.2.0
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
@@ -143,7 +143,7 @@
MOVS PC, LR
switch_before_exit
- ; A context swtich is to be performed. Clear the context switch pending
+ ; A context switch is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
diff --git a/Source/portable/RVDS/ARM_CA9/portmacro.h b/Source/portable/RVDS/ARM_CA9/portmacro.h
index 35e4887..d59527d 100644
--- a/Source/portable/RVDS/ARM_CA9/portmacro.h
+++ b/Source/portable/RVDS/ARM_CA9/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -46,61 +46,61 @@
*/
/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
-#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
#else
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
#endif
/*-----------------------------------------------------------*/
/* Hardware specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Task utilities. */
/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{ \
-extern uint32_t ulPortYieldRequired; \
- \
- if( xSwitchRequired != pdFALSE ) \
- { \
- ulPortYieldRequired = pdTRUE; \
- } \
-}
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ { \
+ extern uint32_t ulPortYieldRequired; \
+ \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ ulPortYieldRequired = pdTRUE; \
+ } \
+ }
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm( "SWI 0" );
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm( "SWI 0" );
/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
+* Critical section control
+*----------------------------------------------------------*/
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
@@ -108,57 +108,57 @@
extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
/* These macros do not globally disable/enable interrupts. They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL() vPortEnterCritical();
+#define portEXIT_CRITICAL() vPortExitCritical();
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x )
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/* Prototype of the FreeRTOS tick handler. This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
+ * handler for whichever peripheral is used to generate the RTOS tick. */
void FreeRTOS_Tick_Handler( void );
/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
+ * before any floating point instructions are executed. */
void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
/* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
- /* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
- /*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
-#define portNOP() __nop()
+#define portNOP() __nop()
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/RVDS/ARM_CA9/portmacro.inc b/Source/portable/RVDS/ARM_CA9/portmacro.inc
index cfcdc58..574069d 100644
--- a/Source/portable/RVDS/ARM_CA9/portmacro.inc
+++ b/Source/portable/RVDS/ARM_CA9/portmacro.inc
@@ -1,6 +1,6 @@
;/*
-; * FreeRTOS Kernel V10.6.2
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; * FreeRTOS Kernel V11.2.0
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
diff --git a/Source/portable/RVDS/ARM_CM0/port.c b/Source/portable/RVDS/ARM_CM0/port.c
index 169e262..378a850 100644
--- a/Source/portable/RVDS/ARM_CM0/port.c
+++ b/Source/portable/RVDS/ARM_CM0/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -352,13 +352,19 @@
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
diff --git a/Source/portable/RVDS/ARM_CM0/portmacro.h b/Source/portable/RVDS/ARM_CM0/portmacro.h
index e75c8ef..5fad46d 100644
--- a/Source/portable/RVDS/ARM_CM0/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -86,9 +86,19 @@
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portYIELD() vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired ) \
- do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
- while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
diff --git a/Source/portable/RVDS/ARM_CM3/port.c b/Source/portable/RVDS/ARM_CM3/port.c
index d39491d..9f95488 100644
--- a/Source/portable/RVDS/ARM_CM3/port.c
+++ b/Source/portable/RVDS/ARM_CM3/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -310,22 +310,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -449,14 +449,21 @@
* known - therefore the slightly faster vPortRaiseBASEPRI() function is used
* in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
vPortRaiseBASEPRI();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
vPortClearBASEPRIFromISR();
@@ -763,7 +770,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/RVDS/ARM_CM3/portmacro.h b/Source/portable/RVDS/ARM_CM3/portmacro.h
index 2455220..71e4983 100644
--- a/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,45 +47,45 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/* Constants used with memory barrier intrinsics. */
- #define portSY_FULL_READ_WRITE ( 15 )
+#define portSY_FULL_READ_WRITE ( 15 )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,167 +97,179 @@
}
/*-----------------------------------------------------------*/
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Port specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
- #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE __forceinline
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE __forceinline
+#endif
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+ __asm
{
- __asm
- {
- /* Barrier instructions are not used as this function is only used to
- * lower the BASEPRI value. */
+ /* Barrier instructions are not used as this function is only used to
+ * lower the BASEPRI value. */
/* *INDENT-OFF* */
msr basepri, ulBASEPRI
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
+ __asm
+ {
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
/* *INDENT-OFF* */
msr basepri, ulNewBASEPRI
dsb
isb
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+ __asm
{
- __asm
- {
- /* Set BASEPRI to 0 so no interrupts are masked. This function is only
- * used to lower the mask in an interrupt, so memory barriers are not
- * used. */
+ /* Set BASEPRI to 0 so no interrupts are masked. This function is only
+ * used to lower the mask in an interrupt, so memory barriers are not
+ * used. */
/* *INDENT-OFF* */
msr basepri, # 0
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
+ __asm
+ {
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
/* *INDENT-OFF* */
mrs ulReturn, basepri
msr basepri, ulNewBASEPRI
dsb
isb
/* *INDENT-ON* */
- }
-
- return ulReturn;
}
+
+ return ulReturn;
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
- {
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
- /* Obtain the number of the currently executing interrupt. */
- __asm
- {
+ /* Obtain the number of the currently executing interrupt. */
+ __asm
+ {
/* *INDENT-OFF* */
mrs ulCurrentInterrupt, ipsr
/* *INDENT-ON* */
- }
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
}
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+
/* *INDENT-OFF* */
#ifdef __cplusplus
diff --git a/Source/portable/RVDS/ARM_CM4F/port.c b/Source/portable/RVDS/ARM_CM4F/port.c
index 05ef20c..54c53ce 100644
--- a/Source/portable/RVDS/ARM_CM4F/port.c
+++ b/Source/portable/RVDS/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -376,22 +376,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -545,14 +545,21 @@
* known - therefore the slightly faster vPortRaiseBASEPRI() function is used
* in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
vPortRaiseBASEPRI();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
vPortClearBASEPRIFromISR();
@@ -859,7 +866,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Source/portable/RVDS/ARM_CM4F/portmacro.h
index d79c9b4..1ed12dd 100644
--- a/Source/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,45 +47,45 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/* Constants used with memory barrier intrinsics. */
- #define portSY_FULL_READ_WRITE ( 15 )
+#define portSY_FULL_READ_WRITE ( 15 )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,167 +97,179 @@
}
/*-----------------------------------------------------------*/
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Port specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
- #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE __forceinline
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE __forceinline
+#endif
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+ __asm
{
- __asm
- {
- /* Barrier instructions are not used as this function is only used to
- * lower the BASEPRI value. */
+ /* Barrier instructions are not used as this function is only used to
+ * lower the BASEPRI value. */
/* *INDENT-OFF* */
msr basepri, ulBASEPRI
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
+ __asm
+ {
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
/* *INDENT-OFF* */
msr basepri, ulNewBASEPRI
dsb
isb
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+ __asm
{
- __asm
- {
- /* Set BASEPRI to 0 so no interrupts are masked. This function is only
- * used to lower the mask in an interrupt, so memory barriers are not
- * used. */
+ /* Set BASEPRI to 0 so no interrupts are masked. This function is only
+ * used to lower the mask in an interrupt, so memory barriers are not
+ * used. */
/* *INDENT-OFF* */
msr basepri, # 0
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
+ __asm
+ {
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
/* *INDENT-OFF* */
mrs ulReturn, basepri
msr basepri, ulNewBASEPRI
dsb
isb
/* *INDENT-ON* */
- }
-
- return ulReturn;
}
+
+ return ulReturn;
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
- {
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
- /* Obtain the number of the currently executing interrupt. */
- __asm
- {
+ /* Obtain the number of the currently executing interrupt. */
+ __asm
+ {
/* *INDENT-OFF* */
mrs ulCurrentInterrupt, ipsr
/* *INDENT-ON* */
- }
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
}
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
index 80f0ee1..76a50bb 100644
--- a/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
+++ b/Source/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -60,12 +60,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv
- pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
}
@@ -84,12 +83,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv
- pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
}
@@ -108,12 +106,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv
- pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTaskDelay
}
@@ -132,12 +129,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv
- pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
}
@@ -156,12 +152,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv
- pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv
- pop {r0}
svc #SYSTEM_CALL_eTaskGetState
}
@@ -186,12 +181,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv
- pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
}
@@ -210,12 +204,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv
- pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
}
@@ -234,12 +227,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv
- pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
}
@@ -258,12 +250,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv
- pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTaskResume
}
@@ -280,12 +271,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv
- pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
}
/*-----------------------------------------------------------*/
@@ -300,36 +290,15 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv
- pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
}
/*-----------------------------------------------------------*/
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
-
-__asm char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
-{
- PRESERVE8
- extern MPU_pcTaskGetNameImpl
-
- push {r0}
- mrs r0, control
- tst r0, #1
- bne MPU_pcTaskGetName_Unpriv
-MPU_pcTaskGetName_Priv
- pop {r0}
- b MPU_pcTaskGetNameImpl
-MPU_pcTaskGetName_Unpriv
- pop {r0}
- svc #SYSTEM_CALL_pcTaskGetName
-}
-/*-----------------------------------------------------------*/
-
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
@@ -342,12 +311,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv
- pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
}
@@ -366,12 +334,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv
- pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
}
@@ -390,12 +357,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv
- pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
}
@@ -414,12 +380,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv
- pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv
- pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
}
@@ -440,12 +405,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv
- pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
}
@@ -464,12 +428,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv
- pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
}
@@ -492,12 +455,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv
- pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
}
@@ -518,12 +480,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv
- pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
- pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
}
@@ -546,12 +507,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv
- pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
}
@@ -570,12 +530,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv
- pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
}
@@ -594,12 +553,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv
- pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
}
@@ -618,12 +576,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv
- pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
}
@@ -642,12 +599,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv
- pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
}
@@ -664,12 +620,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv
- pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
}
/*-----------------------------------------------------------*/
@@ -686,12 +641,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv
- pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
}
/*-----------------------------------------------------------*/
@@ -708,12 +662,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv
- pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
}
@@ -732,12 +685,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv
- pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
}
@@ -760,12 +712,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv
- pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
}
@@ -786,12 +737,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv
- pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
}
@@ -814,12 +764,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv
- pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv
- pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
}
@@ -842,12 +791,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv
- pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
}
/*-----------------------------------------------------------*/
@@ -862,12 +810,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv
- pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
}
/*-----------------------------------------------------------*/
@@ -882,12 +829,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv
- pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
}
/*-----------------------------------------------------------*/
@@ -906,12 +852,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv
- pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueReceive
}
/*-----------------------------------------------------------*/
@@ -930,12 +875,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv
- pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueuePeek
}
/*-----------------------------------------------------------*/
@@ -952,12 +896,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv
- pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
}
/*-----------------------------------------------------------*/
@@ -974,12 +917,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv
- pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
}
@@ -1000,12 +942,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv
- pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
}
@@ -1024,12 +965,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv
- pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
}
@@ -1050,12 +990,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv
- pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
}
@@ -1076,12 +1015,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv
- pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
}
@@ -1102,12 +1040,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv
- pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
}
@@ -1126,12 +1063,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv
- pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
}
@@ -1150,12 +1086,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv
- pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv
- pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
}
@@ -1174,12 +1109,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv
- pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv
- pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
}
@@ -1200,12 +1134,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv
- pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
}
@@ -1224,12 +1157,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv
- pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
}
@@ -1248,12 +1180,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv
- pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
}
@@ -1262,26 +1193,22 @@
#if ( configUSE_TIMERS == 1 )
-BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
-__asm BaseType_t MPU_xTimerGenericCommandEntry( const xTimerGenericCommandParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
+__asm BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
{
PRESERVE8
- extern MPU_xTimerGenericCommandPrivImpl
+ extern MPU_xTimerGenericCommandFromTaskImpl
push {r0}
- mrs r0, ipsr
- cmp r0, #0
- bne MPU_xTimerGenericCommand_Priv
mrs r0, control
tst r0, #1
- beq MPU_xTimerGenericCommand_Priv
-MPU_xTimerGenericCommand_Unpriv
- pop {r0}
- svc #SYSTEM_CALL_xTimerGenericCommand
-MPU_xTimerGenericCommand_Priv
- pop {r0}
- b MPU_xTimerGenericCommandPrivImpl
+ pop {r0}
+ bne MPU_xTimerGenericCommandFromTask_Unpriv
+MPU_xTimerGenericCommandFromTask_Priv
+ b MPU_xTimerGenericCommandFromTaskImpl
+MPU_xTimerGenericCommandFromTask_Unpriv
+ svc #SYSTEM_CALL_xTimerGenericCommandFromTask
}
#endif /* if ( configUSE_TIMERS == 1 ) */
@@ -1299,12 +1226,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv
- pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv
- pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
}
@@ -1314,10 +1240,10 @@
#if ( configUSE_TIMERS == 1 )
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+ const BaseType_t xAutoReload ) FREERTOS_SYSTEM_CALL;
__asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const BaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+ const BaseType_t xAutoReload ) /* FREERTOS_SYSTEM_CALL */
{
PRESERVE8
extern MPU_vTimerSetReloadModeImpl
@@ -1325,12 +1251,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv
- pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
}
@@ -1349,12 +1274,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv
- pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
}
@@ -1373,12 +1297,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv
- pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
}
@@ -1397,12 +1320,11 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv
- pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
}
@@ -1421,18 +1343,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv
- pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
}
#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_EVENT_GROUPS == 1 )
+
EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
__asm EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */
@@ -1443,16 +1366,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv
- pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
}
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_EVENT_GROUPS == 1 )
+
EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
@@ -1465,16 +1391,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv
- pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
}
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_EVENT_GROUPS == 1 )
+
EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
@@ -1487,16 +1416,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv
- pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
}
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_EVENT_GROUPS == 1 )
+
EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet,
const EventBits_t uxBitsToWaitFor,
@@ -1513,17 +1445,18 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv
- pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
}
+
+#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */
/*-----------------------------------------------------------*/
-#if ( configUSE_TRACE_FACILITY == 1 )
+#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
@@ -1535,19 +1468,18 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv
- pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv
- pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
}
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+#endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
-#if ( configUSE_TRACE_FACILITY == 1 )
+#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void MPU_vEventGroupSetNumber( void * xEventGroup,
UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
@@ -1561,18 +1493,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv
- pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv
- pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
}
-#endif /*( configUSE_TRACE_FACILITY == 1 )*/
+#endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
const void * pvTxData,
size_t xDataLengthBytes,
@@ -1589,16 +1522,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv
- pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
void * pvRxData,
size_t xBufferLengthBytes,
@@ -1615,16 +1551,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv
- pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
__asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1635,16 +1574,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv
- pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
__asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1655,16 +1597,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv
- pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
__asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1675,16 +1620,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv
- pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
__asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1695,16 +1643,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv
- pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
@@ -1717,16 +1668,19 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv
- pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
__asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
@@ -1737,14 +1691,15 @@
push {r0}
mrs r0, control
tst r0, #1
+ pop {r0}
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv
- pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv
- pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
}
+
+#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */
/*-----------------------------------------------------------*/
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
diff --git a/Source/portable/RVDS/ARM_CM4_MPU/port.c b/Source/portable/RVDS/ARM_CM4_MPU/port.c
index b5c4cb9..a491d4b 100644
--- a/Source/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/Source/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -51,6 +51,9 @@
#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
#endif
+/* Prototype of all Interrupt Service Routines (ISRs). */
+typedef void ( * portISR_t )( void );
+
/* Constants required to access and manipulate the NVIC. */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
@@ -87,7 +90,6 @@
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
/* Constants required to manipulate the VFP. */
#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
@@ -99,6 +101,11 @@
#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
+/* Constants used to check the installation of the FreeRTOS interrupt handlers. */
+#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
+#define portVECTOR_INDEX_SVC ( 11 )
+#define portVECTOR_INDEX_PENDSV ( 14 )
+
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
@@ -142,14 +149,14 @@
* switches can only occur when uxCriticalNesting is zero. */
PRIVILEGED_DATA static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
/*
* This variable is set to pdTRUE when the scheduler is started.
*/
PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
-#endif
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*
* Setup the timer to generate the tick interrupts.
@@ -230,6 +237,11 @@
void vResetPrivilege( void );
/**
+ * @brief Make a task unprivileged.
+ */
+void vPortSwitchToUserMode( void );
+
+/**
* @brief Enter critical section.
*/
#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
@@ -283,13 +295,13 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
- /**
- * @brief Sets up the task stack so that upon returning from
- * SVC, the task stack is used again.
- *
- * @param pulSystemCallStack The current SP when the SVC was raised.
- * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
- */
+/**
+ * @brief Sets up the task stack so that upon returning from
+ * SVC, the task stack is used again.
+ *
+ * @param pulSystemCallStack The current SP when the SVC was raised.
+ * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
+ */
void vSystemCallExit( uint32_t * pulSystemCallStack,
uint32_t ulLR ) PRIVILEGED_FUNCTION;
@@ -319,28 +331,29 @@
}
else
{
- xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
+ xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
}
- xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
- xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
- xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
- xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
- xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
- xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
- xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
- xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
- xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
- xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
- xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
- xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
- xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
- xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
- xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
- xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
+ xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
+ xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
+ xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
+ xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
+ xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
+ xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
+ xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
+ xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
+ xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
+
+ xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
+ xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
+ xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
+ xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
+ xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
+ xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
+ xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
- xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
+ xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
@@ -380,7 +393,6 @@
switch( ucSVCNumber )
{
case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
prvRestoreContextOfFirstTask();
break;
@@ -519,7 +531,7 @@
__asm
{
mrs r1, control /* Obtain current control value. */
- bic r1, #1 /* Clear nPRIV bit. */
+ bic r1, # 1 /* Clear nPRIV bit. */
msr control, r1 /* Write back new control value. */
};
@@ -535,7 +547,6 @@
/* Start executing the system call upon returning from this handler. */
pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
-
/* Raise a request to exit from the system call upon finishing the
* system call. */
pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
@@ -634,7 +645,7 @@
__asm
{
mrs r1, control /* Obtain current control value. */
- orr r1, #1 /* Set nPRIV bit. */
+ orr r1, # 1 /* Set nPRIV bit. */
msr control, r1 /* Write back new control value. */
};
@@ -680,13 +691,13 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-/* *INDENT-OFF* */
-__asm void vPortSVCHandler( void )
-{
- extern vSVCHandler_C
- extern vSystemCallEnter
- extern vSystemCallExit
+ __asm void vPortSVCHandler( void )
+ {
+ extern vSVCHandler_C
+ extern vSystemCallEnter
+ extern vSystemCallExit
+/* *INDENT-OFF* */
PRESERVE8
tst lr, #4
@@ -709,15 +720,17 @@
syscall_exit
mov r1, lr
b vSystemCallExit
-}
+/* *INDENT-ON* */
+ }
#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
-__asm void vPortSVCHandler( void )
-{
- extern vSVCHandler_C
+ __asm void vPortSVCHandler( void )
+ {
+ extern vSVCHandler_C
- PRESERVE8
+/* *INDENT-OFF* */
+ PRESERVE8
/* Assumes psp was in use. */
#ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
@@ -730,8 +743,8 @@
#endif
b vSVCHandler_C
-}
/* *INDENT-ON* */
+ }
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
@@ -758,14 +771,14 @@
str r3, [r0] /* Disable MPU. */
ldr r0, =0xe000ed9c /* Region Base Address register. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
#if ( configTOTAL_MPU_REGIONS == 16 )
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* configTOTAL_MPU_REGIONS == 16. */
ldr r0, =0xe000ed94 /* MPU_CTRL register. */
@@ -807,6 +820,7 @@
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
#else
+
/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
* configENABLE_ERRATA_837070_WORKAROUND to 1 in your
* FreeRTOSConfig.h. */
@@ -814,6 +828,40 @@
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#endif
+ /* An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ * 1. Direct Routing - Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
+ * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
+ * interrupts and route program control from those handlers to
+ * vPortSVCHandler and xPortPendSVHandler functions.
+ *
+ * Applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
+ * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
+ * is 1, should be preferred when possible. */
+ #if ( configCHECK_HANDLER_INSTALLATION == 1 )
+ {
+ const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
+
+ /* Validate that the application has correctly installed the FreeRTOS
+ * handlers for SVCall and PendSV interrupts. We do not check the
+ * installation of the SysTick handler because the application may
+ * choose to drive the RTOS tick using a timer other than the SysTick
+ * timer by overriding the weak function vPortSetupTimerInterrupt().
+ *
+ * Assertion failures here indicate incorrect installation of the
+ * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
+ * https://www.freertos.org/Why-FreeRTOS/FAQs.
+ *
+ * Systems with a configurable address for the interrupt vector table
+ * can also encounter assertion failures or even system faults here if
+ * VTOR is not set correctly to point to the application's vector table. */
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
+ configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
+ }
+ #endif /* configCHECK_HANDLER_INSTALLATION */
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
@@ -899,10 +947,11 @@
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the same priority as the kernel, and the SVC
- * handler higher priority so it can be used to exit a critical section (where
- * lower priorities are masked). */
+ * handler highest priority so it can be used to exit a critical section
+ * (where lower priorities are masked). */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+ portNVIC_SHPR2_REG = 0;
/* Configure the regions in the MPU that are common to all tasks. */
prvSetupMPU();
@@ -914,11 +963,11 @@
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
- #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
+ #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
{
xSchedulerRunning = pdTRUE;
}
- #endif
+ #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
@@ -1099,14 +1148,14 @@
str r3, [r0] /* Disable MPU. */
ldr r0, =0xe000ed9c /* Region Base Address register. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
#if ( configTOTAL_MPU_REGIONS == 16 )
+ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* configTOTAL_MPU_REGIONS == 16. */
ldr r0, =0xe000ed94 /* MPU_CTRL register. */
@@ -1143,13 +1192,19 @@
uint32_t ulDummy;
ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
}
@@ -1171,19 +1226,6 @@
}
/*-----------------------------------------------------------*/
-__asm void vPortSwitchToUserMode( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- mrs r0, control
- orr r0, #1
- msr control, r0
- bx r14
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
__asm void vPortEnableVFP( void )
{
/* *INDENT-OFF* */
@@ -1195,6 +1237,7 @@
orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
str r1, [ r0 ]
bx r14
+ nop
/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
@@ -1299,10 +1342,10 @@
PRESERVE8
mrs r0, control /* r0 = CONTROL. */
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
bx lr /* Return. */
/* *INDENT-ON* */
}
@@ -1313,18 +1356,31 @@
/* *INDENT-OFF* */
PRESERVE8
- mrs r0, control /* r0 = CONTROL. */
- orrs r0, #1 /* r0 = r0 | 1. */
- msr control, r0 /* CONTROL = r0. */
- bx lr /* Return. */
+ mrs r0, control /* r0 = CONTROL. */
+ orrs r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return. */
/* *INDENT-ON* */
}
/*-----------------------------------------------------------*/
+void vPortSwitchToUserMode( void )
+{
+ /* Load the current task's MPU settings from its TCB. */
+ xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
+
+ /* Mark the task as unprivileged. */
+ xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
+
+ /* Lower the processor's privilege level. */
+ vResetPrivilege();
+}
+/*-----------------------------------------------------------*/
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
const struct xMEMORY_REGION * const xRegions,
StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
+ configSTACK_DEPTH_TYPE uxStackDepth )
{
extern uint32_t __SRAM_segment_start__;
extern uint32_t __SRAM_segment_end__;
@@ -1371,7 +1427,7 @@
* which case the stack region parameters will be valid. At all other
* times the stack parameters will not be valid and it is assumed that the
* stack region has already been configured. */
- if( ulStackDepth > 0 )
+ if( uxStackDepth > 0 )
{
/* Define the region that allows access to the stack. */
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
@@ -1382,13 +1438,13 @@
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
( portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+ ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( portMPU_REGION_ENABLE );
xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
- ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
+ ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
tskMPU_WRITE_PERMISSION );
}
@@ -1443,45 +1499,58 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
- uint32_t ulBufferLength,
- uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
+#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-{
- uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
- BaseType_t xAccessGranted = pdFALSE;
- const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+ BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
+ uint32_t ulBufferLength,
+ uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
- if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
{
- xAccessGranted = pdTRUE;
- }
- else
- {
- if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
+ uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
+ BaseType_t xAccessGranted = pdFALSE;
+ const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
+
+
+ if( xSchedulerRunning == pdFALSE )
{
- ulBufferStartAddress = ( uint32_t ) pvBuffer;
- ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
-
- for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
+ /* Grant access to all the kernel objects before the scheduler
+ * is started. It is necessary because there is no task running
+ * yet and therefore, we cannot use the permissions of any
+ * task. */
+ xAccessGranted = pdTRUE;
+ }
+ else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
+ {
+ xAccessGranted = pdTRUE;
+ }
+ else
+ {
+ if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
{
- if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
- xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
- portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ ulBufferStartAddress = ( uint32_t ) pvBuffer;
+ ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
+
+ for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
{
- xAccessGranted = pdTRUE;
- break;
+ if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
+ xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
+ portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
+ {
+ xAccessGranted = pdTRUE;
+ break;
+ }
}
}
}
+
+ return xAccessGranted;
}
- return xAccessGranted;
-}
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
__asm uint32_t prvPortGetIPSR( void )
@@ -1533,7 +1602,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 0f30043..9a6e37d 100644
--- a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -62,7 +62,7 @@
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
-#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
@@ -70,9 +70,14 @@
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+ #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
#endif
+/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+#ifndef configENABLE_ERRATA_837070_WORKAROUND
+ #define configENABLE_ERRATA_837070_WORKAROUND 0
+#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@@ -92,7 +97,7 @@
#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
@@ -174,8 +179,8 @@
#define configTEX_S_C_B_SRAM ( 0x07UL )
#endif
-#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
-#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
+#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL )
+#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL )
#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
@@ -184,9 +189,6 @@
#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
-void vPortSwitchToUserMode( void );
-#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
-
typedef struct MPU_REGION_REGISTERS
{
uint32_t ulRegionBaseAddress;
@@ -203,7 +205,7 @@
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
#ifndef configSYSTEM_CALL_STACK_SIZE
- #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
+ #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
#endif
typedef struct SYSTEM_CALL_STACK_INFO
@@ -216,14 +218,23 @@
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
-#define MAX_CONTEXT_SIZE ( 52 )
+/*
+ * +---------+---------------+-----------------+-----------------+-----+
+ * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 | |
+ * | | | EXC_RETURN | LR, PC, xPSR | |
+ * +---------+---------------+-----------------+-----------------+-----+
+ *
+ * <--------><---------------><----------------><----------------><---->
+ * 16 17 10 9 1
+ */
+#define MAX_CONTEXT_SIZE ( 53 )
/* Size of an Access Control List (ACL) entry in bits. */
#define portACL_ENTRY_SIZE_BITS ( 32U )
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
-#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
+#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
+#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
typedef struct MPU_SETTINGS
{
@@ -258,7 +269,7 @@
/* Scheduler utilities. */
-#define portYIELD() __asm{ SVC portSVC_YIELD }
+#define portYIELD() __asm { SVC portSVC_YIELD }
#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
@@ -273,8 +284,20 @@
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
@@ -299,7 +322,7 @@
/* Check the configuration. */
#if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
#endif
/* Store/clear the ready priorities in a bit map. */
@@ -320,7 +343,7 @@
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
-#ifdef configASSERT
+#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void );
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
@@ -337,24 +360,33 @@
extern BaseType_t xIsPrivileged( void );
extern void vResetPrivilege( void );
+extern void vPortSwitchToUserMode( void );
/**
* @brief Checks whether or not the processor is privileged.
*
* @return 1 if the processor is already privileged, 0 otherwise.
*/
-#define portIS_PRIVILEGED() xIsPrivileged()
+#define portIS_PRIVILEGED() xIsPrivileged()
/**
* @brief Raise an SVC request to raise privilege.
*/
-#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
+#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
/**
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
* register.
*/
-#define portRESET_PRIVILEGE() vResetPrivilege()
+#define portRESET_PRIVILEGE() vResetPrivilege()
+
+/**
+ * @brief Make a task unprivileged.
+ *
+ * It must be called from privileged tasks only. Calling it from unprivileged
+ * task will result in a memory protection fault.
+ */
+#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
/*-----------------------------------------------------------*/
extern BaseType_t xPortIsTaskPrivileged( void );
@@ -364,7 +396,7 @@
*
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
*/
-#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
+#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
/*-----------------------------------------------------------*/
static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
@@ -468,7 +500,7 @@
/*-----------------------------------------------------------*/
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+ #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
#endif
/*-----------------------------------------------------------*/
diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/Source/portable/RVDS/ARM_CM7/r0p1/port.c
index 2e1bdfc..1d0e460 100644
--- a/Source/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/Source/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -360,22 +360,22 @@
if( ulImplementedPrioBits == 8 )
{
/* When the hardware implements 8 priority bits, there is no way for
- * the software to configure PRIGROUP to not have sub-priorities. As
- * a result, the least significant bit is always used for sub-priority
- * and there are 128 preemption priorities and 2 sub-priorities.
- *
- * This may cause some confusion in some cases - for example, if
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
- * priority interrupts will be masked in Critical Sections as those
- * are at the same preemption priority. This may appear confusing as
- * 4 is higher (numerically lower) priority than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
- * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
- * to 4, this confusion does not happen and the behaviour remains the same.
- *
- * The following assert ensures that the sub-priority bit in the
- * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
- * confusion. */
+ * the software to configure PRIGROUP to not have sub-priorities. As
+ * a result, the least significant bit is always used for sub-priority
+ * and there are 128 preemption priorities and 2 sub-priorities.
+ *
+ * This may cause some confusion in some cases - for example, if
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
+ * priority interrupts will be masked in Critical Sections as those
+ * are at the same preemption priority. This may appear confusing as
+ * 4 is higher (numerically lower) priority than
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
+ * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * to 4, this confusion does not happen and the behaviour remains the same.
+ *
+ * The following assert ensures that the sub-priority bit in the
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
+ * confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
}
@@ -531,14 +531,21 @@
* known - therefore the slightly faster vPortRaiseBASEPRI() function is used
* in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
vPortRaiseBASEPRI();
+ traceISR_ENTER();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
+
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
vPortClearBASEPRIFromISR();
@@ -845,7 +852,7 @@
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
+ * https://www.freertos.org/Why-FreeRTOS/FAQs */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
}
diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index 19301dd..ef1389a 100644
--- a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -47,45 +47,45 @@
*/
/* Type definitions. */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
- #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #else
- #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
- #endif
+ #define portTICK_TYPE_IS_ATOMIC 1
+#else
+ #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
+#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
/* Constants used with memory barrier intrinsics. */
- #define portSY_FULL_READ_WRITE ( 15 )
+#define portSY_FULL_READ_WRITE ( 15 )
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
- #define portYIELD() \
+#define portYIELD() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -97,99 +97,111 @@
}
/*-----------------------------------------------------------*/
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ portYIELD(); \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* Critical section management. */
- extern void vPortEnterCritical( void );
- extern void vPortExitCritical( void );
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
- #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
- #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
/*-----------------------------------------------------------*/
/* Port specific optimisations. */
- #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
- #endif
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
- #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
+ #if ( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
- #endif /* taskRECORD_READY_PRIORITY */
+#endif /* taskRECORD_READY_PRIORITY */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
* not necessary for to use this port. They are defined so the common demo files
* (which build with all the ports) will build. */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*-----------------------------------------------------------*/
- #ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
- #endif
+#if ( configASSERT_DEFINED == 1 )
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
/* portNOP() is not required by this port. */
- #define portNOP()
+#define portNOP()
- #define portINLINE __inline
+#define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE __forceinline
- #endif
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE __forceinline
+#endif
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+ __asm
{
- __asm
- {
- /* Barrier instructions are not used as this function is only used to
- * lower the BASEPRI value. */
+ /* Barrier instructions are not used as this function is only used to
+ * lower the BASEPRI value. */
/* *INDENT-OFF* */
msr basepri, ulBASEPRI
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortRaiseBASEPRI( void )
- {
- uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+ uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
+ __asm
+ {
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
/* *INDENT-OFF* */
cpsid i
msr basepri, ulNewBASEPRI
@@ -197,32 +209,32 @@
isb
cpsie i
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+ __asm
{
- __asm
- {
- /* Set BASEPRI to 0 so no interrupts are masked. This function is only
- * used to lower the mask in an interrupt, so memory barriers are not
- * used. */
+ /* Set BASEPRI to 0 so no interrupts are masked. This function is only
+ * used to lower the mask in an interrupt, so memory barriers are not
+ * used. */
/* *INDENT-OFF* */
msr basepri, # 0
/* *INDENT-ON* */
- }
}
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
- {
- uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+ uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
+ __asm
+ {
+ /* Set BASEPRI to the max syscall priority to effect a critical
+ * section. */
/* *INDENT-OFF* */
mrs ulReturn, basepri
cpsid i
@@ -231,37 +243,37 @@
isb
cpsie i
/* *INDENT-ON* */
- }
-
- return ulReturn;
}
+
+ return ulReturn;
+}
/*-----------------------------------------------------------*/
- static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
- {
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+ uint32_t ulCurrentInterrupt;
+ BaseType_t xReturn;
- /* Obtain the number of the currently executing interrupt. */
- __asm
- {
+ /* Obtain the number of the currently executing interrupt. */
+ __asm
+ {
/* *INDENT-OFF* */
mrs ulCurrentInterrupt, ipsr
/* *INDENT-ON* */
- }
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
}
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+
/* *INDENT-OFF* */
#ifdef __cplusplus
}
diff --git a/Source/portable/Tasking/ARM_CM4F/port.c b/Source/portable/Tasking/ARM_CM4F/port.c
index b5967d3..577bbb8 100644
--- a/Source/portable/Tasking/ARM_CM4F/port.c
+++ b/Source/portable/Tasking/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -246,12 +246,18 @@
uint32_t ulDummy;
ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ traceISR_ENTER();
{
if( xTaskIncrementTick() != pdFALSE )
{
+ traceISR_EXIT_TO_SCHEDULER();
/* Pend a context switch. */
*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
}
+ else
+ {
+ traceISR_EXIT();
+ }
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
}
diff --git a/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/Source/portable/Tasking/ARM_CM4F/port_asm.asm
index f47139e..3022668 100644
--- a/Source/portable/Tasking/ARM_CM4F/port_asm.asm
+++ b/Source/portable/Tasking/ARM_CM4F/port_asm.asm
@@ -1,6 +1,6 @@
;/*
-; * FreeRTOS Kernel V10.6.2
-; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; * FreeRTOS Kernel V11.2.0
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
diff --git a/Source/portable/Tasking/ARM_CM4F/portmacro.h b/Source/portable/Tasking/ARM_CM4F/portmacro.h
index 1527091..0f2e3be 100644
--- a/Source/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -83,13 +83,25 @@
/* Scheduler utilities. */
- extern void vPortYield( void );
- #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
- #define portNVIC_PENDSVSET 0x10000000
- #define portYIELD() vPortYield()
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_PENDSVSET 0x10000000
+#define portYIELD() vPortYield()
- #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \
+ do \
+ { \
+ if( xSwitchRequired != pdFALSE ) \
+ { \
+ traceISR_EXIT_TO_SCHEDULER(); \
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \
+ } \
+ else \
+ { \
+ traceISR_EXIT(); \
+ } \
+ } while( 0 )
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
diff --git a/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/README.md b/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/README.md
index 1643817..7df149f 100644
--- a/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/README.md
+++ b/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/README.md
@@ -2,20 +2,22 @@
This port adds the support that FreeRTOS applications can call the secure
services in Trusted Firmware M(TF-M) through Platform Security Architecture
-(PSA) API based on the ARM Cortex-M33 platform.
+(PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M55 and Cortex-M85
+platform.
The Platform Security Architecture (PSA) makes it quicker, easier and cheaper
to design security into a device from the ground up. PSA is made up of four key
-stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://developer.arm.com/architectures/security-architectures/platform-security-architecture).
+stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://www.arm.com/architecture/security-features/platform-security).
TF-M is an open source project. It provides a reference implementation of PSA
-for Arm M-profile architecture. Please get the details from this [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/about/).
+for Arm M-profile architecture. Please get the details from this [link](https://www.trustedfirmware.org/projects/tf-m/).
# Derivation of the source code
-* ```os_wrapper_freertos.c```
- The implementation of APIs which are defined in ```\os_wrapper\mutex.h``` by tf-m-tests
- (tag: TF-Mv1.4.0). The implementation is based on FreeRTOS mutex type semaphore.
+* `os_wrapper_freertos.c`
+ The implementation of APIs which are defined in `/interface/include/os_wrapper/mutex.h`
+ in trusted-firmware-m (tag: TF-Mv2.0.0). The implementation is based on
+ FreeRTOS mutex type semaphore.
# Usage notes
@@ -27,46 +29,52 @@
### Get the TF-M source code
-See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is based on TF-M version **tag: TF-Mv1.4.0**.
+See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is supported by TF-M version **tag: TF-Mv2.0.0**.
### Build TF-M
-Please refer to this [link](https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/instructions/tfm_build_instruction.html) to build the secure side.
-_**Note:** ```TFM_NS_CLIENT_IDENTIFICATION``` must be configured as "OFF" when building TF-M_.
+Please refer to this [link](https://trustedfirmware-m.readthedocs.io/en/latest/getting_started/) to build the secure side.
+_**Note:** `TFM_NS_MANAGE_NSID` must be configured as "OFF" when building TF-M_.
## Build the Non-Secure Side
-Please copy all the files in ```freertos_kernel\portable\GCC\ARM_CM33_NTZ``` into the ```freertos_kernel\portable\ThirdParty\GCC\ARM_CM33_TFM``` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
+Please copy all the files in `freertos_kernel/portable/GCC/ARM_CM[23|33|55|85]_NTZ` into the `freertos_kernel/portable/ThirdParty/GCC/ARM_TFM` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
-Please call the API ```tfm_ns_interface_init()``` which is defined in ```tfm_ns_interface.c``` by tf-m-tests
-(tag: TF-Mv1.4.0)at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side.
+Please call the API `tfm_ns_interface_init()` which is defined in `/interface/src/os_wrapper/tfm_ns_interface_rtos.c` by trusted-firmware-m (tag: TF-Mv2.0.0) at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side.
### Configuration in FreeRTOS kernel
-* ```configRUN_FREERTOS_SECURE_ONLY```
+* `configRUN_FREERTOS_SECURE_ONLY`
This macro should be configured as 0. In this port, TF-M runs in the Secure Side while FreeRTOS
Kernel runs in the Non-Secure Side.
-* ```configENABLE_FPU```
+* `configENABLE_FPU`
The setting of this macro is decided by the setting in Secure Side which is platform-specific.
If the Secure Side enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
+Please note that Cortex-M23 does not support FPU.
+Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for FPU usage on the Non-Secure side.
-* ```configENABLE_TRUSTZONE```
+* `configENABLE_MVE`
+The setting of this macro is decided by the setting in Secure Side which is platform-specific.
+If the Secure Side enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
+Please note that only Cortex-M55 and Cortex-M85 support MVE.
+Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side.
+
+* `configENABLE_TRUSTZONE`
This macro should be configured as 0 because TF-M doesn't use the secure context management function of FreeRTOS. New secure context management might be introduced when TF-M supports multiple secure context.
### Integrate TF-M Non-Secure interface with FreeRTOS project
To enable calling TF-M services by the Non-Secure Side, the files below should be included in the FreeRTOS project and built together.
-* files in ```trusted-firmware-m\build\install\interface\src```
- These files contain the implementation of PSA Functional Developer APIs which can be called by Non-Secure Side directly and PSA Firmware Framework APIs in the IPC model. These files should be taken
- as part of the Non-Secure source code.
-* files in ```trusted-firmware-m\build\install\interface\include```
+* files in `trusted-firmware-m/build/api_ns/interface/src`
+ These files contain the implementation of PSA Functional Developer APIs which can be called by Non-Secure Side directly and PSA Firmware Framework APIs in the IPC model. These files should be taken as part of the Non-Secure source code.
+* files in `trusted-firmware-m/build/api_ns/interface/include`
These files are the necessary header files to call TF-M services.
-* ```trusted-firmware-m\build\install\interface\lib\s_veneers.o```
+* `trusted-firmware-m/build/api_ns/interface/lib/s_veneers.o`
This object file contains all the Non-Secure callable functions exported by
TF-M and it should be linked when generating the Non-Secure image.
-*Copyright (c) 2020-2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2020-2024, Arm Limited. All rights reserved.*
diff --git a/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/os_wrapper_freertos.c b/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/os_wrapper_freertos.c
index 01183fb..35add2b 100644
--- a/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/os_wrapper_freertos.c
+++ b/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/os_wrapper_freertos.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -24,8 +24,8 @@
/*
* This file contains the implementation of APIs which are defined in
- * os_wrapper/mutex.h by TF-M(tag: TF-Mv1.1). The implementation is based
- * on FreeRTOS mutex type semaphore.
+ * \interface/include/os_wrapper/mutex.h by TF-M(tag: TF-Mv2.0.0).
+ * The implementation is based on FreeRTOS mutex type semaphore.
*/
#include "os_wrapper/mutex.h"
@@ -34,65 +34,79 @@
#include "semphr.h"
#include "mpu_wrappers.h"
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- /*
- * In the static allocation, the RAM is required to hold the semaphore's
- * state.
- */
- StaticSemaphore_t xSecureMutexBuffer;
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+/*
+ * In the static allocation, the RAM is required to hold the semaphore's
+ * state.
+ */
+ StaticSemaphore_t xSecureMutexBuffer;
#endif
void * os_wrapper_mutex_create( void )
{
-SemaphoreHandle_t xMutexHandle = NULL;
+ SemaphoreHandle_t xMutexHandle = NULL;
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- xMutexHandle = xSemaphoreCreateMutex();
-#elif( configSUPPORT_STATIC_ALLOCATION == 1 )
- xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer );
-#endif
- return ( void * ) xMutexHandle;
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ xMutexHandle = xSemaphoreCreateMutex();
+ #elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer );
+ #endif
+ return ( void * ) xMutexHandle;
}
/*-----------------------------------------------------------*/
-uint32_t os_wrapper_mutex_acquire( void * handle, uint32_t timeout )
+uint32_t os_wrapper_mutex_acquire( void * handle,
+ uint32_t timeout )
{
-BaseType_t xRet;
+ BaseType_t xRet;
- if( ! handle )
- return OS_WRAPPER_ERROR;
+ if( !handle )
+ {
+ return OS_WRAPPER_ERROR;
+ }
- xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle,
- ( timeout == OS_WRAPPER_WAIT_FOREVER ) ?
+ xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle,
+ ( timeout == OS_WRAPPER_WAIT_FOREVER ) ?
portMAX_DELAY : ( TickType_t ) timeout );
- if( xRet != pdPASS )
- return OS_WRAPPER_ERROR;
- else
- return OS_WRAPPER_SUCCESS;
+ if( xRet != pdPASS )
+ {
+ return OS_WRAPPER_ERROR;
+ }
+ else
+ {
+ return OS_WRAPPER_SUCCESS;
+ }
}
/*-----------------------------------------------------------*/
uint32_t os_wrapper_mutex_release( void * handle )
{
-BaseType_t xRet;
+ BaseType_t xRet;
- if( !handle )
- return OS_WRAPPER_ERROR;
+ if( !handle )
+ {
+ return OS_WRAPPER_ERROR;
+ }
- xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle );
+ xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle );
- if( xRet != pdPASS )
- return OS_WRAPPER_ERROR;
- else
- return OS_WRAPPER_SUCCESS;
+ if( xRet != pdPASS )
+ {
+ return OS_WRAPPER_ERROR;
+ }
+ else
+ {
+ return OS_WRAPPER_SUCCESS;
+ }
}
/*-----------------------------------------------------------*/
uint32_t os_wrapper_mutex_delete( void * handle )
{
- vSemaphoreDelete( ( SemaphoreHandle_t ) handle );
+ vSemaphoreDelete( ( SemaphoreHandle_t ) handle );
- return OS_WRAPPER_SUCCESS;
+ return OS_WRAPPER_SUCCESS;
}
/*-----------------------------------------------------------*/
diff --git a/Source/queue.c b/Source/queue.c
index 40edbe4..48156f4 100644
--- a/Source/queue.c
+++ b/Source/queue.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -42,11 +42,10 @@
#include "croutine.h"
#endif
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
* for the header files above, but not in this file, in order to generate the
* correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/* Constants used with the cRxLock and cTxLock structure members. */
@@ -89,7 +88,11 @@
* performed just because a higher priority task has been woken. */
#define queueYIELD_IF_USING_PREEMPTION()
#else
- #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ #define queueYIELD_IF_USING_PREEMPTION() vTaskYieldWithinAPI()
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
#endif
/*
@@ -149,7 +152,7 @@
* more user friendly. */
typedef struct QUEUE_REGISTRY_ITEM
{
- const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcQueueName;
QueueHandle_t xHandle;
} xQueueRegistryItem;
@@ -161,6 +164,10 @@
/* The queue registry is simply an array of QueueRegistryItem_t structures.
* The pcQueueName member of a structure being NULL is indicative of the
* array position being vacant. */
+
+/* MISRA Ref 8.4.2 [Declaration shall be visible] */
+/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+/* coverity[misra_c_2012_rule_8_4_violation] */
PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
#endif /* configQUEUE_REGISTRY_SIZE */
@@ -240,7 +247,7 @@
* other tasks that are waiting for the same mutex. This function returns
* that priority.
*/
- static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+ static UBaseType_t prvGetHighestPriorityOfWaitToReceiveList( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
#endif
/*-----------------------------------------------------------*/
@@ -299,6 +306,8 @@
BaseType_t xReturn = pdPASS;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueGenericReset( xQueue, xNewQueue );
+
configASSERT( pxQueue );
if( ( pxQueue != NULL ) &&
@@ -308,10 +317,10 @@
{
taskENTER_CRITICAL();
{
- pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
pxQueue->pcWriteTo = pxQueue->pcHead;
- pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize );
pxQueue->cRxLock = queueUNLOCKED;
pxQueue->cTxLock = queueUNLOCKED;
@@ -356,6 +365,8 @@
/* A value is returned for calling semantic consistency with previous
* versions. */
+ traceRETURN_xQueueGenericReset( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -370,6 +381,8 @@
{
Queue_t * pxNewQueue = NULL;
+ traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
+
/* The StaticQueue_t structure and the queue storage area must be
* supplied. */
configASSERT( pxStaticQueue );
@@ -379,8 +392,8 @@
/* A queue storage area should be provided if the item size is not 0, and
* should not be provided if the item size is 0. */
- ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) &&
- ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) )
+ ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0U ) ) ) &&
+ ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0U ) ) ) )
{
#if ( configASSERT_DEFINED == 1 )
{
@@ -391,18 +404,21 @@
/* This assertion cannot be branch covered in unit tests */
configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
- ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */
}
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
* The address of a statically allocated storage area was also passed in
* but is already set. */
- pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ pxNewQueue = ( Queue_t * ) pxStaticQueue;
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
- /* Queues can be allocated wither statically or dynamically, so
+ /* Queues can be allocated either statically or dynamically, so
* note this queue was allocated statically in case the queue is
* later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
@@ -417,6 +433,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xQueueGenericCreateStatic( pxNewQueue );
+
return pxNewQueue;
}
@@ -432,6 +450,8 @@
BaseType_t xReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue );
+
configASSERT( pxQueue );
configASSERT( ppxStaticQueue );
@@ -445,6 +465,9 @@
*ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead;
}
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
*ppxStaticQueue = ( StaticQueue_t * ) pxQueue;
xReturn = pdTRUE;
}
@@ -466,6 +489,8 @@
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ traceRETURN_xQueueGenericGetStaticBuffers( xReturn );
+
return xReturn;
}
@@ -482,34 +507,33 @@
size_t xQueueSizeInBytes;
uint8_t * pucQueueStorage;
+ traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
+
if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
/* Check for multiplication overflow. */
( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
/* Check for addition overflow. */
- ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
+ /* MISRA Ref 14.3.1 [Configuration dependent invariant] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-143. */
+ /* coverity[misra_c_2012_rule_14_3_violation] */
+ ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize ) ) )
{
/* Allocate enough space to hold the maximum number of items that
* can be in the queue at any time. It is valid for uxItemSize to be
* zero in the case the queue is used as a semaphore. */
- xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ xQueueSizeInBytes = ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize );
- /* Allocate the queue and storage area. Justification for MISRA
- * deviation as follows: pvPortMalloc() always ensures returned memory
- * blocks are aligned per the requirements of the MCU stack. In this case
- * pvPortMalloc() must return a pointer that is guaranteed to meet the
- * alignment requirements of the Queue_t structure - which in this case
- * is an int8_t *. Therefore, whenever the stack alignment requirements
- * are greater than or equal to the pointer to char requirements the cast
- * is safe. In other cases alignment requirements are not strict (one or
- * two bytes). */
- pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
if( pxNewQueue != NULL )
{
/* Jump past the queue structure to find the location of the queue
* storage area. */
pucQueueStorage = ( uint8_t * ) pxNewQueue;
- pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ pucQueueStorage += sizeof( Queue_t );
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
{
@@ -534,6 +558,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xQueueGenericCreate( pxNewQueue );
+
return pxNewQueue;
}
@@ -623,9 +649,13 @@
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+ traceENTER_xQueueCreateMutex( ucQueueType );
+
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+ traceRETURN_xQueueCreateMutex( xNewQueue );
+
return xNewQueue;
}
@@ -640,6 +670,8 @@
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+ traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
+
/* Prevent compiler warnings about unused parameters if
* configUSE_TRACE_FACILITY does not equal 1. */
( void ) ucQueueType;
@@ -647,6 +679,8 @@
xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+ traceRETURN_xQueueCreateMutexStatic( xNewQueue );
+
return xNewQueue;
}
@@ -660,6 +694,8 @@
TaskHandle_t pxReturn;
Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+ traceENTER_xQueueGetMutexHolder( xSemaphore );
+
configASSERT( xSemaphore );
/* This function is called by xSemaphoreGetMutexHolder(), and should not
@@ -680,8 +716,10 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_xQueueGetMutexHolder( pxReturn );
+
return pxReturn;
- } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+ }
#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
/*-----------------------------------------------------------*/
@@ -692,6 +730,8 @@
{
TaskHandle_t pxReturn;
+ traceENTER_xQueueGetMutexHolderFromISR( xSemaphore );
+
configASSERT( xSemaphore );
/* Mutexes cannot be used in interrupt service routines, so the mutex
@@ -706,8 +746,10 @@
pxReturn = NULL;
}
+ traceRETURN_xQueueGetMutexHolderFromISR( pxReturn );
+
return pxReturn;
- } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+ }
#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
/*-----------------------------------------------------------*/
@@ -719,6 +761,8 @@
BaseType_t xReturn;
Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+ traceENTER_xQueueGiveMutexRecursive( xMutex );
+
configASSERT( pxMutex );
/* If this is the task that holds the mutex then xMutexHolder will not
@@ -761,6 +805,8 @@
traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
}
+ traceRETURN_xQueueGiveMutexRecursive( xReturn );
+
return xReturn;
}
@@ -775,6 +821,8 @@
BaseType_t xReturn;
Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+ traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait );
+
configASSERT( pxMutex );
/* Comments regarding mutual exclusion as per those within
@@ -804,6 +852,8 @@
}
}
+ traceRETURN_xQueueTakeMutexRecursive( xReturn );
+
return xReturn;
}
@@ -818,7 +868,9 @@
{
QueueHandle_t xHandle = NULL;
- if( ( uxMaxCount != 0 ) &&
+ traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
+
+ if( ( uxMaxCount != 0U ) &&
( uxInitialCount <= uxMaxCount ) )
{
xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
@@ -840,6 +892,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle );
+
return xHandle;
}
@@ -853,7 +907,9 @@
{
QueueHandle_t xHandle = NULL;
- if( ( uxMaxCount != 0 ) &&
+ traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount );
+
+ if( ( uxMaxCount != 0U ) &&
( uxInitialCount <= uxMaxCount ) )
{
xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
@@ -875,6 +931,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xQueueCreateCountingSemaphore( xHandle );
+
return xHandle;
}
@@ -890,6 +948,8 @@
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+
configASSERT( pxQueue );
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
@@ -899,9 +959,6 @@
}
#endif
- /*lint -save -e904 This function relaxes the coding standard somewhat to
- * allow return statements within the function itself. This is done in the
- * interest of execution time efficiency. */
for( ; ; )
{
taskENTER_CRITICAL();
@@ -1011,6 +1068,9 @@
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
+
+ traceRETURN_xQueueGenericSend( pdPASS );
+
return pdPASS;
}
else
@@ -1024,6 +1084,8 @@
/* Return to the original privilege level before exiting
* the function. */
traceQUEUE_SEND_FAILED( pxQueue );
+ traceRETURN_xQueueGenericSend( errQUEUE_FULL );
+
return errQUEUE_FULL;
}
else if( xEntryTimeSet == pdFALSE )
@@ -1070,7 +1132,7 @@
* is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
{
- portYIELD_WITHIN_API();
+ taskYIELD_WITHIN_API();
}
}
else
@@ -1087,9 +1149,11 @@
( void ) xTaskResumeAll();
traceQUEUE_SEND_FAILED( pxQueue );
+ traceRETURN_xQueueGenericSend( errQUEUE_FULL );
+
return errQUEUE_FULL;
}
- } /*lint -restore */
+ }
}
/*-----------------------------------------------------------*/
@@ -1102,6 +1166,8 @@
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition );
+
configASSERT( pxQueue );
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
@@ -1127,7 +1193,10 @@
* read, instead return a flag to say whether a context switch is required or
* not (i.e. has a task with a higher priority than us been woken by this
* post). */
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
{
@@ -1252,7 +1321,9 @@
xReturn = errQUEUE_FULL;
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xQueueGenericSendFromISR( xReturn );
return xReturn;
}
@@ -1265,6 +1336,8 @@
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken );
+
/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
* item size is 0. Don't directly wake a task that was blocked on a queue
* read, instead return a flag to say whether a context switch is required or
@@ -1298,7 +1371,10 @@
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@@ -1317,7 +1393,7 @@
* can be assumed there is no mutex holder and no need to determine if
* priority disinheritance is needed. Simply increase the count of
* messages (semaphores) available. */
- pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+ pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );
/* The event list is not altered if the queue is locked. This will
* be done when the queue is unlocked later. */
@@ -1418,7 +1494,9 @@
xReturn = errQUEUE_FULL;
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xQueueGiveFromISR( xReturn );
return xReturn;
}
@@ -1432,6 +1510,8 @@
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait );
+
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
@@ -1446,9 +1526,6 @@
}
#endif
- /*lint -save -e904 This function relaxes the coding standard somewhat to
- * allow return statements within the function itself. This is done in the
- * interest of execution time efficiency. */
for( ; ; )
{
taskENTER_CRITICAL();
@@ -1462,7 +1539,7 @@
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
traceQUEUE_RECEIVE( pxQueue );
- pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+ pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );
/* There is now space in the queue, were any tasks waiting to
* post to the queue? If so, unblock the highest priority waiting
@@ -1484,6 +1561,9 @@
}
taskEXIT_CRITICAL();
+
+ traceRETURN_xQueueReceive( pdPASS );
+
return pdPASS;
}
else
@@ -1493,7 +1573,10 @@
/* The queue was empty and no block time is specified (or
* the block time has expired) so leave now. */
taskEXIT_CRITICAL();
+
traceQUEUE_RECEIVE_FAILED( pxQueue );
+ traceRETURN_xQueueReceive( errQUEUE_EMPTY );
+
return errQUEUE_EMPTY;
}
else if( xEntryTimeSet == pdFALSE )
@@ -1531,7 +1614,7 @@
if( xTaskResumeAll() == pdFALSE )
{
- portYIELD_WITHIN_API();
+ taskYIELD_WITHIN_API();
}
else
{
@@ -1556,6 +1639,8 @@
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
+ traceRETURN_xQueueReceive( errQUEUE_EMPTY );
+
return errQUEUE_EMPTY;
}
else
@@ -1563,7 +1648,7 @@
mtCOVERAGE_TEST_MARKER();
}
}
- } /*lint -restore */
+ }
}
/*-----------------------------------------------------------*/
@@ -1578,6 +1663,8 @@
BaseType_t xInheritanceOccurred = pdFALSE;
#endif
+ traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait );
+
/* Check the queue pointer is not NULL. */
configASSERT( ( pxQueue ) );
@@ -1592,9 +1679,6 @@
}
#endif
- /*lint -save -e904 This function relaxes the coding standard somewhat to allow return
- * statements within the function itself. This is done in the interest
- * of execution time efficiency. */
for( ; ; )
{
taskENTER_CRITICAL();
@@ -1611,7 +1695,7 @@
/* Semaphores are queues with a data size of zero and where the
* messages waiting is the semaphore's count. Reduce the count. */
- pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+ pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxSemaphoreCount - ( UBaseType_t ) 1 );
#if ( configUSE_MUTEXES == 1 )
{
@@ -1647,6 +1731,9 @@
}
taskEXIT_CRITICAL();
+
+ traceRETURN_xQueueSemaphoreTake( pdPASS );
+
return pdPASS;
}
else
@@ -1656,7 +1743,10 @@
/* The semaphore count was 0 and no block time is specified
* (or the block time has expired) so exit now. */
taskEXIT_CRITICAL();
+
traceQUEUE_RECEIVE_FAILED( pxQueue );
+ traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );
+
return errQUEUE_EMPTY;
}
else if( xEntryTimeSet == pdFALSE )
@@ -1714,7 +1804,7 @@
if( xTaskResumeAll() == pdFALSE )
{
- portYIELD_WITHIN_API();
+ taskYIELD_WITHIN_API();
}
else
{
@@ -1757,7 +1847,15 @@
* has timed out the priority should be disinherited
* again, but only as low as the next highest priority
* task that is waiting for the same mutex. */
- uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+ uxHighestWaitingPriority = prvGetHighestPriorityOfWaitToReceiveList( pxQueue );
+
+ /* vTaskPriorityDisinheritAfterTimeout uses the uxHighestWaitingPriority
+ * parameter to index pxReadyTasksLists when adding the task holding
+ * mutex to the ready list for its new priority. Coverity thinks that
+ * it can result in out-of-bounds access which is not true because
+ * uxHighestWaitingPriority, as returned by prvGetHighestPriorityOfWaitToReceiveList,
+ * is capped at ( configMAX_PRIORITIES - 1 ). */
+ /* coverity[overrun] */
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
}
taskEXIT_CRITICAL();
@@ -1766,6 +1864,8 @@
#endif /* configUSE_MUTEXES */
traceQUEUE_RECEIVE_FAILED( pxQueue );
+ traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );
+
return errQUEUE_EMPTY;
}
else
@@ -1773,7 +1873,7 @@
mtCOVERAGE_TEST_MARKER();
}
}
- } /*lint -restore */
+ }
}
/*-----------------------------------------------------------*/
@@ -1786,6 +1886,8 @@
int8_t * pcOriginalReadPosition;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait );
+
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
@@ -1800,9 +1902,6 @@
}
#endif
- /*lint -save -e904 This function relaxes the coding standard somewhat to
- * allow return statements within the function itself. This is done in the
- * interest of execution time efficiency. */
for( ; ; )
{
taskENTER_CRITICAL();
@@ -1844,6 +1943,9 @@
}
taskEXIT_CRITICAL();
+
+ traceRETURN_xQueuePeek( pdPASS );
+
return pdPASS;
}
else
@@ -1853,7 +1955,10 @@
/* The queue was empty and no block time is specified (or
* the block time has expired) so leave now. */
taskEXIT_CRITICAL();
+
traceQUEUE_PEEK_FAILED( pxQueue );
+ traceRETURN_xQueuePeek( errQUEUE_EMPTY );
+
return errQUEUE_EMPTY;
}
else if( xEntryTimeSet == pdFALSE )
@@ -1892,7 +1997,7 @@
if( xTaskResumeAll() == pdFALSE )
{
- portYIELD_WITHIN_API();
+ taskYIELD_WITHIN_API();
}
else
{
@@ -1917,6 +2022,8 @@
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
{
traceQUEUE_PEEK_FAILED( pxQueue );
+ traceRETURN_xQueuePeek( errQUEUE_EMPTY );
+
return errQUEUE_EMPTY;
}
else
@@ -1924,7 +2031,7 @@
mtCOVERAGE_TEST_MARKER();
}
}
- } /*lint -restore */
+ }
}
/*-----------------------------------------------------------*/
@@ -1936,6 +2043,8 @@
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken );
+
configASSERT( pxQueue );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1955,7 +2064,10 @@
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
@@ -1967,7 +2079,7 @@
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
prvCopyDataFromQueue( pxQueue, pvBuffer );
- pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+ pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );
/* If the queue is locked the event list will not be modified.
* Instead update the lock count so the task that unlocks the queue
@@ -2015,7 +2127,9 @@
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xQueueReceiveFromISR( xReturn );
return xReturn;
}
@@ -2029,6 +2143,8 @@
int8_t * pcOriginalReadPosition;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueuePeekFromISR( xQueue, pvBuffer );
+
configASSERT( pxQueue );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
@@ -2049,7 +2165,10 @@
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
{
/* Cannot block in an ISR, so check there is data available. */
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
@@ -2070,7 +2189,9 @@
traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xQueuePeekFromISR( xReturn );
return xReturn;
}
@@ -2080,16 +2201,20 @@
{
UBaseType_t uxReturn;
+ traceENTER_uxQueueMessagesWaiting( xQueue );
+
configASSERT( xQueue );
- taskENTER_CRITICAL();
+ portBASE_TYPE_ENTER_CRITICAL();
{
uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
}
- taskEXIT_CRITICAL();
+ portBASE_TYPE_EXIT_CRITICAL();
+
+ traceRETURN_uxQueueMessagesWaiting( uxReturn );
return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+}
/*-----------------------------------------------------------*/
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
@@ -2097,16 +2222,20 @@
UBaseType_t uxReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_uxQueueSpacesAvailable( xQueue );
+
configASSERT( pxQueue );
- taskENTER_CRITICAL();
+ portBASE_TYPE_ENTER_CRITICAL();
{
- uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+ uxReturn = ( UBaseType_t ) ( pxQueue->uxLength - pxQueue->uxMessagesWaiting );
}
- taskEXIT_CRITICAL();
+ portBASE_TYPE_EXIT_CRITICAL();
+
+ traceRETURN_uxQueueSpacesAvailable( uxReturn );
return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+}
/*-----------------------------------------------------------*/
UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
@@ -2114,17 +2243,23 @@
UBaseType_t uxReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_uxQueueMessagesWaitingFromISR( xQueue );
+
configASSERT( pxQueue );
uxReturn = pxQueue->uxMessagesWaiting;
+ traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn );
+
return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+}
/*-----------------------------------------------------------*/
void vQueueDelete( QueueHandle_t xQueue )
{
Queue_t * const pxQueue = xQueue;
+ traceENTER_vQueueDelete( xQueue );
+
configASSERT( pxQueue );
traceQUEUE_DELETE( pxQueue );
@@ -2160,6 +2295,8 @@
( void ) pxQueue;
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+ traceRETURN_vQueueDelete();
}
/*-----------------------------------------------------------*/
@@ -2167,6 +2304,10 @@
UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
{
+ traceENTER_uxQueueGetQueueNumber( xQueue );
+
+ traceRETURN_uxQueueGetQueueNumber( ( ( Queue_t * ) xQueue )->uxQueueNumber );
+
return ( ( Queue_t * ) xQueue )->uxQueueNumber;
}
@@ -2178,7 +2319,11 @@
void vQueueSetQueueNumber( QueueHandle_t xQueue,
UBaseType_t uxQueueNumber )
{
+ traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber );
+
( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+
+ traceRETURN_vQueueSetQueueNumber();
}
#endif /* configUSE_TRACE_FACILITY */
@@ -2188,6 +2333,10 @@
uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
{
+ traceENTER_ucQueueGetQueueType( xQueue );
+
+ traceRETURN_ucQueueGetQueueType( ( ( Queue_t * ) xQueue )->ucQueueType );
+
return ( ( Queue_t * ) xQueue )->ucQueueType;
}
@@ -2196,19 +2345,27 @@
UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
{
+ traceENTER_uxQueueGetQueueItemSize( xQueue );
+
+ traceRETURN_uxQueueGetQueueItemSize( ( ( Queue_t * ) xQueue )->uxItemSize );
+
return ( ( Queue_t * ) xQueue )->uxItemSize;
}
/*-----------------------------------------------------------*/
UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
{
+ traceENTER_uxQueueGetQueueLength( xQueue );
+
+ traceRETURN_uxQueueGetQueueLength( ( ( Queue_t * ) xQueue )->uxLength );
+
return ( ( Queue_t * ) xQueue )->uxLength;
}
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
- static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+ static UBaseType_t prvGetHighestPriorityOfWaitToReceiveList( const Queue_t * const pxQueue )
{
UBaseType_t uxHighestPriorityOfWaitingTasks;
@@ -2220,7 +2377,7 @@
* mutex. */
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
{
- uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+ uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) ( ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ) );
}
else
{
@@ -2263,10 +2420,10 @@
}
else if( xPosition == queueSEND_TO_BACK )
{
- ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
- pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
+ pxQueue->pcWriteTo += pxQueue->uxItemSize;
- if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )
{
pxQueue->pcWriteTo = pxQueue->pcHead;
}
@@ -2277,10 +2434,10 @@
}
else
{
- ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
+ ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
- if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead )
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
}
@@ -2310,7 +2467,7 @@
}
}
- pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+ pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );
return xReturn;
}
@@ -2321,9 +2478,9 @@
{
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
{
- pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+ if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
}
@@ -2332,7 +2489,7 @@
mtCOVERAGE_TEST_MARKER();
}
- ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize );
}
}
/*-----------------------------------------------------------*/
@@ -2483,6 +2640,8 @@
BaseType_t xReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueIsQueueEmptyFromISR( xQueue );
+
configASSERT( pxQueue );
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
@@ -2494,8 +2653,10 @@
xReturn = pdFALSE;
}
+ traceRETURN_xQueueIsQueueEmptyFromISR( xReturn );
+
return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+}
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
@@ -2524,6 +2685,8 @@
BaseType_t xReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueIsQueueFullFromISR( xQueue );
+
configASSERT( pxQueue );
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
@@ -2535,8 +2698,10 @@
xReturn = pdFALSE;
}
+ traceRETURN_xQueueIsQueueFullFromISR( xReturn );
+
return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+}
/*-----------------------------------------------------------*/
#if ( configUSE_CO_ROUTINES == 1 )
@@ -2548,6 +2713,8 @@
BaseType_t xReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait );
+
/* If the queue is already full we may have to block. A critical section
* is required to prevent an interrupt removing something from the queue
* between the check to see if the queue is full and blocking on the queue. */
@@ -2612,6 +2779,8 @@
}
portENABLE_INTERRUPTS();
+ traceRETURN_xQueueCRSend( xReturn );
+
return xReturn;
}
@@ -2627,6 +2796,8 @@
BaseType_t xReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait );
+
/* If the queue is already empty we may have to block. A critical section
* is required to prevent an interrupt adding something to the queue
* between the check to see if the queue is empty and blocking on the queue. */
@@ -2706,6 +2877,8 @@
}
portENABLE_INTERRUPTS();
+ traceRETURN_xQueueCRReceive( xReturn );
+
return xReturn;
}
@@ -2720,6 +2893,8 @@
{
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken );
+
/* Cannot block within an ISR so if there is no space on the queue then
* exit without doing anything. */
if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
@@ -2756,6 +2931,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken );
+
return xCoRoutinePreviouslyWoken;
}
@@ -2771,6 +2948,8 @@
BaseType_t xReturn;
Queue_t * const pxQueue = xQueue;
+ traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken );
+
/* We cannot block from an ISR, so check there is data available. If
* not then just leave without doing anything. */
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
@@ -2820,6 +2999,8 @@
xReturn = pdFAIL;
}
+ traceRETURN_xQueueCRReceiveFromISR( xReturn );
+
return xReturn;
}
@@ -2829,11 +3010,13 @@
#if ( configQUEUE_REGISTRY_SIZE > 0 )
void vQueueAddToRegistry( QueueHandle_t xQueue,
- const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcQueueName )
{
UBaseType_t ux;
QueueRegistryItem_t * pxEntryToWrite = NULL;
+ traceENTER_vQueueAddToRegistry( xQueue, pcQueueName );
+
configASSERT( xQueue );
if( pcQueueName != NULL )
@@ -2868,6 +3051,8 @@
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
}
+
+ traceRETURN_vQueueAddToRegistry();
}
#endif /* configQUEUE_REGISTRY_SIZE */
@@ -2875,10 +3060,12 @@
#if ( configQUEUE_REGISTRY_SIZE > 0 )
- const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcQueueGetName( QueueHandle_t xQueue )
{
UBaseType_t ux;
- const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcReturn = NULL;
+
+ traceENTER_pcQueueGetName( xQueue );
configASSERT( xQueue );
@@ -2898,8 +3085,10 @@
}
}
+ traceRETURN_pcQueueGetName( pcReturn );
+
return pcReturn;
- } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+ }
#endif /* configQUEUE_REGISTRY_SIZE */
/*-----------------------------------------------------------*/
@@ -2910,6 +3099,8 @@
{
UBaseType_t ux;
+ traceENTER_vQueueUnregisterQueue( xQueue );
+
configASSERT( xQueue );
/* See if the handle of the queue being unregistered in actually in the
@@ -2932,7 +3123,9 @@
mtCOVERAGE_TEST_MARKER();
}
}
- } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+ traceRETURN_vQueueUnregisterQueue();
+ }
#endif /* configQUEUE_REGISTRY_SIZE */
/*-----------------------------------------------------------*/
@@ -2945,6 +3138,8 @@
{
Queue_t * const pxQueue = xQueue;
+ traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely );
+
/* This function should not be called by application code hence the
* 'Restricted' in its name. It is not part of the public API. It is
* designed for use by kernel code, and has special calling requirements.
@@ -2972,6 +3167,8 @@
}
prvUnlockQueue( pxQueue );
+
+ traceRETURN_vQueueWaitForMessageRestricted();
}
#endif /* configUSE_TIMERS */
@@ -2983,12 +3180,36 @@
{
QueueSetHandle_t pxQueue;
+ traceENTER_xQueueCreateSet( uxEventQueueLength );
+
pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+ traceRETURN_xQueueCreateSet( pxQueue );
+
return pxQueue;
}
-#endif /* configUSE_QUEUE_SETS */
+#endif /* #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+ QueueSetHandle_t xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+ uint8_t * pucQueueStorage,
+ StaticQueue_t * pxStaticQueue )
+ {
+ QueueSetHandle_t pxQueue;
+
+ traceENTER_xQueueCreateSetStatic( uxEventQueueLength );
+
+ pxQueue = xQueueGenericCreateStatic( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), pucQueueStorage, pxStaticQueue, queueQUEUE_TYPE_SET );
+
+ traceRETURN_xQueueCreateSetStatic( pxQueue );
+
+ return pxQueue;
+ }
+
+#endif /* #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( configUSE_QUEUE_SETS == 1 )
@@ -2998,6 +3219,8 @@
{
BaseType_t xReturn;
+ traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
+
taskENTER_CRITICAL();
{
if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
@@ -3019,6 +3242,8 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_xQueueAddToSet( xReturn );
+
return xReturn;
}
@@ -3033,6 +3258,8 @@
BaseType_t xReturn;
Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+ traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
+
if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
{
/* The queue was not a member of the set. */
@@ -3056,8 +3283,10 @@
xReturn = pdPASS;
}
+ traceRETURN_xQueueRemoveFromSet( xReturn );
+
return xReturn;
- } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+ }
#endif /* configUSE_QUEUE_SETS */
/*-----------------------------------------------------------*/
@@ -3069,7 +3298,12 @@
{
QueueSetMemberHandle_t xReturn = NULL;
- ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+ traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait );
+
+ ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait );
+
+ traceRETURN_xQueueSelectFromSet( xReturn );
+
return xReturn;
}
@@ -3082,7 +3316,12 @@
{
QueueSetMemberHandle_t xReturn = NULL;
- ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+ traceENTER_xQueueSelectFromSetFromISR( xQueueSet );
+
+ ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL );
+
+ traceRETURN_xQueueSelectFromSetFromISR( xReturn );
+
return xReturn;
}
diff --git a/Source/st_readme.txt b/Source/st_readme.txt
index 06fdf50..c3843ea 100644
--- a/Source/st_readme.txt
+++ b/Source/st_readme.txt
@@ -31,6 +31,19 @@
@endverbatim
=======
+### 20-June-2025 ###
+=========================
++ FreeRTOS: Update to FreeRTOS v11.2.0
+
++ Add files to portable folder to support MPU for CM0 cortex
+ - portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c
+ - portable/GCC/ARM_CM0/portasm.h
+ - portable/GCC/ARM_CM0/portasm.c
+
++ CMSIS_RTOS_V2 update against the latest CMSIS-FreeRTOS v11.2.0 release
+ - CMSIS_RTOS_V2/cmsis_os2.c
+ - CMSIS_RTOS_V2/freertos_os2.h
+
### 11-October-2024 ###
=========================
+ FreeRTOS: Update to FreeRTOS v10.6.2
diff --git a/Source/stream_buffer.c b/Source/stream_buffer.c
index 53208ac..66a7d07 100644
--- a/Source/stream_buffer.c
+++ b/Source/stream_buffer.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -27,7 +27,6 @@
*/
/* Standard includes. */
-#include <stdint.h>
#include <string.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@@ -40,44 +39,52 @@
#include "task.h"
#include "stream_buffer.h"
-#if ( configUSE_TASK_NOTIFICATIONS != 1 )
- #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
-#endif
-
-#if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )
- #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
-#endif
-
-/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
* for the header files above, but not in this file, in order to generate the
* correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* This entire source file will be skipped if the application is not configured
+ * to include stream buffer functionality. This #if is closed at the very bottom
+ * of this file. If you want to include stream buffers then ensure
+ * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_STREAM_BUFFERS == 1 )
+
+ #if ( configUSE_TASK_NOTIFICATIONS != 1 )
+ #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+ #endif
+
+ #if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )
+ #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
+ #endif
/* If the user has not provided application specific Rx notification macros,
* or #defined the notification macros away, then provide default implementations
* that uses task notifications. */
-/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */
-#ifndef sbRECEIVE_COMPLETED
- #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \
- vTaskSuspendAll(); \
- { \
- if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
- { \
- ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
- ( uint32_t ) 0, \
- eNoAction ); \
- ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \
- } \
- } \
- ( void ) xTaskResumeAll()
-#endif /* sbRECEIVE_COMPLETED */
+ #ifndef sbRECEIVE_COMPLETED
+ #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \
+ do \
+ { \
+ vTaskSuspendAll(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
+ { \
+ ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToSend, \
+ ( pxStreamBuffer )->uxNotificationIndex, \
+ ( uint32_t ) 0, \
+ eNoAction ); \
+ ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \
+ } \
+ } \
+ ( void ) xTaskResumeAll(); \
+ } while( 0 )
+ #endif /* sbRECEIVE_COMPLETED */
/* If user has provided a per-instance receive complete callback, then
* invoke the callback else use the receive complete macro which is provided by default for all instances.
*/
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
- #define prvRECEIVE_COMPLETED( pxStreamBuffer ) \
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvRECEIVE_COMPLETED( pxStreamBuffer ) \
do { \
if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \
{ \
@@ -88,34 +95,35 @@
sbRECEIVE_COMPLETED( ( pxStreamBuffer ) ); \
} \
} while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
- #define prvRECEIVE_COMPLETED( pxStreamBuffer ) sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvRECEIVE_COMPLETED( pxStreamBuffer ) sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )
+ #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
-#ifndef sbRECEIVE_COMPLETED_FROM_ISR
- #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \
- pxHigherPriorityTaskWoken ) \
- do { \
- UBaseType_t uxSavedInterruptStatus; \
- \
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \
- { \
- if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
- { \
- ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
- ( uint32_t ) 0, \
- eNoAction, \
- ( pxHigherPriorityTaskWoken ) ); \
- ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \
- } \
- } \
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
+ #ifndef sbRECEIVE_COMPLETED_FROM_ISR
+ #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \
+ pxHigherPriorityTaskWoken ) \
+ do { \
+ UBaseType_t uxSavedInterruptStatus; \
+ \
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
+ { \
+ ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
+ ( pxStreamBuffer )->uxNotificationIndex, \
+ ( uint32_t ) 0, \
+ eNoAction, \
+ ( pxHigherPriorityTaskWoken ) ); \
+ ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \
+ } \
+ } \
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \
} while( 0 )
-#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+ #endif /* sbRECEIVE_COMPLETED_FROM_ISR */
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
- #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \
- pxHigherPriorityTaskWoken ) \
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \
+ pxHigherPriorityTaskWoken ) \
do { \
if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \
{ \
@@ -126,73 +134,75 @@
sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \
} \
} while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
- #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
/* If the user has not provided an application specific Tx notification macro,
* or #defined the notification macro away, then provide a default
* implementation that uses task notifications.
*/
-#ifndef sbSEND_COMPLETED
- #define sbSEND_COMPLETED( pxStreamBuffer ) \
- vTaskSuspendAll(); \
- { \
- if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
- { \
- ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \
- ( uint32_t ) 0, \
- eNoAction ); \
- ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \
- } \
- } \
+ #ifndef sbSEND_COMPLETED
+ #define sbSEND_COMPLETED( pxStreamBuffer ) \
+ vTaskSuspendAll(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
+ { \
+ ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+ ( pxStreamBuffer )->uxNotificationIndex, \
+ ( uint32_t ) 0, \
+ eNoAction ); \
+ ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \
+ } \
+ } \
( void ) xTaskResumeAll()
-#endif /* sbSEND_COMPLETED */
+ #endif /* sbSEND_COMPLETED */
/* If user has provided a per-instance send completed callback, then
* invoke the callback else use the send complete macro which is provided by default for all instances.
*/
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
- #define prvSEND_COMPLETED( pxStreamBuffer ) \
- do { \
- if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \
- { \
- pxStreamBuffer->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
- } \
- else \
- { \
- sbSEND_COMPLETED( ( pxStreamBuffer ) ); \
- } \
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvSEND_COMPLETED( pxStreamBuffer ) \
+ do { \
+ if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \
+ { \
+ ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
+ } \
+ else \
+ { \
+ sbSEND_COMPLETED( ( pxStreamBuffer ) ); \
+ } \
} while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
- #define prvSEND_COMPLETED( pxStreamBuffer ) sbSEND_COMPLETED( ( pxStreamBuffer ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvSEND_COMPLETED( pxStreamBuffer ) sbSEND_COMPLETED( ( pxStreamBuffer ) )
+ #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
-#ifndef sbSEND_COMPLETE_FROM_ISR
- #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
- do { \
- UBaseType_t uxSavedInterruptStatus; \
- \
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \
- { \
- if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
- { \
- ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
- ( uint32_t ) 0, \
- eNoAction, \
- ( pxHigherPriorityTaskWoken ) ); \
- ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \
- } \
- } \
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
+ #ifndef sbSEND_COMPLETE_FROM_ISR
+ #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ do { \
+ UBaseType_t uxSavedInterruptStatus; \
+ \
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
+ { \
+ ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+ ( pxStreamBuffer )->uxNotificationIndex, \
+ ( uint32_t ) 0, \
+ eNoAction, \
+ ( pxHigherPriorityTaskWoken ) ); \
+ ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \
+ } \
+ } \
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \
} while( 0 )
-#endif /* sbSEND_COMPLETE_FROM_ISR */
+ #endif /* sbSEND_COMPLETE_FROM_ISR */
-#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
- #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
do { \
if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \
{ \
@@ -203,24 +213,23 @@
sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \
} \
} while( 0 )
-#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
- #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
-#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
-
-/*lint -restore (9026) */
+ #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
/* The number of bytes used to hold the length of a message in the buffer. */
-#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+ #define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
/* Bits stored in the ucFlags field of the stream buffer. */
-#define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
-#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+ #define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+ #define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+ #define sbFLAGS_IS_BATCHING_BUFFER ( ( uint8_t ) 4 ) /* Set if the stream buffer was created as a batching buffer, meaning the receiver task will only unblock when the trigger level exceededs. */
/*-----------------------------------------------------------*/
/* Structure that hold state information on the buffer. */
-typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+typedef struct StreamBufferDef_t
{
volatile size_t xTail; /* Index to the next item to read within the buffer. */
volatile size_t xHead; /* Index to the next item to write within the buffer. */
@@ -239,6 +248,7 @@
StreamBufferCallbackFunction_t pxSendCompletedCallback; /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */
StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete. sbRECEIVE_COMPLETED is called if this is NULL. */
#endif
+ UBaseType_t uxNotificationIndex; /* The index we are using for notification, by default tskDEFAULT_INDEX_TO_NOTIFY. */
} StreamBuffer_t;
/*
@@ -317,26 +327,34 @@
StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
+ BaseType_t xStreamBufferType,
StreamBufferCallbackFunction_t pxSendCompletedCallback,
StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
{
void * pvAllocatedMemory;
uint8_t ucFlags;
+ traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback );
+
/* In case the stream buffer is going to be used as a message buffer
* (that is, it will hold discrete messages with a little meta data that
* says how big the next message is) check the buffer will be large enough
* to hold at least one message. */
- if( xIsMessageBuffer == pdTRUE )
+ if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER )
{
/* Is a message buffer but not statically allocated. */
ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
}
+ else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER )
+ {
+ /* Is a batching buffer but not statically allocated. */
+ ucFlags = sbFLAGS_IS_BATCHING_BUFFER;
+ configASSERT( xBufferSizeBytes > 0 );
+ }
else
{
/* Not a message buffer and not statically allocated. */
@@ -361,7 +379,7 @@
* this is a quirk of the implementation that means otherwise the free
* space would be reported as one byte smaller than would be logically
* expected. */
- if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) )
+ if( xBufferSizeBytes < ( xBufferSizeBytes + 1U + sizeof( StreamBuffer_t ) ) )
{
xBufferSizeBytes++;
pvAllocatedMemory = pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) );
@@ -373,40 +391,56 @@
if( pvAllocatedMemory != NULL )
{
- prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
- ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory, /* Structure at the start of the allocated memory. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */
xBufferSizeBytes,
xTriggerLevelBytes,
ucFlags,
pxSendCompletedCallback,
pxReceiveCompletedCallback );
- traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pvAllocatedMemory ), xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pvAllocatedMemory ), xStreamBufferType );
}
else
{
- traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType );
}
- return ( StreamBufferHandle_t ) pvAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+ traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory );
+
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ return ( StreamBufferHandle_t ) pvAllocatedMemory;
}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
+ BaseType_t xStreamBufferType,
uint8_t * const pucStreamBufferStorageArea,
StaticStreamBuffer_t * const pxStaticStreamBuffer,
StreamBufferCallbackFunction_t pxSendCompletedCallback,
StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
{
- StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer;
StreamBufferHandle_t xReturn;
uint8_t ucFlags;
+ traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );
+
configASSERT( pucStreamBufferStorageArea );
configASSERT( pxStaticStreamBuffer );
configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
@@ -418,10 +452,22 @@
xTriggerLevelBytes = ( size_t ) 1;
}
- if( xIsMessageBuffer != pdFALSE )
+ /* In case the stream buffer is going to be used as a message buffer
+ * (that is, it will hold discrete messages with a little meta data that
+ * says how big the next message is) check the buffer will be large enough
+ * to hold at least one message. */
+
+ if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER )
{
/* Statically allocated message buffer. */
ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+ configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+ }
+ else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER )
+ {
+ /* Statically allocated batching buffer. */
+ ucFlags = sbFLAGS_IS_BATCHING_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+ configASSERT( xBufferSizeBytes > 0 );
}
else
{
@@ -429,12 +475,6 @@
ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
}
- /* In case the stream buffer is going to be used as a message buffer
- * (that is, it will hold discrete messages with a little meta data that
- * says how big the next message is) check the buffer will be large enough
- * to hold at least one message. */
- configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-
#if ( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
@@ -442,7 +482,7 @@
* message buffer structure. */
volatile size_t xSize = sizeof( StaticStreamBuffer_t );
configASSERT( xSize == sizeof( StreamBuffer_t ) );
- } /*lint !e529 xSize is referenced is configASSERT() is defined. */
+ }
#endif /* configASSERT_DEFINED */
if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
@@ -459,22 +499,27 @@
* again. */
pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
- traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType );
- xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer;
}
else
{
xReturn = NULL;
- traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+ traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType );
}
+ traceRETURN_xStreamBufferGenericCreateStatic( xReturn );
+
return xReturn;
}
-#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ #endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
uint8_t ** ppucStreamBufferStorageArea,
StaticStreamBuffer_t ** ppxStaticStreamBuffer )
@@ -482,6 +527,8 @@
BaseType_t xReturn;
StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+ traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer );
+
configASSERT( pxStreamBuffer );
configASSERT( ppucStreamBufferStorageArea );
configASSERT( ppxStaticStreamBuffer );
@@ -489,6 +536,9 @@
if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) != ( uint8_t ) 0 )
{
*ppucStreamBufferStorageArea = pxStreamBuffer->pucBuffer;
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
*ppxStaticStreamBuffer = ( StaticStreamBuffer_t * ) pxStreamBuffer;
xReturn = pdTRUE;
}
@@ -497,15 +547,19 @@
xReturn = pdFALSE;
}
+ traceRETURN_xStreamBufferGetStaticBuffers( xReturn );
+
return xReturn;
}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
{
StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+ traceENTER_vStreamBufferDelete( xStreamBuffer );
+
configASSERT( pxStreamBuffer );
traceSTREAM_BUFFER_DELETE( xStreamBuffer );
@@ -516,7 +570,7 @@
{
/* Both the structure and the buffer were allocated using a single call
* to pvPortMalloc(), hence only one call to vPortFree() is required. */
- vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+ vPortFree( ( void * ) pxStreamBuffer );
}
#else
{
@@ -532,6 +586,8 @@
* freed - just scrub the structure so future use will assert. */
( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
}
+
+ traceRETURN_vStreamBufferDelete();
}
/*-----------------------------------------------------------*/
@@ -545,6 +601,8 @@
UBaseType_t uxStreamBufferNumber;
#endif
+ traceENTER_xStreamBufferReset( xStreamBuffer );
+
configASSERT( pxStreamBuffer );
#if ( configUSE_TRACE_FACILITY == 1 )
@@ -588,6 +646,73 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_xStreamBufferReset( xReturn );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer )
+{
+ StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+ BaseType_t xReturn = pdFAIL;
+ StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL;
+ UBaseType_t uxSavedInterruptStatus;
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxStreamBufferNumber;
+ #endif
+
+ traceENTER_xStreamBufferResetFromISR( xStreamBuffer );
+
+ configASSERT( pxStreamBuffer );
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ /* Store the stream buffer number so it can be restored after the
+ * reset. */
+ uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+ }
+ #endif
+
+ /* Can only reset a message buffer if there are no tasks blocked on it. */
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
+ {
+ if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
+ {
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ {
+ pxSendCallback = pxStreamBuffer->pxSendCompletedCallback;
+ pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback;
+ }
+ #endif
+
+ prvInitialiseNewStreamBuffer( pxStreamBuffer,
+ pxStreamBuffer->pucBuffer,
+ pxStreamBuffer->xLength,
+ pxStreamBuffer->xTriggerLevelBytes,
+ pxStreamBuffer->ucFlags,
+ pxSendCallback,
+ pxReceiveCallback );
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+ }
+ #endif
+
+ traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer );
+
+ xReturn = pdPASS;
+ }
+ }
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xStreamBufferResetFromISR( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -598,6 +723,8 @@
StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
BaseType_t xReturn;
+ traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+
configASSERT( pxStreamBuffer );
/* It is not valid for the trigger level to be 0. */
@@ -618,6 +745,8 @@
xReturn = pdFALSE;
}
+ traceRETURN_xStreamBufferSetTriggerLevel( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -628,6 +757,8 @@
size_t xSpace;
size_t xOriginalTail;
+ traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer );
+
configASSERT( pxStreamBuffer );
/* The code below reads xTail and then xHead. This is safe if the stream
@@ -651,6 +782,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xStreamBufferSpacesAvailable( xSpace );
+
return xSpace;
}
/*-----------------------------------------------------------*/
@@ -660,9 +793,14 @@
const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReturn;
+ traceENTER_xStreamBufferBytesAvailable( xStreamBuffer );
+
configASSERT( pxStreamBuffer );
xReturn = prvBytesInBuffer( pxStreamBuffer );
+
+ traceRETURN_xStreamBufferBytesAvailable( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -678,6 +816,8 @@
TimeOut_t xTimeOut;
size_t xMaxReportedSpace = 0;
+ traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+
configASSERT( pvTxData );
configASSERT( pxStreamBuffer );
@@ -739,7 +879,7 @@
if( xSpace < xRequiredSpace )
{
/* Clear notification state as going to wait for space. */
- ( void ) xTaskNotifyStateClear( NULL );
+ ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex );
/* Should only be one writer. */
configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
@@ -754,7 +894,7 @@
taskEXIT_CRITICAL();
traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
- ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+ ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
pxStreamBuffer->xTaskWaitingToSend = NULL;
} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
}
@@ -794,6 +934,8 @@
traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
}
+ traceRETURN_xStreamBufferSend( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -807,6 +949,8 @@
size_t xReturn, xSpace;
size_t xRequiredSpace = xDataLengthBytes;
+ traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken );
+
configASSERT( pvTxData );
configASSERT( pxStreamBuffer );
@@ -831,6 +975,9 @@
/* Was a task waiting for the data? */
if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
{
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
}
else
@@ -844,6 +991,7 @@
}
traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+ traceRETURN_xStreamBufferSendFromISR( xReturn );
return xReturn;
}
@@ -892,7 +1040,10 @@
if( xDataLengthBytes != ( size_t ) 0 )
{
/* Write the data to the buffer. */
- pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */
+ /* MISRA Ref 11.5.5 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead );
}
return xDataLengthBytes;
@@ -907,6 +1058,8 @@
StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+ traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+
configASSERT( pvRxData );
configASSERT( pxStreamBuffer );
@@ -919,6 +1072,12 @@
{
xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
}
+ else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_BATCHING_BUFFER ) != ( uint8_t ) 0 )
+ {
+ /* Force task to block if the batching buffer contains less bytes than
+ * the trigger level. */
+ xBytesToStoreMessageLength = pxStreamBuffer->xTriggerLevelBytes;
+ }
else
{
xBytesToStoreMessageLength = 0;
@@ -936,11 +1095,13 @@
* xBytesToStoreMessageLength holds the number of bytes used to hold
* the length of the next discrete message. If this function was
* invoked by a stream buffer read then xBytesToStoreMessageLength will
- * be 0. */
+ * be 0. If this function was invoked by a stream batch buffer read
+ * then xBytesToStoreMessageLength will be xTriggerLevelBytes value
+ * for the buffer.*/
if( xBytesAvailable <= xBytesToStoreMessageLength )
{
/* Clear notification state as going to wait for data. */
- ( void ) xTaskNotifyStateClear( NULL );
+ ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex );
/* Should only be one reader. */
configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
@@ -957,7 +1118,7 @@
{
/* Wait for data to be available. */
traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
- ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+ ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
pxStreamBuffer->xTaskWaitingToReceive = NULL;
/* Recheck the data available after blocking. */
@@ -999,6 +1160,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xStreamBufferReceive( xReceivedLength );
+
return xReceivedLength;
}
/*-----------------------------------------------------------*/
@@ -1009,6 +1172,8 @@
size_t xReturn, xBytesAvailable;
configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+ traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+
configASSERT( pxStreamBuffer );
/* Ensure the stream buffer is being used as a message buffer. */
@@ -1039,6 +1204,8 @@
xReturn = 0;
}
+ traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -1051,6 +1218,8 @@
StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+ traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken );
+
configASSERT( pvRxData );
configASSERT( pxStreamBuffer );
@@ -1082,6 +1251,9 @@
/* Was a task waiting for space in the buffer? */
if( xReceivedLength != ( size_t ) 0 )
{
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
}
else
@@ -1095,6 +1267,7 @@
}
traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+ traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength );
return xReceivedLength;
}
@@ -1145,7 +1318,10 @@
if( xCount != ( size_t ) 0 )
{
/* Read the actual data and update the tail to mark the data as officially consumed. */
- pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+ /* MISRA Ref 11.5.5 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail );
}
return xCount;
@@ -1158,6 +1334,8 @@
BaseType_t xReturn;
size_t xTail;
+ traceENTER_xStreamBufferIsEmpty( xStreamBuffer );
+
configASSERT( pxStreamBuffer );
/* True if no bytes are available. */
@@ -1172,6 +1350,8 @@
xReturn = pdFALSE;
}
+ traceRETURN_xStreamBufferIsEmpty( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -1182,6 +1362,8 @@
size_t xBytesToStoreMessageLength;
const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+ traceENTER_xStreamBufferIsFull( xStreamBuffer );
+
configASSERT( pxStreamBuffer );
/* This generic version of the receive function is used by both message
@@ -1207,6 +1389,8 @@
xReturn = pdFALSE;
}
+ traceRETURN_xStreamBufferIsFull( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -1218,16 +1402,22 @@
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
+ traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );
+
configASSERT( pxStreamBuffer );
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
{
if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
{
- ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
- ( uint32_t ) 0,
- eNoAction,
- pxHigherPriorityTaskWoken );
+ ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+ ( pxStreamBuffer )->uxNotificationIndex,
+ ( uint32_t ) 0,
+ eNoAction,
+ pxHigherPriorityTaskWoken );
( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
xReturn = pdTRUE;
}
@@ -1236,7 +1426,9 @@
xReturn = pdFALSE;
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xStreamBufferSendCompletedFromISR( xReturn );
return xReturn;
}
@@ -1249,16 +1441,22 @@
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
+ traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );
+
configASSERT( pxStreamBuffer );
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
{
if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
{
- ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
- ( uint32_t ) 0,
- eNoAction,
- pxHigherPriorityTaskWoken );
+ ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+ ( pxStreamBuffer )->uxNotificationIndex,
+ ( uint32_t ) 0,
+ eNoAction,
+ pxHigherPriorityTaskWoken );
( pxStreamBuffer )->xTaskWaitingToSend = NULL;
xReturn = pdTRUE;
}
@@ -1267,7 +1465,9 @@
xReturn = pdFALSE;
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn );
return xReturn;
}
@@ -1289,7 +1489,7 @@
/* Write as many bytes as can be written in the first write. */
configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength );
- ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength );
/* If the number of bytes written was less than the number that could be
* written in the first write... */
@@ -1297,7 +1497,7 @@
{
/* ...then write the remaining bytes to the start of the buffer. */
configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
- ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength );
}
else
{
@@ -1337,14 +1537,14 @@
* read. Asserts check bounds of read and write. */
configASSERT( xFirstLength <= xCount );
configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength );
- ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength );
/* If the total number of wanted bytes is greater than the number
* that could be read in the first read... */
if( xCount > xFirstLength )
{
/* ...then read the remaining bytes from the start of the buffer. */
- ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength );
}
else
{
@@ -1365,7 +1565,7 @@
static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
{
-/* Returns the distance between xTail and xHead. */
+ /* Returns the distance between xTail and xHead. */
size_t xCount;
xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
@@ -1400,16 +1600,17 @@
/* The value written just has to be identifiable when looking at the
* memory. Don't use 0xA5 as that is the stack fill value and could
* result in confusion as to what is actually being observed. */
- #define STREAM_BUFFER_BUFFER_WRITE_VALUE ( 0x55 )
+ #define STREAM_BUFFER_BUFFER_WRITE_VALUE ( 0x55 )
configASSERT( memset( pucBuffer, ( int ) STREAM_BUFFER_BUFFER_WRITE_VALUE, xBufferSizeBytes ) == pucBuffer );
}
#endif
- ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+ ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
pxStreamBuffer->pucBuffer = pucBuffer;
pxStreamBuffer->xLength = xBufferSizeBytes;
pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
pxStreamBuffer->ucFlags = ucFlags;
+ pxStreamBuffer->uxNotificationIndex = tskDEFAULT_INDEX_TO_NOTIFY;
#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
{
pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback;
@@ -1417,39 +1618,101 @@
}
#else
{
+ /* MISRA Ref 11.1.1 [Object type casting] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
+ /* coverity[misra_c_2012_rule_11_1_violation] */
( void ) pxSendCompletedCallback;
+
+ /* MISRA Ref 11.1.1 [Object type casting] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
+ /* coverity[misra_c_2012_rule_11_1_violation] */
( void ) pxReceiveCompletedCallback;
}
- #endif
+ #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
}
+/*-----------------------------------------------------------*/
-#if ( configUSE_TRACE_FACILITY == 1 )
+UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer )
+{
+ StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+ traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer );
+
+ configASSERT( pxStreamBuffer );
+
+ traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( pxStreamBuffer->uxNotificationIndex );
+
+ return pxStreamBuffer->uxNotificationIndex;
+}
+/*-----------------------------------------------------------*/
+
+void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer,
+ UBaseType_t uxNotificationIndex )
+{
+ StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+ traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex );
+
+ configASSERT( pxStreamBuffer );
+
+ /* There should be no task waiting otherwise we'd never resume them. */
+ configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+
+ /* Check that the task notification index is valid. */
+ configASSERT( uxNotificationIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+ pxStreamBuffer->uxNotificationIndex = uxNotificationIndex;
+
+ traceRETURN_vStreamBufferSetStreamBufferNotificationIndex();
+}
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
{
+ traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer );
+
+ traceRETURN_uxStreamBufferGetStreamBufferNumber( xStreamBuffer->uxStreamBufferNumber );
+
return xStreamBuffer->uxStreamBufferNumber;
}
-#endif /* configUSE_TRACE_FACILITY */
+ #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/
-#if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( configUSE_TRACE_FACILITY == 1 )
void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
UBaseType_t uxStreamBufferNumber )
{
+ traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber );
+
xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+
+ traceRETURN_vStreamBufferSetStreamBufferNumber();
}
-#endif /* configUSE_TRACE_FACILITY */
+ #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/
-#if ( configUSE_TRACE_FACILITY == 1 )
+ #if ( configUSE_TRACE_FACILITY == 1 )
uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
{
- return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+ traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer );
+
+ traceRETURN_ucStreamBufferGetStreamBufferType( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
+
+ return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
}
-#endif /* configUSE_TRACE_FACILITY */
+ #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+ * to include stream buffer functionality. This #if is closed at the very bottom
+ * of this file. If you want to include stream buffers then ensure
+ * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_STREAM_BUFFERS == 1 */
diff --git a/Source/tasks.c b/Source/tasks.c
index afb7009..b4c9ba0 100644
--- a/Source/tasks.c
+++ b/Source/tasks.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -41,11 +41,17 @@
#include "timers.h"
#include "stack_macros.h"
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The default definitions are only available for non-MPU ports. The
+ * reason is that the stack alignment requirements vary for different
+ * architectures.*/
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS != 0 ) )
+ #error configKERNEL_PROVIDED_STATIC_MEMORY cannot be set to 1 when using an MPU port. The vApplicationGet*TaskMemory() functions must be provided manually.
+#endif
+
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
* for the header files above, but not in this file, in order to generate the
* correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
* functions but without including stdio.h here. */
@@ -62,10 +68,45 @@
/* If the cooperative scheduler is being used then a yield should not be
* performed just because a higher priority task has been woken. */
- #define taskYIELD_IF_USING_PREEMPTION()
+ #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB )
+ #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB )
#else
- #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
-#endif
+
+ #if ( configNUMBER_OF_CORES == 1 )
+
+/* This macro requests the running task pxTCB to yield. In single core
+ * scheduler, a running task always runs on core 0 and portYIELD_WITHIN_API()
+ * can be used to request the task running on core 0 to yield. Therefore, pxTCB
+ * is not used in this macro. */
+ #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) \
+ do { \
+ ( void ) ( pxTCB ); \
+ portYIELD_WITHIN_API(); \
+ } while( 0 )
+
+ #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) \
+ do { \
+ if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority ) \
+ { \
+ portYIELD_WITHIN_API(); \
+ } \
+ else \
+ { \
+ mtCOVERAGE_TEST_MARKER(); \
+ } \
+ } while( 0 )
+
+ #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+/* Yield the core on which this task is running. */
+ #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldCore( ( pxTCB )->xTaskRunState )
+
+/* Yield for the task if a running task has priority lower than this task. */
+ #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldForTask( pxTCB )
+
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+#endif /* if ( configUSE_PREEMPTION == 0 ) */
/* Values that can be assigned to the ucNotifyState member of the TCB. */
#define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */
@@ -102,8 +143,8 @@
#define tskSUSPENDED_CHAR ( 'S' )
/*
- * Some kernel aware debuggers require the data the debugger needs access to to
- * be global, rather than file scope.
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
*/
#ifdef portREMOVE_STATIC_QUALIFIER
#define static
@@ -115,6 +156,22 @@
#define configIDLE_TASK_NAME "IDLE"
#endif
+/* Reserve space for Core ID and null termination. */
+#if ( configNUMBER_OF_CORES > 1 )
+ /* Multi-core systems with up to 9 cores require 1 character for core ID and 1 for null termination. */
+ #if ( configMAX_TASK_NAME_LEN < 2U )
+ #error Minimum required task name length is 2. Please increase configMAX_TASK_NAME_LEN.
+ #endif
+ #define taskRESERVED_TASK_NAME_LENGTH 2U
+
+#else /* if ( configNUMBER_OF_CORES > 1 ) */
+ /* Reserve space for null termination. */
+ #if ( configMAX_TASK_NAME_LEN < 1U )
+ #error Minimum required task name length is 1. Please increase configMAX_TASK_NAME_LEN.
+ #endif
+ #define taskRESERVED_TASK_NAME_LENGTH 1U
+#endif /* if ( ( configNUMBER_OF_CORES > 1 ) */
+
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
@@ -133,22 +190,28 @@
/*-----------------------------------------------------------*/
- #define taskSELECT_HIGHEST_PRIORITY_TASK() \
- do { \
- UBaseType_t uxTopPriority = uxTopReadyPriority; \
- \
- /* Find the highest priority queue that contains ready tasks. */ \
- while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \
- { \
- configASSERT( uxTopPriority ); \
- --uxTopPriority; \
- } \
- \
+ #if ( configNUMBER_OF_CORES == 1 )
+ #define taskSELECT_HIGHEST_PRIORITY_TASK() \
+ do { \
+ UBaseType_t uxTopPriority = uxTopReadyPriority; \
+ \
+ /* Find the highest priority queue that contains ready tasks. */ \
+ while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) != pdFALSE ) \
+ { \
+ configASSERT( uxTopPriority ); \
+ --uxTopPriority; \
+ } \
+ \
/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
* the same priority get an equal share of the processor time. */ \
listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
uxTopReadyPriority = uxTopPriority; \
} while( 0 ) /* taskSELECT_HIGHEST_PRIORITY_TASK */
+ #else /* if ( configNUMBER_OF_CORES == 1 ) */
+
+ #define taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID ) prvSelectHighestPriorityTask( xCoreID )
+
+ #endif /* if ( configNUMBER_OF_CORES == 1 ) */
/*-----------------------------------------------------------*/
@@ -208,7 +271,7 @@
pxTemp = pxDelayedTaskList; \
pxDelayedTaskList = pxOverflowDelayedTaskList; \
pxOverflowDelayedTaskList = pxTemp; \
- xNumOfOverflows++; \
+ xNumOfOverflows = ( BaseType_t ) ( xNumOfOverflows + 1 ); \
prvResetNextTaskUnblockTime(); \
} while( 0 )
@@ -244,13 +307,65 @@
* responsibility of whichever module is using the value to ensure it gets set back
* to its original value when it is released. */
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
- #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U
+ #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint16_t ) 0x8000U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
- #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL
+ #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint32_t ) 0x80000000U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
- #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000000000000000ULL
+ #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint64_t ) 0x8000000000000000U )
#endif
+/* Indicates that the task is not actively running on any core. */
+#define taskTASK_NOT_RUNNING ( ( BaseType_t ) ( -1 ) )
+
+/* Indicates that the task is actively running but scheduled to yield. */
+#define taskTASK_SCHEDULED_TO_YIELD ( ( BaseType_t ) ( -2 ) )
+
+/* Returns pdTRUE if the task is actively running and not scheduled to yield. */
+#if ( configNUMBER_OF_CORES == 1 )
+ #define taskTASK_IS_RUNNING( pxTCB ) ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
+ #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
+#else
+ #define taskTASK_IS_RUNNING( pxTCB ) ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+ #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) ( ( ( pxTCB )->xTaskRunState != taskTASK_NOT_RUNNING ) ? ( pdTRUE ) : ( pdFALSE ) )
+#endif
+
+/* Indicates that the task is an Idle task. */
+#define taskATTRIBUTE_IS_IDLE ( UBaseType_t ) ( 1U << 0U )
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) )
+ #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting )
+ #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting = ( x ) )
+ #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting++ )
+ #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting-- )
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */
+
+#define taskBITS_PER_BYTE ( ( size_t ) 8 )
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* Yields the given core. This must be called from a critical section and xCoreID
+ * must be valid. This macro is not required in single core since there is only
+ * one core to yield. */
+ #define prvYieldCore( xCoreID ) \
+ do { \
+ if( ( xCoreID ) == ( BaseType_t ) portGET_CORE_ID() ) \
+ { \
+ /* Pending a yield for this core since it is in the critical section. */ \
+ xYieldPendings[ ( xCoreID ) ] = pdTRUE; \
+ } \
+ else \
+ { \
+ /* Request other core to yield if it is not requested before. */ \
+ if( pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \
+ { \
+ portYIELD_CORE( xCoreID ); \
+ pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD; \
+ } \
+ } \
+ } while( 0 )
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
/*
* Task control block. A task control block (TCB) is allocated for each task,
* and stores task state information, including a pointer to the task's context
@@ -264,11 +379,23 @@
xMPU_SETTINGS xMPUSettings; /**< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
#endif
+ #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
+ UBaseType_t uxCoreAffinityMask; /**< Used to link the task to certain cores. UBaseType_t must have greater than or equal to the number of bits as configNUMBER_OF_CORES. */
+ #endif
+
ListItem_t xStateListItem; /**< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
ListItem_t xEventListItem; /**< Used to reference a task from an event list. */
UBaseType_t uxPriority; /**< The priority of the task. 0 is the lowest priority. */
StackType_t * pxStack; /**< Points to the start of the stack. */
- char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ #if ( configNUMBER_OF_CORES > 1 )
+ volatile BaseType_t xTaskRunState; /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */
+ UBaseType_t uxTaskAttributes; /**< Task's attributes - currently used to identify the idle tasks. */
+ #endif
+ char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created. Facilitates debugging only. */
+
+ #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+ BaseType_t xPreemptionDisable; /**< Used to prevent the task from being preempted. */
+ #endif
#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
StackType_t * pxEndOfStack; /**< Points to the highest valid address for the stack. */
@@ -311,8 +438,8 @@
/* See the comments in FreeRTOS.h with the definition of
* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
- #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
- uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+ #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+ uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
#endif
#if ( INCLUDE_xTaskAbortDelay == 1 )
@@ -328,9 +455,18 @@
* below to enable the use of older kernel aware debuggers. */
typedef tskTCB TCB_t;
-/*lint -save -e956 A manual analysis and inspection has been used to determine
- * which static variables must be declared volatile. */
-portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+#if ( configNUMBER_OF_CORES == 1 )
+ /* MISRA Ref 8.4.1 [Declaration shall be visible] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+ /* coverity[misra_c_2012_rule_8_4_violation] */
+ portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+#else
+ /* MISRA Ref 8.4.1 [Declaration shall be visible] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
+ /* coverity[misra_c_2012_rule_8_4_violation] */
+ portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCBs[ configNUMBER_OF_CORES ];
+ #define pxCurrentTCB xTaskGetCurrentTaskHandle()
+#endif
/* Lists for ready and blocked tasks. --------------------
* xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but
@@ -368,16 +504,16 @@
PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U;
-PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { pdFALSE };
PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
-PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /**< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandles[ configNUMBER_OF_CORES ]; /**< Holds the handles of the idle tasks. The idle tasks are created automatically when the scheduler is started. */
/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.
* For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority
* to determine the number of priority lists to read back from the remote target. */
-const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
+static const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
/* Context switches are held pending while the scheduler is suspended. Also,
* interrupts must not manipulate the xStateListItem of a TCB, or any of the
@@ -386,24 +522,57 @@
* moves the task's event list item into the xPendingReadyList, ready for the
* kernel to move the task from the pending ready list into the real ready list
* when the scheduler is unsuspended. The pending ready list itself can only be
- * accessed from a critical section. */
+ * accessed from a critical section.
+ *
+ * Updates to uxSchedulerSuspended must be protected by both the task lock and the ISR lock
+ * and must not be done from an ISR. Reads must be protected by either lock and may be done
+ * from either an ISR or a task. */
PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) 0U;
#if ( configGENERATE_RUN_TIME_STATS == 1 )
/* Do not move these variables to function scope as doing so prevents the
* code working with debuggers that need to remove the static qualifier. */
- PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime = 0UL; /**< Holds the value of a timer/counter the last time a task was switched in. */
- PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0UL; /**< Holds the total amount of execution time as defined by the run time counter clock. */
+PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the value of a timer/counter the last time a task was switched in. */
+PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the total amount of execution time as defined by the run time counter clock. */
#endif
-/*lint -restore */
-
/*-----------------------------------------------------------*/
/* File private functions. --------------------------------*/
+/*
+ * Creates the idle tasks during scheduler start.
+ */
+static BaseType_t prvCreateIdleTasks( void );
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Checks to see if another task moved the current task out of the ready
+ * list while it was waiting to enter a critical section and yields, if so.
+ */
+ static void prvCheckForRunStateChange( void );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Yields a core, or cores if multiple priorities are not allowed to run
+ * simultaneously, to allow the task pxTCB to run.
+ */
+ static void prvYieldForTask( const TCB_t * pxTCB );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+/*
+ * Selects the highest priority available task for the given core.
+ */
+ static void prvSelectHighestPriorityTask( BaseType_t xCoreID );
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
/**
* Utility task that simply returns pdTRUE if the task referenced by xTask is
* currently in the Suspended state, or pdFALSE if the task referenced by xTask
@@ -426,13 +595,21 @@
* The idle task is automatically created and added to the ready lists upon
* creation of the first user task.
*
+ * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks are also
+ * created to ensure that each core has an idle task to run when no other
+ * task is available to run.
+ *
* The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
- * language extensions. The equivalent prototype for this function is:
+ * language extensions. The equivalent prototype for these functions are:
*
* void prvIdleTask( void *pvParameters );
+ * void prvPassiveIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+#if ( configNUMBER_OF_CORES > 1 )
+ static portTASK_FUNCTION_PROTO( prvPassiveIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+#endif
/*
* Utility to free all memory allocated by the scheduler to hold a TCB,
@@ -501,7 +678,8 @@
/*
* Return the amount of time, in ticks, that will pass before the kernel will
- * next move a task from the Blocked state to the Running state.
+ * next move a task from the Blocked state to the Running state or before the
+ * tick count overflows (whichever is earlier).
*
* This conditional compilation should use inequality to 0, not equality to 1.
* This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
@@ -536,8 +714,8 @@
* dynamically to fill in the structure's members.
*/
static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
- const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- const uint32_t ulStackDepth,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
@@ -551,6 +729,53 @@
static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
/*
+ * Create a task with static buffer for both TCB and stack. Returns a handle to
+ * the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer,
+ TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+/*
+ * Create a restricted task with static buffer for both TCB and stack. Returns
+ * a handle to the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
+ TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+
+/*
+ * Create a restricted task with static buffer for task stack and allocated buffer
+ * for TCB. Returns a handle to the task if it is created successfully. Otherwise,
+ * returns NULL.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
+ TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+
+/*
+ * Create a task with allocated buffer for both TCB and stack. Returns a handle to
+ * the task if it is created successfully. Otherwise, returns NULL.
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif /* #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+
+/*
* freertos_tasks_c_additions_init() should only be called if the user definable
* macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
* called by the function.
@@ -561,20 +786,503 @@
#endif
+#if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
+ extern void vApplicationPassiveIdleHook( void );
+#endif /* #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) */
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+/*
+ * Convert the snprintf return value to the number of characters
+ * written. The following are the possible cases:
+ *
+ * 1. The buffer supplied to snprintf is large enough to hold the
+ * generated string. The return value in this case is the number
+ * of characters actually written, not counting the terminating
+ * null character.
+ * 2. The buffer supplied to snprintf is NOT large enough to hold
+ * the generated string. The return value in this case is the
+ * number of characters that would have been written if the
+ * buffer had been sufficiently large, not counting the
+ * terminating null character.
+ * 3. Encoding error. The return value in this case is a negative
+ * number.
+ *
+ * From 1 and 2 above ==> Only when the return value is non-negative
+ * and less than the supplied buffer length, the string has been
+ * completely written.
+ */
+ static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
+ size_t n );
+
+#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+ static void prvCheckForRunStateChange( void )
+ {
+ UBaseType_t uxPrevCriticalNesting;
+ const TCB_t * pxThisTCB;
+ BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ /* This must only be called from within a task. */
+ portASSERT_IF_IN_ISR();
+
+ /* This function is always called with interrupts disabled
+ * so this is safe. */
+ pxThisTCB = pxCurrentTCBs[ xCoreID ];
+
+ while( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD )
+ {
+ /* We are only here if we just entered a critical section
+ * or if we just suspended the scheduler, and another task
+ * has requested that we yield.
+ *
+ * This is slightly complicated since we need to save and restore
+ * the suspension and critical nesting counts, as well as release
+ * and reacquire the correct locks. And then, do it all over again
+ * if our state changed again during the reacquisition. */
+ uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT( xCoreID );
+
+ if( uxPrevCriticalNesting > 0U )
+ {
+ portSET_CRITICAL_NESTING_COUNT( xCoreID, 0U );
+ portRELEASE_ISR_LOCK( xCoreID );
+ }
+ else
+ {
+ /* The scheduler is suspended. uxSchedulerSuspended is updated
+ * only when the task is not requested to yield. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ portRELEASE_TASK_LOCK( xCoreID );
+ portMEMORY_BARRIER();
+ configASSERT( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD );
+
+ portENABLE_INTERRUPTS();
+
+ /* Enabling interrupts should cause this core to immediately service
+ * the pending interrupt and yield. After servicing the pending interrupt,
+ * the task needs to re-evaluate its run state within this loop, as
+ * other cores may have requested this task to yield, potentially altering
+ * its run state. */
+
+ portDISABLE_INTERRUPTS();
+
+ xCoreID = ( BaseType_t ) portGET_CORE_ID();
+ portGET_TASK_LOCK( xCoreID );
+ portGET_ISR_LOCK( xCoreID );
+
+ portSET_CRITICAL_NESTING_COUNT( xCoreID, uxPrevCriticalNesting );
+
+ if( uxPrevCriticalNesting == 0U )
+ {
+ portRELEASE_ISR_LOCK( xCoreID );
+ }
+ }
+ }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+ static void prvYieldForTask( const TCB_t * pxTCB )
+ {
+ BaseType_t xLowestPriorityToPreempt;
+ BaseType_t xCurrentCoreTaskPriority;
+ BaseType_t xLowestPriorityCore = ( BaseType_t ) -1;
+ BaseType_t xCoreID;
+ const BaseType_t xCurrentCoreID = portGET_CORE_ID();
+
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ BaseType_t xYieldCount = 0;
+ #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+ /* This must be called from a critical section. */
+ configASSERT( portGET_CRITICAL_NESTING_COUNT( xCurrentCoreID ) > 0U );
+
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+
+ /* No task should yield for this one if it is a lower priority
+ * than priority level of currently ready tasks. */
+ if( pxTCB->uxPriority >= uxTopReadyPriority )
+ #else
+ /* Yield is not required for a task which is already running. */
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
+ #endif
+ {
+ xLowestPriorityToPreempt = ( BaseType_t ) pxTCB->uxPriority;
+
+ /* xLowestPriorityToPreempt will be decremented to -1 if the priority of pxTCB
+ * is 0. This is ok as we will give system idle tasks a priority of -1 below. */
+ --xLowestPriorityToPreempt;
+
+ for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+ {
+ xCurrentCoreTaskPriority = ( BaseType_t ) pxCurrentTCBs[ xCoreID ]->uxPriority;
+
+ /* System idle tasks are being assigned a priority of tskIDLE_PRIORITY - 1 here. */
+ if( ( pxCurrentTCBs[ xCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+ {
+ xCurrentCoreTaskPriority = ( BaseType_t ) ( xCurrentCoreTaskPriority - 1 );
+ }
+
+ if( ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCoreID ] ) != pdFALSE ) && ( xYieldPendings[ xCoreID ] == pdFALSE ) )
+ {
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
+ #endif
+ {
+ if( xCurrentCoreTaskPriority <= xLowestPriorityToPreempt )
+ {
+ #if ( configUSE_CORE_AFFINITY == 1 )
+ if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+ #endif
+ {
+ #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+ if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
+ #endif
+ {
+ xLowestPriorityToPreempt = xCurrentCoreTaskPriority;
+ xLowestPriorityCore = xCoreID;
+ }
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ {
+ /* Yield all currently running non-idle tasks with a priority lower than
+ * the task that needs to run. */
+ if( ( xCurrentCoreTaskPriority > ( ( BaseType_t ) tskIDLE_PRIORITY - 1 ) ) &&
+ ( xCurrentCoreTaskPriority < ( BaseType_t ) pxTCB->uxPriority ) )
+ {
+ prvYieldCore( xCoreID );
+ xYieldCount++;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ if( ( xYieldCount == 0 ) && ( xLowestPriorityCore >= 0 ) )
+ #else /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+ if( xLowestPriorityCore >= 0 )
+ #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+ {
+ prvYieldCore( xLowestPriorityCore );
+ }
+
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ /* Verify that the calling core always yields to higher priority tasks. */
+ if( ( ( pxCurrentTCBs[ xCurrentCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) &&
+ ( pxTCB->uxPriority > pxCurrentTCBs[ xCurrentCoreID ]->uxPriority ) )
+ {
+ configASSERT( ( xYieldPendings[ xCurrentCoreID ] == pdTRUE ) ||
+ ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCurrentCoreID ] ) == pdFALSE ) );
+ }
+ #endif
+ }
+ }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+ static void prvSelectHighestPriorityTask( BaseType_t xCoreID )
+ {
+ UBaseType_t uxCurrentPriority = uxTopReadyPriority;
+ BaseType_t xTaskScheduled = pdFALSE;
+ BaseType_t xDecrementTopPriority = pdTRUE;
+ TCB_t * pxTCB = NULL;
+
+ #if ( configUSE_CORE_AFFINITY == 1 )
+ const TCB_t * pxPreviousTCB = NULL;
+ #endif
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ BaseType_t xPriorityDropped = pdFALSE;
+ #endif
+
+ /* This function should be called when scheduler is running. */
+ configASSERT( xSchedulerRunning == pdTRUE );
+
+ /* A new task is created and a running task with the same priority yields
+ * itself to run the new task. When a running task yields itself, it is still
+ * in the ready list. This running task will be selected before the new task
+ * since the new task is always added to the end of the ready list.
+ * The other problem is that the running task still in the same position of
+ * the ready list when it yields itself. It is possible that it will be selected
+ * earlier then other tasks which waits longer than this task.
+ *
+ * To fix these problems, the running task should be put to the end of the
+ * ready list before searching for the ready task in the ready list. */
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
+ &pxCurrentTCBs[ xCoreID ]->xStateListItem ) == pdTRUE )
+ {
+ ( void ) uxListRemove( &pxCurrentTCBs[ xCoreID ]->xStateListItem );
+ vListInsertEnd( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
+ &pxCurrentTCBs[ xCoreID ]->xStateListItem );
+ }
+
+ while( xTaskScheduled == pdFALSE )
+ {
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ {
+ if( uxCurrentPriority < uxTopReadyPriority )
+ {
+ /* We can't schedule any tasks, other than idle, that have a
+ * priority lower than the priority of a task currently running
+ * on another core. */
+ uxCurrentPriority = tskIDLE_PRIORITY;
+ }
+ }
+ #endif
+
+ if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxCurrentPriority ] ) ) == pdFALSE )
+ {
+ const List_t * const pxReadyList = &( pxReadyTasksLists[ uxCurrentPriority ] );
+ const ListItem_t * pxEndMarker = listGET_END_MARKER( pxReadyList );
+ ListItem_t * pxIterator;
+
+ /* The ready task list for uxCurrentPriority is not empty, so uxTopReadyPriority
+ * must not be decremented any further. */
+ xDecrementTopPriority = pdFALSE;
+
+ for( pxIterator = listGET_HEAD_ENTRY( pxReadyList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
+ {
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator );
+
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ {
+ /* When falling back to the idle priority because only one priority
+ * level is allowed to run at a time, we should ONLY schedule the true
+ * idle tasks, not user tasks at the idle priority. */
+ if( uxCurrentPriority < uxTopReadyPriority )
+ {
+ if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U )
+ {
+ continue;
+ }
+ }
+ }
+ #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+ if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+ {
+ #if ( configUSE_CORE_AFFINITY == 1 )
+ if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+ #endif
+ {
+ /* If the task is not being executed by any core swap it in. */
+ pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING;
+ #if ( configUSE_CORE_AFFINITY == 1 )
+ pxPreviousTCB = pxCurrentTCBs[ xCoreID ];
+ #endif
+ pxTCB->xTaskRunState = xCoreID;
+ pxCurrentTCBs[ xCoreID ] = pxTCB;
+ xTaskScheduled = pdTRUE;
+ }
+ }
+ else if( pxTCB == pxCurrentTCBs[ xCoreID ] )
+ {
+ configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) );
+
+ #if ( configUSE_CORE_AFFINITY == 1 )
+ if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+ #endif
+ {
+ /* The task is already running on this core, mark it as scheduled. */
+ pxTCB->xTaskRunState = xCoreID;
+ xTaskScheduled = pdTRUE;
+ }
+ }
+ else
+ {
+ /* This task is running on the core other than xCoreID. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xTaskScheduled != pdFALSE )
+ {
+ /* A task has been selected to run on this core. */
+ break;
+ }
+ }
+ }
+ else
+ {
+ if( xDecrementTopPriority != pdFALSE )
+ {
+ uxTopReadyPriority--;
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ {
+ xPriorityDropped = pdTRUE;
+ }
+ #endif
+ }
+ }
+
+ /* There are configNUMBER_OF_CORES Idle tasks created when scheduler started.
+ * The scheduler should be able to select a task to run when uxCurrentPriority
+ * is tskIDLE_PRIORITY. uxCurrentPriority is never decreased to value blow
+ * tskIDLE_PRIORITY. */
+ if( uxCurrentPriority > tskIDLE_PRIORITY )
+ {
+ uxCurrentPriority--;
+ }
+ else
+ {
+ /* This function is called when idle task is not created. Break the
+ * loop to prevent uxCurrentPriority overrun. */
+ break;
+ }
+ }
+
+ #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
+ {
+ if( xTaskScheduled == pdTRUE )
+ {
+ if( xPriorityDropped != pdFALSE )
+ {
+ /* There may be several ready tasks that were being prevented from running because there was
+ * a higher priority task running. Now that the last of the higher priority tasks is no longer
+ * running, make sure all the other idle tasks yield. */
+ BaseType_t x;
+
+ for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configNUMBER_OF_CORES; x++ )
+ {
+ if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+ {
+ prvYieldCore( x );
+ }
+ }
+ }
+ }
+ }
+ #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
+
+ #if ( configUSE_CORE_AFFINITY == 1 )
+ {
+ if( xTaskScheduled == pdTRUE )
+ {
+ if( ( pxPreviousTCB != NULL ) && ( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxPreviousTCB->uxPriority ] ), &( pxPreviousTCB->xStateListItem ) ) != pdFALSE ) )
+ {
+ /* A ready task was just evicted from this core. See if it can be
+ * scheduled on any other core. */
+ UBaseType_t uxCoreMap = pxPreviousTCB->uxCoreAffinityMask;
+ BaseType_t xLowestPriority = ( BaseType_t ) pxPreviousTCB->uxPriority;
+ BaseType_t xLowestPriorityCore = -1;
+ BaseType_t x;
+
+ if( ( pxPreviousTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+ {
+ xLowestPriority = xLowestPriority - 1;
+ }
+
+ if( ( uxCoreMap & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
+ {
+ /* pxPreviousTCB was removed from this core and this core is not excluded
+ * from it's core affinity mask.
+ *
+ * pxPreviousTCB is preempted by the new higher priority task
+ * pxCurrentTCBs[ xCoreID ]. When searching a new core for pxPreviousTCB,
+ * we do not need to look at the cores on which pxCurrentTCBs[ xCoreID ]
+ * is allowed to run. The reason is - when more than one cores are
+ * eligible for an incoming task, we preempt the core with the minimum
+ * priority task. Because this core (i.e. xCoreID) was preempted for
+ * pxCurrentTCBs[ xCoreID ], this means that all the others cores
+ * where pxCurrentTCBs[ xCoreID ] can run, are running tasks with priority
+ * no lower than pxPreviousTCB's priority. Therefore, the only cores where
+ * which can be preempted for pxPreviousTCB are the ones where
+ * pxCurrentTCBs[ xCoreID ] is not allowed to run (and obviously,
+ * pxPreviousTCB is allowed to run).
+ *
+ * This is an optimization which reduces the number of cores needed to be
+ * searched for pxPreviousTCB to run. */
+ uxCoreMap &= ~( pxCurrentTCBs[ xCoreID ]->uxCoreAffinityMask );
+ }
+ else
+ {
+ /* pxPreviousTCB's core affinity mask is changed and it is no longer
+ * allowed to run on this core. Searching all the cores in pxPreviousTCB's
+ * new core affinity mask to find a core on which it can run. */
+ }
+
+ uxCoreMap &= ( ( 1U << configNUMBER_OF_CORES ) - 1U );
+
+ for( x = ( ( BaseType_t ) configNUMBER_OF_CORES - 1 ); x >= ( BaseType_t ) 0; x-- )
+ {
+ UBaseType_t uxCore = ( UBaseType_t ) x;
+ BaseType_t xTaskPriority;
+
+ if( ( uxCoreMap & ( ( UBaseType_t ) 1U << uxCore ) ) != 0U )
+ {
+ xTaskPriority = ( BaseType_t ) pxCurrentTCBs[ uxCore ]->uxPriority;
+
+ if( ( pxCurrentTCBs[ uxCore ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
+ {
+ xTaskPriority = xTaskPriority - ( BaseType_t ) 1;
+ }
+
+ uxCoreMap &= ~( ( UBaseType_t ) 1U << uxCore );
+
+ if( ( xTaskPriority < xLowestPriority ) &&
+ ( taskTASK_IS_RUNNING( pxCurrentTCBs[ uxCore ] ) != pdFALSE ) &&
+ ( xYieldPendings[ uxCore ] == pdFALSE ) )
+ {
+ #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+ if( pxCurrentTCBs[ uxCore ]->xPreemptionDisable == pdFALSE )
+ #endif
+ {
+ xLowestPriority = xTaskPriority;
+ xLowestPriorityCore = ( BaseType_t ) uxCore;
+ }
+ }
+ }
+ }
+
+ if( xLowestPriorityCore >= 0 )
+ {
+ prvYieldCore( xLowestPriorityCore );
+ }
+ }
+ }
+ }
+ #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) */
+ }
+
+#endif /* ( configNUMBER_OF_CORES > 1 ) */
+
/*-----------------------------------------------------------*/
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
- const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- const uint32_t ulStackDepth,
- void * const pvParameters,
- UBaseType_t uxPriority,
- StackType_t * const puxStackBuffer,
- StaticTask_t * const pxTaskBuffer )
+ static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer,
+ TaskHandle_t * const pxCreatedTask )
{
TCB_t * pxNewTCB;
- TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
configASSERT( pxTaskBuffer != NULL );
@@ -586,7 +1294,7 @@
* structure. */
volatile size_t xSize = sizeof( StaticTask_t );
configASSERT( xSize == sizeof( TCB_t ) );
- ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+ ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not used. */
}
#endif /* configASSERT_DEFINED */
@@ -594,11 +1302,14 @@
{
/* The memory used for the task's TCB and stack are passed into this
* function - use them. */
- pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
- memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ pxNewTCB = ( TCB_t * ) pxTaskBuffer;
+ ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
- #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+ #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
{
/* Tasks can be created statically or dynamically, so note this
* task was created statically in case the task is later deleted. */
@@ -606,27 +1317,97 @@
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
- prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+ prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+ }
+ else
+ {
+ pxNewTCB = NULL;
+ }
+
+ return pxNewTCB;
+ }
+/*-----------------------------------------------------------*/
+
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer )
+ {
+ TaskHandle_t xReturn = NULL;
+ TCB_t * pxNewTCB;
+
+ traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+
+ pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+
+ if( pxNewTCB != NULL )
+ {
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
+ }
+ #endif
+
prvAddNewTaskToReadyList( pxNewTCB );
}
else
{
- xReturn = NULL;
+ mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xTaskCreateStatic( xReturn );
+
return xReturn;
}
+/*-----------------------------------------------------------*/
+
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer,
+ UBaseType_t uxCoreAffinityMask )
+ {
+ TaskHandle_t xReturn = NULL;
+ TCB_t * pxNewTCB;
+
+ traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask );
+
+ pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );
+
+ if( pxNewTCB != NULL )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+ prvAddNewTaskToReadyList( pxNewTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceRETURN_xTaskCreateStaticAffinitySet( xReturn );
+
+ return xReturn;
+ }
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
#endif /* SUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
- BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
- TaskHandle_t * pxCreatedTask )
+ static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
+ TaskHandle_t * const pxCreatedTask )
{
TCB_t * pxNewTCB;
- BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
@@ -637,7 +1418,7 @@
* on the implementation of the port malloc function and whether or
* not static allocation is being used. */
pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
- memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+ ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
@@ -652,42 +1433,110 @@
prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
pxTaskDefinition->pcName,
- ( uint32_t ) pxTaskDefinition->usStackDepth,
+ pxTaskDefinition->usStackDepth,
pxTaskDefinition->pvParameters,
pxTaskDefinition->uxPriority,
pxCreatedTask, pxNewTCB,
pxTaskDefinition->xRegions );
+ }
+ else
+ {
+ pxNewTCB = NULL;
+ }
+
+ return pxNewTCB;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
+ TaskHandle_t * pxCreatedTask )
+ {
+ TCB_t * pxNewTCB;
+ BaseType_t xReturn;
+
+ traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
+
+ configASSERT( pxTaskDefinition != NULL );
+
+ pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );
+
+ if( pxNewTCB != NULL )
+ {
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
+ }
+ #endif
prvAddNewTaskToReadyList( pxNewTCB );
xReturn = pdPASS;
}
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ }
+
+ traceRETURN_xTaskCreateRestrictedStatic( xReturn );
return xReturn;
}
+/*-----------------------------------------------------------*/
+
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+ UBaseType_t uxCoreAffinityMask,
+ TaskHandle_t * pxCreatedTask )
+ {
+ TCB_t * pxNewTCB;
+ BaseType_t xReturn;
+
+ traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );
+
+ configASSERT( pxTaskDefinition != NULL );
+
+ pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );
+
+ if( pxNewTCB != NULL )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+ prvAddNewTaskToReadyList( pxNewTCB );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ }
+
+ traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn );
+
+ return xReturn;
+ }
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
- BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
- TaskHandle_t * pxCreatedTask )
+ static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
+ TaskHandle_t * const pxCreatedTask )
{
TCB_t * pxNewTCB;
- BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
configASSERT( pxTaskDefinition->puxStackBuffer );
if( pxTaskDefinition->puxStackBuffer != NULL )
{
- /* Allocate space for the TCB. Where the memory comes from depends
- * on the implementation of the port malloc function and whether or
- * not static allocation is being used. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
if( pxNewTCB != NULL )
{
- memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+ ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
@@ -703,34 +1552,101 @@
prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
pxTaskDefinition->pcName,
- ( uint32_t ) pxTaskDefinition->usStackDepth,
+ pxTaskDefinition->usStackDepth,
pxTaskDefinition->pvParameters,
pxTaskDefinition->uxPriority,
pxCreatedTask, pxNewTCB,
pxTaskDefinition->xRegions );
-
- prvAddNewTaskToReadyList( pxNewTCB );
- xReturn = pdPASS;
}
}
+ else
+ {
+ pxNewTCB = NULL;
+ }
+
+ return pxNewTCB;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
+ TaskHandle_t * pxCreatedTask )
+ {
+ TCB_t * pxNewTCB;
+ BaseType_t xReturn;
+
+ traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
+
+ pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );
+
+ if( pxNewTCB != NULL )
+ {
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
+ }
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+ prvAddNewTaskToReadyList( pxNewTCB );
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ }
+
+ traceRETURN_xTaskCreateRestricted( xReturn );
return xReturn;
}
+/*-----------------------------------------------------------*/
+
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
+ UBaseType_t uxCoreAffinityMask,
+ TaskHandle_t * pxCreatedTask )
+ {
+ TCB_t * pxNewTCB;
+ BaseType_t xReturn;
+
+ traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );
+
+ pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );
+
+ if( pxNewTCB != NULL )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+ prvAddNewTaskToReadyList( pxNewTCB );
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ }
+
+ traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn );
+
+ return xReturn;
+ }
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
- BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
- const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- const configSTACK_DEPTH_TYPE usStackDepth,
- void * const pvParameters,
- UBaseType_t uxPriority,
- TaskHandle_t * const pxCreatedTask )
+ static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * const pxCreatedTask )
{
TCB_t * pxNewTCB;
- BaseType_t xReturn;
/* If the stack grows down then allocate the stack then the TCB so the stack
* does not grow into the TCB. Likewise if the stack grows up then allocate
@@ -740,16 +1656,22 @@
/* Allocate space for the TCB. Where the memory comes from depends on
* the implementation of the port malloc function and whether or not static
* allocation is being used. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
if( pxNewTCB != NULL )
{
- memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+ ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
/* Allocate space for the stack used by the task being created.
* The base of the stack memory stored in the TCB so the task can
* be deleted later if required. */
- pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) );
if( pxNewTCB->pxStack == NULL )
{
@@ -764,16 +1686,22 @@
StackType_t * pxStack;
/* Allocate space for the stack used by the task being created. */
- pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxStack = pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) );
if( pxStack != NULL )
{
/* Allocate space for the TCB. */
- pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
if( pxNewTCB != NULL )
{
- memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+ ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
@@ -794,7 +1722,7 @@
if( pxNewTCB != NULL )
{
- #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+ #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
{
/* Tasks can be created statically or dynamically, so note this
* task was created dynamically in case it is later deleted. */
@@ -802,7 +1730,36 @@
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
- prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+ prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+ }
+
+ return pxNewTCB;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * const pxCreatedTask )
+ {
+ TCB_t * pxNewTCB;
+ BaseType_t xReturn;
+
+ traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+ pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+ if( pxNewTCB != NULL )
+ {
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
+ }
+ #endif
+
prvAddNewTaskToReadyList( pxNewTCB );
xReturn = pdPASS;
}
@@ -811,15 +1768,53 @@
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
}
+ traceRETURN_xTaskCreate( xReturn );
+
return xReturn;
}
+/*-----------------------------------------------------------*/
+
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ UBaseType_t uxCoreAffinityMask,
+ TaskHandle_t * const pxCreatedTask )
+ {
+ TCB_t * pxNewTCB;
+ BaseType_t xReturn;
+
+ traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask );
+
+ pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );
+
+ if( pxNewTCB != NULL )
+ {
+ /* Set the task's affinity before scheduling it. */
+ pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+ prvAddNewTaskToReadyList( pxNewTCB );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ }
+
+ traceRETURN_xTaskCreateAffinitySet( xReturn );
+
+ return xReturn;
+ }
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
- const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- const uint32_t ulStackDepth,
+ const char * const pcName,
+ const configSTACK_DEPTH_TYPE uxStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
@@ -848,7 +1843,7 @@
#if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
- ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) uxStackDepth * sizeof( StackType_t ) );
}
#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
@@ -858,11 +1853,11 @@
* by the port. */
#if ( portSTACK_GROWTH < 0 )
{
- pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
- pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
+ pxTopOfStack = &( pxNewTCB->pxStack[ uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 ] );
+ pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
/* Check the alignment of the calculated top of stack is correct. */
- configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) );
#if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
{
@@ -875,13 +1870,14 @@
#else /* portSTACK_GROWTH */
{
pxTopOfStack = pxNewTCB->pxStack;
+ pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
- /* Check the alignment of the stack buffer is correct. */
- configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+ /* Check the alignment of the calculated top of stack is correct. */
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) );
/* The other extreme of the stack space is required if stack checking is
* performed. */
- pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+ pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 );
}
#endif /* portSTACK_GROWTH */
@@ -907,7 +1903,7 @@
/* Ensure the name string is terminated in the case that the string length
* was greater or equal to configMAX_TASK_NAME_LEN. */
- pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1U ] = '\0';
}
else
{
@@ -941,12 +1937,12 @@
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
/* Event lists are always in priority order. */
- listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority );
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
#if ( portUSING_MPU_WRAPPERS == 1 )
{
- vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+ vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, uxStackDepth );
}
#else
{
@@ -1014,6 +2010,19 @@
}
#endif /* portUSING_MPU_WRAPPERS */
+ /* Initialize task state and task attributes. */
+ #if ( configNUMBER_OF_CORES > 1 )
+ {
+ pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING;
+
+ /* Is this an idle task? */
+ if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) ( &prvIdleTask ) ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) ( &prvPassiveIdleTask ) ) )
+ {
+ pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE;
+ }
+ }
+ #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
if( pxCreatedTask != NULL )
{
/* Pass the handle out in an anonymous way. The handle can be used to
@@ -1027,42 +2036,28 @@
}
/*-----------------------------------------------------------*/
-static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
-{
- /* Ensure interrupts don't access the task lists while the lists are being
- * updated. */
- taskENTER_CRITICAL();
+#if ( configNUMBER_OF_CORES == 1 )
+
+ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
{
- uxCurrentNumberOfTasks++;
-
- if( pxCurrentTCB == NULL )
+ /* Ensure interrupts don't access the task lists while the lists are being
+ * updated. */
+ taskENTER_CRITICAL();
{
- /* There are no other tasks, or all the other tasks are in
- * the suspended state - make this the current task. */
- pxCurrentTCB = pxNewTCB;
+ uxCurrentNumberOfTasks = ( UBaseType_t ) ( uxCurrentNumberOfTasks + 1U );
- if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+ if( pxCurrentTCB == NULL )
{
- /* This is the first task to be created so do the preliminary
- * initialisation required. We will not recover if this call
- * fails, but we will report the failure. */
- prvInitialiseTaskLists();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- /* If the scheduler is not already running, make this task the
- * current task if it is the highest priority task to be created
- * so far. */
- if( xSchedulerRunning == pdFALSE )
- {
- if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+ /* There are no other tasks, or all the other tasks are in
+ * the suspended state - make this the current task. */
+ pxCurrentTCB = pxNewTCB;
+
+ if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
{
- pxCurrentTCB = pxNewTCB;
+ /* This is the first task to be created so do the preliminary
+ * initialisation required. We will not recover if this call
+ * fails, but we will report the failure. */
+ prvInitialiseTaskLists();
}
else
{
@@ -1071,44 +2066,146 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ /* If the scheduler is not already running, make this task the
+ * current task if it is the highest priority task to be created
+ * so far. */
+ if( xSchedulerRunning == pdFALSE )
+ {
+ if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+ {
+ pxCurrentTCB = pxNewTCB;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
+
+ uxTaskNumber++;
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ /* Add a counter into the TCB for tracing only. */
+ pxNewTCB->uxTCBNumber = uxTaskNumber;
+ }
+ #endif /* configUSE_TRACE_FACILITY */
+ traceTASK_CREATE( pxNewTCB );
+
+ prvAddTaskToReadyList( pxNewTCB );
+
+ portSETUP_TCB( pxNewTCB );
}
+ taskEXIT_CRITICAL();
- uxTaskNumber++;
-
- #if ( configUSE_TRACE_FACILITY == 1 )
+ if( xSchedulerRunning != pdFALSE )
{
- /* Add a counter into the TCB for tracing only. */
- pxNewTCB->uxTCBNumber = uxTaskNumber;
- }
- #endif /* configUSE_TRACE_FACILITY */
- traceTASK_CREATE( pxNewTCB );
-
- prvAddTaskToReadyList( pxNewTCB );
-
- portSETUP_TCB( pxNewTCB );
- }
- taskEXIT_CRITICAL();
-
- if( xSchedulerRunning != pdFALSE )
- {
- /* If the created task is of a higher priority than the current task
- * then it should run now. */
- if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
- {
- taskYIELD_IF_USING_PREEMPTION();
+ /* If the created task is of a higher priority than the current task
+ * then it should run now. */
+ taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
- else
+
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
{
- mtCOVERAGE_TEST_MARKER();
+ /* Ensure interrupts don't access the task lists while the lists are being
+ * updated. */
+ taskENTER_CRITICAL();
+ {
+ uxCurrentNumberOfTasks++;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+ {
+ /* This is the first task to be created so do the preliminary
+ * initialisation required. We will not recover if this call
+ * fails, but we will report the failure. */
+ prvInitialiseTaskLists();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* All the cores start with idle tasks before the SMP scheduler
+ * is running. Idle tasks are assigned to cores when they are
+ * created in prvCreateIdleTasks(). */
+ }
+
+ uxTaskNumber++;
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ /* Add a counter into the TCB for tracing only. */
+ pxNewTCB->uxTCBNumber = uxTaskNumber;
+ }
+ #endif /* configUSE_TRACE_FACILITY */
+ traceTASK_CREATE( pxNewTCB );
+
+ prvAddTaskToReadyList( pxNewTCB );
+
+ portSETUP_TCB( pxNewTCB );
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* If the created task is of a higher priority than another
+ * currently running task and preemption is on then it should
+ * run now. */
+ taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
}
-}
+
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+ static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
+ size_t n )
+ {
+ size_t uxCharsWritten;
+
+ if( iSnprintfReturnValue < 0 )
+ {
+ /* Encoding error - Return 0 to indicate that nothing
+ * was written to the buffer. */
+ uxCharsWritten = 0;
+ }
+ else if( iSnprintfReturnValue >= ( int ) n )
+ {
+ /* This is the case when the supplied buffer is not
+ * large to hold the generated string. Return the
+ * number of characters actually written without
+ * counting the terminating NULL character. */
+ uxCharsWritten = n - 1U;
+ }
+ else
+ {
+ /* Complete string was written to the buffer. */
+ uxCharsWritten = ( size_t ) iSnprintfReturnValue;
+ }
+
+ return uxCharsWritten;
+ }
+
+#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
@@ -1116,12 +2213,17 @@
void vTaskDelete( TaskHandle_t xTaskToDelete )
{
TCB_t * pxTCB;
+ BaseType_t xDeleteTCBInIdleTask = pdFALSE;
+ BaseType_t xTaskIsRunningOrYielding;
+
+ traceENTER_vTaskDelete( xTaskToDelete );
taskENTER_CRITICAL();
{
/* If null is passed in here then it is the calling task that is
* being deleted. */
pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+ configASSERT( pxTCB != NULL );
/* Remove task from the ready/delayed list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
@@ -1149,13 +2251,22 @@
* not return. */
uxTaskNumber++;
- if( pxTCB == pxCurrentTCB )
+ /* Use temp variable as distinct sequence points for reading volatile
+ * variables prior to a logical operator to ensure compliance with
+ * MISRA C 2012 Rule 13.5. */
+ xTaskIsRunningOrYielding = taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB );
+
+ /* If the task is running (or yielding), we must add it to the
+ * termination list so that an idle task can delete it when it is
+ * no longer running. */
+ if( ( xSchedulerRunning != pdFALSE ) && ( xTaskIsRunningOrYielding != pdFALSE ) )
{
- /* A task is deleting itself. This cannot complete within the
- * task itself, as a context switch to another task is required.
- * Place the task in the termination list. The idle task will
- * check the termination list and free up any memory allocated by
- * the scheduler for the TCB and stack of the deleted task. */
+ /* A running task or a task which is scheduled to yield is being
+ * deleted. This cannot complete when the task is still running
+ * on a core, as a context switch to another task is required.
+ * Place the task in the termination list. The idle task will check
+ * the termination list and free up any memory allocated by the
+ * scheduler for the TCB and stack of the deleted task. */
vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
/* Increment the ucTasksDeleted variable so the idle task knows
@@ -1167,12 +2278,43 @@
* portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
traceTASK_DELETE( pxTCB );
+ /* Delete the task TCB in idle task. */
+ xDeleteTCBInIdleTask = pdTRUE;
+
/* The pre-delete hook is primarily for the Windows simulator,
* in which Windows specific clean up operations are performed,
* after which it is not possible to yield away from this task -
* hence xYieldPending is used to latch that a context switch is
* required. */
- portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+ #if ( configNUMBER_OF_CORES == 1 )
+ portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ 0 ] ) );
+ #else
+ portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ pxTCB->xTaskRunState ] ) );
+ #endif
+
+ /* In the case of SMP, it is possible that the task being deleted
+ * is running on another core. We must evict the task before
+ * exiting the critical section to ensure that the task cannot
+ * take an action which puts it back on ready/state/event list,
+ * thereby nullifying the delete operation. Once evicted, the
+ * task won't be scheduled ever as it will no longer be on the
+ * ready list. */
+ #if ( configNUMBER_OF_CORES > 1 )
+ {
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+ {
+ configASSERT( uxSchedulerSuspended == 0 );
+ taskYIELD_WITHIN_API();
+ }
+ else
+ {
+ prvYieldCore( pxTCB->xTaskRunState );
+ }
+ }
+ }
+ #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
}
else
{
@@ -1189,25 +2331,31 @@
/* If the task is not deleting itself, call prvDeleteTCB from outside of
* critical section. If a task deletes itself, prvDeleteTCB is called
* from prvCheckTasksWaitingTermination which is called from Idle task. */
- if( pxTCB != pxCurrentTCB )
+ if( xDeleteTCBInIdleTask != pdTRUE )
{
prvDeleteTCB( pxTCB );
}
/* Force a reschedule if it is the currently running task that has just
* been deleted. */
- if( xSchedulerRunning != pdFALSE )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- if( pxTCB == pxCurrentTCB )
+ if( xSchedulerRunning != pdFALSE )
{
- configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
- portYIELD_WITHIN_API();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
+ if( pxTCB == pxCurrentTCB )
+ {
+ configASSERT( uxSchedulerSuspended == 0 );
+ taskYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ traceRETURN_vTaskDelete();
}
#endif /* INCLUDE_vTaskDelete */
@@ -1221,9 +2369,10 @@
TickType_t xTimeToWake;
BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+ traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+
configASSERT( pxPreviousWakeTime );
configASSERT( ( xTimeIncrement > 0U ) );
- configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
vTaskSuspendAll();
{
@@ -1231,6 +2380,8 @@
* block. */
const TickType_t xConstTickCount = xTickCount;
+ configASSERT( uxSchedulerSuspended == 1U );
+
/* Generate the tick time at which the task wants to wake. */
xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
@@ -1287,13 +2438,15 @@
* have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
{
- portYIELD_WITHIN_API();
+ taskYIELD_WITHIN_API();
}
else
{
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xTaskDelayUntil( xShouldDelay );
+
return xShouldDelay;
}
@@ -1306,12 +2459,15 @@
{
BaseType_t xAlreadyYielded = pdFALSE;
+ traceENTER_vTaskDelay( xTicksToDelay );
+
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
{
- configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
vTaskSuspendAll();
{
+ configASSERT( uxSchedulerSuspended == 1U );
+
traceTASK_DELAY();
/* A task that is removed from the event list while the
@@ -1334,12 +2490,14 @@
* have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
{
- portYIELD_WITHIN_API();
+ taskYIELD_WITHIN_API();
}
else
{
mtCOVERAGE_TEST_MARKER();
}
+
+ traceRETURN_vTaskDelay();
}
#endif /* INCLUDE_vTaskDelay */
@@ -1356,14 +2514,18 @@
List_t const * pxOverflowedDelayedList;
const TCB_t * const pxTCB = xTask;
- configASSERT( pxTCB );
+ traceENTER_eTaskGetState( xTask );
- if( pxTCB == pxCurrentTCB )
- {
- /* The task calling this function is querying its own state. */
- eReturn = eRunning;
- }
- else
+ configASSERT( pxTCB != NULL );
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ if( pxTCB == pxCurrentTCB )
+ {
+ /* The task calling this function is querying its own state. */
+ eReturn = eRunning;
+ }
+ else
+ #endif
{
taskENTER_CRITICAL();
{
@@ -1407,7 +2569,7 @@
* suspended. */
eReturn = eSuspended;
- for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+ for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
{
if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
{
@@ -1439,16 +2601,36 @@
}
#endif
- else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+ else
{
- /* If the task is not in any other state, it must be in the
- * Ready (including pending ready) state. */
- eReturn = eReady;
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ /* If the task is not in any other state, it must be in the
+ * Ready (including pending ready) state. */
+ eReturn = eReady;
+ }
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ {
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ /* Is it actively running on a core? */
+ eReturn = eRunning;
+ }
+ else
+ {
+ /* If the task is not in any other state, it must be in the
+ * Ready (including pending ready) state. */
+ eReturn = eReady;
+ }
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
}
+ traceRETURN_eTaskGetState( eReturn );
+
return eReturn;
- } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+ }
#endif /* INCLUDE_eTaskGetState */
/*-----------------------------------------------------------*/
@@ -1460,14 +2642,20 @@
TCB_t const * pxTCB;
UBaseType_t uxReturn;
- taskENTER_CRITICAL();
+ traceENTER_uxTaskPriorityGet( xTask );
+
+ portBASE_TYPE_ENTER_CRITICAL();
{
/* If null is passed in here then it is the priority of the task
* that called uxTaskPriorityGet() that is being queried. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
uxReturn = pxTCB->uxPriority;
}
- taskEXIT_CRITICAL();
+ portBASE_TYPE_EXIT_CRITICAL();
+
+ traceRETURN_uxTaskPriorityGet( uxReturn );
return uxReturn;
}
@@ -1481,7 +2669,9 @@
{
TCB_t const * pxTCB;
UBaseType_t uxReturn;
- UBaseType_t uxSavedInterruptState;
+ UBaseType_t uxSavedInterruptStatus;
+
+ traceENTER_uxTaskPriorityGetFromISR( xTask );
/* RTOS ports that support interrupt nesting have the concept of a
* maximum system call (or maximum API call) interrupt priority.
@@ -1501,14 +2691,21 @@
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
{
/* If null is passed in here then it is the priority of the calling
* task that is being queried. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
uxReturn = pxTCB->uxPriority;
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_uxTaskPriorityGetFromISR( uxReturn );
return uxReturn;
}
@@ -1516,6 +2713,84 @@
#endif /* INCLUDE_uxTaskPriorityGet */
/*-----------------------------------------------------------*/
+#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+ UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask )
+ {
+ TCB_t const * pxTCB;
+ UBaseType_t uxReturn;
+
+ traceENTER_uxTaskBasePriorityGet( xTask );
+
+ portBASE_TYPE_ENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the base priority of the task
+ * that called uxTaskBasePriorityGet() that is being queried. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ uxReturn = pxTCB->uxBasePriority;
+ }
+ portBASE_TYPE_EXIT_CRITICAL();
+
+ traceRETURN_uxTaskBasePriorityGet( uxReturn );
+
+ return uxReturn;
+ }
+
+#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )
+
+ UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask )
+ {
+ TCB_t const * pxTCB;
+ UBaseType_t uxReturn;
+ UBaseType_t uxSavedInterruptStatus;
+
+ traceENTER_uxTaskBasePriorityGetFromISR( xTask );
+
+ /* RTOS ports that support interrupt nesting have the concept of a
+ * maximum system call (or maximum API call) interrupt priority.
+ * Interrupts that are above the maximum system call priority are keep
+ * permanently enabled, even when the RTOS kernel is in a critical section,
+ * but cannot make any calls to FreeRTOS API functions. If configASSERT()
+ * is defined in FreeRTOSConfig.h then
+ * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ * failure if a FreeRTOS API function is called from an interrupt that has
+ * been assigned a priority above the configured maximum system call
+ * priority. Only FreeRTOS functions that end in FromISR can be called
+ * from interrupts that have been assigned a priority at or (logically)
+ * below the maximum system call interrupt priority. FreeRTOS maintains a
+ * separate interrupt safe API to ensure interrupt entry is as fast and as
+ * simple as possible. More information (albeit Cortex-M specific) is
+ * provided on the following link:
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
+ {
+ /* If null is passed in here then it is the base priority of the calling
+ * task that is being queried. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ uxReturn = pxTCB->uxBasePriority;
+ }
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn );
+
+ return uxReturn;
+ }
+
+#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
#if ( INCLUDE_vTaskPrioritySet == 1 )
void vTaskPrioritySet( TaskHandle_t xTask,
@@ -1525,6 +2800,12 @@
UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
BaseType_t xYieldRequired = pdFALSE;
+ #if ( configNUMBER_OF_CORES > 1 )
+ BaseType_t xYieldForTask = pdFALSE;
+ #endif
+
+ traceENTER_vTaskPrioritySet( xTask, uxNewPriority );
+
configASSERT( uxNewPriority < configMAX_PRIORITIES );
/* Ensure the new priority is valid. */
@@ -1542,6 +2823,7 @@
/* If null is passed in here then it is the priority of the calling
* task that is being changed. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
@@ -1558,36 +2840,51 @@
if( uxCurrentBasePriority != uxNewPriority )
{
/* The priority change may have readied a task of higher
- * priority than the calling task. */
+ * priority than a running task. */
if( uxNewPriority > uxCurrentBasePriority )
{
- if( pxTCB != pxCurrentTCB )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- /* The priority of a task other than the currently
- * running task is being raised. Is the priority being
- * raised above that of the running task? */
- if( uxNewPriority > pxCurrentTCB->uxPriority )
+ if( pxTCB != pxCurrentTCB )
{
- xYieldRequired = pdTRUE;
+ /* The priority of a task other than the currently
+ * running task is being raised. Is the priority being
+ * raised above that of the running task? */
+ if( uxNewPriority > pxCurrentTCB->uxPriority )
+ {
+ xYieldRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ /* The priority of the running task is being raised,
+ * but the running task must already be the highest
+ * priority task able to run so no yield is required. */
}
}
- else
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
{
- /* The priority of the running task is being raised,
- * but the running task must already be the highest
- * priority task able to run so no yield is required. */
+ /* The priority of a task is being raised so
+ * perform a yield for this task later. */
+ xYieldForTask = pdTRUE;
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
- else if( pxTCB == pxCurrentTCB )
+ else if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
{
- /* Setting the priority of the running task down means
+ /* Setting the priority of a running task down means
* there may now be another task of higher priority that
* is ready to execute. */
- xYieldRequired = pdTRUE;
+ #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+ if( pxTCB->xPreemptionDisable == pdFALSE )
+ #endif
+ {
+ xYieldRequired = pdTRUE;
+ }
}
else
{
@@ -1604,8 +2901,9 @@
#if ( configUSE_MUTEXES == 1 )
{
/* Only change the priority being used if the task is not
- * currently using an inherited priority. */
- if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+ * currently using an inherited priority or the new priority
+ * is bigger than the inherited priority. */
+ if( ( pxTCB->uxBasePriority == pxTCB->uxPriority ) || ( uxNewPriority > pxTCB->uxPriority ) )
{
pxTCB->uxPriority = uxNewPriority;
}
@@ -1625,9 +2923,9 @@
/* Only reset the event list item value if the value is not
* being used for anything else. */
- if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
{
- listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) );
}
else
{
@@ -1659,16 +2957,40 @@
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ #else
+ {
+ /* It's possible that xYieldForTask was already set to pdTRUE because
+ * its priority is being raised. However, since it is not in a ready list
+ * we don't actually need to yield for it. */
+ xYieldForTask = pdFALSE;
+ }
+ #endif
}
if( xYieldRequired != pdFALSE )
{
- taskYIELD_IF_USING_PREEMPTION();
+ /* The running task priority is set down. Request the task to yield. */
+ taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB );
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ #if ( configNUMBER_OF_CORES > 1 )
+ if( xYieldForTask != pdFALSE )
+ {
+ /* The priority of the task is being raised. If a running
+ * task has priority lower than this task, it should yield
+ * for this task. */
+ taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
+ }
+ else
+ #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
/* Remove compiler warning about unused variables when the port
@@ -1677,22 +2999,165 @@
}
}
taskEXIT_CRITICAL();
+
+ traceRETURN_vTaskPrioritySet();
}
#endif /* INCLUDE_vTaskPrioritySet */
/*-----------------------------------------------------------*/
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ void vTaskCoreAffinitySet( const TaskHandle_t xTask,
+ UBaseType_t uxCoreAffinityMask )
+ {
+ TCB_t * pxTCB;
+ BaseType_t xCoreID;
+
+ traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask );
+
+ taskENTER_CRITICAL();
+ {
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ pxTCB->uxCoreAffinityMask = uxCoreAffinityMask;
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;
+
+ /* If the task can no longer run on the core it was running,
+ * request the core to yield. */
+ if( ( uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) == 0U )
+ {
+ prvYieldCore( xCoreID );
+ }
+ }
+ else
+ {
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ /* The SMP scheduler requests a core to yield when a ready
+ * task is able to run. It is possible that the core affinity
+ * of the ready task is changed before the requested core
+ * can select it to run. In that case, the task may not be
+ * selected by the previously requested core due to core affinity
+ * constraint and the SMP scheduler must select a new core to
+ * yield for the task. */
+ prvYieldForTask( xTask );
+ }
+ #else /* #if( configUSE_PREEMPTION == 1 ) */
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ #endif /* #if( configUSE_PREEMPTION == 1 ) */
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ traceRETURN_vTaskCoreAffinitySet();
+ }
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+ UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask )
+ {
+ const TCB_t * pxTCB;
+ UBaseType_t uxCoreAffinityMask;
+
+ traceENTER_vTaskCoreAffinityGet( xTask );
+
+ portBASE_TYPE_ENTER_CRITICAL();
+ {
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+ }
+ portBASE_TYPE_EXIT_CRITICAL();
+
+ traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask );
+
+ return uxCoreAffinityMask;
+ }
+#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+ void vTaskPreemptionDisable( const TaskHandle_t xTask )
+ {
+ TCB_t * pxTCB;
+
+ traceENTER_vTaskPreemptionDisable( xTask );
+
+ taskENTER_CRITICAL();
+ {
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ pxTCB->xPreemptionDisable = pdTRUE;
+ }
+ taskEXIT_CRITICAL();
+
+ traceRETURN_vTaskPreemptionDisable();
+ }
+
+#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+
+ void vTaskPreemptionEnable( const TaskHandle_t xTask )
+ {
+ TCB_t * pxTCB;
+ BaseType_t xCoreID;
+
+ traceENTER_vTaskPreemptionEnable( xTask );
+
+ taskENTER_CRITICAL();
+ {
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ pxTCB->xPreemptionDisable = pdFALSE;
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;
+ prvYieldCore( xCoreID );
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ traceRETURN_vTaskPreemptionEnable();
+ }
+
+#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
+/*-----------------------------------------------------------*/
+
#if ( INCLUDE_vTaskSuspend == 1 )
void vTaskSuspend( TaskHandle_t xTaskToSuspend )
{
TCB_t * pxTCB;
+ traceENTER_vTaskSuspend( xTaskToSuspend );
+
taskENTER_CRITICAL();
{
/* If null is passed in here then it is the running task that is
* being suspended. */
pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+ configASSERT( pxTCB != NULL );
traceTASK_SUSPEND( pxTCB );
@@ -1723,7 +3188,7 @@
{
BaseType_t x;
- for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+ for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
{
if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
{
@@ -1734,55 +3199,109 @@
}
}
#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
- }
- taskEXIT_CRITICAL();
- if( xSchedulerRunning != pdFALSE )
- {
- /* Reset the next expected unblock time in case it referred to the
- * task that is now in the Suspended state. */
- taskENTER_CRITICAL();
+ /* In the case of SMP, it is possible that the task being suspended
+ * is running on another core. We must evict the task before
+ * exiting the critical section to ensure that the task cannot
+ * take an action which puts it back on ready/state/event list,
+ * thereby nullifying the suspend operation. Once evicted, the
+ * task won't be scheduled before it is resumed as it will no longer
+ * be on the ready list. */
+ #if ( configNUMBER_OF_CORES > 1 )
{
- prvResetNextTaskUnblockTime();
- }
- taskEXIT_CRITICAL();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- if( pxTCB == pxCurrentTCB )
- {
- if( xSchedulerRunning != pdFALSE )
- {
- /* The current task has just been suspended. */
- configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
- portYIELD_WITHIN_API();
- }
- else
- {
- /* The scheduler is not running, but the task that was pointed
- * to by pxCurrentTCB has just been suspended and pxCurrentTCB
- * must be adjusted to point to a different task. */
- if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+ if( xSchedulerRunning != pdFALSE )
{
- /* No other tasks are ready, so set pxCurrentTCB back to
- * NULL so when the next task is created pxCurrentTCB will
- * be set to point to it no matter what its relative priority
- * is. */
- pxCurrentTCB = NULL;
+ /* Reset the next expected unblock time in case it referred to the
+ * task that is now in the Suspended state. */
+ prvResetNextTaskUnblockTime();
+
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
+ {
+ /* The current task has just been suspended. */
+ configASSERT( uxSchedulerSuspended == 0 );
+ vTaskYieldWithinAPI();
+ }
+ else
+ {
+ prvYieldCore( pxTCB->xTaskRunState );
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
else
{
- vTaskSwitchContext();
+ mtCOVERAGE_TEST_MARKER();
}
}
+ #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
}
- else
+ taskEXIT_CRITICAL();
+
+ #if ( configNUMBER_OF_CORES == 1 )
{
- mtCOVERAGE_TEST_MARKER();
+ UBaseType_t uxCurrentListLength;
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* Reset the next expected unblock time in case it referred to the
+ * task that is now in the Suspended state. */
+ taskENTER_CRITICAL();
+ {
+ prvResetNextTaskUnblockTime();
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( pxTCB == pxCurrentTCB )
+ {
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* The current task has just been suspended. */
+ configASSERT( uxSchedulerSuspended == 0 );
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ /* The scheduler is not running, but the task that was pointed
+ * to by pxCurrentTCB has just been suspended and pxCurrentTCB
+ * must be adjusted to point to a different task. */
+
+ /* Use a temp variable as a distinct sequence point for reading
+ * volatile variables prior to a comparison to ensure compliance
+ * with MISRA C 2012 Rule 13.2. */
+ uxCurrentListLength = listCURRENT_LIST_LENGTH( &xSuspendedTaskList );
+
+ if( uxCurrentListLength == uxCurrentNumberOfTasks )
+ {
+ /* No other tasks are ready, so set pxCurrentTCB back to
+ * NULL so when the next task is created pxCurrentTCB will
+ * be set to point to it no matter what its relative priority
+ * is. */
+ pxCurrentTCB = NULL;
+ }
+ else
+ {
+ vTaskSwitchContext();
+ }
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ traceRETURN_vTaskSuspend();
}
#endif /* INCLUDE_vTaskSuspend */
@@ -1808,10 +3327,34 @@
if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
{
/* Is it in the suspended list because it is in the Suspended
- * state, or because is is blocked with no timeout? */
- if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961. The cast is only redundant when NULL is used. */
+ * state, or because it is blocked with no timeout? */
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
{
- xReturn = pdTRUE;
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ {
+ BaseType_t x;
+
+ /* The task does not appear on the event list item of
+ * and of the RTOS objects, but could still be in the
+ * blocked state if it is waiting on its notification
+ * rather than waiting on an object. If not, is
+ * suspended. */
+ xReturn = pdTRUE;
+
+ for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+ {
+ if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+ {
+ xReturn = pdFALSE;
+ break;
+ }
+ }
+ }
+ #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+ {
+ xReturn = pdTRUE;
+ }
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
}
else
{
@@ -1829,7 +3372,7 @@
}
return xReturn;
- } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+ }
#endif /* INCLUDE_vTaskSuspend */
/*-----------------------------------------------------------*/
@@ -1840,12 +3383,25 @@
{
TCB_t * const pxTCB = xTaskToResume;
+ traceENTER_vTaskResume( xTaskToResume );
+
/* It does not make sense to resume the calling task. */
configASSERT( xTaskToResume );
- /* The parameter cannot be NULL as it is impossible to resume the
- * currently executing task. */
- if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+ #if ( configNUMBER_OF_CORES == 1 )
+
+ /* The parameter cannot be NULL as it is impossible to resume the
+ * currently executing task. */
+ if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+ #else
+
+ /* The parameter cannot be NULL as it is impossible to resume the
+ * currently executing task. It is also impossible to resume a task
+ * that is actively running on another core but it is not safe
+ * to check their run state here. Therefore, we get into a critical
+ * section and check if the task is actually suspended or not. */
+ if( pxTCB != NULL )
+ #endif
{
taskENTER_CRITICAL();
{
@@ -1858,18 +3414,10 @@
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
prvAddTaskToReadyList( pxTCB );
- /* A higher priority task may have just been resumed. */
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
- {
- /* This yield may not cause the task just resumed to run,
- * but will leave the lists in the correct state for the
- * next yield. */
- taskYIELD_IF_USING_PREEMPTION();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* This yield may not cause the task just resumed to run,
+ * but will leave the lists in the correct state for the
+ * next yield. */
+ taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
}
else
{
@@ -1882,6 +3430,8 @@
{
mtCOVERAGE_TEST_MARKER();
}
+
+ traceRETURN_vTaskResume();
}
#endif /* INCLUDE_vTaskSuspend */
@@ -1896,6 +3446,8 @@
TCB_t * const pxTCB = xTaskToResume;
UBaseType_t uxSavedInterruptStatus;
+ traceENTER_xTaskResumeFromISR( xTaskToResume );
+
configASSERT( xTaskToResume );
/* RTOS ports that support interrupt nesting have the concept of a
@@ -1916,7 +3468,10 @@
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
{
if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
{
@@ -1925,21 +3480,25 @@
/* Check the ready lists can be accessed. */
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
{
- /* Ready lists can be accessed so move the task from the
- * suspended list to the ready list directly. */
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- xYieldRequired = pdTRUE;
+ /* Ready lists can be accessed so move the task from the
+ * suspended list to the ready list directly. */
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ xYieldRequired = pdTRUE;
- /* Mark that a yield is pending in case the user is not
- * using the return value to initiate a context switch
- * from the ISR using portYIELD_FROM_ISR. */
- xYieldPending = pdTRUE;
+ /* Mark that a yield is pending in case the user is not
+ * using the return value to initiate a context switch
+ * from the ISR using the port specific portYIELD_FROM_ISR(). */
+ xYieldPendings[ 0 ] = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
prvAddTaskToReadyList( pxTCB );
@@ -1951,13 +3510,26 @@
* unsuspended. */
vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
}
+
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) )
+ {
+ prvYieldForTask( pxTCB );
+
+ if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
+ {
+ xYieldRequired = pdTRUE;
+ }
+ }
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) */
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xTaskResumeFromISR( xYieldRequired );
return xYieldRequired;
}
@@ -1965,48 +3537,170 @@
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
+static BaseType_t prvCreateIdleTasks( void )
+{
+ BaseType_t xReturn = pdPASS;
+ BaseType_t xCoreID;
+ char cIdleName[ configMAX_TASK_NAME_LEN ] = { 0 };
+ TaskFunction_t pxIdleTaskFunction = NULL;
+ UBaseType_t xIdleTaskNameIndex;
+
+ /* MISRA Ref 14.3.1 [Configuration dependent invariant] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-143. */
+ /* coverity[misra_c_2012_rule_14_3_violation] */
+ for( xIdleTaskNameIndex = 0U; xIdleTaskNameIndex < ( configMAX_TASK_NAME_LEN - taskRESERVED_TASK_NAME_LENGTH ); xIdleTaskNameIndex++ )
+ {
+ /* MISRA Ref 18.1.1 [Configuration dependent bounds checking] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-181. */
+ /* coverity[misra_c_2012_rule_18_1_violation] */
+ cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ];
+
+ if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 )
+ {
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* Ensure null termination. */
+ cIdleName[ xIdleTaskNameIndex ] = '\0';
+
+ /* Add each idle task at the lowest priority. */
+ for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+ {
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ pxIdleTaskFunction = &prvIdleTask;
+ }
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ {
+ /* In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks
+ * are also created to ensure that each core has an idle task to
+ * run when no other task is available to run. */
+ if( xCoreID == 0 )
+ {
+ pxIdleTaskFunction = &prvIdleTask;
+ }
+ else
+ {
+ pxIdleTaskFunction = &prvPassiveIdleTask;
+ }
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ /* Update the idle task name with suffix to differentiate the idle tasks.
+ * This function is not required in single core FreeRTOS since there is
+ * only one idle task. */
+ #if ( configNUMBER_OF_CORES > 1 )
+ {
+ /* Append the idle task number to the end of the name.
+ *
+ * Note: Idle task name index only supports single-character
+ * core IDs (0-9). If the core ID exceeds 9, the idle task
+ * name will contain an incorrect ASCII character. This is
+ * acceptable as the task name is used mainly for debugging. */
+ cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );
+ cIdleName[ xIdleTaskNameIndex + 1U ] = '\0';
+ }
+ #endif /* if ( configNUMBER_OF_CORES > 1 ) */
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ StaticTask_t * pxIdleTaskTCBBuffer = NULL;
+ StackType_t * pxIdleTaskStackBuffer = NULL;
+ configSTACK_DEPTH_TYPE uxIdleTaskStackSize;
+
+ /* The Idle task is created using user provided RAM - obtain the
+ * address of the RAM then create the idle task. */
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize );
+ }
+ #else
+ {
+ if( xCoreID == 0 )
+ {
+ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize );
+ }
+ else
+ {
+ vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize, ( BaseType_t ) ( xCoreID - 1 ) );
+ }
+ }
+ #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+ xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction,
+ cIdleName,
+ uxIdleTaskStackSize,
+ ( void * ) NULL,
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+ pxIdleTaskStackBuffer,
+ pxIdleTaskTCBBuffer );
+
+ if( xIdleTaskHandles[ xCoreID ] != NULL )
+ {
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ {
+ /* The Idle task is being created using dynamically allocated RAM. */
+ xReturn = xTaskCreate( pxIdleTaskFunction,
+ cIdleName,
+ configMINIMAL_STACK_SIZE,
+ ( void * ) NULL,
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+ &xIdleTaskHandles[ xCoreID ] );
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ /* Break the loop if any of the idle task is failed to be created. */
+ if( xReturn != pdPASS )
+ {
+ break;
+ }
+ else
+ {
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ #else
+ {
+ /* Assign idle task to each core before SMP scheduler is running. */
+ xIdleTaskHandles[ xCoreID ]->xTaskRunState = xCoreID;
+ pxCurrentTCBs[ xCoreID ] = xIdleTaskHandles[ xCoreID ];
+ }
+ #endif
+ }
+ }
+
+ return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
void vTaskStartScheduler( void )
{
BaseType_t xReturn;
- /* Add the idle task at the lowest priority. */
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- StaticTask_t * pxIdleTaskTCBBuffer = NULL;
- StackType_t * pxIdleTaskStackBuffer = NULL;
- uint32_t ulIdleTaskStackSize;
+ traceENTER_vTaskStartScheduler();
- /* The Idle task is created using user provided RAM - obtain the
- * address of the RAM then create the idle task. */
- vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
- xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
- configIDLE_TASK_NAME,
- ulIdleTaskStackSize,
- ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
- portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
- pxIdleTaskStackBuffer,
- pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-
- if( xIdleTaskHandle != NULL )
- {
- xReturn = pdPASS;
- }
- else
- {
- xReturn = pdFAIL;
- }
- }
- #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
{
- /* The Idle task is being created using dynamically allocated RAM. */
- xReturn = xTaskCreate( prvIdleTask,
- configIDLE_TASK_NAME,
- configMINIMAL_STACK_SIZE,
- ( void * ) NULL,
- portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
- &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+ /* Sanity check that the UBaseType_t must have greater than or equal to
+ * the number of bits as confNUMBER_OF_CORES. */
+ configASSERT( ( sizeof( UBaseType_t ) * taskBITS_PER_BYTE ) >= configNUMBER_OF_CORES );
}
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) */
+
+ xReturn = prvCreateIdleTasks();
#if ( configUSE_TIMERS == 1 )
{
@@ -2061,9 +3755,14 @@
traceTASK_SWITCHED_IN();
+ traceSTARTING_SCHEDULER( xIdleTaskHandles );
+
/* Setting up the timer tick is hardware specific and thus in the
* portable interface. */
- xPortStartScheduler();
+
+ /* The return value for xPortStartScheduler is not required
+ * hence using a void datatype. */
+ ( void ) xPortStartScheduler();
/* In most cases, xPortStartScheduler() will not return. If it
* returns pdTRUE then there was not enough heap memory available
@@ -2081,45 +3780,168 @@
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
- * meaning xIdleTaskHandle is not used anywhere else. */
- ( void ) xIdleTaskHandle;
+ * meaning xIdleTaskHandles are not used anywhere else. */
+ ( void ) xIdleTaskHandles;
/* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
* from getting optimized out as it is no longer used by the kernel. */
( void ) uxTopUsedPriority;
+
+ traceRETURN_vTaskStartScheduler();
}
/*-----------------------------------------------------------*/
void vTaskEndScheduler( void )
{
+ traceENTER_vTaskEndScheduler();
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ {
+ BaseType_t xCoreID;
+
+ #if ( configUSE_TIMERS == 1 )
+ {
+ /* Delete the timer task created by the kernel. */
+ vTaskDelete( xTimerGetTimerDaemonTaskHandle() );
+ }
+ #endif /* #if ( configUSE_TIMERS == 1 ) */
+
+ /* Delete Idle tasks created by the kernel.*/
+ for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+ {
+ vTaskDelete( xIdleTaskHandles[ xCoreID ] );
+ }
+
+ /* Idle task is responsible for reclaiming the resources of the tasks in
+ * xTasksWaitingTermination list. Since the idle task is now deleted and
+ * no longer going to run, we need to reclaim resources of all the tasks
+ * in the xTasksWaitingTermination list. */
+ prvCheckTasksWaitingTermination();
+ }
+ #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */
+
/* Stop the scheduler interrupts and call the portable scheduler end
* routine so the original ISRs can be restored if necessary. The port
* layer must ensure interrupts enable bit is left in the correct state. */
portDISABLE_INTERRUPTS();
xSchedulerRunning = pdFALSE;
+
+ /* This function must be called from a task and the application is
+ * responsible for deleting that task after the scheduler is stopped. */
vPortEndScheduler();
+
+ traceRETURN_vTaskEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
- /* A critical section is not required as the variable is of type
- * BaseType_t. Please read Richard Barry's reply in the following link to a
- * post in the FreeRTOS support forum before reporting this as a bug! -
- * https://goo.gl/wu4acr */
+ traceENTER_vTaskSuspendAll();
- /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
- * do not otherwise exhibit real time behaviour. */
- portSOFTWARE_BARRIER();
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ /* A critical section is not required as the variable is of type
+ * BaseType_t. Each task maintains its own context, and a context switch
+ * cannot occur if the variable is non zero. So, as long as the writing
+ * from the register back into the memory is atomic, it is not a
+ * problem.
+ *
+ * Consider the following scenario, which starts with
+ * uxSchedulerSuspended at zero.
+ *
+ * 1. load uxSchedulerSuspended into register.
+ * 2. Now a context switch causes another task to run, and the other
+ * task uses the same variable. The other task will see the variable
+ * as zero because the variable has not yet been updated by the
+ * original task. Eventually the original task runs again. **That can
+ * only happen when uxSchedulerSuspended is once again zero**. When
+ * the original task runs again, the contents of the CPU registers
+ * are restored to exactly how they were when it was switched out -
+ * therefore the value it read into the register still matches the
+ * value of the uxSchedulerSuspended variable.
+ *
+ * 3. increment register.
+ * 4. store register into uxSchedulerSuspended. The value restored to
+ * uxSchedulerSuspended will be the correct value of 1, even though
+ * the variable was used by other tasks in the mean time.
+ */
- /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
- * is used to allow calls to vTaskSuspendAll() to nest. */
- ++uxSchedulerSuspended;
+ /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
+ * do not otherwise exhibit real time behaviour. */
+ portSOFTWARE_BARRIER();
- /* Enforces ordering for ports and optimised compilers that may otherwise place
- * the above increment elsewhere. */
- portMEMORY_BARRIER();
+ /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
+ * is used to allow calls to vTaskSuspendAll() to nest. */
+ uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended + 1U );
+
+ /* Enforces ordering for ports and optimised compilers that may otherwise place
+ * the above increment elsewhere. */
+ portMEMORY_BARRIER();
+ }
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ {
+ UBaseType_t ulState;
+ BaseType_t xCoreID;
+
+ /* This must only be called from within a task. */
+ portASSERT_IF_IN_ISR();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks.
+ * We must disable interrupts before we grab the locks in the event that this task is
+ * interrupted and switches context before incrementing uxSchedulerSuspended.
+ * It is safe to re-enable interrupts after releasing the ISR lock and incrementing
+ * uxSchedulerSuspended since that will prevent context switches. */
+ ulState = portSET_INTERRUPT_MASK();
+
+ xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ /* This must never be called from inside a critical section. */
+ configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 );
+
+ /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
+ * do not otherwise exhibit real time behaviour. */
+ portSOFTWARE_BARRIER();
+
+ portGET_TASK_LOCK( xCoreID );
+
+ /* uxSchedulerSuspended is increased after prvCheckForRunStateChange. The
+ * purpose is to prevent altering the variable when fromISR APIs are readying
+ * it. */
+ if( uxSchedulerSuspended == 0U )
+ {
+ prvCheckForRunStateChange();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Query the coreID again as prvCheckForRunStateChange may have
+ * caused the task to get scheduled on a different core. The correct
+ * task lock for the core is acquired in prvCheckForRunStateChange. */
+ xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ portGET_ISR_LOCK( xCoreID );
+
+ /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
+ * is used to allow calls to vTaskSuspendAll() to nest. */
+ ++uxSchedulerSuspended;
+ portRELEASE_ISR_LOCK( xCoreID );
+
+ portCLEAR_INTERRUPT_MASK( ulState );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ traceRETURN_vTaskSuspendAll();
}
+
/*----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE != 0 )
@@ -2127,9 +3949,9 @@
static TickType_t prvGetExpectedIdleTime( void )
{
TickType_t xReturn;
- UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+ BaseType_t xHigherPriorityReadyTasks = pdFALSE;
- /* uxHigherPriorityReadyTasks takes care of the case where
+ /* xHigherPriorityReadyTasks takes care of the case where
* configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
* task that are in the Ready state, even though the idle task is
* running. */
@@ -2137,7 +3959,7 @@
{
if( uxTopReadyPriority > tskIDLE_PRIORITY )
{
- uxHigherPriorityReadyTasks = pdTRUE;
+ xHigherPriorityReadyTasks = pdTRUE;
}
}
#else
@@ -2151,7 +3973,7 @@
* care of the case where the co-operative scheduler is in use. */
if( uxTopReadyPriority > uxLeastSignificantBit )
{
- uxHigherPriorityReadyTasks = pdTRUE;
+ xHigherPriorityReadyTasks = pdTRUE;
}
}
#endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */
@@ -2160,14 +3982,14 @@
{
xReturn = 0;
}
- else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+ else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1U )
{
/* There are other idle priority tasks in the ready state. If
* time slicing is used then the very next tick interrupt must be
* processed. */
xReturn = 0;
}
- else if( uxHigherPriorityReadyTasks != pdFALSE )
+ else if( xHigherPriorityReadyTasks != pdFALSE )
{
/* There are tasks in the Ready state that have a priority above the
* idle priority. This path can only be reached if
@@ -2176,7 +3998,8 @@
}
else
{
- xReturn = xNextTaskUnblockTime - xTickCount;
+ xReturn = xNextTaskUnblockTime;
+ xReturn -= xTickCount;
}
return xReturn;
@@ -2190,108 +4013,145 @@
TCB_t * pxTCB = NULL;
BaseType_t xAlreadyYielded = pdFALSE;
- /* If uxSchedulerSuspended is zero then this function does not match a
- * previous call to vTaskSuspendAll(). */
- configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
+ traceENTER_xTaskResumeAll();
- /* It is possible that an ISR caused a task to be removed from an event
- * list while the scheduler was suspended. If this was the case then the
- * removed task will have been added to the xPendingReadyList. Once the
- * scheduler has been resumed it is safe to move all the pending ready
- * tasks from this list into their appropriate ready list. */
- taskENTER_CRITICAL();
+ #if ( configNUMBER_OF_CORES > 1 )
+ if( xSchedulerRunning != pdFALSE )
+ #endif
{
- --uxSchedulerSuspended;
-
- if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+ /* It is possible that an ISR caused a task to be removed from an event
+ * list while the scheduler was suspended. If this was the case then the
+ * removed task will have been added to the xPendingReadyList. Once the
+ * scheduler has been resumed it is safe to move all the pending ready
+ * tasks from this list into their appropriate ready list. */
+ taskENTER_CRITICAL();
{
- if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+ const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ /* If uxSchedulerSuspended is zero then this function does not match a
+ * previous call to vTaskSuspendAll(). */
+ configASSERT( uxSchedulerSuspended != 0U );
+
+ uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended - 1U );
+ portRELEASE_TASK_LOCK( xCoreID );
+
+ if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
{
- /* Move any readied tasks from the pending list into the
- * appropriate ready list. */
- while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+ if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
{
- pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
- listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
- portMEMORY_BARRIER();
- listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
- prvAddTaskToReadyList( pxTCB );
-
- /* If the moved task has a priority higher than the current
- * task then a yield must be performed. */
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ /* Move any readied tasks from the pending list into the
+ * appropriate ready list. */
+ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
{
- xYieldPending = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+ listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
+ portMEMORY_BARRIER();
+ listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxTCB );
- if( pxTCB != NULL )
- {
- /* A task was unblocked while the scheduler was suspended,
- * which may have prevented the next unblock time from being
- * re-calculated, in which case re-calculate it now. Mainly
- * important for low power tickless implementations, where
- * this can prevent an unnecessary exit from low power
- * state. */
- prvResetNextTaskUnblockTime();
- }
-
- /* If any ticks occurred while the scheduler was suspended then
- * they should be processed now. This ensures the tick count does
- * not slip, and that any delayed tasks are resumed at the correct
- * time. */
- {
- TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
-
- if( xPendedCounts > ( TickType_t ) 0U )
- {
- do
+ #if ( configNUMBER_OF_CORES == 1 )
{
- if( xTaskIncrementTick() != pdFALSE )
+ /* If the moved task has a priority higher than the current
+ * task then a yield must be performed. */
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
{
- xYieldPending = pdTRUE;
+ xYieldPendings[ xCoreID ] = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
+ }
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ {
+ /* All appropriate tasks yield at the moment a task is added to xPendingReadyList.
+ * If the current core yielded then vTaskSwitchContext() has already been called
+ * which sets xYieldPendings for the current core to pdTRUE. */
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+ }
- --xPendedCounts;
- } while( xPendedCounts > ( TickType_t ) 0U );
+ if( pxTCB != NULL )
+ {
+ /* A task was unblocked while the scheduler was suspended,
+ * which may have prevented the next unblock time from being
+ * re-calculated, in which case re-calculate it now. Mainly
+ * important for low power tickless implementations, where
+ * this can prevent an unnecessary exit from low power
+ * state. */
+ prvResetNextTaskUnblockTime();
+ }
- xPendedTicks = 0;
+ /* If any ticks occurred while the scheduler was suspended then
+ * they should be processed now. This ensures the tick count does
+ * not slip, and that any delayed tasks are resumed at the correct
+ * time.
+ *
+ * It should be safe to call xTaskIncrementTick here from any core
+ * since we are in a critical section and xTaskIncrementTick itself
+ * protects itself within a critical section. Suspending the scheduler
+ * from any core causes xTaskIncrementTick to increment uxPendedCounts. */
+ {
+ TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+ if( xPendedCounts > ( TickType_t ) 0U )
+ {
+ do
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Other cores are interrupted from
+ * within xTaskIncrementTick(). */
+ xYieldPendings[ xCoreID ] = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ --xPendedCounts;
+ } while( xPendedCounts > ( TickType_t ) 0U );
+
+ xPendedTicks = 0;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ if( xYieldPendings[ xCoreID ] != pdFALSE )
+ {
+ #if ( configUSE_PREEMPTION != 0 )
+ {
+ xAlreadyYielded = pdTRUE;
+ }
+ #endif /* #if ( configUSE_PREEMPTION != 0 ) */
+
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxCurrentTCB );
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
-
- if( xYieldPending != pdFALSE )
- {
- #if ( configUSE_PREEMPTION != 0 )
- {
- xAlreadyYielded = pdTRUE;
- }
- #endif
- taskYIELD_IF_USING_PREEMPTION();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
}
}
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ taskEXIT_CRITICAL();
}
- taskEXIT_CRITICAL();
+
+ traceRETURN_xTaskResumeAll( xAlreadyYielded );
return xAlreadyYielded;
}
@@ -2301,6 +4161,8 @@
{
TickType_t xTicks;
+ traceENTER_xTaskGetTickCount();
+
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
@@ -2308,6 +4170,8 @@
}
portTICK_TYPE_EXIT_CRITICAL();
+ traceRETURN_xTaskGetTickCount( xTicks );
+
return xTicks;
}
/*-----------------------------------------------------------*/
@@ -2317,6 +4181,8 @@
TickType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
+ traceENTER_xTaskGetTickCountFromISR();
+
/* RTOS ports that support interrupt nesting have the concept of a maximum
* system call (or maximum API call) interrupt priority. Interrupts that are
* above the maximum system call priority are kept permanently enabled, even
@@ -2339,51 +4205,63 @@
}
portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ traceRETURN_xTaskGetTickCountFromISR( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
UBaseType_t uxTaskGetNumberOfTasks( void )
{
+ traceENTER_uxTaskGetNumberOfTasks();
+
/* A critical section is not required because the variables are of type
* BaseType_t. */
+ traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks );
+
return uxCurrentNumberOfTasks;
}
/*-----------------------------------------------------------*/
-char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+char * pcTaskGetName( TaskHandle_t xTaskToQuery )
{
TCB_t * pxTCB;
+ traceENTER_pcTaskGetName( xTaskToQuery );
+
/* If null is passed in here then the name of the calling task is being
* queried. */
pxTCB = prvGetTCBFromHandle( xTaskToQuery );
- configASSERT( pxTCB );
+ configASSERT( pxTCB != NULL );
+
+ traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) );
+
return &( pxTCB->pcTaskName[ 0 ] );
}
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetHandle == 1 )
-
static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
const char pcNameToQuery[] )
{
- TCB_t * pxNextTCB;
- TCB_t * pxFirstTCB;
TCB_t * pxReturn = NULL;
+ TCB_t * pxTCB = NULL;
UBaseType_t x;
char cNextChar;
BaseType_t xBreakLoop;
+ const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
+ ListItem_t * pxIterator;
/* This function is called with the scheduler suspended. */
if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
{
- listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
- do
+ for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
{
- listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
/* Check each character in the name looking for a match or
* mismatch. */
@@ -2391,7 +4269,7 @@
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
{
- cNextChar = pxNextTCB->pcTaskName[ x ];
+ cNextChar = pxTCB->pcTaskName[ x ];
if( cNextChar != pcNameToQuery[ x ] )
{
@@ -2402,7 +4280,7 @@
{
/* Both strings terminated, a match must have been
* found. */
- pxReturn = pxNextTCB;
+ pxReturn = pxTCB;
xBreakLoop = pdTRUE;
}
else
@@ -2421,7 +4299,7 @@
/* The handle has been found. */
break;
}
- } while( pxNextTCB != pxFirstTCB );
+ }
}
else
{
@@ -2436,11 +4314,13 @@
#if ( INCLUDE_xTaskGetHandle == 1 )
- TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ TaskHandle_t xTaskGetHandle( const char * pcNameToQuery )
{
UBaseType_t uxQueue = configMAX_PRIORITIES;
TCB_t * pxTCB;
+ traceENTER_xTaskGetHandle( pcNameToQuery );
+
/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
@@ -2457,7 +4337,7 @@
/* Found the handle. */
break;
}
- } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );
/* Search the delayed lists. */
if( pxTCB == NULL )
@@ -2492,6 +4372,8 @@
}
( void ) xTaskResumeAll();
+ traceRETURN_xTaskGetHandle( pxTCB );
+
return pxTCB;
}
@@ -2507,16 +4389,22 @@
BaseType_t xReturn;
TCB_t * pxTCB;
+ traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer );
+
configASSERT( ppuxStackBuffer != NULL );
configASSERT( ppxTaskBuffer != NULL );
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 )
{
if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB )
{
*ppuxStackBuffer = pxTCB->pxStack;
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
*ppxTaskBuffer = ( StaticTask_t * ) pxTCB;
xReturn = pdTRUE;
}
@@ -2539,6 +4427,8 @@
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */
+ traceRETURN_xTaskGetStaticBuffers( xReturn );
+
return xReturn;
}
@@ -2553,6 +4443,8 @@
{
UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+ traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+
vTaskSuspendAll();
{
/* Is there a space in the array for each task in the system? */
@@ -2563,19 +4455,19 @@
do
{
uxQueue--;
- uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
- } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ) );
+ } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );
/* Fill in an TaskStatus_t structure with information on each
* task in the Blocked state. */
- uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
- uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+ uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ) );
+ uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ) );
#if ( INCLUDE_vTaskDelete == 1 )
{
/* Fill in an TaskStatus_t structure with information on
* each task that has been deleted but not yet cleaned up. */
- uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+ uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ) );
}
#endif
@@ -2583,7 +4475,7 @@
{
/* Fill in an TaskStatus_t structure with information on
* each task in the Suspended state. */
- uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+ uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ) );
}
#endif
@@ -2614,6 +4506,8 @@
}
( void ) xTaskResumeAll();
+ traceRETURN_uxTaskGetSystemState( uxTask );
+
return uxTask;
}
@@ -2622,12 +4516,35 @@
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
- TaskHandle_t xTaskGetIdleTaskHandle( void )
+ #if ( configNUMBER_OF_CORES == 1 )
+ TaskHandle_t xTaskGetIdleTaskHandle( void )
+ {
+ traceENTER_xTaskGetIdleTaskHandle();
+
+ /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+ * started, then xIdleTaskHandles will be NULL. */
+ configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) );
+
+ traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] );
+
+ return xIdleTaskHandles[ 0 ];
+ }
+ #endif /* if ( configNUMBER_OF_CORES == 1 ) */
+
+ TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID )
{
+ traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID );
+
+ /* Ensure the core ID is valid. */
+ configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE );
+
/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
- * started, then xIdleTaskHandle will be NULL. */
- configASSERT( ( xIdleTaskHandle != NULL ) );
- return xIdleTaskHandle;
+ * started, then xIdleTaskHandles will be NULL. */
+ configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) );
+
+ traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandles[ xCoreID ] );
+
+ return xIdleTaskHandles[ xCoreID ];
}
#endif /* INCLUDE_xTaskGetIdleTaskHandle */
@@ -2641,12 +4558,17 @@
void vTaskStepTick( TickType_t xTicksToJump )
{
+ TickType_t xUpdatedTickCount;
+
+ traceENTER_vTaskStepTick( xTicksToJump );
+
/* Correct the tick count value after a period during which the tick
* was suppressed. Note this does *not* call the tick hook function for
* each stepped tick. */
- configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+ xUpdatedTickCount = xTickCount + xTicksToJump;
+ configASSERT( xUpdatedTickCount <= xNextTaskUnblockTime );
- if( ( xTickCount + xTicksToJump ) == xNextTaskUnblockTime )
+ if( xUpdatedTickCount == xNextTaskUnblockTime )
{
/* Arrange for xTickCount to reach xNextTaskUnblockTime in
* xTaskIncrementTick() when the scheduler resumes. This ensures
@@ -2668,7 +4590,9 @@
}
xTickCount += xTicksToJump;
+
traceINCREASE_TICK_COUNT( xTicksToJump );
+ traceRETURN_vTaskStepTick();
}
#endif /* configUSE_TICKLESS_IDLE */
@@ -2678,6 +4602,8 @@
{
BaseType_t xYieldOccurred;
+ traceENTER_xTaskCatchUpTicks( xTicksToCatchUp );
+
/* Must not be called with the scheduler suspended as the implementation
* relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
@@ -2694,6 +4620,8 @@
taskEXIT_CRITICAL();
xYieldOccurred = xTaskResumeAll();
+ traceRETURN_xTaskCatchUpTicks( xYieldOccurred );
+
return xYieldOccurred;
}
/*----------------------------------------------------------*/
@@ -2705,7 +4633,9 @@
TCB_t * pxTCB = xTask;
BaseType_t xReturn;
- configASSERT( pxTCB );
+ traceENTER_xTaskAbortDelay( xTask );
+
+ configASSERT( pxTCB != NULL );
vTaskSuspendAll();
{
@@ -2733,7 +4663,7 @@
/* This lets the task know it was forcibly removed from the
* blocked state so it should not re-evaluate its block time and
* then block again. */
- pxTCB->ucDelayAborted = pdTRUE;
+ pxTCB->ucDelayAborted = ( uint8_t ) pdTRUE;
}
else
{
@@ -2749,21 +4679,33 @@
* switch if preemption is turned off. */
#if ( configUSE_PREEMPTION == 1 )
{
- /* Preemption is on, but a context switch should only be
- * performed if the unblocked task has a priority that is
- * higher than the currently executing task. */
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- /* Pend the yield to be performed when the scheduler
- * is unsuspended. */
- xYieldPending = pdTRUE;
+ /* Preemption is on, but a context switch should only be
+ * performed if the unblocked task has a priority that is
+ * higher than the currently executing task. */
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* Pend the yield to be performed when the scheduler
+ * is unsuspended. */
+ xYieldPendings[ 0 ] = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
{
- mtCOVERAGE_TEST_MARKER();
+ taskENTER_CRITICAL();
+ {
+ prvYieldForTask( pxTCB );
+ }
+ taskEXIT_CRITICAL();
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
- #endif /* configUSE_PREEMPTION */
+ #endif /* #if ( configUSE_PREEMPTION == 1 ) */
}
else
{
@@ -2772,6 +4714,8 @@
}
( void ) xTaskResumeAll();
+ traceRETURN_xTaskAbortDelay( xReturn );
+
return xReturn;
}
@@ -2784,11 +4728,17 @@
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
+ traceENTER_xTaskIncrementTick();
+
/* Called by the portable layer each time a tick interrupt occurs.
* Increments the tick then checks to see if the new tick value will cause any
* tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
+ /* Tick increment should occur on every kernel timer event. Core 0 has the
+ * responsibility to increment the tick, or increment the pended ticks if the
+ * scheduler is suspended. If pended ticks is greater than zero, the core that
+ * calls xTaskResumeAll has the responsibility to increment the tick. */
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
{
/* Minor optimisation. The tick count cannot change in this
@@ -2799,7 +4749,7 @@
* delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
- if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+ if( xConstTickCount == ( TickType_t ) 0U )
{
taskSWITCH_DELAYED_LISTS();
}
@@ -2823,7 +4773,7 @@
* unlikely that the
* if( xTickCount >= xNextTaskUnblockTime ) test will pass
* next time through. */
- xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ xNextTaskUnblockTime = portMAX_DELAY;
break;
}
else
@@ -2832,7 +4782,10 @@
* item at the head of the delayed list. This is the time
* at which the task at the head of the delayed list must
* be removed from the Blocked state. */
- pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
if( xConstTickCount < xItemValue )
@@ -2843,7 +4796,7 @@
* state - so record the item value in
* xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
- break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */
+ break;
}
else
{
@@ -2872,24 +4825,32 @@
* context switch if preemption is turned off. */
#if ( configUSE_PREEMPTION == 1 )
{
- /* Preemption is on, but a context switch should
- * only be performed if the unblocked task's
- * priority is higher than the currently executing
- * task.
- * The case of equal priority tasks sharing
- * processing time (which happens when both
- * preemption and time slicing are on) is
- * handled below.*/
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- xSwitchRequired = pdTRUE;
+ /* Preemption is on, but a context switch should
+ * only be performed if the unblocked task's
+ * priority is higher than the currently executing
+ * task.
+ * The case of equal priority tasks sharing
+ * processing time (which happens when both
+ * preemption and time slicing are on) is
+ * handled below.*/
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
+ #else /* #if( configNUMBER_OF_CORES == 1 ) */
{
- mtCOVERAGE_TEST_MARKER();
+ prvYieldForTask( pxTCB );
}
+ #endif /* #if( configNUMBER_OF_CORES == 1 ) */
}
- #endif /* configUSE_PREEMPTION */
+ #endif /* #if ( configUSE_PREEMPTION == 1 ) */
}
}
}
@@ -2899,16 +4860,36 @@
* writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
- if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- xSwitchRequired = pdTRUE;
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > 1U )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
{
- mtCOVERAGE_TEST_MARKER();
+ BaseType_t xCoreID;
+
+ for( xCoreID = 0; xCoreID < ( ( BaseType_t ) configNUMBER_OF_CORES ); xCoreID++ )
+ {
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1U )
+ {
+ xYieldPendings[ xCoreID ] = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
- #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+ #endif /* #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
#if ( configUSE_TICK_HOOK == 1 )
{
@@ -2927,20 +4908,54 @@
#if ( configUSE_PREEMPTION == 1 )
{
- if( xYieldPending != pdFALSE )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- xSwitchRequired = pdTRUE;
+ /* For single core the core ID is always 0. */
+ if( xYieldPendings[ 0 ] != pdFALSE )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
{
- mtCOVERAGE_TEST_MARKER();
+ BaseType_t xCoreID, xCurrentCoreID;
+ xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
+ {
+ #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
+ if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
+ #endif
+ {
+ if( xYieldPendings[ xCoreID ] != pdFALSE )
+ {
+ if( xCoreID == xCurrentCoreID )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ prvYieldCore( xCoreID );
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
- #endif /* configUSE_PREEMPTION */
+ #endif /* #if ( configUSE_PREEMPTION == 1 ) */
}
else
{
- ++xPendedTicks;
+ xPendedTicks += 1U;
/* The tick hook gets called at regular intervals, even if the
* scheduler is locked. */
@@ -2951,6 +4966,8 @@
#endif
}
+ traceRETURN_xTaskIncrementTick( xSwitchRequired );
+
return xSwitchRequired;
}
/*-----------------------------------------------------------*/
@@ -2962,6 +4979,8 @@
{
TCB_t * xTCB;
+ traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction );
+
/* If xTask is NULL then it is the task hook of the calling task that is
* getting set. */
if( xTask == NULL )
@@ -2980,6 +4999,8 @@
xTCB->pxTaskTag = pxHookFunction;
}
taskEXIT_CRITICAL();
+
+ traceRETURN_vTaskSetApplicationTaskTag();
}
#endif /* configUSE_APPLICATION_TASK_TAG */
@@ -2992,8 +5013,11 @@
TCB_t * pxTCB;
TaskHookFunction_t xReturn;
+ traceENTER_xTaskGetApplicationTaskTag( xTask );
+
/* If xTask is NULL then set the calling task's hook. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
/* Save the hook function in the TCB. A critical section is required as
* the value can be accessed from an interrupt. */
@@ -3003,6 +5027,8 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_xTaskGetApplicationTaskTag( xReturn );
+
return xReturn;
}
@@ -3017,16 +5043,24 @@
TaskHookFunction_t xReturn;
UBaseType_t uxSavedInterruptStatus;
+ traceENTER_xTaskGetApplicationTaskTagFromISR( xTask );
+
/* If xTask is NULL then set the calling task's hook. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
/* Save the hook function in the TCB. A critical section is required as
* the value can be accessed from an interrupt. */
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
{
xReturn = pxTCB->pxTaskTag;
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn );
return xReturn;
}
@@ -3042,6 +5076,8 @@
TCB_t * xTCB;
BaseType_t xReturn;
+ traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter );
+
/* If xTask is NULL then we are calling our own task hook. */
if( xTask == NULL )
{
@@ -3061,92 +5097,210 @@
xReturn = pdFAIL;
}
+ traceRETURN_xTaskCallApplicationTaskHook( xReturn );
+
return xReturn;
}
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
-void vTaskSwitchContext( void )
-{
- if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
+#if ( configNUMBER_OF_CORES == 1 )
+ void vTaskSwitchContext( void )
{
- /* The scheduler is currently suspended - do not allow a context
- * switch. */
- xYieldPending = pdTRUE;
- }
- else
- {
- xYieldPending = pdFALSE;
- traceTASK_SWITCHED_OUT();
+ traceENTER_vTaskSwitchContext();
- #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
{
- #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
- portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
- #else
- ulTotalRunTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+ /* The scheduler is currently suspended - do not allow a context
+ * switch. */
+ xYieldPendings[ 0 ] = pdTRUE;
+ }
+ else
+ {
+ xYieldPendings[ 0 ] = pdFALSE;
+ traceTASK_SWITCHED_OUT();
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ 0 ] );
+ #else
+ ulTotalRunTime[ 0 ] = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ /* Add the amount of time the task has been running to the
+ * accumulated time so far. The time the task started running was
+ * stored in ulTaskSwitchedInTime. Note that there is no overflow
+ * protection here so count values are only valid until the timer
+ * overflows. The guard against negative values is to protect
+ * against suspect run time stat counter implementations - which
+ * are provided by the application, not the kernel. */
+ if( ulTotalRunTime[ 0 ] > ulTaskSwitchedInTime[ 0 ] )
+ {
+ pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ 0 ] - ulTaskSwitchedInTime[ 0 ] );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ ulTaskSwitchedInTime[ 0 ] = ulTotalRunTime[ 0 ];
+ }
+ #endif /* configGENERATE_RUN_TIME_STATS */
+
+ /* Check for stack overflow, if configured. */
+ taskCHECK_FOR_STACK_OVERFLOW();
+
+ /* Before the currently running task is switched out, save its errno. */
+ #if ( configUSE_POSIX_ERRNO == 1 )
+ {
+ pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+ }
#endif
- /* Add the amount of time the task has been running to the
- * accumulated time so far. The time the task started running was
- * stored in ulTaskSwitchedInTime. Note that there is no overflow
- * protection here so count values are only valid until the timer
- * overflows. The guard against negative values is to protect
- * against suspect run time stat counter implementations - which
- * are provided by the application, not the kernel. */
- if( ulTotalRunTime > ulTaskSwitchedInTime )
+ /* Select a new task to run using either the generic C or port
+ * optimised asm code. */
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ taskSELECT_HIGHEST_PRIORITY_TASK();
+ traceTASK_SWITCHED_IN();
+
+ /* Macro to inject port specific behaviour immediately after
+ * switching tasks, such as setting an end of stack watchpoint
+ * or reconfiguring the MPU. */
+ portTASK_SWITCH_HOOK( pxCurrentTCB );
+
+ /* After the new task is switched in, update the global errno. */
+ #if ( configUSE_POSIX_ERRNO == 1 )
{
- pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+ FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+ }
+ #endif
+
+ #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+ {
+ /* Switch C-Runtime's TLS Block to point to the TLS
+ * Block specific to this task. */
+ configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+ }
+ #endif
+ }
+
+ traceRETURN_vTaskSwitchContext();
+ }
+#else /* if ( configNUMBER_OF_CORES == 1 ) */
+ void vTaskSwitchContext( BaseType_t xCoreID )
+ {
+ traceENTER_vTaskSwitchContext();
+
+ /* Acquire both locks:
+ * - The ISR lock protects the ready list from simultaneous access by
+ * both other ISRs and tasks.
+ * - We also take the task lock to pause here in case another core has
+ * suspended the scheduler. We don't want to simply set xYieldPending
+ * and move on if another core suspended the scheduler. We should only
+ * do that if the current core has suspended the scheduler. */
+
+ portGET_TASK_LOCK( xCoreID ); /* Must always acquire the task lock first. */
+ portGET_ISR_LOCK( xCoreID );
+ {
+ /* vTaskSwitchContext() must never be called from within a critical section.
+ * This is not necessarily true for single core FreeRTOS, but it is for this
+ * SMP port. */
+ configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 );
+
+ if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
+ {
+ /* The scheduler is currently suspended - do not allow a context
+ * switch. */
+ xYieldPendings[ xCoreID ] = pdTRUE;
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ xYieldPendings[ xCoreID ] = pdFALSE;
+ traceTASK_SWITCHED_OUT();
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ xCoreID ] );
+ #else
+ ulTotalRunTime[ xCoreID ] = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ /* Add the amount of time the task has been running to the
+ * accumulated time so far. The time the task started running was
+ * stored in ulTaskSwitchedInTime. Note that there is no overflow
+ * protection here so count values are only valid until the timer
+ * overflows. The guard against negative values is to protect
+ * against suspect run time stat counter implementations - which
+ * are provided by the application, not the kernel. */
+ if( ulTotalRunTime[ xCoreID ] > ulTaskSwitchedInTime[ xCoreID ] )
+ {
+ pxCurrentTCBs[ xCoreID ]->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ ulTaskSwitchedInTime[ xCoreID ] = ulTotalRunTime[ xCoreID ];
+ }
+ #endif /* configGENERATE_RUN_TIME_STATS */
+
+ /* Check for stack overflow, if configured. */
+ taskCHECK_FOR_STACK_OVERFLOW();
+
+ /* Before the currently running task is switched out, save its errno. */
+ #if ( configUSE_POSIX_ERRNO == 1 )
+ {
+ pxCurrentTCBs[ xCoreID ]->iTaskErrno = FreeRTOS_errno;
+ }
+ #endif
+
+ /* Select a new task to run. */
+ taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID );
+ traceTASK_SWITCHED_IN();
+
+ /* Macro to inject port specific behaviour immediately after
+ * switching tasks, such as setting an end of stack watchpoint
+ * or reconfiguring the MPU. */
+ portTASK_SWITCH_HOOK( pxCurrentTCBs[ portGET_CORE_ID() ] );
+
+ /* After the new task is switched in, update the global errno. */
+ #if ( configUSE_POSIX_ERRNO == 1 )
+ {
+ FreeRTOS_errno = pxCurrentTCBs[ xCoreID ]->iTaskErrno;
+ }
+ #endif
+
+ #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
+ {
+ /* Switch C-Runtime's TLS Block to point to the TLS
+ * Block specific to this task. */
+ configSET_TLS_BLOCK( pxCurrentTCBs[ xCoreID ]->xTLSBlock );
+ }
+ #endif
}
-
- ulTaskSwitchedInTime = ulTotalRunTime;
}
- #endif /* configGENERATE_RUN_TIME_STATS */
+ portRELEASE_ISR_LOCK( xCoreID );
+ portRELEASE_TASK_LOCK( xCoreID );
- /* Check for stack overflow, if configured. */
- taskCHECK_FOR_STACK_OVERFLOW();
-
- /* Before the currently running task is switched out, save its errno. */
- #if ( configUSE_POSIX_ERRNO == 1 )
- {
- pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
- }
- #endif
-
- /* Select a new task to run using either the generic C or port
- * optimised asm code. */
- taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
- traceTASK_SWITCHED_IN();
-
- /* After the new task is switched in, update the global errno. */
- #if ( configUSE_POSIX_ERRNO == 1 )
- {
- FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
- }
- #endif
-
- #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
- {
- /* Switch C-Runtime's TLS Block to point to the TLS
- * Block specific to this task. */
- configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
- }
- #endif
+ traceRETURN_vTaskSwitchContext();
}
-}
+#endif /* if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList,
const TickType_t xTicksToWait )
{
+ traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait );
+
configASSERT( pxEventList );
- /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+ /* THIS FUNCTION MUST BE CALLED WITH THE
* SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
/* Place the event list item of the TCB in the appropriate event list.
@@ -3163,6 +5317,8 @@
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+
+ traceRETURN_vTaskPlaceOnEventList();
}
/*-----------------------------------------------------------*/
@@ -3170,6 +5326,8 @@
const TickType_t xItemValue,
const TickType_t xTicksToWait )
{
+ traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait );
+
configASSERT( pxEventList );
/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
@@ -3189,6 +5347,8 @@
listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+
+ traceRETURN_vTaskPlaceOnUnorderedEventList();
}
/*-----------------------------------------------------------*/
@@ -3198,6 +5358,8 @@
TickType_t xTicksToWait,
const BaseType_t xWaitIndefinitely )
{
+ traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely );
+
configASSERT( pxEventList );
/* This function should not be called by application code hence the
@@ -3222,6 +5384,8 @@
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+
+ traceRETURN_vTaskPlaceOnEventListRestricted();
}
#endif /* configUSE_TIMERS */
@@ -3232,6 +5396,8 @@
TCB_t * pxUnblockedTCB;
BaseType_t xReturn;
+ traceENTER_xTaskRemoveFromEventList( pxEventList );
+
/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be
* called from a critical section within an ISR. */
@@ -3245,7 +5411,10 @@
*
* This function assumes that a check has already been made to ensure that
* pxEventList is not empty. */
- pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
configASSERT( pxUnblockedTCB );
listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) );
@@ -3275,22 +5444,42 @@
listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
}
- if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- /* Return true if the task removed from the event list has a higher
- * priority than the calling task. This allows the calling task to know if
- * it should force a context switch now. */
- xReturn = pdTRUE;
+ if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* Return true if the task removed from the event list has a higher
+ * priority than the calling task. This allows the calling task to know if
+ * it should force a context switch now. */
+ xReturn = pdTRUE;
- /* Mark that a yield is pending in case the user is not using the
- * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
- xYieldPending = pdTRUE;
+ /* Mark that a yield is pending in case the user is not using the
+ * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+ xYieldPendings[ 0 ] = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
}
- else
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
{
xReturn = pdFALSE;
- }
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ prvYieldForTask( pxUnblockedTCB );
+
+ if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
+ {
+ xReturn = pdTRUE;
+ }
+ }
+ #endif /* #if ( configUSE_PREEMPTION == 1 ) */
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ traceRETURN_xTaskRemoveFromEventList( xReturn );
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -3300,6 +5489,8 @@
{
TCB_t * pxUnblockedTCB;
+ traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue );
+
/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
* the event flags implementation. */
configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
@@ -3309,7 +5500,10 @@
/* Remove the event list form the event flag. Interrupts do not access
* event flags. */
- pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem );
configASSERT( pxUnblockedTCB );
listREMOVE_ITEM( pxEventListItem );
@@ -3333,19 +5527,39 @@
listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
prvAddTaskToReadyList( pxUnblockedTCB );
- if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- /* The unblocked task has a priority above that of the calling task, so
- * a context switch is required. This function is called with the
- * scheduler suspended so xYieldPending is set so the context switch
- * occurs immediately that the scheduler is resumed (unsuspended). */
- xYieldPending = pdTRUE;
+ if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* The unblocked task has a priority above that of the calling task, so
+ * a context switch is required. This function is called with the
+ * scheduler suspended so xYieldPending is set so the context switch
+ * occurs immediately that the scheduler is resumed (unsuspended). */
+ xYieldPendings[ 0 ] = pdTRUE;
+ }
}
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ {
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ taskENTER_CRITICAL();
+ {
+ prvYieldForTask( pxUnblockedTCB );
+ }
+ taskEXIT_CRITICAL();
+ }
+ #endif
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ traceRETURN_vTaskRemoveFromUnorderedEventList();
}
/*-----------------------------------------------------------*/
void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
{
+ traceENTER_vTaskSetTimeOutState( pxTimeOut );
+
configASSERT( pxTimeOut );
taskENTER_CRITICAL();
{
@@ -3353,14 +5567,20 @@
pxTimeOut->xTimeOnEntering = xTickCount;
}
taskEXIT_CRITICAL();
+
+ traceRETURN_vTaskSetTimeOutState();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
+ traceENTER_vTaskInternalSetTimeOutState( pxTimeOut );
+
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
pxTimeOut->xTimeOnEntering = xTickCount;
+
+ traceRETURN_vTaskInternalSetTimeOutState();
}
/*-----------------------------------------------------------*/
@@ -3369,6 +5589,8 @@
{
BaseType_t xReturn;
+ traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+
configASSERT( pxTimeOut );
configASSERT( pxTicksToWait );
@@ -3383,7 +5605,7 @@
{
/* The delay was aborted, which is not the same as a time out,
* but has the same result. */
- pxCurrentTCB->ucDelayAborted = pdFALSE;
+ pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE;
xReturn = pdTRUE;
}
else
@@ -3400,7 +5622,7 @@
else
#endif
- if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+ if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) )
{
/* The tick count is greater than the time at which
* vTaskSetTimeout() was called, but has also overflowed since
@@ -3410,7 +5632,7 @@
xReturn = pdTRUE;
*pxTicksToWait = ( TickType_t ) 0;
}
- else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+ else if( xElapsedTime < *pxTicksToWait )
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
@@ -3425,13 +5647,20 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_xTaskCheckForTimeOut( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
- xYieldPending = pdTRUE;
+ traceENTER_vTaskMissedYield();
+
+ /* Must be called from within a critical section. */
+ xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
+
+ traceRETURN_vTaskMissedYield();
}
/*-----------------------------------------------------------*/
@@ -3442,6 +5671,8 @@
UBaseType_t uxReturn;
TCB_t const * pxTCB;
+ traceENTER_uxTaskGetTaskNumber( xTask );
+
if( xTask != NULL )
{
pxTCB = xTask;
@@ -3452,6 +5683,8 @@
uxReturn = 0U;
}
+ traceRETURN_uxTaskGetTaskNumber( uxReturn );
+
return uxReturn;
}
@@ -3465,18 +5698,97 @@
{
TCB_t * pxTCB;
+ traceENTER_vTaskSetTaskNumber( xTask, uxHandle );
+
if( xTask != NULL )
{
pxTCB = xTask;
pxTCB->uxTaskNumber = uxHandle;
}
+
+ traceRETURN_vTaskSetTaskNumber();
}
#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
/*
* -----------------------------------------------------------
- * The Idle task.
+ * The passive idle task.
+ * ----------------------------------------------------------
+ *
+ * The passive idle task is used for all the additional cores in a SMP
+ * system. There must be only 1 active idle task and the rest are passive
+ * idle tasks.
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions. The equivalent prototype for this function is:
+ *
+ * void prvPassiveIdleTask( void *pvParameters );
+ */
+
+#if ( configNUMBER_OF_CORES > 1 )
+ static portTASK_FUNCTION( prvPassiveIdleTask, pvParameters )
+ {
+ ( void ) pvParameters;
+
+ taskYIELD();
+
+ for( ; configCONTROL_INFINITE_LOOP(); )
+ {
+ #if ( configUSE_PREEMPTION == 0 )
+ {
+ /* If we are not using preemption we keep forcing a task switch to
+ * see if any other task has become available. If we are using
+ * preemption we don't need to do this as any task becoming available
+ * will automatically get the processor anyway. */
+ taskYIELD();
+ }
+ #endif /* configUSE_PREEMPTION */
+
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+ {
+ /* When using preemption tasks of equal priority will be
+ * timesliced. If a task that is sharing the idle priority is ready
+ * to run then the idle task should yield before the end of the
+ * timeslice.
+ *
+ * A critical region is not required here as we are just reading from
+ * the list, and an occasional incorrect value will not matter. If
+ * the ready list at the idle priority contains one more task than the
+ * number of idle tasks, which is equal to the configured numbers of cores
+ * then a task other than the idle task is ready to execute. */
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
+ {
+ taskYIELD();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+ #if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
+ {
+ /* Call the user defined function from within the idle task. This
+ * allows the application designer to add background functionality
+ * without the overhead of a separate task.
+ *
+ * This hook is intended to manage core activity such as disabling cores that go idle.
+ *
+ * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+ * CALL A FUNCTION THAT MIGHT BLOCK. */
+ vApplicationPassiveIdleHook();
+ }
+ #endif /* configUSE_PASSIVE_IDLE_HOOK */
+ }
+ }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*
+ * -----------------------------------------------------------
+ * The idle task.
* ----------------------------------------------------------
*
* The portTASK_FUNCTION() macro is used to allow port/compiler specific
@@ -3499,7 +5811,15 @@
* any. */
portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
- for( ; ; )
+ #if ( configNUMBER_OF_CORES > 1 )
+ {
+ /* SMP all cores start up in the idle task. This initial yield gets the application
+ * tasks started. */
+ taskYIELD();
+ }
+ #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+ for( ; configCONTROL_INFINITE_LOOP(); )
{
/* See if any tasks have deleted themselves - if so then the idle task
* is responsible for freeing the deleted task's TCB and stack. */
@@ -3524,9 +5844,10 @@
*
* A critical region is not required here as we are just reading from
* the list, and an occasional incorrect value will not matter. If
- * the ready list at the idle priority contains more than one task
+ * the ready list at the idle priority contains one more task than the
+ * number of idle tasks, which is equal to the configured numbers of cores
* then a task other than the idle task is ready to execute. */
- if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
{
taskYIELD();
}
@@ -3559,7 +5880,7 @@
* valid. */
xExpectedIdleTime = prvGetExpectedIdleTime();
- if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
{
vTaskSuspendAll();
{
@@ -3574,7 +5895,7 @@
* portSUPPRESS_TICKS_AND_SLEEP() to be called. */
configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
- if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
{
traceLOW_POWER_IDLE_BEGIN();
portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
@@ -3593,6 +5914,20 @@
}
}
#endif /* configUSE_TICKLESS_IDLE */
+
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) )
+ {
+ /* Call the user defined function from within the idle task. This
+ * allows the application designer to add background functionality
+ * without the overhead of a separate task.
+ *
+ * This hook is intended to manage core activity such as disabling cores that go idle.
+ *
+ * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+ * CALL A FUNCTION THAT MIGHT BLOCK. */
+ vApplicationPassiveIdleHook();
+ }
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) */
}
}
/*-----------------------------------------------------------*/
@@ -3603,24 +5938,26 @@
{
#if ( INCLUDE_vTaskSuspend == 1 )
/* The idle task exists in addition to the application tasks. */
- const UBaseType_t uxNonApplicationTasks = 1;
+ const UBaseType_t uxNonApplicationTasks = configNUMBER_OF_CORES;
#endif /* INCLUDE_vTaskSuspend */
eSleepModeStatus eReturn = eStandardSleep;
+ traceENTER_eTaskConfirmSleepModeStatus();
+
/* This function must be called from a critical section. */
- if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+ if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0U )
{
/* A task was made ready while the scheduler was suspended. */
eReturn = eAbortSleep;
}
- else if( xYieldPending != pdFALSE )
+ else if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
{
/* A yield was pended while the scheduler was suspended. */
eReturn = eAbortSleep;
}
- else if( xPendedTicks != 0 )
+ else if( xPendedTicks != 0U )
{
/* A tick interrupt has already occurred but was held pending
* because the scheduler is suspended. */
@@ -3642,6 +5979,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_eTaskConfirmSleepModeStatus( eReturn );
+
return eReturn;
}
@@ -3656,13 +5995,17 @@
{
TCB_t * pxTCB;
+ traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
+
if( ( xIndex >= 0 ) &&
- ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
+ ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
{
pxTCB = prvGetTCBFromHandle( xTaskToSet );
configASSERT( pxTCB != NULL );
pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
}
+
+ traceRETURN_vTaskSetThreadLocalStoragePointer();
}
#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
@@ -3676,10 +6019,14 @@
void * pvReturn = NULL;
TCB_t * pxTCB;
+ traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
+
if( ( xIndex >= 0 ) &&
- ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
+ ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
{
pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+ configASSERT( pxTCB != NULL );
+
pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
}
else
@@ -3687,6 +6034,8 @@
pvReturn = NULL;
}
+ traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn );
+
return pvReturn;
}
@@ -3696,15 +6045,20 @@
#if ( portUSING_MPU_WRAPPERS == 1 )
void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
- const MemoryRegion_t * const xRegions )
+ const MemoryRegion_t * const pxRegions )
{
TCB_t * pxTCB;
+ traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions );
+
/* If null is passed in here then we are modifying the MPU settings of
* the calling task. */
pxTCB = prvGetTCBFromHandle( xTaskToModify );
+ configASSERT( pxTCB != NULL );
- vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 );
+
+ traceRETURN_vTaskAllocateMPURegions();
}
#endif /* portUSING_MPU_WRAPPERS */
@@ -3754,16 +6108,64 @@
* being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
{
- taskENTER_CRITICAL();
+ #if ( configNUMBER_OF_CORES == 1 )
{
- pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
- ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
- --uxCurrentNumberOfTasks;
- --uxDeletedTasksWaitingCleanUp;
- }
- taskEXIT_CRITICAL();
+ taskENTER_CRITICAL();
+ {
+ {
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ --uxCurrentNumberOfTasks;
+ --uxDeletedTasksWaitingCleanUp;
+ }
+ }
+ taskEXIT_CRITICAL();
- prvDeleteTCB( pxTCB );
+ prvDeleteTCB( pxTCB );
+ }
+ #else /* #if( configNUMBER_OF_CORES == 1 ) */
+ {
+ pxTCB = NULL;
+
+ taskENTER_CRITICAL();
+ {
+ /* For SMP, multiple idles can be running simultaneously
+ * and we need to check that other idles did not cleanup while we were
+ * waiting to enter the critical section. */
+ if( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+ {
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+
+ if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
+ {
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ --uxCurrentNumberOfTasks;
+ --uxDeletedTasksWaitingCleanUp;
+ }
+ else
+ {
+ /* The TCB to be deleted still has not yet been switched out
+ * by the scheduler, so we will just exit this loop early and
+ * try again next time. */
+ taskEXIT_CRITICAL();
+ break;
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ if( pxTCB != NULL )
+ {
+ prvDeleteTCB( pxTCB );
+ }
+ }
+ #endif /* #if( configNUMBER_OF_CORES == 1 ) */
}
}
#endif /* INCLUDE_vTaskDelete */
@@ -3779,19 +6181,28 @@
{
TCB_t * pxTCB;
+ traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
+
/* xTask is NULL then get the state of the calling task. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
- pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+ pxTaskStatus->xHandle = pxTCB;
pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
pxTaskStatus->pxStackBase = pxTCB->pxStack;
- #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
- pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack;
+ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+ pxTaskStatus->pxTopOfStack = ( StackType_t * ) pxTCB->pxTopOfStack;
pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack;
#endif
pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+ #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+ {
+ pxTaskStatus->uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
+ }
+ #endif
+
#if ( configUSE_MUTEXES == 1 )
{
pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
@@ -3804,7 +6215,7 @@
#if ( configGENERATE_RUN_TIME_STATS == 1 )
{
- pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+ pxTaskStatus->ulRunTimeCounter = ulTaskGetRunTimeCounter( xTask );
}
#else
{
@@ -3817,7 +6228,7 @@
* state is just set to whatever is passed in. */
if( eState != eInvalid )
{
- if( pxTCB == pxCurrentTCB )
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
{
pxTaskStatus->eCurrentState = eRunning;
}
@@ -3838,6 +6249,28 @@
{
pxTaskStatus->eCurrentState = eBlocked;
}
+ else
+ {
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ {
+ BaseType_t x;
+
+ /* The task does not appear on the event list item of
+ * and of the RTOS objects, but could still be in the
+ * blocked state if it is waiting on its notification
+ * rather than waiting on an object. If not, is
+ * suspended. */
+ for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+ {
+ if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+ {
+ pxTaskStatus->eCurrentState = eBlocked;
+ break;
+ }
+ }
+ }
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+ }
}
( void ) xTaskResumeAll();
}
@@ -3880,6 +6313,8 @@
{
pxTaskStatus->usStackHighWaterMark = 0;
}
+
+ traceRETURN_vTaskGetInfo();
}
#endif /* configUSE_TRACE_FACILITY */
@@ -3891,24 +6326,27 @@
List_t * pxList,
eTaskState eState )
{
- configLIST_VOLATILE TCB_t * pxNextTCB;
- configLIST_VOLATILE TCB_t * pxFirstTCB;
UBaseType_t uxTask = 0;
+ const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
+ ListItem_t * pxIterator;
+ TCB_t * pxTCB = NULL;
if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
{
- listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
/* Populate an TaskStatus_t structure within the
* pxTaskStatusArray array for each task that is referenced from
* pxList. See the definition of TaskStatus_t in task.h for the
* meaning of each TaskStatus_t structure member. */
- do
+ for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
{
- listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
- vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );
+
+ vTaskGetInfo( ( TaskHandle_t ) pxTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
uxTask++;
- } while( pxNextTCB != pxFirstTCB );
+ }
}
else
{
@@ -3925,17 +6363,17 @@
static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
{
- uint32_t ulCount = 0U;
+ configSTACK_DEPTH_TYPE uxCount = 0U;
while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
{
pucStackByte -= portSTACK_GROWTH;
- ulCount++;
+ uxCount++;
}
- ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+ uxCount /= ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t );
- return ( configSTACK_DEPTH_TYPE ) ulCount;
+ return uxCount;
}
#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
@@ -3954,6 +6392,8 @@
uint8_t * pucEndOfStack;
configSTACK_DEPTH_TYPE uxReturn;
+ traceENTER_uxTaskGetStackHighWaterMark2( xTask );
+
/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
* the same except for their return type. Using configSTACK_DEPTH_TYPE
* allows the user to determine the return type. It gets around the
@@ -3962,6 +6402,7 @@
* type. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
#if portSTACK_GROWTH < 0
{
@@ -3975,6 +6416,8 @@
uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+ traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn );
+
return uxReturn;
}
@@ -3989,7 +6432,10 @@
uint8_t * pucEndOfStack;
UBaseType_t uxReturn;
+ traceENTER_uxTaskGetStackHighWaterMark( xTask );
+
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
#if portSTACK_GROWTH < 0
{
@@ -4003,6 +6449,8 @@
uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+ traceRETURN_uxTaskGetStackHighWaterMark( uxReturn );
+
return uxReturn;
}
@@ -4021,7 +6469,7 @@
#if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
{
/* Free up the memory allocated for the task's TLS Block. */
- configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+ configDEINIT_TLS_BLOCK( pxTCB->xTLSBlock );
}
#endif
@@ -4032,7 +6480,7 @@
vPortFreeStack( pxTCB->pxStack );
vPortFree( pxTCB );
}
- #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+ #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
{
/* The task could have been allocated statically or dynamically, so
* check what was statically allocated before trying to free the
@@ -4085,21 +6533,65 @@
}
/*-----------------------------------------------------------*/
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 )
- TaskHandle_t xTaskGetCurrentTaskHandle( void )
+ #if ( configNUMBER_OF_CORES == 1 )
+ TaskHandle_t xTaskGetCurrentTaskHandle( void )
+ {
+ TaskHandle_t xReturn;
+
+ traceENTER_xTaskGetCurrentTaskHandle();
+
+ /* A critical section is not required as this is not called from
+ * an interrupt and the current TCB will always be the same for any
+ * individual execution thread. */
+ xReturn = pxCurrentTCB;
+
+ traceRETURN_xTaskGetCurrentTaskHandle( xReturn );
+
+ return xReturn;
+ }
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ TaskHandle_t xTaskGetCurrentTaskHandle( void )
+ {
+ TaskHandle_t xReturn;
+ UBaseType_t uxSavedInterruptStatus;
+
+ traceENTER_xTaskGetCurrentTaskHandle();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK();
+ {
+ xReturn = pxCurrentTCBs[ portGET_CORE_ID() ];
+ }
+ portCLEAR_INTERRUPT_MASK( uxSavedInterruptStatus );
+
+ traceRETURN_xTaskGetCurrentTaskHandle( xReturn );
+
+ return xReturn;
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID )
{
- TaskHandle_t xReturn;
+ TaskHandle_t xReturn = NULL;
- /* A critical section is not required as this is not called from
- * an interrupt and the current TCB will always be the same for any
- * individual execution thread. */
- xReturn = pxCurrentTCB;
+ traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID );
+
+ if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
+ {
+ #if ( configNUMBER_OF_CORES == 1 )
+ xReturn = pxCurrentTCB;
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
+ xReturn = pxCurrentTCBs[ xCoreID ];
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+ }
+
+ traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn );
return xReturn;
}
-#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
@@ -4108,22 +6600,34 @@
{
BaseType_t xReturn;
+ traceENTER_xTaskGetSchedulerState();
+
if( xSchedulerRunning == pdFALSE )
{
xReturn = taskSCHEDULER_NOT_STARTED;
}
else
{
- if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+ #if ( configNUMBER_OF_CORES > 1 )
+ taskENTER_CRITICAL();
+ #endif
{
- xReturn = taskSCHEDULER_RUNNING;
+ if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
+ {
+ xReturn = taskSCHEDULER_RUNNING;
+ }
+ else
+ {
+ xReturn = taskSCHEDULER_SUSPENDED;
+ }
}
- else
- {
- xReturn = taskSCHEDULER_SUSPENDED;
- }
+ #if ( configNUMBER_OF_CORES > 1 )
+ taskEXIT_CRITICAL();
+ #endif
}
+ traceRETURN_xTaskGetSchedulerState( xReturn );
+
return xReturn;
}
@@ -4137,9 +6641,10 @@
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
BaseType_t xReturn = pdFALSE;
- /* If the mutex was given back by an interrupt while the queue was
- * locked then the mutex holder might now be NULL. _RB_ Is this still
- * needed as interrupts can no longer use mutexes? */
+ traceENTER_xTaskPriorityInherit( pxMutexHolder );
+
+ /* If the mutex is taken by an interrupt, the mutex holder is NULL. Priority
+ * inheritance is not applied in this scenario. */
if( pxMutexHolder != NULL )
{
/* If the holder of the mutex has a priority below the priority of
@@ -4150,9 +6655,9 @@
/* Adjust the mutex holder state to account for its new
* priority. Only reset the event list item value if the value is
* not being used for anything else. */
- if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
{
- listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority );
}
else
{
@@ -4178,6 +6683,16 @@
/* Inherit the priority before being moved into the new list. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
prvAddTaskToReadyList( pxMutexHolderTCB );
+ #if ( configNUMBER_OF_CORES > 1 )
+ {
+ /* The priority of the task is raised. Yield for this task
+ * if it is not running. */
+ if( taskTASK_IS_RUNNING( pxMutexHolderTCB ) != pdTRUE )
+ {
+ prvYieldForTask( pxMutexHolderTCB );
+ }
+ }
+ #endif /* if ( configNUMBER_OF_CORES > 1 ) */
}
else
{
@@ -4214,6 +6729,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xTaskPriorityInherit( xReturn );
+
return xReturn;
}
@@ -4227,6 +6744,8 @@
TCB_t * const pxTCB = pxMutexHolder;
BaseType_t xReturn = pdFALSE;
+ traceENTER_xTaskPriorityDisinherit( pxMutexHolder );
+
if( pxMutexHolder != NULL )
{
/* A task can only have an inherited priority if it holds the mutex.
@@ -4266,8 +6785,18 @@
/* Reset the event list item value. It cannot be in use for
* any other purpose if this task is running, and it must be
* running to give back the mutex. */
- listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority );
prvAddTaskToReadyList( pxTCB );
+ #if ( configNUMBER_OF_CORES > 1 )
+ {
+ /* The priority of the task is dropped. Yield the core on
+ * which the task is running. */
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ prvYieldCore( pxTCB->xTaskRunState );
+ }
+ }
+ #endif /* if ( configNUMBER_OF_CORES > 1 ) */
/* Return true to indicate that a context switch is required.
* This is only actually required in the corner case whereby
@@ -4294,6 +6823,8 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xTaskPriorityDisinherit( xReturn );
+
return xReturn;
}
@@ -4309,6 +6840,8 @@
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+ traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask );
+
if( pxMutexHolder != NULL )
{
/* If pxMutexHolder is not NULL then the holder must hold at least
@@ -4351,9 +6884,9 @@
/* Only reset the event list item value if the value is not
* being used for anything else. */
- if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
{
- listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse );
}
else
{
@@ -4381,6 +6914,16 @@
}
prvAddTaskToReadyList( pxTCB );
+ #if ( configNUMBER_OF_CORES > 1 )
+ {
+ /* The priority of the task is dropped. Yield the core on
+ * which the task is running. */
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ prvYieldCore( pxTCB->xTaskRunState );
+ }
+ }
+ #endif /* if ( configNUMBER_OF_CORES > 1 ) */
}
else
{
@@ -4401,15 +6944,52 @@
{
mtCOVERAGE_TEST_MARKER();
}
+
+ traceRETURN_vTaskPriorityDisinheritAfterTimeout();
}
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+#if ( configNUMBER_OF_CORES > 1 )
+
+/* If not in a critical section then yield immediately.
+ * Otherwise set xYieldPendings to true to wait to
+ * yield until exiting the critical section.
+ */
+ void vTaskYieldWithinAPI( void )
+ {
+ UBaseType_t ulState;
+
+ traceENTER_vTaskYieldWithinAPI();
+
+ ulState = portSET_INTERRUPT_MASK();
+ {
+ const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
+ {
+ portYIELD();
+ }
+ else
+ {
+ xYieldPendings[ xCoreID ] = pdTRUE;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK( ulState );
+
+ traceRETURN_vTaskYieldWithinAPI();
+ }
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )
void vTaskEnterCritical( void )
{
+ traceENTER_vTaskEnterCritical();
+
portDISABLE_INTERRUPTS();
if( xSchedulerRunning != pdFALSE )
@@ -4422,7 +7002,7 @@
* interrupt. Only assert if the critical nesting count is 1 to
* protect against recursive calls if the assert function also uses a
* critical section. */
- if( pxCurrentTCB->uxCriticalNesting == 1 )
+ if( pxCurrentTCB->uxCriticalNesting == 1U )
{
portASSERT_IF_IN_ISR();
}
@@ -4431,17 +7011,115 @@
{
mtCOVERAGE_TEST_MARKER();
}
+
+ traceRETURN_vTaskEnterCritical();
}
-#endif /* portCRITICAL_NESTING_IN_TCB */
+#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
/*-----------------------------------------------------------*/
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+#if ( configNUMBER_OF_CORES > 1 )
+
+ void vTaskEnterCritical( void )
+ {
+ traceENTER_vTaskEnterCritical();
+
+ portDISABLE_INTERRUPTS();
+ {
+ const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
+ {
+ portGET_TASK_LOCK( xCoreID );
+ portGET_ISR_LOCK( xCoreID );
+ }
+
+ portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID );
+
+ /* This is not the interrupt safe version of the enter critical
+ * function so assert() if it is being called from an interrupt
+ * context. Only API functions that end in "FromISR" can be used in an
+ * interrupt. Only assert if the critical nesting count is 1 to
+ * protect against recursive calls if the assert function also uses a
+ * critical section. */
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 1U )
+ {
+ portASSERT_IF_IN_ISR();
+
+ if( uxSchedulerSuspended == 0U )
+ {
+ /* The only time there would be a problem is if this is called
+ * before a context switch and vTaskExitCritical() is called
+ * after pxCurrentTCB changes. Therefore this should not be
+ * used within vTaskSwitchContext(). */
+ prvCheckForRunStateChange();
+ }
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ traceRETURN_vTaskEnterCritical();
+ }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+ UBaseType_t vTaskEnterCriticalFromISR( void )
+ {
+ UBaseType_t uxSavedInterruptStatus = 0;
+ const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ traceENTER_vTaskEnterCriticalFromISR();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
+ {
+ portGET_ISR_LOCK( xCoreID );
+ }
+
+ portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus );
+
+ return uxSavedInterruptStatus;
+ }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )
void vTaskExitCritical( void )
{
+ traceENTER_vTaskExitCritical();
+
if( xSchedulerRunning != pdFALSE )
{
+ /* If pxCurrentTCB->uxCriticalNesting is zero then this function
+ * does not match a previous call to vTaskEnterCritical(). */
+ configASSERT( pxCurrentTCB->uxCriticalNesting > 0U );
+
+ /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
+ * to exit critical section from ISR. */
+ portASSERT_IF_IN_ISR();
+
if( pxCurrentTCB->uxCriticalNesting > 0U )
{
( pxCurrentTCB->uxCriticalNesting )--;
@@ -4464,9 +7142,120 @@
{
mtCOVERAGE_TEST_MARKER();
}
+
+ traceRETURN_vTaskExitCritical();
}
-#endif /* portCRITICAL_NESTING_IN_TCB */
+#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+ void vTaskExitCritical( void )
+ {
+ const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ traceENTER_vTaskExitCritical();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* If critical nesting count is zero then this function
+ * does not match a previous call to vTaskEnterCritical(). */
+ configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U );
+
+ /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
+ * to exit critical section from ISR. */
+ portASSERT_IF_IN_ISR();
+
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U )
+ {
+ portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID );
+
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
+ {
+ BaseType_t xYieldCurrentTask;
+
+ /* Get the xYieldPending stats inside the critical section. */
+ xYieldCurrentTask = xYieldPendings[ xCoreID ];
+
+ portRELEASE_ISR_LOCK( xCoreID );
+ portRELEASE_TASK_LOCK( xCoreID );
+ portENABLE_INTERRUPTS();
+
+ /* When a task yields in a critical section it just sets
+ * xYieldPending to true. So now that we have exited the
+ * critical section check if xYieldPending is true, and
+ * if so yield. */
+ if( xYieldCurrentTask != pdFALSE )
+ {
+ portYIELD();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceRETURN_vTaskExitCritical();
+ }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configNUMBER_OF_CORES > 1 )
+
+ void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus )
+ {
+ BaseType_t xCoreID;
+
+ traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus );
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ xCoreID = ( BaseType_t ) portGET_CORE_ID();
+
+ /* If critical nesting count is zero then this function
+ * does not match a previous call to vTaskEnterCritical(). */
+ configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U );
+
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U )
+ {
+ portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID );
+
+ if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U )
+ {
+ portRELEASE_ISR_LOCK( xCoreID );
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceRETURN_vTaskExitCriticalFromISR();
+ }
+
+#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/
#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
@@ -4477,11 +7266,11 @@
size_t x;
/* Start by copying the entire string. */
- strcpy( pcBuffer, pcTaskName );
+ ( void ) strcpy( pcBuffer, pcTaskName );
/* Pad the end of the string with spaces to ensure columns line up when
* printed out. */
- for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+ for( x = strlen( pcBuffer ); x < ( size_t ) ( ( size_t ) configMAX_TASK_NAME_LEN - 1U ); x++ )
{
pcBuffer[ x ] = ' ';
}
@@ -4498,12 +7287,19 @@
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
- void vTaskList( char * pcWriteBuffer )
+ void vTaskListTasks( char * pcWriteBuffer,
+ size_t uxBufferLength )
{
TaskStatus_t * pxTaskStatusArray;
+ size_t uxConsumedBufferLength = 0;
+ size_t uxCharsWrittenBySnprintf;
+ int iSnprintfReturnValue;
+ BaseType_t xOutputBufferFull = pdFALSE;
UBaseType_t uxArraySize, x;
char cStatus;
+ traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength );
+
/*
* PLEASE NOTE:
*
@@ -4511,23 +7307,23 @@
* of the demo applications. Do not consider it to be part of the
* scheduler.
*
- * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
* uxTaskGetSystemState() output into a human readable table that
* displays task: names, states, priority, stack usage and task number.
* Stack usage specified as the number of unused StackType_t words stack can hold
* on top of stack - not the number of bytes.
*
- * vTaskList() has a dependency on the sprintf() C library function that
+ * vTaskListTasks() has a dependency on the snprintf() C library function that
* might bloat the code size, use a lot of stack, and provide different
* results on different platforms. An alternative, tiny, third party,
- * and limited functionality implementation of sprintf() is provided in
+ * and limited functionality implementation of snprintf() is provided in
* many of the FreeRTOS/Demo sub-directories in a file called
* printf-stdarg.c (note printf-stdarg.c does not provide a full
* snprintf() implementation!).
*
* It is recommended that production systems call uxTaskGetSystemState()
* directly to get access to raw stats data, rather than indirectly
- * through a call to vTaskList().
+ * through a call to vTaskListTasks().
*/
@@ -4541,7 +7337,10 @@
/* Allocate an array index for each task. NOTE! if
* configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
* equate to NULL. */
- pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
if( pxTaskStatusArray != NULL )
{
@@ -4580,13 +7379,65 @@
break;
}
- /* Write the task name to the string, padding with spaces so it
- * can be printed in tabular form more easily. */
- pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+ /* Is there enough space in the buffer to hold task name? */
+ if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
+ {
+ /* Write the task name to the string, padding with spaces so it
+ * can be printed in tabular form more easily. */
+ pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+ /* Do not count the terminating null character. */
+ uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );
- /* Write the rest of the string. */
- sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
- pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+ /* Is there space left in the buffer? -1 is done because snprintf
+ * writes a terminating null character. So we are essentially
+ * checking if the buffer has space to write at least one non-null
+ * character. */
+ if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
+ {
+ /* Write the rest of the string. */
+ #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
+ /* MISRA Ref 21.6.1 [snprintf for utility] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+ /* coverity[misra_c_2012_rule_21_6_violation] */
+ iSnprintfReturnValue = snprintf( pcWriteBuffer,
+ uxBufferLength - uxConsumedBufferLength,
+ "\t%c\t%u\t%u\t%u\t0x%x\r\n",
+ cStatus,
+ ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
+ ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
+ ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber,
+ ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask );
+ #else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
+ /* MISRA Ref 21.6.1 [snprintf for utility] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+ /* coverity[misra_c_2012_rule_21_6_violation] */
+ iSnprintfReturnValue = snprintf( pcWriteBuffer,
+ uxBufferLength - uxConsumedBufferLength,
+ "\t%c\t%u\t%u\t%u\r\n",
+ cStatus,
+ ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
+ ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
+ ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
+ #endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
+ uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
+
+ uxConsumedBufferLength += uxCharsWrittenBySnprintf;
+ pcWriteBuffer += uxCharsWrittenBySnprintf;
+ }
+ else
+ {
+ xOutputBufferFull = pdTRUE;
+ }
+ }
+ else
+ {
+ xOutputBufferFull = pdTRUE;
+ }
+
+ if( xOutputBufferFull == pdTRUE )
+ {
+ break;
+ }
}
/* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION
@@ -4597,6 +7448,8 @@
{
mtCOVERAGE_TEST_MARKER();
}
+
+ traceRETURN_vTaskListTasks();
}
#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
@@ -4604,11 +7457,19 @@
#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
- void vTaskGetRunTimeStats( char * pcWriteBuffer )
+ void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+ size_t uxBufferLength )
{
TaskStatus_t * pxTaskStatusArray;
+ size_t uxConsumedBufferLength = 0;
+ size_t uxCharsWrittenBySnprintf;
+ int iSnprintfReturnValue;
+ BaseType_t xOutputBufferFull = pdFALSE;
UBaseType_t uxArraySize, x;
- configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage;
+ configRUN_TIME_COUNTER_TYPE ulTotalTime = 0;
+ configRUN_TIME_COUNTER_TYPE ulStatsAsPercentage;
+
+ traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );
/*
* PLEASE NOTE:
@@ -4617,22 +7478,22 @@
* of the demo applications. Do not consider it to be part of the
* scheduler.
*
- * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+ * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part
* of the uxTaskGetSystemState() output into a human readable table that
* displays the amount of time each task has spent in the Running state
* in both absolute and percentage terms.
*
- * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+ * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library
* function that might bloat the code size, use a lot of stack, and
* provide different results on different platforms. An alternative,
* tiny, third party, and limited functionality implementation of
- * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+ * snprintf() is provided in many of the FreeRTOS/Demo sub-directories in
* a file called printf-stdarg.c (note printf-stdarg.c does not provide
* a full snprintf() implementation!).
*
* It is recommended that production systems call uxTaskGetSystemState()
* directly to get access to raw stats data, rather than indirectly
- * through a call to vTaskGetRunTimeStats().
+ * through a call to vTaskGetRunTimeStatistics().
*/
/* Make sure the write buffer does not contain a string. */
@@ -4645,7 +7506,10 @@
/* Allocate an array index for each task. NOTE! If
* configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
* equate to NULL. */
- pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
if( pxTaskStatusArray != NULL )
{
@@ -4653,10 +7517,10 @@
uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
/* For percentage calculations. */
- ulTotalTime /= 100UL;
+ ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100U );
/* Avoid divide by zero errors. */
- if( ulTotalTime > 0UL )
+ if( ulTotalTime > 0U )
{
/* Create a human readable table from the binary data. */
for( x = 0; x < uxArraySize; x++ )
@@ -4666,43 +7530,97 @@
* ulTotalRunTime has already been divided by 100. */
ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
- /* Write the task name to the string, padding with
- * spaces so it can be printed in tabular form more
- * easily. */
- pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
- if( ulStatsAsPercentage > 0UL )
+ /* Is there enough space in the buffer to hold task name? */
+ if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
{
- #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+ /* Write the task name to the string, padding with
+ * spaces so it can be printed in tabular form more
+ * easily. */
+ pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+ /* Do not count the terminating null character. */
+ uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );
+
+ /* Is there space left in the buffer? -1 is done because snprintf
+ * writes a terminating null character. So we are essentially
+ * checking if the buffer has space to write at least one non-null
+ * character. */
+ if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
{
- sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ if( ulStatsAsPercentage > 0U )
+ {
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+ {
+ /* MISRA Ref 21.6.1 [snprintf for utility] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+ /* coverity[misra_c_2012_rule_21_6_violation] */
+ iSnprintfReturnValue = snprintf( pcWriteBuffer,
+ uxBufferLength - uxConsumedBufferLength,
+ "\t%lu\t\t%lu%%\r\n",
+ pxTaskStatusArray[ x ].ulRunTimeCounter,
+ ulStatsAsPercentage );
+ }
+ #else /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ * printf() library can be used. */
+ /* MISRA Ref 21.6.1 [snprintf for utility] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+ /* coverity[misra_c_2012_rule_21_6_violation] */
+ iSnprintfReturnValue = snprintf( pcWriteBuffer,
+ uxBufferLength - uxConsumedBufferLength,
+ "\t%u\t\t%u%%\r\n",
+ ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter,
+ ( unsigned int ) ulStatsAsPercentage );
+ }
+ #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+ }
+ else
+ {
+ /* If the percentage is zero here then the task has
+ * consumed less than 1% of the total run time. */
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+ {
+ /* MISRA Ref 21.6.1 [snprintf for utility] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+ /* coverity[misra_c_2012_rule_21_6_violation] */
+ iSnprintfReturnValue = snprintf( pcWriteBuffer,
+ uxBufferLength - uxConsumedBufferLength,
+ "\t%lu\t\t<1%%\r\n",
+ pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
+ #else
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ * printf() library can be used. */
+ /* MISRA Ref 21.6.1 [snprintf for utility] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
+ /* coverity[misra_c_2012_rule_21_6_violation] */
+ iSnprintfReturnValue = snprintf( pcWriteBuffer,
+ uxBufferLength - uxConsumedBufferLength,
+ "\t%u\t\t<1%%\r\n",
+ ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
+ #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
+ }
+
+ uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
+ uxConsumedBufferLength += uxCharsWrittenBySnprintf;
+ pcWriteBuffer += uxCharsWrittenBySnprintf;
}
- #else
+ else
{
- /* sizeof( int ) == sizeof( long ) so a smaller
- * printf() library can be used. */
- sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+ xOutputBufferFull = pdTRUE;
}
- #endif
}
else
{
- /* If the percentage is zero here then the task has
- * consumed less than 1% of the total run time. */
- #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
- {
- sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
- }
- #else
- {
- /* sizeof( int ) == sizeof( long ) so a smaller
- * printf() library can be used. */
- sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
- }
- #endif
+ xOutputBufferFull = pdTRUE;
}
- pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+ if( xOutputBufferFull == pdTRUE )
+ {
+ break;
+ }
}
}
else
@@ -4718,6 +7636,8 @@
{
mtCOVERAGE_TEST_MARKER();
}
+
+ traceRETURN_vTaskGetRunTimeStatistics();
}
#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
@@ -4727,11 +7647,15 @@
{
TickType_t uxReturn;
+ traceENTER_uxTaskResetEventItemValue();
+
uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
/* Reset the event list item to its normal value - so it can be used with
* queues and semaphores. */
- listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) );
+
+ traceRETURN_uxTaskResetEventItemValue( uxReturn );
return uxReturn;
}
@@ -4741,14 +7665,22 @@
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
{
+ TCB_t * pxTCB;
+
+ traceENTER_pvTaskIncrementMutexHeldCount();
+
+ pxTCB = pxCurrentTCB;
+
/* If xSemaphoreCreateMutex() is called before any tasks have been created
* then pxCurrentTCB will be NULL. */
- if( pxCurrentTCB != NULL )
+ if( pxTCB != NULL )
{
- ( pxCurrentTCB->uxMutexesHeld )++;
+ ( pxTCB->uxMutexesHeld )++;
}
- return pxCurrentTCB;
+ traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB );
+
+ return pxTCB;
}
#endif /* configUSE_MUTEXES */
@@ -4756,59 +7688,87 @@
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait,
+ uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
BaseType_t xClearCountOnExit,
TickType_t xTicksToWait )
{
uint32_t ulReturn;
+ BaseType_t xAlreadyYielded, xShouldBlock = pdFALSE;
- configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+ traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
- taskENTER_CRITICAL();
+ configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+ /* If the notification count is zero, and if we are willing to wait for a
+ * notification, then block the task and wait. */
+ if( ( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U ) && ( xTicksToWait > ( TickType_t ) 0 ) )
{
- /* Only block if the notification count is not already non-zero. */
- if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL )
+ /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
+ * non-deterministic operation. */
+ vTaskSuspendAll();
{
- /* Mark this task as waiting for a notification. */
- pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
-
- if( xTicksToWait > ( TickType_t ) 0 )
+ /* We MUST enter a critical section to atomically check if a notification
+ * has occurred and set the flag to indicate that we are waiting for
+ * a notification. If we do not do so, a notification sent from an ISR
+ * will get lost. */
+ taskENTER_CRITICAL();
{
- prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
- traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait );
+ /* Only block if the notification count is not already non-zero. */
+ if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U )
+ {
+ /* Mark this task as waiting for a notification. */
+ pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
- /* All ports are written to allow a yield in a critical
- * section (some will yield immediately, others wait until the
- * critical section exits) - but it is not something that
- * application code should ever do. */
- portYIELD_WITHIN_API();
+ /* Arrange to wait for a notification. */
+ xShouldBlock = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* We are now out of the critical section but the scheduler is still
+ * suspended, so we are safe to do non-deterministic operations such
+ * as prvAddCurrentTaskToDelayedList. */
+ if( xShouldBlock == pdTRUE )
+ {
+ traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
+ prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
+ xAlreadyYielded = xTaskResumeAll();
+
+ /* Force a reschedule if xTaskResumeAll has not already done so. */
+ if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
+ {
+ taskYIELD_WITHIN_API();
+ }
else
{
mtCOVERAGE_TEST_MARKER();
}
}
- taskEXIT_CRITICAL();
taskENTER_CRITICAL();
{
- traceTASK_NOTIFY_TAKE( uxIndexToWait );
- ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
+ traceTASK_NOTIFY_TAKE( uxIndexToWaitOn );
+ ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
- if( ulReturn != 0UL )
+ if( ulReturn != 0U )
{
if( xClearCountOnExit != pdFALSE )
{
- pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL;
+ pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0U;
}
else
{
- pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1;
+ pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ulReturn - ( uint32_t ) 1;
}
}
else
@@ -4816,10 +7776,12 @@
mtCOVERAGE_TEST_MARKER();
}
- pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
+ pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
}
taskEXIT_CRITICAL();
+ traceRETURN_ulTaskGenericNotifyTake( ulReturn );
+
return ulReturn;
}
@@ -4828,68 +7790,94 @@
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait,
+ BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
uint32_t ulBitsToClearOnEntry,
uint32_t ulBitsToClearOnExit,
uint32_t * pulNotificationValue,
TickType_t xTicksToWait )
{
- BaseType_t xReturn;
+ BaseType_t xReturn, xAlreadyYielded, xShouldBlock = pdFALSE;
- configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+ traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
- taskENTER_CRITICAL();
+ configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+ /* If the task hasn't received a notification, and if we are willing to wait
+ * for it, then block the task and wait. */
+ if( ( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED ) && ( xTicksToWait > ( TickType_t ) 0 ) )
{
- /* Only block if a notification is not already pending. */
- if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
+ /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
+ * non-deterministic operation. */
+ vTaskSuspendAll();
{
- /* Clear bits in the task's notification value as bits may get
- * set by the notifying task or interrupt. This can be used to
- * clear the value to zero. */
- pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry;
-
- /* Mark this task as waiting for a notification. */
- pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
-
- if( xTicksToWait > ( TickType_t ) 0 )
+ /* We MUST enter a critical section to atomically check and update the
+ * task notification value. If we do not do so, a notification from
+ * an ISR will get lost. */
+ taskENTER_CRITICAL();
{
- prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
- traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait );
+ /* Only block if a notification is not already pending. */
+ if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
+ {
+ /* Clear bits in the task's notification value as bits may get
+ * set by the notifying task or interrupt. This can be used
+ * to clear the value to zero. */
+ pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;
- /* All ports are written to allow a yield in a critical
- * section (some will yield immediately, others wait until the
- * critical section exits) - but it is not something that
- * application code should ever do. */
- portYIELD_WITHIN_API();
+ /* Mark this task as waiting for a notification. */
+ pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;
+
+ /* Arrange to wait for a notification. */
+ xShouldBlock = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* We are now out of the critical section but the scheduler is still
+ * suspended, so we are safe to do non-deterministic operations such
+ * as prvAddCurrentTaskToDelayedList. */
+ if( xShouldBlock == pdTRUE )
+ {
+ traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
+ prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
+ xAlreadyYielded = xTaskResumeAll();
+
+ /* Force a reschedule if xTaskResumeAll has not already done so. */
+ if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
+ {
+ taskYIELD_WITHIN_API();
+ }
else
{
mtCOVERAGE_TEST_MARKER();
}
}
- taskEXIT_CRITICAL();
taskENTER_CRITICAL();
{
- traceTASK_NOTIFY_WAIT( uxIndexToWait );
+ traceTASK_NOTIFY_WAIT( uxIndexToWaitOn );
if( pulNotificationValue != NULL )
{
/* Output the current notification value, which may or may not
* have changed. */
- *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
+ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
}
/* If ucNotifyValue is set then either the task never entered the
* blocked state (because a notification was already pending) or the
* task unblocked because of a notification. Otherwise the task
* unblocked because of a timeout. */
- if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
+ if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
{
/* A notification was not received. */
xReturn = pdFALSE;
@@ -4898,14 +7886,16 @@
{
/* A notification was already pending or a notification was
* received while the task was waiting. */
- pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit;
+ pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnExit;
xReturn = pdTRUE;
}
- pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
+ pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
}
taskEXIT_CRITICAL();
+ traceRETURN_xTaskGenericNotifyWait( xReturn );
+
return xReturn;
}
@@ -4924,6 +7914,8 @@
BaseType_t xReturn = pdPASS;
uint8_t ucOriginalNotifyState;
+ traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
configASSERT( xTaskToNotify );
pxTCB = xTaskToNotify;
@@ -5011,16 +8003,9 @@
}
#endif
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
- {
- /* The notified task has a priority above the currently
- * executing task so a yield is required. */
- taskYIELD_IF_USING_PREEMPTION();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* Check if the notified task has a priority above the currently
+ * executing task. */
+ taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
}
else
{
@@ -5029,6 +8014,8 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_xTaskGenericNotify( xReturn );
+
return xReturn;
}
@@ -5049,6 +8036,8 @@
BaseType_t xReturn = pdPASS;
UBaseType_t uxSavedInterruptStatus;
+ traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken );
+
configASSERT( xTaskToNotify );
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
@@ -5072,7 +8061,10 @@
pxTCB = xTaskToNotify;
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
{
if( pulPreviousNotificationValue != NULL )
{
@@ -5138,6 +8130,22 @@
{
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
prvAddTaskToReadyList( pxTCB );
+
+ #if ( configUSE_TICKLESS_IDLE != 0 )
+ {
+ /* If a task is blocked waiting for a notification then
+ * xNextTaskUnblockTime might be set to the blocked task's time
+ * out time. If the task is unblocked for a reason other than
+ * a timeout xNextTaskUnblockTime is normally left unchanged,
+ * because it will automatically get reset to a new value when
+ * the tick count equals xNextTaskUnblockTime. However if
+ * tickless idling is used it might be more important to enter
+ * sleep mode at the earliest possible time - so reset
+ * xNextTaskUnblockTime here to ensure it is updated at the
+ * earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
+ #endif
}
else
{
@@ -5146,27 +8154,49 @@
listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
}
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- /* The notified task has a priority above the currently
- * executing task so a yield is required. */
- if( pxHigherPriorityTaskWoken != NULL )
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
{
- *pxHigherPriorityTaskWoken = pdTRUE;
- }
+ /* The notified task has a priority above the currently
+ * executing task so a yield is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
- /* Mark that a yield is pending in case the user is not
- * using the "xHigherPriorityTaskWoken" parameter to an ISR
- * safe FreeRTOS function. */
- xYieldPending = pdTRUE;
+ /* Mark that a yield is pending in case the user is not
+ * using the "xHigherPriorityTaskWoken" parameter to an ISR
+ * safe FreeRTOS function. */
+ xYieldPendings[ 0 ] = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
{
- mtCOVERAGE_TEST_MARKER();
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ prvYieldForTask( pxTCB );
+
+ if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
+ {
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ }
+ }
+ #endif /* if ( configUSE_PREEMPTION == 1 ) */
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_xTaskGenericNotifyFromISR( xReturn );
return xReturn;
}
@@ -5184,6 +8214,8 @@
uint8_t ucOriginalNotifyState;
UBaseType_t uxSavedInterruptStatus;
+ traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken );
+
configASSERT( xTaskToNotify );
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
@@ -5207,7 +8239,10 @@
pxTCB = xTaskToNotify;
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ /* MISRA Ref 4.7.1 [Return value shall be checked] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
+ /* coverity[misra_c_2012_directive_4_7_violation] */
+ uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
{
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
@@ -5229,6 +8264,22 @@
{
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
prvAddTaskToReadyList( pxTCB );
+
+ #if ( configUSE_TICKLESS_IDLE != 0 )
+ {
+ /* If a task is blocked waiting for a notification then
+ * xNextTaskUnblockTime might be set to the blocked task's time
+ * out time. If the task is unblocked for a reason other than
+ * a timeout xNextTaskUnblockTime is normally left unchanged,
+ * because it will automatically get reset to a new value when
+ * the tick count equals xNextTaskUnblockTime. However if
+ * tickless idling is used it might be more important to enter
+ * sleep mode at the earliest possible time - so reset
+ * xNextTaskUnblockTime here to ensure it is updated at the
+ * earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
+ #endif
}
else
{
@@ -5237,27 +8288,49 @@
listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
}
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ #if ( configNUMBER_OF_CORES == 1 )
{
- /* The notified task has a priority above the currently
- * executing task so a yield is required. */
- if( pxHigherPriorityTaskWoken != NULL )
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
{
- *pxHigherPriorityTaskWoken = pdTRUE;
- }
+ /* The notified task has a priority above the currently
+ * executing task so a yield is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
- /* Mark that a yield is pending in case the user is not
- * using the "xHigherPriorityTaskWoken" parameter in an ISR
- * safe FreeRTOS function. */
- xYieldPending = pdTRUE;
+ /* Mark that a yield is pending in case the user is not
+ * using the "xHigherPriorityTaskWoken" parameter in an ISR
+ * safe FreeRTOS function. */
+ xYieldPendings[ 0 ] = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
+ #else /* #if ( configNUMBER_OF_CORES == 1 ) */
{
- mtCOVERAGE_TEST_MARKER();
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ prvYieldForTask( pxTCB );
+
+ if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
+ {
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ }
+ }
+ #endif /* #if ( configUSE_PREEMPTION == 1 ) */
}
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
}
}
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
+
+ traceRETURN_vTaskGenericNotifyGiveFromISR();
}
#endif /* configUSE_TASK_NOTIFICATIONS */
@@ -5271,11 +8344,14 @@
TCB_t * pxTCB;
BaseType_t xReturn;
+ traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
+
configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
/* If null is passed in here then it is the calling task that is having
* its notification state cleared. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
taskENTER_CRITICAL();
{
@@ -5291,6 +8367,8 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_xTaskGenericNotifyStateClear( xReturn );
+
return xReturn;
}
@@ -5306,11 +8384,14 @@
TCB_t * pxTCB;
uint32_t ulReturn;
+ traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
+
configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
/* If null is passed in here then it is the calling task that is having
* its notification state cleared. */
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
taskENTER_CRITICAL();
{
@@ -5321,6 +8402,8 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_ulTaskGenericNotifyValueClear( ulReturn );
+
return ulReturn;
}
@@ -5331,34 +8414,38 @@
configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask )
{
- return xTask->ulRunTimeCounter;
- }
+ TCB_t * pxTCB;
+ configRUN_TIME_COUNTER_TYPE ulTotalTime = 0, ulTimeSinceLastSwitchedIn = 0, ulTaskRunTime = 0;
-#endif
-/*-----------------------------------------------------------*/
+ traceENTER_ulTaskGetRunTimeCounter( xTask );
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
- configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask )
- {
- configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
-
- ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
-
- /* For percentage calculations. */
- ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
-
- /* Avoid divide by zero errors. */
- if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
+ taskENTER_CRITICAL();
{
- ulReturn = xTask->ulRunTimeCounter / ulTotalTime;
- }
- else
- {
- ulReturn = 0;
- }
+ if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+ #else
+ ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
- return ulReturn;
+ #if ( configNUMBER_OF_CORES == 1 )
+ ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ 0 ];
+ #else
+ ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ pxTCB->xTaskRunState ];
+ #endif
+ }
+
+ ulTaskRunTime = pxTCB->ulRunTimeCounter + ulTimeSinceLastSwitchedIn;
+ }
+ taskEXIT_CRITICAL();
+
+ traceRETURN_ulTaskGetRunTimeCounter( ulTaskRunTime );
+
+ return ulTaskRunTime;
}
#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
@@ -5366,22 +8453,127 @@
#if ( configGENERATE_RUN_TIME_STATS == 1 )
- configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void )
+ configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask )
{
- return ulTaskGetRunTimeCounter( xIdleTaskHandle );
+ TCB_t * pxTCB;
+ configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn, ulTaskRunTime;
+
+ traceENTER_ulTaskGetRunTimePercent( xTask );
+
+ ulTaskRunTime = ulTaskGetRunTimeCounter( xTask );
+
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+ #else
+ ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ /* For percentage calculations. */
+ ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
+
+ /* Avoid divide by zero errors. */
+ if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
+ {
+ pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ ulReturn = ulTaskRunTime / ulTotalTime;
+ }
+ else
+ {
+ ulReturn = 0;
+ }
+
+ traceRETURN_ulTaskGetRunTimePercent( ulReturn );
+
+ return ulReturn;
}
-#endif
+#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
/*-----------------------------------------------------------*/
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+ configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void )
+ {
+ configRUN_TIME_COUNTER_TYPE ulTotalTime = 0, ulTimeSinceLastSwitchedIn = 0, ulIdleTaskRunTime = 0;
+ BaseType_t i;
+
+ traceENTER_ulTaskGetIdleRunTimeCounter();
+
+ taskENTER_CRITICAL();
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+ #else
+ ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
+ {
+ if( taskTASK_IS_RUNNING( xIdleTaskHandles[ i ] ) == pdTRUE )
+ {
+ #if ( configNUMBER_OF_CORES == 1 )
+ ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ 0 ];
+ #else
+ ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ xIdleTaskHandles[ i ]->xTaskRunState ];
+ #endif
+ }
+ else
+ {
+ ulTimeSinceLastSwitchedIn = 0;
+ }
+
+ ulIdleTaskRunTime += ( xIdleTaskHandles[ i ]->ulRunTimeCounter + ulTimeSinceLastSwitchedIn );
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ traceRETURN_ulTaskGetIdleRunTimeCounter( ulIdleTaskRunTime );
+
+ return ulIdleTaskRunTime;
+ }
+
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void )
{
- return ulTaskGetRunTimePercent( xIdleTaskHandle );
+ configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
+ configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0;
+
+ traceENTER_ulTaskGetIdleRunTimePercent();
+
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime );
+ #else
+ ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ ulTotalTime *= configNUMBER_OF_CORES;
+
+ /* For percentage calculations. */
+ ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;
+
+ /* Avoid divide by zero errors. */
+ if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
+ {
+ ulRunTimeCounter = ulTaskGetIdleRunTimeCounter();
+ ulReturn = ulRunTimeCounter / ulTotalTime;
+ }
+ else
+ {
+ ulReturn = 0;
+ }
+
+ traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn );
+
+ return ulReturn;
}
-#endif
+#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
@@ -5389,13 +8581,15 @@
{
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
+ List_t * const pxDelayedList = pxDelayedTaskList;
+ List_t * const pxOverflowDelayedList = pxOverflowDelayedTaskList;
#if ( INCLUDE_xTaskAbortDelay == 1 )
{
/* About to enter a delayed list, so ensure the ucDelayAborted flag is
* reset to pdFALSE so it can be detected as having been set to pdTRUE
* when the task leaves the Blocked state. */
- pxCurrentTCB->ucDelayAborted = pdFALSE;
+ pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE;
}
#endif
@@ -5405,7 +8599,7 @@
{
/* The current task must be in a ready list, so there is no need to
* check, and the port reset macro can be called directly. */
- portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
}
else
{
@@ -5435,13 +8629,15 @@
{
/* Wake time has overflowed. Place this item in the overflow
* list. */
- vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
+ vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
}
else
{
/* The wake time has not overflowed, so the current block list
* is used. */
- vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ traceMOVED_TASK_TO_DELAYED_LIST();
+ vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );
/* If the task entering the blocked state was placed at the
* head of the list of blocked tasks then xNextTaskUnblockTime
@@ -5469,13 +8665,15 @@
if( xTimeToWake < xConstTickCount )
{
+ traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
/* Wake time has overflowed. Place this item in the overflow list. */
- vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
}
else
{
+ traceMOVED_TASK_TO_DELAYED_LIST();
/* The wake time has not overflowed, so the current block list is used. */
- vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );
/* If the task entering the blocked state was placed at the head of the
* list of blocked tasks then xNextTaskUnblockTime needs to be updated
@@ -5503,7 +8701,12 @@
{
TCB_t * pxTCB;
+ traceENTER_xTaskGetMPUSettings( xTask );
+
pxTCB = prvGetTCBFromHandle( xTask );
+ configASSERT( pxTCB != NULL );
+
+ traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) );
return &( pxTCB->xMPUSettings );
}
@@ -5532,3 +8735,127 @@
#endif
#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+
+/*
+ * This is the kernel provided implementation of vApplicationGetIdleTaskMemory()
+ * to provide the memory that is used by the Idle task. It is used when
+ * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
+ * it's own implementation of vApplicationGetIdleTaskMemory by setting
+ * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
+ */
+ void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+ StackType_t ** ppxIdleTaskStackBuffer,
+ configSTACK_DEPTH_TYPE * puxIdleTaskStackSize )
+ {
+ static StaticTask_t xIdleTaskTCB;
+ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+ *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
+ *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
+ *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+ }
+
+ #if ( configNUMBER_OF_CORES > 1 )
+
+ void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+ StackType_t ** ppxIdleTaskStackBuffer,
+ configSTACK_DEPTH_TYPE * puxIdleTaskStackSize,
+ BaseType_t xPassiveIdleTaskIndex )
+ {
+ static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ];
+ static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ];
+
+ *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xPassiveIdleTaskIndex ] );
+ *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] );
+ *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+ }
+
+ #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
+
+#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) && ( configUSE_TIMERS == 1 ) )
+
+/*
+ * This is the kernel provided implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. It is used when
+ * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
+ * it's own implementation of vApplicationGetTimerTaskMemory by setting
+ * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
+ */
+ void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+ StackType_t ** ppxTimerTaskStackBuffer,
+ configSTACK_DEPTH_TYPE * puxTimerTaskStackSize )
+ {
+ static StaticTask_t xTimerTaskTCB;
+ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
+
+ *ppxTimerTaskTCBBuffer = &( xTimerTaskTCB );
+ *ppxTimerTaskStackBuffer = &( uxTimerTaskStack[ 0 ] );
+ *puxTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+ }
+
+#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+void vTaskResetState( void )
+{
+ BaseType_t xCoreID;
+
+ /* Task control block. */
+ #if ( configNUMBER_OF_CORES == 1 )
+ {
+ pxCurrentTCB = NULL;
+ }
+ #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ {
+ uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+ }
+ #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */
+
+ #if ( configUSE_POSIX_ERRNO == 1 )
+ {
+ FreeRTOS_errno = 0;
+ }
+ #endif /* #if ( configUSE_POSIX_ERRNO == 1 ) */
+
+ /* Other file private variables. */
+ uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
+ xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+ uxTopReadyPriority = tskIDLE_PRIORITY;
+ xSchedulerRunning = pdFALSE;
+ xPendedTicks = ( TickType_t ) 0U;
+
+ for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
+ {
+ xYieldPendings[ xCoreID ] = pdFALSE;
+ }
+
+ xNumOfOverflows = ( BaseType_t ) 0;
+ uxTaskNumber = ( UBaseType_t ) 0U;
+ xNextTaskUnblockTime = ( TickType_t ) 0U;
+
+ uxSchedulerSuspended = ( UBaseType_t ) 0U;
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
+ {
+ ulTaskSwitchedInTime[ xCoreID ] = 0U;
+ ulTotalRunTime[ xCoreID ] = 0U;
+ }
+ }
+ #endif /* #if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/timers.c b/Source/timers.c
index d5012ad..454be0a 100644
--- a/Source/timers.c
+++ b/Source/timers.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.6.2
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V11.2.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
@@ -43,11 +43,10 @@
#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
#endif
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
* for the header files above, but not in this file, in order to generate the
* correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/* This entire source file will be skipped if the application is not configured
@@ -60,29 +59,38 @@
#define tmrNO_DELAY ( ( TickType_t ) 0U )
#define tmrMAX_TIME_BEFORE_OVERFLOW ( ( TickType_t ) -1 )
-/* The name assigned to the timer service task. This can be overridden by
- * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+/* The name assigned to the timer service task. This can be overridden by
+ * defining configTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
#ifndef configTIMER_SERVICE_TASK_NAME
#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
#endif
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
+
+/* The core affinity assigned to the timer service task on SMP systems.
+ * This can be overridden by defining configTIMER_SERVICE_TASK_CORE_AFFINITY in FreeRTOSConfig.h. */
+ #ifndef configTIMER_SERVICE_TASK_CORE_AFFINITY
+ #define configTIMER_SERVICE_TASK_CORE_AFFINITY tskNO_AFFINITY
+ #endif
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
+
/* Bit definitions used in the ucStatus member of a timer structure. */
- #define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 )
- #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 )
- #define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 )
+ #define tmrSTATUS_IS_ACTIVE ( 0x01U )
+ #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( 0x02U )
+ #define tmrSTATUS_IS_AUTORELOAD ( 0x04U )
/* The definition of the timers themselves. */
- typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+ typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
{
- const char * pcTimerName; /**< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- ListItem_t xTimerListItem; /**< Standard linked list item as used by all kernel features for event management. */
- TickType_t xTimerPeriodInTicks; /**< How quickly and often the timer expires. */
- void * pvTimerID; /**< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */
- TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */
+ const char * pcTimerName; /**< Text name. This is not used by the kernel, it is included simply to make debugging easier. */
+ ListItem_t xTimerListItem; /**< Standard linked list item as used by all kernel features for event management. */
+ TickType_t xTimerPeriodInTicks; /**< How quickly and often the timer expires. */
+ void * pvTimerID; /**< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */
+ portTIMER_CALLBACK_ATTRIBUTE TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */
#if ( configUSE_TRACE_FACILITY == 1 )
- UBaseType_t uxTimerNumber; /**< An ID assigned by trace tools such as FreeRTOS+Trace */
+ UBaseType_t uxTimerNumber; /**< An ID assigned by trace tools such as FreeRTOS+Trace */
#endif
- uint8_t ucStatus; /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+ uint8_t ucStatus; /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
} xTIMER;
/* The old xTIMER name is maintained above then typedefed to the new Timer_t
@@ -103,6 +111,7 @@
typedef struct tmrCallbackParameters
{
+ portTIMER_CALLBACK_ATTRIBUTE
PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
void * pvParameter1; /* << The value that will be used as the callback functions first parameter. */
uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */
@@ -125,9 +134,6 @@
} u;
} DaemonTaskMessage_t;
-/*lint -save -e956 A manual analysis and inspection has been used to determine
- * which static variables must be declared volatile. */
-
/* The list in which active timers are stored. Timers are referenced in expire
* time order, with the nearest expiry time at the front of the list. Only the
* timer service task is allowed to access these lists.
@@ -143,8 +149,6 @@
PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
-/*lint -restore */
-
/*-----------------------------------------------------------*/
/*
@@ -222,7 +226,7 @@
* Called after a Timer_t structure has been allocated either statically or
* dynamically to fill in the structure's members.
*/
- static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ static void prvInitialiseNewTimer( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
const BaseType_t xAutoReload,
void * const pvTimerID,
@@ -234,6 +238,8 @@
{
BaseType_t xReturn = pdFAIL;
+ traceENTER_xTimerCreateTimerTask();
+
/* This function is called when the scheduler is started if
* configUSE_TIMERS is set to 1. Check that the infrastructure used by the
* timer service task has been created/initialised. If timers have already
@@ -242,36 +248,75 @@
if( xTimerQueue != NULL )
{
- #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
{
- StaticTask_t * pxTimerTaskTCBBuffer = NULL;
- StackType_t * pxTimerTaskStackBuffer = NULL;
- uint32_t ulTimerTaskStackSize;
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+ StackType_t * pxTimerTaskStackBuffer = NULL;
+ configSTACK_DEPTH_TYPE uxTimerTaskStackSize;
- vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
- xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+ vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
+ xTimerTaskHandle = xTaskCreateStaticAffinitySet( &prvTimerTask,
+ configTIMER_SERVICE_TASK_NAME,
+ uxTimerTaskStackSize,
+ NULL,
+ ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+ pxTimerTaskStackBuffer,
+ pxTimerTaskTCBBuffer,
+ configTIMER_SERVICE_TASK_CORE_AFFINITY );
+
+ if( xTimerTaskHandle != NULL )
+ {
+ xReturn = pdPASS;
+ }
+ }
+ #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ {
+ xReturn = xTaskCreateAffinitySet( &prvTimerTask,
configTIMER_SERVICE_TASK_NAME,
- ulTimerTaskStackSize,
+ configTIMER_TASK_STACK_DEPTH,
NULL,
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
- pxTimerTaskStackBuffer,
- pxTimerTaskTCBBuffer );
-
- if( xTimerTaskHandle != NULL )
- {
- xReturn = pdPASS;
+ configTIMER_SERVICE_TASK_CORE_AFFINITY,
+ &xTimerTaskHandle );
}
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
}
- #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ #else /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
{
- xReturn = xTaskCreate( prvTimerTask,
- configTIMER_SERVICE_TASK_NAME,
- configTIMER_TASK_STACK_DEPTH,
- NULL,
- ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
- &xTimerTaskHandle );
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+ StackType_t * pxTimerTaskStackBuffer = NULL;
+ configSTACK_DEPTH_TYPE uxTimerTaskStackSize;
+
+ vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
+ xTimerTaskHandle = xTaskCreateStatic( &prvTimerTask,
+ configTIMER_SERVICE_TASK_NAME,
+ uxTimerTaskStackSize,
+ NULL,
+ ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+ pxTimerTaskStackBuffer,
+ pxTimerTaskTCBBuffer );
+
+ if( xTimerTaskHandle != NULL )
+ {
+ xReturn = pdPASS;
+ }
+ }
+ #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ {
+ xReturn = xTaskCreate( &prvTimerTask,
+ configTIMER_SERVICE_TASK_NAME,
+ configTIMER_TASK_STACK_DEPTH,
+ NULL,
+ ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+ &xTimerTaskHandle );
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
}
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
}
else
{
@@ -279,13 +324,16 @@
}
configASSERT( xReturn );
+
+ traceRETURN_xTimerCreateTimerTask( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ TimerHandle_t xTimerCreate( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
const BaseType_t xAutoReload,
void * const pvTimerID,
@@ -293,7 +341,12 @@
{
Timer_t * pxNewTimer;
- pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+ traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction );
+
+ /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
if( pxNewTimer != NULL )
{
@@ -304,6 +357,8 @@
prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
}
+ traceRETURN_xTimerCreate( pxNewTimer );
+
return pxNewTimer;
}
@@ -312,7 +367,7 @@
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
const BaseType_t xAutoReload,
void * const pvTimerID,
@@ -321,6 +376,8 @@
{
Timer_t * pxNewTimer;
+ traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
+
#if ( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
@@ -328,31 +385,36 @@
* structure. */
volatile size_t xSize = sizeof( StaticTimer_t );
configASSERT( xSize == sizeof( Timer_t ) );
- ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */
}
#endif /* configASSERT_DEFINED */
/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
configASSERT( pxTimerBuffer );
- pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
+ pxNewTimer = ( Timer_t * ) pxTimerBuffer;
if( pxNewTimer != NULL )
{
/* Timers can be created statically or dynamically so note this
* timer was created statically in case it is later deleted. The
* auto-reload bit may get set in prvInitialiseNewTimer(). */
- pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+ pxNewTimer->ucStatus = ( uint8_t ) tmrSTATUS_IS_STATICALLY_ALLOCATED;
prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
}
+ traceRETURN_xTimerCreateStatic( pxNewTimer );
+
return pxNewTimer;
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
- static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ static void prvInitialiseNewTimer( const char * const pcTimerName,
const TickType_t xTimerPeriodInTicks,
const BaseType_t xAutoReload,
void * const pvTimerID,
@@ -376,33 +438,37 @@
if( xAutoReload != pdFALSE )
{
- pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+ pxNewTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
}
traceTIMER_CREATE( pxNewTimer );
}
/*-----------------------------------------------------------*/
- BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
- const BaseType_t xCommandID,
- const TickType_t xOptionalValue,
- BaseType_t * const pxHigherPriorityTaskWoken,
- const TickType_t xTicksToWait )
+ BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait )
{
BaseType_t xReturn = pdFAIL;
DaemonTaskMessage_t xMessage;
- configASSERT( xTimer );
+ ( void ) pxHigherPriorityTaskWoken;
+
+ traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
/* Send a message to the timer service task to perform a particular action
* on a particular timer definition. */
- if( xTimerQueue != NULL )
+ if( ( xTimerQueue != NULL ) && ( xTimer != NULL ) )
{
/* Send a command to the timer service task to start the xTimer timer. */
xMessage.xMessageID = xCommandID;
xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
xMessage.u.xTimerParameters.pxTimer = xTimer;
+ configASSERT( xCommandID < tmrFIRST_FROM_ISR_COMMAND );
+
if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
{
if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
@@ -414,7 +480,45 @@
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
}
}
- else
+
+ traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceRETURN_xTimerGenericCommandFromTask( xReturn );
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn = pdFAIL;
+ DaemonTaskMessage_t xMessage;
+
+ ( void ) xTicksToWait;
+
+ traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+
+ /* Send a message to the timer service task to perform a particular action
+ * on a particular timer definition. */
+ if( ( xTimerQueue != NULL ) && ( xTimer != NULL ) )
+ {
+ /* Send a command to the timer service task to start the xTimer timer. */
+ xMessage.xMessageID = xCommandID;
+ xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+ xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+ configASSERT( xCommandID >= tmrFIRST_FROM_ISR_COMMAND );
+
+ if( xCommandID >= tmrFIRST_FROM_ISR_COMMAND )
{
xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
}
@@ -426,15 +530,22 @@
mtCOVERAGE_TEST_MARKER();
}
+ traceRETURN_xTimerGenericCommandFromISR( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
{
+ traceENTER_xTimerGetTimerDaemonTaskHandle();
+
/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
* started, then xTimerTaskHandle will be NULL. */
configASSERT( ( xTimerTaskHandle != NULL ) );
+
+ traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle );
+
return xTimerTaskHandle;
}
/*-----------------------------------------------------------*/
@@ -443,7 +554,12 @@
{
Timer_t * pxTimer = xTimer;
+ traceENTER_xTimerGetPeriod( xTimer );
+
configASSERT( xTimer );
+
+ traceRETURN_xTimerGetPeriod( pxTimer->xTimerPeriodInTicks );
+
return pxTimer->xTimerPeriodInTicks;
}
/*-----------------------------------------------------------*/
@@ -453,12 +569,14 @@
{
Timer_t * pxTimer = xTimer;
+ traceENTER_vTimerSetReloadMode( xTimer, xAutoReload );
+
configASSERT( xTimer );
taskENTER_CRITICAL();
{
if( xAutoReload != pdFALSE )
{
- pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+ pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
}
else
{
@@ -466,6 +584,8 @@
}
}
taskEXIT_CRITICAL();
+
+ traceRETURN_vTimerSetReloadMode();
}
/*-----------------------------------------------------------*/
@@ -474,10 +594,12 @@
Timer_t * pxTimer = xTimer;
BaseType_t xReturn;
+ traceENTER_xTimerGetReloadMode( xTimer );
+
configASSERT( xTimer );
- taskENTER_CRITICAL();
+ portBASE_TYPE_ENTER_CRITICAL();
{
- if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0U )
{
/* Not an auto-reload timer. */
xReturn = pdFALSE;
@@ -488,14 +610,24 @@
xReturn = pdTRUE;
}
}
- taskEXIT_CRITICAL();
+ portBASE_TYPE_EXIT_CRITICAL();
+
+ traceRETURN_xTimerGetReloadMode( xReturn );
return xReturn;
}
UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
{
- return ( UBaseType_t ) xTimerGetReloadMode( xTimer );
+ UBaseType_t uxReturn;
+
+ traceENTER_uxTimerGetReloadMode( xTimer );
+
+ uxReturn = ( UBaseType_t ) xTimerGetReloadMode( xTimer );
+
+ traceRETURN_uxTimerGetReloadMode( uxReturn );
+
+ return uxReturn;
}
/*-----------------------------------------------------------*/
@@ -504,8 +636,13 @@
Timer_t * pxTimer = xTimer;
TickType_t xReturn;
+ traceENTER_xTimerGetExpiryTime( xTimer );
+
configASSERT( xTimer );
xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+
+ traceRETURN_xTimerGetExpiryTime( xReturn );
+
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -517,10 +654,15 @@
BaseType_t xReturn;
Timer_t * pxTimer = xTimer;
+ traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer );
+
configASSERT( ppxTimerBuffer != NULL );
- if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0 )
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0U )
{
+ /* MISRA Ref 11.3.1 [Misaligned access] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
+ /* coverity[misra_c_2012_rule_11_3_violation] */
*ppxTimerBuffer = ( StaticTimer_t * ) pxTimer;
xReturn = pdTRUE;
}
@@ -529,16 +671,23 @@
xReturn = pdFALSE;
}
+ traceRETURN_xTimerGetStaticBuffer( xReturn );
+
return xReturn;
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
- const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const char * pcTimerGetName( TimerHandle_t xTimer )
{
Timer_t * pxTimer = xTimer;
+ traceENTER_pcTimerGetName( xTimer );
+
configASSERT( xTimer );
+
+ traceRETURN_pcTimerGetName( pxTimer->pcTimerName );
+
return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/
@@ -565,7 +714,10 @@
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
const TickType_t xTimeNow )
{
- Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ /* MISRA Ref 11.5.3 [Void pointer assignment] */
+ /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+ /* coverity[misra_c_2012_rule_11_5_violation] */
+ Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
/* Remove the timer from the list of active timers. A check has already
* been performed to ensure the list is not empty. */
@@ -574,7 +726,7 @@
/* If the timer is an auto-reload timer then calculate the next
* expiry time and re-insert the timer in the list of active timers. */
- if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
{
prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow );
}
@@ -607,7 +759,7 @@
}
#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
- for( ; ; )
+ for( ; configCONTROL_INFINITE_LOOP(); )
{
/* Query the timers list to see if it contains any timers, and if so,
* obtain the time at which the next timer will expire. */
@@ -669,7 +821,7 @@
* block time to expire. If a command arrived between the
* critical section being exited and this yield then the yield
* will not cause the task to block. */
- portYIELD_WITHIN_API();
+ taskYIELD_WITHIN_API();
}
else
{
@@ -715,7 +867,7 @@
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
TickType_t xTimeNow;
- PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+ PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U;
xTimeNow = xTaskGetTickCount();
@@ -749,7 +901,7 @@
{
/* Has the expiry time elapsed between the command to start/reset a
* timer was issued, and the time the command was processed? */
- if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks )
{
/* The time between a command being issued and the command being
* processed actually exceeds the timers period. */
@@ -781,12 +933,12 @@
static void prvProcessReceivedCommands( void )
{
- DaemonTaskMessage_t xMessage;
+ DaemonTaskMessage_t xMessage = { 0 };
Timer_t * pxTimer;
BaseType_t xTimerListsWereSwitched;
TickType_t xTimeNow;
- while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+ while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL )
{
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
{
@@ -818,110 +970,117 @@
* software timer. */
pxTimer = xMessage.u.xTimerParameters.pxTimer;
- if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+ if( pxTimer != NULL )
{
- /* The timer is in a list, remove it. */
- ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
+ {
+ /* The timer is in a list, remove it. */
+ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+ /* In this case the xTimerListsWereSwitched parameter is not used, but
+ * it must be present in the function call. prvSampleTimeNow() must be
+ * called after the message is received from xTimerQueue so there is no
+ * possibility of a higher priority task adding a message to the message
+ * queue with a time that is ahead of the timer daemon task (because it
+ * pre-empted the timer daemon task after the xTimeNow value was set). */
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+ switch( xMessage.xMessageID )
+ {
+ case tmrCOMMAND_START:
+ case tmrCOMMAND_START_FROM_ISR:
+ case tmrCOMMAND_RESET:
+ case tmrCOMMAND_RESET_FROM_ISR:
+ /* Start or restart a timer. */
+ pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
+
+ if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+ {
+ /* The timer expired before it was added to the active
+ * timer list. Process it now. */
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
+ {
+ prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
+ }
+ else
+ {
+ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+ }
+
+ /* Call the timer callback. */
+ traceTIMER_EXPIRED( pxTimer );
+ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ break;
+
+ case tmrCOMMAND_STOP:
+ case tmrCOMMAND_STOP_FROM_ISR:
+ /* The timer has already been removed from the active list. */
+ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+ break;
+
+ case tmrCOMMAND_CHANGE_PERIOD:
+ case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
+ pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
+ pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+ configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+ /* The new period does not really have a reference, and can
+ * be longer or shorter than the old one. The command time is
+ * therefore set to the current time, and as the period cannot
+ * be zero the next expiry time can only be in the future,
+ * meaning (unlike for the xTimerStart() case above) there is
+ * no fail case that needs to be handled here. */
+ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+ break;
+
+ case tmrCOMMAND_DELETE:
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* The timer has already been removed from the active list,
+ * just free up the memory if the memory was dynamically
+ * allocated. */
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+ {
+ vPortFree( pxTimer );
+ }
+ else
+ {
+ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+ }
+ }
+ #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ {
+ /* If dynamic allocation is not enabled, the memory
+ * could not have been dynamically allocated. So there is
+ * no need to free the memory - just mark the timer as
+ * "not active". */
+ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ break;
+
+ default:
+ /* Don't expect to get here. */
+ break;
+ }
}
else
{
mtCOVERAGE_TEST_MARKER();
}
-
- traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
-
- /* In this case the xTimerListsWereSwitched parameter is not used, but
- * it must be present in the function call. prvSampleTimeNow() must be
- * called after the message is received from xTimerQueue so there is no
- * possibility of a higher priority task adding a message to the message
- * queue with a time that is ahead of the timer daemon task (because it
- * pre-empted the timer daemon task after the xTimeNow value was set). */
- xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-
- switch( xMessage.xMessageID )
- {
- case tmrCOMMAND_START:
- case tmrCOMMAND_START_FROM_ISR:
- case tmrCOMMAND_RESET:
- case tmrCOMMAND_RESET_FROM_ISR:
- /* Start or restart a timer. */
- pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
-
- if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
- {
- /* The timer expired before it was added to the active
- * timer list. Process it now. */
- if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
- {
- prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
- }
- else
- {
- pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
- }
-
- /* Call the timer callback. */
- traceTIMER_EXPIRED( pxTimer );
- pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- break;
-
- case tmrCOMMAND_STOP:
- case tmrCOMMAND_STOP_FROM_ISR:
- /* The timer has already been removed from the active list. */
- pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
- break;
-
- case tmrCOMMAND_CHANGE_PERIOD:
- case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
- pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
- pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
- configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
-
- /* The new period does not really have a reference, and can
- * be longer or shorter than the old one. The command time is
- * therefore set to the current time, and as the period cannot
- * be zero the next expiry time can only be in the future,
- * meaning (unlike for the xTimerStart() case above) there is
- * no fail case that needs to be handled here. */
- ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
- break;
-
- case tmrCOMMAND_DELETE:
- #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- /* The timer has already been removed from the active list,
- * just free up the memory if the memory was dynamically
- * allocated. */
- if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
- {
- vPortFree( pxTimer );
- }
- else
- {
- pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
- }
- }
- #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
- {
- /* If dynamic allocation is not enabled, the memory
- * could not have been dynamically allocated. So there is
- * no need to free the memory - just mark the timer as
- * "not active". */
- pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
- }
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
- break;
-
- default:
- /* Don't expect to get here. */
- break;
- }
}
}
}
@@ -970,14 +1129,14 @@
{
/* The timer queue is allocated statically in case
* configSUPPORT_DYNAMIC_ALLOCATION is 0. */
- PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
- PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+ PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;
+ PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ];
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
}
#else
{
- xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+ xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ) );
}
#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
@@ -1008,12 +1167,14 @@
BaseType_t xReturn;
Timer_t * pxTimer = xTimer;
+ traceENTER_xTimerIsTimerActive( xTimer );
+
configASSERT( xTimer );
/* Is the timer in the list of active timers? */
- taskENTER_CRITICAL();
+ portBASE_TYPE_ENTER_CRITICAL();
{
- if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0U )
{
xReturn = pdFALSE;
}
@@ -1022,10 +1183,12 @@
xReturn = pdTRUE;
}
}
- taskEXIT_CRITICAL();
+ portBASE_TYPE_EXIT_CRITICAL();
+
+ traceRETURN_xTimerIsTimerActive( xReturn );
return xReturn;
- } /*lint !e818 Can't be pointer to const due to the typedef. */
+ }
/*-----------------------------------------------------------*/
void * pvTimerGetTimerID( const TimerHandle_t xTimer )
@@ -1033,6 +1196,8 @@
Timer_t * const pxTimer = xTimer;
void * pvReturn;
+ traceENTER_pvTimerGetTimerID( xTimer );
+
configASSERT( xTimer );
taskENTER_CRITICAL();
@@ -1041,6 +1206,8 @@
}
taskEXIT_CRITICAL();
+ traceRETURN_pvTimerGetTimerID( pvReturn );
+
return pvReturn;
}
/*-----------------------------------------------------------*/
@@ -1050,6 +1217,8 @@
{
Timer_t * const pxTimer = xTimer;
+ traceENTER_vTimerSetTimerID( xTimer, pvNewID );
+
configASSERT( xTimer );
taskENTER_CRITICAL();
@@ -1057,6 +1226,8 @@
pxTimer->pvTimerID = pvNewID;
}
taskEXIT_CRITICAL();
+
+ traceRETURN_vTimerSetTimerID();
}
/*-----------------------------------------------------------*/
@@ -1070,6 +1241,8 @@
DaemonTaskMessage_t xMessage;
BaseType_t xReturn;
+ traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken );
+
/* Complete the message with the function parameters and post it to the
* daemon task. */
xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
@@ -1080,6 +1253,7 @@
xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+ traceRETURN_xTimerPendFunctionCallFromISR( xReturn );
return xReturn;
}
@@ -1097,6 +1271,8 @@
DaemonTaskMessage_t xMessage;
BaseType_t xReturn;
+ traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
+
/* This function can only be called after a timer has been created or
* after the scheduler has been started because, until then, the timer
* queue does not exist. */
@@ -1112,6 +1288,7 @@
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+ traceRETURN_xTimerPendFunctionCall( xReturn );
return xReturn;
}
@@ -1123,6 +1300,10 @@
UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
{
+ traceENTER_uxTimerGetTimerNumber( xTimer );
+
+ traceRETURN_uxTimerGetTimerNumber( ( ( Timer_t * ) xTimer )->uxTimerNumber );
+
return ( ( Timer_t * ) xTimer )->uxTimerNumber;
}
@@ -1134,12 +1315,28 @@
void vTimerSetTimerNumber( TimerHandle_t xTimer,
UBaseType_t uxTimerNumber )
{
+ traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber );
+
( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+
+ traceRETURN_vTimerSetTimerNumber();
}
#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/
+/*
+ * Reset the state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+ void vTimerResetState( void )
+ {
+ xTimerQueue = NULL;
+ xTimerTaskHandle = NULL;
+ }
+/*-----------------------------------------------------------*/
+
/* This entire source file will be skipped if the application is not configured
* to include software timer functionality. If you want to include software timer
* functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
