Release v10.5.1_20230818
diff --git a/LICENSE.md b/LICENSE.md
index 975f524..e2657f3 100644
--- a/LICENSE.md
+++ b/LICENSE.md
@@ -1,3 +1,19 @@
# MIT License
-This software component is under the **MIT open source** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/MIT).
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
\ No newline at end of file
diff --git a/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Source/CMSIS_RTOS_V2/cmsis_os2.c
index 2d1d0fc..bfb3223 100644
--- a/Source/CMSIS_RTOS_V2/cmsis_os2.c
+++ b/Source/CMSIS_RTOS_V2/cmsis_os2.c
@@ -1,5 +1,5 @@
/* --------------------------------------------------------------------------
- * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -99,6 +99,15 @@
/* Kernel initialization state */
static osKernelState_t KernelState = osKernelInactive;
+/* Get OS Tick count value */
+static uint32_t OS_Tick_GetCount (void);
+#if (configUSE_TICKLESS_IDLE == 0)
+/* Get OS Tick overflow status */
+static uint32_t OS_Tick_GetOverflow (void);
+#endif
+/* Get OS Tick interval */
+static uint32_t OS_Tick_GetInterval (void);
+
/*
Heap region definition used by heap_5 variant
@@ -118,7 +127,7 @@
HeapRegion_t array.
*/
#define HEAP_5_REGION_SETUP 1
-
+
#ifndef configHEAP_5_REGIONS
#define configHEAP_5_REGIONS xHeapRegions
@@ -152,15 +161,19 @@
/*
SysTick handler implementation that also clears overflow flag.
*/
+#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
+#if (configUSE_TICKLESS_IDLE == 0)
/* Clear overflow flag */
SysTick->CTRL;
+#endif
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
/* Call tick handler */
xPortSysTickHandler();
}
}
+#endif
#endif /* SysTick */
/*
@@ -168,9 +181,9 @@
*/
__STATIC_INLINE void SVC_Setup (void) {
#if (__ARM_ARCH_7A__ == 0U)
- /* Service Call interrupt might be configured before kernel start */
- /* and when its priority is lower or equal to BASEPRI, svc intruction */
- /* causes a Hard Fault. */
+ /* Service Call interrupt might be configured before kernel start */
+ /* and when its priority is lower or equal to BASEPRI, svc instruction */
+ /* causes a Hard Fault. */
NVIC_SetPriority (SVCall_IRQn, 0U);
#endif
}
@@ -213,11 +226,22 @@
}
/* Get OS Tick count value */
-static uint32_t OS_Tick_GetCount (void);
+static uint32_t OS_Tick_GetCount (void) {
+ uint32_t load = SysTick->LOAD;
+ return (load - SysTick->VAL);
+}
+
+#if (configUSE_TICKLESS_IDLE == 0)
/* Get OS Tick overflow status */
-static uint32_t OS_Tick_GetOverflow (void);
+static uint32_t OS_Tick_GetOverflow (void) {
+ return ((SysTick->CTRL >> 16) & 1U);
+}
+#endif
+
/* Get OS Tick interval */
-static uint32_t OS_Tick_GetInterval (void);
+static uint32_t OS_Tick_GetInterval (void) {
+ return (SysTick->LOAD + 1U);
+}
/* ==== Kernel Management Functions ==== */
@@ -464,26 +488,10 @@
return (ticks);
}
-/* Get OS Tick count value */
-static uint32_t OS_Tick_GetCount (void) {
- uint32_t load = SysTick->LOAD;
- return (load - SysTick->VAL);
-}
-
-/* Get OS Tick overflow status */
-static uint32_t OS_Tick_GetOverflow (void) {
- return ((SysTick->CTRL >> 16) & 1U);
-}
-
-/* Get OS Tick interval */
-static uint32_t OS_Tick_GetInterval (void) {
- return (SysTick->LOAD + 1U);
-}
-
/*
Get the RTOS kernel tick frequency.
*/
- uint32_t osKernelGetTickFreq (void) {
+uint32_t osKernelGetTickFreq (void) {
/* Return frequency in hertz */
return (configTICK_RATE_HZ);
}
@@ -495,6 +503,17 @@
uint32_t irqmask = IS_IRQ_MASKED();
TickType_t ticks;
uint32_t val;
+#if (configUSE_TICKLESS_IDLE != 0)
+ uint32_t val0;
+
+ /* Low Power Tickless Idle controls timer overflow flag and therefore */
+ /* OS_Tick_GetOverflow may be non-functional. As a workaround a reference */
+ /* time is measured here before disabling interrupts. Timer value overflow */
+ /* is then checked by comparing reference against latest time measurement. */
+ /* Timer count value returned by this method is less accurate but if an */
+ /* overflow is missed, an invalid timer count would be returned. */
+ val0 = OS_Tick_GetCount();
+#endif
__disable_irq();
@@ -502,10 +521,17 @@
val = OS_Tick_GetCount();
/* Update tick count and timer value when timer overflows */
+#if (configUSE_TICKLESS_IDLE != 0)
+ if (val < val0) {
+ ticks++;
+ }
+#else
if (OS_Tick_GetOverflow() != 0U) {
val = OS_Tick_GetCount();
ticks++;
}
+#endif
+
val += ticks * OS_Tick_GetInterval();
if (irqmask == 0U) {
@@ -652,7 +678,7 @@
case eReady: state = osThreadReady; break;
case eBlocked:
case eSuspended: state = osThreadBlocked; break;
- case eDeleted: state = osThreadTerminated; break;
+ case eDeleted:
case eInvalid:
default: state = osThreadError; break;
}
@@ -1257,7 +1283,7 @@
if (IRQ_Context() != 0U) {
stat = osErrorISR;
}
- else if (hTimer == NULL) {
+ else if ((hTimer == NULL) || (ticks == 0U)) {
stat = osErrorParameter;
}
else {
@@ -1442,7 +1468,9 @@
if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) {
rflags = (uint32_t)osErrorResource;
} else {
- rflags = flags;
+ /* Retrieve bits that are already set and add flags to be set in current call */
+ rflags = xEventGroupGetBitsFromISR (hEventGroup);
+ rflags |= flags;
portYIELD_FROM_ISR (yield);
}
#endif
@@ -1535,7 +1563,13 @@
rflags = (uint32_t)osErrorParameter;
}
else if (IRQ_Context() != 0U) {
- rflags = (uint32_t)osErrorISR;
+ if (timeout == 0U) {
+ /* Try semantic is not supported */
+ rflags = (uint32_t)osErrorISR;
+ } else {
+ /* Calling osEventFlagsWait from ISR with non-zero timeout is invalid */
+ rflags = (uint32_t)osFlagsErrorParameter;
+ }
}
else {
if (options & osFlagsWaitAll) {
@@ -1901,7 +1935,7 @@
#endif
}
}
-
+
#if (configQUEUE_REGISTRY_SIZE > 0)
if (hSemaphore != NULL) {
if ((attr != NULL) && (attr->name != NULL)) {
diff --git a/Source/History.txt b/Source/History.txt
index 3453854..30d2610 100644
--- a/Source/History.txt
+++ b/Source/History.txt
@@ -1,5 +1,154 @@
Documentation and download available at https://www.FreeRTOS.org/
+Changes between FreeRTOS V10.5.0 and FreeRTOS V10.5.1 released November 16 2022
+
+ + Updating the version in the manifest.yml file to be accurate.
+
+Changes between FreeRTOS V10.4.6 and FreeRTOS V10.5.0 released September 16 2022
+
+ + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
+ already independently gained the ability to execute injected code to
+ read from or write to arbitrary addresses by passing a negative argument
+ as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or
+ vTaskSetThreadLocalStoragePointer respectively. A check has been added to
+ ensure that passing a negative argument as the xIndex parameter does not
+ cause arbitrary read or write.
+ We thank Certibit Consulting, LLC for reporting this issue.
+ + ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task
+ to invoke any function with privilege by passing it as a parameter to
+ MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate,
+ MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTaskCreate
+ and MPU_xTaskCreateStatic have been updated to only allow creation of
+ unprivileged tasks. MPU_xTimerCreate, MPU_xTimerCreateStatic and
+ MPU_xTimerPendFunctionCall APIs have been removed.
+ We thank Huazhong University of Science and Technology for reporting
+ this issue.
+ + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
+ already independently gained the ability to execute injected code to
+ achieve further privilege escalation by branching directly inside a
+ FreeRTOS MPU API wrapper function with a manually crafted stack frame.
+ The local stack variable `xRunningPrivileged` has been removed so that
+ a manually crafted stack frame cannot be used for privilege escalation
+ by branching directly inside a FreeRTOS MPU API wrapper.
+ We thank Certibit Consulting, LLC, Huazhong University of Science and
+ Technology and the SecLab team at Northeastern University for reporting
+ this issue.
+ + ARMv7-M MPU ports: It was possible to configure overlapping memory
+ protection unit (MPU) regions such that an unprivileged task could access
+ privileged data. The kernel now uses highest numbered MPU regions for
+ kernel protections to prevent such MPU configurations.
+ We thank the SecLab team at Northeastern University for reporting this
+ issue.
+ + Add support for ARM Cortex-M55.
+ + Add support for ARM Cortex-M85. Contributed by @gbrtth.
+ + Add vectored mode interrupt support to the RISC-V port.
+ + Add support for RV32E extension (Embedded Profile) in RISC-V GCC port.
+ Contributed by @Limoto.
+ + Heap improvements:
+ - Add a check to heap_2 to track if a memory block is allocated to
+ the application or not. The MSB of the size field is used for this
+ purpose. The same check already exists in heap_4 and heap_5. This
+ check prevents double free errors.
+ - Add a new flag configHEAP_CLEAR_MEMORY_ON_FREE to heap_2, heap_4
+ and heap_5. If the flag is set in FreeRTOSConfig.h then memory freed using
+ vPortFree() is automatically cleared to zero.
+ - Add a new API pvPortCalloc to heap_2, heap_4 and heap_5 which has the same
+ signature as the standard library calloc function.
+ - Update the pointer types to portPOINTER_SIZE_TYPE. Contributed by
+ @Octaviarius.
+ + Add the ability to override send and receive completed callbacks for each
+ instance of a stream buffer or message buffer. Earlier there could be
+ one send and one receive callback for all instances of stream and message
+ buffers. Having separate callbacks per instance allows different message
+ and stream buffers to be used differently - for example, some for inter core
+ communication and others for same core communication.
+ The feature can be controlled by setting the configuration option
+ configUSE_SB_COMPLETED_CALLBACK in FreeRTOSConfig.h. When the option is set to 1,
+ APIs xStreamBufferCreateWithCallback() or xStreamBufferCreateStaticWithCallback()
+ (and likewise APIs for message buffer) can be used to create a stream buffer
+ or message buffer instance with application provided callback overrides. When
+ the option is set to 0, then the default callbacks as defined by
+ sbSEND_COMPLETED() and sbRECEIVE_COMPLETED() macros are invoked. To maintain
+ backwards compatibility, configUSE_SB_COMPLETED_CALLBACK defaults to 0. The
+ functionality is currently not supported for MPU enabled ports.
+ + Generalize the FreeRTOS's Thread Local Storage (TLS) support so that it
+ is not tied to newlib and can be used with other c-runtime libraries also.
+ The default behavior for newlib support is kept same for backward
+ compatibility.
+ + Add support to build and link FreeRTOS using CMake build system. Contributed
+ by @yhsb2k.
+ + Add support to generate Software Bill of Materials (SBOM) for every release.
+ + Add support for 16 MPU regions to the GCC Cortex-M33 ports.
+ + Add ARM Cortex-M7 r0p0/r0p1 Errata 837070 workaround to ARM CM4 MPU ports.
+ The application writer needs to define configENABLE_ERRATA_837070_WORKAROUND
+ when using CM4 MPU ports on a Cortex-M7 r0p0/r0p1 core.
+ + Add configSYSTICK_CLOCK_HZ to Cortex-M0 ports. This is needed to support
+ the case when the SysTick timer is not clocked from the same source as the CPU.
+ + Add hardware stack protection support to MicroBlazeV9 port. This ensures that
+ the CPU immediately raises Stack Protection Violation exception as soon as any
+ task violates its stack limits. Contributed by @uecasm.
+ + Introduce the configUSE_MINI_LIST_ITEM configuration option. When this
+ option is set to 1, ListItem_t and MiniLitItem_t remain separate types.
+ However, when configUSE_MINI_LIST_ITEM == 0, MiniLitItem_t and ListItem_t
+ are both typedefs of the same struct xLIST_ITEM. This addresses some issues
+ observed when strict-aliasing and link time optimization are enabled.
+ To maintain backwards compatibility, configUSE_MINI_LIST_ITEM defaults to 1.
+ + Simplify prvInitialiseNewTask to memset newly allocated TCB structures
+ to zero, and remove code that set individual structure members to zero.
+ + Add prototype for prvPortYieldFromISR to the POSIX port so that it builds
+ without any warning with -Wmissing-prototypes compiler option.
+ + Add top of stack and end of stack to the task info report obtained using
+ vTaskGetInfo(). Contributed by @shreyasbharath.
+ + Add a cap to the cRxLock and cTxLock members of the queue data structure.
+ These locks count the number items received and sent to the queue while
+ the queue was locked. These are later used to unblock tasks waiting on
+ the queue when the queue is unlocked. This PR caps the values of the
+ cRxLock and cTxLock to the number of tasks in the system because we cannot
+ unblock more tasks than there are in the system. Note that the same assert
+ could still be triggered is the application creates more than 127 tasks.
+ + Changed uxAutoReload parameter in timer functions to xAutoReload. The
+ type is now BaseType_t. This matches the type of pdTRUE and pdFALSE.
+ The new function xTimerGetAutoReload() provides the auto-reload state as
+ a BaseType_t. The legacy function uxTimerGetAutoReload is retained with the
+ original UBaseType_t return value.
+ + Fix support for user implementations of tickless idle that call
+ vTaskStepTick() with xExpectedIdleTime ticks to step. The new code
+ ensures xTickCount reaches xNextTaskUnblockTime inside xTaskIncrementTick()
+ instead of inside vTaskStepTick(). This fixes the typical case where a task
+ wakes up one tick late and a rare case assertion failure when xTickCount\
+ rolls over. Contributed by @jefftenney.
+ + Fix deadlock in event groups when pvPortMalloc and vPortFree functions
+ are protected with a mutex. Contributed by @clemenskresser.
+ + Fix a warning in tasks.c when compiled with -Wduplicated-branches
+ GCC option. Contributed by @pierrenoel-bouteville-act.
+ + Fix compilation error in tasks.c when configSUPPORT_DYNAMIC_ALLOCATION
+ is set to zero. Contributed by @rdpoor.
+ + Fix prvWriteMessageToBuffer() function in stream_buffer.c so that it correctly
+ copies length on big endian platforms too.
+ + Remove the need for INCLUDE_vTaskSuspend to be set to 1
+ when configUSE_TICKLESS_IDLE is enabled. Contributed by @pramithkv.
+ + Update the RL78 IAR port to the latest version of IAR which uses the
+ industry standard ELF format as opposed to earlier UBROF object format.
+ Contributed by @felipe-iar.
+ + Add tick type is atomic flag when tick count is 16-bit to PIC24 port. This
+ allows the PIC24 family of 16 bit processors to read the tick count without
+ a critical section when the tick count is also 16 bits.
+ + Fix offset-out-of-range errors for GCC CM3/CM4 mpu ports when
+ Link Time Optimization is enabled. Contributed by @niniemann.
+ + Remove #error when RISC-V port is compiled on a 64-bit RISC-V platform.
+ Contributed by @cmdrf.
+ + Fix ullPortInterruptNesting alignment in Cortex-A53 port so that it is
+ 8-byte aligned. This fixes the unaligned access exception. Contributed
+ by @Atomar25.
+ + Fix Interrupt Handler Register Function and Exception Process in NiosII
+ Port. Contributed by @ghost.
+ + Change FreeRTOS IRQ Handler for Cortex-A53 SRE port to store and restore
+ interrupt acknowledge register. This ensures that the SRE port behavior
+ matches the Memory Mapped IO port. Contributed by @sviaunxp.
+ + Update the uncrustify config file to match the version of the uncrustify
+ used in the CI Action. Also, pin the version of uncrustify in CI. Contributed
+ by @swaldhoer.
+
Changes between FreeRTOS V10.4.5 and FreeRTOS V10.4.6 released November 12 2021
+ ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the
@@ -27,7 +176,7 @@
configIDLE_SHOULD_YIELD is set to 0.
+ ARMv8-M secure-side port: Tasks that call secure functions from the
non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two
- contexts – one on the non-secure side and one on the secure-side. Previous
+ contexts - one on the non-secure side and one on the secure-side. Previous
versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures
that reference secure-side contexts at run time. Now the structures are
allocated statically at compile time. The change necessitates the
@@ -39,43 +188,43 @@
this change.
Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021
- + Minor performance improvements to xTaskIncrementTick() achieved by providing
- macro versions of uxListRemove() and vListInsertEnd().
- + Minor refactor of timers.c that obsoletes the need for the
- tmrCOMMAND_START_DONT_TRACE macro and removes the need for timers.c to
- post to its own event queue. A consequence of this change is that auto-
- reload timers that miss their intended next execution time will execute
- again immediately rather than executing again the next time the command
- queue is processed. (thanks Jeff Tenney).
- + Fix a race condition in the message buffer implementation. The
- underlying cause was that length and data bytes are written and read as
- two distinct operations, which both modify the size of the buffer. If a
- context switch occurs after adding or removing the length bytes, but
- before adding or removing the data bytes, then another task may observe
- the message buffer in an invalid state.
- + The xTaskCreate() and xTaskCreateStatic() functions accept a task priority
- as an input parameter. The priority has always been silently capped to
- (configMAX_PRIORITIES - 1) should it be set to a value above that priority.
- Now values above that priority will also trigger a configASSERT() failure.
+ + Minor performance improvements to xTaskIncrementTick() achieved by providing
+ macro versions of uxListRemove() and vListInsertEnd().
+ + Minor refactor of timers.c that obsoletes the need for the
+ tmrCOMMAND_START_DONT_TRACE macro and removes the need for timers.c to
+ post to its own event queue. A consequence of this change is that auto-
+ reload timers that miss their intended next execution time will execute
+ again immediately rather than executing again the next time the command
+ queue is processed. (thanks Jeff Tenney).
+ + Fix a race condition in the message buffer implementation. The
+ underlying cause was that length and data bytes are written and read as
+ two distinct operations, which both modify the size of the buffer. If a
+ context switch occurs after adding or removing the length bytes, but
+ before adding or removing the data bytes, then another task may observe
+ the message buffer in an invalid state.
+ + The xTaskCreate() and xTaskCreateStatic() functions accept a task priority
+ as an input parameter. The priority has always been silently capped to
+ (configMAX_PRIORITIES - 1) should it be set to a value above that priority.
+ Now values above that priority will also trigger a configASSERT() failure.
+ Replace configASSERT( pcQueueName ) in vQueueAddToRegistry with a NULL
- pointer check.
- + Introduce the configSTACK_ALLOCATION_FROM_SEPARATE_HEAP configuration
- constant that enables the stack allocated to tasks to come from a heap other
- than the heap used by other memory allocations. This enables stacks to be
- placed within special regions, such as fast tightly coupled memory.
- + If there is an attempt to add the same queue or semaphore handle to the
- queue registry more than once then prior versions would create two separate
- entries. Now if this is done the first entry is overwritten rather than
- duplicated.
- + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from
- their respective repositories.
- + Correct a build error in the POSIX port.
- + Additional minor formatting updates, including replacing tabs with spaces
- in more files.
- + Other minor updates include adding additional configASSERT() checks and
- correcting and improving code comments.
- + Go look at the smp branch to see the progress towards the Symetric
- Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp
+ pointer check.
+ + Introduce the configSTACK_ALLOCATION_FROM_SEPARATE_HEAP configuration
+ constant that enables the stack allocated to tasks to come from a heap other
+ than the heap used by other memory allocations. This enables stacks to be
+ placed within special regions, such as fast tightly coupled memory.
+ + If there is an attempt to add the same queue or semaphore handle to the
+ queue registry more than once then prior versions would create two separate
+ entries. Now if this is done the first entry is overwritten rather than
+ duplicated.
+ + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from
+ their respective repositories.
+ + Correct a build error in the POSIX port.
+ + Additional minor formatting updates, including replacing tabs with spaces
+ in more files.
+ + Other minor updates include adding additional configASSERT() checks and
+ correcting and improving code comments.
+ + Go look at the smp branch to see the progress towards the Symetric
+ Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp
Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
diff --git a/Source/croutine.c b/Source/croutine.c
index d9bce9b..aa5ea6f 100644
--- a/Source/croutine.c
+++ b/Source/croutine.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -65,13 +65,13 @@
* This macro accesses the co-routine ready lists and therefore must not be
* used from within an ISR.
*/
- #define prvAddCoRoutineToReadyQueue( pxCRCB ) \
- { \
- if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \
- { \
- uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \
- } \
- vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \
+ #define prvAddCoRoutineToReadyQueue( pxCRCB ) \
+ { \
+ if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority ) \
+ { \
+ uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority; \
+ } \
+ vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \
}
/*
diff --git a/Source/event_groups.c b/Source/event_groups.c
index 93d9d0d..f3e6aff 100644
--- a/Source/event_groups.c
+++ b/Source/event_groups.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -101,13 +101,13 @@
configASSERT( pxEventGroupBuffer );
#if ( configASSERT_DEFINED == 1 )
- {
- /* Sanity check that the size of the structure used to declare a
- * variable of type StaticEventGroup_t equals the size of the real
- * event group structure. */
- volatile size_t xSize = sizeof( StaticEventGroup_t );
- configASSERT( xSize == sizeof( EventGroup_t ) );
- } /*lint !e529 xSize is referenced if configASSERT() is defined. */
+ {
+ /* Sanity check that the size of the structure used to declare a
+ * variable of type StaticEventGroup_t equals the size of the real
+ * event group structure. */
+ volatile size_t xSize = sizeof( StaticEventGroup_t );
+ configASSERT( xSize == sizeof( EventGroup_t ) );
+ } /*lint !e529 xSize is referenced if configASSERT() is defined. */
#endif /* configASSERT_DEFINED */
/* The user has provided a statically allocated event group - use it. */
@@ -119,12 +119,12 @@
vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- /* Both static and dynamic allocation can be used, so note that
- * this event group was created statically in case the event group
- * is later deleted. */
- pxEventBits->ucStaticallyAllocated = pdTRUE;
- }
+ {
+ /* Both static and dynamic allocation can be used, so note that
+ * this event group was created statically in case the event group
+ * is later deleted. */
+ pxEventBits->ucStaticallyAllocated = pdTRUE;
+ }
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
traceEVENT_GROUP_CREATE( pxEventBits );
@@ -170,12 +170,12 @@
vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- /* Both static and dynamic allocation can be used, so note this
- * event group was allocated statically in case the event group is
- * later deleted. */
- pxEventBits->ucStaticallyAllocated = pdFALSE;
- }
+ {
+ /* Both static and dynamic allocation can be used, so note this
+ * event group was allocated statically in case the event group is
+ * later deleted. */
+ pxEventBits->ucStaticallyAllocated = pdFALSE;
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
traceEVENT_GROUP_CREATE( pxEventBits );
@@ -204,9 +204,9 @@
configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
configASSERT( uxBitsToWaitFor != 0 );
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
#endif
vTaskSuspendAll();
@@ -331,9 +331,9 @@
configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
configASSERT( uxBitsToWaitFor != 0 );
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
#endif
vTaskSuspendAll();
@@ -533,7 +533,8 @@
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
const EventBits_t uxBitsToSet )
{
- ListItem_t * pxListItem, * pxNext;
+ ListItem_t * pxListItem;
+ ListItem_t * pxNext;
ListItem_t const * pxListEnd;
List_t const * pxList;
EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
@@ -645,29 +646,29 @@
configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
}
-
- #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
- {
- /* The event group can only have been allocated dynamically - free
- * it again. */
- vPortFree( pxEventBits );
- }
- #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
- {
- /* The event group could have been allocated statically or
- * dynamically, so check before attempting to free the memory. */
- if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
- {
- vPortFree( pxEventBits );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
( void ) xTaskResumeAll();
+
+ #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+ {
+ /* The event group can only have been allocated dynamically - free
+ * it again. */
+ vPortFree( pxEventBits );
+ }
+ #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ {
+ /* The event group could have been allocated statically or
+ * dynamically, so check before attempting to free the memory. */
+ if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+ {
+ vPortFree( pxEventBits );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
/*-----------------------------------------------------------*/
diff --git a/Source/include/FreeRTOS.h b/Source/include/FreeRTOS.h
index 383f04a..d829d44 100644
--- a/Source/include/FreeRTOS.h
+++ b/Source/include/FreeRTOS.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -71,9 +71,60 @@
/* Required if struct _reent is used. */
#if ( configUSE_NEWLIB_REENTRANT == 1 )
+
+/* Note Newlib support has been included by popular demand, but is not
+ * used by the FreeRTOS maintainers themselves. FreeRTOS is not
+ * responsible for resulting newlib operation. User must be familiar with
+ * newlib and must provide system-wide implementations of the necessary
+ * stubs. Be warned that (at the time of writing) the current newlib design
+ * implements a system-wide malloc() that must be provided with locks.
+ *
+ * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+ * for additional information. */
#include <reent.h>
+
+ #define configUSE_C_RUNTIME_TLS_SUPPORT 1
+
+ #ifndef configTLS_BLOCK_TYPE
+ #define configTLS_BLOCK_TYPE struct _reent
+ #endif
+
+ #ifndef configINIT_TLS_BLOCK
+ #define configINIT_TLS_BLOCK( xTLSBlock ) _REENT_INIT_PTR( &( xTLSBlock ) )
+ #endif
+
+ #ifndef configSET_TLS_BLOCK
+ #define configSET_TLS_BLOCK( xTLSBlock ) _impure_ptr = &( xTLSBlock )
+ #endif
+
+ #ifndef configDEINIT_TLS_BLOCK
+ #define configDEINIT_TLS_BLOCK( xTLSBlock ) _reclaim_reent( &( xTLSBlock ) )
+ #endif
+#endif /* if ( configUSE_NEWLIB_REENTRANT == 1 ) */
+
+#ifndef configUSE_C_RUNTIME_TLS_SUPPORT
+ #define configUSE_C_RUNTIME_TLS_SUPPORT 0
#endif
+#if ( ( configUSE_NEWLIB_REENTRANT == 0 ) && ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )
+
+ #ifndef configTLS_BLOCK_TYPE
+ #error Missing definition: configTLS_BLOCK_TYPE must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+ #endif
+
+ #ifndef configINIT_TLS_BLOCK
+ #error Missing definition: configINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+ #endif
+
+ #ifndef configSET_TLS_BLOCK
+ #error Missing definition: configSET_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+ #endif
+
+ #ifndef configDEINIT_TLS_BLOCK
+ #error Missing definition: configDEINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
+ #endif
+#endif /* if ( ( configUSE_NEWLIB_REENTRANT == 0 ) && ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) ) */
+
/*
* Check all the required application specific macros have been defined.
* These macros are application specific and (as downloaded) are defined
@@ -203,7 +254,7 @@
#endif
#ifndef INCLUDE_xTaskGetCurrentTaskHandle
- #define INCLUDE_xTaskGetCurrentTaskHandle 0
+ #define INCLUDE_xTaskGetCurrentTaskHandle 1
#endif
#if configUSE_CO_ROUTINES != 0
@@ -309,11 +360,11 @@
#endif
#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) ( uxSavedStatusValue )
#endif
#ifndef portCLEAN_UP_TCB
- #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+ #define portCLEAN_UP_TCB( pxTCB ) ( void ) ( pxTCB )
#endif
#ifndef portPRE_TASK_DELETE_HOOK
@@ -321,7 +372,7 @@
#endif
#ifndef portSETUP_TCB
- #define portSETUP_TCB( pxTCB ) ( void ) pxTCB
+ #define portSETUP_TCB( pxTCB ) ( void ) ( pxTCB )
#endif
#ifndef configQUEUE_REGISTRY_SIZE
@@ -334,6 +385,10 @@
#define pcQueueGetName( xQueue )
#endif
+#ifndef configUSE_MINI_LIST_ITEM
+ #define configUSE_MINI_LIST_ITEM 1
+#endif
+
#ifndef portPOINTER_SIZE_TYPE
#define portPOINTER_SIZE_TYPE uint32_t
#endif
@@ -629,7 +684,7 @@
#endif
#ifndef traceEVENT_GROUP_SYNC_END
- #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+ #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) ( xTimeoutOccurred )
#endif
#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
@@ -637,7 +692,7 @@
#endif
#ifndef traceEVENT_GROUP_WAIT_BITS_END
- #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+ #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) ( xTimeoutOccurred )
#endif
#ifndef traceEVENT_GROUP_CLEAR_BITS
@@ -886,6 +941,12 @@
#define configUSE_POSIX_ERRNO 0
#endif
+#ifndef configUSE_SB_COMPLETED_CALLBACK
+
+/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */
+ #define configUSE_SB_COMPLETED_CALLBACK 0
+#endif
+
#ifndef portTICK_TYPE_IS_ATOMIC
#define portTICK_TYPE_IS_ATOMIC 0
#endif
@@ -900,6 +961,16 @@
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#endif
+#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) )
+ #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1.
+#endif
+
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
+ #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) )
+ #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1. Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h.
+ #endif
+#endif
+
#ifndef configSTACK_DEPTH_TYPE
/* Defaults to uint16_t for backward compatibility, but can be overridden
@@ -924,12 +995,6 @@
#endif
/* Sanity check the configuration. */
-#if ( configUSE_TICKLESS_IDLE != 0 )
- #if ( INCLUDE_vTaskSuspend != 1 )
- #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
- #endif /* INCLUDE_vTaskSuspend */
-#endif /* configUSE_TICKLESS_IDLE */
-
#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
#endif
@@ -958,7 +1023,7 @@
#define portTICK_TYPE_ENTER_CRITICAL()
#define portTICK_TYPE_EXIT_CRITICAL()
#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
- #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x
+ #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) ( x )
#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */
/* Definitions to allow backward compatibility with FreeRTOS versions prior to
@@ -1054,6 +1119,12 @@
#define configENABLE_FPU 1
#endif
+/* Set configENABLE_MVE to 1 to enable MVE support and 0 to disable it. This is
+ * currently used in ARMv8M ports. */
+#ifndef configENABLE_MVE
+ #define configENABLE_MVE 0
+#endif
+
/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
* This is currently used in ARMv8M ports. */
#ifndef configENABLE_TRUSTZONE
@@ -1140,16 +1211,20 @@
};
typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
-/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
-struct xSTATIC_MINI_LIST_ITEM
-{
- #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
- TickType_t xDummy1;
- #endif
- TickType_t xDummy2;
- void * pvDummy3[ 2 ];
-};
-typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+#if ( configUSE_MINI_LIST_ITEM == 1 )
+ /* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+ struct xSTATIC_MINI_LIST_ITEM
+ {
+ #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy1;
+ #endif
+ TickType_t xDummy2;
+ void * pvDummy3[ 2 ];
+ };
+ typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+#else /* if ( configUSE_MINI_LIST_ITEM == 1 ) */
+ typedef struct xSTATIC_LIST_ITEM StaticMiniListItem_t;
+#endif /* if ( configUSE_MINI_LIST_ITEM == 1 ) */
/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
typedef struct xSTATIC_LIST
@@ -1209,8 +1284,8 @@
#if ( configGENERATE_RUN_TIME_STATS == 1 )
configRUN_TIME_COUNTER_TYPE ulDummy16;
#endif
- #if ( configUSE_NEWLIB_REENTRANT == 1 )
- struct _reent xDummy17;
+ #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )
+ configTLS_BLOCK_TYPE xDummy17;
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
@@ -1348,6 +1423,9 @@
#if ( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxDummy4;
#endif
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ void * pvDummy5[ 2 ];
+ #endif
} StaticStreamBuffer_t;
/* Message buffers are built on stream buffers. */
diff --git a/Source/include/StackMacros.h b/Source/include/StackMacros.h
index 6ddeb3a..099ac0c 100644
--- a/Source/include/StackMacros.h
+++ b/Source/include/StackMacros.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -28,7 +28,7 @@
#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
- #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released.
+ #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in a future release.
#endif
#include "stack_macros.h"
diff --git a/Source/include/atomic.h b/Source/include/atomic.h
index 8d7c107..8e356e1 100644
--- a/Source/include/atomic.h
+++ b/Source/include/atomic.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/include/croutine.h b/Source/include/croutine.h
index 51bdd4f..48e6f03 100644
--- a/Source/include/croutine.h
+++ b/Source/include/croutine.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/include/deprecated_definitions.h b/Source/include/deprecated_definitions.h
index a833141..1cb9372 100644
--- a/Source/include/deprecated_definitions.h
+++ b/Source/include/deprecated_definitions.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/include/event_groups.h b/Source/include/event_groups.h
index 601a29b..275f316 100644
--- a/Source/include/event_groups.h
+++ b/Source/include/event_groups.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -65,8 +65,6 @@
* be set and then tested atomically - as is the case where event groups are
* used to create a synchronisation point between multiple tasks (a
* 'rendezvous').
- *
- * \defgroup EventGroup
*/
@@ -243,7 +241,8 @@
*
* @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
* for one/all (depending on the xWaitForAllBits value) of the bits specified by
- * uxBitsToWaitFor to become set.
+ * uxBitsToWaitFor to become set. A value of portMAX_DELAY can be used to block
+ * indefinitely (provided INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
*
* @return The value of the event group at the time either the bits being waited
* for became set, or the block time expired. Test the return value to know
@@ -377,6 +376,12 @@
* timer task to have the clear operation performed in the context of the timer
* task.
*
+ * @note If this function returns pdPASS then the timer task is ready to run
+ * and a portYIELD_FROM_ISR(pdTRUE) should be executed to perform the needed
+ * clear on the event group. This behavior is different from
+ * xEventGroupSetBitsFromISR because the parameter xHigherPriorityTaskWoken is
+ * not present.
+ *
* @param xEventGroup The event group in which the bits are to be cleared.
*
* @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
@@ -406,6 +411,7 @@
* if( xResult == pdPASS )
* {
* // The message was posted successfully.
+ * portYIELD_FROM_ISR(pdTRUE);
* }
* }
* @endcode
@@ -417,7 +423,7 @@
const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
#else
#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
- xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+ xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL )
#endif
/**
@@ -573,7 +579,7 @@
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
#else
#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
- xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+ xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) )
#endif
/**
@@ -722,7 +728,7 @@
* \defgroup xEventGroupGetBits xEventGroupGetBits
* \ingroup EventGroup
*/
-#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( ( xEventGroup ), 0 )
/**
* event_groups.h
diff --git a/Source/include/list.h b/Source/include/list.h
index f866f9f..35e4789 100644
--- a/Source/include/list.h
+++ b/Source/include/list.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -153,14 +153,18 @@
};
typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */
-struct xMINI_LIST_ITEM
-{
- listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
- configLIST_VOLATILE TickType_t xItemValue;
- struct xLIST_ITEM * configLIST_VOLATILE pxNext;
- struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
-};
-typedef struct xMINI_LIST_ITEM MiniListItem_t;
+#if ( configUSE_MINI_LIST_ITEM == 1 )
+ struct xMINI_LIST_ITEM
+ {
+ listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+ configLIST_VOLATILE TickType_t xItemValue;
+ struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+ };
+ typedef struct xMINI_LIST_ITEM MiniListItem_t;
+#else
+ typedef struct xLIST_ITEM MiniListItem_t;
+#endif
/*
* Definition of the type of queue used by the scheduler.
diff --git a/Source/include/message_buffer.h b/Source/include/message_buffer.h
index 1406267..bb8a7f7 100644
--- a/Source/include/message_buffer.h
+++ b/Source/include/message_buffer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -80,9 +80,10 @@
* Type by which message buffers are referenced. For example, a call to
* xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
* then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
- * etc.
+ * etc. Message buffer is essentially built as a stream buffer hence its handle
+ * is also set to same type as a stream buffer handle.
*/
-typedef void * MessageBufferHandle_t;
+typedef StreamBufferHandle_t MessageBufferHandle_t;
/*-----------------------------------------------------------*/
@@ -107,6 +108,18 @@
* 32-bit architecture, so on most 32-bit architectures a 10 byte message will
* take up 14 bytes of message buffer space.
*
+ * @param pxSendCompletedCallback Callback invoked when a send operation to the
+ * message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
+ * is called without the parameter, then it will use the default implementation
+ * provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when a receive operation from
+ * the message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
+ * is called without the parameter, it will use the default implementation provided
+ * by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
* @return If NULL is returned, then the message buffer cannot be created
* because there is insufficient heap memory available for FreeRTOS to allocate
* the message buffer data structures and storage area. A non-NULL value being
@@ -125,7 +138,7 @@
* // Create a message buffer that can hold 100 bytes. The memory used to hold
* // both the message buffer structure and the messages themselves is allocated
* // dynamically. Each message added to the buffer consumes an additional 4
- * // bytes which are used to hold the lengh of the message.
+ * // bytes which are used to hold the length of the message.
* xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
*
* if( xMessageBuffer == NULL )
@@ -143,7 +156,12 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferCreate( xBufferSizeBytes ) \
- ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
/**
* message_buffer.h
@@ -172,6 +190,16 @@
* StaticMessageBuffer_t, which will be used to hold the message buffer's data
* structure.
*
+ * @param pxSendCompletedCallback Callback invoked when a new message is sent to the message buffer.
+ * If the parameter is NULL or xMessageBufferCreate() is called without the parameter, then it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when a message is read from a
+ * message buffer. If the parameter is NULL or xMessageBufferCreate() is called without the parameter, it will
+ * use the default implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
* @return If the message buffer is created successfully then a handle to the
* created message buffer is returned. If either pucMessageBufferStorageArea or
* pxStaticmessageBuffer are NULL then NULL is returned.
@@ -210,7 +238,12 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
- ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
/**
* message_buffer.h
@@ -310,7 +343,7 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \
- xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+ xStreamBufferSend( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( xTicksToWait ) )
/**
* message_buffer.h
@@ -415,7 +448,7 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \
- xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+ xStreamBufferSendFromISR( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( pxHigherPriorityTaskWoken ) )
/**
* message_buffer.h
@@ -504,7 +537,7 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \
- xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+ xStreamBufferReceive( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( xTicksToWait ) )
/**
@@ -606,7 +639,7 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \
- xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+ xStreamBufferReceiveFromISR( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( pxHigherPriorityTaskWoken ) )
/**
* message_buffer.h
@@ -627,7 +660,7 @@
*
*/
#define vMessageBufferDelete( xMessageBuffer ) \
- vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+ vStreamBufferDelete( xMessageBuffer )
/**
* message_buffer.h
@@ -645,7 +678,7 @@
* pdTRUE is returned. Otherwise pdFALSE is returned.
*/
#define xMessageBufferIsFull( xMessageBuffer ) \
- xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+ xStreamBufferIsFull( xMessageBuffer )
/**
* message_buffer.h
@@ -662,7 +695,7 @@
*
*/
#define xMessageBufferIsEmpty( xMessageBuffer ) \
- xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+ xStreamBufferIsEmpty( xMessageBuffer )
/**
* message_buffer.h
@@ -686,7 +719,7 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferReset( xMessageBuffer ) \
- xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+ xStreamBufferReset( xMessageBuffer )
/**
@@ -709,9 +742,9 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferSpaceAvailable( xMessageBuffer ) \
- xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+ xStreamBufferSpacesAvailable( xMessageBuffer )
#define xMessageBufferSpacesAvailable( xMessageBuffer ) \
- xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+ xStreamBufferSpacesAvailable( xMessageBuffer ) /* Corrects typo in original macro name. */
/**
* message_buffer.h
@@ -731,7 +764,7 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
- xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+ xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION;
/**
* message_buffer.h
@@ -771,7 +804,7 @@
* \ingroup StreamBufferManagement
*/
#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
- xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+ xStreamBufferSendCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )
/**
* message_buffer.h
@@ -812,7 +845,7 @@
* \ingroup StreamBufferManagement
*/
#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
- xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+ xStreamBufferReceiveCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )
/* *INDENT-OFF* */
#if defined( __cplusplus )
diff --git a/Source/include/mpu_prototypes.h b/Source/include/mpu_prototypes.h
index cb743be..933794c 100644
--- a/Source/include/mpu_prototypes.h
+++ b/Source/include/mpu_prototypes.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -38,7 +38,7 @@
#ifndef MPU_PROTOTYPES_H
#define MPU_PROTOTYPES_H
-/* MPU versions of tasks.h API functions. */
+/* MPU versions of task.h API functions. */
BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
const char * const pcName,
const uint16_t usStackDepth,
@@ -248,12 +248,16 @@
size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+ BaseType_t xIsMessageBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
BaseType_t xIsMessageBuffer,
uint8_t * const pucStreamBufferStorageArea,
- StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+ StaticStreamBuffer_t * const pxStaticStreamBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
diff --git a/Source/include/mpu_wrappers.h b/Source/include/mpu_wrappers.h
index 9b6cd7c..af06ab3 100644
--- a/Source/include/mpu_wrappers.h
+++ b/Source/include/mpu_wrappers.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -46,7 +46,7 @@
* privileges.
*/
-/* Map standard tasks.h API functions to the MPU equivalents. */
+/* Map standard task.h API functions to the MPU equivalents. */
#define xTaskCreate MPU_xTaskCreate
#define xTaskCreateStatic MPU_xTaskCreateStatic
#define vTaskDelete MPU_vTaskDelete
@@ -120,13 +120,10 @@
#endif
/* Map standard timer.h API functions to the MPU equivalents. */
- #define xTimerCreate MPU_xTimerCreate
- #define xTimerCreateStatic MPU_xTimerCreateStatic
#define pvTimerGetTimerID MPU_pvTimerGetTimerID
#define vTimerSetTimerID MPU_vTimerSetTimerID
#define xTimerIsTimerActive MPU_xTimerIsTimerActive
#define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle
- #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall
#define pcTimerGetName MPU_pcTimerGetName
#define vTimerSetReloadMode MPU_vTimerSetReloadMode
#define uxTimerGetReloadMode MPU_uxTimerGetReloadMode
@@ -168,41 +165,11 @@
#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
- /* Ensure API functions go in the privileged execution section. */
+/* Ensure API functions go in the privileged execution section. */
#define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) )
#define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) )
#define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) )
- /**
- * @brief Calls the port specific code to raise the privilege.
- *
- * Sets xRunningPrivileged to pdFALSE if privilege was raised, else sets
- * it to pdTRUE.
- */
- #define xPortRaisePrivilege( xRunningPrivileged ) \
- { \
- /* Check whether the processor is already privileged. */ \
- xRunningPrivileged = portIS_PRIVILEGED(); \
- \
- /* If the processor is not already privileged, raise privilege. */ \
- if( xRunningPrivileged == pdFALSE ) \
- { \
- portRAISE_PRIVILEGE(); \
- } \
- }
-
- /**
- * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
- * code to reset the privilege, otherwise does nothing.
- */
- #define vPortResetPrivilege( xRunningPrivileged ) \
- { \
- if( xRunningPrivileged == pdFALSE ) \
- { \
- portRESET_PRIVILEGE(); \
- } \
- }
-
#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
#else /* portUSING_MPU_WRAPPERS */
diff --git a/Source/include/portable.h b/Source/include/portable.h
index 0ec6416..e7ec7bd 100644
--- a/Source/include/portable.h
+++ b/Source/include/portable.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -173,6 +173,8 @@
* Map to the memory management routines required for the port.
*/
void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void * pvPortCalloc( size_t xNum,
+ size_t xSize ) PRIVILEGED_FUNCTION;
void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
@@ -186,6 +188,19 @@
#define vPortFreeStack vPortFree
#endif
+#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationMallocFailedHook( void )
+ * @endcode
+ *
+ * This hook function is called when allocation failed.
+ */
+ void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+#endif
+
/*
* Setup the hardware ready for the scheduler to take control. This generally
* sets up a tick interrupt and sets timers for the correct tick frequency.
diff --git a/Source/include/projdefs.h b/Source/include/projdefs.h
index e623bf7..aa49e59 100644
--- a/Source/include/projdefs.h
+++ b/Source/include/projdefs.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/include/queue.h b/Source/include/queue.h
index 6a92b6b..df572e1 100644
--- a/Source/include/queue.h
+++ b/Source/include/queue.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -978,7 +978,7 @@
* void vBufferISR( void )
* {
* char cIn;
- * BaseType_t xHigherPrioritTaskWoken;
+ * BaseType_t xHigherPriorityTaskWoken;
*
* // We have not woken a task at the start of the ISR.
* xHigherPriorityTaskWoken = pdFALSE;
@@ -1400,12 +1400,12 @@
* vOutputCharacter( cRxedChar );
*
* // If removing the character from the queue woke the task that was
- * // posting onto the queue cTaskWokenByReceive will have been set to
+ * // posting onto the queue xTaskWokenByReceive will have been set to
* // pdTRUE. No matter how many times this loop iterates only one
* // task will be woken.
* }
*
- * if( cTaskWokenByPost != ( char ) pdFALSE;
+ * if( xTaskWokenByReceive != ( char ) pdFALSE;
* {
* taskYIELD ();
* }
@@ -1420,7 +1420,7 @@
/*
* Utilities to query queues that are safe to use from an ISR. These utilities
- * should be used only from witin an ISR, or within a critical section.
+ * should be used only from within an ISR, or within a critical section.
*/
BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
@@ -1478,7 +1478,7 @@
* Reset a queue back to its original empty state. The return value is now
* obsolete and is always set to pdPASS.
*/
-#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+#define xQueueReset( xQueue ) xQueueGenericReset( ( xQueue ), pdFALSE )
/*
* The registry is provided as a means for kernel aware debuggers to
@@ -1490,7 +1490,7 @@
* configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
* registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0
* within FreeRTOSConfig.h for the registry to be available. Its value
- * does not effect the number of queues, semaphores and mutexes that can be
+ * does not affect the number of queues, semaphores and mutexes that can be
* created - just the number that the registry can hold.
*
* If vQueueAddToRegistry is called more than once with the same xQueue
diff --git a/Source/include/semphr.h b/Source/include/semphr.h
index d28d4a0..d3165d8 100644
--- a/Source/include/semphr.h
+++ b/Source/include/semphr.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -225,7 +225,7 @@
* \ingroup Semaphores
*/
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+ #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, ( pxStaticSemaphore ), queueQUEUE_TYPE_BINARY_SEMAPHORE )
#endif /* configSUPPORT_STATIC_ALLOCATION */
/**
@@ -731,7 +731,7 @@
* \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
* \ingroup Semaphores
*/
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )
#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
#endif
@@ -794,9 +794,9 @@
* \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
* \ingroup Semaphores
*/
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )
#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+#endif
/**
@@ -808,7 +808,7 @@
* Creates a new recursive mutex type semaphore instance, and returns a handle
* by which the new recursive mutex can be referenced.
*
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * Internally, within the FreeRTOS implementation, recursive mutexes use a block
* of memory, in which the mutex structure is stored. If a recursive mutex is
* created using xSemaphoreCreateRecursiveMutex() then the required memory is
* automatically dynamically allocated inside the
@@ -877,7 +877,7 @@
* Creates a new recursive mutex type semaphore instance, and returns a handle
* by which the new recursive mutex can be referenced.
*
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * Internally, within the FreeRTOS implementation, recursive mutexes use a block
* of memory, in which the mutex structure is stored. If a recursive mutex is
* created using xSemaphoreCreateRecursiveMutex() then the required memory is
* automatically dynamically allocated inside the
@@ -940,7 +940,7 @@
* \ingroup Semaphores
*/
#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
- #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+ #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, ( pxStaticSemaphore ) )
#endif /* configSUPPORT_STATIC_ALLOCATION */
/**
@@ -1126,7 +1126,7 @@
* \defgroup vSemaphoreDelete vSemaphoreDelete
* \ingroup Semaphores
*/
-#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
/**
* semphr.h
@@ -1143,7 +1143,9 @@
* the holder may change between the function exiting and the returned value
* being tested.
*/
-#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+ #define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+#endif
/**
* semphr.h
@@ -1156,7 +1158,9 @@
* by a task), return NULL.
*
*/
-#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+ #define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+#endif
/**
* semphr.h
@@ -1170,7 +1174,7 @@
* semaphore is not available.
*
*/
-#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
/**
* semphr.h
@@ -1184,6 +1188,6 @@
* semaphore is not available.
*
*/
-#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )
+#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )
#endif /* SEMAPHORE_H */
diff --git a/Source/include/stack_macros.h b/Source/include/stack_macros.h
index cfe5b95..2455674 100644
--- a/Source/include/stack_macros.h
+++ b/Source/include/stack_macros.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/include/stdint.readme b/Source/include/stdint.readme
index 654c62b..ef2b7f7 100644
--- a/Source/include/stdint.readme
+++ b/Source/include/stdint.readme
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/include/stream_buffer.h b/Source/include/stream_buffer.h
index c2812d4..bf5019e 100644
--- a/Source/include/stream_buffer.h
+++ b/Source/include/stream_buffer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -71,6 +71,12 @@
struct StreamBufferDef_t;
typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+/**
+ * Type used as a stream buffer's optional callback.
+ */
+typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuffer,
+ BaseType_t xIsInsideISR,
+ BaseType_t * const pxHigherPriorityTaskWoken );
/**
* stream_buffer.h
@@ -103,6 +109,16 @@
* trigger level of 1 being used. It is not valid to specify a trigger level
* that is greater than the buffer size.
*
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
+ * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
+ * stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
* @return If NULL is returned, then the stream buffer cannot be created
* because there is insufficient heap memory available for FreeRTOS to allocate
* the stream buffer data structures and storage area. A non-NULL value being
@@ -137,7 +153,14 @@
* \defgroup xStreamBufferCreate xStreamBufferCreate
* \ingroup StreamBufferManagement
*/
-#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+ xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
/**
* stream_buffer.h
@@ -179,6 +202,16 @@
* StaticStreamBuffer_t, which will be used to hold the stream buffer's data
* structure.
*
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
+ * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
+ * stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
* @return If the stream buffer is created successfully then a handle to the
* created stream buffer is returned. If either pucStreamBufferStorageArea or
* pxStaticstreamBuffer are NULL then NULL is returned.
@@ -218,8 +251,14 @@
* \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
* \ingroup StreamBufferManagement
*/
+
#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
- xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+ xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
/**
* stream_buffer.h
@@ -405,10 +444,10 @@
* // priority of the currently executing task was unblocked and a context
* // switch should be performed to ensure the ISR returns to the unblocked
* // task. In most FreeRTOS ports this is done by simply passing
- * // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
* // variables value, and perform the context switch if necessary. Check the
* // documentation for the port in use for port specific instructions.
- * taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
* }
* @endcode
* \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
@@ -495,7 +534,7 @@
*
* if( xReceivedBytes > 0 )
* {
- * // A ucRxData contains another xRecievedBytes bytes of data, which can
+ * // A ucRxData contains another xReceivedBytes bytes of data, which can
* // be processed here....
* }
* }
@@ -580,10 +619,10 @@
* // priority of the currently executing task was unblocked and a context
* // switch should be performed to ensure the ISR returns to the unblocked
* // task. In most FreeRTOS ports this is done by simply passing
- * // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
* // variables value, and perform the context switch if necessary. Check the
* // documentation for the port in use for port specific instructions.
- * taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
* }
* @endcode
* \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
@@ -843,13 +882,18 @@
/* Functions below here are not part of the public API. */
StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+ BaseType_t xIsMessageBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+
StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
BaseType_t xIsMessageBuffer,
uint8_t * const pucStreamBufferStorageArea,
- StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+ StaticStreamBuffer_t * const pxStaticStreamBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
diff --git a/Source/include/task.h b/Source/include/task.h
index ec80cd9..ab8eeb8 100644
--- a/Source/include/task.h
+++ b/Source/include/task.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -53,10 +53,10 @@
* The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
* values will reflect the last released version number.
*/
-#define tskKERNEL_VERSION_NUMBER "V10.4.6"
+#define tskKERNEL_VERSION_NUMBER "V10.5.1"
#define tskKERNEL_VERSION_MAJOR 10
-#define tskKERNEL_VERSION_MINOR 4
-#define tskKERNEL_VERSION_BUILD 6
+#define tskKERNEL_VERSION_MINOR 5
+#define tskKERNEL_VERSION_BUILD 1
/* MPU region parameters passed in ulParameters
* of MemoryRegion_t struct. */
@@ -161,15 +161,21 @@
UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */
+ #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+ StackType_t * pxTopOfStack; /* Points to the top address of the task's stack area. */
+ StackType_t * pxEndOfStack; /* Points to the end address of the task's stack area. */
+ #endif
configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */
} TaskStatus_t;
/* Possible return values for eTaskConfirmSleepModeStatus(). */
typedef enum
{
- eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
- eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */
- eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+ eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+ eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+ #endif /* INCLUDE_vTaskSuspend */
} eSleepModeStatus;
/**
@@ -622,7 +628,7 @@
* // Create a task from the const structure defined above. The task handle
* // is requested (the second parameter is not NULL) but in this case just for
* // demonstration purposes as its not actually used.
- * xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ * xTaskCreateRestrictedStatic( &xRegTest1Parameters, &xHandle );
*
* // Start the scheduler.
* vTaskStartScheduler();
@@ -684,7 +690,7 @@
* // defined or shared regions have been declared elsewhere).
* }
* @endcode
- * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions
* \ingroup Tasks
*/
void vTaskAllocateMPURegions( TaskHandle_t xTask,
@@ -859,10 +865,10 @@
* vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not
* return a value.
*/
-#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) \
- { \
- ( void ) xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); \
- }
+#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) \
+ do { \
+ ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); \
+ } while( 0 )
/**
@@ -994,7 +1000,7 @@
* filled with information about the task referenced by the handle passed using
* the xTask parameter.
*
- * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * @param xGetFreeStackSpace The TaskStatus_t structure contains a member to report
* the stack high water mark of the task being queried. Calculating the stack
* high water mark takes a relatively long time, and can make the system
* temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
@@ -2404,7 +2410,7 @@
*
* When task notifications are being used as a binary or counting semaphore
* equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTakeIndexed() API function rather than the
+ * using the ulTaskNotifyTakeIndexed() API function rather than the
* xTaskNotifyWaitIndexed() API function.
*
* **NOTE** Each notification within the array operates independently - a task
@@ -2481,7 +2487,7 @@
*
* When task notifications are being used as a binary or counting semaphore
* equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTakeIndexed() API function rather than the
+ * using the ulTaskNotifyTakeIndexed() API function rather than the
* xTaskNotifyWaitIndexed() API function.
*
* **NOTE** Each notification within the array operates independently - a task
@@ -2525,9 +2531,9 @@
UBaseType_t uxIndexToNotify,
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \
- vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) );
+ vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) )
#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \
- vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) );
+ vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) )
/**
* task. h
@@ -3054,7 +3060,7 @@
UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
/*
- * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ * Get the uxTaskNumber assigned to the task referenced by the xTask parameter.
*/
UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
@@ -3073,7 +3079,7 @@
* to date with the actual execution time by being skipped forward by a time
* equal to the idle period.
*/
-void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
/*
* Only available when configUSE_TICKLESS_IDLE is set to 1.
diff --git a/Source/include/timers.h b/Source/include/timers.h
index 2be826c..4b73908 100644
--- a/Source/include/timers.h
+++ b/Source/include/timers.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -94,7 +94,7 @@
/**
* TimerHandle_t xTimerCreate( const char * const pcTimerName,
* TickType_t xTimerPeriodInTicks,
- * UBaseType_t uxAutoReload,
+ * BaseType_t xAutoReload,
* void * pvTimerID,
* TimerCallbackFunction_t pxCallbackFunction );
*
@@ -127,9 +127,9 @@
* to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
* equal to 1000. Time timer period must be greater than 0.
*
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
* expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
* enter the dormant state after it expires.
*
* @param pvTimerID An identifier that is assigned to the timer being created.
@@ -192,11 +192,11 @@
* // the scheduler starts.
* for( x = 0; x < NUM_TIMERS; x++ )
* {
- * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel.
- * ( 100 * x ), // The timer period in ticks.
- * pdTRUE, // The timers will auto-reload themselves when they expire.
- * ( void * ) x, // Assign each timer a unique id equal to its array index.
- * vTimerCallback // Each timer calls the same callback when it expires.
+ * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel.
+ * ( 100 * ( x + 1 ) ), // The timer period in ticks.
+ * pdTRUE, // The timers will auto-reload themselves when they expire.
+ * ( void * ) x, // Assign each timer a unique id equal to its array index.
+ * vTimerCallback // Each timer calls the same callback when it expires.
* );
*
* if( xTimers[ x ] == NULL )
@@ -231,7 +231,7 @@
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
#endif
@@ -239,7 +239,7 @@
/**
* TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
* TickType_t xTimerPeriodInTicks,
- * UBaseType_t uxAutoReload,
+ * BaseType_t xAutoReload,
* void * pvTimerID,
* TimerCallbackFunction_t pxCallbackFunction,
* StaticTimer_t *pxTimerBuffer );
@@ -273,9 +273,9 @@
* to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
* equal to 1000. The timer period must be greater than 0.
*
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
* expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
* enter the dormant state after it expires.
*
* @param pvTimerID An identifier that is assigned to the timer being created.
@@ -361,7 +361,7 @@
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction,
StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
@@ -1252,7 +1252,7 @@
const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
/**
- * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload );
*
* Updates a timer to be either an auto-reload timer, in which case the timer
* automatically resets itself each time it expires, or a one-shot timer, in
@@ -1260,14 +1260,28 @@
*
* @param xTimer The handle of the timer being updated.
*
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
* expire repeatedly with a frequency set by the timer's period (see the
* xTimerPeriodInTicks parameter of the xTimerCreate() API function). If
- * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
* enter the dormant state after it expires.
*/
void vTimerSetReloadMode( TimerHandle_t xTimer,
- const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+ const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer );
+ *
+ * Queries a timer to determine if it is an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+ * pdFALSE is returned.
+ */
+BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
/**
* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
@@ -1338,7 +1352,7 @@
* configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
*
* @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer
- * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task
+ * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
* @param pulTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
*/
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
diff --git a/Source/list.c b/Source/list.c
index 42a2e09..0f4f42e 100644
--- a/Source/list.c
+++ b/Source/list.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -54,6 +54,8 @@
* as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
+
/* The list end value is the highest possible value in the list to
* ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
@@ -63,6 +65,15 @@
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
+ #if ( configUSE_MINI_LIST_ITEM == 0 )
+ {
+ pxList->xListEnd.pvOwner = NULL;
+ pxList->xListEnd.pxContainer = NULL;
+ listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
+ }
+ #endif
+
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
/* Write known values into the list if
diff --git a/Source/portable/Common/mpu_wrappers.c b/Source/portable/Common/mpu_wrappers.c
index 827c44a..9a45ba8 100644
--- a/Source/portable/Common/mpu_wrappers.c
+++ b/Source/portable/Common/mpu_wrappers.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -48,1416 +48,2461 @@
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
- const char * const pcName,
- uint16_t usStackDepth,
- void * pvParameters,
- UBaseType_t uxPriority,
- TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
+ const char * const pcName,
+ uint16_t usStackDepth,
+ void * pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxPriority = uxPriority & ~( portPRIVILEGE_BIT );
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+ }
+
+ return xReturn;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+ const char * const pcName,
+ const uint32_t ulStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TaskHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxPriority = uxPriority & ~( portPRIVILEGE_BIT );
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+ }
+
+ return xReturn;
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskDelete( pxTaskToDelete );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskDelete( pxTaskToDelete );
+ }
+ }
+ #endif /* if ( INCLUDE_vTaskDelete == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskDelayUntil == 1 )
+ BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+ TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskAbortDelay == 1 )
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskAbortDelay( xTask );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskAbortDelay( xTask );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskDelay == 1 )
+ void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskDelay( xTicksToDelay );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskDelay( xTicksToDelay );
+ }
+ }
+ #endif /* if ( INCLUDE_vTaskDelay == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskPriorityGet == 1 )
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ UBaseType_t uxReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxTaskPriorityGet( pxTask );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxTaskPriorityGet( pxTask );
+ }
+
+ return uxReturn;
+ }
+ #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskPrioritySet == 1 )
+ void MPU_vTaskPrioritySet( TaskHandle_t pxTask,
+ UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskPrioritySet( pxTask, uxNewPriority );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskPrioritySet( pxTask, uxNewPriority );
+ }
+ }
+ #endif /* if ( INCLUDE_vTaskPrioritySet == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+ eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ eTaskState eReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ eReturn = eTaskGetState( pxTask );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ eReturn = eTaskGetState( pxTask );
+ }
+
+ return eReturn;
+ }
+ #endif /* if ( INCLUDE_eTaskGetState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ void MPU_vTaskGetInfo( TaskHandle_t xTask,
+ TaskStatus_t * pxTaskStatus,
+ BaseType_t xGetFreeStackSpace,
+ eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
+ }
+ }
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TaskHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ xReturn = xTaskGetIdleTaskHandle();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGetIdleTaskHandle();
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskSuspend( pxTaskToSuspend );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskSuspend( pxTaskToSuspend );
+ }
+ }
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskResume( pxTaskToResume );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskResume( pxTaskToResume );
+ }
+ }
+ #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+/*-----------------------------------------------------------*/
+
+ void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
{
- BaseType_t xReturn, xRunningPrivileged;
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
- vPortResetPrivilege( xRunningPrivileged );
+ vTaskSuspendAll();
+ portMEMORY_BARRIER();
- return xReturn;
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskSuspendAll();
+ }
}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
- const char * const pcName,
- const uint32_t ulStackDepth,
- void * const pvParameters,
- UBaseType_t uxPriority,
- StackType_t * const puxStackBuffer,
- StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- TaskHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
- void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskDelete( pxTaskToDelete );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskDelayUntil == 1 )
- BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
- TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged, xReturn;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskAbortDelay == 1 )
- BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskAbortDelay( xTask );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
- void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskDelay( xTicksToDelay );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
- UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
- {
- UBaseType_t uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxTaskPriorityGet( pxTask );
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
- }
-#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
- void MPU_vTaskPrioritySet( TaskHandle_t pxTask,
- UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskPrioritySet( pxTask, uxNewPriority );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if ( INCLUDE_vTaskPrioritySet == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_eTaskGetState == 1 )
- eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
- {
- eTaskState eReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- eReturn = eTaskGetState( pxTask );
- vPortResetPrivilege( xRunningPrivileged );
-
- return eReturn;
- }
-#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
- void MPU_vTaskGetInfo( TaskHandle_t xTask,
- TaskStatus_t * pxTaskStatus,
- BaseType_t xGetFreeStackSpace,
- eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
- TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
- {
- TaskHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGetIdleTaskHandle();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
- void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskSuspend( pxTaskToSuspend );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
- void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskResume( pxTaskToResume );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskSuspendAll();
- vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskResumeAll();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
-{
- TickType_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGetTickCount();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
-{
- UBaseType_t uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxTaskGetNumberOfTasks();
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
-{
- char * pcReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- pcReturn = pcTaskGetName( xTaskToQuery );
- vPortResetPrivilege( xRunningPrivileged );
-
- return pcReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
- TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
- {
- TaskHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGetHandle( pcNameToQuery );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( INCLUDE_xTaskGetHandle == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskList( pcWriteBuffer );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskGetRunTimeStats( pcWriteBuffer );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
- configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */
- {
- configRUN_TIME_COUNTER_TYPE xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = ulTaskGetIdleRunTimePercent();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
- configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
- {
- configRUN_TIME_COUNTER_TYPE xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = ulTaskGetIdleRunTimeCounter();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
- void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
- TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskSetApplicationTaskTag( xTask, pxTagValue );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
- TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
- {
- TaskHookFunction_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGetApplicationTaskTag( xTask );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
- void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
- BaseType_t xIndex,
- void * pvValue ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
- void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
- BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
- {
- void * pvReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
- vPortResetPrivilege( xRunningPrivileged );
-
- return pvReturn;
- }
-#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
- BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
- void * pvParameter ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
- UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray,
- UBaseType_t uxArraySize,
- configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
- {
- UBaseType_t uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
- }
-#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskCatchUpTicks( xTicksToCatchUp );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
- UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
- {
- UBaseType_t uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxTaskGetStackHighWaterMark( xTask );
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
- }
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
- configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
- {
- configSTACK_DEPTH_TYPE uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxTaskGetStackHighWaterMark2( xTask );
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
- }
-#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
- TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
- {
- TaskHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGetCurrentTaskHandle();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
- BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGetSchedulerState();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTaskSetTimeOutState( pxTimeOut );
- vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
- TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
- UBaseType_t uxIndexToNotify,
- uint32_t ulValue,
- eNotifyAction eAction,
- uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
- uint32_t ulBitsToClearOnEntry,
- uint32_t ulBitsToClearOnExit,
- uint32_t * pulNotificationValue,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
- BaseType_t xClearCountOnExit,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- uint32_t ulReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return ulReturn;
- }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
- UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
- UBaseType_t uxIndexToClear,
- uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
- {
- uint32_t ulReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
- vPortResetPrivilege( xRunningPrivileged );
-
- return ulReturn;
- }
-#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength,
- UBaseType_t uxItemSize,
- uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
- const UBaseType_t uxItemSize,
- uint8_t * pucQueueStorage,
- StaticQueue_t * pxStaticQueue,
- const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue,
- BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueGenericReset( pxQueue, xNewQueue );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
- const void * const pvItemToQueue,
- TickType_t xTicksToWait,
- BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
-{
- UBaseType_t uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxQueueMessagesWaiting( pxQueue );
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
- UBaseType_t uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxQueueSpacesAvailable( xQueue );
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue,
- void * const pvBuffer,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
- void * const pvBuffer,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
- TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
- {
- void * xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueGetMutexHolder( xSemaphore );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueCreateMutex( ucQueueType );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
- QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
- StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue,
- UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
- QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
- const UBaseType_t uxInitialCount,
- StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
- BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
- TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
- BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueGiveMutexRecursive( xMutex );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueSetHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueCreateSet( uxEventQueueLength );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
- QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
- TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
- {
- QueueSetMemberHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
- BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
- QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
- BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
- QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
- void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
- const char * pcName ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vQueueAddToRegistry( xQueue, pcName );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if configQUEUE_REGISTRY_SIZE > 0 */
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
- void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vQueueUnregisterQueue( xQueue );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if configQUEUE_REGISTRY_SIZE > 0 */
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
- const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
- {
- const char * pcReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- pcReturn = pcQueueGetName( xQueue );
- vPortResetPrivilege( xRunningPrivileged );
-
- return pcReturn;
- }
-#endif /* if configQUEUE_REGISTRY_SIZE > 0 */
-/*-----------------------------------------------------------*/
-
-void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vQueueDelete( xQueue );
- vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
- TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
- const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
- void * const pvTimerID,
- TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
- {
- TimerHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
- TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
- const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
- void * const pvTimerID,
- TimerCallbackFunction_t pxCallbackFunction,
- StaticTimer_t * pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
- {
- TimerHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
- {
- void * pvReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- pvReturn = pvTimerGetTimerID( xTimer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return pvReturn;
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
- void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTimerSetTimerID( xTimer, pvNewID );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerIsTimerActive( xTimer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
- {
- TaskHandle_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerGetTimerDaemonTaskHandle();
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
- BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
- void * pvParameter1,
- uint32_t ulParameter2,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
- const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
- {
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vTimerSetReloadMode( xTimer, uxAutoReload );
- vPortResetPrivilege( xRunningPrivileged );
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer )
- {
- UBaseType_t uxReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- uxReturn = uxTimerGetReloadMode( xTimer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return uxReturn;
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
- {
- const char * pcReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- pcReturn = pcTimerGetName( xTimer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return pcReturn;
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
- {
- TickType_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerGetPeriod( xTimer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
- {
- TickType_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerGetExpiryTime( xTimer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
- }
-#endif /* if ( configUSE_TIMERS == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
- const BaseType_t xCommandID,
- const TickType_t xOptionalValue,
- BaseType_t * const pxHigherPriorityTaskWoken,
- const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskResumeAll();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskResumeAll();
+ }
return xReturn;
}
-#endif /* if ( configUSE_TIMERS == 1 ) */
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
+ TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
{
- EventGroupHandle_t xReturn;
- BaseType_t xRunningPrivileged;
+ TickType_t xReturn;
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xEventGroupCreate();
- vPortResetPrivilege( xRunningPrivileged );
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskGetTickCount();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGetTickCount();
+ }
return xReturn;
}
-#endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
+ UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
{
- EventGroupHandle_t xReturn;
- BaseType_t xRunningPrivileged;
+ UBaseType_t uxReturn;
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
- vPortResetPrivilege( xRunningPrivileged );
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxTaskGetNumberOfTasks();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxTaskGetNumberOfTasks();
+ }
+
+ return uxReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
+ {
+ char * pcReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ pcReturn = pcTaskGetName( xTaskToQuery );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ pcReturn = pcTaskGetName( xTaskToQuery );
+ }
+
+ return pcReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetHandle == 1 )
+ TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TaskHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskGetHandle( pcNameToQuery );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGetHandle( pcNameToQuery );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( INCLUDE_xTaskGetHandle == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskList( pcWriteBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskList( pcWriteBuffer );
+ }
+ }
+ #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskGetRunTimeStats( pcWriteBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskGetRunTimeStats( pcWriteBuffer );
+ }
+ }
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ configRUN_TIME_COUNTER_TYPE xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = ulTaskGetIdleRunTimePercent();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = ulTaskGetIdleRunTimePercent();
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+ configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ configRUN_TIME_COUNTER_TYPE xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = ulTaskGetIdleRunTimeCounter();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = ulTaskGetIdleRunTimeCounter();
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+ TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskSetApplicationTaskTag( xTask, pxTagValue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskSetApplicationTaskTag( xTask, pxTagValue );
+ }
+ }
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TaskHookFunction_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskGetApplicationTaskTag( xTask );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGetApplicationTaskTag( xTask );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+ BaseType_t xIndex,
+ void * pvValue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
+ }
+ }
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+ void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+ BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
+ {
+ void * pvReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
+ }
+
+ return pvReturn;
+ }
+ #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+ void * pvParameter ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray,
+ UBaseType_t uxArraySize,
+ configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
+ {
+ UBaseType_t uxReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+ }
+
+ return uxReturn;
+ }
+ #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskCatchUpTicks( xTicksToCatchUp );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskCatchUpTicks( xTicksToCatchUp );
+ }
return xReturn;
}
-#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ UBaseType_t uxReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxTaskGetStackHighWaterMark( xTask );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxTaskGetStackHighWaterMark( xTask );
+ }
+
+ return uxReturn;
+ }
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ configSTACK_DEPTH_TYPE uxReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxTaskGetStackHighWaterMark2( xTask );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxTaskGetStackHighWaterMark2( xTask );
+ }
+
+ return uxReturn;
+ }
+ #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TaskHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ xReturn = xTaskGetCurrentTaskHandle();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGetCurrentTaskHandle();
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( INCLUDE_xTaskGetSchedulerState == 1 )
+ BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskGetSchedulerState();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGetSchedulerState();
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
+/*-----------------------------------------------------------*/
+
+ void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTaskSetTimeOutState( pxTimeOut );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTaskSetTimeOutState( pxTimeOut );
+ }
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+ TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+ UBaseType_t uxIndexToNotify,
+ uint32_t ulValue,
+ eNotifyAction eAction,
+ uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+ uint32_t ulBitsToClearOnEntry,
+ uint32_t ulBitsToClearOnExit,
+ uint32_t * pulNotificationValue,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+ BaseType_t xClearCountOnExit,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ uint32_t ulReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
+ }
+
+ return ulReturn;
+ }
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+ UBaseType_t uxIndexToClear,
+ uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+ {
+ uint32_t ulReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
+ }
+
+ return ulReturn;
+ }
+ #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength,
+ UBaseType_t uxItemSize,
+ uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+ const UBaseType_t uxItemSize,
+ uint8_t * pucQueueStorage,
+ StaticQueue_t * pxStaticQueue,
+ const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue,
+ BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueGenericReset( pxQueue, xNewQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueGenericReset( pxQueue, xNewQueue );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+ const void * const pvItemToQueue,
+ TickType_t xTicksToWait,
+ BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ UBaseType_t uxReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxQueueMessagesWaiting( pxQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxQueueMessagesWaiting( pxQueue );
+ }
+
+ return uxReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ UBaseType_t uxReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxQueueSpacesAvailable( xQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxQueueSpacesAvailable( xQueue );
+ }
+
+ return uxReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
+ {
+ void * xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueGetMutexHolder( xSemaphore );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueGetMutexHolder( xSemaphore );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueCreateMutex( ucQueueType );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueCreateMutex( ucQueueType );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+ StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue,
+ UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+ QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+ const UBaseType_t uxInitialCount,
+ StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+ TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_RECURSIVE_MUTEXES == 1 )
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueGiveMutexRecursive( xMutex );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueGiveMutexRecursive( xMutex );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueSetHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueCreateSet( uxEventQueueLength );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueCreateSet( uxEventQueueLength );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+ TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
+ {
+ QueueSetMemberHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+ QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if configQUEUE_REGISTRY_SIZE > 0
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+ const char * pcName ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vQueueAddToRegistry( xQueue, pcName );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vQueueAddToRegistry( xQueue, pcName );
+ }
+ }
+ #endif /* if configQUEUE_REGISTRY_SIZE > 0 */
+/*-----------------------------------------------------------*/
+
+ #if configQUEUE_REGISTRY_SIZE > 0
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vQueueUnregisterQueue( xQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vQueueUnregisterQueue( xQueue );
+ }
+ }
+ #endif /* if configQUEUE_REGISTRY_SIZE > 0 */
+/*-----------------------------------------------------------*/
+
+ #if configQUEUE_REGISTRY_SIZE > 0
+ const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ const char * pcReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ pcReturn = pcQueueGetName( xQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ pcReturn = pcQueueGetName( xQueue );
+ }
+
+ return pcReturn;
+ }
+ #endif /* if configQUEUE_REGISTRY_SIZE > 0 */
+/*-----------------------------------------------------------*/
+
+ void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vQueueDelete( xQueue );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vQueueDelete( xQueue );
+ }
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ void * pvReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ pvReturn = pvTimerGetTimerID( xTimer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ pvReturn = pvTimerGetTimerID( xTimer );
+ }
+
+ return pvReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+ void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTimerSetTimerID( xTimer, pvNewID );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTimerSetTimerID( xTimer, pvNewID );
+ }
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTimerIsTimerActive( xTimer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTimerIsTimerActive( xTimer );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TaskHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTimerGetTimerDaemonTaskHandle();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTimerGetTimerDaemonTaskHandle();
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+ const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vTimerSetReloadMode( xTimer, uxAutoReload );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vTimerSetReloadMode( xTimer, uxAutoReload );
+ }
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer )
+ {
+ UBaseType_t uxReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ uxReturn = uxTimerGetReloadMode( xTimer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ uxReturn = uxTimerGetReloadMode( xTimer );
+ }
+
+ return uxReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ const char * pcReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ pcReturn = pcTimerGetName( xTimer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ pcReturn = pcTimerGetName( xTimer );
+ }
+
+ return pcReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TickType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTimerGetPeriod( xTimer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTimerGetPeriod( xTimer );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TickType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTimerGetExpiryTime( xTimer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTimerGetExpiryTime( xTimer );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configUSE_TIMERS == 1 )
+ BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
+ const BaseType_t xCommandID,
+ const TickType_t xOptionalValue,
+ BaseType_t * const pxHigherPriorityTaskWoken,
+ const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventGroupHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupCreate();
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupCreate();
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventGroupHandle_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
+ }
+
+ return xReturn;
+ }
+ #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xClearOnExit,
+ const BaseType_t xWaitForAllBits,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventBits_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventBits_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
+ {
+ EventBits_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
const EventBits_t uxBitsToWaitFor,
- const BaseType_t xClearOnExit,
- const BaseType_t xWaitForAllBits,
TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- EventBits_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-{
- EventBits_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
-{
- EventBits_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
- const EventBits_t uxBitsToSet,
- const EventBits_t uxBitsToWaitFor,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- EventBits_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vEventGroupDelete( xEventGroup );
- vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- const void * pvTxData,
- size_t xDataLengthBytes,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- size_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
- size_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- void * pvRxData,
- size_t xBufferLengthBytes,
- TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
- size_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- vStreamBufferDelete( xStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferIsFull( xStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferIsEmpty( xStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferReset( xStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
- size_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
- size_t xReturn;
- BaseType_t xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
- size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
-{
- BaseType_t xReturn, xRunningPrivileged;
-
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
- size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
{
- StreamBufferHandle_t xReturn;
- BaseType_t xRunningPrivileged;
+ EventBits_t xReturn;
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer );
- vPortResetPrivilege( xRunningPrivileged );
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+ }
return xReturn;
}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/
-#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
- size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer,
- uint8_t * const pucStreamBufferStorageArea,
- StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
{
- StreamBufferHandle_t xReturn;
- BaseType_t xRunningPrivileged;
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
- xPortRaisePrivilege( xRunningPrivileged );
- xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer );
- vPortResetPrivilege( xRunningPrivileged );
+ vEventGroupDelete( xEventGroup );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vEventGroupDelete( xEventGroup );
+ }
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ size_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+ }
return xReturn;
}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ size_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void * pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+ {
+ size_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ vStreamBufferDelete( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ vStreamBufferDelete( xStreamBuffer );
+ }
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferIsFull( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferIsFull( xStreamBuffer );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferReset( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferReset( xStreamBuffer );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ size_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+ {
+ size_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+ size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xReturn;
+
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+ }
+
+ return xReturn;
+ }
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ BaseType_t xIsMessageBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */
+ {
+ StreamBufferHandle_t xReturn;
+
+ /**
+ * Streambuffer application level callback functionality is disabled for MPU
+ * enabled ports.
+ */
+ configASSERT( ( pxSendCompletedCallback == NULL ) &&
+ ( pxReceiveCompletedCallback == NULL ) );
+
+ if( ( pxSendCompletedCallback == NULL ) &&
+ ( pxReceiveCompletedCallback == NULL ) )
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,
+ xTriggerLevelBytes,
+ xIsMessageBuffer,
+ NULL,
+ NULL );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferGenericCreate( xBufferSizeBytes,
+ xTriggerLevelBytes,
+ xIsMessageBuffer,
+ NULL,
+ NULL );
+ }
+ }
+ else
+ {
+ traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+ xReturn = NULL;
+ }
+
+ return xReturn;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ BaseType_t xIsMessageBuffer,
+ uint8_t * const pucStreamBufferStorageArea,
+ StaticStreamBuffer_t * const pxStaticStreamBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */
+ {
+ StreamBufferHandle_t xReturn;
+
+ /**
+ * Streambuffer application level callback functionality is disabled for MPU
+ * enabled ports.
+ */
+ configASSERT( ( pxSendCompletedCallback == NULL ) &&
+ ( pxReceiveCompletedCallback == NULL ) );
+
+ if( ( pxSendCompletedCallback == NULL ) &&
+ ( pxReceiveCompletedCallback == NULL ) )
+ {
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+
+ xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
+ xTriggerLevelBytes,
+ xIsMessageBuffer,
+ pucStreamBufferStorageArea,
+ pxStaticStreamBuffer,
+ NULL,
+ NULL );
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes,
+ xTriggerLevelBytes,
+ xIsMessageBuffer,
+ pucStreamBufferStorageArea,
+ pxStaticStreamBuffer,
+ NULL,
+ NULL );
+ }
+ }
+ else
+ {
+ traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+ xReturn = NULL;
+ }
+
+ return xReturn;
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
@@ -1469,14 +2514,28 @@
* void MPU_FunctionName( [parameters ] ) FREERTOS_SYSTEM_CALL;
* void MPU_FunctionName( [parameters ] )
* {
- * BaseType_t xRunningPrivileged;
+ * if( portIS_PRIVILEGED() == pdFALSE )
+ * {
+ * portRAISE_PRIVILEGE();
+ * portMEMORY_BARRIER();
*
- * xPortRaisePrivilege( xRunningPrivileged );
- * FunctionName( [parameters ] );
- * vPortResetPrivilege( xRunningPrivileged );
+ * FunctionName( [parameters ] );
+ * portMEMORY_BARRIER();
+ *
+ * portRESET_PRIVILEGE();
+ * portMEMORY_BARRIER();
+ * }
+ * else
+ * {
+ * FunctionName( [parameters ] );
+ * }
* }
*/
-#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1
- #include "application_defined_privileged_functions.h"
-#endif
+ #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1
+ #include "application_defined_privileged_functions.h"
+ #endif
+/*-----------------------------------------------------------*/
+
+#endif /* portUSING_MPU_WRAPPERS == 1 */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM0/port.c b/Source/portable/GCC/ARM_CM0/port.c
index f66f482..3a93cea 100644
--- a/Source/portable/GCC/ARM_CM0/port.c
+++ b/Source/portable/GCC/ARM_CM0/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -45,6 +45,8 @@
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
@@ -59,7 +61,19 @@
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
#ifndef portMISSED_COUNTS_FACTOR
- #define portMISSED_COUNTS_FACTOR ( 45UL )
+ #define portMISSED_COUNTS_FACTOR ( 94UL )
+#endif
+
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
#endif
/* Let the user override the pre-loading of the initial LR with the address of
@@ -381,11 +395,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -393,8 +407,8 @@
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
@@ -402,7 +416,7 @@
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -411,22 +425,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -437,23 +435,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -482,8 +506,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
@@ -503,27 +527,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -537,11 +557,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -552,15 +591,41 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
- /* Exit with interrpts enabled. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
}
}
diff --git a/Source/portable/GCC/ARM_CM0/portmacro.h b/Source/portable/GCC/ARM_CM0/portmacro.h
index 20dc03f..c56d47e 100644
--- a/Source/portable/GCC/ARM_CM0/portmacro.h
+++ b/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/port.c b/Source/portable/GCC/ARM_CM23/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
index f9253a5..c3a9782 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -137,6 +137,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" movs r1, #1 \n"/* r1 = 1. */
" tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
@@ -157,6 +159,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* Read the CONTROL register. */
" movs r1, #1 \n"/* r1 = 1. */
" bics r0, r1 \n"/* Clear the bit 0. */
@@ -171,6 +175,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" movs r1, #1 \n"/* r1 = 1. */
" orrs r0, r1 \n"/* r0 = r0 | r1. */
@@ -185,6 +191,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
@@ -206,6 +214,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, PRIMASK \n"
" cpsid i \n"
" bx lr \n"
@@ -218,6 +228,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" msr PRIMASK, r0 \n"
" bx lr \n"
::: "memory"
@@ -413,6 +425,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" movs r0, #4 \n"
" mov r1, lr \n"
" tst r0, r1 \n"
@@ -435,6 +449,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" svc %0 \n"/* Secure context is allocated in the supervisor call. */
" bx lr \n"/* Return. */
::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
@@ -446,6 +462,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
" ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
" cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
index 5f7cc2c..6852153 100644
--- a/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,268 +45,27 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M23"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M23"
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
- #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/Source/portable/GCC/ARM_CM23/secure/secure_context.c
index 20ab679..1996693 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_context.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/Source/portable/GCC/ARM_CM23/secure/secure_context.h
index 6ae8580..de33d15 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_context.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
index 2f35d95..3331fc3 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
index 5b56064..b3bf007 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -113,7 +113,8 @@
/**
* @brief Create a couple of list links to mark the start and end of the list.
*/
-static BlockLink_t xStart, * pxEnd = NULL;
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
/**
* @brief Keeps track of the number of free bytes remaining, but says nothing
@@ -245,7 +246,9 @@
void * pvPortMalloc( size_t xWantedSize )
{
- BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
/* If this is the first call to malloc then the heap will require
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
index 796db8a..e469f2c 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/Source/portable/GCC/ARM_CM23/secure/secure_init.c
index aa7150c..f6570d8 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_init.c
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/Source/portable/GCC/ARM_CM23/secure/secure_init.h
index 2725462..e89af71 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_init.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
index 7c3b395..2fb7c59 100644
--- a/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
index babbb74..b668d15 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -132,6 +132,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" movs r1, #1 \n"/* r1 = 1. */
" tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
@@ -152,6 +154,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* Read the CONTROL register. */
" movs r1, #1 \n"/* r1 = 1. */
" bics r0, r1 \n"/* Clear the bit 0. */
@@ -166,6 +170,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" movs r1, #1 \n"/* r1 = 1. */
" orrs r0, r1 \n"/* r0 = r0 | r1. */
@@ -180,6 +186,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
@@ -201,6 +209,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, PRIMASK \n"
" cpsid i \n"
" bx lr \n"
@@ -213,6 +223,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" msr PRIMASK, r0 \n"
" bx lr \n"
::: "memory"
@@ -348,6 +360,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" movs r0, #4 \n"
" mov r1, lr \n"
" tst r0, r1 \n"
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
index 5f7cc2c..6852153 100644
--- a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,268 +45,27 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M23"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __attribute__( ( used ) )
+#define portARCH_NAME "Cortex-M23"
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
- #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/GCC/ARM_CM3/port.c b/Source/portable/GCC/ARM_CM3/port.c
index 60b7a40..a5f4fd5 100644
--- a/Source/portable/GCC/ARM_CM3/port.c
+++ b/Source/portable/GCC/ARM_CM3/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -41,27 +41,18 @@
#define configKERNEL_INTERRUPT_PRIORITY 255
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
@@ -89,12 +80,24 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/* Let the user override the pre-loading of the initial LR with the address of
* prvTaskExitError() in case it messes up unwinding of the stack in the
* debugger. */
@@ -267,66 +270,66 @@
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -455,7 +458,7 @@
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -464,22 +467,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -490,23 +477,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -535,8 +548,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
@@ -556,27 +569,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -590,11 +599,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -605,13 +633,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -629,11 +683,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -642,7 +696,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h
index 410d331..d9c1c1b 100644
--- a/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/port.c b/Source/portable/GCC/ARM_CM33/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
index dfd09a0..3424b42 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -69,6 +69,21 @@
" ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
" \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
@@ -120,6 +135,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
" ite ne \n"
@@ -137,6 +154,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* Read the CONTROL register. */
" bic r0, #1 \n"/* Clear the bit 0. */
" msr control, r0 \n"/* Write back the new CONTROL value. */
@@ -150,6 +169,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" orr r0, #1 \n"/* r0 = r0 | 1. */
" msr control, r0 \n"/* CONTROL = r0. */
@@ -163,6 +184,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
@@ -185,6 +208,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
@@ -200,6 +225,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" msr basepri, r0 \n"/* basepri = ulMask. */
" dsb \n"
" isb \n"
@@ -252,11 +279,11 @@
" save_ns_context: \n"
" ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
" ldr r1, [r3] \n"/* Read pxCurrentTCB. */
- #if ( configENABLE_FPU == 1 )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
" it eq \n"
- " vstmdbeq r2!, {s16-s31} \n"/* Store the FPU registers which are not saved automatically. */
- #endif /* configENABLE_FPU */
+ " vstmdbeq r2!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
" subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
" str r2, [r1] \n"/* Save the new top of stack in TCB. */
@@ -310,6 +337,21 @@
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
" stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
" \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #8 \n"/* r4 = 8. */
+ " str r4, [r3] \n"/* Program RNR = 8. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #12 \n"/* r4 = 12. */
+ " str r4, [r3] \n"/* Program RNR = 12. */
+ " ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
" ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
@@ -356,11 +398,11 @@
" \n"
" restore_ns_context: \n"
" ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
- #if ( configENABLE_FPU == 1 )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
" it eq \n"
- " vldmiaeq r2!, {s16-s31} \n"/* Restore the FPU registers which are not restored automatically. */
- #endif /* configENABLE_FPU */
+ " vldmiaeq r2!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
" msr psp, r2 \n"/* Remember the new top of stack for the task. */
" bx lr \n"
" \n"
@@ -382,6 +424,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
@@ -399,6 +443,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" svc %0 \n"/* Secure context is allocated in the supervisor call. */
" bx lr \n"/* Return. */
::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
@@ -410,6 +456,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
" ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
" cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
index dd0a6ad..82f937a 100644
--- a/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,268 +45,22 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M33"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portARCH_NAME "Cortex-M33"
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() ulSetInterruptMask()
- #define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/Source/portable/GCC/ARM_CM33/secure/secure_context.c
index 20ab679..1996693 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_context.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/Source/portable/GCC/ARM_CM33/secure/secure_context.h
index 6ae8580..de33d15 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_context.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
index a843379..952db8a 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -73,10 +73,10 @@
" cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
" mrs r1, psp \n" /* r1 = PSP. */
" \n"
- #if ( configENABLE_FPU == 1 )
- " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */
- " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */
- #endif /* configENABLE_FPU */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
" \n"
#if ( configENABLE_MPU == 1 )
" mrs r2, control \n" /* r2 = CONTROL. */
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
index 5b56064..b3bf007 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -113,7 +113,8 @@
/**
* @brief Create a couple of list links to mark the start and end of the list.
*/
-static BlockLink_t xStart, * pxEnd = NULL;
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
/**
* @brief Keeps track of the number of free bytes remaining, but says nothing
@@ -245,7 +246,9 @@
void * pvPortMalloc( size_t xWantedSize )
{
- BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
/* If this is the first call to malloc then the heap will require
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
index 796db8a..e469f2c 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/Source/portable/GCC/ARM_CM33/secure/secure_init.c
index aa7150c..f6570d8 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_init.c
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/Source/portable/GCC/ARM_CM33/secure/secure_init.h
index 2725462..e89af71 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_init.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
index 7c3b395..2fb7c59 100644
--- a/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
index b12d212..3a97911 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -69,6 +69,21 @@
" ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
" \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
@@ -115,6 +130,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
" ite ne \n"
@@ -132,6 +149,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* Read the CONTROL register. */
" bic r0, #1 \n"/* Clear the bit 0. */
" msr control, r0 \n"/* Write back the new CONTROL value. */
@@ -145,6 +164,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, control \n"/* r0 = CONTROL. */
" orr r0, #1 \n"/* r0 = r0 | 1. */
" msr control, r0 \n"/* CONTROL = r0. */
@@ -158,6 +179,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
" ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
@@ -180,6 +203,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
" mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
" msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
@@ -195,6 +220,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" msr basepri, r0 \n"/* basepri = ulMask. */
" dsb \n"
" isb \n"
@@ -211,11 +238,11 @@
" .syntax unified \n"
" \n"
" mrs r0, psp \n"/* Read PSP in r0. */
- #if ( configENABLE_FPU == 1 )
- " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
" it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"/* Store the FPU registers which are not saved automatically. */
- #endif /* configENABLE_FPU */
+ " vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
" mrs r1, psplim \n"/* r1 = PSPLIM. */
" mrs r2, control \n"/* r2 = CONTROL. */
@@ -262,6 +289,21 @@
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
" \n"
+ #if ( configTOTAL_MPU_REGIONS == 16 )
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #8 \n"/* r3 = 8. */
+ " str r3, [r2] \n"/* Program RNR = 8. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #12 \n"/* r3 = 12. */
+ " str r3, [r2] \n"/* Program RNR = 12. */
+ " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+ #endif /* configTOTAL_MPU_REGIONS == 16 */
+ " \n"
" ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
@@ -275,11 +317,11 @@
" ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#endif /* configENABLE_MPU */
" \n"
- #if ( configENABLE_FPU == 1 )
- " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
" it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"/* Restore the FPU registers which are not restored automatically. */
- #endif /* configENABLE_FPU */
+ " vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
" \n"
#if ( configENABLE_MPU == 1 )
" msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
@@ -307,6 +349,8 @@
{
__asm volatile
(
+ " .syntax unified \n"
+ " \n"
" tst lr, #4 \n"
" ite eq \n"
" mrseq r0, msp \n"
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
index dd0a6ad..82f937a 100644
--- a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,268 +45,22 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M33"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portARCH_NAME "Cortex-M33"
+#define portDONT_DISCARD __attribute__( ( used ) )
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() ulSetInterruptMask()
- #define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/GCC/ARM_CM3_MPU/port.c b/Source/portable/GCC/ARM_CM3_MPU/port.c
index 04377be..40b38b2 100644
--- a/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ b/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -369,6 +369,7 @@
" ldr r14, =0xfffffffd \n"/* Load exec return code. */
" bx r14 \n"
" \n"
+ " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
@@ -494,15 +495,26 @@
void vPortEnterCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ }
+#else
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -510,10 +522,34 @@
void vPortExitCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ }
+#else
configASSERT( uxCriticalNesting );
uxCriticalNesting--;
@@ -521,9 +557,6 @@
{
portENABLE_INTERRUPTS();
}
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -579,6 +612,7 @@
" msr psp, r0 \n"
" bx r14 \n"
" \n"
+ " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
@@ -660,6 +694,7 @@
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
@@ -754,31 +789,19 @@
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION );
+ ( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
- /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
- * just removed the privileged only parameters. */
- xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
- ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + 1 );
-
- xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate all other regions. */
- for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ /* Invalidate user configurable regions. */
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
}
@@ -797,7 +820,8 @@
( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
( portMPU_REGION_ENABLE );
@@ -805,7 +829,7 @@
lIndex = 0;
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
{
@@ -815,7 +839,7 @@
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + ul ); /* Region number. */
+ ( ul - 1UL ); /* Region number. */
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -825,7 +849,7 @@
else
{
/* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
diff --git a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
index 1e82739..23499eb 100644
--- a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -82,15 +82,15 @@
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 0UL )
- #define portPRIVILEGED_FLASH_REGION ( 1UL )
- #define portPRIVILEGED_RAM_REGION ( 2UL )
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
#define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 5UL )
+ #define portPRIVILEGED_FLASH_REGION ( 6UL )
+ #define portPRIVILEGED_RAM_REGION ( 7UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 0UL )
+ #define portLAST_CONFIGURABLE_REGION ( 2UL )
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+ #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
@@ -103,7 +103,7 @@
/* Plus 1 to create space for the stack region. */
typedef struct MPU_SETTINGS
{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
} xMPU_SETTINGS;
/* Architecture specifics. */
diff --git a/Source/portable/GCC/ARM_CM4F/port.c b/Source/portable/GCC/ARM_CM4F/port.c
index 0f7929c..4c9925c 100644
--- a/Source/portable/GCC/ARM_CM4F/port.c
+++ b/Source/portable/GCC/ARM_CM4F/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -38,27 +38,18 @@
#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
@@ -101,7 +92,19 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
/* Let the user override the pre-loading of the initial LR with the address of
* prvTaskExitError() in case it messes up unwinding of the stack in the
@@ -303,66 +306,66 @@
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -517,7 +520,7 @@
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -526,22 +529,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -552,23 +539,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -597,8 +610,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
@@ -618,27 +631,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -652,11 +661,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -667,13 +695,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -691,11 +745,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -704,7 +758,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM4F/portmacro.h b/Source/portable/GCC/ARM_CM4F/portmacro.h
index 615bb2a..b85a98b 100644
--- a/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM4_MPU/port.c b/Source/portable/GCC/ARM_CM4_MPU/port.c
index c42ea5f..d99b8b4 100644
--- a/Source/portable/GCC/ARM_CM4_MPU/port.c
+++ b/Source/portable/GCC/ARM_CM4_MPU/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -70,12 +70,18 @@
#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
+ * that a work around is active for errata 837070. */
+#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
+
/* Constants required to access and manipulate the MPU. */
#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
#define portMPU_ENABLE ( 0x01UL )
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@@ -374,12 +380,12 @@
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
" \n"
- #if ( portTOTAL_NUM_REGIONS == 16 )
+ #if ( configTOTAL_MPU_REGIONS == 16 )
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
" \n"
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@@ -394,6 +400,7 @@
" msr basepri, r0 \n"
" bx r14 \n"
" \n"
+ " .ltorg \n"/* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
@@ -409,6 +416,18 @@
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+ /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
+ #else
+ /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
+ * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
+ * FreeRTOSConfig.h. */
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ #endif
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -530,15 +549,26 @@
void vPortEnterCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ }
+#else
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -546,10 +576,34 @@
void vPortExitCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ }
+#else
configASSERT( uxCriticalNesting );
uxCriticalNesting--;
@@ -557,9 +611,6 @@
{
portENABLE_INTERRUPTS();
}
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -586,9 +637,15 @@
" \n"
" stmdb sp!, {r0, r3} \n"
" mov r0, %0 \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
" msr basepri, r0 \n"
" dsb \n"
" isb \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
" bl vTaskSwitchContext \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"
@@ -608,12 +665,12 @@
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
" \n"
- #if ( portTOTAL_NUM_REGIONS == 16 )
+ #if ( configTOTAL_MPU_REGIONS == 16 )
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
" \n"
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@@ -631,6 +688,7 @@
" msr psp, r0 \n"
" bx r14 \n"
" \n"
+ " .ltorg \n"/* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
@@ -710,7 +768,7 @@
#endif /* if defined( __ARMCC_VERSION ) */
/* The only permitted number of regions are 8 or 16. */
- configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
@@ -746,6 +804,7 @@
( portPRIVILEGED_RAM_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
@@ -853,31 +912,19 @@
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION );
+ ( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
- /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
- * just removed the privileged only parameters. */
- xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
- ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + 1 );
-
- xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate all other regions. */
- for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ /* Invalidate user configurable regions. */
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
}
@@ -896,7 +943,8 @@
( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( portMPU_REGION_ENABLE );
@@ -904,7 +952,7 @@
lIndex = 0;
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
{
@@ -914,7 +962,7 @@
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + ul ); /* Region number. */
+ ( ul - 1UL ); /* Region number. */
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -924,7 +972,7 @@
else
{
/* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
diff --git a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
index 45a8a09..0e7dd18 100644
--- a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -71,6 +71,7 @@
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
+
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@@ -172,15 +173,15 @@
#define configTEX_S_C_B_SRAM ( 0x07UL )
#endif
-#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
-#define portPRIVILEGED_FLASH_REGION ( 1UL )
-#define portPRIVILEGED_RAM_REGION ( 2UL )
-#define portGENERAL_PERIPHERALS_REGION ( 3UL )
-#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
-#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
-#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
-#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
+#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
+#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
+#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
+#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
+#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portFIRST_CONFIGURABLE_REGION ( 0UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
+#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
+#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
@@ -190,10 +191,9 @@
uint32_t ulRegionAttribute;
} xMPU_REGION_REGISTERS;
-/* Plus 1 to create space for the stack region. */
typedef struct MPU_SETTINGS
{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
} xMPU_SETTINGS;
/* Architecture specifics. */
@@ -346,10 +346,16 @@
__asm volatile
(
- " mov %0, %1 \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
+ " mov %0, %1 \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ " msr basepri, %0 \n"
+ " isb \n"
+ " dsb \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
@@ -362,11 +368,17 @@
__asm volatile
(
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
+ " mrs %0, basepri \n"
+ " mov %1, %2 \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
+ " msr basepri, %1 \n"
+ " isb \n"
+ " dsb \n"
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
diff --git a/Source/portable/GCC/ARM_CM7/r0p1/port.c b/Source/portable/GCC/ARM_CM7/r0p1/port.c
index f7f7335..bbba49e 100644
--- a/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -38,27 +38,18 @@
#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
@@ -95,7 +86,19 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
+
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
/* Let the user override the pre-loading of the initial LR with the address of
* prvTaskExitError() in case it messes up unwinding of the stack in the
@@ -291,66 +294,66 @@
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -445,11 +448,11 @@
" \n"
" stmdb sp!, {r0, r3} \n"
" mov r0, %0 \n"
- " cpsid i \n"/* Errata workaround. */
+ " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
" msr basepri, r0 \n"
" dsb \n"
" isb \n"
- " cpsie i \n"/* Errata workaround. */
+ " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
" bl vTaskSwitchContext \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"
@@ -507,7 +510,7 @@
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -516,22 +519,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -542,23 +529,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -587,8 +600,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
@@ -608,27 +621,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -642,11 +651,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -657,13 +685,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -681,11 +735,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -694,7 +748,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
index e304b10..c66c6d0 100644
--- a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/GCC/ARM_CM7_MPU/ReadMe.txt b/Source/portable/GCC/ARM_CM7_MPU/ReadMe.txt
deleted file mode 100644
index ff4e74c..0000000
--- a/Source/portable/GCC/ARM_CM7_MPU/ReadMe.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
-The best option depends on the revision of the ARM Cortex-M7 core in use. The
-revision is specified by an 'r' number, and a 'p' number, so will look something
-like 'r0p1'. Check the documentation for the microcontroller in use to find the
-revision of the Cortex-M7 core used in that microcontroller. If in doubt, use
-the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
-with all core revisions.
-
-The first option is to use the ARM Cortex-M4F port, and the second option is to
-use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
-
-If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
-used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in
-the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.
-
-If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
-Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7_GCC/r0p1
-directory.
diff --git a/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c b/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
deleted file mode 100644
index c42ea5f..0000000
--- a/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
+++ /dev/null
@@ -1,996 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.6
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM4 MPU port.
-*----------------------------------------------------------*/
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
- #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK ( 0 )
-#endif
-
-#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
- #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
- #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
-#endif
-
-/* Constants required to access and manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
-#define portMPU_ENABLE ( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
-#define portMPU_REGION_VALID ( 0x10UL )
-#define portMPU_REGION_ENABLE ( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS 0x40000000UL
-#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
-
-/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_INT ( 0x00000002UL )
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000UL )
-#define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC ( 6 )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into. The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Standard FreeRTOS exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
-void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/*
- * Starts the scheduler by restoring the context of the first task to run.
- */
-static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
-
-/*
- * C portion of the SVC handler. The SVC handler is split between an asm entry
- * and a C wrapper for simplicity of coding and maintenance.
- */
-static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__( ( naked ) );
-
-/**
- * @brief Enter critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * @brief Exit from critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. Note this is not saved as part of the task context as context
- * switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters,
- BaseType_t xRunPrivileged )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = 0; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
- /* A save method is being used that requires each task to maintain its
- * own exec return value. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN;
-
- pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
- }
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
- /* Assumes psp was in use. */
- __asm volatile
- (
- #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
- " tst lr, #4 \n"
- " ite eq \n"
- " mrseq r0, msp \n"
- " mrsne r0, psp \n"
- #else
- " mrs r0, psp \n"
- #endif
- " b %0 \n"
- ::"i" ( prvSVCHandler ) : "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSVCHandler( uint32_t * pulParam )
-{
- uint8_t ucSVCNumber;
- uint32_t ulPC;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- #if defined( __ARMCC_VERSION )
-
- /* Declaration when these variable are defined in code instead of being
- * exported from linker scripts. */
- extern uint32_t * __syscalls_flash_start__;
- extern uint32_t * __syscalls_flash_end__;
- #else
- /* Declaration when these variable are exported from linker scripts. */
- extern uint32_t __syscalls_flash_start__[];
- extern uint32_t __syscalls_flash_end__[];
- #endif /* #if defined( __ARMCC_VERSION ) */
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
- * argument (r0) is pulParam[ 0 ]. */
- ulPC = pulParam[ portOFFSET_TO_PC ];
- ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
-
- switch( ucSVCNumber )
- {
- case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
- prvRestoreContextOfFirstTask();
- break;
-
- case portSVC_YIELD:
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
- /* Barriers are normally not required
- * but do ensure the code is completely
- * within the specified behaviour for the
- * architecture. */
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-
- break;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
- * svc was raised from any of the
- * system calls. */
-
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- }
-
- break;
- #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
- case portSVC_RAISE_PRIVILEGE:
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- break;
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- default: /* Unknown SVC call. */
- break;
- }
-}
-/*-----------------------------------------------------------*/
-
-static void prvRestoreContextOfFirstTask( void )
-{
- __asm volatile
- (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
- " ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
- " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
- " \n"
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " \n"
- #if ( portTOTAL_NUM_REGIONS == 16 )
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
- " \n"
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- " \n"
- " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */
- " msr control, r3 \n"
- " msr psp, r0 \n"/* Restore the task stack pointer. */
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the same priority as the kernel, and the SVC
- * handler higher priority so it can be used to exit a critical section (where
- * lower priorities are masked). */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Configure the regions in the MPU that are common to all tasks. */
- prvSetupMPU();
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Ensure the VFP is enabled - it should be anyway. */
- vPortEnableVFP();
-
- /* Lazy save always. */
- *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
- /* Start the first task. This also clears the bit that indicates the FPU is
- * in use in case the FPU was used before the scheduler was started - which
- * would otherwise result in the unnecessary leaving of space in the SVC stack
- * for lazy saving of FPU registers. */
- __asm volatile (
- " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
- " ldr r0, [r0] \n"
- " ldr r0, [r0] \n"
- " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
- " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */
- " msr control, r0 \n"
- " cpsie i \n"/* Globally enable interrupts. */
- " cpsie f \n"
- " dsb \n"
- " isb \n"
- " svc %0 \n"/* System call to start first task. */
- " nop \n"
- " .ltorg \n"
- ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
-
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
-
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
- /* This is a naked function. */
-
- __asm volatile
- (
- " mrs r0, psp \n"
- " isb \n"
- " \n"
- " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
- " ldr r2, [r3] \n"
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */
- " it eq \n"
- " vstmdbeq r0!, {s16-s31} \n"
- " \n"
- " mrs r1, control \n"
- " stmdb r0!, {r1, r4-r11, r14} \n"/* Save the remaining registers. */
- " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
- " \n"
- " stmdb sp!, {r0, r3} \n"
- " mov r0, %0 \n"
- " msr basepri, r0 \n"
- " dsb \n"
- " isb \n"
- " bl vTaskSwitchContext \n"
- " mov r0, #0 \n"
- " msr basepri, r0 \n"
- " ldmia sp!, {r0, r3} \n"
- " \n"/* Restore the context. */
- " ldr r1, [r3] \n"
- " ldr r0, [r1] \n"/* The first item in the TCB is the task top of stack. */
- " add r1, r1, #4 \n"/* Move onto the second item in the TCB... */
- " \n"
- " dmb \n"/* Complete outstanding transfers before disabling MPU. */
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " bic r3, #1 \n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- " str r3, [r2] \n"/* Disable MPU. */
- " \n"
- " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- " \n"
- #if ( portTOTAL_NUM_REGIONS == 16 )
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- " ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- " stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
- " \n"
- " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
- " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
- " orr r3, #1 \n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- " str r3, [r2] \n"/* Enable MPU. */
- " dsb \n"/* Force memory writes before continuing. */
- " \n"
- " ldmia r0!, {r3-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry. */
- " msr control, r3 \n"
- " \n"
- " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */
- " it eq \n"
- " vldmiaeq r0!, {s16-s31} \n"
- " \n"
- " msr psp, r0 \n"
- " bx r14 \n"
- " \n"
- " .align 4 \n"
- "pxCurrentTCBConst: .word pxCurrentTCB \n"
- ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
- );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- uint32_t ulDummy;
-
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
-{
- /* Stop and clear the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
- __asm volatile
- (
- " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */
- " ldr r1, [r0] \n"
- " \n"
- " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */
- " str r1, [r0] \n"
- " bx r14 \n"
- " .ltorg \n"
- );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
- #if defined( __ARMCC_VERSION )
-
- /* Declaration when these variable are defined in code instead of being
- * exported from linker scripts. */
- extern uint32_t * __privileged_functions_start__;
- extern uint32_t * __privileged_functions_end__;
- extern uint32_t * __FLASH_segment_start__;
- extern uint32_t * __FLASH_segment_end__;
- extern uint32_t * __privileged_data_start__;
- extern uint32_t * __privileged_data_end__;
- #else
- /* Declaration when these variable are exported from linker scripts. */
- extern uint32_t __privileged_functions_start__[];
- extern uint32_t __privileged_functions_end__[];
- extern uint32_t __FLASH_segment_start__[];
- extern uint32_t __FLASH_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
- #endif /* if defined( __ARMCC_VERSION ) */
-
- /* The only permitted number of regions are 8 or 16. */
- configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
-
- /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
- configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
-
- /* Check the expected MPU is present. */
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
- {
- /* First setup the unprivileged flash for unprivileged read only access. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portUNPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged flash for privileged only access. This is where
- * the kernel code is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged data RAM region. This is where the kernel data
- * is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_RAM_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* By default allow everything to access the general peripherals. The
- * system peripherals and registers are protected. */
- portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
- ( portMPU_REGION_VALID ) |
- ( portGENERAL_PERIPHERALS_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Enable the memory fault exception. */
- portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
- /* Enable the MPU with the background region configured. */
- portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
- }
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
- uint32_t ulRegionSize, ulReturnValue = 4;
-
- /* 32 is the smallest region size, 31 is the largest valid value for
- * ulReturnValue. */
- for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
- {
- if( ulActualSizeInBytes <= ulRegionSize )
- {
- break;
- }
- else
- {
- ulReturnValue++;
- }
- }
-
- /* Shift the code by one before returning so it can be written directly
- * into the the correct bit position of the attribute register. */
- return( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " mrs r0, control \n"/* r0 = CONTROL. */
- " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- " ite ne \n"
- " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- " bx lr \n"/* Return. */
- " \n"
- " .align 4 \n"
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
- __asm volatile
- (
- " mrs r0, control \n"/* r0 = CONTROL. */
- " orr r0, #1 \n"/* r0 = r0 | 1. */
- " msr control, r0 \n"/* CONTROL = r0. */
- " bx lr \n"/* Return to the caller. */
- ::: "r0", "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
- const struct xMEMORY_REGION * const xRegions,
- StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
-{
- #if defined( __ARMCC_VERSION )
-
- /* Declaration when these variable are defined in code instead of being
- * exported from linker scripts. */
- extern uint32_t * __SRAM_segment_start__;
- extern uint32_t * __SRAM_segment_end__;
- extern uint32_t * __privileged_data_start__;
- extern uint32_t * __privileged_data_end__;
- #else
- /* Declaration when these variable are exported from linker scripts. */
- extern uint32_t __SRAM_segment_start__[];
- extern uint32_t __SRAM_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
- #endif /* if defined( __ARMCC_VERSION ) */
-
- int32_t lIndex;
- uint32_t ul;
-
- if( xRegions == NULL )
- {
- /* No MPU regions are specified so allow access to all RAM. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION );
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
- * just removed the privileged only parameters. */
- xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
- ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + 1 );
-
- xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate all other regions. */
- for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
- }
- else
- {
- /* This function is called automatically when the task is created - in
- * which case the stack region parameters will be valid. At all other
- * times the stack parameters will not be valid and it is assumed that the
- * stack region has already been configured. */
- if( ulStackDepth > 0 )
- {
- /* Define the region that allows access to the stack. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) pxBottomOfStack ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( portMPU_REGION_ENABLE );
- }
-
- lIndex = 0;
-
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
- {
- /* Translate the generic region definition contained in
- * xRegions into the CM4 specific MPU settings that are then
- * stored in xMPUSettings. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
- ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + ul ); /* Region number. */
-
- xMPUSettings->xRegion[ ul ].ulRegionAttribute =
- ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
- ( xRegions[ lIndex ].ulParameters ) |
- ( portMPU_REGION_ENABLE );
- }
- else
- {
- /* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
-
- lIndex++;
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredicable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h b/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
deleted file mode 100644
index 560131a..0000000
--- a/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.6
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
- extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS 1
-#define portPRIVILEGE_BIT ( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
-
-/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
- * Register (RASR). */
-#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
-#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
-
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
-#ifndef configTOTAL_MPU_REGIONS
- /* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
-#endif
-
-/*
- * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
- * memory type, and where necessary the cacheable and shareable properties
- * of the memory region.
- *
- * The TEX, C, and B bits together indicate the memory type of the region,
- * and:
- * - For Normal memory, the cacheable properties of the region.
- * - For Device memory, whether the region is shareable.
- *
- * For Normal memory regions, the S bit indicates whether the region is
- * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
- *
- * See the following two tables for setting TEX, S, C and B bits for
- * unprivileged flash, privileged flash and privileged RAM regions.
- *
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 1 | Device | Shared device | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 1 | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 011 | X | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
- | | | | | outer cacheability rules that must be exported on the | |
- | | | | | bus. See the table below for the cacheability policy | |
- | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- |
- +-----------------------------------------+----------------------------------------+
- | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
- +-----------------------------------------+----------------------------------------+
- | 00 | Non-cacheable |
- +-----------------------------------------+----------------------------------------+
- | 01 | Write-back, write and read allocate |
- +-----------------------------------------+----------------------------------------+
- | 10 | Write-through, no write allocate |
- +-----------------------------------------+----------------------------------------+
- | 11 | Write-back, no write allocate |
- +-----------------------------------------+----------------------------------------+
- */
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
- * region. */
-#ifndef configTEX_S_C_B_FLASH
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_FLASH ( 0x07UL )
-#endif
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
- * region. */
-#ifndef configTEX_S_C_B_SRAM
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_SRAM ( 0x07UL )
-#endif
-
-#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
-#define portPRIVILEGED_FLASH_REGION ( 1UL )
-#define portPRIVILEGED_RAM_REGION ( 2UL )
-#define portGENERAL_PERIPHERALS_REGION ( 3UL )
-#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
-#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
-#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
-#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
-
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
-typedef struct MPU_REGION_REGISTERS
-{
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
-typedef struct MPU_SETTINGS
-{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
-} xMPU_SETTINGS;
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-#define portDONT_DISCARD __attribute__( ( used ) )
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER 0
-#define portSVC_YIELD 1
-#define portSVC_RAISE_PRIVILEGE 2
-
-/* Scheduler utilities. */
-
-#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
-#define portYIELD_WITHIN_API() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- \
- /* Barriers are normally not required but do ensure the code is completely \
- * within the specified behaviour for the architecture. */ \
- __asm volatile ( "dsb" ::: "memory" ); \
- __asm volatile ( "isb" ); \
- }
-
-#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
-#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Generic helper function. */
- __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
- {
- uint8_t ucReturn;
-
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-
- return ucReturn;
- }
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
-#endif
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- */
-#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE() vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-{
- uint32_t ulNewBASEPRI;
-
- __asm volatile
- (
- " mov %0, %1 \n"\
- " cpsid i \n"\
- " msr basepri, %0 \n"\
- " isb \n"\
- " dsb \n"\
- " cpsie i \n"\
- : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-{
- uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
- __asm volatile
- (
- " mrs %0, basepri \n"\
- " mov %1, %2 \n"\
- " cpsid i \n"\
- " msr basepri, %1 \n"\
- " isb \n"\
- " dsb \n"\
- " cpsie i \n"\
- : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
- );
-
- /* This return will not be reached but is necessary to prevent compiler
- * warnings. */
- return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-{
- __asm volatile
- (
- " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
- );
-}
-/*-----------------------------------------------------------*/
-
-#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
-
-#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
-#endif
-/*-----------------------------------------------------------*/
-
-/* *INDENT-OFF* */
- #ifdef __cplusplus
- }
- #endif
-/* *INDENT-ON* */
-
-#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM0/port.c b/Source/portable/IAR/ARM_CM0/port.c
index 1bd4ac6..6fed504 100644
--- a/Source/portable/IAR/ARM_CM0/port.c
+++ b/Source/portable/IAR/ARM_CM0/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -47,6 +47,8 @@
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
@@ -72,7 +74,7 @@
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
#ifndef portMISSED_COUNTS_FACTOR
- #define portMISSED_COUNTS_FACTOR ( 45UL )
+ #define portMISSED_COUNTS_FACTOR ( 94UL )
#endif
/* The number of SysTick increments that make up one tick period. */
@@ -92,6 +94,18 @@
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
@@ -246,11 +260,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -258,8 +272,8 @@
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
@@ -267,7 +281,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -276,22 +290,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_interrupt();
@@ -302,23 +300,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_interrupt()
+ /* Re-enable interrupts - see comments above the __disable_interrupt()
* call above. */
__enable_interrupt();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -347,8 +371,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_interrupt() call above. */
__enable_interrupt();
__DSB();
__ISB();
@@ -368,27 +392,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -402,11 +422,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -417,15 +456,41 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
- /* Exit with interrpts enabled. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
__enable_interrupt();
}
}
diff --git a/Source/portable/IAR/ARM_CM0/portasm.s b/Source/portable/IAR/ARM_CM0/portasm.s
index 28eea1d..4e6ea5b 100644
--- a/Source/portable/IAR/ARM_CM0/portasm.s
+++ b/Source/portable/IAR/ARM_CM0/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM0/portmacro.h b/Source/portable/IAR/ARM_CM0/portmacro.h
index 5ca772a..d5f8f82 100644
--- a/Source/portable/IAR/ARM_CM0/portmacro.h
+++ b/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -26,7 +26,6 @@
*
*/
-
#ifndef PORTMACRO_H
#define PORTMACRO_H
@@ -80,8 +79,8 @@
/* Scheduler utilities. */
extern void vPortYield( void );
- #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
- #define portNVIC_PENDSVSET 0x10000000
+ #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+ #define portNVIC_PENDSVSET 0x10000000
#define portYIELD() vPortYield()
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/port.c b/Source/portable/IAR/ARM_CM23/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
index a59e661..6e658f8 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
index b4f7292..f31bd3f 100644
--- a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,275 +45,34 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M23"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
- #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Be006
- #pragma diag_suppress=Pa082
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
/*-----------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/Source/portable/IAR/ARM_CM23/secure/secure_context.c
index 20ab679..1996693 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_context.c
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/Source/portable/IAR/ARM_CM23/secure/secure_context.h
index 6ae8580..de33d15 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_context.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
index 4713d71..aee841a 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
index 5b56064..b3bf007 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -113,7 +113,8 @@
/**
* @brief Create a couple of list links to mark the start and end of the list.
*/
-static BlockLink_t xStart, * pxEnd = NULL;
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
/**
* @brief Keeps track of the number of free bytes remaining, but says nothing
@@ -245,7 +246,9 @@
void * pvPortMalloc( size_t xWantedSize )
{
- BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
/* If this is the first call to malloc then the heap will require
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
index 796db8a..e469f2c 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/Source/portable/IAR/ARM_CM23/secure/secure_init.c
index aa7150c..f6570d8 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_init.c
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/Source/portable/IAR/ARM_CM23/secure/secure_init.h
index 2725462..e89af71 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_init.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
index 7c3b395..2fb7c59 100644
--- a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
index af90b9e..9850588 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
index 1f1e026..f31bd3f 100644
--- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,275 +45,34 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M23"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M23"
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
- #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Be006
- #pragma diag_suppress=Pa082
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
/*-----------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/IAR/ARM_CM3/port.c b/Source/portable/IAR/ARM_CM3/port.c
index ab82102..17eaa63 100644
--- a/Source/portable/IAR/ARM_CM3/port.c
+++ b/Source/portable/IAR/ARM_CM3/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -41,27 +41,18 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
@@ -89,7 +80,7 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
@@ -102,6 +93,18 @@
#define configKERNEL_INTERRUPT_PRIORITY 255
#endif
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
@@ -216,66 +219,66 @@
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -358,7 +361,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -367,22 +370,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_interrupt();
@@ -393,23 +380,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_interrupt()
+ /* Re-enable interrupts - see comments above the __disable_interrupt()
* call above. */
__enable_interrupt();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -438,8 +451,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_interrupt() call above. */
__enable_interrupt();
__DSB();
__ISB();
@@ -459,27 +472,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -493,11 +502,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -508,13 +536,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__enable_interrupt();
@@ -532,11 +586,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -545,7 +599,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM3/portasm.s b/Source/portable/IAR/ARM_CM3/portasm.s
index 093252e..b53183e 100644
--- a/Source/portable/IAR/ARM_CM3/portasm.s
+++ b/Source/portable/IAR/ARM_CM3/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM3/portmacro.h b/Source/portable/IAR/ARM_CM3/portmacro.h
index 132263c..9e4ada4 100644
--- a/Source/portable/IAR/ARM_CM3/portmacro.h
+++ b/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/port.c b/Source/portable/IAR/ARM_CM33/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
index 2ddec67..2f0fb7e 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -219,11 +219,11 @@
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
- #if ( configENABLE_FPU == 1 )
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
- vstmdbeq r2!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
- #endif /* configENABLE_FPU */
+ vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
@@ -323,11 +323,11 @@
restore_ns_context:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
- #if ( configENABLE_FPU == 1 )
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
- vldmiaeq r2!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
- #endif /* configENABLE_FPU */
+ vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
+ #endif /* configENABLE_FPU || configENABLE_MVE */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
index c1aef9d..3575c1f 100644
--- a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,275 +45,34 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M33"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M33"
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() ulSetInterruptMask()
- #define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Be006
- #pragma diag_suppress=Pa082
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
/*-----------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/Source/portable/IAR/ARM_CM33/secure/secure_context.c
index 20ab679..1996693 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_context.c
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/Source/portable/IAR/ARM_CM33/secure/secure_context.h
index 6ae8580..de33d15 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_context.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
index f88fb28..4e26cf9 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -64,10 +64,10 @@
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
-#if ( configENABLE_FPU == 1 )
- vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */
- vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */
-#endif /* configENABLE_FPU */
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
+ vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
index 5b56064..b3bf007 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -113,7 +113,8 @@
/**
* @brief Create a couple of list links to mark the start and end of the list.
*/
-static BlockLink_t xStart, * pxEnd = NULL;
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
/**
* @brief Keeps track of the number of free bytes remaining, but says nothing
@@ -245,7 +246,9 @@
void * pvPortMalloc( size_t xWantedSize )
{
- BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
/* If this is the first call to malloc then the heap will require
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
index 796db8a..e469f2c 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/Source/portable/IAR/ARM_CM33/secure/secure_init.c
index aa7150c..f6570d8 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_init.c
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/Source/portable/IAR/ARM_CM33/secure/secure_init.h
index 2725462..e89af71 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_init.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
index 7c3b395..2fb7c59 100644
--- a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
index df68896..349aeff 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -78,20 +78,13 @@
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the
- * same a the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
/*-----------------------------------------------------------*/
/**
@@ -184,7 +177,7 @@
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/*-----------------------------------------------------------*/
/**
@@ -199,7 +192,7 @@
* have occurred while the SysTick counter is stopped during tickless idle
* calculations.
*/
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/*-----------------------------------------------------------*/
/**
@@ -259,6 +252,20 @@
#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
/**
+ * @brief Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register.
+ */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
+/**
* @brief Let the user override the pre-loading of the initial LR with the
* address of prvTaskExitError() in case it messes up unwinding of the stack
* in the debugger.
@@ -386,7 +393,7 @@
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -395,22 +402,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for is
- * accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
@@ -418,26 +409,52 @@
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
- * to be un-suspended then abandon the low power entry. */
+ * to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above the cpsid instruction()
+ /* Re-enable interrupts - see comments above the cpsid instruction
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -448,12 +465,11 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
- * set its parameter to 0 to indicate that its implementation
- * contains its own wait for interrupt or wait for event
- * instruction, and so wfi should not be executed again. However,
- * the original expected idle time variable must remain unmodified,
- * so a copy is taken. */
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ * set its parameter to 0 to indicate that its implementation contains
+ * its own wait for interrupt or wait for event instruction, and so wfi
+ * should not be executed again. However, the original expected idle
+ * time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -467,48 +483,44 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. See comments above
+ * out of sleep mode to execute immediately. See comments above
* the cpsid instruction above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
- * and interrupts that execute while the clock is stopped will
- * increase any slippage between the time maintained by the RTOS and
- * calendar time. */
+ * and interrupts that execute while the clock is stopped will increase
+ * any slippage between the time maintained by the RTOS and calendar
+ * time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
- * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
- * Again, the time the SysTick is stopped for is accounted for as
- * best it can be, but using the tickless mode will inevitably
- * result in some tiny drift of the time maintained by the kernel
- * with respect to calendar time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ * the time the SysTick is stopped for is accounted for as best it can
+ * be, but using the tickless mode will inevitably result in some tiny
+ * drift of the time maintained by the kernel with respect to calendar
+ * time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is
- * yet to count to zero (in which case an interrupt other than the
- * SysTick must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,17 +528,36 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
- * function exits, the tick value maintained by the tick is
- * stepped forward by one less than the time spent waiting. */
+ * function exits, the tick value maintained by the tick is stepped
+ * forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -537,13 +568,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
@@ -556,11 +613,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
@@ -569,7 +626,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
@@ -625,6 +682,12 @@
extern uint32_t __privileged_sram_end__[];
#endif /* defined( __ARMCC_VERSION ) */
+ /* The only permitted number of regions are 8 or 16. */
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
+
+ /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+ configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
@@ -688,10 +751,10 @@
static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
{
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* Enable non-secure access to the FPU. */
- SecureInit_EnableNSFPUAccess();
- }
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
#endif /* configENABLE_TRUSTZONE */
/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
@@ -804,22 +867,22 @@
ulR0 = pulCallerStackAddress[ 0 ];
#if ( configENABLE_MPU == 1 )
- {
- /* Read the CONTROL register value. */
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
- /* The task that raised the SVC is privileged if Bit[0]
- * in the CONTROL register is 0. */
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
- }
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
+ }
#else /* if ( configENABLE_MPU == 1 ) */
- {
- /* Allocate and load a context for the secure task. */
- xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
- }
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
+ }
#endif /* configENABLE_MPU */
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
@@ -827,6 +890,7 @@
break;
case portSVC_FREE_SECURE_CONTEXT:
+
/* R0 contains TCB being freed and R1 contains the secure
* context handle to be freed. */
ulR0 = pulCallerStackAddress[ 0 ];
@@ -839,21 +903,21 @@
case portSVC_START_SCHEDULER:
#if ( configENABLE_TRUSTZONE == 1 )
- {
- /* De-prioritize the non-secure exceptions so that the
- * non-secure pendSV runs at the lowest priority. */
- SecureInit_DePrioritizeNSExceptions();
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
- /* Initialize the secure context management system. */
- SecureContext_Init();
- }
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
#endif /* configENABLE_TRUSTZONE */
#if ( configENABLE_FPU == 1 )
- {
- /* Setup the Floating Point Unit (FPU). */
- prvSetupFPU();
- }
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
#endif /* configENABLE_FPU */
/* Setup the context of the first task so that the first task starts
@@ -898,105 +962,105 @@
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
#if ( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
- *pxTopOfStack = portINITIAL_EXC_RETURN;
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if ( configENABLE_MPU == 1 )
{
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
- #if ( configENABLE_MPU == 1 )
- {
- pxTopOfStack--;
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
- }
- }
- #endif /* configENABLE_MPU */
-
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
-
- #if ( configENABLE_TRUSTZONE == 1 )
- {
- pxTopOfStack--;
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
- }
- #endif /* configENABLE_TRUSTZONE */
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
}
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
#endif /* portPRELOAD_REGISTERS */
return pxTopOfStack;
@@ -1010,10 +1074,10 @@
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
#if ( configENABLE_MPU == 1 )
- {
- /* Setup the Memory Protection Unit (MPU). */
- prvSetupMPU();
- }
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
#endif /* configENABLE_MPU */
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -1156,7 +1220,7 @@
}
else
{
- /* Attr1 in MAIR0 is configured as normal memory. */
+ /* Attr0 in MAIR0 is configured as normal memory. */
xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
}
}
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
index 129cd47..93606b1 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
index c48b478..4d02a43 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -171,11 +171,11 @@
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
-#if ( configENABLE_FPU == 1 )
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
- vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
-#endif /* configENABLE_FPU */
+ vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
mrs r1, psplim /* r1 = PSPLIM. */
mrs r2, control /* r2 = CONTROL. */
@@ -235,11 +235,11 @@
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#endif /* configENABLE_MPU */
-#if ( configENABLE_FPU == 1 )
- tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
- vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
-#endif /* configENABLE_FPU */
+ vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
index c1aef9d..3575c1f 100644
--- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -27,11 +27,13 @@
*/
#ifndef PORTMACRO_H
- #define PORTMACRO_H
+#define PORTMACRO_H
- #ifdef __cplusplus
- extern "C" {
- #endif
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "portmacrocommon.h"
/*------------------------------------------------------------------------------
* Port specific definitions.
@@ -43,275 +45,34 @@
*------------------------------------------------------------------------------
*/
- #ifndef configENABLE_FPU
- #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
- #endif /* configENABLE_FPU */
-
- #ifndef configENABLE_MPU
- #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
- #endif /* configENABLE_MPU */
-
- #ifndef configENABLE_TRUSTZONE
- #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
- #endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
- #define portCHAR char
- #define portFLOAT float
- #define portDOUBLE double
- #define portLONG long
- #define portSHORT short
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE long
-
- typedef portSTACK_TYPE StackType_t;
- typedef long BaseType_t;
- typedef unsigned long UBaseType_t;
-
- #if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
- #else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
- #endif
-/*-----------------------------------------------------------*/
-
/**
* Architecture specifics.
*/
- #define portARCH_NAME "Cortex-M33"
- #define portSTACK_GROWTH ( -1 )
- #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
- #define portBYTE_ALIGNMENT 8
- #define portNOP()
- #define portINLINE __inline
- #ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
- #endif
- #define portHAS_STACK_OVERFLOW_CHECKING 1
- #define portDONT_DISCARD __root
+#define portARCH_NAME "Cortex-M33"
+#define portDONT_DISCARD __root
/*-----------------------------------------------------------*/
-/**
- * @brief Extern declarations.
- */
- extern BaseType_t xPortIsInsideInterrupt( void );
-
- extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
- extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
- extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
- extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
- extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
- #if ( configENABLE_TRUSTZONE == 1 )
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
- extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
- #endif /* configENABLE_TRUSTZONE */
-
- #if ( configENABLE_MPU == 1 )
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
- #if ( configENABLE_MPU == 1 )
- #define portUSING_MPU_WRAPPERS 1
- #define portPRIVILEGE_BIT ( 0x80000000UL )
- #else
- #define portPRIVILEGE_BIT ( 0x0UL )
- #endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
- #define portPRIVILEGED_FLASH_REGION ( 0UL )
- #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
- #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
- #define portPRIVILEGED_RAM_REGION ( 3UL )
- #define portSTACK_REGION ( 4UL )
- #define portFIRST_CONFIGURABLE_REGION ( 5UL )
- #define portLAST_CONFIGURABLE_REGION ( 7UL )
- #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
- #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- * Bit[7:4] - 0000 - Device Memory
- * Bit[3:2] - 00 --> Device-nGnRnE
- * 01 --> Device-nGnRE
- * 10 --> Device-nGRE
- * 11 --> Device-GRE
- * Bit[1:0] - 00, Reserved.
- */
- #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
- #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
- #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
- #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
- #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
- #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
- #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
- #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
- #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
-
- #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
- #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
- #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
- #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
-
- #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
- typedef struct MPURegionSettings
- {
- uint32_t ulRBAR; /**< RBAR for the region. */
- uint32_t ulRLAR; /**< RLAR for the region. */
- } MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
- typedef struct MPU_SETTINGS
- {
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
- } xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
- #define portSVC_ALLOCATE_SECURE_CONTEXT 0
- #define portSVC_FREE_SECURE_CONTEXT 1
- #define portSVC_START_SCHEDULER 2
- #define portSVC_RAISE_PRIVILEGE 3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
- #define portYIELD() vPortYield()
- #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
- #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
- #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
- #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if( configTOTAL_MPU_REGIONS == 16 )
+ #error 16 MPU regions are not yet supported for this port.
+#endif
/*-----------------------------------------------------------*/
/**
* @brief Critical section management.
*/
- #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
- #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
- #define portDISABLE_INTERRUPTS() ulSetInterruptMask()
- #define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
- #define portENTER_CRITICAL() vPortEnterCritical()
- #define portEXIT_CRITICAL() vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Tickless idle/low power functionality.
- */
- #ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
- #endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
- #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
- #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_TRUSTZONE == 1 )
-
-/**
- * @brief Allocate a secure context for the task.
- *
- * Tasks are not created with a secure context. Any task that is going to call
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
- * secure context before it calls any secure function.
- *
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
- */
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
-
-/**
- * @brief Called when a task is deleted to delete the task's secure context,
- * if it has one.
- *
- * @param[in] pxTCB The TCB of the task being deleted.
- */
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
- #endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
- #if ( configENABLE_MPU == 1 )
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
- #define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- *
- * The SVC handler checks that the SVC was raised from a system call and only
- * then it raises the privilege. If this is called from any other place,
- * the privilege is not raised.
- */
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
- #define portRESET_PRIVILEGE() vResetPrivilege()
- #else
- #define portIS_PRIVILEGED()
- #define portRAISE_PRIVILEGE()
- #define portRESET_PRIVILEGE()
- #endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
- #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS() ulSetInterruptMask()
+#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 )
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
* the source code because to do so would cause other compilers to generate
* warnings. */
- #pragma diag_suppress=Be006
- #pragma diag_suppress=Pa082
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
/*-----------------------------------------------------------*/
- #ifdef __cplusplus
- }
- #endif
+#ifdef __cplusplus
+ }
+#endif
#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
new file mode 100644
index 0000000..e68692a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+ #define PORTMACROCOMMON_H
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+ #ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+ #endif /* configENABLE_FPU */
+
+ #ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+ #endif /* configENABLE_MPU */
+
+ #ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+ #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+ #define portCHAR char
+ #define portFLOAT float
+ #define portDOUBLE double
+ #define portLONG long
+ #define portSHORT short
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE long
+
+ typedef portSTACK_TYPE StackType_t;
+ typedef long BaseType_t;
+ typedef unsigned long UBaseType_t;
+
+ #if ( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+ #else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+ #define portSTACK_GROWTH ( -1 )
+ #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+ #define portBYTE_ALIGNMENT 8
+ #define portNOP()
+ #define portINLINE __inline
+ #ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
+ #endif
+ #define portHAS_STACK_OVERFLOW_CHECKING 1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+ extern BaseType_t xPortIsInsideInterrupt( void );
+
+ extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+ extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if ( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+ #if ( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+ #else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+ #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+ /* Define to 8 for backward compatibility. */
+ #define configTOTAL_MPU_REGIONS ( 8UL )
+#endif
+
+/* MPU regions. */
+ #define portPRIVILEGED_FLASH_REGION ( 0UL )
+ #define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+ #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+ #define portPRIVILEGED_RAM_REGION ( 3UL )
+ #define portSTACK_REGION ( 4UL )
+ #define portFIRST_CONFIGURABLE_REGION ( 5UL )
+ #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+ #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+ #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+ #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+ #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+ #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+ #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+ #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+ #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+ #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+ #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+ #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+ #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+ #define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+ #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+ #define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+ #define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+ typedef struct MPURegionSettings
+ {
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+ } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+ typedef struct MPU_SETTINGS
+ {
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+ } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+ #define portSVC_ALLOCATE_SECURE_CONTEXT 0
+ #define portSVC_FREE_SECURE_CONTEXT 1
+ #define portSVC_START_SCHEDULER 2
+ #define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+ #define portYIELD() vPortYield()
+ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+ #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+ #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+ #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+ #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
+ #define portENTER_CRITICAL() vPortEnterCritical()
+ #define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+ #ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+ #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+ #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+ #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+ #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+ #else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+ #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+#endif /* PORTMACROCOMMON_H */
diff --git a/Source/portable/IAR/ARM_CM4F/port.c b/Source/portable/IAR/ARM_CM4F/port.c
index e16f20a..79bdf68 100644
--- a/Source/portable/IAR/ARM_CM4F/port.c
+++ b/Source/portable/IAR/ARM_CM4F/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -45,27 +45,18 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
@@ -104,12 +95,24 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
@@ -247,66 +250,66 @@
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -395,7 +398,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -404,22 +407,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_interrupt();
@@ -430,23 +417,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_interrupt()
+ /* Re-enable interrupts - see comments above the __disable_interrupt()
* call above. */
__enable_interrupt();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -475,8 +488,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_interrupt() call above. */
__enable_interrupt();
__DSB();
__ISB();
@@ -496,27 +509,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -530,11 +539,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -545,13 +573,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__enable_interrupt();
@@ -569,11 +623,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -582,7 +636,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM4F/portasm.s b/Source/portable/IAR/ARM_CM4F/portasm.s
index b96c45c..7ac74ff 100644
--- a/Source/portable/IAR/ARM_CM4F/portasm.s
+++ b/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM4F/portmacro.h b/Source/portable/IAR/ARM_CM4F/portmacro.h
index 8377a9d..07779bb 100644
--- a/Source/portable/IAR/ARM_CM4F/portmacro.h
+++ b/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM4_MPU/port.c b/Source/portable/IAR/ARM_CM4_MPU/port.c
index 06e02ad..f6dae02 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/port.c
+++ b/Source/portable/IAR/ARM_CM4_MPU/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -82,7 +82,7 @@
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
#define portMPU_ENABLE ( 0x01UL )
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@@ -98,8 +98,8 @@
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
- * r0p1 port. */
+/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
+ * that a work around is active for errata 837070. */
#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
@@ -350,11 +350,17 @@
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
- /* This port can be used on all revisions of the Cortex-M7 core other than
- * the r0p1 parts. r0p1 parts should use the port from the
- * /source/portable/GCC/ARM_CM7/r0p1 directory. */
- configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
- configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
+ #else
+ /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
+ * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
+ * FreeRTOSConfig.h. */
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ #endif
#if ( configASSERT_DEFINED == 1 )
{
@@ -458,13 +464,44 @@
void vPortEnterCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ /* This is not the interrupt safe version of the enter critical function so
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
+ if( uxCriticalNesting == 1 )
+ {
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ }
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ /* This is not the interrupt safe version of the enter critical function so
+ * assert() if it is being called from an interrupt context. Only API
+ * functions that end in "FromISR" can be used in an interrupt. Only assert if
+ * the critical nesting count is 1 to protect against recursive calls if the
+ * assert function also uses a critical section. */
+ if( uxCriticalNesting == 1 )
+ {
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ }
+ }
+#else
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
-
/* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
@@ -474,9 +511,6 @@
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
}
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -484,21 +518,41 @@
void vPortExitCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ }
+#else
configASSERT( uxCriticalNesting );
-
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -549,7 +603,7 @@
extern uint32_t __privileged_data_end__[];
/* The only permitted number of regions are 8 or 16. */
- configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
@@ -585,6 +639,7 @@
( portPRIVILEGED_RAM_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
@@ -650,31 +705,19 @@
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION );
+ ( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
- /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
- * just removed the privileged only parameters. */
- xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
- ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + 1 );
-
- xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate all other regions. */
- for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ /* Invalidate user configurable regions. */
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
}
@@ -693,7 +736,8 @@
( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( portMPU_REGION_ENABLE );
@@ -701,7 +745,7 @@
lIndex = 0;
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
{
@@ -711,7 +755,7 @@
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + ul ); /* Region number. */
+ ( ul - 1UL ); /* Region number. */
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -721,7 +765,7 @@
else
{
/* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portasm.s b/Source/portable/IAR/ARM_CM4_MPU/portasm.s
index c1622b2..a399bf5 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/portasm.s
+++ b/Source/portable/IAR/ARM_CM4_MPU/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -70,9 +70,15 @@
stmdb sp!, {r0, r3}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
msr basepri, r0
dsb
isb
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
index a1e6b62..cf02898 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -73,6 +73,7 @@
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
+
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@@ -174,15 +175,15 @@
#define configTEX_S_C_B_SRAM ( 0x07UL )
#endif
-#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
-#define portPRIVILEGED_FLASH_REGION ( 1UL )
-#define portPRIVILEGED_RAM_REGION ( 2UL )
-#define portGENERAL_PERIPHERALS_REGION ( 3UL )
-#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
-#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
-#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
-#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL )
+#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
+#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
+#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
+#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
+#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portFIRST_CONFIGURABLE_REGION ( 0UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
+#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
+#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
@@ -192,10 +193,9 @@
uint32_t ulRegionAttribute;
} xMPU_REGION_REGISTERS;
-/* Plus 1 to create space for the stack region. */
typedef struct MPU_SETTINGS
{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
} xMPU_SETTINGS;
/* Architecture specifics. */
@@ -253,12 +253,23 @@
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
-#define portDISABLE_INTERRUPTS() \
- { \
- __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
- __DSB(); \
- __ISB(); \
- }
+#if( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ __disable_interrupt(); \
+ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+ __DSB(); \
+ __ISB(); \
+ __enable_interrupt(); \
+ }
+#else
+ #define portDISABLE_INTERRUPTS() \
+ { \
+ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+ __DSB(); \
+ __ISB(); \
+ }
+#endif
#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
#define portENTER_CRITICAL() vPortEnterCritical()
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/port.c b/Source/portable/IAR/ARM_CM7/r0p1/port.c
index 94ba94b..d360131 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -45,27 +45,18 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
@@ -98,12 +89,24 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
@@ -235,66 +238,66 @@
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -383,7 +386,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -392,22 +395,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_interrupt();
@@ -418,23 +405,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_interrupt()
+ /* Re-enable interrupts - see comments above the __disable_interrupt()
* call above. */
__enable_interrupt();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -463,8 +476,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_interrupt() call above. */
__enable_interrupt();
__DSB();
__ISB();
@@ -484,27 +497,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -518,11 +527,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -533,13 +561,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__enable_interrupt();
@@ -557,11 +611,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -570,7 +624,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
index 23a9019..521d8b4 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
+++ b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
index 6b3bbb8..db95f29 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/IAR/ARM_CM7_MPU/ReadMe.txt b/Source/portable/IAR/ARM_CM7_MPU/ReadMe.txt
deleted file mode 100644
index e1dd275..0000000
--- a/Source/portable/IAR/ARM_CM7_MPU/ReadMe.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
-The best option depends on the revision of the ARM Cortex-M7 core in use. The
-revision is specified by an 'r' number, and a 'p' number, so will look something
-like 'r0p1'. Check the documentation for the microcontroller in use to find the
-revision of the Cortex-M7 core used in that microcontroller. If in doubt, use
-the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
-with all core revisions.
-
-The first option is to use the ARM Cortex-M4F port, and the second option is to
-use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
-
-If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
-used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in
-the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory.
-
-If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
-Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7_MPU/r0p1
-directory.
diff --git a/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c b/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
deleted file mode 100644
index 556277e..0000000
--- a/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
+++ /dev/null
@@ -1,781 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.6
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
-* Implementation of functions defined in portable.h for the ARM CM4F MPU port.
-*----------------------------------------------------------*/
-
-/* IAR includes. */
-#include <intrinsics.h>
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#ifndef __ARMVFP__
- #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
- #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
-#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
- #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
- #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
-#endif
-
-/* Constants required to manipulate the core. Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
-#define portMPU_ENABLE ( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
-#define portMPU_REGION_VALID ( 0x10UL )
-#define portMPU_REGION_ENABLE ( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS 0x40000000UL
-#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
-
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK ( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000 )
-#define portINITIAL_EXC_RETURN ( 0xfffffffd )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC ( 6 )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
- * occurred while the SysTick counter is stopped during tickless idle
- * calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into. The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Turn the VFP on.
- */
-extern void vPortEnableVFP( void );
-
-/*
- * The C portion of the SVC handler.
- */
-void vPortSVCHandler_C( uint32_t * pulParam );
-
-/*
- * Called from the SVC handler used to start the scheduler.
- */
-extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * @brief Exit from critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters,
- BaseType_t xRunPrivileged )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
-
- /* Offset added to account for the way the MCU uses the stack on entry/exit
- * of interrupts, and to ensure alignment. */
- pxTopOfStack--;
-
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = ( StackType_t ) 0; /* LR */
-
- /* Save code space by skipping register initialisation. */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
- /* A save method is being used that requires each task to maintain its
- * own exec return value. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN;
-
- pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
- }
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t * pulParam )
-{
- uint8_t ucSVCNumber;
- uint32_t ulPC;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- extern uint32_t __syscalls_flash_start__[];
- extern uint32_t __syscalls_flash_end__[];
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
- * argument (r0) is pulParam[ 0 ]. */
- ulPC = pulParam[ portOFFSET_TO_PC ];
- ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
-
- switch( ucSVCNumber )
- {
- case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
- vPortRestoreContextOfFirstTask();
- break;
-
- case portSVC_YIELD:
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
- /* Barriers are normally not required
- * but do ensure the code is completely
- * within the specified behaviour for the
- * architecture. */
- __asm volatile ( "dsb" ::: "memory" );
- __asm volatile ( "isb" );
-
- break;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
- * svc was raised from any of the
- * system calls. */
-
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- }
-
- break;
- #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
- case portSVC_RAISE_PRIVILEGE:
- __asm volatile
- (
- " mrs r1, control \n"/* Obtain current control value. */
- " bic r1, r1, #1 \n"/* Set privilege bit. */
- " msr control, r1 \n"/* Write back new control value. */
- ::: "r1", "memory"
- );
- break;
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- default: /* Unknown SVC call. */
- break;
- }
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the lowest priority interrupts. */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Configure the regions in the MPU that are common to all tasks. */
- prvSetupMPU();
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vPortSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Ensure the VFP is enabled - it should be anyway. */
- vPortEnableVFP();
-
- /* Lazy save always. */
- *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
- /* Start the first task. */
- vPortStartFirstTask();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
-
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-
- /* This is not the interrupt safe version of the enter critical function so
- * assert() if it is being called from an interrupt context. Only API
- * functions that end in "FromISR" can be used in an interrupt. Only assert if
- * the critical nesting count is 1 to protect against recursive calls if the
- * assert function also uses a critical section. */
- if( uxCriticalNesting == 1 )
- {
- configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
- }
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
-
- configASSERT( uxCriticalNesting );
-
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- /* The SysTick runs at the lowest interrupt priority, so when this interrupt
- * executes all interrupts must be unmasked. There is therefore no need to
- * save and then restore the interrupt mask value as its value is already
- * known. */
- portDISABLE_INTERRUPTS();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* A context switch is required. Context switching is performed in
- * the PendSV interrupt. Pend the PendSV interrupt. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__weak void vPortSetupTimerInterrupt( void )
-{
- /* Stop and clear the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
- extern uint32_t __privileged_functions_start__[];
- extern uint32_t __privileged_functions_end__[];
- extern uint32_t __FLASH_segment_start__[];
- extern uint32_t __FLASH_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
-
- /* The only permitted number of regions are 8 or 16. */
- configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
-
- /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
- configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
-
- /* Check the expected MPU is present. */
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
- {
- /* First setup the unprivileged flash for unprivileged read only access. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portUNPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged flash for privileged only access. This is where
- * the kernel code is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged data RAM region. This is where the kernel data
- * is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_RAM_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* By default allow everything to access the general peripherals. The
- * system peripherals and registers are protected. */
- portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
- ( portMPU_REGION_VALID ) |
- ( portGENERAL_PERIPHERALS_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Enable the memory fault exception. */
- portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
- /* Enable the MPU with the background region configured. */
- portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
- }
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
- uint32_t ulRegionSize, ulReturnValue = 4;
-
- /* 32 is the smallest region size, 31 is the largest valid value for
- * ulReturnValue. */
- for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
- {
- if( ulActualSizeInBytes <= ulRegionSize )
- {
- break;
- }
- else
- {
- ulReturnValue++;
- }
- }
-
- /* Shift the code by one before returning so it can be written directly
- * into the the correct bit position of the attribute register. */
- return( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
- const struct xMEMORY_REGION * const xRegions,
- StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
-{
- extern uint32_t __SRAM_segment_start__[];
- extern uint32_t __SRAM_segment_end__[];
- extern uint32_t __privileged_data_start__[];
- extern uint32_t __privileged_data_end__[];
- int32_t lIndex;
- uint32_t ul;
-
- if( xRegions == NULL )
- {
- /* No MPU regions are specified so allow access to all RAM. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION );
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
- * just removed the privileged only parameters. */
- xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
- ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + 1 );
-
- xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate all other regions. */
- for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
- }
- else
- {
- /* This function is called automatically when the task is created - in
- * which case the stack region parameters will be valid. At all other
- * times the stack parameters will not be valid and it is assumed that the
- * stack region has already been configured. */
- if( ulStackDepth > 0 )
- {
- /* Define the region that allows access to the stack. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) pxBottomOfStack ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( portMPU_REGION_ENABLE );
- }
-
- lIndex = 0;
-
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
- {
- /* Translate the generic region definition contained in
- * xRegions into the CM7 specific MPU settings that are then
- * stored in xMPUSettings. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
- ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + ul ); /* Region number. */
-
- xMPUSettings->xRegion[ ul ].ulRegionAttribute =
- ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
- ( xRegions[ lIndex ].ulParameters ) |
- ( portMPU_REGION_ENABLE );
- }
- else
- {
- /* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
-
- lIndex++;
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredictable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s b/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
deleted file mode 100644
index 3b1d8e4..0000000
--- a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.6
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-/* Including FreeRTOSConfig.h here will cause build errors if the header file
-contains code not understood by the assembler - for example the 'extern' keyword.
-To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
-the code is included in C files but excluded by the preprocessor in assembly
-files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
-#include <FreeRTOSConfig.h>
-
- RSEG CODE:CODE(2)
- thumb
-
- EXTERN pxCurrentTCB
- EXTERN vTaskSwitchContext
- EXTERN vPortSVCHandler_C
-
- PUBLIC xPortPendSVHandler
- PUBLIC vPortSVCHandler
- PUBLIC vPortStartFirstTask
- PUBLIC vPortEnableVFP
- PUBLIC vPortRestoreContextOfFirstTask
- PUBLIC xIsPrivileged
- PUBLIC vResetPrivilege
-
-/*-----------------------------------------------------------*/
-
-xPortPendSVHandler:
- mrs r0, psp
- isb
- /* Get the location of the current TCB. */
- ldr r3, =pxCurrentTCB
- ldr r2, [r3]
-
- /* Is the task using the FPU context? If so, push high vfp registers. */
- tst r14, #0x10
- it eq
- vstmdbeq r0!, {s16-s31}
-
- /* Save the core registers. */
- mrs r1, control
- stmdb r0!, {r1, r4-r11, r14}
-
- /* Save the new top of stack into the first member of the TCB. */
- str r0, [r2]
-
- stmdb sp!, {r0, r3}
- mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- cpsid i
- msr basepri, r0
- dsb
- isb
- cpsie i
- bl vTaskSwitchContext
- mov r0, #0
- msr basepri, r0
- ldmia sp!, {r0, r3}
-
- /* The first item in pxCurrentTCB is the task top of stack. */
- ldr r1, [r3]
- ldr r0, [r1]
- /* Move onto the second item in the TCB... */
- add r1, r1, #4
-
- dmb /* Complete outstanding transfers before disabling MPU. */
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [r2] /* Read the value of MPU_CTRL. */
- bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- str r3, [r2] /* Disable MPU. */
-
- /* Region Base Address register. */
- ldr r2, =0xe000ed9c
- /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- ldmia r1!, {r4-r11}
- /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r2, {r4-r11}
-
- #ifdef configTOTAL_MPU_REGIONS
- #if ( configTOTAL_MPU_REGIONS == 16 )
- /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- ldmia r1!, {r4-r11}
- /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- stmia r2, {r4-r11}
- /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- ldmia r1!, {r4-r11}
- /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- stmia r2, {r4-r11}
- #endif /* configTOTAL_MPU_REGIONS == 16. */
- #endif /* configTOTAL_MPU_REGIONS */
-
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [r2] /* Read the value of MPU_CTRL. */
- orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- str r3, [r2] /* Enable MPU. */
- dsb /* Force memory writes before continuing. */
-
- /* Pop the registers that are not automatically saved on exception entry. */
- ldmia r0!, {r3-r11, r14}
- msr control, r3
-
- /* Is the task using the FPU context? If so, pop the high vfp registers
- too. */
- tst r14, #0x10
- it eq
- vldmiaeq r0!, {s16-s31}
-
- msr psp, r0
- isb
-
- bx r14
-
-
-/*-----------------------------------------------------------*/
-
-vPortSVCHandler:
- #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
- tst lr, #4
- ite eq
- mrseq r0, msp
- mrsne r0, psp
- #else
- mrs r0, psp
- #endif
- b vPortSVCHandler_C
-
-/*-----------------------------------------------------------*/
-
-vPortStartFirstTask:
- /* Use the NVIC offset register to locate the stack. */
- ldr r0, =0xE000ED08
- ldr r0, [r0]
- ldr r0, [r0]
- /* Set the msp back to the start of the stack. */
- msr msp, r0
- /* Clear the bit that indicates the FPU is in use in case the FPU was used
- before the scheduler was started - which would otherwise result in the
- unnecessary leaving of space in the SVC stack for lazy saving of FPU
- registers. */
- mov r0, #0
- msr control, r0
- /* Call SVC to start the first task. */
- cpsie i
- cpsie f
- dsb
- isb
- svc 0
-
-/*-----------------------------------------------------------*/
-
-vPortRestoreContextOfFirstTask:
- /* Use the NVIC offset register to locate the stack. */
- ldr r0, =0xE000ED08
- ldr r0, [r0]
- ldr r0, [r0]
- /* Set the msp back to the start of the stack. */
- msr msp, r0
- /* Restore the context. */
- ldr r3, =pxCurrentTCB
- ldr r1, [r3]
- /* The first item in the TCB is the task top of stack. */
- ldr r0, [r1]
- /* Move onto the second item in the TCB... */
- add r1, r1, #4
-
- dmb /* Complete outstanding transfers before disabling MPU. */
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [r2] /* Read the value of MPU_CTRL. */
- bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- str r3, [r2] /* Disable MPU. */
-
- /* Region Base Address register. */
- ldr r2, =0xe000ed9c
- /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- ldmia r1!, {r4-r11}
- /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r2, {r4-r11}
-
- #ifdef configTOTAL_MPU_REGIONS
- #if ( configTOTAL_MPU_REGIONS == 16 )
- /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- ldmia r1!, {r4-r11}
- /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- stmia r2, {r4-r11}
- /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- ldmia r1!, {r4-r11}
- /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- stmia r2, {r4-r11}
- #endif /* configTOTAL_MPU_REGIONS == 16. */
- #endif /* configTOTAL_MPU_REGIONS */
-
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [r2] /* Read the value of MPU_CTRL. */
- orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- str r3, [r2] /* Enable MPU. */
- dsb /* Force memory writes before continuing. */
-
- /* Pop the registers that are not automatically saved on exception entry. */
- ldmia r0!, {r3-r11, r14}
- msr control, r3
- /* Restore the task stack pointer. */
- msr psp, r0
- mov r0, #0
- msr basepri, r0
- bx r14
-
-/*-----------------------------------------------------------*/
-
-vPortEnableVFP:
- /* The FPU enable bits are in the CPACR. */
- ldr.w r0, =0xE000ED88
- ldr r1, [r0]
-
- /* Enable CP10 and CP11 coprocessors, then save back. */
- orr r1, r1, #( 0xf << 20 )
- str r1, [r0]
- bx r14
-
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
- mrs r0, control /* r0 = CONTROL. */
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- ite ne
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- bx lr /* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
- mrs r0, control /* r0 = CONTROL. */
- orr r0, r0, #1 /* r0 = r0 | 1. */
- msr control, r0 /* CONTROL = r0. */
- bx lr /* Return to the caller. */
-/*-----------------------------------------------------------*/
-
- END
diff --git a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h b/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
deleted file mode 100644
index 4794fb0..0000000
--- a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.6
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
- extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* IAR includes. */
-#include <intrinsics.h>
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS 1
-#define portPRIVILEGE_BIT ( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
-
-/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
- * Register (RASR). */
-#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
-#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
-
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
-#ifndef configTOTAL_MPU_REGIONS
- /* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
-#endif
-
-/*
- * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
- * memory type, and where necessary the cacheable and shareable properties
- * of the memory region.
- *
- * The TEX, C, and B bits together indicate the memory type of the region,
- * and:
- * - For Normal memory, the cacheable properties of the region.
- * - For Device memory, whether the region is shareable.
- *
- * For Normal memory regions, the S bit indicates whether the region is
- * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
- *
- * See the following two tables for setting TEX, S, C and B bits for
- * unprivileged flash, privileged flash and privileged RAM regions.
- *
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 1 | Device | Shared device | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 1 | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 011 | X | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
- | | | | | outer cacheability rules that must be exported on the | |
- | | | | | bus. See the table below for the cacheability policy | |
- | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- |
- +-----------------------------------------+----------------------------------------+
- | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
- +-----------------------------------------+----------------------------------------+
- | 00 | Non-cacheable |
- +-----------------------------------------+----------------------------------------+
- | 01 | Write-back, write and read allocate |
- +-----------------------------------------+----------------------------------------+
- | 10 | Write-through, no write allocate |
- +-----------------------------------------+----------------------------------------+
- | 11 | Write-back, no write allocate |
- +-----------------------------------------+----------------------------------------+
- */
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
- * region. */
-#ifndef configTEX_S_C_B_FLASH
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_FLASH ( 0x07UL )
-#endif
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
- * region. */
-#ifndef configTEX_S_C_B_SRAM
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_SRAM ( 0x07UL )
-#endif
-
-#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
-#define portPRIVILEGED_FLASH_REGION ( 1UL )
-#define portPRIVILEGED_RAM_REGION ( 2UL )
-#define portGENERAL_PERIPHERALS_REGION ( 3UL )
-#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
-#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
-#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
-#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL )
-
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
-typedef struct MPU_REGION_REGISTERS
-{
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
-typedef struct MPU_SETTINGS
-{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
-} xMPU_SETTINGS;
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER 0
-#define portSVC_YIELD 1
-#define portSVC_RAISE_PRIVILEGE 2
-
-/* Scheduler utilities. */
-
-#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
-#define portYIELD_WITHIN_API() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- __DSB(); \
- __ISB(); \
- }
-
-#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS() \
- { \
- __disable_interrupt(); \
- __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
- __DSB(); \
- __ISB(); \
- __enable_interrupt(); \
- }
-
-#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
-#endif
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
-}
-
-
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- */
-#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE() vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
-#endif
-/*-----------------------------------------------------------*/
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
- * the source code because to do so would cause other compilers to generate
- * warnings. */
-#pragma diag_suppress=Pe191
-#pragma diag_suppress=Pa082
-#pragma diag_suppress=Be006
-/*-----------------------------------------------------------*/
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
- }
-#endif
-/* *INDENT-ON* */
-
-#endif /* PORTMACRO_H */
diff --git a/Source/portable/MemMang/heap_1.c b/Source/portable/MemMang/heap_1.c
index f442caf..43a55f9 100644
--- a/Source/portable/MemMang/heap_1.c
+++ b/Source/portable/MemMang/heap_1.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -75,21 +75,21 @@
/* Ensure that blocks are always aligned. */
#if ( portBYTE_ALIGNMENT != 1 )
+ {
+ if( xWantedSize & portBYTE_ALIGNMENT_MASK )
{
- if( xWantedSize & portBYTE_ALIGNMENT_MASK )
+ /* Byte alignment required. Check for overflow. */
+ if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) > xWantedSize )
{
- /* Byte alignment required. Check for overflow. */
- if ( (xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) )) > xWantedSize )
- {
- xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
- }
- else
- {
- xWantedSize = 0;
- }
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+ }
+ else
+ {
+ xWantedSize = 0;
}
}
- #endif
+ }
+ #endif /* if ( portBYTE_ALIGNMENT != 1 ) */
vTaskSuspendAll();
{
@@ -100,7 +100,7 @@
}
/* Check there is enough room left for the allocation and. */
- if( ( xWantedSize > 0 ) && /* valid size */
+ if( ( xWantedSize > 0 ) && /* valid size */
( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */
{
@@ -115,13 +115,12 @@
( void ) xTaskResumeAll();
#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
+ vApplicationMallocFailedHook();
}
+ }
#endif
return pvReturn;
diff --git a/Source/portable/MemMang/heap_2.c b/Source/portable/MemMang/heap_2.c
index f690fd2..497295d 100644
--- a/Source/portable/MemMang/heap_2.c
+++ b/Source/portable/MemMang/heap_2.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -36,6 +36,7 @@
* memory management pages of https://www.FreeRTOS.org for more information.
*/
#include <stdlib.h>
+#include <string.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
* all the API functions to use the MPU wrappers. That should only be done when
@@ -51,13 +52,36 @@
#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
#endif
+#ifndef configHEAP_CLEAR_MEMORY_ON_FREE
+ #define configHEAP_CLEAR_MEMORY_ON_FREE 0
+#endif
+
/* A few bytes might be lost to byte aligning the heap start address. */
#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
-/*
- * Initialises the heap structures before their first use.
- */
-static void prvHeapInit( void );
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Max value that fits in a size_t type. */
+#define heapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if multiplying a and b will result in overflow. */
+#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+
+/* Check if adding a and b will result in overflow. */
+#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) )
+#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )
+#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )
+
+/*-----------------------------------------------------------*/
/* Allocate the memory for the heap. */
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
@@ -66,7 +90,7 @@
* heap - probably so it can be placed in a special segment or address. */
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#else
- static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+ PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
#endif /* configAPPLICATION_ALLOCATED_HEAP */
@@ -79,15 +103,24 @@
} BlockLink_t;
-static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
+static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );
#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, xEnd;
+PRIVILEGED_DATA static BlockLink_t xStart, xEnd;
/* Keeps track of the number of free bytes remaining, but says nothing about
* fragmentation. */
-static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialises the heap structures before their first use.
+ */
+static void prvHeapInit( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
@@ -119,9 +152,12 @@
void * pvPortMalloc( size_t xWantedSize )
{
- BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
- static BaseType_t xHeapHasBeenInitialised = pdFALSE;
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
+ PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
vTaskSuspendAll();
{
@@ -133,73 +169,77 @@
xHeapHasBeenInitialised = pdTRUE;
}
- /* The wanted size must be increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( ( xWantedSize > 0 ) &&
- ( ( xWantedSize + heapSTRUCT_SIZE ) > xWantedSize ) ) /* Overflow check */
+ if( xWantedSize > 0 )
{
- xWantedSize += heapSTRUCT_SIZE;
+ /* The wanted size must be increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. Some
+ * additional increment may also be needed for alignment. */
+ xAdditionalRequiredSize = heapSTRUCT_SIZE + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
- /* Byte alignment required. Check for overflow. */
- if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) )
- > xWantedSize )
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
{
- xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
- configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+ xWantedSize += xAdditionalRequiredSize;
}
else
{
xWantedSize = 0;
}
}
- else
+
+ /* Check the block size we are trying to allocate is not so large that the
+ * top bit is set. The top bit of the block size member of the BlockLink_t
+ * structure is used to determine who owns the block - the application or
+ * the kernel, so it must be free. */
+ if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
{
- xWantedSize = 0;
- }
-
-
- if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
- {
- /* Blocks are stored in byte order - traverse the list from the start
- * (smallest) block until one of adequate size is found. */
- pxPreviousBlock = &xStart;
- pxBlock = xStart.pxNextFreeBlock;
-
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
- pxPreviousBlock = pxBlock;
- pxBlock = pxBlock->pxNextFreeBlock;
- }
+ /* Blocks are stored in byte order - traverse the list from the start
+ * (smallest) block until one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
- /* If we found the end marker then a block of adequate size was not found. */
- if( pxBlock != &xEnd )
- {
- /* Return the memory space - jumping over the BlockLink_t structure
- * at its start. */
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
-
- /* This block is being returned for use so must be taken out of the
- * list of free blocks. */
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
- /* If the block is larger than required it can be split into two. */
- if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
{
- /* This block is to be split into two. Create a new block
- * following the number of bytes requested. The void cast is
- * used to prevent byte alignment warnings from the compiler. */
- pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-
- /* Calculate the sizes of two blocks split from the single
- * block. */
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
- pxBlock->xBlockSize = xWantedSize;
-
- /* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
}
- xFreeBytesRemaining -= pxBlock->xBlockSize;
+ /* If we found the end marker then a block of adequate size was not found. */
+ if( pxBlock != &xEnd )
+ {
+ /* Return the memory space - jumping over the BlockLink_t structure
+ * at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
+
+ /* This block is being returned for use so must be taken out of the
+ * list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new block
+ * following the number of bytes requested. The void cast is
+ * used to prevent byte alignment warnings from the compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ /* The block is being returned - it is allocated and owned
+ * by the application and has no "next" block. */
+ heapALLOCATE_BLOCK( pxBlock );
+ pxBlock->pxNextFreeBlock = NULL;
+ }
}
}
@@ -208,13 +248,12 @@
( void ) xTaskResumeAll();
#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
+ vApplicationMallocFailedHook();
}
+ }
#endif
return pvReturn;
@@ -236,14 +275,32 @@
* byte alignment warnings. */
pxLink = ( void * ) puc;
- vTaskSuspendAll();
+ configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
+ configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
- /* Add this block to the list of free blocks. */
- prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
- xFreeBytesRemaining += pxLink->xBlockSize;
- traceFREE( pv, pxLink->xBlockSize );
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ heapFREE_BLOCK( pxLink );
+ #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
+ {
+ ( void ) memset( puc + heapSTRUCT_SIZE, 0, pxLink->xBlockSize - heapSTRUCT_SIZE );
+ }
+ #endif
+
+ vTaskSuspendAll();
+ {
+ /* Add this block to the list of free blocks. */
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ }
+ ( void ) xTaskResumeAll();
+ }
}
- ( void ) xTaskResumeAll();
}
}
/*-----------------------------------------------------------*/
@@ -260,7 +317,26 @@
}
/*-----------------------------------------------------------*/
-static void prvHeapInit( void )
+void * pvPortCalloc( size_t xNum,
+ size_t xSize )
+{
+ void * pv = NULL;
+
+ if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 )
+ {
+ pv = pvPortMalloc( xNum * xSize );
+
+ if( pv != NULL )
+ {
+ ( void ) memset( pv, 0, xNum * xSize );
+ }
+ }
+
+ return pv;
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
{
BlockLink_t * pxFirstFreeBlock;
uint8_t * pucAlignedHeap;
@@ -279,7 +355,7 @@
/* To start with there is a single free block that is sized to take up the
* entire heap space. */
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
}
diff --git a/Source/portable/MemMang/heap_3.c b/Source/portable/MemMang/heap_3.c
index b734769..89c011a 100644
--- a/Source/portable/MemMang/heap_3.c
+++ b/Source/portable/MemMang/heap_3.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -68,13 +68,12 @@
( void ) xTaskResumeAll();
#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
+ vApplicationMallocFailedHook();
}
+ }
#endif
return pvReturn;
@@ -83,7 +82,7 @@
void vPortFree( void * pv )
{
- if( pv )
+ if( pv != NULL )
{
vTaskSuspendAll();
{
diff --git a/Source/portable/MemMang/heap_4.c b/Source/portable/MemMang/heap_4.c
index 2676835..7748f50 100644
--- a/Source/portable/MemMang/heap_4.c
+++ b/Source/portable/MemMang/heap_4.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -35,6 +35,7 @@
* memory management pages of https://www.FreeRTOS.org for more information.
*/
#include <stdlib.h>
+#include <string.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
* all the API functions to use the MPU wrappers. That should only be done when
@@ -50,12 +51,37 @@
#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
#endif
+#ifndef configHEAP_CLEAR_MEMORY_ON_FREE
+ #define configHEAP_CLEAR_MEMORY_ON_FREE 0
+#endif
+
/* Block sizes must not get too small. */
#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
/* Assumes 8bit bytes! */
#define heapBITS_PER_BYTE ( ( size_t ) 8 )
+/* Max value that fits in a size_t type. */
+#define heapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if multiplying a and b will result in overflow. */
+#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+
+/* Check if adding a and b will result in overflow. */
+#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) )
+#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )
+#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )
+
+/*-----------------------------------------------------------*/
+
/* Allocate the memory for the heap. */
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
@@ -97,7 +123,8 @@
static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
/* Create a couple of list links to mark the start and end of the list. */
-PRIVILEGED_DATA static BlockLink_t xStart, * pxEnd = NULL;
+PRIVILEGED_DATA static BlockLink_t xStart;
+PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL;
/* Keeps track of the number of calls to allocate and free memory as well as the
* number of free bytes remaining, but says nothing about fragmentation. */
@@ -106,18 +133,15 @@
PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
-/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize
- * member of an BlockLink_t structure is set then the block belongs to the
- * application. When the bit is free the block is still part of the free heap
- * space. */
-PRIVILEGED_DATA static size_t xBlockAllocatedBit = 0;
-
/*-----------------------------------------------------------*/
void * pvPortMalloc( size_t xWantedSize )
{
- BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
vTaskSuspendAll();
{
@@ -132,44 +156,33 @@
mtCOVERAGE_TEST_MARKER();
}
- /* Check the requested block size is not so large that the top bit is
- * set. The top bit of the block size member of the BlockLink_t structure
- * is used to determine who owns the block - the application or the
- * kernel, so it must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
/* The wanted size must be increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( ( xWantedSize > 0 ) &&
- ( ( xWantedSize + xHeapStructSize ) > xWantedSize ) ) /* Overflow check */
- {
- xWantedSize += xHeapStructSize;
+ * structure in addition to the requested amount of bytes. Some
+ * additional increment may also be needed for alignment. */
+ xAdditionalRequiredSize = xHeapStructSize + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
- /* Ensure that blocks are always aligned. */
- if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
- {
- /* Byte alignment required. Check for overflow. */
- if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) )
- > xWantedSize )
- {
- xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
- configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
- }
- else
- {
- xWantedSize = 0;
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
}
else
{
xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the block size we are trying to allocate is not so large that the
+ * top bit is set. The top bit of the block size member of the BlockLink_t
+ * structure is used to determine who owns the block - the application or
+ * the kernel, so it must be free. */
+ if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -232,7 +245,7 @@
/* The block is being returned - it is allocated and owned
* by the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ heapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
xNumberOfSuccessfulAllocations++;
}
@@ -256,17 +269,16 @@
( void ) xTaskResumeAll();
#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
@@ -288,17 +300,21 @@
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
- /* Check the block is actually allocated. */
- configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
configASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ heapFREE_BLOCK( pxLink );
+ #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
+ {
+ ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+ }
+ #endif
vTaskSuspendAll();
{
@@ -341,21 +357,40 @@
}
/*-----------------------------------------------------------*/
+void * pvPortCalloc( size_t xNum,
+ size_t xSize )
+{
+ void * pv = NULL;
+
+ if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 )
+ {
+ pv = pvPortMalloc( xNum * xSize );
+
+ if( pv != NULL )
+ {
+ ( void ) memset( pv, 0, xNum * xSize );
+ }
+ }
+
+ return pv;
+}
+/*-----------------------------------------------------------*/
+
static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
{
BlockLink_t * pxFirstFreeBlock;
uint8_t * pucAlignedHeap;
- size_t uxAddress;
+ portPOINTER_SIZE_TYPE uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
/* Ensure the heap starts on a correctly aligned boundary. */
- uxAddress = ( size_t ) ucHeap;
+ uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
- uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
- xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap;
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
@@ -367,25 +402,22 @@
/* pxEnd is used to mark the end of the list of free blocks and is inserted
* at the end of the heap space. */
- uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress = ( ( portPOINTER_SIZE_TYPE ) pucAlignedHeap ) + xTotalHeapSize;
uxAddress -= xHeapStructSize;
- uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
- pxEnd = ( void * ) uxAddress;
+ uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
+ pxEnd = ( BlockLink_t * ) uxAddress;
pxEnd->xBlockSize = 0;
pxEnd->pxNextFreeBlock = NULL;
/* To start with there is a single free block that is sized to take up the
* entire heap space, minus the space taken by pxEnd. */
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;
- pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -465,7 +497,7 @@
* is initialised automatically when the first allocation is made. */
if( pxBlock != NULL )
{
- do
+ while( pxBlock != pxEnd )
{
/* Increment the number of blocks and record the largest block seen
* so far. */
@@ -484,7 +516,7 @@
/* Move to the next block in the chain until the last block is
* reached. */
pxBlock = pxBlock->pxNextFreeBlock;
- } while( pxBlock != pxEnd );
+ }
}
}
( void ) xTaskResumeAll();
@@ -502,3 +534,4 @@
}
taskEXIT_CRITICAL();
}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/MemMang/heap_5.c b/Source/portable/MemMang/heap_5.c
index 53a818b..5c95925 100644
--- a/Source/portable/MemMang/heap_5.c
+++ b/Source/portable/MemMang/heap_5.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -69,6 +69,7 @@
*
*/
#include <stdlib.h>
+#include <string.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
* all the API functions to use the MPU wrappers. That should only be done when
@@ -84,12 +85,37 @@
#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
#endif
+#ifndef configHEAP_CLEAR_MEMORY_ON_FREE
+ #define configHEAP_CLEAR_MEMORY_ON_FREE 0
+#endif
+
/* Block sizes must not get too small. */
#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
/* Assumes 8bit bytes! */
#define heapBITS_PER_BYTE ( ( size_t ) 8 )
+/* Max value that fits in a size_t type. */
+#define heapSIZE_MAX ( ~( ( size_t ) 0 ) )
+
+/* Check if multiplying a and b will result in overflow. */
+#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) )
+
+/* Check if adding a and b will result in overflow. */
+#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) )
+
+/* MSB of the xBlockSize member of an BlockLink_t structure is used to track
+ * the allocation status of a block. When MSB of the xBlockSize member of
+ * an BlockLink_t structure is set then the block belongs to the application.
+ * When the bit is free the block is still part of the free heap space. */
+#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) )
+#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 )
+#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 )
+#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK )
+#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK )
+
+/*-----------------------------------------------------------*/
+
/* Define the linked list structure. This is used to link free blocks in order
* of their memory address. */
typedef struct A_BLOCK_LINK
@@ -115,7 +141,8 @@
static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, * pxEnd = NULL;
+static BlockLink_t xStart;
+static BlockLink_t * pxEnd = NULL;
/* Keeps track of the number of calls to allocate and free memory as well as the
* number of free bytes remaining, but says nothing about fragmentation. */
@@ -124,18 +151,15 @@
static size_t xNumberOfSuccessfulAllocations = 0;
static size_t xNumberOfSuccessfulFrees = 0;
-/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize
- * member of an BlockLink_t structure is set then the block belongs to the
- * application. When the bit is free the block is still part of the free heap
- * space. */
-static size_t xBlockAllocatedBit = 0;
-
/*-----------------------------------------------------------*/
void * pvPortMalloc( size_t xWantedSize )
{
- BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+ BlockLink_t * pxBlock;
+ BlockLink_t * pxPreviousBlock;
+ BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
+ size_t xAdditionalRequiredSize;
/* The heap must be initialised before the first call to
* prvPortMalloc(). */
@@ -143,43 +167,33 @@
vTaskSuspendAll();
{
- /* Check the requested block size is not so large that the top bit is
- * set. The top bit of the block size member of the BlockLink_t structure
- * is used to determine who owns the block - the application or the
- * kernel, so it must be free. */
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ if( xWantedSize > 0 )
{
- /* The wanted size is increased so it can contain a BlockLink_t
- * structure in addition to the requested amount of bytes. */
- if( ( xWantedSize > 0 ) &&
- ( ( xWantedSize + xHeapStructSize ) > xWantedSize ) ) /* Overflow check */
- {
- xWantedSize += xHeapStructSize;
+ /* The wanted size must be increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. Some
+ * additional increment may also be needed for alignment. */
+ xAdditionalRequiredSize = xHeapStructSize + portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
- /* Ensure that blocks are always aligned */
- if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
- {
- /* Byte alignment required. Check for overflow */
- if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) >
- xWantedSize )
- {
- xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
- }
- else
- {
- xWantedSize = 0;
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
+ {
+ xWantedSize += xAdditionalRequiredSize;
}
else
{
xWantedSize = 0;
}
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ /* Check the block size we are trying to allocate is not so large that the
+ * top bit is set. The top bit of the block size member of the BlockLink_t
+ * structure is used to determine who owns the block - the application or
+ * the kernel, so it must be free. */
+ if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
+ {
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
{
/* Traverse the list from the start (lowest address) block until
@@ -241,7 +255,7 @@
/* The block is being returned - it is allocated and owned
* by the application and has no "next" block. */
- pxBlock->xBlockSize |= xBlockAllocatedBit;
+ heapALLOCATE_BLOCK( pxBlock );
pxBlock->pxNextFreeBlock = NULL;
xNumberOfSuccessfulAllocations++;
}
@@ -265,17 +279,16 @@
( void ) xTaskResumeAll();
#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
{
- if( pvReturn == NULL )
- {
- extern void vApplicationMallocFailedHook( void );
- vApplicationMallocFailedHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ vApplicationMallocFailedHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
return pvReturn;
@@ -296,17 +309,21 @@
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
- /* Check the block is actually allocated. */
- configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
configASSERT( pxLink->pxNextFreeBlock == NULL );
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
{
if( pxLink->pxNextFreeBlock == NULL )
{
/* The block is being returned to the heap - it is no longer
* allocated. */
- pxLink->xBlockSize &= ~xBlockAllocatedBit;
+ heapFREE_BLOCK( pxLink );
+ #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 )
+ {
+ ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
+ }
+ #endif
vTaskSuspendAll();
{
@@ -343,6 +360,25 @@
}
/*-----------------------------------------------------------*/
+void * pvPortCalloc( size_t xNum,
+ size_t xSize )
+{
+ void * pv = NULL;
+
+ if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 )
+ {
+ pv = pvPortMalloc( xNum * xSize );
+
+ if( pv != NULL )
+ {
+ ( void ) memset( pv, 0, xNum * xSize );
+ }
+ }
+
+ return pv;
+}
+/*-----------------------------------------------------------*/
+
static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
{
BlockLink_t * pxIterator;
@@ -408,11 +444,12 @@
void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
{
- BlockLink_t * pxFirstFreeBlockInRegion = NULL, * pxPreviousFreeBlock;
- size_t xAlignedHeap;
+ BlockLink_t * pxFirstFreeBlockInRegion = NULL;
+ BlockLink_t * pxPreviousFreeBlock;
+ portPOINTER_SIZE_TYPE xAlignedHeap;
size_t xTotalRegionSize, xTotalHeapSize = 0;
BaseType_t xDefinedRegions = 0;
- size_t xAddress;
+ portPOINTER_SIZE_TYPE xAddress;
const HeapRegion_t * pxHeapRegion;
/* Can only call once! */
@@ -425,7 +462,7 @@
xTotalRegionSize = pxHeapRegion->xSizeInBytes;
/* Ensure the heap region starts on a correctly aligned boundary. */
- xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
+ xAddress = ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress;
if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
{
@@ -433,7 +470,7 @@
xAddress &= ~portBYTE_ALIGNMENT_MASK;
/* Adjust the size for the bytes lost to alignment. */
- xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
+ xTotalRegionSize -= ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress );
}
xAlignedHeap = xAddress;
@@ -464,7 +501,7 @@
* inserted at the end of the region space. */
xAddress = xAlignedHeap + xTotalRegionSize;
xAddress -= xHeapStructSize;
- xAddress &= ~portBYTE_ALIGNMENT_MASK;
+ xAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
pxEnd = ( BlockLink_t * ) xAddress;
pxEnd->xBlockSize = 0;
pxEnd->pxNextFreeBlock = NULL;
@@ -473,7 +510,7 @@
* sized to take up the entire heap region minus the space taken by the
* free block structure. */
pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
- pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
+ pxFirstFreeBlockInRegion->xBlockSize = ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlockInRegion );
pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
/* If this is not the first region that makes up the entire heap space
@@ -495,9 +532,6 @@
/* Check something was actually defined before it is accessed. */
configASSERT( xTotalHeapSize );
-
- /* Work out the position of the top bit in a size_t variable. */
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
}
/*-----------------------------------------------------------*/
@@ -514,7 +548,7 @@
* is initialised automatically when the first allocation is made. */
if( pxBlock != NULL )
{
- do
+ while( pxBlock != pxEnd )
{
/* Increment the number of blocks and record the largest block seen
* so far. */
@@ -539,7 +573,7 @@
/* Move to the next block in the chain until the last block is
* reached. */
pxBlock = pxBlock->pxNextFreeBlock;
- } while( pxBlock != pxEnd );
+ }
}
}
( void ) xTaskResumeAll();
@@ -557,3 +591,4 @@
}
taskEXIT_CRITICAL();
}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/RVDS/ARM_CM0/port.c b/Source/portable/RVDS/ARM_CM0/port.c
index f256726..d82e33b 100644
--- a/Source/portable/RVDS/ARM_CM0/port.c
+++ b/Source/portable/RVDS/ARM_CM0/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -45,6 +45,8 @@
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
@@ -59,12 +61,24 @@
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
#ifndef portMISSED_COUNTS_FACTOR
- #define portMISSED_COUNTS_FACTOR ( 45UL )
+ #define portMISSED_COUNTS_FACTOR ( 94UL )
#endif
/* Constants used with memory barrier intrinsics. */
#define portSY_FULL_READ_WRITE ( 15 )
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/* Legacy macro for backward compatibility only. This macro used to be used to
* replace the function that configures the clock used to generate the tick
* interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
@@ -360,18 +374,20 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
- /* Stop and reset the SysTick. */
+ /* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
@@ -381,7 +397,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -390,22 +406,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_irq();
@@ -416,23 +416,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_irq() call
- * above. */
+ /* Re-enable interrupts - see comments above the __disable_irq()
+ * call above. */
__enable_irq();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -443,10 +469,10 @@
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation contains
* its own wait for interrupt or wait for event instruction, and so wfi
- * should not be executed again. However, the original expected idle
+ * should not be executed again. However, the original expected idle
* time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
@@ -461,8 +487,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_irq() call above. */
__enable_irq();
__dsb( portSY_FULL_READ_WRITE );
__isb( portSY_FULL_READ_WRITE );
@@ -482,27 +508,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -516,11 +538,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -531,15 +572,41 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD
- * again, then set portNVIC_SYSTICK_LOAD back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
- vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
- /* Exit with interrpts enabled. */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
+ vTaskStepTick( ulCompleteTickPeriods );
+
+ /* Exit with interrupts enabled. */
__enable_irq();
}
}
diff --git a/Source/portable/RVDS/ARM_CM0/portmacro.h b/Source/portable/RVDS/ARM_CM0/portmacro.h
index 16ce116..8b4c0c4 100644
--- a/Source/portable/RVDS/ARM_CM0/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM0/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/RVDS/ARM_CM3/port.c b/Source/portable/RVDS/ARM_CM3/port.c
index 4377d76..167ce78 100644
--- a/Source/portable/RVDS/ARM_CM3/port.c
+++ b/Source/portable/RVDS/ARM_CM3/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -42,17 +42,6 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Legacy macro for backward compatibility only. This macro used to be used to
* replace the function that configures the clock used to generate the tick
* interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
@@ -68,10 +57,12 @@
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
@@ -99,12 +90,24 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
@@ -262,70 +265,70 @@
BaseType_t xPortStartScheduler( void )
{
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* The kernel interrupt priority should be set to the lowest
+ * priority. */
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* The kernel interrupt priority should be set to the lowest
- * priority. */
- configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -450,7 +453,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -459,22 +462,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_irq();
@@ -485,23 +472,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_irq() call
- * above. */
+ /* Re-enable interrupts - see comments above the __disable_irq()
+ * call above. */
__enable_irq();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -530,8 +543,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_irq() call above. */
__enable_irq();
__dsb( portSY_FULL_READ_WRITE );
__isb( portSY_FULL_READ_WRITE );
@@ -551,27 +564,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -585,11 +594,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -600,13 +628,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__enable_irq();
@@ -627,11 +681,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -640,7 +694,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
diff --git a/Source/portable/RVDS/ARM_CM3/portmacro.h b/Source/portable/RVDS/ARM_CM3/portmacro.h
index 354034c..db1c44e 100644
--- a/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/RVDS/ARM_CM4F/port.c b/Source/portable/RVDS/ARM_CM4F/port.c
index 2bdee4f..9c0892a 100644
--- a/Source/portable/RVDS/ARM_CM4F/port.c
+++ b/Source/portable/RVDS/ARM_CM4F/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -42,17 +42,6 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* Legacy macro for backward compatibility only. This macro used to be used to
* replace the function that configures the clock used to generate the tick
* interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
@@ -68,10 +57,12 @@
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
@@ -110,12 +101,24 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
@@ -324,70 +327,70 @@
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* The kernel interrupt priority should be set to the lowest
+ * priority. */
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* The kernel interrupt priority should be set to the lowest
- * priority. */
- configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -542,7 +545,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -551,22 +554,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_irq();
@@ -577,23 +564,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_irq() call
- * above. */
+ /* Re-enable interrupts - see comments above the __disable_irq()
+ * call above. */
__enable_irq();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -622,8 +635,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_irq() call above. */
__enable_irq();
__dsb( portSY_FULL_READ_WRITE );
__isb( portSY_FULL_READ_WRITE );
@@ -643,27 +656,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -677,11 +686,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -692,13 +720,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__enable_irq();
@@ -719,11 +773,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -732,7 +786,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
diff --git a/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Source/portable/RVDS/ARM_CM4F/portmacro.h
index 41eb461..21ac481 100644
--- a/Source/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/RVDS/ARM_CM4_MPU/port.c b/Source/portable/RVDS/ARM_CM4_MPU/port.c
index 1befeee..d9dbf66 100644
--- a/Source/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/Source/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -59,12 +59,18 @@
#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
+ * that a work around is active for errata 837070. */
+#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
+
/* Constants required to access and manipulate the MPU. */
#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
+#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
#define portMPU_ENABLE ( 0x01UL )
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@@ -367,12 +373,12 @@
ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- #if ( portTOTAL_NUM_REGIONS == 16 )
+ #if ( configTOTAL_MPU_REGIONS == 16 )
ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
ldr r2, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
@@ -400,6 +406,18 @@
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+ /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
+ * and r0p1 cores. */
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
+ #else
+ /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
+ * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
+ * FreeRTOSConfig.h. */
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+ #endif
+
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -533,15 +551,26 @@
void vPortEnterCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ }
+#else
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -549,10 +578,34 @@
void vPortExitCritical( void )
{
#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
+ if( portIS_PRIVILEGED() == pdFALSE )
+ {
+ portRAISE_PRIVILEGE();
+ portMEMORY_BARRIER();
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ portMEMORY_BARRIER();
+
+ portRESET_PRIVILEGE();
+ portMEMORY_BARRIER();
+ }
+ else
+ {
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ }
+#else
configASSERT( uxCriticalNesting );
uxCriticalNesting--;
@@ -560,9 +613,6 @@
{
portENABLE_INTERRUPTS();
}
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
#endif
}
/*-----------------------------------------------------------*/
@@ -591,9 +641,15 @@
stmdb sp !, { r0, r3 }
mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
msr basepri, r0
dsb
isb
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
+ #endif
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
@@ -613,12 +669,12 @@
ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
- #if ( portTOTAL_NUM_REGIONS == 16 )
+ #if ( configTOTAL_MPU_REGIONS == 16 )
ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
+ #endif /* configTOTAL_MPU_REGIONS == 16. */
ldr r2, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
@@ -713,7 +769,7 @@
extern uint32_t __privileged_data_end__;
/* The only permitted number of regions are 8 or 16. */
- configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
+ configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
@@ -749,6 +805,7 @@
( portPRIVILEGED_RAM_REGION );
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
( portMPU_REGION_ENABLE );
@@ -844,31 +901,19 @@
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION );
+ ( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
- /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
- * just removed the privileged only parameters. */
- xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
- ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + 1 );
-
- xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate all other regions. */
- for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ /* Invalidate user configurable regions. */
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
}
@@ -887,7 +932,8 @@
( portSTACK_REGION ); /* Region number. */
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER ) |
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
( portMPU_REGION_ENABLE );
@@ -895,7 +941,7 @@
lIndex = 0;
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+ for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
{
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
{
@@ -905,7 +951,7 @@
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + ul ); /* Region number. */
+ ( ul - 1UL ); /* Region number. */
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -915,7 +961,7 @@
else
{
/* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+ xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
}
diff --git a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 564a96d..c9c942e 100644
--- a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -70,6 +70,7 @@
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
+
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@@ -171,15 +172,15 @@
#define configTEX_S_C_B_SRAM ( 0x07UL )
#endif
-#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
-#define portPRIVILEGED_FLASH_REGION ( 1UL )
-#define portPRIVILEGED_RAM_REGION ( 2UL )
-#define portGENERAL_PERIPHERALS_REGION ( 3UL )
-#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
-#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
-#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
-#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
+#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
+#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
+#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
+#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
+#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
+#define portFIRST_CONFIGURABLE_REGION ( 0UL )
+#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
+#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
+#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
void vPortSwitchToUserMode( void );
#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
@@ -190,10 +191,9 @@
uint32_t ulRegionAttribute;
} xMPU_REGION_REGISTERS;
-/* Plus 1 to create space for the stack region. */
typedef struct MPU_SETTINGS
{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+ xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
} xMPU_SETTINGS;
/* Architecture specifics. */
@@ -334,9 +334,15 @@
/* Set BASEPRI to the max syscall priority to effect a critical
* section. */
/* *INDENT-OFF* */
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsid i
+ #endif
msr basepri, ulNewBASEPRI
dsb
isb
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsie i
+ #endif
/* *INDENT-ON* */
}
}
@@ -366,9 +372,15 @@
* section. */
/* *INDENT-OFF* */
mrs ulReturn, basepri
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsid i
+ #endif
msr basepri, ulNewBASEPRI
dsb
isb
+ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
+ cpsie i
+ #endif
/* *INDENT-ON* */
}
diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/Source/portable/RVDS/ARM_CM7/r0p1/port.c
index 0dc23f8..9796035 100644
--- a/Source/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/Source/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -42,17 +42,6 @@
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
#endif
-#ifndef configSYSTICK_CLOCK_HZ
- #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
- /* Ensure the SysTick is clocked at the same frequency as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
-#else
-
-/* The way the SysTick is clocked is not modified in case it is not the same
- * as the core. */
- #define portNVIC_SYSTICK_CLK_BIT ( 0 )
-#endif
-
/* The __weak attribute does not work as you might expect with the Keil tools
* so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
* the application writer wants to provide their own implementation of
@@ -68,10 +57,12 @@
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
@@ -104,12 +95,24 @@
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
+#define portMISSED_COUNTS_FACTOR ( 94UL )
/* For strict compliance with the Cortex-M spec the task start address should
* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+/* Let the user override the default SysTick clock rate. If defined by the
+ * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
+ * configuration register. */
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
+#else
+ /* Select the option to clock SysTick not at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
+#endif
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
@@ -308,70 +311,70 @@
BaseType_t xPortStartScheduler( void )
{
#if ( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ * functions can be called. ISR safe functions are those that end in
+ * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ * ensure interrupt entry is as fast and simple as possible.
+ *
+ * Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ * possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* The kernel interrupt priority should be set to the lowest
+ * priority. */
+ configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ * of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* The kernel interrupt priority should be set to the lowest
- * priority. */
- configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ * priority bits matches the number of priority bits actually queried
+ * from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ * register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ * value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
@@ -528,7 +531,7 @@
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -537,22 +540,6 @@
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
- /* Stop the SysTick momentarily. The time the SysTick is stopped for
- * is accounted for as best it can be, but using the tickless mode will
- * inevitably result in some tiny drift of the time maintained by the
- * kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Calculate the reload value required to wait xExpectedIdleTime
- * tick periods. -1 is used because this code will execute part way
- * through one of the tick periods. */
- ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-
- if( ulReloadValue > ulStoppedTimerCompensation )
- {
- ulReloadValue -= ulStoppedTimerCompensation;
- }
-
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__disable_irq();
@@ -563,23 +550,49 @@
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
- /* Restart from whatever is left in the count register to complete
- * this tick period. */
- portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
- /* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
- /* Reset the reload register to the value required for normal tick
- * periods. */
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
- /* Re-enable interrupts - see comments above __disable_irq() call
- * above. */
+ /* Re-enable interrupts - see comments above the __disable_irq()
+ * call above. */
__enable_irq();
}
else
{
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ * is accounted for as best it can be, but using the tickless mode will
+ * inevitably result in some tiny drift of the time maintained by the
+ * kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
+
+ /* Use the SysTick current-value register to determine the number of
+ * SysTick decrements remaining until the next tick interrupt. If the
+ * current-value register is zero, then there are actually
+ * ulTimerCountsForOneTick decrements remaining, not zero, because the
+ * SysTick requests the interrupt when decrementing from 1 to 0. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
+ }
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ * tick periods. -1 is used because this code normally executes part
+ * way through the first tick period. But if the SysTick IRQ is now
+ * pending, then clear the IRQ, suppressing the first tick, and correct
+ * the reload value to reflect that the second tick period is already
+ * underway. The expected idle time is always at least two ticks. */
+ ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+ if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
+ {
+ portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
+ ulReloadValue -= ulTimerCountsForOneTick;
+ }
+
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
@@ -608,8 +621,8 @@
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
- * out of sleep mode to execute immediately. see comments above
- * __disable_interrupt() call above. */
+ * out of sleep mode to execute immediately. See comments above
+ * the __disable_irq() call above. */
__enable_irq();
__dsb( portSY_FULL_READ_WRITE );
__isb( portSY_FULL_READ_WRITE );
@@ -629,27 +642,23 @@
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
- /* Determine if the SysTick clock has already counted to zero and
- * been set back to the current reload value (the reload back being
- * correct for the entire expected idle time) or if the SysTick is yet
- * to count to zero (in which case an interrupt other than the SysTick
- * must have brought the system out of sleep mode). */
+ /* Determine whether the SysTick has already counted to zero. */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt is already pending, and the SysTick count
- * reloaded with ulReloadValue. Reset the
- * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
- * period. */
+ /* The tick interrupt ended the sleep (or is now pending), and
+ * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
+ * with whatever remains of the new tick period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
- * that took too long. */
- if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ * that took too long or because the SysTick current-value register
+ * is zero. */
+ if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
@@ -663,11 +672,30 @@
}
else
{
- /* Something other than the tick interrupt ended the sleep.
- * Work out how long the sleep lasted rounded to complete tick
+ /* Something other than the tick interrupt ended the sleep. */
+
+ /* Use the SysTick current-value register to determine the
+ * number of SysTick decrements remaining until the expected idle
+ * time would have ended. */
+ ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
+ {
+ /* If the SysTick is not using the core clock, the current-
+ * value register might still be zero here. In that case, the
+ * SysTick didn't load from the reload register, and there are
+ * ulReloadValue decrements remaining in the expected idle
+ * time, not zero. */
+ if( ulSysTickDecrementsLeft == 0 )
+ {
+ ulSysTickDecrementsLeft = ulReloadValue;
+ }
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
- ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
/* How many complete tick periods passed while the processor
* was waiting? */
@@ -678,13 +706,39 @@
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
- /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
- * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- * value. */
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
+ * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
+ * the SysTick is not using the core clock, temporarily configure it to
+ * use the core clock. This configuration forces the SysTick to load
+ * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
+ * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
+ * to receive the standard value immediately. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
+ {
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ #else
+ {
+ /* The temporary usage of the core clock has served its purpose,
+ * as described above. Resume usage of the other clock. */
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
+
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ /* The partial tick period already ended. Be sure the SysTick
+ * counts it only once. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+ }
+ #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
+
+ /* Step the tick to account for any tick periods that elapsed. */
vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrupts enabled. */
__enable_irq();
@@ -705,11 +759,11 @@
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
@@ -718,7 +772,7 @@
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
}
#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index ce908c8..b1d9a98 100644
--- a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/RVDS/ARM_CM7_MPU/ReadMe.txt b/Source/portable/RVDS/ARM_CM7_MPU/ReadMe.txt
deleted file mode 100644
index 4e44c98..0000000
--- a/Source/portable/RVDS/ARM_CM7_MPU/ReadMe.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
-The best option depends on the revision of the ARM Cortex-M7 core in use. The
-revision is specified by an 'r' number, and a 'p' number, so will look something
-like 'r0p1'. Check the documentation for the microcontroller in use to find the
-revision of the Cortex-M7 core used in that microcontroller. If in doubt, use
-the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
-with all core revisions.
-
-The first option is to use the ARM Cortex-M4F port, and the second option is to
-use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
-
-If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
-used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in
-the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory.
-
-If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
-Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7_MPU/r0p1
-directory.
diff --git a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c b/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
deleted file mode 100644
index b9cdde9..0000000
--- a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
+++ /dev/null
@@ -1,997 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.6
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM7 port.
-*----------------------------------------------------------*/
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __TARGET_FPU_VFP
- #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
- #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
- #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
-#endif
-
-/* Constants required to access and manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
-#define portMPU_ENABLE ( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
-#define portMPU_REGION_VALID ( 0x10UL )
-#define portMPU_REGION_ENABLE ( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS 0x40000000UL
-#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
-
-/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
-#define portNVIC_SYSTICK_INT ( 0x00000002UL )
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000UL )
-#define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC ( 6 )
-
-/* For strict compliance with the Cortex-M spec the task start address should
- * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-
-/* Each task maintains its own interrupt status in the critical nesting
- * variable. Note this is not saved as part of the task context as context
- * switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-void vSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into. The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Standard FreeRTOS exception handlers.
- */
-void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
-void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
-void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Starts the scheduler by restoring the context of the first task to run.
- */
-static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/*
- * C portion of the SVC handler. The SVC handler is split between an asm entry
- * and a C wrapper for simplicity of coding and maintenance.
- */
-void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( used ) ) PRIVILEGED_FUNCTION;
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void );
-
-/*
- * Utility function.
- */
-static uint32_t prvPortGetIPSR( void );
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
- static uint8_t ucMaxSysCallPriority = 0;
- static uint32_t ulMaxPRIGROUPValue = 0;
- static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- * Bit[0] = 0 --> The processor is running privileged
- * Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void );
-
-/**
- * @brief Enter critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * @brief Exit from critical section.
- */
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
-#else
- void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
- TaskFunction_t pxCode,
- void * pvParameters,
- BaseType_t xRunPrivileged )
-{
- /* Simulate the stack frame as it would be created by a context switch
- * interrupt. */
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
- pxTopOfStack--;
- *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
- pxTopOfStack--;
- *pxTopOfStack = 0; /* LR */
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
- /* A save method is being used that requires each task to maintain its
- * own exec return value. */
- pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXC_RETURN;
-
- pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- if( xRunPrivileged == pdTRUE )
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
- }
- else
- {
- *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
- }
-
- return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void prvSVCHandler( uint32_t * pulParam )
-{
- uint8_t ucSVCNumber;
- uint32_t ulReg, ulPC;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- extern uint32_t __syscalls_flash_start__;
- extern uint32_t __syscalls_flash_end__;
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
- * argument (r0) is pulParam[ 0 ]. */
- ulPC = pulParam[ portOFFSET_TO_PC ];
- ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
-
- switch( ucSVCNumber )
- {
- case portSVC_START_SCHEDULER:
- portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
- prvRestoreContextOfFirstTask();
- break;
-
- case portSVC_YIELD:
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-
- /* Barriers are normally not required
- * but do ensure the code is completely
- * within the specified behaviour for the
- * architecture. */
- __asm volatile ( "dsb" );
- __asm volatile ( "isb" );
-
- break;
-
- #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
- case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
- * svc was raised from any of the
- * system calls. */
-
- if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
- ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
- {
- __asm
- {
-/* *INDENT-OFF* */
- mrs ulReg, control /* Obtain current control value. */
- bic ulReg, # 1 /* Set privilege bit. */
- msr control, ulReg /* Write back new control value. */
-/* *INDENT-ON* */
- }
- }
-
- break;
- #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
- case portSVC_RAISE_PRIVILEGE:
- __asm
- {
-/* *INDENT-OFF* */
- mrs ulReg, control /* Obtain current control value. */
- bic ulReg, # 1 /* Set privilege bit. */
- msr control, ulReg /* Write back new control value. */
-/* *INDENT-ON* */
- }
- break;
- #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
-
- default: /* Unknown SVC call. */
- break;
- }
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortSVCHandler( void )
-{
- extern prvSVCHandler
-
-/* *INDENT-OFF* */
- PRESERVE8
-
- /* Assumes psp was in use. */
- #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
- tst lr, # 4
- ite eq
- mrseq r0, msp
- mrsne r0, psp
- #else
- mrs r0, psp
- #endif
-
- b prvSVCHandler
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvRestoreContextOfFirstTask( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
- ldr r0, [ r0 ]
- ldr r0, [ r0 ]
- msr msp, r0 /* Set the msp back to the start of the stack. */
- ldr r3, =pxCurrentTCB /* Restore the context. */
- ldr r1, [ r3 ]
- ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
- add r1, r1, #4 /* Move onto the second item in the TCB... */
-
- dmb /* Complete outstanding transfers before disabling MPU. */
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- str r3, [ r2 ] /* Disable MPU. */
-
- ldr r2, =0xe000ed9c /* Region Base Address register. */
- ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
-
- #if ( portTOTAL_NUM_REGIONS == 16 )
- ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
-
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- str r3, [ r2 ] /* Enable MPU. */
- dsb /* Force memory writes before continuing. */
-
- ldmia r0 !, { r3 - r11, r14 } /* Pop the registers that are not automatically saved on exception entry. */
- msr control, r3
- msr psp, r0 /* Restore the task stack pointer. */
- mov r0, #0
- msr basepri, r0
- bx r14
- nop
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
- /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
- * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
- configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
- #if ( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t ulOriginalPriority;
- volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
- volatile uint8_t ucMaxPriorityValue;
-
- /* Determine the maximum priority from which ISR safe FreeRTOS API
- * functions can be called. ISR safe functions are those that end in
- * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
- * ensure interrupt entry is as fast and simple as possible.
- *
- * Save the interrupt priority value that is about to be clobbered. */
- ulOriginalPriority = *pucFirstUserPriorityRegister;
-
- /* Determine the number of priority bits available. First write to all
- * possible bits. */
- *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
- /* Read the value back to see how many bits stuck. */
- ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
- /* Use the same mask on the maximum system call priority. */
- ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
- /* Calculate the maximum acceptable priority group value for the number
- * of bits read back. */
- ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-
- while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
- {
- ulMaxPRIGROUPValue--;
- ucMaxPriorityValue <<= ( uint8_t ) 0x01;
- }
-
- #ifdef __NVIC_PRIO_BITS
- {
- /* Check the CMSIS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
- }
- #endif
-
- #ifdef configPRIO_BITS
- {
- /* Check the FreeRTOS configuration that defines the number of
- * priority bits matches the number of priority bits actually queried
- * from the hardware. */
- configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
- }
- #endif
-
- /* Shift the priority group value back to its position within the AIRCR
- * register. */
- ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
- ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
- /* Restore the clobbered interrupt priority register to its original
- * value. */
- *pucFirstUserPriorityRegister = ulOriginalPriority;
- }
- #endif /* configASSERT_DEFINED */
-
- /* Make PendSV and SysTick the same priority as the kernel, and the SVC
- * handler higher priority so it can be used to exit a critical section (where
- * lower priorities are masked). */
- portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
- portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
-
- /* Configure the regions in the MPU that are common to all tasks. */
- prvSetupMPU();
-
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already. */
- vSetupTimerInterrupt();
-
- /* Initialise the critical nesting count ready for the first task. */
- uxCriticalNesting = 0;
-
- /* Ensure the VFP is enabled - it should be anyway. */
- vPortEnableVFP();
-
- /* Lazy save always. */
- *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
- /* Start the first task. */
- prvStartFirstTask();
-
- /* Should not get here! */
- return 0;
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvStartFirstTask( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- /* Use the NVIC offset register to locate the stack. */
- ldr r0, =0xE000ED08
- ldr r0, [ r0 ]
- ldr r0, [ r0 ]
- /* Set the msp back to the start of the stack. */
- msr msp, r0
-
- /* Clear the bit that indicates the FPU is in use in case the FPU was used
- * before the scheduler was started - which would otherwise result in the
- * unnecessary leaving of space in the SVC stack for lazy saving of FPU
- * registers. */
- mov r0, #0
- msr control, r0
- /* Globally enable interrupts. */
- cpsie i
- cpsie f
- dsb
- isb
- svc portSVC_START_SCHEDULER /* System call to start first task. */
- nop
- nop
-/* *INDENT-ON* */
-}
-
-void vPortEndScheduler( void )
-{
- /* Not implemented in ports where there is nothing to return to.
- * Artificially force an assert. */
- configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
-
- portDISABLE_INTERRUPTS();
- uxCriticalNesting++;
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- BaseType_t xRunningPrivileged;
- xPortRaisePrivilege( xRunningPrivileged );
-#endif
-
- configASSERT( uxCriticalNesting );
- uxCriticalNesting--;
-
- if( uxCriticalNesting == 0 )
- {
- portENABLE_INTERRUPTS();
- }
-
-#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
- vPortResetPrivilege( xRunningPrivileged );
-#endif
-}
-/*-----------------------------------------------------------*/
-
-__asm void xPortPendSVHandler( void )
-{
- extern uxCriticalNesting;
- extern pxCurrentTCB;
- extern vTaskSwitchContext;
-
-/* *INDENT-OFF* */
- PRESERVE8
-
- mrs r0, psp
-
- ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
- ldr r2, [ r3 ]
-
- tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
- it eq
- vstmdbeq r0 !, { s16 - s31 }
-
- mrs r1, control
- stmdb r0 !, { r1, r4 - r11, r14 } /* Save the remaining registers. */
- str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
-
- stmdb sp !, { r0, r3 }
- mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
- msr basepri, r0
- dsb
- isb
- bl vTaskSwitchContext
- mov r0, #0
- msr basepri, r0
- ldmia sp !, { r0, r3 }
- /* Restore the context. */
- ldr r1, [ r3 ]
- ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
- add r1, r1, #4 /* Move onto the second item in the TCB... */
-
- dmb /* Complete outstanding transfers before disabling MPU. */
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
- str r3, [ r2 ] /* Disable MPU. */
-
- ldr r2, =0xe000ed9c /* Region Base Address register. */
- ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
- stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
-
- #if ( portTOTAL_NUM_REGIONS == 16 )
- ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
- stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
- ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
- stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
- #endif /* portTOTAL_NUM_REGIONS == 16. */
-
- ldr r2, =0xe000ed94 /* MPU_CTRL register. */
- ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
- orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
- str r3, [ r2 ] /* Enable MPU. */
- dsb /* Force memory writes before continuing. */
-
- ldmia r0 !, { r3 - r11, r14 } /* Pop the registers that are not automatically saved on exception entry. */
- msr control, r3
-
- tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
- it eq
- vldmiaeq r0 !, { s16 - s31 }
-
- msr psp, r0
- bx r14
- nop
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
- uint32_t ulDummy;
-
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__weak void vSetupTimerInterrupt( void )
-{
- /* Reset the SysTick. */
- portNVIC_SYSTICK_CTRL_REG = 0UL;
- portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortSwitchToUserMode( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- mrs r0, control
- orr r0, #1
- msr control, r0
- bx r14
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortEnableVFP( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
- ldr r1, [ r0 ]
-
- orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
- str r1, [ r0 ]
- bx r14
- nop
- nop
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
- extern uint32_t __privileged_functions_start__;
- extern uint32_t __privileged_functions_end__;
- extern uint32_t __FLASH_segment_start__;
- extern uint32_t __FLASH_segment_end__;
- extern uint32_t __privileged_data_start__;
- extern uint32_t __privileged_data_end__;
-
- /* The only permitted number of regions are 8 or 16. */
- configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
-
- /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
- configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
-
- /* Check the expected MPU is present. */
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
- {
- /* First setup the unprivileged flash for unprivileged read only access. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portUNPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged flash for privileged only access. This is where
- * the kernel code is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_FLASH_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
- ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Setup the privileged data RAM region. This is where the kernel data
- * is placed. */
- portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portPRIVILEGED_RAM_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* By default allow everything to access the general peripherals. The
- * system peripherals and registers are protected. */
- portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
- ( portMPU_REGION_VALID ) |
- ( portGENERAL_PERIPHERALS_REGION );
-
- portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
- ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Enable the memory fault exception. */
- portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
- /* Enable the MPU with the background region configured. */
- portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
- }
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
- uint32_t ulRegionSize, ulReturnValue = 4;
-
- /* 32 is the smallest region size, 31 is the largest valid value for
- * ulReturnValue. */
- for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
- {
- if( ulActualSizeInBytes <= ulRegionSize )
- {
- break;
- }
- else
- {
- ulReturnValue++;
- }
- }
-
- /* Shift the code by one before returning so it can be written directly
- * into the the correct bit position of the attribute register. */
- return( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-__asm BaseType_t xIsPrivileged( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- mrs r0, control /* r0 = CONTROL. */
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
- ite ne
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
- bx lr /* Return. */
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-__asm void vResetPrivilege( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- mrs r0, control /* r0 = CONTROL. */
- orrs r0, #1 /* r0 = r0 | 1. */
- msr control, r0 /* CONTROL = r0. */
- bx lr /* Return. */
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
- const struct xMEMORY_REGION * const xRegions,
- StackType_t * pxBottomOfStack,
- uint32_t ulStackDepth )
-{
- extern uint32_t __SRAM_segment_start__;
- extern uint32_t __SRAM_segment_end__;
- extern uint32_t __privileged_data_start__;
- extern uint32_t __privileged_data_end__;
-
-
- int32_t lIndex;
- uint32_t ul;
-
- if( xRegions == NULL )
- {
- /* No MPU regions are specified so allow access to all RAM. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION );
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
- ( portMPU_REGION_ENABLE );
-
- /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
- * just removed the privileged only parameters. */
- xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
- ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + 1 );
-
- xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
- ( portMPU_REGION_ENABLE );
-
- /* Invalidate all other regions. */
- for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
- }
- else
- {
- /* This function is called automatically when the task is created - in
- * which case the stack region parameters will be valid. At all other
- * times the stack parameters will not be valid and it is assumed that the
- * stack region has already been configured. */
- if( ulStackDepth > 0 )
- {
- /* Define the region that allows access to the stack. */
- xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
- ( ( uint32_t ) pxBottomOfStack ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION ); /* Region number. */
-
- xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
- ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
- ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
- ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
- ( portMPU_REGION_ENABLE );
- }
-
- lIndex = 0;
-
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
- {
- if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
- {
- /* Translate the generic region definition contained in
- * xRegions into the CM7 specific MPU settings that are then
- * stored in xMPUSettings. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
- ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
- ( portMPU_REGION_VALID ) |
- ( portSTACK_REGION + ul ); /* Region number. */
-
- xMPUSettings->xRegion[ ul ].ulRegionAttribute =
- ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
- ( xRegions[ lIndex ].ulParameters ) |
- ( portMPU_REGION_ENABLE );
- }
- else
- {
- /* Invalidate the region. */
- xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
- xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
- }
-
- lIndex++;
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-__asm uint32_t prvPortGetIPSR( void )
-{
-/* *INDENT-OFF* */
- PRESERVE8
-
- mrs r0, ipsr
- bx r14
-/* *INDENT-ON* */
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
- void vPortValidateInterruptPriority( void )
- {
- uint32_t ulCurrentInterrupt;
- uint8_t ucCurrentPriority;
-
- /* Obtain the number of the currently executing interrupt. */
- ulCurrentInterrupt = prvPortGetIPSR();
-
- /* Is the interrupt number a user defined interrupt? */
- if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
- {
- /* Look up the interrupt's priority. */
- ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
- /* The following assertion will fail if a service routine (ISR) for
- * an interrupt that has been assigned a priority above
- * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
- * function. ISR safe FreeRTOS API functions must *only* be called
- * from interrupts that have been assigned a priority at or below
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Numerically low interrupt priority numbers represent logically high
- * interrupt priorities, therefore the priority of the interrupt must
- * be set to a value equal to or numerically *higher* than
- * configMAX_SYSCALL_INTERRUPT_PRIORITY.
- *
- * Interrupts that use the FreeRTOS API must not be left at their
- * default priority of zero as that is the highest possible priority,
- * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
- * and therefore also guaranteed to be invalid.
- *
- * FreeRTOS maintains separate thread and ISR API functions to ensure
- * interrupt entry is as fast and simple as possible.
- *
- * The following links provide detailed information:
- * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
- * https://www.FreeRTOS.org/FAQHelp.html */
- configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
- }
-
- /* Priority grouping: The interrupt controller (NVIC) allows the bits
- * that define each interrupt's priority to be split between bits that
- * define the interrupt's pre-emption priority bits and bits that define
- * the interrupt's sub-priority. For simplicity all bits must be defined
- * to be pre-emption priority bits. The following assertion will fail if
- * this is not the case (if some bits represent a sub-priority).
- *
- * If the application only uses CMSIS libraries for interrupt
- * configuration then the correct setting can be achieved on all Cortex-M
- * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
- * scheduler. Note however that some vendor specific peripheral libraries
- * assume a non-zero priority group setting, in which cases using a value
- * of zero will result in unpredictable behaviour. */
- configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
- }
-
-#endif /* configASSERT_DEFINED */
diff --git a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h b/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
deleted file mode 100644
index 8b48f87..0000000
--- a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
- * FreeRTOS Kernel V10.4.6
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * https://www.FreeRTOS.org
- * https://github.com/FreeRTOS
- *
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
- extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE uint32_t
-#define portBASE_TYPE long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if ( configUSE_16_BIT_TICKS == 1 )
- typedef uint16_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
- typedef uint32_t TickType_t;
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
- * not need to be guarded with a critical section. */
- #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS 1
-#define portPRIVILEGE_BIT ( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
-
-/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
- * Register (RASR). */
-#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
-#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
-
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
-#ifndef configTOTAL_MPU_REGIONS
- /* Define to 8 for backward compatibility. */
- #define configTOTAL_MPU_REGIONS ( 8UL )
-#endif
-
-/*
- * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
- * memory type, and where necessary the cacheable and shareable properties
- * of the memory region.
- *
- * The TEX, C, and B bits together indicate the memory type of the region,
- * and:
- * - For Normal memory, the cacheable properties of the region.
- * - For Device memory, whether the region is shareable.
- *
- * For Normal memory regions, the S bit indicates whether the region is
- * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
- *
- * See the following two tables for setting TEX, S, C and B bits for
- * unprivileged flash, privileged flash and privileged RAM regions.
- *
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 0 | 1 | Device | Shared device | Shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 0 | 1 | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 010 | 1 | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 011 | X | X | Reserved | Reserved | Reserved |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
- | | | | | outer cacheability rules that must be exported on the | |
- | | | | | bus. See the table below for the cacheability policy | |
- | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
- +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
- |
- +-----------------------------------------+----------------------------------------+
- | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
- +-----------------------------------------+----------------------------------------+
- | 00 | Non-cacheable |
- +-----------------------------------------+----------------------------------------+
- | 01 | Write-back, write and read allocate |
- +-----------------------------------------+----------------------------------------+
- | 10 | Write-through, no write allocate |
- +-----------------------------------------+----------------------------------------+
- | 11 | Write-back, no write allocate |
- +-----------------------------------------+----------------------------------------+
- */
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash
- * region. */
-#ifndef configTEX_S_C_B_FLASH
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_FLASH ( 0x07UL )
-#endif
-
-/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM
- * region. */
-#ifndef configTEX_S_C_B_SRAM
- /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
- #define configTEX_S_C_B_SRAM ( 0x07UL )
-#endif
-
-#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
-#define portPRIVILEGED_FLASH_REGION ( 1UL )
-#define portPRIVILEGED_RAM_REGION ( 2UL )
-#define portGENERAL_PERIPHERALS_REGION ( 3UL )
-#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
-#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
-#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
-#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
-
-void vPortSwitchToUserMode( void );
-#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
-
-typedef struct MPU_REGION_REGISTERS
-{
- uint32_t ulRegionBaseAddress;
- uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
-typedef struct MPU_SETTINGS
-{
- xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
-} xMPU_SETTINGS;
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 8
-
-/* Constants used with memory barrier intrinsics. */
-#define portSY_FULL_READ_WRITE ( 15 )
-
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER 0
-#define portSVC_YIELD 1
-#define portSVC_RAISE_PRIVILEGE 2
-
-/* Scheduler utilities. */
-
-#define portYIELD() __asm{ SVC portSVC_YIELD }
-#define portYIELD_WITHIN_API() \
- { \
- /* Set a PendSV to request a context switch. */ \
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
- \
- /* Barriers are normally not required but do ensure the code is completely \
- * within the specified behaviour for the architecture. */ \
- __dsb( portSY_FULL_READ_WRITE ); \
- __isb( portSY_FULL_READ_WRITE ); \
- }
-/*-----------------------------------------------------------*/
-
-#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
-#define portENTER_CRITICAL() vPortEnterCritical()
-#define portEXIT_CRITICAL() vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-/* Check the configuration. */
- #if ( configMAX_PRIORITIES > 32 )
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
- #endif
-
-/* Store/clear the ready priorities in a bit map. */
- #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
- #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-/*-----------------------------------------------------------*/
-
- #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
- * not necessary for to use this port. They are defined so the common demo files
- * (which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
- void vPortValidateInterruptPriority( void );
- #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
- #define portFORCE_INLINE __forceinline
-#endif
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED() xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- */
-#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE() vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
-{
- __asm
- {
- /* Barrier instructions are not used as this function is only used to
- * lower the BASEPRI value. */
-/* *INDENT-OFF* */
- msr basepri, ulBASEPRI
-/* *INDENT-ON* */
- }
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-{
- uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
-/* *INDENT-OFF* */
- cpsid i
- msr basepri, ulNewBASEPRI
- dsb
- isb
- cpsie i
-/* *INDENT-ON* */
- }
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
-{
- __asm
- {
- /* Set BASEPRI to 0 so no interrupts are masked. This function is only
- * used to lower the mask in an interrupt, so memory barriers are not
- * used. */
-/* *INDENT-OFF* */
- msr basepri, # 0
-/* *INDENT-ON* */
- }
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-{
- uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
- __asm
- {
- /* Set BASEPRI to the max syscall priority to effect a critical
- * section. */
-/* *INDENT-OFF* */
- cpsid i
- mrs ulReturn, basepri
- msr basepri, ulNewBASEPRI
- dsb
- isb
- cpsie i
-/* *INDENT-ON* */
- }
-
- return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-{
- uint32_t ulCurrentInterrupt;
- BaseType_t xReturn;
-
- /* Obtain the number of the currently executing interrupt. */
- __asm
- {
- mrs ulCurrentInterrupt, ipsr
- }
-
- if( ulCurrentInterrupt == 0 )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
- #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
- #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
-#endif
-/*-----------------------------------------------------------*/
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
- }
-#endif
-/* *INDENT-ON* */
-
-#endif /* PORTMACRO_H */
diff --git a/Source/portable/Tasking/ARM_CM4F/port.c b/Source/portable/Tasking/ARM_CM4F/port.c
index 1e3d7c3..7e2dade 100644
--- a/Source/portable/Tasking/ARM_CM4F/port.c
+++ b/Source/portable/Tasking/ARM_CM4F/port.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/Source/portable/Tasking/ARM_CM4F/port_asm.asm
index 309267d..b0f436c 100644
--- a/Source/portable/Tasking/ARM_CM4F/port_asm.asm
+++ b/Source/portable/Tasking/ARM_CM4F/port_asm.asm
@@ -1,5 +1,5 @@
;/*
-; * FreeRTOS Kernel V10.4.6
+; * FreeRTOS Kernel V10.5.1
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
diff --git a/Source/portable/Tasking/ARM_CM4F/portmacro.h b/Source/portable/Tasking/ARM_CM4F/portmacro.h
index 3a2d66c..edc5b0e 100644
--- a/Source/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
diff --git a/Source/portable/ThirdParty/README.md b/Source/portable/ThirdParty/README.md
index f80aade..93a4398 100644
--- a/Source/portable/ThirdParty/README.md
+++ b/Source/portable/ThirdParty/README.md
@@ -13,8 +13,9 @@
* The code has been reviewed by the FreeRTOS team.
* FreeRTOS team has access to the hardware and the test results have been
- verified by the FreeRTOS team.
+ verified by the FreeRTOS team.
* Customer queries as well as bugs are addressed by the FreeRTOS team.
+* The code can be included in Long Term Support (LTS) releases.
A new FreeRTOS port cannot be directly contributed to this location. Instead,
the FreeRTOS team will decide to take ownership of a partner supported or a
@@ -29,9 +30,10 @@
* The code has not been reviewed by the FreeRTOS team.
* FreeRTOS team has not verified the tests results but tests exist and are
- reported to be successful by the partner.
+ reported to be successful by the partner.
* Customer queries as well as bugs are addressed by the partner.
-* A new FreeRTOS port can be directly contributed by a partner. The process to
+
+A new FreeRTOS port can be directly contributed by a partner. The process to
contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/blob/main/README.md).
## Community Supported FreeRTOS Ports
@@ -44,5 +46,6 @@
* The code has not been reviewed by the FreeRTOS team.
* Tests may or may not exist for the FreeRTOS port.
* Customer queries as well as bugs are addressed by the community.
-* A new FreeRTOS port can be directly contributed by anyone. The process to
+
+A new FreeRTOS port can be directly contributed by anyone. The process to
contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports/blob/main/README.md).
diff --git a/Source/queue.c b/Source/queue.c
index 46ed9a4..e76e7ff 100644
--- a/Source/queue.c
+++ b/Source/queue.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -261,6 +261,36 @@
} \
} \
taskEXIT_CRITICAL()
+
+/*
+ * Macro to increment cTxLock member of the queue data structure. It is
+ * capped at the number of tasks in the system as we cannot unblock more
+ * tasks than the number of tasks in the system.
+ */
+#define prvIncrementQueueTxLock( pxQueue, cTxLock ) \
+ { \
+ const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks(); \
+ if( ( UBaseType_t ) ( cTxLock ) < uxNumberOfTasks ) \
+ { \
+ configASSERT( ( cTxLock ) != queueINT8_MAX ); \
+ ( pxQueue )->cTxLock = ( int8_t ) ( ( cTxLock ) + ( int8_t ) 1 ); \
+ } \
+ }
+
+/*
+ * Macro to increment cRxLock member of the queue data structure. It is
+ * capped at the number of tasks in the system as we cannot unblock more
+ * tasks than the number of tasks in the system.
+ */
+#define prvIncrementQueueRxLock( pxQueue, cRxLock ) \
+ { \
+ const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks(); \
+ if( ( UBaseType_t ) ( cRxLock ) < uxNumberOfTasks ) \
+ { \
+ configASSERT( ( cRxLock ) != queueINT8_MAX ); \
+ ( pxQueue )->cRxLock = ( int8_t ) ( ( cRxLock ) + ( int8_t ) 1 ); \
+ } \
+ }
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
@@ -353,16 +383,16 @@
( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) )
{
#if ( configASSERT_DEFINED == 1 )
- {
- /* Sanity check that the size of the structure used to declare a
- * variable of type StaticQueue_t or StaticSemaphore_t equals the size of
- * the real queue and semaphore structures. */
- volatile size_t xSize = sizeof( StaticQueue_t );
+ {
+ /* Sanity check that the size of the structure used to declare a
+ * variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+ * the real queue and semaphore structures. */
+ volatile size_t xSize = sizeof( StaticQueue_t );
- /* This assertion cannot be branch covered in unit tests */
- configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
- ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
- }
+ /* This assertion cannot be branch covered in unit tests */
+ configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
+ ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ }
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
@@ -371,12 +401,12 @@
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- /* Queues can be allocated wither statically or dynamically, so
- * note this queue was allocated statically in case the queue is
- * later deleted. */
- pxNewQueue->ucStaticallyAllocated = pdTRUE;
- }
+ {
+ /* Queues can be allocated wither statically or dynamically, so
+ * note this queue was allocated statically in case the queue is
+ * later deleted. */
+ pxNewQueue->ucStaticallyAllocated = pdTRUE;
+ }
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
@@ -433,12 +463,12 @@
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- /* Queues can be created either statically or dynamically, so
- * note this task was created dynamically in case it is later
- * deleted. */
- pxNewQueue->ucStaticallyAllocated = pdFALSE;
- }
+ {
+ /* Queues can be created either statically or dynamically, so
+ * note this task was created dynamically in case it is later
+ * deleted. */
+ pxNewQueue->ucStaticallyAllocated = pdFALSE;
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
@@ -492,15 +522,15 @@
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
#if ( configUSE_TRACE_FACILITY == 1 )
- {
- pxNewQueue->ucQueueType = ucQueueType;
- }
+ {
+ pxNewQueue->ucQueueType = ucQueueType;
+ }
#endif /* configUSE_TRACE_FACILITY */
#if ( configUSE_QUEUE_SETS == 1 )
- {
- pxNewQueue->pxQueueSetContainer = NULL;
- }
+ {
+ pxNewQueue->pxQueueSetContainer = NULL;
+ }
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
@@ -815,9 +845,9 @@
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
#endif
/*lint -save -e904 This function relaxes the coding standard somewhat to
@@ -836,69 +866,34 @@
traceQUEUE_SEND( pxQueue );
#if ( configUSE_QUEUE_SETS == 1 )
+ {
+ const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+ if( pxQueue->pxQueueSetContainer != NULL )
{
- const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
-
- xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
- if( pxQueue->pxQueueSetContainer != NULL )
+ if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
{
- if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
- {
- /* Do not notify the queue set as an existing item
- * was overwritten in the queue so the number of items
- * in the queue has not changed. */
- mtCOVERAGE_TEST_MARKER();
- }
- else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
- {
- /* The queue is a member of a queue set, and posting
- * to the queue set caused a higher priority task to
- * unblock. A context switch is required. */
- queueYIELD_IF_USING_PREEMPTION();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* Do not notify the queue set as an existing item
+ * was overwritten in the queue so the number of items
+ * in the queue has not changed. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+ {
+ /* The queue is a member of a queue set, and posting
+ * to the queue set caused a higher priority task to
+ * unblock. A context switch is required. */
+ queueYIELD_IF_USING_PREEMPTION();
}
else
{
- /* If there was a task waiting for data to arrive on the
- * queue then unblock it now. */
- if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
- {
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- /* The unblocked task has a priority higher than
- * our own so yield immediately. Yes it is ok to
- * do this from within the critical section - the
- * kernel takes care of that. */
- queueYIELD_IF_USING_PREEMPTION();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else if( xYieldRequired != pdFALSE )
- {
- /* This path is a special case that will only get
- * executed if the task was holding multiple mutexes
- * and the mutexes were given back in an order that is
- * different to that in which they were taken. */
- queueYIELD_IF_USING_PREEMPTION();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ mtCOVERAGE_TEST_MARKER();
}
}
- #else /* configUSE_QUEUE_SETS */
+ else
{
- xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
/* If there was a task waiting for data to arrive on the
* queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
@@ -906,9 +901,9 @@
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
/* The unblocked task has a priority higher than
- * our own so yield immediately. Yes it is ok to do
- * this from within the critical section - the kernel
- * takes care of that. */
+ * our own so yield immediately. Yes it is ok to
+ * do this from within the critical section - the
+ * kernel takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
}
else
@@ -919,8 +914,8 @@
else if( xYieldRequired != pdFALSE )
{
/* This path is a special case that will only get
- * executed if the task was holding multiple mutexes and
- * the mutexes were given back in an order that is
+ * executed if the task was holding multiple mutexes
+ * and the mutexes were given back in an order that is
* different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
}
@@ -929,6 +924,41 @@
mtCOVERAGE_TEST_MARKER();
}
}
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+ /* If there was a task waiting for data to arrive on the
+ * queue then unblock it now. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The unblocked task has a priority higher than
+ * our own so yield immediately. Yes it is ok to do
+ * this from within the critical section - the kernel
+ * takes care of that. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( xYieldRequired != pdFALSE )
+ {
+ /* This path is a special case that will only get
+ * executed if the task was holding multiple mutexes and
+ * the mutexes were given back in an order that is
+ * different to that in which they were taken. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
@@ -1069,29 +1099,24 @@
if( cTxLock == queueUNLOCKED )
{
#if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
{
- if( pxQueue->pxQueueSetContainer != NULL )
+ if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
{
- if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+ /* Do not notify the queue set as an existing item
+ * was overwritten in the queue so the number of items
+ * in the queue has not changed. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+ {
+ /* The queue is a member of a queue set, and posting
+ * to the queue set caused a higher priority task to
+ * unblock. A context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
{
- /* Do not notify the queue set as an existing item
- * was overwritten in the queue so the number of items
- * in the queue has not changed. */
- mtCOVERAGE_TEST_MARKER();
- }
- else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
- {
- /* The queue is a member of a queue set, and posting
- * to the queue set caused a higher priority task to
- * unblock. A context switch is required. */
- if( pxHigherPriorityTaskWoken != NULL )
- {
- *pxHigherPriorityTaskWoken = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ *pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
@@ -1100,40 +1125,17 @@
}
else
{
- if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
- {
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- /* The task waiting has a higher priority so
- * record that a context switch is required. */
- if( pxHigherPriorityTaskWoken != NULL )
- {
- *pxHigherPriorityTaskWoken = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ mtCOVERAGE_TEST_MARKER();
}
}
- #else /* configUSE_QUEUE_SETS */
+ else
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
- /* The task waiting has a higher priority so record that a
- * context switch is required. */
+ /* The task waiting has a higher priority so
+ * record that a context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
@@ -1152,19 +1154,45 @@
{
mtCOVERAGE_TEST_MARKER();
}
-
- /* Not used in this path. */
- ( void ) uxPreviousMessagesWaiting;
}
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ * context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Not used in this path. */
+ ( void ) uxPreviousMessagesWaiting;
+ }
#endif /* configUSE_QUEUE_SETS */
}
else
{
/* Increment the lock count so the task that unlocks the queue
* knows that data was posted while it was locked. */
- configASSERT( cTxLock != queueINT8_MAX );
-
- pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ prvIncrementQueueTxLock( pxQueue, cTxLock );
}
xReturn = pdPASS;
@@ -1247,22 +1275,17 @@
if( cTxLock == queueUNLOCKED )
{
#if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
{
- if( pxQueue->pxQueueSetContainer != NULL )
+ if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
{
- if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+ /* The semaphore is a member of a queue set, and
+ * posting to the queue set caused a higher priority
+ * task to unblock. A context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
{
- /* The semaphore is a member of a queue set, and
- * posting to the queue set caused a higher priority
- * task to unblock. A context switch is required. */
- if( pxHigherPriorityTaskWoken != NULL )
- {
- *pxHigherPriorityTaskWoken = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ *pxHigherPriorityTaskWoken = pdTRUE;
}
else
{
@@ -1271,40 +1294,17 @@
}
else
{
- if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
- {
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- /* The task waiting has a higher priority so
- * record that a context switch is required. */
- if( pxHigherPriorityTaskWoken != NULL )
- {
- *pxHigherPriorityTaskWoken = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ mtCOVERAGE_TEST_MARKER();
}
}
- #else /* configUSE_QUEUE_SETS */
+ else
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
- /* The task waiting has a higher priority so record that a
- * context switch is required. */
+ /* The task waiting has a higher priority so
+ * record that a context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
{
*pxHigherPriorityTaskWoken = pdTRUE;
@@ -1324,15 +1324,41 @@
mtCOVERAGE_TEST_MARKER();
}
}
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ * context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_QUEUE_SETS */
}
else
{
/* Increment the lock count so the task that unlocks the queue
* knows that data was posted while it was locked. */
- configASSERT( cTxLock != queueINT8_MAX );
-
- pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ prvIncrementQueueTxLock( pxQueue, cTxLock );
}
xReturn = pdPASS;
@@ -1366,9 +1392,9 @@
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
#endif
/*lint -save -e904 This function relaxes the coding standard somewhat to
@@ -1512,9 +1538,9 @@
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
#endif
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
@@ -1539,18 +1565,18 @@
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
#if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
- if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
- {
- /* Record the information required to implement
- * priority inheritance should it become necessary. */
- pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* Record the information required to implement
+ * priority inheritance should it become necessary. */
+ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_MUTEXES */
/* Check to see if other tasks are blocked waiting to give the
@@ -1578,15 +1604,6 @@
{
if( xTicksToWait == ( TickType_t ) 0 )
{
- /* For inheritance to have occurred there must have been an
- * initial timeout, and an adjusted timeout cannot become 0, as
- * if it were 0 the function would have exited. */
- #if ( configUSE_MUTEXES == 1 )
- {
- configASSERT( xInheritanceOccurred == pdFALSE );
- }
- #endif /* configUSE_MUTEXES */
-
/* The semaphore count was 0 and no block time is specified
* (or the block time has expired) so exit now. */
taskEXIT_CRITICAL();
@@ -1627,20 +1644,20 @@
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
- if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ taskENTER_CRITICAL();
{
- taskENTER_CRITICAL();
- {
- xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
- }
- taskEXIT_CRITICAL();
+ xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
}
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ taskEXIT_CRITICAL();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* if ( configUSE_MUTEXES == 1 ) */
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
@@ -1676,27 +1693,27 @@
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
{
#if ( configUSE_MUTEXES == 1 )
+ {
+ /* xInheritanceOccurred could only have be set if
+ * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+ * test the mutex type again to check it is actually a mutex. */
+ if( xInheritanceOccurred != pdFALSE )
{
- /* xInheritanceOccurred could only have be set if
- * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
- * test the mutex type again to check it is actually a mutex. */
- if( xInheritanceOccurred != pdFALSE )
+ taskENTER_CRITICAL();
{
- taskENTER_CRITICAL();
- {
- UBaseType_t uxHighestWaitingPriority;
+ UBaseType_t uxHighestWaitingPriority;
- /* This task blocking on the mutex caused another
- * task to inherit this task's priority. Now this task
- * has timed out the priority should be disinherited
- * again, but only as low as the next highest priority
- * task that is waiting for the same mutex. */
- uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
- vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
- }
- taskEXIT_CRITICAL();
+ /* This task blocking on the mutex caused another
+ * task to inherit this task's priority. Now this task
+ * has timed out the priority should be disinherited
+ * again, but only as low as the next highest priority
+ * task that is waiting for the same mutex. */
+ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+ vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
}
+ taskEXIT_CRITICAL();
}
+ }
#endif /* configUSE_MUTEXES */
traceQUEUE_RECEIVE_FAILED( pxQueue );
@@ -1729,9 +1746,9 @@
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
- {
- configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
- }
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
#endif
/*lint -save -e904 This function relaxes the coding standard somewhat to
@@ -1938,9 +1955,7 @@
{
/* Increment the lock count so the task that unlocks the queue
* knows that data was removed while it was locked. */
- configASSERT( cRxLock != queueINT8_MAX );
-
- pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+ prvIncrementQueueRxLock( pxQueue, cRxLock );
}
xReturn = pdPASS;
@@ -2065,36 +2080,36 @@
traceQUEUE_DELETE( pxQueue );
#if ( configQUEUE_REGISTRY_SIZE > 0 )
- {
- vQueueUnregisterQueue( pxQueue );
- }
+ {
+ vQueueUnregisterQueue( pxQueue );
+ }
#endif
#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+ {
+ /* The queue can only have been allocated dynamically - free it
+ * again. */
+ vPortFree( pxQueue );
+ }
+ #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ {
+ /* The queue could have been allocated statically or dynamically, so
+ * check before attempting to free the memory. */
+ if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
{
- /* The queue can only have been allocated dynamically - free it
- * again. */
vPortFree( pxQueue );
}
- #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ else
{
- /* The queue could have been allocated statically or dynamically, so
- * check before attempting to free the memory. */
- if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
- {
- vPortFree( pxQueue );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ mtCOVERAGE_TEST_MARKER();
}
+ }
#else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */
- {
- /* The queue must have been statically allocated, so is not going to be
- * deleted. Avoid compiler warnings about the unused parameter. */
- ( void ) pxQueue;
- }
+ {
+ /* The queue must have been statically allocated, so is not going to be
+ * deleted. Avoid compiler warnings about the unused parameter. */
+ ( void ) pxQueue;
+ }
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
/*-----------------------------------------------------------*/
@@ -2171,18 +2186,18 @@
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
{
#if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
- if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
- {
- /* The mutex is no longer being held. */
- xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
- pxQueue->u.xSemaphore.xMutexHolder = NULL;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* The mutex is no longer being held. */
+ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+ pxQueue->u.xSemaphore.xMutexHolder = NULL;
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
@@ -2279,55 +2294,32 @@
/* Data was posted while the queue was locked. Are any tasks
* blocked waiting for data to become available? */
#if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
{
- if( pxQueue->pxQueueSetContainer != NULL )
+ if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
{
- if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
- {
- /* The queue is a member of a queue set, and posting to
- * the queue set caused a higher priority task to unblock.
- * A context switch is required. */
- vTaskMissedYield();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* The queue is a member of a queue set, and posting to
+ * the queue set caused a higher priority task to unblock.
+ * A context switch is required. */
+ vTaskMissedYield();
}
else
{
- /* Tasks that are removed from the event list will get
- * added to the pending ready list as the scheduler is still
- * suspended. */
- if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
- {
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- /* The task waiting has a higher priority so record that a
- * context switch is required. */
- vTaskMissedYield();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- else
- {
- break;
- }
+ mtCOVERAGE_TEST_MARKER();
}
}
- #else /* configUSE_QUEUE_SETS */
+ else
{
- /* Tasks that are removed from the event list will get added to
- * the pending ready list as the scheduler is still suspended. */
+ /* Tasks that are removed from the event list will get
+ * added to the pending ready list as the scheduler is still
+ * suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
{
- /* The task waiting has a higher priority so record that
- * a context switch is required. */
+ /* The task waiting has a higher priority so record that a
+ * context switch is required. */
vTaskMissedYield();
}
else
@@ -2340,6 +2332,29 @@
break;
}
}
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ /* Tasks that are removed from the event list will get added to
+ * the pending ready list as the scheduler is still suspended. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that
+ * a context switch is required. */
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
@@ -2756,11 +2771,10 @@
const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
UBaseType_t ux;
+ QueueRegistryItem_t * pxEntryToWrite = NULL;
configASSERT( xQueue );
- QueueRegistryItem_t * pxEntryToWrite = NULL;
-
if( pcQueueName != NULL )
{
/* See if there is an empty space in the registry. A NULL name denotes
@@ -3059,9 +3073,7 @@
}
else
{
- configASSERT( cTxLock != queueINT8_MAX );
-
- pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ prvIncrementQueueTxLock( pxQueueSetContainer, cTxLock );
}
}
else
diff --git a/Source/st_readme.txt b/Source/st_readme.txt
index 08d69d0..0736166 100644
--- a/Source/st_readme.txt
+++ b/Source/st_readme.txt
@@ -16,10 +16,10 @@
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
-*
+*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
-*
+*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -32,6 +32,41 @@
=======
+### 18-August-2023 ###
+=========================
+ + LICENSE update
+ - Add a LICENSE.md file at the root of the directory
+
+### 19-May-2023 ###
+=========================
+ + FreeRTOS: Update to FreeRTOS v10.5.1
+
+ + Add portmacrocommon files:
+
+ - GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+ - GCC/ARM_CM23/non_secure/portmacrocommon.h
+ - GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+ - GCC/ARM_CM33/non_secure/portmacrocommon.h
+ - IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
+ - IAR/ARM_CM23/non_secure/portmacrocommon.h
+ - IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
+ - IAR/ARM_CM33/non_secure/portmacrocommon.h
+
+ + Delete ARM_CM7_MPU files :
+ - GCC/ARM_CM7_MPU/r0p1/port.c
+ - GCC/ARM_CM7_MPU/r0p1/portmacro.h
+ - GCC/ARM_CM7_MPU/ReadMe.txt
+ - IAR/ARM_CM7_MPU/r0p1/port.c
+ - IAR/ARM_CM7_MPU/r0p1/portasm.s
+ - IAR/ARM_CM7_MPU/r0p1/portmacro.h
+ - IAR/ARM_CM7_MPU/ReadMe.txt
+ - RVDS/ARM_CM7_MPU/r0p1/port.c
+ - RVDS/ARM_CM7_MPU/r0p1/portmacro.h
+ - RVDS/ARM_CM7_MPU/ReadMe.txt
+
+ + CMSIS_RTOS_V2: update against the latest CMSIS-FreeRTOS v10.5.1 release
+ - CMSIS_RTOS_V2/cmsis_os2.c
+
### 05-August-2022 ###
=========================
+ FreeRTOS: Update to FreeRTOS v10.4.6
@@ -44,12 +79,12 @@
- IAR/ARM_CM7_MPU/r0p1/portmacro.h
- RVDS/ARM_CM7_MPU/r0p1/port.c
- RVDS/ARM_CM7_MPU/r0p1/portmacro.h
-
+
+ CMSIS_RTOS_V2: update against the latest CMSIS-FreeRTOS v10.4.6 release
- CMSIS_RTOS_V2/cmsis_os2.c
- CMSIS_RTOS_V2/freertos_os2.h
- + CMSIS_RTOS_V2: Remove the following files as cmsis_RTOS1 is no more supported
+ + CMSIS_RTOS_V2: Remove the following files as cmsis_RTOS1 is no more supported
(applications should use cmsis_os2.h file under Drivers/CMSIS/RTOS2/Include)
- CMSIS_RTOS_V2/cmsis_os.h
- CMSIS_RTOS_V2/cmsis_os2.h
@@ -68,7 +103,7 @@
### 20-July-2020 ###
=========================
+ FreeRTOS: Update to FreeRTOS v10.3.1
-
+
+ CMSIS_RTOS_V2: update against the latest CMSIS-FreeRTOS v10.3.0 release
- CMSIS_RTOS_V2/cmsis_os2.c
- CMSIS_RTOS_V2/freertos_mpool.h
@@ -91,7 +126,7 @@
- IAR/ARM_CM33/non_secure/portmacro.h
- IAR/ARM_CM33_NTZ/non_secure/port.c
- IAR/ARM_CM33_NTZ/non_secure/portmacro.h
-
+
+ Fix MPU hardfault bug for Cortex-M4 MPU
- GCC\ARM_CM4_MPU\port.c
- IAR\ARM_CM4_MPU\port.c
diff --git a/Source/stream_buffer.c b/Source/stream_buffer.c
index cf6300f..fed7eb8 100644
--- a/Source/stream_buffer.c
+++ b/Source/stream_buffer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -44,6 +44,10 @@
#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
#endif
+#if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )
+ #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
+#endif
+
/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
* because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
* for the header files above, but not in this file, in order to generate the
@@ -69,6 +73,25 @@
( void ) xTaskResumeAll();
#endif /* sbRECEIVE_COMPLETED */
+/* If user has provided a per-instance receive complete callback, then
+ * invoke the callback else use the receive complete macro which is provided by default for all instances.
+ */
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvRECEIVE_COMPLETED( pxStreamBuffer ) \
+ { \
+ if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \
+ { \
+ ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
+ } \
+ else \
+ { \
+ sbRECEIVE_COMPLETED( ( pxStreamBuffer ) ); \
+ } \
+ }
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvRECEIVE_COMPLETED( pxStreamBuffer ) sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
#ifndef sbRECEIVE_COMPLETED_FROM_ISR
#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \
pxHigherPriorityTaskWoken ) \
@@ -82,7 +105,7 @@
( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
( uint32_t ) 0, \
eNoAction, \
- pxHigherPriorityTaskWoken ); \
+ ( pxHigherPriorityTaskWoken ) ); \
( pxStreamBuffer )->xTaskWaitingToSend = NULL; \
} \
} \
@@ -90,9 +113,28 @@
}
#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \
+ pxHigherPriorityTaskWoken ) \
+ { \
+ if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \
+ { \
+ ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \
+ } \
+ else \
+ { \
+ sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \
+ } \
+ }
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
/* If the user has not provided an application specific Tx notification macro,
- * or #defined the notification macro away, them provide a default implementation
- * that uses task notifications. */
+ * or #defined the notification macro away, then provide a default
+ * implementation that uses task notifications.
+ */
#ifndef sbSEND_COMPLETED
#define sbSEND_COMPLETED( pxStreamBuffer ) \
vTaskSuspendAll(); \
@@ -108,6 +150,26 @@
( void ) xTaskResumeAll();
#endif /* sbSEND_COMPLETED */
+/* If user has provided a per-instance send completed callback, then
+ * invoke the callback else use the send complete macro which is provided by default for all instances.
+ */
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvSEND_COMPLETED( pxStreamBuffer ) \
+ { \
+ if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \
+ { \
+ pxStreamBuffer->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
+ } \
+ else \
+ { \
+ sbSEND_COMPLETED( ( pxStreamBuffer ) ); \
+ } \
+ }
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvSEND_COMPLETED( pxStreamBuffer ) sbSEND_COMPLETED( ( pxStreamBuffer ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
+
#ifndef sbSEND_COMPLETE_FROM_ISR
#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
{ \
@@ -120,13 +182,32 @@
( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
( uint32_t ) 0, \
eNoAction, \
- pxHigherPriorityTaskWoken ); \
+ ( pxHigherPriorityTaskWoken ) ); \
( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \
} \
} \
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
}
#endif /* sbSEND_COMPLETE_FROM_ISR */
+
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ { \
+ if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \
+ { \
+ ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \
+ } \
+ else \
+ { \
+ sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \
+ } \
+ }
+#else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+ #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
+#endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
+
/*lint -restore (9026) */
/* The number of bytes used to hold the length of a message in the buffer. */
@@ -153,6 +234,11 @@
#if ( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */
#endif
+
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ StreamBufferCallbackFunction_t pxSendCompletedCallback; /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete. sbRECEIVE_COMPLETED is called if this is NULL. */
+ #endif
} StreamBuffer_t;
/*
@@ -226,15 +312,17 @@
uint8_t * const pucBuffer,
size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+ uint8_t ucFlags,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
-
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer )
+ BaseType_t xIsMessageBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
{
uint8_t * pucAllocatedMemory;
uint8_t ucFlags;
@@ -289,7 +377,9 @@
pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
xBufferSizeBytes,
xTriggerLevelBytes,
- ucFlags );
+ ucFlags,
+ pxSendCompletedCallback,
+ pxReceiveCompletedCallback );
traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
}
@@ -300,7 +390,6 @@
return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
}
-
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/
@@ -310,7 +399,9 @@
size_t xTriggerLevelBytes,
BaseType_t xIsMessageBuffer,
uint8_t * const pucStreamBufferStorageArea,
- StaticStreamBuffer_t * const pxStaticStreamBuffer )
+ StaticStreamBuffer_t * const pxStaticStreamBuffer,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
{
StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
StreamBufferHandle_t xReturn;
@@ -345,13 +436,13 @@
configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
#if ( configASSERT_DEFINED == 1 )
- {
- /* Sanity check that the size of the structure used to declare a
- * variable of type StaticStreamBuffer_t equals the size of the real
- * message buffer structure. */
- volatile size_t xSize = sizeof( StaticStreamBuffer_t );
- configASSERT( xSize == sizeof( StreamBuffer_t ) );
- } /*lint !e529 xSize is referenced is configASSERT() is defined. */
+ {
+ /* Sanity check that the size of the structure used to declare a
+ * variable of type StaticStreamBuffer_t equals the size of the real
+ * message buffer structure. */
+ volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+ configASSERT( xSize == sizeof( StreamBuffer_t ) );
+ } /*lint !e529 xSize is referenced is configASSERT() is defined. */
#endif /* configASSERT_DEFINED */
if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
@@ -360,7 +451,9 @@
pucStreamBufferStorageArea,
xBufferSizeBytes,
xTriggerLevelBytes,
- ucFlags );
+ ucFlags,
+ pxSendCompletedCallback,
+ pxReceiveCompletedCallback );
/* Remember this was statically allocated in case it is ever deleted
* again. */
@@ -378,7 +471,6 @@
return xReturn;
}
-
#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/
@@ -393,17 +485,17 @@
if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
{
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- /* Both the structure and the buffer were allocated using a single call
- * to pvPortMalloc(), hence only one call to vPortFree() is required. */
- vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
- }
+ {
+ /* Both the structure and the buffer were allocated using a single call
+ * to pvPortMalloc(), hence only one call to vPortFree() is required. */
+ vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+ }
#else
- {
- /* Should not be possible to get here, ucFlags must be corrupt.
- * Force an assert. */
- configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
- }
+ {
+ /* Should not be possible to get here, ucFlags must be corrupt.
+ * Force an assert. */
+ configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+ }
#endif
}
else
@@ -419,6 +511,7 @@
{
StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
BaseType_t xReturn = pdFAIL;
+ StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL;
#if ( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxStreamBufferNumber;
@@ -427,35 +520,42 @@
configASSERT( pxStreamBuffer );
#if ( configUSE_TRACE_FACILITY == 1 )
- {
- /* Store the stream buffer number so it can be restored after the
- * reset. */
- uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
- }
+ {
+ /* Store the stream buffer number so it can be restored after the
+ * reset. */
+ uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+ }
#endif
/* Can only reset a message buffer if there are no tasks blocked on it. */
taskENTER_CRITICAL();
{
- if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+ if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
{
- if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
{
- prvInitialiseNewStreamBuffer( pxStreamBuffer,
- pxStreamBuffer->pucBuffer,
- pxStreamBuffer->xLength,
- pxStreamBuffer->xTriggerLevelBytes,
- pxStreamBuffer->ucFlags );
- xReturn = pdPASS;
-
- #if ( configUSE_TRACE_FACILITY == 1 )
- {
- pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
- }
- #endif
-
- traceSTREAM_BUFFER_RESET( xStreamBuffer );
+ pxSendCallback = pxStreamBuffer->pxSendCompletedCallback;
+ pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback;
}
+ #endif
+
+ prvInitialiseNewStreamBuffer( pxStreamBuffer,
+ pxStreamBuffer->pucBuffer,
+ pxStreamBuffer->xLength,
+ pxStreamBuffer->xTriggerLevelBytes,
+ pxStreamBuffer->ucFlags,
+ pxSendCallback,
+ pxReceiveCallback );
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+ }
+ #endif
+
+ traceSTREAM_BUFFER_RESET( xStreamBuffer );
+
+ xReturn = pdPASS;
}
}
taskEXIT_CRITICAL();
@@ -653,7 +753,7 @@
/* Was a task waiting for the data? */
if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
{
- sbSEND_COMPLETED( pxStreamBuffer );
+ prvSEND_COMPLETED( pxStreamBuffer );
}
else
{
@@ -703,7 +803,7 @@
/* Was a task waiting for the data? */
if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
{
- sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+ prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
}
else
{
@@ -728,17 +828,24 @@
size_t xRequiredSpace )
{
size_t xNextHead = pxStreamBuffer->xHead;
+ configMESSAGE_BUFFER_LENGTH_TYPE xMessageLength;
if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
{
/* This is a message buffer, as opposed to a stream buffer. */
+ /* Convert xDataLengthBytes to the message length type. */
+ xMessageLength = ( configMESSAGE_BUFFER_LENGTH_TYPE ) xDataLengthBytes;
+
+ /* Ensure the data length given fits within configMESSAGE_BUFFER_LENGTH_TYPE. */
+ configASSERT( ( size_t ) xMessageLength == xDataLengthBytes );
+
if( xSpace >= xRequiredSpace )
{
/* There is enough space to write both the message length and the message
* itself into the buffer. Start by writing the length of the data, the data
* itself will be written later in this function. */
- xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead );
+ xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xMessageLength ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead );
}
else
{
@@ -851,7 +958,7 @@
if( xReceivedLength != ( size_t ) 0 )
{
traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
- sbRECEIVE_COMPLETED( pxStreamBuffer );
+ prvRECEIVE_COMPLETED( xStreamBuffer );
}
else
{
@@ -947,7 +1054,7 @@
/* Was a task waiting for space in the buffer? */
if( xReceivedLength != ( size_t ) 0 )
{
- sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+ prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
}
else
{
@@ -1253,19 +1360,21 @@
uint8_t * const pucBuffer,
size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- uint8_t ucFlags )
+ uint8_t ucFlags,
+ StreamBufferCallbackFunction_t pxSendCompletedCallback,
+ StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
{
/* Assert here is deliberately writing to the entire buffer to ensure it can
* be written to without generating exceptions, and is setting the buffer to a
* known value to assist in development/debugging. */
#if ( configASSERT_DEFINED == 1 )
- {
- /* The value written just has to be identifiable when looking at the
- * memory. Don't use 0xA5 as that is the stack fill value and could
- * result in confusion as to what is actually being observed. */
- const BaseType_t xWriteValue = 0x55;
- configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
- } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+ {
+ /* The value written just has to be identifiable when looking at the
+ * memory. Don't use 0xA5 as that is the stack fill value and could
+ * result in confusion as to what is actually being observed. */
+ const BaseType_t xWriteValue = 0x55;
+ configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+ } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
#endif
( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
@@ -1273,6 +1382,17 @@
pxStreamBuffer->xLength = xBufferSizeBytes;
pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
pxStreamBuffer->ucFlags = ucFlags;
+ #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+ {
+ pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback;
+ pxStreamBuffer->pxReceiveCompletedCallback = pxReceiveCompletedCallback;
+ }
+ #else
+ {
+ ( void ) pxSendCompletedCallback;
+ ( void ) pxReceiveCompletedCallback;
+ }
+ #endif
}
#if ( configUSE_TRACE_FACILITY == 1 )
diff --git a/Source/tasks.c b/Source/tasks.c
index 6bd84ce..0cc948f 100644
--- a/Source/tasks.c
+++ b/Source/tasks.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -165,7 +165,7 @@
* architecture being used. */
/* A port optimised version is provided. Call the port defined macros. */
- #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+ #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( ( uxPriority ), uxTopReadyPriority )
/*-----------------------------------------------------------*/
@@ -296,19 +296,8 @@
configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
#endif
- #if ( configUSE_NEWLIB_REENTRANT == 1 )
-
- /* Allocate a Newlib reent structure that is specific to this task.
- * Note Newlib support has been included by popular demand, but is not
- * used by the FreeRTOS maintainers themselves. FreeRTOS is not
- * responsible for resulting newlib operation. User must be familiar with
- * newlib and must provide system-wide implementations of the necessary
- * stubs. Be warned that (at the time of writing) the current newlib design
- * implements a system-wide malloc() that must be provided with locks.
- *
- * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
- * for additional information. */
- struct _reent xNewLib_reent;
+ #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )
+ configTLS_BLOCK_TYPE xTLSBlock; /*< Memory block used as Thread Local Storage (TLS) Block for the task. */
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
@@ -337,7 +326,7 @@
/*lint -save -e956 A manual analysis and inspection has been used to determine
* which static variables must be declared volatile. */
-PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
/* Lists for ready and blocked tasks. --------------------
* xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but
@@ -527,7 +516,7 @@
*/
static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
/*
* Helper function used to pad task names with spaces when printing out
@@ -587,14 +576,14 @@
configASSERT( pxTaskBuffer != NULL );
#if ( configASSERT_DEFINED == 1 )
- {
- /* Sanity check that the size of the structure used to declare a
- * variable of type StaticTask_t equals the size of the real task
- * structure. */
- volatile size_t xSize = sizeof( StaticTask_t );
- configASSERT( xSize == sizeof( TCB_t ) );
- ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
- }
+ {
+ /* Sanity check that the size of the structure used to declare a
+ * variable of type StaticTask_t equals the size of the real task
+ * structure. */
+ volatile size_t xSize = sizeof( StaticTask_t );
+ configASSERT( xSize == sizeof( TCB_t ) );
+ ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+ }
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
@@ -602,14 +591,15 @@
/* The memory used for the task's TCB and stack are passed into this
* function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
- {
- /* Tasks can be created statically or dynamically, so note this
- * task was created statically in case the task is later deleted. */
- pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
- }
+ {
+ /* Tasks can be created statically or dynamically, so note this
+ * task was created statically in case the task is later deleted. */
+ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+ }
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
@@ -643,16 +633,17 @@
* on the implementation of the port malloc function and whether or
* not static allocation is being used. */
pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+ memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
- {
- /* Tasks can be created statically or dynamically, so note this
- * task was created statically in case the task is later deleted. */
- pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
- }
+ {
+ /* Tasks can be created statically or dynamically, so note this
+ * task was created statically in case the task is later deleted. */
+ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+ }
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
@@ -692,16 +683,18 @@
if( pxNewTCB != NULL )
{
+ memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
- {
- /* Tasks can be created statically or dynamically, so note
- * this task had a statically allocated stack in case it is
- * later deleted. The TCB was allocated dynamically. */
- pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
- }
+ {
+ /* Tasks can be created statically or dynamically, so note
+ * this task had a statically allocated stack in case it is
+ * later deleted. The TCB was allocated dynamically. */
+ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+ }
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
@@ -739,66 +732,70 @@
* does not grow into the TCB. Likewise if the stack grows up then allocate
* the TCB then the stack. */
#if ( portSTACK_GROWTH > 0 )
+ {
+ /* Allocate space for the TCB. Where the memory comes from depends on
+ * the implementation of the port malloc function and whether or not static
+ * allocation is being used. */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+ if( pxNewTCB != NULL )
{
- /* Allocate space for the TCB. Where the memory comes from depends on
- * the implementation of the port malloc function and whether or not static
- * allocation is being used. */
- pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+ memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
- if( pxNewTCB != NULL )
+ /* Allocate space for the stack used by the task being created.
+ * The base of the stack memory stored in the TCB so the task can
+ * be deleted later if required. */
+ pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ if( pxNewTCB->pxStack == NULL )
{
- /* Allocate space for the stack used by the task being created.
- * The base of the stack memory stored in the TCB so the task can
- * be deleted later if required. */
- pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
- if( pxNewTCB->pxStack == NULL )
- {
- /* Could not allocate the stack. Delete the allocated TCB. */
- vPortFree( pxNewTCB );
- pxNewTCB = NULL;
- }
- }
- }
- #else /* portSTACK_GROWTH */
- {
- StackType_t * pxStack;
-
- /* Allocate space for the stack used by the task being created. */
- pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
-
- if( pxStack != NULL )
- {
- /* Allocate space for the TCB. */
- pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
-
- if( pxNewTCB != NULL )
- {
- /* Store the stack location in the TCB. */
- pxNewTCB->pxStack = pxStack;
- }
- else
- {
- /* The stack cannot be used as the TCB was not created. Free
- * it again. */
- vPortFreeStack( pxStack );
- }
- }
- else
- {
+ /* Could not allocate the stack. Delete the allocated TCB. */
+ vPortFree( pxNewTCB );
pxNewTCB = NULL;
}
}
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ StackType_t * pxStack;
+
+ /* Allocate space for the stack used by the task being created. */
+ pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+ if( pxStack != NULL )
+ {
+ /* Allocate space for the TCB. */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+ if( pxNewTCB != NULL )
+ {
+ memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
+
+ /* Store the stack location in the TCB. */
+ pxNewTCB->pxStack = pxStack;
+ }
+ else
+ {
+ /* The stack cannot be used as the TCB was not created. Free
+ * it again. */
+ vPortFreeStack( pxStack );
+ }
+ }
+ else
+ {
+ pxNewTCB = NULL;
+ }
+ }
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
{
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
- {
- /* Tasks can be created statically or dynamically, so note this
- * task was created dynamically in case it is later deleted. */
- pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
- }
+ {
+ /* Tasks can be created statically or dynamically, so note this
+ * task was created dynamically in case it is later deleted. */
+ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+ }
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
@@ -845,10 +842,10 @@
/* Avoid dependency on memset() if it is not required. */
#if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
- {
- /* Fill the stack with a known value to assist debugging. */
- ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
- }
+ {
+ /* Fill the stack with a known value to assist debugging. */
+ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+ }
#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
/* Calculate the top of stack address. This depends on whether the stack
@@ -856,32 +853,32 @@
* portSTACK_GROWTH is used to make the result positive or negative as required
* by the port. */
#if ( portSTACK_GROWTH < 0 )
+ {
+ pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+ pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
+
+ /* Check the alignment of the calculated top of stack is correct. */
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+ #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
{
- pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
- pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
-
- /* Check the alignment of the calculated top of stack is correct. */
- configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
-
- #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
- {
- /* Also record the stack's high address, which may assist
- * debugging. */
- pxNewTCB->pxEndOfStack = pxTopOfStack;
- }
- #endif /* configRECORD_STACK_HIGH_ADDRESS */
+ /* Also record the stack's high address, which may assist
+ * debugging. */
+ pxNewTCB->pxEndOfStack = pxTopOfStack;
}
+ #endif /* configRECORD_STACK_HIGH_ADDRESS */
+ }
#else /* portSTACK_GROWTH */
- {
- pxTopOfStack = pxNewTCB->pxStack;
+ {
+ pxTopOfStack = pxNewTCB->pxStack;
- /* Check the alignment of the stack buffer is correct. */
- configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+ /* Check the alignment of the stack buffer is correct. */
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
- /* The other extreme of the stack space is required if stack checking is
- * performed. */
- pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
- }
+ /* The other extreme of the stack space is required if stack checking is
+ * performed. */
+ pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+ }
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
@@ -910,9 +907,7 @@
}
else
{
- /* The task has not been given a name, so just ensure there is a NULL
- * terminator when it is read out. */
- pxNewTCB->pcTaskName[ 0 ] = 0x00;
+ mtCOVERAGE_TEST_MARKER();
}
/* This is used as an array index so must ensure it's not too large. */
@@ -929,10 +924,9 @@
pxNewTCB->uxPriority = uxPriority;
#if ( configUSE_MUTEXES == 1 )
- {
- pxNewTCB->uxBasePriority = uxPriority;
- pxNewTCB->uxMutexesHeld = 0;
- }
+ {
+ pxNewTCB->uxBasePriority = uxPriority;
+ }
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
@@ -946,61 +940,22 @@
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
- #if ( portCRITICAL_NESTING_IN_TCB == 1 )
- {
- pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
- }
- #endif /* portCRITICAL_NESTING_IN_TCB */
-
- #if ( configUSE_APPLICATION_TASK_TAG == 1 )
- {
- pxNewTCB->pxTaskTag = NULL;
- }
- #endif /* configUSE_APPLICATION_TASK_TAG */
-
- #if ( configGENERATE_RUN_TIME_STATS == 1 )
- {
- pxNewTCB->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0;
- }
- #endif /* configGENERATE_RUN_TIME_STATS */
-
#if ( portUSING_MPU_WRAPPERS == 1 )
- {
- vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
- }
+ {
+ vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+ }
#else
- {
- /* Avoid compiler warning about unreferenced parameter. */
- ( void ) xRegions;
- }
+ {
+ /* Avoid compiler warning about unreferenced parameter. */
+ ( void ) xRegions;
+ }
#endif
- #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
- {
- memset( ( void * ) &( pxNewTCB->pvThreadLocalStoragePointers[ 0 ] ), 0x00, sizeof( pxNewTCB->pvThreadLocalStoragePointers ) );
- }
- #endif
-
- #if ( configUSE_TASK_NOTIFICATIONS == 1 )
- {
- memset( ( void * ) &( pxNewTCB->ulNotifiedValue[ 0 ] ), 0x00, sizeof( pxNewTCB->ulNotifiedValue ) );
- memset( ( void * ) &( pxNewTCB->ucNotifyState[ 0 ] ), 0x00, sizeof( pxNewTCB->ucNotifyState ) );
- }
- #endif
-
- #if ( configUSE_NEWLIB_REENTRANT == 1 )
- {
- /* Initialise this task's Newlib reent structure.
- * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
- * for additional information. */
- _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
- }
- #endif
-
- #if ( INCLUDE_xTaskAbortDelay == 1 )
- {
- pxNewTCB->ucDelayAborted = pdFALSE;
- }
+ #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )
+ {
+ /* Allocate and initialize memory for the task's TLS Block. */
+ configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock );
+ }
#endif
/* Initialize the TCB stack to look as if the task was already running,
@@ -1008,51 +963,51 @@
* to the start of the task function. Once the stack has been initialised
* the top of stack variable is updated. */
#if ( portUSING_MPU_WRAPPERS == 1 )
+ {
+ /* If the port has capability to detect stack overflow,
+ * pass the stack end address to the stack initialization
+ * function as well. */
+ #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
{
- /* If the port has capability to detect stack overflow,
- * pass the stack end address to the stack initialization
- * function as well. */
- #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
- {
- #if ( portSTACK_GROWTH < 0 )
- {
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
- }
- #else /* portSTACK_GROWTH */
- {
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
- }
- #endif /* portSTACK_GROWTH */
- }
- #else /* portHAS_STACK_OVERFLOW_CHECKING */
- {
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
- }
- #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+ #if ( portSTACK_GROWTH < 0 )
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #endif /* portSTACK_GROWTH */
}
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+ }
#else /* portUSING_MPU_WRAPPERS */
+ {
+ /* If the port has capability to detect stack overflow,
+ * pass the stack end address to the stack initialization
+ * function as well. */
+ #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
{
- /* If the port has capability to detect stack overflow,
- * pass the stack end address to the stack initialization
- * function as well. */
- #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
- {
- #if ( portSTACK_GROWTH < 0 )
- {
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
- }
- #else /* portSTACK_GROWTH */
- {
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
- }
- #endif /* portSTACK_GROWTH */
- }
- #else /* portHAS_STACK_OVERFLOW_CHECKING */
- {
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
- }
- #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+ #if ( portSTACK_GROWTH < 0 )
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+ }
+ #endif /* portSTACK_GROWTH */
}
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+ }
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+ }
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
@@ -1119,10 +1074,10 @@
uxTaskNumber++;
#if ( configUSE_TRACE_FACILITY == 1 )
- {
- /* Add a counter into the TCB for tracing only. */
- pxNewTCB->uxTCBNumber = uxTaskNumber;
- }
+ {
+ /* Add a counter into the TCB for tracing only. */
+ pxNewTCB->uxTCBNumber = uxTaskNumber;
+ }
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
@@ -1391,7 +1346,9 @@
eTaskState eTaskGetState( TaskHandle_t xTask )
{
eTaskState eReturn;
- List_t const * pxStateList, * pxDelayedList, * pxOverflowedDelayedList;
+ List_t const * pxStateList;
+ List_t const * pxDelayedList;
+ List_t const * pxOverflowedDelayedList;
const TCB_t * const pxTCB = xTask;
configASSERT( pxTCB );
@@ -1427,29 +1384,29 @@
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
{
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ {
+ BaseType_t x;
+
+ /* The task does not appear on the event list item of
+ * and of the RTOS objects, but could still be in the
+ * blocked state if it is waiting on its notification
+ * rather than waiting on an object. If not, is
+ * suspended. */
+ eReturn = eSuspended;
+
+ for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
{
- BaseType_t x;
-
- /* The task does not appear on the event list item of
- * and of the RTOS objects, but could still be in the
- * blocked state if it is waiting on its notification
- * rather than waiting on an object. If not, is
- * suspended. */
- eReturn = eSuspended;
-
- for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+ if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
{
- if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
- {
- eReturn = eBlocked;
- break;
- }
+ eReturn = eBlocked;
+ break;
}
}
+ }
#else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
- {
- eReturn = eSuspended;
- }
+ {
+ eReturn = eSuspended;
+ }
#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
}
else
@@ -1575,13 +1532,13 @@
traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
#if ( configUSE_MUTEXES == 1 )
- {
- uxCurrentBasePriority = pxTCB->uxBasePriority;
- }
+ {
+ uxCurrentBasePriority = pxTCB->uxBasePriority;
+ }
#else
- {
- uxCurrentBasePriority = pxTCB->uxPriority;
- }
+ {
+ uxCurrentBasePriority = pxTCB->uxPriority;
+ }
#endif
if( uxCurrentBasePriority != uxNewPriority )
@@ -1631,25 +1588,25 @@
uxPriorityUsedOnEntry = pxTCB->uxPriority;
#if ( configUSE_MUTEXES == 1 )
- {
- /* Only change the priority being used if the task is not
- * currently using an inherited priority. */
- if( pxTCB->uxBasePriority == pxTCB->uxPriority )
- {
- pxTCB->uxPriority = uxNewPriority;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- /* The base priority gets set whatever. */
- pxTCB->uxBasePriority = uxNewPriority;
- }
- #else /* if ( configUSE_MUTEXES == 1 ) */
+ {
+ /* Only change the priority being used if the task is not
+ * currently using an inherited priority. */
+ if( pxTCB->uxBasePriority == pxTCB->uxPriority )
{
pxTCB->uxPriority = uxNewPriority;
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The base priority gets set whatever. */
+ pxTCB->uxBasePriority = uxNewPriority;
+ }
+ #else /* if ( configUSE_MUTEXES == 1 ) */
+ {
+ pxTCB->uxPriority = uxNewPriority;
+ }
#endif /* if ( configUSE_MUTEXES == 1 ) */
/* Only reset the event list item value if the value is not
@@ -1749,19 +1706,19 @@
vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
- {
- BaseType_t x;
+ {
+ BaseType_t x;
- for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+ for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+ {
+ if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
{
- if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
- {
- /* The task was blocked to wait for a notification, but is
- * now suspended, so no notification was received. */
- pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION;
- }
+ /* The task was blocked to wait for a notification, but is
+ * now suspended, so no notification was received. */
+ pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION;
}
}
+ }
#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
}
taskEXIT_CRITICAL();
@@ -2000,54 +1957,54 @@
/* Add the idle task at the lowest priority. */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ StaticTask_t * pxIdleTaskTCBBuffer = NULL;
+ StackType_t * pxIdleTaskStackBuffer = NULL;
+ uint32_t ulIdleTaskStackSize;
+
+ /* The Idle task is created using user provided RAM - obtain the
+ * address of the RAM then create the idle task. */
+ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+ xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
+ configIDLE_TASK_NAME,
+ ulIdleTaskStackSize,
+ ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+ pxIdleTaskStackBuffer,
+ pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+ if( xIdleTaskHandle != NULL )
{
- StaticTask_t * pxIdleTaskTCBBuffer = NULL;
- StackType_t * pxIdleTaskStackBuffer = NULL;
- uint32_t ulIdleTaskStackSize;
-
- /* The Idle task is created using user provided RAM - obtain the
- * address of the RAM then create the idle task. */
- vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
- xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
- configIDLE_TASK_NAME,
- ulIdleTaskStackSize,
- ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
- portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
- pxIdleTaskStackBuffer,
- pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-
- if( xIdleTaskHandle != NULL )
- {
- xReturn = pdPASS;
- }
- else
- {
- xReturn = pdFAIL;
- }
+ xReturn = pdPASS;
}
+ else
+ {
+ xReturn = pdFAIL;
+ }
+ }
#else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
- {
- /* The Idle task is being created using dynamically allocated RAM. */
- xReturn = xTaskCreate( prvIdleTask,
- configIDLE_TASK_NAME,
- configMINIMAL_STACK_SIZE,
- ( void * ) NULL,
- portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
- &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
- }
+ {
+ /* The Idle task is being created using dynamically allocated RAM. */
+ xReturn = xTaskCreate( prvIdleTask,
+ configIDLE_TASK_NAME,
+ configMINIMAL_STACK_SIZE,
+ ( void * ) NULL,
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+ &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
#if ( configUSE_TIMERS == 1 )
+ {
+ if( xReturn == pdPASS )
{
- if( xReturn == pdPASS )
- {
- xReturn = xTimerCreateTimerTask();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ xReturn = xTimerCreateTimerTask();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
@@ -2056,9 +2013,9 @@
* definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
* the only macro called by the function. */
#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
- {
- freertos_tasks_c_additions_init();
- }
+ {
+ freertos_tasks_c_additions_init();
+ }
#endif
/* Interrupts are turned off here, to ensure a tick does not occur
@@ -2068,15 +2025,13 @@
* starts to run. */
portDISABLE_INTERRUPTS();
- #if ( configUSE_NEWLIB_REENTRANT == 1 )
- {
- /* Switch Newlib's _impure_ptr variable to point to the _reent
- * structure specific to the task that will run first.
- * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
- * for additional information. */
- _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
- }
- #endif /* configUSE_NEWLIB_REENTRANT */
+ #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )
+ {
+ /* Switch C-Runtime's TLS Block to point to the TLS
+ * block specific to the task that will run first. */
+ configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+ }
+ #endif
xNextTaskUnblockTime = portMAX_DELAY;
xSchedulerRunning = pdTRUE;
@@ -2094,15 +2049,14 @@
/* Setting up the timer tick is hardware specific and thus in the
* portable interface. */
- if( xPortStartScheduler() != pdFALSE )
- {
- /* Should not reach here as if the scheduler is running the
- * function will not return. */
- }
- else
- {
- /* Should only reach here if a task calls xTaskEndScheduler(). */
- }
+ xPortStartScheduler();
+
+ /* In most cases, xPortStartScheduler() will not return. If it
+ * returns pdTRUE then there was not enough heap memory available
+ * to create either the Idle or the Timer task. If it returned
+ * pdFALSE, then the application called xTaskEndScheduler().
+ * Most ports don't implement xTaskEndScheduler() as there is
+ * nothing to return to. */
}
else
{
@@ -2166,26 +2120,26 @@
* task that are in the Ready state, even though the idle task is
* running. */
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+ {
+ if( uxTopReadyPriority > tskIDLE_PRIORITY )
{
- if( uxTopReadyPriority > tskIDLE_PRIORITY )
- {
- uxHigherPriorityReadyTasks = pdTRUE;
- }
+ uxHigherPriorityReadyTasks = pdTRUE;
}
+ }
#else
- {
- const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+ {
+ const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
- /* When port optimised task selection is used the uxTopReadyPriority
- * variable is used as a bit map. If bits other than the least
- * significant bit are set then there are tasks that have a priority
- * above the idle priority that are in the Ready state. This takes
- * care of the case where the co-operative scheduler is in use. */
- if( uxTopReadyPriority > uxLeastSignificantBit )
- {
- uxHigherPriorityReadyTasks = pdTRUE;
- }
+ /* When port optimised task selection is used the uxTopReadyPriority
+ * variable is used as a bit map. If bits other than the least
+ * significant bit are set then there are tasks that have a priority
+ * above the idle priority that are in the Ready state. This takes
+ * care of the case where the co-operative scheduler is in use. */
+ if( uxTopReadyPriority > uxLeastSignificantBit )
+ {
+ uxHigherPriorityReadyTasks = pdTRUE;
}
+ }
#endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */
if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
@@ -2306,9 +2260,9 @@
if( xYieldPending != pdFALSE )
{
#if ( configUSE_PREEMPTION != 0 )
- {
- xAlreadyYielded = pdTRUE;
- }
+ {
+ xAlreadyYielded = pdTRUE;
+ }
#endif
taskYIELD_IF_USING_PREEMPTION();
}
@@ -2400,7 +2354,9 @@
static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
const char pcNameToQuery[] )
{
- TCB_t * pxNextTCB, * pxFirstTCB, * pxReturn = NULL;
+ TCB_t * pxNextTCB;
+ TCB_t * pxFirstTCB;
+ TCB_t * pxReturn = NULL;
UBaseType_t x;
char cNextChar;
BaseType_t xBreakLoop;
@@ -2501,23 +2457,23 @@
}
#if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ if( pxTCB == NULL )
{
- if( pxTCB == NULL )
- {
- /* Search the suspended list. */
- pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
- }
+ /* Search the suspended list. */
+ pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
}
+ }
#endif
#if ( INCLUDE_vTaskDelete == 1 )
+ {
+ if( pxTCB == NULL )
{
- if( pxTCB == NULL )
- {
- /* Search the deleted list. */
- pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
- }
+ /* Search the deleted list. */
+ pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
}
+ }
#endif
}
( void ) xTaskResumeAll();
@@ -2555,39 +2511,39 @@
uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
#if ( INCLUDE_vTaskDelete == 1 )
- {
- /* Fill in an TaskStatus_t structure with information on
- * each task that has been deleted but not yet cleaned up. */
- uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
- }
+ {
+ /* Fill in an TaskStatus_t structure with information on
+ * each task that has been deleted but not yet cleaned up. */
+ uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+ }
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
- {
- /* Fill in an TaskStatus_t structure with information on
- * each task in the Suspended state. */
- uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
- }
+ {
+ /* Fill in an TaskStatus_t structure with information on
+ * each task in the Suspended state. */
+ uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+ }
#endif
#if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ if( pulTotalRunTime != NULL )
{
- if( pulTotalRunTime != NULL )
- {
- #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
- portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
- #else
- *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
- #endif
- }
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+ #else
+ *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
}
+ }
#else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+ {
+ if( pulTotalRunTime != NULL )
{
- if( pulTotalRunTime != NULL )
- {
- *pulTotalRunTime = 0;
- }
+ *pulTotalRunTime = 0;
}
+ }
#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
}
else
@@ -2622,12 +2578,34 @@
* 1. */
#if ( configUSE_TICKLESS_IDLE != 0 )
- void vTaskStepTick( const TickType_t xTicksToJump )
+ void vTaskStepTick( TickType_t xTicksToJump )
{
/* Correct the tick count value after a period during which the tick
* was suppressed. Note this does *not* call the tick hook function for
* each stepped tick. */
configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+
+ if( ( xTickCount + xTicksToJump ) == xNextTaskUnblockTime )
+ {
+ /* Arrange for xTickCount to reach xNextTaskUnblockTime in
+ * xTaskIncrementTick() when the scheduler resumes. This ensures
+ * that any delayed tasks are resumed at the correct time. */
+ configASSERT( uxSchedulerSuspended );
+ configASSERT( xTicksToJump != ( TickType_t ) 0 );
+
+ /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */
+ taskENTER_CRITICAL();
+ {
+ xPendedTicks++;
+ }
+ taskEXIT_CRITICAL();
+ xTicksToJump--;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
xTickCount += xTicksToJump;
traceINCREASE_TICK_COUNT( xTicksToJump );
}
@@ -2646,7 +2624,13 @@
/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
* the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
vTaskSuspendAll();
- xPendedTicks += xTicksToCatchUp;
+
+ /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */
+ taskENTER_CRITICAL();
+ {
+ xPendedTicks += xTicksToCatchUp;
+ }
+ taskEXIT_CRITICAL();
xYieldOccurred = xTaskResumeAll();
return xYieldOccurred;
@@ -2703,21 +2687,21 @@
/* A task being unblocked cannot cause an immediate context
* switch if preemption is turned off. */
#if ( configUSE_PREEMPTION == 1 )
+ {
+ /* Preemption is on, but a context switch should only be
+ * performed if the unblocked task has a priority that is
+ * higher than the currently executing task. */
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
{
- /* Preemption is on, but a context switch should only be
- * performed if the unblocked task has a priority that is
- * higher than the currently executing task. */
- if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
- {
- /* Pend the yield to be performed when the scheduler
- * is unsuspended. */
- xYieldPending = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* Pend the yield to be performed when the scheduler
+ * is unsuspended. */
+ xYieldPending = pdTRUE;
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_PREEMPTION */
}
else
@@ -2826,20 +2810,24 @@
/* A task being unblocked cannot cause an immediate
* context switch if preemption is turned off. */
#if ( configUSE_PREEMPTION == 1 )
+ {
+ /* Preemption is on, but a context switch should
+ * only be performed if the unblocked task's
+ * priority is higher than the currently executing
+ * task.
+ * The case of equal priority tasks sharing
+ * processing time (which happens when both
+ * preemption and time slicing are on) is
+ * handled below.*/
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
{
- /* Preemption is on, but a context switch should
- * only be performed if the unblocked task has a
- * priority that is equal to or higher than the
- * currently executing task. */
- if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
- {
- xSwitchRequired = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ xSwitchRequired = pdTRUE;
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_PREEMPTION */
}
}
@@ -2849,44 +2837,44 @@
* processing time (time slice) if preemption is on, and the application
* writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+ {
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
{
- if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
- {
- xSwitchRequired = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ xSwitchRequired = pdTRUE;
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
#if ( configUSE_TICK_HOOK == 1 )
+ {
+ /* Guard against the tick hook being called when the pended tick
+ * count is being unwound (when the scheduler is being unlocked). */
+ if( xPendedTicks == ( TickType_t ) 0 )
{
- /* Guard against the tick hook being called when the pended tick
- * count is being unwound (when the scheduler is being unlocked). */
- if( xPendedTicks == ( TickType_t ) 0 )
- {
- vApplicationTickHook();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ vApplicationTickHook();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_TICK_HOOK */
#if ( configUSE_PREEMPTION == 1 )
+ {
+ if( xYieldPending != pdFALSE )
{
- if( xYieldPending != pdFALSE )
- {
- xSwitchRequired = pdTRUE;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ xSwitchRequired = pdTRUE;
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_PREEMPTION */
}
else
@@ -2896,9 +2884,9 @@
/* The tick hook gets called at regular intervals, even if the
* scheduler is locked. */
#if ( configUSE_TICK_HOOK == 1 )
- {
- vApplicationTickHook();
- }
+ {
+ vApplicationTickHook();
+ }
#endif
}
@@ -3032,31 +3020,31 @@
traceTASK_SWITCHED_OUT();
#if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+ #else
+ ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ /* Add the amount of time the task has been running to the
+ * accumulated time so far. The time the task started running was
+ * stored in ulTaskSwitchedInTime. Note that there is no overflow
+ * protection here so count values are only valid until the timer
+ * overflows. The guard against negative values is to protect
+ * against suspect run time stat counter implementations - which
+ * are provided by the application, not the kernel. */
+ if( ulTotalRunTime > ulTaskSwitchedInTime )
{
- #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
- portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
- #else
- ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
- #endif
-
- /* Add the amount of time the task has been running to the
- * accumulated time so far. The time the task started running was
- * stored in ulTaskSwitchedInTime. Note that there is no overflow
- * protection here so count values are only valid until the timer
- * overflows. The guard against negative values is to protect
- * against suspect run time stat counter implementations - which
- * are provided by the application, not the kernel. */
- if( ulTotalRunTime > ulTaskSwitchedInTime )
- {
- pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- ulTaskSwitchedInTime = ulTotalRunTime;
+ pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ ulTaskSwitchedInTime = ulTotalRunTime;
+ }
#endif /* configGENERATE_RUN_TIME_STATS */
/* Check for stack overflow, if configured. */
@@ -3064,9 +3052,9 @@
/* Before the currently running task is switched out, save its errno. */
#if ( configUSE_POSIX_ERRNO == 1 )
- {
- pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
- }
+ {
+ pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+ }
#endif
/* Select a new task to run using either the generic C or port
@@ -3076,20 +3064,18 @@
/* After the new task is switched in, update the global errno. */
#if ( configUSE_POSIX_ERRNO == 1 )
- {
- FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
- }
+ {
+ FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+ }
#endif
- #if ( configUSE_NEWLIB_REENTRANT == 1 )
- {
- /* Switch Newlib's _impure_ptr variable to point to the _reent
- * structure specific to this task.
- * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
- * for additional information. */
- _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
- }
- #endif /* configUSE_NEWLIB_REENTRANT */
+ #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )
+ {
+ /* Switch C-Runtime's TLS Block to point to the TLS
+ * Block specific to this task. */
+ configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+ }
+ #endif
}
}
/*-----------------------------------------------------------*/
@@ -3208,17 +3194,17 @@
prvAddTaskToReadyList( pxUnblockedTCB );
#if ( configUSE_TICKLESS_IDLE != 0 )
- {
- /* If a task is blocked on a kernel object then xNextTaskUnblockTime
- * might be set to the blocked task's time out time. If the task is
- * unblocked for a reason other than a timeout xNextTaskUnblockTime is
- * normally left unchanged, because it is automatically reset to a new
- * value when the tick count equals xNextTaskUnblockTime. However if
- * tickless idling is used it might be more important to enter sleep mode
- * at the earliest possible time - so reset xNextTaskUnblockTime here to
- * ensure it is updated at the earliest possible time. */
- prvResetNextTaskUnblockTime();
- }
+ {
+ /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+ * might be set to the blocked task's time out time. If the task is
+ * unblocked for a reason other than a timeout xNextTaskUnblockTime is
+ * normally left unchanged, because it is automatically reset to a new
+ * value when the tick count equals xNextTaskUnblockTime. However if
+ * tickless idling is used it might be more important to enter sleep mode
+ * at the earliest possible time - so reset xNextTaskUnblockTime here to
+ * ensure it is updated at the earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
#endif
}
else
@@ -3267,17 +3253,17 @@
listREMOVE_ITEM( pxEventListItem );
#if ( configUSE_TICKLESS_IDLE != 0 )
- {
- /* If a task is blocked on a kernel object then xNextTaskUnblockTime
- * might be set to the blocked task's time out time. If the task is
- * unblocked for a reason other than a timeout xNextTaskUnblockTime is
- * normally left unchanged, because it is automatically reset to a new
- * value when the tick count equals xNextTaskUnblockTime. However if
- * tickless idling is used it might be more important to enter sleep mode
- * at the earliest possible time - so reset xNextTaskUnblockTime here to
- * ensure it is updated at the earliest possible time. */
- prvResetNextTaskUnblockTime();
- }
+ {
+ /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+ * might be set to the blocked task's time out time. If the task is
+ * unblocked for a reason other than a timeout xNextTaskUnblockTime is
+ * normally left unchanged, because it is automatically reset to a new
+ * value when the tick count equals xNextTaskUnblockTime. However if
+ * tickless idling is used it might be more important to enter sleep mode
+ * at the earliest possible time - so reset xNextTaskUnblockTime here to
+ * ensure it is updated at the earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
#endif
/* Remove the task from the delayed list and add it to the ready list. The
@@ -3458,48 +3444,48 @@
prvCheckTasksWaitingTermination();
#if ( configUSE_PREEMPTION == 0 )
- {
- /* If we are not using preemption we keep forcing a task switch to
- * see if any other task has become available. If we are using
- * preemption we don't need to do this as any task becoming available
- * will automatically get the processor anyway. */
- taskYIELD();
- }
+ {
+ /* If we are not using preemption we keep forcing a task switch to
+ * see if any other task has become available. If we are using
+ * preemption we don't need to do this as any task becoming available
+ * will automatically get the processor anyway. */
+ taskYIELD();
+ }
#endif /* configUSE_PREEMPTION */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+ {
+ /* When using preemption tasks of equal priority will be
+ * timesliced. If a task that is sharing the idle priority is ready
+ * to run then the idle task should yield before the end of the
+ * timeslice.
+ *
+ * A critical region is not required here as we are just reading from
+ * the list, and an occasional incorrect value will not matter. If
+ * the ready list at the idle priority contains more than one task
+ * then a task other than the idle task is ready to execute. */
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
{
- /* When using preemption tasks of equal priority will be
- * timesliced. If a task that is sharing the idle priority is ready
- * to run then the idle task should yield before the end of the
- * timeslice.
- *
- * A critical region is not required here as we are just reading from
- * the list, and an occasional incorrect value will not matter. If
- * the ready list at the idle priority contains more than one task
- * then a task other than the idle task is ready to execute. */
- if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
- {
- taskYIELD();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ taskYIELD();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
#if ( configUSE_IDLE_HOOK == 1 )
- {
- extern void vApplicationIdleHook( void );
+ {
+ extern void vApplicationIdleHook( void );
- /* Call the user defined function from within the idle task. This
- * allows the application designer to add background functionality
- * without the overhead of a separate task.
- * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
- * CALL A FUNCTION THAT MIGHT BLOCK. */
- vApplicationIdleHook();
- }
+ /* Call the user defined function from within the idle task. This
+ * allows the application designer to add background functionality
+ * without the overhead of a separate task.
+ * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+ * CALL A FUNCTION THAT MIGHT BLOCK. */
+ vApplicationIdleHook();
+ }
#endif /* configUSE_IDLE_HOOK */
/* This conditional compilation should use inequality to 0, not equality
@@ -3507,49 +3493,49 @@
* user defined low power mode implementations require
* configUSE_TICKLESS_IDLE to be set to a value other than 1. */
#if ( configUSE_TICKLESS_IDLE != 0 )
+ {
+ TickType_t xExpectedIdleTime;
+
+ /* It is not desirable to suspend then resume the scheduler on
+ * each iteration of the idle task. Therefore, a preliminary
+ * test of the expected idle time is performed without the
+ * scheduler suspended. The result here is not necessarily
+ * valid. */
+ xExpectedIdleTime = prvGetExpectedIdleTime();
+
+ if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
{
- TickType_t xExpectedIdleTime;
-
- /* It is not desirable to suspend then resume the scheduler on
- * each iteration of the idle task. Therefore, a preliminary
- * test of the expected idle time is performed without the
- * scheduler suspended. The result here is not necessarily
- * valid. */
- xExpectedIdleTime = prvGetExpectedIdleTime();
-
- if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ vTaskSuspendAll();
{
- vTaskSuspendAll();
+ /* Now the scheduler is suspended, the expected idle
+ * time can be sampled again, and this time its value can
+ * be used. */
+ configASSERT( xNextTaskUnblockTime >= xTickCount );
+ xExpectedIdleTime = prvGetExpectedIdleTime();
+
+ /* Define the following macro to set xExpectedIdleTime to 0
+ * if the application does not want
+ * portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+ configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
{
- /* Now the scheduler is suspended, the expected idle
- * time can be sampled again, and this time its value can
- * be used. */
- configASSERT( xNextTaskUnblockTime >= xTickCount );
- xExpectedIdleTime = prvGetExpectedIdleTime();
-
- /* Define the following macro to set xExpectedIdleTime to 0
- * if the application does not want
- * portSUPPRESS_TICKS_AND_SLEEP() to be called. */
- configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
-
- if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
- {
- traceLOW_POWER_IDLE_BEGIN();
- portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
- traceLOW_POWER_IDLE_END();
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ traceLOW_POWER_IDLE_BEGIN();
+ portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+ traceLOW_POWER_IDLE_END();
}
- ( void ) xTaskResumeAll();
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ ( void ) xTaskResumeAll();
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configUSE_TICKLESS_IDLE */
}
}
@@ -3559,8 +3545,11 @@
eSleepModeStatus eTaskConfirmSleepModeStatus( void )
{
- /* The idle task exists in addition to the application tasks. */
- const UBaseType_t uxNonApplicationTasks = 1;
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ /* The idle task exists in addition to the application tasks. */
+ const UBaseType_t uxNonApplicationTasks = 1;
+ #endif /* INCLUDE_vTaskSuspend */
+
eSleepModeStatus eReturn = eStandardSleep;
/* This function must be called from a critical section. */
@@ -3581,20 +3570,20 @@
* because the scheduler is suspended. */
eReturn = eAbortSleep;
}
- else
- {
- /* If all the tasks are in the suspended list (which might mean they
- * have an infinite block time rather than actually being suspended)
- * then it is safe to turn all clocks off and just wait for external
- * interrupts. */
- if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ else if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
{
+ /* If all the tasks are in the suspended list (which might mean they
+ * have an infinite block time rather than actually being suspended)
+ * then it is safe to turn all clocks off and just wait for external
+ * interrupts. */
eReturn = eNoTasksWaitingTimeout;
}
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ #endif /* INCLUDE_vTaskSuspend */
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
}
return eReturn;
@@ -3611,7 +3600,8 @@
{
TCB_t * pxTCB;
- if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+ if( ( xIndex >= 0 ) &&
+ ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
{
pxTCB = prvGetTCBFromHandle( xTaskToSet );
configASSERT( pxTCB != NULL );
@@ -3630,7 +3620,8 @@
void * pvReturn = NULL;
TCB_t * pxTCB;
- if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+ if( ( xIndex >= 0 ) &&
+ ( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
{
pxTCB = prvGetTCBFromHandle( xTaskToQuery );
pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
@@ -3677,15 +3668,15 @@
vListInitialise( &xPendingReadyList );
#if ( INCLUDE_vTaskDelete == 1 )
- {
- vListInitialise( &xTasksWaitingTermination );
- }
+ {
+ vListInitialise( &xTasksWaitingTermination );
+ }
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
- {
- vListInitialise( &xSuspendedTaskList );
- }
+ {
+ vListInitialise( &xSuspendedTaskList );
+ }
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
@@ -3700,25 +3691,25 @@
/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
#if ( INCLUDE_vTaskDelete == 1 )
+ {
+ TCB_t * pxTCB;
+
+ /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+ * being called too often in the idle task. */
+ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
{
- TCB_t * pxTCB;
-
- /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
- * being called too often in the idle task. */
- while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+ taskENTER_CRITICAL();
{
- taskENTER_CRITICAL();
- {
- pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
- ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
- --uxCurrentNumberOfTasks;
- --uxDeletedTasksWaitingCleanUp;
- }
- taskEXIT_CRITICAL();
-
- prvDeleteTCB( pxTCB );
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ --uxCurrentNumberOfTasks;
+ --uxDeletedTasksWaitingCleanUp;
}
+ taskEXIT_CRITICAL();
+
+ prvDeleteTCB( pxTCB );
}
+ }
#endif /* INCLUDE_vTaskDelete */
}
/*-----------------------------------------------------------*/
@@ -3739,26 +3730,30 @@
pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
pxTaskStatus->pxStackBase = pxTCB->pxStack;
+ #if ( ( portSTACK_GROWTH > 0 ) && ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+ pxTaskStatus->pxTopOfStack = pxTCB->pxTopOfStack;
+ pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack;
+ #endif
pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
#if ( configUSE_MUTEXES == 1 )
- {
- pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
- }
+ {
+ pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+ }
#else
- {
- pxTaskStatus->uxBasePriority = 0;
- }
+ {
+ pxTaskStatus->uxBasePriority = 0;
+ }
#endif
#if ( configGENERATE_RUN_TIME_STATS == 1 )
- {
- pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
- }
+ {
+ pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+ }
#else
- {
- pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0;
- }
+ {
+ pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0;
+ }
#endif
/* Obtaining the task state is a little fiddly, so is only done if the
@@ -3775,22 +3770,22 @@
pxTaskStatus->eCurrentState = eState;
#if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ /* If the task is in the suspended list then there is a
+ * chance it is actually just blocked indefinitely - so really
+ * it should be reported as being in the Blocked state. */
+ if( eState == eSuspended )
{
- /* If the task is in the suspended list then there is a
- * chance it is actually just blocked indefinitely - so really
- * it should be reported as being in the Blocked state. */
- if( eState == eSuspended )
+ vTaskSuspendAll();
{
- vTaskSuspendAll();
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
{
- if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
- {
- pxTaskStatus->eCurrentState = eBlocked;
- }
+ pxTaskStatus->eCurrentState = eBlocked;
}
- ( void ) xTaskResumeAll();
}
+ ( void ) xTaskResumeAll();
}
+ }
#endif /* INCLUDE_vTaskSuspend */
}
}
@@ -3804,13 +3799,13 @@
if( xGetFreeStackSpace != pdFALSE )
{
#if ( portSTACK_GROWTH > 0 )
- {
- pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
- }
+ {
+ pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+ }
#else
- {
- pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
- }
+ {
+ pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+ }
#endif
}
else
@@ -3828,7 +3823,8 @@
List_t * pxList,
eTaskState eState )
{
- configLIST_VOLATILE TCB_t * pxNextTCB, * pxFirstTCB;
+ configLIST_VOLATILE TCB_t * pxNextTCB;
+ configLIST_VOLATILE TCB_t * pxFirstTCB;
UBaseType_t uxTask = 0;
if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
@@ -3900,13 +3896,13 @@
pxTCB = prvGetTCBFromHandle( xTask );
#if portSTACK_GROWTH < 0
- {
- pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
- }
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+ }
#else
- {
- pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
- }
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+ }
#endif
uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
@@ -3928,13 +3924,13 @@
pxTCB = prvGetTCBFromHandle( xTask );
#if portSTACK_GROWTH < 0
- {
- pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
- }
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+ }
#else
- {
- pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
- }
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+ }
#endif
uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
@@ -3954,49 +3950,46 @@
* want to allocate and clean RAM statically. */
portCLEAN_UP_TCB( pxTCB );
- /* Free up the memory allocated by the scheduler for the task. It is up
- * to the task to free any memory allocated at the application level.
- * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
- * for additional information. */
- #if ( configUSE_NEWLIB_REENTRANT == 1 )
- {
- _reclaim_reent( &( pxTCB->xNewLib_reent ) );
- }
- #endif /* configUSE_NEWLIB_REENTRANT */
+ #if ( ( configUSE_NEWLIB_REENTRANT == 1 ) || ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) )
+ {
+ /* Free up the memory allocated for the task's TLS Block. */
+ configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
+ }
+ #endif
#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+ {
+ /* The task can only have been allocated dynamically - free both
+ * the stack and TCB. */
+ vPortFreeStack( pxTCB->pxStack );
+ vPortFree( pxTCB );
+ }
+ #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+ {
+ /* The task could have been allocated statically or dynamically, so
+ * check what was statically allocated before trying to free the
+ * memory. */
+ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
{
- /* The task can only have been allocated dynamically - free both
- * the stack and TCB. */
+ /* Both the stack and TCB were allocated dynamically, so both
+ * must be freed. */
vPortFreeStack( pxTCB->pxStack );
vPortFree( pxTCB );
}
- #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+ else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
{
- /* The task could have been allocated statically or dynamically, so
- * check what was statically allocated before trying to free the
- * memory. */
- if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
- {
- /* Both the stack and TCB were allocated dynamically, so both
- * must be freed. */
- vPortFreeStack( pxTCB->pxStack );
- vPortFree( pxTCB );
- }
- else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
- {
- /* Only the stack was statically allocated, so the TCB is the
- * only memory that must be freed. */
- vPortFree( pxTCB );
- }
- else
- {
- /* Neither the stack nor the TCB were allocated dynamically, so
- * nothing needs to be freed. */
- configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
- mtCOVERAGE_TEST_MARKER();
- }
+ /* Only the stack was statically allocated, so the TCB is the
+ * only memory that must be freed. */
+ vPortFree( pxTCB );
}
+ else
+ {
+ /* Neither the stack nor the TCB were allocated dynamically, so
+ * nothing needs to be freed. */
+ configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
@@ -4408,7 +4401,7 @@
#endif /* portCRITICAL_NESTING_IN_TCB */
/*-----------------------------------------------------------*/
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
static char * prvWriteNameToBuffer( char * pcBuffer,
const char * pcTaskName )
@@ -4432,10 +4425,10 @@
return &( pcBuffer[ x ] );
}
-#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+#endif /* ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
/*-----------------------------------------------------------*/
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
void vTaskList( char * pcWriteBuffer )
{
@@ -4538,10 +4531,10 @@
}
}
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
/*----------------------------------------------------------*/
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
void vTaskGetRunTimeStats( char * pcWriteBuffer )
{
@@ -4549,12 +4542,6 @@
UBaseType_t uxArraySize, x;
configRUN_TIME_COUNTER_TYPE ulTotalTime, ulStatsAsPercentage;
- #if ( configUSE_TRACE_FACILITY != 1 )
- {
- #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
- }
- #endif
-
/*
* PLEASE NOTE:
*
@@ -4619,15 +4606,15 @@
if( ulStatsAsPercentage > 0UL )
{
#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
- {
- sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
- }
+ {
+ sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ }
#else
- {
- /* sizeof( int ) == sizeof( long ) so a smaller
- * printf() library can be used. */
- sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
- }
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ * printf() library can be used. */
+ sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+ }
#endif
}
else
@@ -4635,15 +4622,15 @@
/* If the percentage is zero here then the task has
* consumed less than 1% of the total run time. */
#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
- {
- sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
- }
+ {
+ sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
#else
- {
- /* sizeof( int ) == sizeof( long ) so a smaller
- * printf() library can be used. */
- sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
- }
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ * printf() library can be used. */
+ sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+ }
#endif
}
@@ -4665,7 +4652,7 @@
}
}
-#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
/*-----------------------------------------------------------*/
TickType_t uxTaskResetEventItemValue( void )
@@ -4941,19 +4928,19 @@
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
#if ( configUSE_TICKLESS_IDLE != 0 )
- {
- /* If a task is blocked waiting for a notification then
- * xNextTaskUnblockTime might be set to the blocked task's time
- * out time. If the task is unblocked for a reason other than
- * a timeout xNextTaskUnblockTime is normally left unchanged,
- * because it will automatically get reset to a new value when
- * the tick count equals xNextTaskUnblockTime. However if
- * tickless idling is used it might be more important to enter
- * sleep mode at the earliest possible time - so reset
- * xNextTaskUnblockTime here to ensure it is updated at the
- * earliest possible time. */
- prvResetNextTaskUnblockTime();
- }
+ {
+ /* If a task is blocked waiting for a notification then
+ * xNextTaskUnblockTime might be set to the blocked task's time
+ * out time. If the task is unblocked for a reason other than
+ * a timeout xNextTaskUnblockTime is normally left unchanged,
+ * because it will automatically get reset to a new value when
+ * the tick count equals xNextTaskUnblockTime. However if
+ * tickless idling is used it might be more important to enter
+ * sleep mode at the earliest possible time - so reset
+ * xNextTaskUnblockTime here to ensure it is updated at the
+ * earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
#endif
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
@@ -5314,12 +5301,12 @@
const TickType_t xConstTickCount = xTickCount;
#if ( INCLUDE_xTaskAbortDelay == 1 )
- {
- /* About to enter a delayed list, so ensure the ucDelayAborted flag is
- * reset to pdFALSE so it can be detected as having been set to pdTRUE
- * when the task leaves the Blocked state. */
- pxCurrentTCB->ucDelayAborted = pdFALSE;
- }
+ {
+ /* About to enter a delayed list, so ensure the ucDelayAborted flag is
+ * reset to pdFALSE so it can be detected as having been set to pdTRUE
+ * when the task leaves the Blocked state. */
+ pxCurrentTCB->ucDelayAborted = pdFALSE;
+ }
#endif
/* Remove the task from the ready list before adding it to the blocked list
@@ -5336,55 +5323,19 @@
}
#if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
{
- if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
- {
- /* Add the task to the suspended task list instead of a delayed task
- * list to ensure it is not woken by a timing event. It will block
- * indefinitely. */
- listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
- }
- else
- {
- /* Calculate the time at which the task should be woken if the event
- * does not occur. This may overflow but this doesn't matter, the
- * kernel will manage it correctly. */
- xTimeToWake = xConstTickCount + xTicksToWait;
-
- /* The list item will be inserted in wake time order. */
- listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
-
- if( xTimeToWake < xConstTickCount )
- {
- /* Wake time has overflowed. Place this item in the overflow
- * list. */
- vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
- }
- else
- {
- /* The wake time has not overflowed, so the current block list
- * is used. */
- vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-
- /* If the task entering the blocked state was placed at the
- * head of the list of blocked tasks then xNextTaskUnblockTime
- * needs to be updated too. */
- if( xTimeToWake < xNextTaskUnblockTime )
- {
- xNextTaskUnblockTime = xTimeToWake;
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- }
- }
+ /* Add the task to the suspended task list instead of a delayed task
+ * list to ensure it is not woken by a timing event. It will block
+ * indefinitely. */
+ listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
}
- #else /* INCLUDE_vTaskSuspend */
+ else
{
/* Calculate the time at which the task should be woken if the event
- * does not occur. This may overflow but this doesn't matter, the kernel
- * will manage it correctly. */
+ * does not occur. This may overflow but this doesn't matter, the
+ * kernel will manage it correctly. */
xTimeToWake = xConstTickCount + xTicksToWait;
/* The list item will be inserted in wake time order. */
@@ -5392,17 +5343,19 @@
if( xTimeToWake < xConstTickCount )
{
- /* Wake time has overflowed. Place this item in the overflow list. */
+ /* Wake time has overflowed. Place this item in the overflow
+ * list. */
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
}
else
{
- /* The wake time has not overflowed, so the current block list is used. */
+ /* The wake time has not overflowed, so the current block list
+ * is used. */
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
- /* If the task entering the blocked state was placed at the head of the
- * list of blocked tasks then xNextTaskUnblockTime needs to be updated
- * too. */
+ /* If the task entering the blocked state was placed at the
+ * head of the list of blocked tasks then xNextTaskUnblockTime
+ * needs to be updated too. */
if( xTimeToWake < xNextTaskUnblockTime )
{
xNextTaskUnblockTime = xTimeToWake;
@@ -5412,10 +5365,44 @@
mtCOVERAGE_TEST_MARKER();
}
}
-
- /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
- ( void ) xCanBlockIndefinitely;
}
+ }
+ #else /* INCLUDE_vTaskSuspend */
+ {
+ /* Calculate the time at which the task should be woken if the event
+ * does not occur. This may overflow but this doesn't matter, the kernel
+ * will manage it correctly. */
+ xTimeToWake = xConstTickCount + xTicksToWait;
+
+ /* The list item will be inserted in wake time order. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+ if( xTimeToWake < xConstTickCount )
+ {
+ /* Wake time has overflowed. Place this item in the overflow list. */
+ vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ }
+ else
+ {
+ /* The wake time has not overflowed, so the current block list is used. */
+ vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+ /* If the task entering the blocked state was placed at the head of the
+ * list of blocked tasks then xNextTaskUnblockTime needs to be updated
+ * too. */
+ if( xTimeToWake < xNextTaskUnblockTime )
+ {
+ xNextTaskUnblockTime = xTimeToWake;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+ ( void ) xCanBlockIndefinitely;
+ }
#endif /* INCLUDE_vTaskSuspend */
}
diff --git a/Source/timers.c b/Source/timers.c
index 88d834b..800a2b8 100644
--- a/Source/timers.c
+++ b/Source/timers.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS Kernel V10.4.6
+ * FreeRTOS Kernel V10.5.1
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
@@ -224,7 +224,7 @@
*/
static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction,
Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;
@@ -243,34 +243,34 @@
if( xTimerQueue != NULL )
{
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+ StackType_t * pxTimerTaskStackBuffer = NULL;
+ uint32_t ulTimerTaskStackSize;
+
+ vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+ xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+ configTIMER_SERVICE_TASK_NAME,
+ ulTimerTaskStackSize,
+ NULL,
+ ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+ pxTimerTaskStackBuffer,
+ pxTimerTaskTCBBuffer );
+
+ if( xTimerTaskHandle != NULL )
{
- StaticTask_t * pxTimerTaskTCBBuffer = NULL;
- StackType_t * pxTimerTaskStackBuffer = NULL;
- uint32_t ulTimerTaskStackSize;
-
- vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
- xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
- configTIMER_SERVICE_TASK_NAME,
- ulTimerTaskStackSize,
- NULL,
- ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
- pxTimerTaskStackBuffer,
- pxTimerTaskTCBBuffer );
-
- if( xTimerTaskHandle != NULL )
- {
- xReturn = pdPASS;
- }
+ xReturn = pdPASS;
}
+ }
#else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
- {
- xReturn = xTaskCreate( prvTimerTask,
- configTIMER_SERVICE_TASK_NAME,
- configTIMER_TASK_STACK_DEPTH,
- NULL,
- ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
- &xTimerTaskHandle );
- }
+ {
+ xReturn = xTaskCreate( prvTimerTask,
+ configTIMER_SERVICE_TASK_NAME,
+ configTIMER_TASK_STACK_DEPTH,
+ NULL,
+ ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+ &xTimerTaskHandle );
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
}
else
@@ -287,7 +287,7 @@
TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction )
{
@@ -301,7 +301,7 @@
* and has not been started. The auto-reload bit may get set in
* prvInitialiseNewTimer. */
pxNewTimer->ucStatus = 0x00;
- prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+ prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
}
return pxNewTimer;
@@ -314,7 +314,7 @@
TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction,
StaticTimer_t * pxTimerBuffer )
@@ -322,14 +322,14 @@
Timer_t * pxNewTimer;
#if ( configASSERT_DEFINED == 1 )
- {
- /* Sanity check that the size of the structure used to declare a
- * variable of type StaticTimer_t equals the size of the real timer
- * structure. */
- volatile size_t xSize = sizeof( StaticTimer_t );
- configASSERT( xSize == sizeof( Timer_t ) );
- ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
- }
+ {
+ /* Sanity check that the size of the structure used to declare a
+ * variable of type StaticTimer_t equals the size of the real timer
+ * structure. */
+ volatile size_t xSize = sizeof( StaticTimer_t );
+ configASSERT( xSize == sizeof( Timer_t ) );
+ ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ }
#endif /* configASSERT_DEFINED */
/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
@@ -343,7 +343,7 @@
* auto-reload bit may get set in prvInitialiseNewTimer(). */
pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
- prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+ prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
}
return pxNewTimer;
@@ -354,7 +354,7 @@
static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const TickType_t xTimerPeriodInTicks,
- const UBaseType_t uxAutoReload,
+ const BaseType_t xAutoReload,
void * const pvTimerID,
TimerCallbackFunction_t pxCallbackFunction,
Timer_t * pxNewTimer )
@@ -374,7 +374,7 @@
pxNewTimer->pxCallbackFunction = pxCallbackFunction;
vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
- if( uxAutoReload != pdFALSE )
+ if( xAutoReload != pdFALSE )
{
pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
}
@@ -449,14 +449,14 @@
/*-----------------------------------------------------------*/
void vTimerSetReloadMode( TimerHandle_t xTimer,
- const UBaseType_t uxAutoReload )
+ const BaseType_t xAutoReload )
{
Timer_t * pxTimer = xTimer;
configASSERT( xTimer );
taskENTER_CRITICAL();
{
- if( uxAutoReload != pdFALSE )
+ if( xAutoReload != pdFALSE )
{
pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
}
@@ -469,10 +469,10 @@
}
/*-----------------------------------------------------------*/
- UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+ BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer )
{
Timer_t * pxTimer = xTimer;
- UBaseType_t uxReturn;
+ BaseType_t xReturn;
configASSERT( xTimer );
taskENTER_CRITICAL();
@@ -480,17 +480,22 @@
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
{
/* Not an auto-reload timer. */
- uxReturn = ( UBaseType_t ) pdFALSE;
+ xReturn = pdFALSE;
}
else
{
/* Is an auto-reload timer. */
- uxReturn = ( UBaseType_t ) pdTRUE;
+ xReturn = pdTRUE;
}
}
taskEXIT_CRITICAL();
- return uxReturn;
+ return xReturn;
+ }
+
+ UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+ {
+ return ( UBaseType_t ) xTimerGetReloadMode( xTimer );
}
/*-----------------------------------------------------------*/
@@ -569,15 +574,15 @@
( void ) pvParameters;
#if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
- {
- extern void vApplicationDaemonTaskStartupHook( void );
+ {
+ extern void vApplicationDaemonTaskStartupHook( void );
- /* Allow the application writer to execute some code in the context of
- * this task at the point the task starts executing. This is useful if the
- * application includes initialisation code that would benefit from
- * executing after the scheduler has been started. */
- vApplicationDaemonTaskStartupHook();
- }
+ /* Allow the application writer to execute some code in the context of
+ * this task at the point the task starts executing. This is useful if the
+ * application includes initialisation code that would benefit from
+ * executing after the scheduler has been started. */
+ vApplicationDaemonTaskStartupHook();
+ }
#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
for( ; ; )
@@ -762,25 +767,25 @@
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
{
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+ {
+ /* Negative commands are pended function calls rather than timer
+ * commands. */
+ if( xMessage.xMessageID < ( BaseType_t ) 0 )
{
- /* Negative commands are pended function calls rather than timer
- * commands. */
- if( xMessage.xMessageID < ( BaseType_t ) 0 )
- {
- const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+ const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
- /* The timer uses the xCallbackParameters member to request a
- * callback be executed. Check the callback is not NULL. */
- configASSERT( pxCallback );
+ /* The timer uses the xCallbackParameters member to request a
+ * callback be executed. Check the callback is not NULL. */
+ configASSERT( pxCallback );
- /* Call the function. */
- pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ /* Call the function. */
+ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* INCLUDE_xTimerPendFunctionCall */
/* Commands that are positive are timer commands rather than pended
@@ -867,27 +872,27 @@
case tmrCOMMAND_DELETE:
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* The timer has already been removed from the active list,
+ * just free up the memory if the memory was dynamically
+ * allocated. */
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
{
- /* The timer has already been removed from the active list,
- * just free up the memory if the memory was dynamically
- * allocated. */
- if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
- {
- vPortFree( pxTimer );
- }
- else
- {
- pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
- }
+ vPortFree( pxTimer );
}
- #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ else
{
- /* If dynamic allocation is not enabled, the memory
- * could not have been dynamically allocated. So there is
- * no need to free the memory - just mark the timer as
- * "not active". */
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
}
+ }
+ #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ {
+ /* If dynamic allocation is not enabled, the memory
+ * could not have been dynamically allocated. So there is
+ * no need to free the memory - just mark the timer as
+ * "not active". */
+ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
+ }
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
break;
@@ -940,31 +945,31 @@
pxOverflowTimerList = &xActiveTimerList2;
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- /* The timer queue is allocated statically in case
- * configSUPPORT_DYNAMIC_ALLOCATION is 0. */
- PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
- PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+ {
+ /* The timer queue is allocated statically in case
+ * configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+ PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+ PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
- xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
- }
+ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+ }
#else
- {
- xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
- }
+ {
+ xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+ }
#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
#if ( configQUEUE_REGISTRY_SIZE > 0 )
+ {
+ if( xTimerQueue != NULL )
{
- if( xTimerQueue != NULL )
- {
- vQueueAddToRegistry( xTimerQueue, "TmrQ" );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+ vQueueAddToRegistry( xTimerQueue, "TmrQ" );
}
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
#endif /* configQUEUE_REGISTRY_SIZE */
}
else
