Release v1.7.7
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index ed22448..f321b33 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2019 STMicroelectronics.
+ * Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -37,14 +37,16 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
+#endif /* STM32U5 || STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -104,6 +106,16 @@
#if defined(STM32H7)
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
/**
* @}
*/
@@ -131,7 +143,8 @@
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
+ input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -205,6 +218,11 @@
#endif
#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
/**
* @}
*/
@@ -213,10 +231,25 @@
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
/**
* @}
*/
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
+ inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
+ inter STM32 series compatibility */
+#endif
/**
* @}
*/
@@ -246,12 +279,25 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+ defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -316,7 +362,8 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+ defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@@ -393,6 +440,10 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -472,7 +523,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@@ -497,6 +548,9 @@
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
/**
@@ -541,6 +595,106 @@
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
/**
* @}
*/
@@ -608,14 +762,16 @@
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+ STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+ defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@@ -636,6 +792,42 @@
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@@ -816,7 +1008,8 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+ defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -873,9 +1066,19 @@
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
#endif /* STM32U5 */
/**
* @}
@@ -944,7 +1147,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1028,8 +1231,8 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1040,15 +1243,42 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H5)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA */
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 */
/**
* @}
@@ -1215,6 +1445,10 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
+#if defined(STM32U5)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
/**
* @}
*/
@@ -1324,30 +1558,40 @@
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
+ the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
+ MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
+ or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
+ of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
+ transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
+ frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
+ de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
+ activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
+ (or time-stamp) */
#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
+ status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@@ -1518,7 +1762,8 @@
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
- )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+ HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1527,8 +1772,10 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
+ HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+ defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@@ -1562,16 +1809,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
- )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+ defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+ STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1645,10 +1897,111 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
/**
* @}
*/
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32WBA)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA */
+
+/**
+ * @}
+ */
+
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1674,7 +2027,8 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@@ -1931,7 +2285,8 @@
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+ defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@@ -2103,8 +2458,10 @@
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
/**
* @}
*/
@@ -2263,7 +2620,9 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -2272,8 +2631,12 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+ HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+ } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+ HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+ } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -2309,8 +2672,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+ HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -2814,6 +3177,11 @@
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
+#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3278,7 +3646,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3391,8 +3760,8 @@
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
-#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3403,7 +3772,112 @@
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
-#endif
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3420,7 +3894,9 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3473,6 +3949,11 @@
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3484,7 +3965,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3844,3 +4325,5 @@
#endif
#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/Inc/Legacy/stm32f0xx_hal_can_legacy.h b/Inc/Legacy/stm32f0xx_hal_can_legacy.h
index d73d049..427f0ed 100644
--- a/Inc/Legacy/stm32f0xx_hal_can_legacy.h
+++ b/Inc/Legacy/stm32f0xx_hal_can_legacy.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2017 STMicroelectronics.
+ * Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index d0c3b72..ff69bd7 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -51,3 +51,6 @@
#endif
#endif /* __STM32_ASSERT_H */
+
+
+
diff --git a/Inc/stm32f0xx_hal.h b/Inc/stm32f0xx_hal.h
index 7141635..0e38043 100644
--- a/Inc/stm32f0xx_hal.h
+++ b/Inc/stm32f0xx_hal.h
@@ -102,13 +102,13 @@
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
#if defined(STM32F091xC) || defined(STM32F098xx)
-/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
+/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Envelope Selection
* @note Applicable on STM32F09x
* @{
*/
-#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
-#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
-#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation envelope source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation envelope source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation envelope source */
/**
* @}
@@ -580,3 +580,5 @@
#endif
#endif /* __STM32F0xx_HAL_H */
+
+
diff --git a/Inc/stm32f0xx_hal_adc.h b/Inc/stm32f0xx_hal_adc.h
index ad46b66..78c8e3b 100644
--- a/Inc/stm32f0xx_hal_adc.h
+++ b/Inc/stm32f0xx_hal_adc.h
@@ -782,7 +782,7 @@
/**
* @brief Enable ADC overrun mode.
* @param _OVERRUN_MODE_ Overrun mode.
- * @retval Overun bit setting to be programmed into CFGR register
+ * @retval Overrun bit setting to be programmed into CFGR register
*/
/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
@@ -1013,3 +1013,5 @@
#endif /* STM32F0xx_HAL_ADC_H */
+
+
diff --git a/Inc/stm32f0xx_hal_adc_ex.h b/Inc/stm32f0xx_hal_adc_ex.h
index 045a19c..3de0941 100644
--- a/Inc/stm32f0xx_hal_adc_ex.h
+++ b/Inc/stm32f0xx_hal_adc_ex.h
@@ -292,3 +292,5 @@
#endif
#endif /* __STM32F0xx_HAL_ADC_EX_H */
+
+
diff --git a/Inc/stm32f0xx_hal_cec.h b/Inc/stm32f0xx_hal_cec.h
index 4190a27..38323f7 100644
--- a/Inc/stm32f0xx_hal_cec.h
+++ b/Inc/stm32f0xx_hal_cec.h
@@ -48,70 +48,80 @@
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
- It can be one of @ref CEC_Signal_Free_Time
+ It can be one of CEC_Signal_Free_Time
and belongs to the set {0,...,7} where
0x0 is the default configuration
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
- it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
- or CEC_EXTENDED_TOLERANCE */
+ it can be a value of CEC_Tolerance :
+ it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
- uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
+ Error stops the reception.
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
CEC_RX_STOP_ON_BRE: reception is stopped. */
- uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
+ Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
- uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
+ Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
- uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
+ Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
- It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error
+ handling. It can take two values:
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
- a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
- and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if
+ BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
- no error-bit generation in case neither a) nor b) are satisfied. Additionally,
- there is no error-bit generation in case of Short Bit Period Error detection in
- a broadcast message while LSTN bit is set. */
+ no error-bit generation in case neither a) nor b) are satisfied.
+ Additionally, there is no error-bit generation in case of Short Bit
+ Period Error detection in a broadcast message while LSTN bit is set. */
- uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
- CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
+ of message transmission/reception. */
- uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+ uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
+ It can take two values:
- CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
- own address (OAR). Messages addressed to different destination are ignored.
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
+ to its own address (OAR). Messages addressed to different destination
+ are ignored.
Broadcast messages are always received.
- CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
- address (OAR) with positive acknowledge. Messages addressed to different destination
- are received, but without interfering with the CEC bus: no acknowledge sent. */
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
+ own address (OAR) with positive acknowledge. Messages addressed to
+ different destination are received, but without interfering with the
+ CEC bus: no acknowledge sent. */
- uint16_t OwnAddress; /*!< Own addresses configuration
- This parameter can be a value of @ref CEC_OWN_ADDRESS */
+ uint16_t OwnAddress; /*!< Own addresses configuration
+ This parameter can be a value of CEC_OWN_ADDRESS */
- uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
} CEC_InitTypeDef;
/**
* @brief HAL CEC State definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState
+ (see CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -159,37 +169,37 @@
typedef struct
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
- CEC_TypeDef *Instance; /*!< CEC registers base address */
+ CEC_TypeDef *Instance; /*!< CEC registers base address */
- CEC_InitTypeDef Init; /*!< CEC communication parameters */
+ CEC_InitTypeDef Init; /*!< CEC communication parameters */
- const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
- uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
- uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
+ uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+ This parameter can be a value of HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+ This parameter can be a value of HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
- in case error is reported */
+ in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
- *hcec); /*!< CEC Tx Transfer completed callback */
+ *hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
- uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
- void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
+ uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
- void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
- void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
+ void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
+ void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
} CEC_HandleTypeDef;
@@ -202,7 +212,7 @@
{
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
- HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
+ HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
} HAL_CEC_CallbackIDTypeDef;
@@ -212,7 +222,8 @@
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
- uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
+ uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
+ callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
@@ -358,16 +369,16 @@
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
-#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
-#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
-#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
-#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
-#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
-#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
-#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
-#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
-#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
-#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
@@ -421,8 +432,8 @@
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
-#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
@@ -430,7 +441,7 @@
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
-#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
@@ -438,7 +449,7 @@
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
-#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
@@ -622,7 +633,8 @@
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
+ (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
@@ -731,8 +743,9 @@
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
-#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
+ (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
diff --git a/Inc/stm32f0xx_hal_comp.h b/Inc/stm32f0xx_hal_comp.h
index 599e36f..3185757 100644
--- a/Inc/stm32f0xx_hal_comp.h
+++ b/Inc/stm32f0xx_hal_comp.h
@@ -63,7 +63,7 @@
uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
This parameter can be a value of @ref COMP_Hysteresis */
- uint32_t Mode; /*!< Selects the operating comsumption mode of the comparator
+ uint32_t Mode; /*!< Selects the operating consumption mode of the comparator
to adjust the speed/consumption.
This parameter can be a value of @ref COMP_Mode */
@@ -198,7 +198,7 @@
*/
#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< I/O1 (PA1 for COMP1, PA3 for COMP2)
connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC output connected to comparator COMP1 non inverting input */
/**
* @}
*/
@@ -694,3 +694,6 @@
#endif
#endif /* STM32F0xx_HAL_COMP_H */
+
+
+
diff --git a/Inc/stm32f0xx_hal_conf_template.h b/Inc/stm32f0xx_hal_conf_template.h
index 856ed04..0f2e114 100644
--- a/Inc/stm32f0xx_hal_conf_template.h
+++ b/Inc/stm32f0xx_hal_conf_template.h
@@ -319,3 +319,6 @@
#endif
#endif /* __STM32F0xx_HAL_CONF_H */
+
+
+
diff --git a/Inc/stm32f0xx_hal_cortex.h b/Inc/stm32f0xx_hal_cortex.h
index 79bcb28..1a07f94 100644
--- a/Inc/stm32f0xx_hal_cortex.h
+++ b/Inc/stm32f0xx_hal_cortex.h
@@ -9,8 +9,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -126,3 +126,6 @@
#endif
#endif /* __STM32F0xx_HAL_CORTEX_H */
+
+
+
diff --git a/Inc/stm32f0xx_hal_dac.h b/Inc/stm32f0xx_hal_dac.h
index e46e7d8..2cff803 100644
--- a/Inc/stm32f0xx_hal_dac.h
+++ b/Inc/stm32f0xx_hal_dac.h
@@ -423,3 +423,5 @@
#endif /* STM32F0xx_HAL_DAC_H */
+
+
diff --git a/Inc/stm32f0xx_hal_dac_ex.h b/Inc/stm32f0xx_hal_dac_ex.h
index 73f75d6..c7bf91f 100644
--- a/Inc/stm32f0xx_hal_dac_ex.h
+++ b/Inc/stm32f0xx_hal_dac_ex.h
@@ -287,3 +287,4 @@
#endif
#endif /*__STM32F0xx_HAL_DAC_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_def.h b/Inc/stm32f0xx_hal_def.h
index a52e75a..55d2b8a 100644
--- a/Inc/stm32f0xx_hal_def.h
+++ b/Inc/stm32f0xx_hal_def.h
@@ -54,7 +54,9 @@
/* Exported macro ------------------------------------------------------------*/
+#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU
@@ -173,3 +175,5 @@
#endif
#endif /* ___STM32F0xx_HAL_DEF */
+
+
diff --git a/Inc/stm32f0xx_hal_dma.h b/Inc/stm32f0xx_hal_dma.h
index a0b5fbd..5ae68fe 100644
--- a/Inc/stm32f0xx_hal_dma.h
+++ b/Inc/stm32f0xx_hal_dma.h
@@ -9,8 +9,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -21,7 +21,7 @@
#define __STM32F0xx_HAL_DMA_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -33,106 +33,106 @@
/** @addtogroup DMA
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
-/**
- * @brief DMA Configuration Structure definition
+/**
+ * @brief DMA Configuration Structure definition
*/
typedef struct
{
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
+
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
+
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
-
+
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
+ data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
- * @brief HAL DMA State structures definition
+ * @brief HAL DMA State structures definition
*/
typedef enum
{
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
-}HAL_DMA_StateTypeDef;
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
+} HAL_DMA_StateTypeDef;
-/**
- * @brief HAL DMA Error Code structure definition
- */
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
+} HAL_DMA_LevelCompleteTypeDef;
-/**
+/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
-
-}HAL_DMA_CallbackIDTypeDef;
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
-/**
- * @brief DMA handle Structure definition
- */
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
typedef struct __DMA_HandleTypeDef
-{
+{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
- void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
- void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
-
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
-
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
+
+ void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
+
__IO uint32_t ErrorCode; /*!< DMA Error code */
-
+
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
-
+
uint32_t ChannelIndex; /*!< DMA Channel Index */
-} DMA_HandleTypeDef;
+} DMA_HandleTypeDef;
/**
* @}
@@ -146,19 +146,19 @@
/** @defgroup DMA_Error_Code DMA Error Code
* @{
- */
+ */
#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
-#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
- */
+ */
#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
@@ -166,19 +166,19 @@
/**
* @}
*/
-
+
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
- */
+ */
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
/**
* @}
- */
+ */
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
- */
+ */
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
/**
@@ -187,16 +187,16 @@
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
- */
+ */
#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
/**
* @}
- */
+ */
/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @{
+ * @{
*/
#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
@@ -207,7 +207,7 @@
/** @defgroup DMA_mode DMA mode
* @{
- */
+ */
#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
/**
@@ -223,7 +223,7 @@
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
/**
* @}
- */
+ */
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
@@ -238,7 +238,7 @@
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
- */
+ */
#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */
#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */
@@ -277,15 +277,15 @@
/** @defgroup HAL_DMA_remapping HAL DMA remapping
* Elements values convention: 0xYYYYYYYY
* - YYYYYYYY : Position in the SYSCFG register CFGR1
- * @{
+ * @{
*/
-#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
+#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
0: No remap (ADC DMA requests mapped on DMA channel 1
1: Remap (ADC DMA requests mapped on DMA channel 2 */
-#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
+#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
0: No remap (USART1_TX DMA request mapped on DMA channel 2
1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
-#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
+#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
0: No remap (USART1_RX DMA request mapped on DMA channel 3
1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
@@ -296,7 +296,7 @@
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
#if defined (STM32F070xB)
#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
- 0: Disabled, need to remap before use
+ 0: Disabled, need to remap before use
1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
#endif
@@ -371,7 +371,7 @@
/**
* @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
@@ -383,7 +383,7 @@
/**
* @brief Disables the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
@@ -407,7 +407,7 @@
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__ DMA handle
- *
+ *
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
@@ -429,7 +429,7 @@
*/
/* Include DMA HAL Extension module */
-#include "stm32f0xx_hal_dma_ex.h"
+#include "stm32f0xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
@@ -441,7 +441,7 @@
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/**
* @}
*/
@@ -450,13 +450,13 @@
* @{
*/
/* Input and Output operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
@@ -471,18 +471,18 @@
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/** @addtogroup DMA_Private_Macros
* @{
*/
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
@@ -502,7 +502,7 @@
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#if defined(SYSCFG_CFGR1_DMA_RMP)
@@ -537,12 +537,12 @@
((RMP) == DMA_REMAP_TIM17_DMA_CH2))
#endif
-#endif /* SYSCFG_CFGR1_DMA_RMP */
+#endif /* SYSCFG_CFGR1_DMA_RMP */
/**
* @}
- */
+ */
/**
* @}
@@ -557,3 +557,5 @@
#endif
#endif /* __STM32F0xx_HAL_DMA_H */
+
+
diff --git a/Inc/stm32f0xx_hal_dma_ex.h b/Inc/stm32f0xx_hal_dma_ex.h
index 71a7c3c..2bdba29 100644
--- a/Inc/stm32f0xx_hal_dma_ex.h
+++ b/Inc/stm32f0xx_hal_dma_ex.h
@@ -9,8 +9,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -21,7 +21,7 @@
#define __STM32F0xx_HAL_DMA_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -36,230 +36,230 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{
- */
-#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
+ */
+#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remapping on STM32F09x/30xC */
#if !defined(STM32F030xC)
-#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
-#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
+#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remapping on STM32F09x/30xC */
+#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remapping on STM32F09x/30xC */
#endif /* !defined(STM32F030xC) */
/****************** DMA1 remap bit field definition********************/
/* DMA1 - Channel 1 */
-#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
+#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
-#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
#if !defined(STM32F030xC)
-#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
-#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
+#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
#endif /* !defined(STM32F030xC) */
/* DMA1 - Channel 2 */
-#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
-#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
+#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
-#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
#if !defined(STM32F030xC)
-#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
-#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
+#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
#endif /* !defined(STM32F030xC) */
/* DMA1 - Channel 3 */
-#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
+#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
#if !defined(STM32F030xC)
-#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
+#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
#endif /* !defined(STM32F030xC) */
-#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
#endif /* !defined(STM32F030xC) */
#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
-#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
#if !defined(STM32F030xC)
-#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
-#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
+#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
#endif /* !defined(STM32F030xC) */
/* DMA1 - Channel 4 */
-#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
+#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
#endif /* !defined(STM32F030xC) */
-#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
#endif /* !defined(STM32F030xC) */
#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
-#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
-#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
#if !defined(STM32F030xC)
-#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
-#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
+#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
#endif /* !defined(STM32F030xC) */
/* DMA1 - Channel 5 */
-#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
#if !defined(STM32F030xC)
-#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
-#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
+#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
#endif /* !defined(STM32F030xC) */
#if !defined(STM32F030xC)
/* DMA1 - Channel 6 */
-#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
-#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
-#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
+#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
/* DMA1 - Channel 7 */
-#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
-#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
+#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
-#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
-#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
+#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
/****************** DMA2 remap bit field definition********************/
/* DMA2 - Channel 1 */
-#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
-#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
+#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
/* DMA2 - Channel 2 */
-#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
-#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
+#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
/* DMA2 - Channel 3 */
-#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
+#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
-#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
-#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
+#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
/* DMA2 - Channel 4 */
-#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
+#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
-#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
-#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
+#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
/* DMA2 - Channel 5 */
-#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
-#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
-#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
+#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
+#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
#endif /* !defined(STM32F030xC) */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F091xC) || defined(STM32F098xx)
#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
@@ -491,7 +491,7 @@
/**
* @}
- */
+ */
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/* Exported macros -----------------------------------------------------------*/
@@ -506,7 +506,7 @@
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
- */
+ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
@@ -520,7 +520,7 @@
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
- */
+ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
@@ -566,7 +566,7 @@
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 to select the DMA Channel flag.
+ * Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
@@ -580,7 +580,7 @@
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 to select the DMA Channel flag.
+ * Where x can be 1_7 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
@@ -590,7 +590,7 @@
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
- */
+ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
@@ -609,7 +609,7 @@
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
- */
+ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
@@ -670,7 +670,7 @@
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
@@ -686,7 +686,7 @@
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
@@ -698,7 +698,7 @@
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
- */
+ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
@@ -710,7 +710,7 @@
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
- */
+ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
@@ -750,7 +750,7 @@
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_5 to select the DMA Channel flag.
+ * Where x can be 1_5 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
@@ -764,7 +764,7 @@
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_5 to select the DMA Channel flag.
+ * Where x can be 1_5 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
@@ -795,7 +795,7 @@
/**
* @}
- */
+ */
/**
* @}
@@ -806,3 +806,4 @@
#endif
#endif /* __STM32F0xx_HAL_DMA_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_exti.h b/Inc/stm32f0xx_hal_exti.h
index 5fc707f..dcfcb7d 100644
--- a/Inc/stm32f0xx_hal_exti.h
+++ b/Inc/stm32f0xx_hal_exti.h
@@ -370,3 +370,4 @@
#endif
#endif /* STM32F0xx_HAL_EXTI_H */
+
diff --git a/Inc/stm32f0xx_hal_flash.h b/Inc/stm32f0xx_hal_flash.h
index 9523fa0..88d4d91 100644
--- a/Inc/stm32f0xx_hal_flash.h
+++ b/Inc/stm32f0xx_hal_flash.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -347,3 +346,5 @@
#endif
#endif /* __STM32F0xx_HAL_FLASH_H */
+
+
diff --git a/Inc/stm32f0xx_hal_flash_ex.h b/Inc/stm32f0xx_hal_flash_ex.h
index 2afb872..62531f3 100644
--- a/Inc/stm32f0xx_hal_flash_ex.h
+++ b/Inc/stm32f0xx_hal_flash_ex.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -442,3 +441,5 @@
#endif
#endif /* __STM32F0xx_HAL_FLASH_EX_H */
+
+
diff --git a/Inc/stm32f0xx_hal_gpio.h b/Inc/stm32f0xx_hal_gpio.h
index 38d0fb9..09e6a65 100644
--- a/Inc/stm32f0xx_hal_gpio.h
+++ b/Inc/stm32f0xx_hal_gpio.h
@@ -317,3 +317,4 @@
#endif
#endif /* __STM32F0xx_HAL_GPIO_H */
+
diff --git a/Inc/stm32f0xx_hal_gpio_ex.h b/Inc/stm32f0xx_hal_gpio_ex.h
index 33b0ac0..f87eaa6 100644
--- a/Inc/stm32f0xx_hal_gpio_ex.h
+++ b/Inc/stm32f0xx_hal_gpio_ex.h
@@ -501,7 +501,7 @@
#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
-#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */
@@ -515,8 +515,8 @@
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
-#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
-#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
+#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */
#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
@@ -585,7 +585,7 @@
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
-#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
/* AF 2 */
@@ -794,3 +794,4 @@
#endif
#endif /* __STM32F0xx_HAL_GPIO_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_i2c.h b/Inc/stm32f0xx_hal_i2c.h
index 97f8be8..0b869a9 100644
--- a/Inc/stm32f0xx_hal_i2c.h
+++ b/Inc/stm32f0xx_hal_i2c.h
@@ -207,6 +207,7 @@
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@@ -217,6 +218,10 @@
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+ __IO uint32_t Devaddress; /*!< I2C Target device address */
+
+ __IO uint32_t Memaddress; /*!< I2C Target memory address */
+
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
@@ -705,9 +710,9 @@
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
@@ -800,8 +805,8 @@
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
- (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
- (~I2C_CR2_RD_WRN)))
+ (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+ (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
diff --git a/Inc/stm32f0xx_hal_i2s.h b/Inc/stm32f0xx_hal_i2s.h
index 07c5b43..870c733 100644
--- a/Inc/stm32f0xx_hal_i2s.h
+++ b/Inc/stm32f0xx_hal_i2s.h
@@ -173,6 +173,7 @@
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
@@ -379,6 +380,15 @@
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg_udr); \
}while(0U)
+/** @brief Flush the I2S DR Register.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
+ __IO uint32_t tmpreg_dr = 0x00U;\
+ tmpreg_dr = ((__HANDLE__)->Instance->DR);\
+ UNUSED(tmpreg_dr); \
+ }while(0U)
/**
* @}
*/
@@ -541,3 +551,4 @@
#endif
#endif /* STM32F0xx_HAL_I2S_H */
+
diff --git a/Inc/stm32f0xx_hal_irda.h b/Inc/stm32f0xx_hal_irda.h
index 3bd894c..755b2fc 100644
--- a/Inc/stm32f0xx_hal_irda.h
+++ b/Inc/stm32f0xx_hal_irda.h
@@ -826,8 +826,8 @@
*/
/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
/**
* @}
@@ -851,3 +851,4 @@
#endif
#endif /* STM32F0xx_HAL_IRDA_H */
+
diff --git a/Inc/stm32f0xx_hal_irda_ex.h b/Inc/stm32f0xx_hal_irda_ex.h
index 226777a..4e9dfec 100644
--- a/Inc/stm32f0xx_hal_irda_ex.h
+++ b/Inc/stm32f0xx_hal_irda_ex.h
@@ -50,10 +50,12 @@
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
-#elif defined(USART_CR1_M)
+#else
+#if defined(USART_CR1_M)
#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long frame */
-#endif
+#endif /* USART_CR1_M1 */
+#endif /* USART_CR1_M1 && USART_CR1_M0 */
/**
* @}
*/
@@ -79,8 +81,8 @@
#if defined(STM32F031x6) || defined(STM32F038xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -96,15 +98,15 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} while(0)
#elif defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -120,7 +122,7 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -136,8 +138,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -153,12 +155,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -174,7 +176,7 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
@@ -194,8 +196,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -211,12 +213,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -232,12 +234,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -253,7 +255,7 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
@@ -334,33 +336,35 @@
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
-#elif defined(USART_CR1_M)
+#else
+#if defined(USART_CR1_M)
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
-} while(0U)
-#endif
+ } \
+ } \
+ } while(0U)
+#endif /* USART_CR1_M */
+#endif /* USART_CR1_M && USART_CR1_M0 */
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.
@@ -370,10 +374,12 @@
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#elif defined(USART_CR1_M)
+#else
+#if defined(USART_CR1_M)
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#endif
+#endif /* USART_CR1_M */
+#endif /* USART_CR1_M && USART_CR1_M0 */
/**
* @}
*/
@@ -387,10 +393,11 @@
/**
* @}
*/
-#endif /* USART_IRDA_SUPPORT */
+#endif /* USART_IRDA_SUPPORT */
#ifdef __cplusplus
}
#endif
#endif /* STM32F0xx_HAL_IRDA_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_pcd.h b/Inc/stm32f0xx_hal_pcd.h
index 85bed14..4b5ed0a 100644
--- a/Inc/stm32f0xx_hal_pcd.h
+++ b/Inc/stm32f0xx_hal_pcd.h
@@ -101,8 +101,8 @@
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
+ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
@@ -190,18 +190,18 @@
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
+#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
- & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
+ &= (uint16_t)(~(__INTERRUPT__)))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
- &= (uint16_t)(~(__INTERRUPT__)))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
/**
@@ -262,12 +262,10 @@
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
@@ -289,14 +287,10 @@
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
- pPCD_BcdCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
- pPCD_LpmCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -335,23 +329,16 @@
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint16_t ep_mps, uint8_t ep_type);
-
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
@@ -435,14 +422,12 @@
#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\
- (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
+ (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -451,8 +436,9 @@
* @param wType Endpoint Type.
* @retval None
*/
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
- & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
+ (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
@@ -470,7 +456,7 @@
* @param bEpNum, bDir
* @retval None
*/
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
+#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
@@ -742,11 +728,13 @@
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
- + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) \
+ ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
+ ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
- + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) \
+ ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
+ ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/**
@@ -799,7 +787,7 @@
{ \
(wNBlocks)--; \
} \
- *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
+ *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
@@ -809,24 +797,29 @@
{ \
(wNBlocks)++; \
} \
- *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
+ *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
- if ((wCount) == 0U) \
+ \
+ *(pdwReg) &= 0x3FFU; \
+ \
+ if ((wCount) > 62U) \
{ \
- *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
- *(pdwReg) |= USB_CNTRX_BLSIZE; \
- } \
- else if((wCount) <= 62U) \
- { \
- PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
- PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+ if ((wCount) == 0U) \
+ { \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } \
+ else \
+ { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ } \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
diff --git a/Inc/stm32f0xx_hal_pcd_ex.h b/Inc/stm32f0xx_hal_pcd_ex.h
index d7884b1..960befc 100644
--- a/Inc/stm32f0xx_hal_pcd_ex.h
+++ b/Inc/stm32f0xx_hal_pcd_ex.h
@@ -22,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -82,7 +82,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32F0xx_HAL_PCD_EX_H */
diff --git a/Inc/stm32f0xx_hal_rcc.h b/Inc/stm32f0xx_hal_rcc.h
index 5d52aa5..fd3a8d9 100644
--- a/Inc/stm32f0xx_hal_rcc.h
+++ b/Inc/stm32f0xx_hal_rcc.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -102,7 +101,7 @@
#define RCC_CR_PLLRDY_BitNumber 25
/* Flags in the CR2 register */
#define RCC_CR2_HSI14RDY_BitNumber 1
-#define RCC_CR2_HSI48RDY_BitNumber 16
+#define RCC_CR2_HSI48RDY_BitNumber 17
/* Flags in the BDCR register */
#define RCC_BDCR_LSERDY_BitNumber 1
/* Flags in the CSR register */
@@ -1680,3 +1679,5 @@
#endif
#endif /* __STM32F0xx_HAL_RCC_H */
+
+
diff --git a/Inc/stm32f0xx_hal_rcc_ex.h b/Inc/stm32f0xx_hal_rcc_ex.h
index dd347ab..c185717 100644
--- a/Inc/stm32f0xx_hal_rcc_ex.h
+++ b/Inc/stm32f0xx_hal_rcc_ex.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -2080,3 +2079,4 @@
#endif
#endif /* __STM32F0xx_HAL_RCC_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_rtc.h b/Inc/stm32f0xx_hal_rtc.h
index d51a50c..1f438e2 100644
--- a/Inc/stm32f0xx_hal_rtc.h
+++ b/Inc/stm32f0xx_hal_rtc.h
@@ -17,25 +17,27 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_RTC_H
-#define __STM32F0xx_HAL_RTC_H
+#ifndef STM32F0xx_HAL_RTC_H
+#define STM32F0xx_HAL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
+
#include "stm32f0xx_hal_def.h"
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-/** @defgroup RTC RTC
+/** @addtogroup RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
@@ -50,7 +52,6 @@
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-
} HAL_RTCStateTypeDef;
/**
@@ -65,10 +66,10 @@
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
- This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+ This parameter can be a value of @ref RTC_Output_selection_Definitions */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
@@ -83,8 +84,8 @@
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
@@ -95,12 +96,12 @@
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
- uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
- corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ corresponding to Synchronous prescaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
@@ -145,7 +146,7 @@
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
@@ -162,7 +163,7 @@
typedef struct __RTC_HandleTypeDef
#else
typedef struct
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
{
RTC_TypeDef *Instance; /*!< Register base address */
@@ -173,27 +174,27 @@
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
+ void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
- void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
+ void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */
#if defined(RTC_WAKEUP_SUPPORT)
- void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
-
+ void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
#endif /* RTC_WAKEUP_SUPPORT */
- void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
- void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
+ void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
+
+ void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
#if defined(RTC_TAMPER3_SUPPORT)
- void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
-
+ void (* Tamper3EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
#endif /* RTC_TAMPER3_SUPPORT */
- void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
- void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
+ void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+ void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
+
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
} RTC_HandleTypeDef;
@@ -203,18 +204,18 @@
*/
typedef enum
{
- HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
- HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
+ HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
+ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */
#if defined(RTC_WAKEUP_SUPPORT)
- HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC WakeUp Timer Event Callback ID */
+ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */
#endif /* RTC_WAKEUP_SUPPORT */
- HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
- HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
+ HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
+ HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
#if defined(RTC_TAMPER3_SUPPORT)
- HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06u, /*!< RTC Tamper 3 Callback ID */
+ HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
#endif /* RTC_TAMPER3_SUPPORT */
- HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
- HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
+ HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
+ HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
} HAL_RTC_CallbackIDTypeDef;
/**
@@ -222,11 +223,13 @@
*/
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
@@ -235,8 +238,19 @@
* @{
*/
#define RTC_HOURFORMAT_24 0x00000000U
-#define RTC_HOURFORMAT_12 0x00000040U
+#define RTC_HOURFORMAT_12 RTC_CR_FMT
+/**
+ * @}
+ */
+/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE 0x00000000U
+#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
+#if defined(RTC_WAKEUP_SUPPORT)
+#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
+#endif /* RTC_WAKEUP_SUPPORT */
/**
* @}
*/
@@ -245,7 +259,7 @@
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
-#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
+#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
/**
* @}
*/
@@ -254,7 +268,7 @@
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
-#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U
+#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
/**
* @}
*/
@@ -263,7 +277,7 @@
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x01)
/**
* @}
*/
@@ -271,8 +285,8 @@
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
-#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
-#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
+#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
+#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
/**
* @}
@@ -282,24 +296,23 @@
* @{
*/
#define RTC_STOREOPERATION_RESET 0x00000000U
-#define RTC_STOREOPERATION_SET 0x00040000U
+#define RTC_STOREOPERATION_SET RTC_CR_BKP
/**
* @}
*/
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
-#define RTC_FORMAT_BIN 0x000000000U
-#define RTC_FORMAT_BCD 0x000000001U
+#define RTC_FORMAT_BIN 0x00000000U
+#define RTC_FORMAT_BCD 0x00000001U
/**
* @}
*/
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
* @{
*/
-/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
@@ -334,7 +347,7 @@
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
/**
* @}
*/
@@ -347,7 +360,10 @@
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL 0x80808080U
+#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \
+ RTC_ALARMMASK_HOURS | \
+ RTC_ALARMMASK_MINUTES | \
+ RTC_ALARMMASK_SECONDS)
/**
* @}
*/
@@ -356,7 +372,6 @@
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
-
/**
* @}
*/
@@ -364,39 +379,38 @@
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
-#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match
- to activate alarm. */
+/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
+/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
+/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
+/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
+/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
+/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
+/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:0] are compared and must match to activate alarm. */
+#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
/**
* @}
*/
@@ -404,13 +418,11 @@
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
-#define RTC_IT_TS 0x00008000U
-#define RTC_IT_WUT 0x00004000U
-#define RTC_IT_ALRA 0x00001000U
-#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/
-#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/
-#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/
+#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
+#if defined(RTC_WAKEUP_SUPPORT)
+#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
+#endif /* RTC_WAKEUP_SUPPORT */
+#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
/**
* @}
*/
@@ -418,20 +430,26 @@
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
-#define RTC_FLAG_RECALPF 0x00010000U
-#define RTC_FLAG_TAMP3F 0x00008000U
-#define RTC_FLAG_TAMP2F 0x00004000U
-#define RTC_FLAG_TAMP1F 0x00002000U
-#define RTC_FLAG_TSOVF 0x00001000U
-#define RTC_FLAG_TSF 0x00000800U
-#define RTC_FLAG_WUTF 0x00000400U
-#define RTC_FLAG_ALRAF 0x00000100U
-#define RTC_FLAG_INITF 0x00000040U
-#define RTC_FLAG_RSF 0x00000020U
-#define RTC_FLAG_INITS 0x00000010U
-#define RTC_FLAG_SHPF 0x00000008U
-#define RTC_FLAG_WUTWF 0x00000004U
-#define RTC_FLAG_ALRAWF 0x00000001U
+#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Tamper 3 event flag */
+#endif /* RTC_TAMPER3_SUPPORT */
+#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */
+#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */
+#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */
+#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */
+#if defined(RTC_WAKEUP_SUPPORT)
+#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */
+#endif /* RTC_WAKEUP_SUPPORT */
+#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */
+#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */
+#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */
+#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */
+#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */
+#if defined(RTC_WAKEUP_SUPPORT)
+#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */
+#endif /* RTC_WAKEUP_SUPPORT */
+#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */
/**
* @}
*/
@@ -440,21 +458,22 @@
* @}
*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
/** @brief Reset RTC handle state
- * @param __HANDLE__ RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
- (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL;\
- (__HANDLE__)->MspDeInitCallback = NULL;\
- }while(0u)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_RTC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
@@ -464,21 +483,26 @@
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xCAU; \
- (__HANDLE__)->Instance->WPR = 0x53U; \
- } while(0)
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \
+ (__HANDLE__)->Instance->WPR = 0xCAU; \
+ (__HANDLE__)->Instance->WPR = 0x53U; \
+ } while(0U)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xFFU; \
- } while(0)
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \
+ (__HANDLE__)->Instance->WPR = 0xFFU; \
+ } while(0U)
+
+/**
+ * @brief Check whether the RTC Calendar is initialized.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
/**
* @brief Enable the RTC ALARMA peripheral.
@@ -498,7 +522,7 @@
* @brief Enable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
+ * This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
@@ -508,8 +532,8 @@
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
@@ -522,7 +546,28 @@
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF: Alarm A interrupt flag
+ * @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm flag to be cleared.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
@@ -532,103 +577,88 @@
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC Alarm's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to check.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRAWF
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Alarm's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @retval None
- */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @brief Enable interrupt on the RTC Alarm associated EXTI line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable interrupt on the RTC Alarm associated Exti line.
+ * @brief Disable interrupt on the RTC Alarm associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable event on the RTC Alarm associated Exti line.
+ * @brief Enable event on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable event on the RTC Alarm associated Exti line.
+ * @brief Disable event on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Clear the RTC Alarm associated Exti line flag.
+ * @brief Clear the RTC Alarm associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @brief Generate a Software interrupt on RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
@@ -640,14 +670,14 @@
#include "stm32f0xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
+
+/** @addtogroup RTC_Exported_Functions
* @{
*/
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup RTC_Exported_Functions_Group1
* @{
*/
-
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
@@ -663,28 +693,19 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+/** @addtogroup RTC_Exported_Functions_Group2
* @{
*/
-
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-
-
-/* RTC Daylight Saving Time functions *****************************************/
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+/** @addtogroup RTC_Exported_Functions_Group3
* @{
*/
/* RTC Alarm functions ********************************************************/
@@ -699,16 +720,23 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+/** @addtogroup RTC_Exported_Functions_Group4
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
+
+/* RTC Daylight Saving Time functions *****************************************/
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+/** @addtogroup RTC_Exported_Functions_Group5
* @{
*/
/* Peripheral State functions *************************************************/
@@ -724,28 +752,46 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
-#define RTC_TR_RESERVED_MASK 0x007F7F7FU
-#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
+#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \
+ RTC_TR_MNT | RTC_TR_MNU | \
+ RTC_TR_ST | RTC_TR_SU | \
+ RTC_TR_PM))
+#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \
+ RTC_DR_MT | RTC_DR_MU | \
+ RTC_DR_DT | RTC_DR_DU | \
+ RTC_DR_WDU))
+#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT))
#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
-#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
- RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
- RTC_FLAG_WUTF | RTC_FLAG_ALRAF | \
- RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS | \
- RTC_FLAG_SHPF | RTC_FLAG_WUTWF | RTC_FLAG_ALRAWF))
+#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
+#if defined(RTC_WAKEUP_SUPPORT)
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
+ RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \
+ RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \
+ RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
+ RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
+#else /* RTC_WAKEUP_SUPPORT */
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
+ RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \
+ RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
+ RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
+#endif /* RTC_WAKEUP_SUPPORT */
#define RTC_TIMEOUT_VALUE 1000U
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
+
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
@@ -756,14 +802,26 @@
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
+#if defined(RTC_WAKEUP_SUPPORT)
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+#else /* RTC_WAKEUP_SUPPORT */
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA))
+#endif /* RTC_WAKEUP_SUPPORT */
+
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
+
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
+
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
+
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
@@ -773,12 +831,16 @@
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
+
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
+
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -786,7 +848,9 @@
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
+
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -794,27 +858,31 @@
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
-#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U)
+
+#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
/**
* @}
@@ -825,12 +893,14 @@
*/
/* Private functions ---------------------------------------------------------*/
+
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
-uint8_t RTC_ByteToBcd2(uint8_t Value);
-uint8_t RTC_Bcd2ToByte(uint8_t Value);
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t number);
+uint8_t RTC_Bcd2ToByte(uint8_t number);
/**
* @}
*/
@@ -847,4 +917,4 @@
}
#endif
-#endif /* __STM32F0xx_HAL_RTC_H */
+#endif /* STM32F0xx_HAL_RTC_H */
diff --git a/Inc/stm32f0xx_hal_rtc_ex.h b/Inc/stm32f0xx_hal_rtc_ex.h
index 204159a..f6b264a 100644
--- a/Inc/stm32f0xx_hal_rtc_ex.h
+++ b/Inc/stm32f0xx_hal_rtc_ex.h
@@ -17,21 +17,22 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_RTC_EX_H
-#define __STM32F0xx_HAL_RTC_EX_H
+#ifndef STM32F0xx_HAL_RTC_EX_H
+#define STM32F0xx_HAL_RTC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
+
#include "stm32f0xx_hal_def.h"
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-/** @defgroup RTCEx RTCEx
+/** @addtogroup RTCEx
* @{
*/
@@ -47,10 +48,10 @@
typedef struct
{
uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Definitions */
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
@@ -62,7 +63,7 @@
This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
- This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
@@ -72,25 +73,13 @@
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
*/
-/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
- * @{
- */
-#define RTC_OUTPUT_DISABLE 0x00000000U
-#define RTC_OUTPUT_ALARMA 0x00200000U
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-#define RTC_OUTPUT_WAKEUP 0x00600000U
-#endif
-
-/**
- * @}
- */
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
-/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definitions
* @{
*/
#define RTC_BKP_DR0 0x00000000U
@@ -101,191 +90,197 @@
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB) */
+#endif /* RTC_BACKUP_SUPPORT */
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
+/** @defgroup RTCEx_Timestamp_Edges_Definitions RTCEx Timestamp Edges Definitions
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
-#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U
-
+#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
/**
* @}
*/
-/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
+/** @defgroup RTCEx_Timestamp_Pin_Selection RTC Timestamp Pin Selection
* @{
*/
-#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
-
+#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
/**
* @}
*/
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition
+/** @defgroup RTCEx_Tamper_Pin_Definitions RTCEx Tamper Pins Definitions
* @{
*/
#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(RTC_TAMPER3_SUPPORT)
#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E
-#endif
-
+#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
+/** @defgroup RTCEx_Tamper_Pin_Selection RTC tamper Pins Selection
+ * @{
+ */
+#define RTC_TAMPERPIN_DEFAULT 0x00000000U
+/**
+ * @}
+ */
+/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
+ * @{
+ */
+#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /*!< Enable global Tamper Interrupt */
+/**
+ * @}
+ */
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
-
-
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definition
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
* @{
*/
-#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
-#define RTC_TAMPERFILTER_2SAMPLE 0x00000800U /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE 0x00001000U /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE 0x00001800U /*!< Tamper is activated after 8
- consecutive samples at the active level. */
-
+#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_MASK RTC_TAFCR_TAMPFLT /*!< Masking all bits except those of
+ field TAMPFLT */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
* @{
*/
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 0x00000100U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 0x00000200U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 0x00000300U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 0x00000400U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 0x00000500U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 0x00000600U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 0x00000700U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAFCR_TAMPFREQ /*!< Masking all bits except those of
+ field TAMPFREQ */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definition
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
* @{
*/
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAFCR_TAMPPRCH /*!< Masking all bits except those of
+ field TAMPPRCH */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definition
+/** @defgroup RTCEx_Tamper_Pull_Up_Definitions RTCEx Tamper Pull Up Definitions
* @{
*/
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
-
+#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_DISABLE RTC_TAFCR_TAMPPUDIS /*!< Tamper pins are not pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_MASK RTC_TAFCR_TAMPPUDIS /*!< Masking all bits except bit TAMPPUDIS */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions
* @{
*/
-#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */
-
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAFCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAFCR_TAMPTS /*!< Masking all bits except bit TAMPTS */
/**
* @}
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definition
+#if defined(RTC_WAKEUP_SUPPORT)
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U
-
-
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
/**
* @}
*/
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+#endif /* RTC_WAKEUP_SUPPORT */
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definition
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC 0x00002000U /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC 0x00004000U /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
-
+#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 32s, otherwise 2^20 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 16s, otherwise 2^19 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 8s, otherwise 2^18 RTCCLK pulses */
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definition
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth Calib Plus Pulses Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET 0x00008000U /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0]
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0] */
-
-/**
- * @}
- */
-/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
- * @{
- */
-#define RTC_CALIBOUTPUT_512HZ 0x00000000U
-#define RTC_CALIBOUTPUT_1HZ 0x00080000U
-
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
/**
* @}
*/
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definition
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions
* @{
*/
#define RTC_SHIFTADD1S_RESET 0x00000000U
-#define RTC_SHIFTADD1S_SET 0x80000000U
+#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
+/**
+ * @}
+ */
+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ 0x00000000U
+#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
/**
* @}
*/
@@ -295,15 +290,18 @@
*/
/* Exported macros -----------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
* @{
*/
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+#if defined(RTC_WAKEUP_SUPPORT)
+/* ---------------------------------WAKEUPTIMER-------------------------------*/
+
+/** @defgroup RTCEx_WakeUp_Timer RTCEx WakeUp Timer
* @{
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+
/**
* @brief Enable the RTC WakeUp Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
@@ -312,180 +310,187 @@
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
- * @brief Disable the RTC WakeUp Timer peripheral.
+ * @brief Disable the RTC Wakeup Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
/**
- * @brief Enable the RTC WakeUpTimer interrupt.
+ * @brief Enable the RTC Wakeup Timer interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC WakeUpTimer interrupt.
+ * @brief Disable the RTC Wakeup Timer interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @brief Check whether the specified RTC Wakeup Timer interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt to check.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
- * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @brief Check whether the specified RTC Wakeup timer interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+ * @param __INTERRUPT__ specifies the RTC Wakeup timer interrupt sources to check.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @brief Get the selected RTC Wakeup Timer's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
+ * @param __FLAG__ specifies the RTC Wakeup Timer flag to check.
* This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
+ * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt flag
+ * @arg RTC_FLAG_WUTWF: Wakeup Timer 'write allowed' flag
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
- * @brief Clear the RTC Wake Up timer's pending flags.
+ * @brief Clear the RTC Wakeup timer's pending flags.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
+ * @param __FLAG__ specifies the RTC Wakeup Timer Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt Flag
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-/* WAKE-UP TIMER EXTI */
-/* ------------------ */
/**
- * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable event on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable event on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable event on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable event on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Wakeup Timer associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Clear the RTC WakeUp Timer associated Exti line flag.
+ * @brief Clear the RTC Wakeup Timer associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
+ * @brief Generate a Software interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
/**
* @}
*/
+#endif /* RTC_WAKEUP_SUPPORT */
/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Timestamp
+
+/** @defgroup RTCEx_Timestamp RTCEx Timestamp
* @{
*/
+
/**
- * @brief Enable the RTC TimeStamp peripheral.
+ * @brief Enable the RTC Timestamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
/**
- * @brief Disable the RTC TimeStamp peripheral.
+ * @brief Disable the RTC Timestamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
- * @brief Enable the RTC TimeStamp interrupt.
+ * @brief Enable the RTC Timestamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -493,9 +498,9 @@
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC TimeStamp interrupt.
+ * @brief Disable the RTC Timestamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -503,42 +508,43 @@
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @brief Check whether the specified RTC Timestamp interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
- * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @brief Check whether the specified RTC Timestamp interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC TimeStamp's flag status.
+ * @brief Get the selected RTC Timestamp's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
+ * @param __FLAG__ specifies the RTC Timestamp flag to check.
* This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
+ * @arg RTC_FLAG_TSF: Timestamp interrupt flag
+ * @arg RTC_FLAG_TSOVF: Timestamp overflow flag
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
- * @brief Clear the RTC Time Stamp's pending flags.
+ * @brief Clear the RTC Timestamp's pending flags.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
+ * @param __FLAG__ specifies the RTC Timestamp flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF: Timestamp interrupt flag
+ * @arg RTC_FLAG_TSOVF: Timestamp overflow flag
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -548,7 +554,8 @@
*/
/* ---------------------------------TAMPER------------------------------------*/
-/** @defgroup RTCEx_Tamper RTC Tamper
+
+/** @defgroup RTCEx_Tamper RTCEx Tamper
* @{
*/
@@ -580,7 +587,7 @@
*/
#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+#if defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Enable the RTC Tamper3 input detection.
* @param __HANDLE__ specifies the RTC handle.
@@ -594,14 +601,14 @@
* @retval None
*/
#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
+#endif /* RTC_TAMPER3_SUPPORT */
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
/**
* @brief Enable the RTC Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
* This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: Tamper interrupt
+ * @arg RTC_IT_TAMP: Tamper global interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
@@ -611,100 +618,59 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: Tamper interrupt
+ * @arg RTC_IT_TAMP: Tamper global interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @arg RTC_IT_TAMP1: Tamper 1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper 2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper 3 interrupt
+ * @note RTC_IT_TAMP3 is not applicable to all devices.
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-#else
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be:
- * @arg RTC_IT_TAMP: Tamper interrupt
+ * @arg RTC_IT_TAMP: Tamper global interrupt
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Get the selected RTC Tamper's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
+ * @param __FLAG__ specifies the RTC Tamper flag to be checked.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @arg RTC_FLAG_TAMP3F
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag
+ * @note RTC_FLAG_TAMP3F is not applicable to all devices.
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
* @brief Clear the RTC Tamper's pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @arg RTC_FLAG_TAMP3F
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag
+ * @note RTC_FLAG_TAMP3F is not applicable to all devices.
* @retval None
*/
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-#else
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-
-/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @}
*/
@@ -714,83 +680,87 @@
* @{
*/
-/* TAMPER TIMESTAMP EXTI */
-/* --------------------- */
/**
- * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated EXTI line.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Tamper and Timestamp associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @brief Clear the RTC Tamper and Timestamp associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated EXTI line
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
@@ -798,8 +768,9 @@
* @}
*/
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Calibration
+/* ------------------------------CALIBRATION----------------------------------*/
+
+/** @defgroup RTCEx_Calibration RTCEx Calibration
* @{
*/
@@ -836,10 +807,10 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
* This parameter can be:
- * @arg RTC_FLAG_SHPF
+ * @arg RTC_FLAG_SHPF: Shift pending flag
* @retval None
*/
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
* @}
*/
@@ -849,17 +820,17 @@
*/
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @{
+ */
+/* RTC Timestamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
@@ -870,47 +841,45 @@
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+#if defined(RTC_TAMPER3_SUPPORT)
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+#if defined(RTC_TAMPER3_SUPPORT)
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/* RTC Wake-up functions ******************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
- * @{
- */
-
+#if defined(RTC_WAKEUP_SUPPORT)
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @{
+ */
+/* RTC Wakeup functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif
/**
* @}
*/
+#endif /* RTC_WAKEUP_SUPPORT */
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @{
+ */
/* Extended Control functions ************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @{
- */
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
+#if defined(RTC_BACKUP_SUPPORT)
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB) */
+#endif /* RTC_BACKUP_SUPPORT */
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
@@ -924,8 +893,6 @@
* @}
*/
-/* Extended RTC features functions *******************************************/
-
/**
* @}
*/
@@ -933,16 +900,41 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19 /*!< External interrupt line 19 Connected to the RTC Tamper and Timestamp event */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+/* Masks Definition */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \
+ RTC_TAMPER_2 | \
+ RTC_TAMPER_3))
+
+#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \
+ RTC_FLAG_TAMP2F | \
+ RTC_FLAG_TAMP3F))
+#else /* RTC_TAMPER3_SUPPORT */
+#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \
+ RTC_TAMPER_2))
+
+#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \
+ RTC_FLAG_TAMP2F))
+#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
+
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
* @{
*/
@@ -950,38 +942,35 @@
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
* @{
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-#else
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA))
-#endif
-
-#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
-#else
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~RTC_TAMPER_ENABLE_BITS_MASK)) == 0x00U) && ((TAMPER) != 0U))
-#endif
+#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT)
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+
+#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER) \
+ ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) \
+ && ( ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) \
+ || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \
+ || ( ((FILTER) == RTC_TAMPERFILTER_DISABLE) \
+ && ( ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) \
+ || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))))
+
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
@@ -990,14 +979,18 @@
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
@@ -1005,20 +998,22 @@
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
-
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
((SEL) == RTC_SHIFTADD1S_SET))
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
+
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
+
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
@@ -1041,4 +1036,4 @@
}
#endif
-#endif /* __STM32F0xx_HAL_RTC_EX_H */
+#endif /* STM32F0xx_HAL_RTC_EX_H */
diff --git a/Inc/stm32f0xx_hal_smartcard.h b/Inc/stm32f0xx_hal_smartcard.h
index c72a472..466abbb 100644
--- a/Inc/stm32f0xx_hal_smartcard.h
+++ b/Inc/stm32f0xx_hal_smartcard.h
@@ -23,7 +23,8 @@
#ifdef __cplusplus
extern "C" {
#endif
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) \
+ && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -1029,8 +1030,8 @@
* @{
*/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
@@ -1047,9 +1048,10 @@
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* !STM32F030x6 && !STM32F030x8 && !STM32F070x6 && !STM32F070xB && !STM32F030xC */
#ifdef __cplusplus
}
#endif
#endif /* STM32F0xx_HAL_SMARTCARD_H */
+
diff --git a/Inc/stm32f0xx_hal_smartcard_ex.h b/Inc/stm32f0xx_hal_smartcard_ex.h
index 57fe9e7..531e018 100644
--- a/Inc/stm32f0xx_hal_smartcard_ex.h
+++ b/Inc/stm32f0xx_hal_smartcard_ex.h
@@ -23,7 +23,8 @@
#ifdef __cplusplus
extern "C" {
#endif
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) \
+ && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -160,300 +161,302 @@
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} while(0)
-#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) \
+ || defined (STM32F051x8) || defined (STM32F058xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
#elif defined (STM32F070xB)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
#elif defined(STM32F091xC) || defined (STM32F098xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART5) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART7) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART8) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
#elif defined(STM32F030xC)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART5) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
+
/** @brief Set the Transmission Completion flag
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
@@ -557,9 +560,10 @@
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* !STM32F030x6 && !STM32F030x8 && !STM32F070x6 && !STM32F070xB && !STM32F030xC */
#ifdef __cplusplus
}
#endif
#endif /* STM32F0xx_HAL_SMARTCARD_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_smbus.h b/Inc/stm32f0xx_hal_smbus.h
index 9091b74..ee43be4 100644
--- a/Inc/stm32f0xx_hal_smbus.h
+++ b/Inc/stm32f0xx_hal_smbus.h
@@ -749,8 +749,8 @@
*/
/* Peripheral State and Errors functions **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
/**
* @}
diff --git a/Inc/stm32f0xx_hal_spi.h b/Inc/stm32f0xx_hal_spi.h
index f17bb45..a1ba5a8 100644
--- a/Inc/stm32f0xx_hal_spi.h
+++ b/Inc/stm32f0xx_hal_spi.h
@@ -777,7 +777,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
@@ -847,3 +848,4 @@
#endif
#endif /* STM32F0xx_HAL_SPI_H */
+
diff --git a/Inc/stm32f0xx_hal_spi_ex.h b/Inc/stm32f0xx_hal_spi_ex.h
index 23caed2..6f815a6 100644
--- a/Inc/stm32f0xx_hal_spi_ex.h
+++ b/Inc/stm32f0xx_hal_spi_ex.h
@@ -70,3 +70,4 @@
#endif
#endif /* STM32F0xx_HAL_SPI_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_tim.h b/Inc/stm32f0xx_hal_tim.h
index 1bde3c8..9996d1f 100644
--- a/Inc/stm32f0xx_hal_tim.h
+++ b/Inc/stm32f0xx_hal_tim.h
@@ -706,6 +706,15 @@
* @}
*/
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+ * @{
+ */
+#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
@@ -740,16 +749,16 @@
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
/**
* @}
*/
@@ -1527,6 +1536,17 @@
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
+/** @brief Select the Capture/compare DMA request source.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __CCDMA__ specifies Capture/compare DMA request source
+ * This parameter can be one of the following values:
+ * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+ * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+ * @retval None
+ */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
+ MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
/**
* @}
*/
@@ -1636,20 +1656,23 @@
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
+ ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3))
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
@@ -1725,13 +1748,13 @@
((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
@@ -1976,7 +1999,7 @@
* @{
*/
/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
diff --git a/Inc/stm32f0xx_hal_tim_ex.h b/Inc/stm32f0xx_hal_tim_ex.h
index 46c50b7..909a68e 100644
--- a/Inc/stm32f0xx_hal_tim_ex.h
+++ b/Inc/stm32f0xx_hal_tim_ex.h
@@ -241,7 +241,7 @@
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
diff --git a/Inc/stm32f0xx_hal_tsc.h b/Inc/stm32f0xx_hal_tsc.h
index 3e405ba..d2cc752 100644
--- a/Inc/stm32f0xx_hal_tsc.h
+++ b/Inc/stm32f0xx_hal_tsc.h
@@ -187,22 +187,38 @@
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{
*/
-#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
-#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
-#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
-#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
-#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
-#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
-#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
-#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
-#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
-#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
-#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
-#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
-#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
-#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
-#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
-#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
+#define TSC_CTPH_1CYCLE 0x00000000UL
+/*!< Charge transfer pulse high during 1 cycle (PGCLK) */
+#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0
+/*!< Charge transfer pulse high during 2 cycles (PGCLK) */
+#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1
+/*!< Charge transfer pulse high during 3 cycles (PGCLK) */
+#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 4 cycles (PGCLK) */
+#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2
+/*!< Charge transfer pulse high during 5 cycles (PGCLK) */
+#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 6 cycles (PGCLK) */
+#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 7 cycles (PGCLK) */
+#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 8 cycles (PGCLK) */
+#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3
+/*!< Charge transfer pulse high during 9 cycles (PGCLK) */
+#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 10 cycles (PGCLK) */
+#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 11 cycles (PGCLK) */
+#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 12 cycles (PGCLK) */
+#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)
+/*!< Charge transfer pulse high during 13 cycles (PGCLK) */
+#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 14 cycles (PGCLK) */
+#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 15 cycles (PGCLK) */
+#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 16 cycles (PGCLK) */
/**
* @}
*/
@@ -210,22 +226,38 @@
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{
*/
-#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
-#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
-#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
-#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
-#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
-#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
-#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
-#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
-#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
-#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
-#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
-#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
-#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
-#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
-#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
-#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
+#define TSC_CTPL_1CYCLE 0x00000000UL
+/*!< Charge transfer pulse low during 1 cycle (PGCLK) */
+#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0
+/*!< Charge transfer pulse low during 2 cycles (PGCLK) */
+#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1
+/*!< Charge transfer pulse low during 3 cycles (PGCLK) */
+#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 4 cycles (PGCLK) */
+#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2
+/*!< Charge transfer pulse low during 5 cycles (PGCLK) */
+#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 6 cycles (PGCLK) */
+#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 7 cycles (PGCLK) */
+#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 8 cycles (PGCLK) */
+#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3
+/*!< Charge transfer pulse low during 9 cycles (PGCLK) */
+#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 10 cycles (PGCLK) */
+#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 11 cycles (PGCLK) */
+#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 12 cycles (PGCLK) */
+#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
+/*!< Charge transfer pulse low during 13 cycles (PGCLK) */
+#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 14 cycles (PGCLK) */
+#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 15 cycles (PGCLK) */
+#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 16 cycles (PGCLK) */
/**
* @}
*/
@@ -289,8 +321,11 @@
/** @defgroup TSC_Acquisition_Mode Acquisition Mode
* @{
*/
-#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
-#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
+#define TSC_ACQ_MODE_NORMAL 0x00000000UL
+/*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
+#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM
+/*!< Synchronized acquisition mode (acquisition starts if START bit is set and
+when the selected signal is detected on the SYNC input pin) */
/**
* @}
*/
@@ -383,10 +418,10 @@
* @retval None
*/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
@@ -656,7 +691,7 @@
((__VALUE__) == TSC_MCV_2047) || \
((__VALUE__) == TSC_MCV_4095) || \
((__VALUE__) == TSC_MCV_8191) || \
- ((__VALUE__) == TSC_MCV_16383))
+ ((__VALUE__) == TSC_MCV_16383))
#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
@@ -741,8 +776,8 @@
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
/**
* @}
*/
@@ -751,7 +786,7 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config);
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
/**
* @}
@@ -767,8 +802,8 @@
*/
/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* TSC IRQHandler and Callbacks used in Interrupt mode */
void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
diff --git a/Inc/stm32f0xx_hal_uart.h b/Inc/stm32f0xx_hal_uart.h
index 44b1f73..deedb8a 100644
--- a/Inc/stm32f0xx_hal_uart.h
+++ b/Inc/stm32f0xx_hal_uart.h
@@ -185,7 +185,7 @@
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
- * It is expected to admit following values :
+ * This parameter can be a value of @ref UART_Reception_Type_Values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
@@ -194,6 +194,17 @@
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
+ * @brief HAL UART Rx Event type definition
+ * @note HAL UART Rx Event type value aims to identify which type of Event has occurred
+ * leading to call of the RxEvent callback.
+ * This parameter can be a value of @ref UART_RxEvent_Type_Values :
+ * HAL_UART_RXEVENT_TC = 0x00U,
+ * HAL_UART_RXEVENT_HT = 0x01U,
+ * HAL_UART_RXEVENT_IDLE = 0x02U,
+ */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -204,7 +215,7 @@
UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
@@ -220,6 +231,8 @@
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+ __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -781,7 +794,7 @@
* @}
*/
-/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+/** @defgroup UART_Reception_Type_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
@@ -792,6 +805,16 @@
* @}
*/
+/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
+ * @{
+ */
+#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
+#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -1542,11 +1565,11 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
@@ -1646,3 +1669,4 @@
#endif
#endif /* STM32F0xx_HAL_UART_H */
+
diff --git a/Inc/stm32f0xx_hal_uart_ex.h b/Inc/stm32f0xx_hal_uart_ex.h
index 3ef2acf..29ef4f1 100644
--- a/Inc/stm32f0xx_hal_uart_ex.h
+++ b/Inc/stm32f0xx_hal_uart_ex.h
@@ -136,7 +136,7 @@
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
-#endif/* USART_CR1_UESM */
+#endif /* USART_CR1_UESM */
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
@@ -145,6 +145,8 @@
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+
/**
* @}
@@ -168,8 +170,8 @@
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -185,15 +187,16 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
- } while(0)
-#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ } \
+ } while(0)
+#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) \
+ || defined (STM32F051x8) || defined (STM32F058xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -209,7 +212,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -219,14 +222,14 @@
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
#elif defined(STM32F070xB)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -242,7 +245,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -260,14 +263,14 @@
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -283,12 +286,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -304,7 +307,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
@@ -318,14 +321,14 @@
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
#elif defined(STM32F091xC) || defined (STM32F098xx)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -341,12 +344,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -362,12 +365,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -383,7 +386,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
@@ -411,12 +414,12 @@
} \
} while(0)
#elif defined(STM32F030xC)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -432,7 +435,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -459,7 +462,7 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
-
+
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
/** @brief Report the UART mask to apply to retrieve the received data
@@ -587,3 +590,4 @@
#endif
#endif /* STM32F0xx_HAL_UART_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_usart.h b/Inc/stm32f0xx_hal_usart.h
index f09617a..991108f 100644
--- a/Inc/stm32f0xx_hal_usart.h
+++ b/Inc/stm32f0xx_hal_usart.h
@@ -729,7 +729,8 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
@@ -766,8 +767,8 @@
*/
/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
/**
* @}
@@ -790,3 +791,4 @@
#endif
#endif /* STM32F0xx_HAL_USART_H */
+
diff --git a/Inc/stm32f0xx_hal_usart_ex.h b/Inc/stm32f0xx_hal_usart_ex.h
index 49ef0c1..78cd09e 100644
--- a/Inc/stm32f0xx_hal_usart_ex.h
+++ b/Inc/stm32f0xx_hal_usart_ex.h
@@ -51,7 +51,7 @@
#elif defined(USART_CR1_M)
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M) /*!< 9-bit long USART frame */
-#endif
+#endif /* USART_CR1_M0 && USART_CR1_M */
/**
* @}
*/
@@ -80,8 +80,8 @@
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -97,15 +97,16 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} while(0)
-#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
+#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) \
+ || defined (STM32F051x8) || defined (STM32F058xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -121,7 +122,7 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -137,8 +138,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -154,7 +155,7 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -178,8 +179,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -195,12 +196,12 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -216,7 +217,7 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
@@ -236,8 +237,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -253,12 +254,12 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -274,12 +275,12 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -295,7 +296,7 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
@@ -327,8 +328,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
@@ -344,7 +345,7 @@
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -452,7 +453,7 @@
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
-#endif
+#endif /* USART_CR1_M0 && USART_CR1_M */
/**
* @brief Ensure that USART frame length is valid.
@@ -466,7 +467,7 @@
#elif defined(USART_CR1_M)
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
-#endif
+#endif /* USART_CR1_M0 && USART_CR1_M */
/**
@@ -515,3 +516,4 @@
#endif
#endif /* STM32F0xx_HAL_USART_EX_H */
+
diff --git a/Inc/stm32f0xx_hal_wwdg.h b/Inc/stm32f0xx_hal_wwdg.h
index 59d60e9..7abc5d7 100644
--- a/Inc/stm32f0xx_hal_wwdg.h
+++ b/Inc/stm32f0xx_hal_wwdg.h
@@ -183,7 +183,7 @@
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
+ * @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
diff --git a/Inc/stm32f0xx_ll_adc.h b/Inc/stm32f0xx_ll_adc.h
index f3eaba1..55b0b95 100644
--- a/Inc/stm32f0xx_ll_adc.h
+++ b/Inc/stm32f0xx_ll_adc.h
@@ -228,7 +228,7 @@
{
uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
- @note On this STM32 serie, this parameter has some clock ratio constraints:
+ @note On this STM32 series, this parameter has some clock ratio constraints:
ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
(APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
@@ -276,7 +276,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
@@ -365,7 +365,7 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
#if defined(ADC_CCR_VBATEN)
@@ -380,7 +380,7 @@
*/
#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
-#define LL_ADC_CLOCK_ASYNC (0x00000000U) /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */
+#define LL_ADC_CLOCK_ASYNC (0x00000000U) /*!< ADC asynchronous clock. On this STM32 series, asynchronous clock has no prescaler. */
/**
* @}
*/
@@ -400,7 +400,7 @@
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -605,7 +605,7 @@
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
+/* STM32 series: */
/* - ADC calibration time: maximum delay is 83/fADC. */
/* (refer to device datasheet, parameter "tCAL") */
/* - ADC enable time: maximum delay is 1 conversion cycle. */
@@ -631,7 +631,7 @@
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles */
/* are required between ADC end of calibration and ADC enable. */
/* Wait time can be computed in user application by waiting for the */
/* equivalent number of CPU cycles, by taking into account */
@@ -1217,7 +1217,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -1267,7 +1267,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -1441,7 +1441,7 @@
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -1508,7 +1508,7 @@
/**
* @brief Set ADC instance clock source and prescaler.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled.
* @rmtoll CFGR2 CKMODE LL_ADC_SetClock
@@ -1518,7 +1518,7 @@
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC (1)
*
- * (1) On this STM32 serie, synchronous clock has no prescaler.
+ * (1) On this STM32 series, synchronous clock has no prescaler.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
@@ -1535,7 +1535,7 @@
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC (1)
*
- * (1) On this STM32 serie, synchronous clock has no prescaler.
+ * (1) On this STM32 series, synchronous clock has no prescaler.
*/
__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
{
@@ -1546,7 +1546,7 @@
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -1585,7 +1585,7 @@
* @brief Set ADC conversion data alignment.
* @note Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -1652,7 +1652,7 @@
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -1724,7 +1724,7 @@
/**
* @brief Set sampling time common to a group of channels.
* @note Unit: ADC clock cycles.
- * @note On this STM32 serie, sampling time scope is on ADC instance:
+ * @note On this STM32 series, sampling time scope is on ADC instance:
* Sampling time common to all channels.
* (on some other STM32 families, sampling time is channel wise)
* @note In case of internal channel (VrefInt, TempSensor, ...) to be
@@ -1735,7 +1735,7 @@
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -1744,7 +1744,7 @@
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -1769,12 +1769,12 @@
/**
* @brief Get sampling time common to a group of channels.
* @note Unit: ADC clock cycles.
- * @note On this STM32 serie, sampling time scope is on ADC instance:
+ * @note On this STM32 series, sampling time scope is on ADC instance:
* Sampling time common to all channels.
* (on some other STM32 families, sampling time is channel wise)
* @note Conversion time is the addition of sampling time and processing time.
* Refer to reference manual for ADC processing time of
- * this STM32 serie.
+ * this STM32 series.
* @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
@@ -1804,7 +1804,7 @@
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external IP (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -1812,7 +1812,7 @@
* function @ref LL_ADC_REG_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -1895,7 +1895,7 @@
/**
* @brief Set ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -1932,7 +1932,7 @@
* @brief Set ADC group regular sequencer scan direction.
* @note On some other STM32 families, this setting is not available and
* the default scan direction is forward.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -1969,7 +1969,7 @@
* number of ranks.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2009,16 +2009,16 @@
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Set channels selected by overwriting the current sequencer
* configuration.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* not fully configurable: sequencer length and each rank
* affectation to a channel are fixed by channel HW number.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2087,16 +2087,16 @@
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Set channels selected by adding them to the current sequencer
* configuration.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* not fully configurable: sequencer length and each rank
* affectation to a channel are fixed by channel HW number.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2165,16 +2165,16 @@
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Set channels selected by removing them to the current sequencer
* configuration.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* not fully configurable: sequencer length and each rank
* affectation to a channel are fixed by channel HW number.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2241,16 +2241,16 @@
* - Channels order reading into each rank of scan sequence:
* rank of each channel is fixed by channel HW number
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* not fully configurable: sequencer length and each rank
* affectation to a channel are fixed by channel HW number.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2337,7 +2337,7 @@
* conversions launched successively automatically.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2390,7 +2390,7 @@
* (overrun flag and interruption if enabled).
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2450,7 +2450,7 @@
* The default setting of overrun is data preserved.
* Therefore, for compatibility with all devices, parameter
* overrun should be set to data overwritten.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2498,14 +2498,14 @@
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC group regular.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2564,14 +2564,14 @@
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC group regular.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2622,14 +2622,14 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC group regular.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2655,14 +2655,14 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC group regular.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -2732,14 +2732,14 @@
/**
* @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
+ * @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled and ADC internal voltage regulator enabled.
* @rmtoll CR ADEN LL_ADC_Enable
@@ -2758,7 +2758,7 @@
/**
* @brief Disable the selected ADC instance.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be not disabled. Must be enabled without conversion on going
* on group regular.
@@ -2778,7 +2778,7 @@
/**
* @brief Get the selected ADC instance enable state.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll CR ADEN LL_ADC_IsEnabled
@@ -2804,14 +2804,14 @@
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
- * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * @note On this STM32 series, a minimum number of ADC clock cycles
* are required between ADC end of calibration and ADC enable.
* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
* @note In case of usage of ADC with DMA transfer:
- * On this STM32 serie, ADC DMA transfer request should be disabled
+ * On this STM32 series, ADC DMA transfer request should be disabled
* during calibration:
* Calibration factor is available in data register
- * and also transfered by DMA.
+ * and also transferred by DMA.
* To not insert ADC calibration factor among ADC conversion data
* in array variable, DMA transfer must be disabled during
* calibration.
@@ -2819,7 +2819,7 @@
* DMA transfer setting restore after calibration.
* Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
* @ref LL_ADC_REG_SetDMATransfer() ).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADCAL LL_ADC_StartCalibration
@@ -2857,14 +2857,14 @@
/**
* @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
@@ -2885,7 +2885,7 @@
/**
* @brief Stop ADC group regular conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group regular,
* without ADC disable command on going.
@@ -3009,7 +3009,7 @@
/**
* @brief Get flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
@@ -3078,7 +3078,7 @@
/**
* @brief Clear flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
@@ -3367,7 +3367,7 @@
*/
/* Initialization of some features of ADC common parameters and multimode */
-/* Note: On this STM32 serie, there is no ADC common initialization */
+/* Note: On this STM32 series, there is no ADC common initialization */
/* function. */
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
@@ -3406,3 +3406,4 @@
#endif
#endif /* __STM32F0xx_LL_ADC_H */
+
diff --git a/Inc/stm32f0xx_ll_bus.h b/Inc/stm32f0xx_ll_bus.h
index abdf72a..d58df30 100644
--- a/Inc/stm32f0xx_ll_bus.h
+++ b/Inc/stm32f0xx_ll_bus.h
@@ -26,10 +26,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -840,3 +839,4 @@
#endif
#endif /* __STM32F0xx_LL_BUS_H */
+
diff --git a/Inc/stm32f0xx_ll_comp.h b/Inc/stm32f0xx_ll_comp.h
index 785349e..05b5a3e 100644
--- a/Inc/stm32f0xx_ll_comp.h
+++ b/Inc/stm32f0xx_ll_comp.h
@@ -826,3 +826,4 @@
#endif
#endif /* __STM32F0xx_LL_COMP_H */
+
diff --git a/Inc/stm32f0xx_ll_cortex.h b/Inc/stm32f0xx_ll_cortex.h
index e6587ce..e91ea13 100644
--- a/Inc/stm32f0xx_ll_cortex.h
+++ b/Inc/stm32f0xx_ll_cortex.h
@@ -22,8 +22,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -315,3 +315,4 @@
#endif
#endif /* __STM32F0xx_LL_CORTEX_H */
+
diff --git a/Inc/stm32f0xx_ll_crc.h b/Inc/stm32f0xx_ll_crc.h
index f3d9cac..12008c1 100644
--- a/Inc/stm32f0xx_ll_crc.h
+++ b/Inc/stm32f0xx_ll_crc.h
@@ -241,7 +241,7 @@
}
/**
- * @brief Configure the reversal of the bit order of the Output data
+ * @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
diff --git a/Inc/stm32f0xx_ll_crs.h b/Inc/stm32f0xx_ll_crs.h
index 3ae5eb3..32c9232 100644
--- a/Inc/stm32f0xx_ll_crs.h
+++ b/Inc/stm32f0xx_ll_crs.h
@@ -93,7 +93,7 @@
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
-#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
diff --git a/Inc/stm32f0xx_ll_dac.h b/Inc/stm32f0xx_ll_dac.h
index a3beb30..737fb03 100644
--- a/Inc/stm32f0xx_ll_dac.h
+++ b/Inc/stm32f0xx_ll_dac.h
@@ -395,7 +395,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval 1...2 (value "2" depending on DAC channel 2 availability)
*/
@@ -415,7 +415,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
*/
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -519,7 +519,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
@@ -552,7 +552,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
@@ -582,7 +582,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param WaveAutoGeneration This parameter can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
@@ -607,7 +607,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
@@ -636,7 +636,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param NoiseLFSRMask This parameter can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
@@ -670,7 +670,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
@@ -708,7 +708,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriangleAmplitude This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
@@ -742,7 +742,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
@@ -775,7 +775,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param OutputBuffer This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
@@ -798,7 +798,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
@@ -830,7 +830,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -851,7 +851,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -871,7 +871,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
@@ -908,7 +908,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Register This parameter can be one of the following values:
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
@@ -942,7 +942,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -961,7 +961,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -981,7 +981,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
@@ -1009,7 +1009,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1028,7 +1028,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1048,7 +1048,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
@@ -1077,7 +1077,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1098,7 +1098,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
@@ -1123,7 +1123,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
@@ -1148,7 +1148,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
@@ -1234,7 +1234,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
@@ -1417,3 +1417,4 @@
#endif
#endif /* __STM32F0xx_LL_DAC_H */
+
diff --git a/Inc/stm32f0xx_ll_dma.h b/Inc/stm32f0xx_ll_dma.h
index c33d9cb..619b6d3 100644
--- a/Inc/stm32f0xx_ll_dma.h
+++ b/Inc/stm32f0xx_ll_dma.h
@@ -9,8 +9,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -1036,7 +1036,7 @@
/**
* @brief Configure the Source and Destination addresses.
* @note This API must not be called when the DMA channel is enabled.
- * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
+ * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
* CMAR MA LL_DMA_ConfigAddresses
* @param DMAx DMAx Instance
@@ -2231,3 +2231,4 @@
#endif
#endif /* __STM32F0xx_LL_DMA_H */
+
diff --git a/Inc/stm32f0xx_ll_exti.h b/Inc/stm32f0xx_ll_exti.h
index 3e32ac1..c992cac 100644
--- a/Inc/stm32f0xx_ll_exti.h
+++ b/Inc/stm32f0xx_ll_exti.h
@@ -1011,3 +1011,4 @@
#endif
#endif /* __STM32F0xx_LL_EXTI_H */
+
diff --git a/Inc/stm32f0xx_ll_gpio.h b/Inc/stm32f0xx_ll_gpio.h
index ab61338..986db52 100644
--- a/Inc/stm32f0xx_ll_gpio.h
+++ b/Inc/stm32f0xx_ll_gpio.h
@@ -935,3 +935,4 @@
#endif
#endif /* __STM32F0xx_LL_GPIO_H */
+
diff --git a/Inc/stm32f0xx_ll_i2c.h b/Inc/stm32f0xx_ll_i2c.h
index 64e90b8..63c8e31 100644
--- a/Inc/stm32f0xx_ll_i2c.h
+++ b/Inc/stm32f0xx_ll_i2c.h
@@ -451,7 +451,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
}
@@ -500,7 +500,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
}
@@ -535,7 +535,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
}
@@ -568,7 +568,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
}
@@ -601,7 +601,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
}
@@ -616,7 +616,7 @@
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
{
uint32_t data_reg_addr;
@@ -664,7 +664,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
}
@@ -697,7 +697,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
}
@@ -738,7 +738,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
}
@@ -774,7 +774,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}
@@ -802,7 +802,7 @@
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
*/
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
}
@@ -851,7 +851,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
}
@@ -907,7 +907,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
}
@@ -932,7 +932,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
}
@@ -943,7 +943,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
}
@@ -954,7 +954,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
}
@@ -965,7 +965,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
}
@@ -976,7 +976,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
}
@@ -1013,7 +1013,7 @@
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
*/
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
}
@@ -1062,7 +1062,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
}
@@ -1101,7 +1101,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
}
@@ -1152,7 +1152,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
}
@@ -1184,7 +1184,7 @@
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
}
@@ -1212,7 +1212,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
}
@@ -1266,7 +1266,7 @@
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
(ClockTimeout)) ? 1UL : 0UL);
@@ -1308,7 +1308,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
}
@@ -1341,7 +1341,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
}
@@ -1374,7 +1374,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
}
@@ -1407,7 +1407,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
}
@@ -1440,7 +1440,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
}
@@ -1479,7 +1479,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
}
@@ -1530,7 +1530,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
}
@@ -1551,7 +1551,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
}
@@ -1564,7 +1564,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
}
@@ -1577,7 +1577,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
}
@@ -1590,7 +1590,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
}
@@ -1603,7 +1603,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
}
@@ -1616,7 +1616,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
}
@@ -1629,7 +1629,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
}
@@ -1642,7 +1642,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
}
@@ -1655,7 +1655,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
}
@@ -1668,7 +1668,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
}
@@ -1681,7 +1681,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
}
@@ -1696,7 +1696,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
}
@@ -1711,7 +1711,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
}
@@ -1727,7 +1727,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
}
@@ -1740,7 +1740,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
}
@@ -1901,7 +1901,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
}
@@ -1936,7 +1936,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
}
@@ -1960,7 +1960,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
}
@@ -2037,7 +2037,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
}
@@ -2065,7 +2065,7 @@
* @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
}
@@ -2089,7 +2089,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
}
@@ -2152,7 +2152,7 @@
* @arg @ref LL_I2C_DIRECTION_WRITE
* @arg @ref LL_I2C_DIRECTION_READ
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
}
@@ -2163,7 +2163,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
}
@@ -2193,7 +2193,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
}
@@ -2206,7 +2206,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
}
@@ -2217,7 +2217,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
{
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
}
@@ -2243,8 +2243,8 @@
* @{
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
diff --git a/Inc/stm32f0xx_ll_pwr.h b/Inc/stm32f0xx_ll_pwr.h
index 072196a..0416b9c 100644
--- a/Inc/stm32f0xx_ll_pwr.h
+++ b/Inc/stm32f0xx_ll_pwr.h
@@ -140,19 +140,19 @@
#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
#endif /* PWR_CSR_EWUP3 */
#if defined(PWR_CSR_EWUP4)
-#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */
+#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : PA2 */
#endif /* PWR_CSR_EWUP4 */
#if defined(PWR_CSR_EWUP5)
-#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */
+#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : PC5 */
#endif /* PWR_CSR_EWUP5 */
#if defined(PWR_CSR_EWUP6)
-#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */
+#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : PB5 */
#endif /* PWR_CSR_EWUP6 */
#if defined(PWR_CSR_EWUP7)
-#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */
+#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : PB15 */
#endif /* PWR_CSR_EWUP7 */
#if defined(PWR_CSR_EWUP8)
-#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */
+#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : PF2 */
#endif /* PWR_CSR_EWUP8 */
/**
* @}
diff --git a/Inc/stm32f0xx_ll_rcc.h b/Inc/stm32f0xx_ll_rcc.h
index 4457bb8..cdcfaf8 100644
--- a/Inc/stm32f0xx_ll_rcc.h
+++ b/Inc/stm32f0xx_ll_rcc.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -2256,3 +2255,4 @@
#endif
#endif /* __STM32F0xx_LL_RCC_H */
+
diff --git a/Inc/stm32f0xx_ll_rtc.h b/Inc/stm32f0xx_ll_rtc.h
index 41889b0..3056420 100644
--- a/Inc/stm32f0xx_ll_rtc.h
+++ b/Inc/stm32f0xx_ll_rtc.h
@@ -17,8 +17,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_LL_RTC_H
-#define __STM32F0xx_LL_RTC_H
+#ifndef STM32F0xx_LL_RTC_H
+#define STM32F0xx_LL_RTC_H
#ifdef __cplusplus
extern "C" {
@@ -45,7 +45,7 @@
*/
/* Masks Definition */
#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
+#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
/* Write protection defines */
#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
@@ -164,25 +164,25 @@
LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A.
- This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A.
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask().
*/
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
- This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A.
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday().
*/
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay().
If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay().
*/
} LL_RTC_AlarmTypeDef;
@@ -200,8 +200,8 @@
/** @defgroup RTC_LL_EC_FORMAT FORMAT
* @{
*/
-#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */
+#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */
/**
* @}
*/
@@ -222,7 +222,9 @@
* @{
*/
#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
+#if defined(RTC_TAMPER3_SUPPORT)
#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
+#endif /* RTC_TAMPER3_SUPPORT */
#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
@@ -393,12 +395,8 @@
/** @defgroup RTC_LL_EC_TAMPER TAMPER
* @{
*/
-#if defined(RTC_TAMPER1_SUPPORT)
#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
#define LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
-#endif /* RTC_TAMPER2_SUPPORT */
#if defined(RTC_TAMPER3_SUPPORT)
#define LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E /*!< RTC_TAMP3 input detection */
#endif /* RTC_TAMPER3_SUPPORT */
@@ -406,39 +404,6 @@
* @}
*/
-/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
* @{
*/
@@ -449,9 +414,7 @@
/**
* @}
*/
-#endif /* RTC_TAFCR_TAMPPRCH */
-#if defined(RTC_TAFCR_TAMPFLT)
/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
* @{
*/
@@ -462,9 +425,7 @@
/**
* @}
*/
-#endif /* RTC_TAFCR_TAMPFLT */
-#if defined(RTC_TAFCR_TAMPFREQ)
/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
* @{
*/
@@ -479,24 +440,20 @@
/**
* @}
*/
-#endif /* RTC_TAFCR_TAMPFREQ */
/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
* @{
*/
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER2_SUPPORT */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
+#if defined(RTC_WAKEUP_SUPPORT)
/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
* @{
*/
@@ -509,6 +466,7 @@
/**
* @}
*/
+#endif /* RTC_WAKEUP_SUPPORT */
#if defined(RTC_BACKUP_SUPPORT)
/** @defgroup RTC_LL_EC_BKP BACKUP
@@ -804,8 +762,8 @@
* @note PC13 forced to push-pull output if all RTC alternate functions are disabled
* @note PC14 and PC15 forced to push-pull output if LSE is disabled
* @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n
- * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
- * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode
+ * TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
+ * TAFCR PC15MODE LL_RTC_EnablePushPullMode
* @param RTCx RTC Instance
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_PIN_PC13
@@ -955,7 +913,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
+ return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
}
/**
@@ -1161,7 +1119,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
{
- return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))) >> RTC_TR_MNU_Pos);
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
}
/**
@@ -1196,7 +1154,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
{
- return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU))) >> RTC_TR_SU_Pos);
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
}
/**
@@ -1222,12 +1180,12 @@
*/
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- uint32_t temp = 0U;
+ uint32_t temp;
- temp = Format12_24 | \
- (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
}
@@ -1250,12 +1208,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
- uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
- (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
- ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)));
}
/**
@@ -1290,7 +1243,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
+ return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
}
/**
@@ -1318,17 +1271,18 @@
}
/**
- * @brief Get Sub second value in the synchronous prescaler counter.
+ * @brief Get subseconds value in the synchronous prescaler counter.
* @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
* LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
* SubSeconds value in second fraction ratio with time unit following
* generic formula:
- * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * ==> Seconds fraction ratio * time_unit =
+ * [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
* This conversion can be performed only if no shift operation is pending
* (ie. SHFP=0) when PREDIV_S >= SS.
* @rmtoll SSR SS LL_RTC_TIME_GetSubSecond
* @param RTCx RTC Instance
- * @retval Sub second value (number between 0 and 65535)
+ * @retval Subseconds value (number between 0 and 65535)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
{
@@ -1552,12 +1506,12 @@
*/
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
{
- uint32_t temp = 0U;
+ uint32_t temp;
- temp = (WeekDay << RTC_DR_WDU_Pos) | \
- (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
+ temp = ( WeekDay << RTC_DR_WDU_Pos) | \
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
(((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
- (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
}
@@ -1580,13 +1534,14 @@
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
- uint32_t temp = 0U;
+ uint32_t temp;
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
- (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
- (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
- ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
+
+ return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+ (((temp & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos) << RTC_OFFSET_DAY) | \
+ (((temp & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos) << RTC_OFFSET_MONTH) | \
+ ((temp & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos));
}
/**
@@ -1880,11 +1835,12 @@
*/
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- uint32_t temp = 0U;
+ uint32_t temp;
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
}
@@ -1908,7 +1864,8 @@
}
/**
- * @brief Set Alarm A Mask the most-significant bits starting at this bit
+ * @brief Mask the most-significant bits of the subseconds field starting from
+ * the bit specified in parameter Mask
* @note This register can be written only when ALRAE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
@@ -1922,7 +1879,7 @@
}
/**
- * @brief Get Alarm A Mask the most-significant bits starting at this bit
+ * @brief Get Alarm A subseconds mask
* @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xF
@@ -1933,7 +1890,7 @@
}
/**
- * @brief Set Alarm A Sub seconds value
+ * @brief Set Alarm A subseconds value
* @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond
* @param RTCx RTC Instance
* @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
@@ -1945,7 +1902,7 @@
}
/**
- * @brief Get Alarm A Sub seconds value
+ * @brief Get Alarm A subseconds value
* @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
@@ -2162,7 +2119,7 @@
}
/**
- * @brief Get time-stamp sub second value
+ * @brief Get time-stamp subseconds value
* @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
@@ -2215,7 +2172,7 @@
* @arg @ref LL_RTC_TAMPER_2
* @arg @ref LL_RTC_TAMPER_3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2234,7 +2191,7 @@
* @arg @ref LL_RTC_TAMPER_2
* @arg @ref LL_RTC_TAMPER_3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2242,7 +2199,6 @@
CLEAR_BIT(RTCx->TAFCR, Tamper);
}
-#if defined(RTC_TAFCR_TAMPPUDIS)
/**
* @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
* @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
@@ -2264,9 +2220,7 @@
{
CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
}
-#endif /* RTC_TAFCR_TAMPPUDIS */
-#if defined(RTC_TAFCR_TAMPPRCH)
/**
* @brief Set RTC_TAMPx precharge duration
* @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
@@ -2297,9 +2251,7 @@
{
return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
}
-#endif /* RTC_TAFCR_TAMPPRCH */
-#if defined(RTC_TAFCR_TAMPFLT)
/**
* @brief Set RTC_TAMPx filter count
* @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
@@ -2330,9 +2282,7 @@
{
return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
}
-#endif /* RTC_TAFCR_TAMPFLT */
-#if defined(RTC_TAFCR_TAMPFREQ)
/**
* @brief Set Tamper sampling frequency
* @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
@@ -2371,7 +2321,6 @@
{
return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
}
-#endif /* RTC_TAFCR_TAMPFREQ */
/**
* @brief Enable Active level for Tamper input
@@ -2384,7 +2333,7 @@
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2403,7 +2352,7 @@
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2452,13 +2401,13 @@
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
}
/**
* @brief Select Wakeup clock
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
+ * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
* @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock
* @param RTCx RTC Instance
* @param WakeupClock This parameter can be one of the following values:
@@ -2494,7 +2443,7 @@
/**
* @brief Set Wakeup auto-reload value
- * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
+ * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
* @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload
* @param RTCx RTC Instance
* @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
@@ -2541,13 +2490,13 @@
*/
__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
- uint32_t tmp = 0U;
+ uint32_t temp;
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
+ temp = (uint32_t)(&(RTCx->BKP0R));
+ temp += (BackupRegister * 4U);
/* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
+ *(__IO uint32_t *)temp = (uint32_t)Data;
}
/**
@@ -2564,13 +2513,13 @@
*/
__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
- uint32_t tmp = 0U;
+ uint32_t temp;
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
+ temp = (uint32_t)(&(RTCx->BKP0R));
+ temp += (BackupRegister * 4U);
/* Read the specified register */
- return (*(__IO uint32_t *)tmp);
+ return (*(__IO uint32_t *)temp);
}
/**
@@ -2592,6 +2541,7 @@
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ *
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
@@ -2608,6 +2558,7 @@
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ *
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
{
@@ -2617,7 +2568,7 @@
/**
* @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
* @rmtoll CALR CALP LL_RTC_CAL_SetPulse
* @param RTCx RTC Instance
* @param Pulse This parameter can be one of the following values:
@@ -2638,11 +2589,11 @@
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
+ return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
}
/**
- * @brief Set the calibration cycle period
+ * @brief Set smooth calibration cycle period
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
* @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n
@@ -2660,7 +2611,7 @@
}
/**
- * @brief Get the calibration cycle period
+ * @brief Get smooth calibration cycle period
* @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n
* CALR CALW16 LL_RTC_CAL_GetPeriod
* @param RTCx RTC Instance
@@ -2675,7 +2626,7 @@
}
/**
- * @brief Set Calibration minus
+ * @brief Set smooth Calibration minus
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
* @rmtoll CALR CALM LL_RTC_CAL_SetMinus
@@ -2689,7 +2640,7 @@
}
/**
- * @brief Get Calibration minus
+ * @brief Get smooth Calibration minus
* @rmtoll CALR CALM LL_RTC_CAL_GetMinus
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
@@ -2715,7 +2666,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
}
#if defined(RTC_TAMPER3_SUPPORT)
@@ -2727,11 +2678,10 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
}
#endif /* RTC_TAMPER3_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
/**
* @brief Get RTC_TAMP2 detection flag
* @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
@@ -2740,11 +2690,9 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
}
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER1_SUPPORT)
/**
* @brief Get RTC_TAMP1 detection flag
* @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
@@ -2753,9 +2701,8 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
}
-#endif /* RTC_TAMPER1_SUPPORT */
/**
* @brief Get Time-stamp overflow flag
@@ -2765,7 +2712,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
}
/**
@@ -2776,7 +2723,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
}
#if defined(RTC_WAKEUP_SUPPORT)
@@ -2788,7 +2735,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
}
#endif /* RTC_WAKEUP_SUPPORT */
@@ -2800,7 +2747,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
}
#if defined(RTC_TAMPER3_SUPPORT)
@@ -2816,7 +2763,6 @@
}
#endif /* RTC_TAMPER3_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
/**
* @brief Clear RTC_TAMP2 detection flag
* @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2
@@ -2827,9 +2773,7 @@
{
WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
}
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER1_SUPPORT)
/**
* @brief Clear RTC_TAMP1 detection flag
* @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1
@@ -2840,7 +2784,6 @@
{
WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
}
-#endif /* RTC_TAMPER1_SUPPORT */
/**
* @brief Clear Time-stamp overflow flag
@@ -2896,7 +2839,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
}
/**
@@ -2907,7 +2850,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
}
/**
@@ -2929,7 +2872,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
}
/**
@@ -2940,7 +2883,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
}
#if defined(RTC_WAKEUP_SUPPORT)
@@ -2952,7 +2895,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
}
#endif /* RTC_WAKEUP_SUPPORT */
@@ -2964,7 +2907,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
}
/**
@@ -3079,7 +3022,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
}
#if defined(RTC_WAKEUP_SUPPORT)
@@ -3091,7 +3034,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
}
#endif /* RTC_WAKEUP_SUPPORT */
@@ -3103,7 +3046,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
}
/**
@@ -3114,8 +3057,8 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->TAFCR,
- RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
+ return ((READ_BIT(RTCx->TAFCR,
+ RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE)) ? 1UL : 0UL);
}
/**
@@ -3163,4 +3106,4 @@
}
#endif
-#endif /* __STM32F0xx_LL_RTC_H */
+#endif /* STM32F0xx_LL_RTC_H */
diff --git a/Inc/stm32f0xx_ll_spi.h b/Inc/stm32f0xx_ll_spi.h
index ad1e84b..84b7c4f 100644
--- a/Inc/stm32f0xx_ll_spi.h
+++ b/Inc/stm32f0xx_ll_spi.h
@@ -2281,3 +2281,4 @@
#endif
#endif /* STM32F0xx_LL_SPI_H */
+
diff --git a/Inc/stm32f0xx_ll_system.h b/Inc/stm32f0xx_ll_system.h
index e212d1f..656200b 100644
--- a/Inc/stm32f0xx_ll_system.h
+++ b/Inc/stm32f0xx_ll_system.h
@@ -83,9 +83,9 @@
/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
* @{
*/
-#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation enveloppe source */
-#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation enveloppe source */
-#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation enveloppe source */
+#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation envelope source */
+#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation envelope source */
+#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation envelope source */
/**
* @}
*/
@@ -1847,3 +1847,5 @@
#endif
#endif /* __STM32F0xx_LL_SYSTEM_H */
+
+
diff --git a/Inc/stm32f0xx_ll_tim.h b/Inc/stm32f0xx_ll_tim.h
index fd0f4bd..f827968 100644
--- a/Inc/stm32f0xx_ll_tim.h
+++ b/Inc/stm32f0xx_ll_tim.h
@@ -932,6 +932,7 @@
* @}
*/
+
/**
* @}
*/
@@ -964,10 +965,6 @@
* @}
*/
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
- * @{
- */
-
/**
* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
@@ -1059,11 +1056,6 @@
* @}
*/
-
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
* @{
@@ -1613,7 +1605,7 @@
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
{
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
@@ -1898,7 +1890,7 @@
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -1962,7 +1954,7 @@
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2035,7 +2027,7 @@
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2510,7 +2502,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
@@ -3974,7 +3966,7 @@
* @{
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
diff --git a/Inc/stm32f0xx_ll_usart.h b/Inc/stm32f0xx_ll_usart.h
index b4b3ca1..a91b3fd 100644
--- a/Inc/stm32f0xx_ll_usart.h
+++ b/Inc/stm32f0xx_ll_usart.h
@@ -31,7 +31,8 @@
* @{
*/
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) || defined (USART6) || defined (USART7) || defined (USART8)
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) \
+ || defined(USART6) || defined(USART7) || defined(USART8)
/** @defgroup USART_LL USART
* @{
@@ -41,6 +42,12 @@
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@@ -286,7 +293,7 @@
#else
#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-#endif/* USART_7BITS_SUPPORT */
+#endif /* USART_7BITS_SUPPORT */
/**
* @}
*/
@@ -591,7 +598,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
@@ -634,7 +641,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
@@ -713,7 +720,7 @@
* @arg @ref LL_USART_DIRECTION_TX
* @arg @ref LL_USART_DIRECTION_TX_RX
*/
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
@@ -747,7 +754,7 @@
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
*/
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
@@ -774,7 +781,7 @@
* @arg @ref LL_USART_WAKEUP_IDLELINE
* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
*/
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
}
@@ -809,7 +816,7 @@
*
* (*) Values not available on all devices
*/
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
}
@@ -842,7 +849,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
@@ -869,7 +876,7 @@
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
*/
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
}
@@ -901,7 +908,7 @@
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
*/
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
}
@@ -932,7 +939,7 @@
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
}
@@ -963,7 +970,7 @@
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
}
@@ -1030,7 +1037,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
}
@@ -1065,7 +1072,7 @@
*
* (*) Values not available on all devices
*/
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
}
@@ -1128,7 +1135,7 @@
* @arg @ref LL_USART_TXRX_STANDARD
* @arg @ref LL_USART_TXRX_SWAPPED
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
}
@@ -1155,7 +1162,7 @@
* @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
}
@@ -1182,7 +1189,7 @@
* @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
}
@@ -1211,7 +1218,7 @@
* @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
*/
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
}
@@ -1242,7 +1249,7 @@
* @arg @ref LL_USART_BITORDER_LSBFIRST
* @arg @ref LL_USART_BITORDER_MSBFIRST
*/
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
}
@@ -1281,7 +1288,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
}
@@ -1320,7 +1327,7 @@
*
* (*) Values not available on all devices
*/
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
}
@@ -1353,7 +1360,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
}
@@ -1397,7 +1404,7 @@
* @param USARTx USART Instance
* @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
*/
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
@@ -1410,7 +1417,7 @@
* @arg @ref LL_USART_ADDRESS_DETECT_4B
* @arg @ref LL_USART_ADDRESS_DETECT_7B
*/
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
}
@@ -1499,7 +1506,7 @@
* @arg @ref LL_USART_HWCONTROL_CTS
* @arg @ref LL_USART_HWCONTROL_RTS_CTS
*/
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
@@ -1532,7 +1539,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
}
@@ -1565,7 +1572,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
@@ -1600,7 +1607,7 @@
* @arg @ref LL_USART_WAKEUP_ON_STARTBIT
* @arg @ref LL_USART_WAKEUP_ON_RXNE
*/
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
}
@@ -1655,7 +1662,7 @@
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
{
uint32_t usartdiv;
uint32_t brrresult = 0x0U;
@@ -1702,7 +1709,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
*/
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
}
@@ -1726,7 +1733,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
}
@@ -1775,7 +1782,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
}
@@ -1806,7 +1813,7 @@
* @arg @ref LL_USART_IRDA_POWER_NORMAL
* @arg @ref LL_USART_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
}
@@ -1835,7 +1842,7 @@
* @param USARTx USART Instance
* @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
@@ -1884,7 +1891,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
}
@@ -1923,7 +1930,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
}
@@ -1955,7 +1962,7 @@
* @param USARTx USART Instance
* @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
}
@@ -1984,7 +1991,7 @@
* @param USARTx USART Instance
* @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
@@ -2013,7 +2020,7 @@
* @param USARTx USART Instance
* @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
}
@@ -2061,7 +2068,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
@@ -2101,7 +2108,7 @@
* @arg @ref LL_USART_LINBREAK_DETECT_10B
* @arg @ref LL_USART_LINBREAK_DETECT_11B
*/
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
}
@@ -2140,7 +2147,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
}
@@ -2176,7 +2183,7 @@
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
@@ -2203,7 +2210,7 @@
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
@@ -2242,7 +2249,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
@@ -2273,7 +2280,7 @@
* @arg @ref LL_USART_DE_POLARITY_HIGH
* @arg @ref LL_USART_DE_POLARITY_LOW
*/
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
}
@@ -2315,7 +2322,8 @@
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported), CLKEN bits in the USART_CR2 register,
- - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.
+ - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported)
+ and HDSEL bits in the USART_CR3 register.
*/
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
@@ -2368,7 +2376,8 @@
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported) bit in the USART_CR2 register,
- - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.
+ - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported)
+ and HDSEL bits in the USART_CR3 register.
*/
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
@@ -2424,7 +2433,8 @@
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- - IREN (if Irda feature is supported) , SCEN (if Smartcard feature is supported)and HDSEL bits in the USART_CR3 register.
+ - IREN (if Irda feature is supported) , SCEN (if Smartcard feature is supported)
+ and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
#if defined(USART_SMARTCARD_SUPPORT)
@@ -2632,7 +2642,8 @@
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported) and CLKEN bits in the USART_CR2 register,
- - IREN (if Irda feature is supported), SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.
+ - IREN (if Irda feature is supported), SCEN (if Smartcard feature is supported)
+ and HDSEL bits in the USART_CR3 register.
*/
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
@@ -2668,7 +2679,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
@@ -2679,7 +2690,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
@@ -2690,7 +2701,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
@@ -2701,7 +2712,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
@@ -2712,7 +2723,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
@@ -2723,7 +2734,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
}
@@ -2734,7 +2745,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
@@ -2745,7 +2756,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
}
@@ -2759,7 +2770,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
}
@@ -2773,7 +2784,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
@@ -2786,7 +2797,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
@@ -2797,7 +2808,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
}
@@ -2811,7 +2822,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
}
@@ -2825,7 +2836,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
}
@@ -2838,7 +2849,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
}
@@ -2849,7 +2860,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
@@ -2860,7 +2871,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
@@ -2871,7 +2882,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
@@ -2882,7 +2893,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
@@ -2897,7 +2908,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
@@ -2910,7 +2921,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
@@ -2921,7 +2932,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
@@ -3189,7 +3200,7 @@
SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
}
-#endif/* USART_LIN_SUPPORT */
+#endif /* USART_LIN_SUPPORT */
/**
* @brief Enable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
@@ -3395,7 +3406,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
@@ -3406,7 +3417,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
}
@@ -3417,7 +3428,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
@@ -3428,7 +3439,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
}
@@ -3439,7 +3450,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
@@ -3450,7 +3461,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
@@ -3461,7 +3472,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
}
@@ -3475,7 +3486,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
}
@@ -3490,7 +3501,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
}
@@ -3502,7 +3513,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
@@ -3515,7 +3526,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
@@ -3530,7 +3541,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
@@ -3574,7 +3585,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
@@ -3607,7 +3618,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
@@ -3640,7 +3651,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
@@ -3655,7 +3666,7 @@
* @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
@@ -3687,7 +3698,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
@@ -3698,7 +3709,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x1FF
*/
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
{
return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
}
@@ -3806,10 +3817,10 @@
/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
/**
* @}
@@ -3835,3 +3846,4 @@
#endif
#endif /* STM32F0xx_LL_USART_H */
+
diff --git a/Inc/stm32f0xx_ll_usb.h b/Inc/stm32f0xx_ll_usb.h
index 86badc0..e6cc4fc 100644
--- a/Inc/stm32f0xx_ll_usb.h
+++ b/Inc/stm32f0xx_ll_usb.h
@@ -22,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -42,15 +42,14 @@
* @brief USB Mode definition
*/
-
-
typedef enum
{
- USB_DEVICE_MODE = 0
+ USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
+
/**
- * @brief USB Initialization Structure definition
+ * @brief USB Instance Initialization Structure definition
*/
typedef struct
{
@@ -69,69 +68,63 @@
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
+ uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type */
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_LL_EP_Type */
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint16_t pmaadress; /*!< PMA Address
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t pmaaddr0; /*!< PMA Address0
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t pmaaddr1; /*!< PMA Address1
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint8_t doublebuffer; /*!< Double buffer enable
- This parameter can be 0 or 1 */
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral
- This parameter is added to ensure compatibility across USB peripherals */
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint32_t xfer_len; /*!< Current transfer length */
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+ uint32_t xfer_len; /*!< Current transfer length */
- uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
- uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
+ uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
+ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-
-
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
@@ -163,10 +156,21 @@
* @}
*/
+
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
+#ifndef USB_EP_RX_STRX
+#define USB_EP_RX_STRX (0x3U << 12)
+#endif /* USB_EP_RX_STRX */
+
#define EP_ADDR_MSK 0x7U
+
+#ifndef USE_USB_DOUBLE_BUFFER
+#define USE_USB_DOUBLE_BUFFER 1U
+#endif /* USE_USB_DOUBLE_BUFFER */
+
+
/**
* @}
*/
@@ -194,6 +198,7 @@
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
@@ -229,7 +234,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32F0xx_LL_USB_H */
diff --git a/Inc/stm32f0xx_ll_utils.h b/Inc/stm32f0xx_ll_utils.h
index 87a93a1..dd46cdf 100644
--- a/Inc/stm32f0xx_ll_utils.h
+++ b/Inc/stm32f0xx_ll_utils.h
@@ -3,6 +3,17 @@
* @file stm32f0xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,16 +27,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
diff --git a/Release_Notes.html b/Release_Notes.html
index 76857a5..de5af71 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -11,41 +11,168 @@
span.underline{text-decoration: underline;}
div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
- <link rel="stylesheet" href="_htmresc/mini-st.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
+ <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
</head>
<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
<center>
-<h1 id="release-notes-for-stm32f0xx-hal-drivers"><strong>Release Notes for STM32F0xx HAL Drivers</strong></h1>
-<p>Copyright © 2016 STMicroelectronics<br />
-</p>
-<a href="https://www.st.com" class="logo"><img src="../../_htmresc/st_logo.png" alt="ST logo" /></a>
+<h1 id="release-notes-forstm32f0xx-hal-drivers"><small>Release Notes for</small><mark>STM32F0xx HAL Drivers</mark></h1>
+<p>Copyright © 2016 STMicroelectronics</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
-</div>
-</div>
-<h1 id="license"><strong>License</strong></h1>
-This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
-<center>
-<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
-</center>
+<h1 id="purpose">Purpose</h1>
+<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
+<p>The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code re-usability and guarantees an easy portability on other devices and STM32 families.</p>
+<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provide basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not Fully Portable across the STM32 families; the availability of some functions depend on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
+<ul>
+<li>New set of inline function for direct and atomic register access</li>
+<li>One-shot operations that can be used by the HAL drivers or from application level.</li>
+<li>Fully Independent from HAL and can be used in standalone usage (without HAL drivers)</li>
+<li>Full features coverage of the all the supported peripherals.</li>
+</ul>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section1_7_6" aria-hidden="true"> <label for="collapse-section1_7_6" aria-hidden="true"><strong>V1.7.6 / 23-July-2021</strong></label>
+<input type="checkbox" id="collapse-section1_7_7" checked aria-hidden="true"> <label for="collapse-section1_7_7" aria-hidden="true"><strong>V1.7.7 / 27-January-2023</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation.</li>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</li>
</ul>
<h2 id="contents">Contents</h2>
<ul>
+<li><strong>HAL GENERIC</strong> update
+<ul>
+<li>Allow redefinition of macro UNUSED(x).</li>
+</ul></li>
+<li><strong>HAL RCC</strong> update
+<ul>
+<li>Add a static storage class specifier in the const tables.</li>
+</ul></li>
+<li><strong>HAL GPIO</strong> update
+<ul>
+<li>Reorder EXTI configuration sequence to avoid unexpected level detection.</li>
+</ul></li>
+<li><strong>HAL EXTI</strong> update
+<ul>
+<li>Fix computation of pExtiConfig->GPIOSel in the HAL_EXTI_GetConfigLine() API.</li>
+</ul></li>
+<li><strong>HAL CRC</strong> update
+<ul>
+<li>Add filter in HAL_CRCEx_Polynomial_Set() to exclude even polynomials.</li>
+<li>Update HAL_CRC_DeInit implementation to avoid overflow issues in CRC_IDR_IDR.</li>
+</ul></li>
+<li><strong>HAL ADC</strong> update
+<ul>
+<li>Remove multiple volatile reads or writes in interrupt handler for better performance.</li>
+</ul></li>
+<li><strong>LL/HAL TIM</strong> update
+<ul>
+<li>Manage configuration of the Capture/compare DMA request source
+<ul>
+<li>Add related new exported constants (TIM_CCDMAREQUEST_CC, TIM_CCDMAREQUEST_UPDATE).</li>
+<li>Create a new macro __HAL_TIM_SELECT_CCDMAREQUEST() allowing to program the TIMx_CR2.CCDS bitfield.</li>
+</ul></li>
+<li>Update __LL_TIM_CALC_PSC() macro to round up the evaluated value when the fractional part of the division is greater than 0.5.</li>
+</ul></li>
+<li><strong>HAL RTC_BKP</strong> update
+<ul>
+<li>Move constants RTC_IT_TAMP from hal_rtc.h to hal_rtc_ex.h.</li>
+<li>Use bits definitions from CMSIS Device header file instead of hard-coded values.</li>
+<li>Add new macro assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)) to check tamper filtering is disabled in case tamper events are triggered on signal edges.</li>
+<li>Rework functions HAL_RTCEx_SetTamper() and HAL_RTCEx_SetTamper_IT() to:
+<ul>
+<li>Write in TAFCR register in one single access instead of two.</li>
+<li>Avoid modifying user structure sTamper.</li>
+</ul></li>
+<li>Add a check on the RTC calendar initialization before entering in initialization mode.</li>
+</ul></li>
+<li><strong>HAL IRDA</strong> update
+<ul>
+<li>Improve header description of IRDA_WaitOnFlagUntilTimeout() function.</li>
+<li>Add a check on the IRDA parity before enabling the parity error interrupt.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li>
+</ul></li>
+<li><strong>HAL UART</strong> update
+<ul>
+<li>Improve header description of UART_WaitOnFlagUntilTimeout() function.</li>
+<li>Add a check on the UART parity before enabling the parity error interruption.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig().</li>
+<li>Correct the way transmit data flush request is managed.</li>
+<li>Removal of HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs</li>
+<li>Disable the Receiver Timeout Interrupt when data reception is completed.</li>
+<li>Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.</li>
+</ul></li>
+<li><strong>LL/HAL USART</strong> update
+<ul>
+<li>Improve header description of USART_WaitOnFlagUntilTimeout() function.</li>
+<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
+<li>Fix compilation warnings generated with ARMV6 compiler.</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong> update
+<ul>
+<li>Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().</li>
+</ul></li>
+<li><strong>LL/HAL I2C</strong> update
+<ul>
+<li>Improve header description of I2C_WaitOnFlagUntilTimeout() function.</li>
+<li>Rename I2C_IsAcknowledgeFailed() I2C_IsErrorOccurred() and correct the way errors are checked and reported when they occur in polling mode.
+<ul>
+<li>Update to fix issue detected due to low system frequency execution (HSI).</li>
+<li>Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA</li>
+</ul></li>
+<li>Clear the ADDRF flag only when direction is confirmed as changed, to prevent that the ADDRF flag is cleared too early when the restart is received.</li>
+<li>Fix timeout issue using HAL MEM interface through FreeRTOS.</li>
+<li>I2C_IsErrorOccurred does not return error if timeout is detected.</li>
+<li>Update [HAL_I2C_IsDeviceReady] API to support 10_bit addressing mode.</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> update
+<ul>
+<li>Add flushing of TX register to fix the issue of mismatching data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master.</li>
+</ul></li>
+<li><strong>HAL SPI</strong> update
+<ul>
+<li>Fix driver to don’t update state in case of error. (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT).</li>
+</ul></li>
+<li><strong>HAL CAN</strong> update
+<ul>
+<li>Removal of never reached code.</li>
+<li>Improve protection against bad inputs.</li>
+</ul></li>
+<li><strong>HAL CEC</strong> update
+<ul>
+<li>Remove multiple volatile reads or writes in interrupt handler for better performance.</li>
+</ul></li>
+<li><strong>USB_FS_HAL</strong> update
+<ul>
+<li>PCD: add supporting multi packets transfer on Interrupt endpoint.</li>
+<li>Set DCD timeout to a minimum of 300ms before starting BCD primary detection process.</li>
+<li>HAL: PCD: software correction added to avoid unexpected STALL condition during EP0 multi packet OUT transfer.</li>
+<li>hal_pcd.h: add a mask for USB RX bytes count.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_7_6" aria-hidden="true"> <label for="collapse-section1_7_6" aria-hidden="true"><strong>V1.7.6 / 23-July-2021</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>General updates to fix known defects and enhancements implementation.</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<ul>
<li><strong>HAL GPIO</strong> driver
<ul>
<li>Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.</li>
@@ -137,7 +264,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_7_5" aria-hidden="true"> <label for="collapse-section1_7_5" aria-hidden="true"><strong>V1.7.5 / 06-November-2020</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Patch release to fix known defects and enhancements implementation.</li>
<li>Remove “register” keyword to be compliant with new C++ rules:
@@ -257,7 +384,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_7_4" aria-hidden="true"> <label for="collapse-section1_7_4" aria-hidden="true"><strong>V1.7.4 / 24-July-2020</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Maintenance release to fix known defects and enhancements implementation</li>
<li><strong>HAL Drivers changes</strong>
@@ -298,7 +425,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_7_3" aria-hidden="true"> <label for="collapse-section1_7_3" aria-hidden="true"><strong>V1.7.3 / 12-September-2019</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li>Add support of HAL callback registration feature</li>
@@ -347,7 +474,7 @@
<ul>
<li>HAL_CRC_Init() call HAL_CRCEx_Polynomial_Set() to initialize the CRC polynomial</li>
</ul></li>
-<li>Remove extra call to HAL_LOCK/HAL_UNLOCK from the followings APIs:
+<li>Remove extra call to HAL_LOCK/HAL_UNLOCK from the following APIs:
<ul>
<li>HAL_CRC_Accumulate()</li>
<li>HAL_CRC_Calculate()</li>
@@ -543,7 +670,7 @@
<li>Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
<ul>
<li>Add checks for HSI and PLL ready before modifying RCC CFGR registers</li>
-<li>Clear all interrupt falgs</li>
+<li>Clear all interrupt flags</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL USB</strong> update
@@ -566,7 +693,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_7_2" aria-hidden="true"> <label for="collapse-section1_7_2" aria-hidden="true"><strong>V1.7.2 / 09-May-2019</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>Maintenance release to fix known defects and enhancements implementation</li>
<li><strong>HAL Drivers changes</strong></li>
@@ -588,7 +715,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_7_1" aria-hidden="true"> <label for="collapse-section1_7_1" aria-hidden="true"><strong>V1.7.1 / 02-April-2019</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>The following changes done on the HAL drivers require an update on the application code based on older HAL versions</strong>
@@ -631,7 +758,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_7_0" aria-hidden="true"> <label for="collapse-section1_7_0" aria-hidden="true"><strong>V1.7.0 / 25-August-2017</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>Generic drivers changes</strong></li>
@@ -654,7 +781,7 @@
<li><strong>LL Drivers changes</strong></li>
<li><strong>LL_TIM</strong>
<ul>
-<li>Ensure write operation of BKE and BKP bits is effective by adding fake read operation to garantee 1 APB clock cycle before function exit.</li>
+<li>Ensure write operation of BKE and BKP bits is effective by adding fake read operation to guarantee 1 APB clock cycle before function exit.</li>
<li>Exchange behavior between LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent().</li>
</ul></li>
<li><strong>LL_RCC</strong>
@@ -667,7 +794,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_6_0" aria-hidden="true"> <label for="collapse-section1_6_0" aria-hidden="true"><strong>V1.6.0 / 07-April-2017</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>HAL Drivers changes</strong></li>
@@ -789,7 +916,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_0" aria-hidden="true"> <label for="collapse-section1_5_0" aria-hidden="true"><strong>V1.5.0 / 04-November-2016</strong></label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>HAL Drivers changes</strong></li>
@@ -811,7 +938,7 @@
<ul>
<li>Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</li>
<li>Remove HAL CEC receive interrupt process function HAL_CEC_Receive_IT() and enable the “receive” mode during the Init phase</li>
-<li>Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()</li>
+<li>Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize()</li>
<li>Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</li>
<li>Remove the InitiatorAddress field from the CEC_InitTypeDef structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function</li>
<li>Add new parameter RxFrameSize in HAL_CEC_RxCpltCallback() function</li>
@@ -820,7 +947,7 @@
<li>HAL TIM driver : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure</li>
<li><strong>HAL Generic</strong>
<ul>
-<li>Update HAL Driver compliancy with:
+<li>Update HAL Driver compliance with:
<ul>
<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type)</li>
<li>MISRA C 2004 rule 14.8 (the statement forming the body of a switch, while, do … while, or for statement shall be a compound statement)</li>
@@ -882,7 +1009,7 @@
<ul>
<li>Polling mode:
<ul>
-<li>Replace the use of SPI_WaitOnFlagUnitTimeout() function by “if” statement to check on RXNE/TXE flage while transferring data</li>
+<li>Replace the use of SPI_WaitOnFlagUnitTimeout() function by “if” statement to check on RXNE/TXE flag while transferring data</li>
</ul></li>
<li>Interrupt mode:</li>
<li>Minimize access on SPI registers</li>
@@ -943,11 +1070,11 @@
<li><strong>LL Drivers changes</strong></li>
<li><strong>LL GPIO</strong>
<ul>
-<li>Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F0xx serie)</li>
+<li>Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F0xx series)</li>
</ul></li>
<li><strong>LL_TIM</strong>
<ul>
-<li>Remove TIM_SMCR_OCCS compilation switch (useless for STM32F0xx serie)</li>
+<li>Remove TIM_SMCR_OCCS compilation switch (useless for STM32F0xx series)</li>
</ul></li>
<li><strong>LL_CRS</strong>
<ul>
@@ -959,7 +1086,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_4_0" aria-hidden="true"> <label for="collapse-section1_4_0" aria-hidden="true"><strong>V1.4.0 / 27-May-2016</strong></label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li><strong>First official release supporting the Low Level drivers for the STM32F0xx family:</strong>
<ul>
@@ -973,7 +1100,7 @@
<li><strong>Maintenance release to fix known defects and enhancements implementation.</strong></li>
<li><strong>HAL generic</strong>
<ul>
-<li>Updated HAL Driver compliancy with MISRA C 2004 rules:
+<li>Updated HAL Driver compliance with MISRA C 2004 rules:
<ul>
<li>MISRA C 2004 rule 5.2 (tmpreg variable shall not be used inside MACRO)</li>
<li>MISRA C 2004 rule 10.3 (illegal explicit conversion from type unsigned int to uint16_t).</li>
@@ -1091,12 +1218,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_3_1" aria-hidden="true"> <label for="collapse-section1_3_1" aria-hidden="true"><strong>V1.3.1 / 29-January-2016</strong></label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>HAL Generic</strong>
<ul>
-<li>Updated HAL Driver compliancy with:
+<li>Updated HAL Driver compliance with:
<ul>
<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type).</li>
<li>MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</li>
@@ -1209,7 +1336,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_3_0" aria-hidden="true"> <label for="collapse-section1_3_0" aria-hidden="true"><strong>V1.3.0 / 26-June-2015</strong></label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>Complete HAL API alignment (macro/function renaming)</strong></li>
@@ -1229,10 +1356,10 @@
<li>ADC_ConversionStop(): correct wrong timeout value.</li>
<li>HAL_ADC_AnalogWDGConfig(): Add missing assert param.</li>
<li>Remove channel for monitoring VBAT power supply pin on F0 Value line devices.</li>
-<li>Move sampling time setting into ADC init stucture (keep setting into ADC channel init stucture with comments of obsolete setting).</li>
+<li>Move sampling time setting into ADC init structure (keep setting into ADC channel init structure with comments of obsolete setting).</li>
<li>Move __HAL_UNLOCK() before peripheral activation because if an interruption occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be executed while HAL still locked.</li>
<li>ADC_DMAConvCplt(): Add call to ADC error callback in case of error.</li>
-<li>Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).</li>
+<li>Rename local variables for compliance with coding rules (tmpHALstatus ==> tmp_hal_status).</li>
<li>Simplify __HAL_ADC_GET_IT_SOURCE().</li>
<li>Add use of POSITION_VAL.</li>
<li>Add optimization of ADC stabilization delays.</li>
@@ -1356,7 +1483,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true"><strong>V1.2.1 / 09-January-2015</strong></label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li><strong>HAL</strong>
<ul>
@@ -1385,13 +1512,13 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true"><strong>V1.2.0 / 05-December-2014</strong></label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong>
<ul>
<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
<li>HandleTypeDef.ErrorCode must be typed uint32_t</li>
-<li>Update HAL drivers to ensure compliancy w/ C++</li>
+<li>Update HAL drivers to ensure compliance w/ C++</li>
<li>Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h</li>
<li>Case mismatch between #include typo and effective file name generating compiler errors under Linux</li>
<li>Correct various issues for documentation generation (group name, doxygen tags, etc..)</li>
@@ -1508,7 +1635,7 @@
<li><strong>ErrorCode</strong> field is now declared as uint32 instead of <strong>enum HAL_SPI_ErrorTypeDef</strong> to fix C++ compilation issue</li>
<li>Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix Unused variable warning w/ TrueSTUDIO.</li>
<li>Add DMA circular mode support on SPI HAL driver.</li>
-<li>Internal fucntion renaming: HAL_SPI_DMATransmitCplt(), HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() & HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError().</li>
+<li>Internal function renaming: HAL_SPI_DMATransmitCplt(), HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() & HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError().</li>
<li>Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype</li>
<li>uint32_t driver alignment for compatibility with other STM32 devices</li>
<li>Add new <strong>API HAL_SPI_GetError()</strong>, which was missing on STM32F0xx family</li>
@@ -1545,7 +1672,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true"><strong>V1.1.0 / 03-October-2014</strong></label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong>
<ul>
@@ -1556,11 +1683,11 @@
<li>[F098xx] Remove PVD IT line wrapper</li>
<li>FLAG&IT assert macros to be removed</li>
<li>Bad macro name in stm32F0xx_hal.c/.h files</li>
-<li>uint32_t Alignement in HAL driver</li>
+<li>uint32_t Alignment in HAL driver</li>
</ul></li>
<li><strong>HAL</strong> update (for STM32F091xC/STM32F098xx)
<ul>
-<li>Add new define for HAL IRDA Enveloppe source Selection</li>
+<li>Add new define for HAL IRDA Envelope source Selection</li>
<li>Add new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()</li>
<li>Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)</li>
<li>Add new macro __HAL_GET_PENDING_IT()</li>
@@ -1591,7 +1718,7 @@
</ul></li>
<li><strong>HAL GPIO</strong>
<ul>
-<li>BSRR regsiter should not be split in BSRRH/BSRRL</li>
+<li>BSRR register should not be split in BSRRH/BSRRL</li>
<li>rework GPIO_GET_SOURCE</li>
<li>Add new defines for AF functions selection</li>
</ul></li>
@@ -1711,7 +1838,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_0_1" aria-hidden="true"> <label for="collapse-section1_0_1" aria-hidden="true"><strong>V1.0.1 / 18-June-2014</strong></label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong> update
<ul>
@@ -1798,7 +1925,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true"><strong>V1.0.0 / 12-June-2018</strong></label>
<div>
-<h2 id="main-changes-16">Main Changes</h2>
+<h2 id="main-changes-17">Main Changes</h2>
<ul>
<li>First official release of STM32F0xx HAL drivers for <strong>STM32F030x4/x6, STM32F030x8, STM32F031x4/x6, STM32F051x4/x6/x8, STM32F071x8/xB, STM32F042x4/x6, STM32F072x8/xB, STM32F038xx, STM32F048xx, STM32F058xx and STM32F078xx devices.</strong></li>
</ul>
diff --git a/Src/Legacy/stm32f0xx_hal_can.c b/Src/Legacy/stm32f0xx_hal_can.c
index 3a730f0..c2dc082 100644
--- a/Src/Legacy/stm32f0xx_hal_can.c
+++ b/Src/Legacy/stm32f0xx_hal_can.c
@@ -86,6 +86,7 @@
(@) You can refer to the CAN Legacy HAL driver header file for more useful macros
@endverbatim
+
******************************************************************************
*/
diff --git a/Src/stm32f0xx_hal.c b/Src/stm32f0xx_hal.c
index 7addd6d..5f16772 100644
--- a/Src/stm32f0xx_hal.c
+++ b/Src/stm32f0xx_hal.c
@@ -52,11 +52,11 @@
* @{
*/
/**
- * @brief STM32F0xx HAL Driver version number V1.7.6
+ * @brief STM32F0xx HAL Driver version number
*/
#define __STM32F0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
-#define __STM32F0xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
+#define __STM32F0xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\
@@ -337,7 +337,8 @@
/**
* @brief return tick frequency.
- * @retval tick period in Hz
+ * @retval Tick frequency.
+ * Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
@@ -345,7 +346,7 @@
}
/**
- * @brief This function provides accurate delay (in milliseconds) based
+ * @brief This function provides accurate delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
@@ -510,3 +511,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f0xx_hal_adc.c b/Src/stm32f0xx_hal_adc.c
index 9a53eff..bb213ed 100644
--- a/Src/stm32f0xx_hal_adc.c
+++ b/Src/stm32f0xx_hal_adc.c
@@ -6,16 +6,8 @@
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
* + Initialization and de-initialization functions
- * ++ Initialization and Configuration of ADC
- * + Operation functions
- * ++ Start, stop, get result of conversions of regular
- * group, using 3 possible modes: polling, interruption or DMA.
- * + Control functions
- * ++ Channels configuration on regular group
- * ++ Analog Watchdog configuration
- * + State functions
- * ++ ADC state machine management
- * ++ Interrupts and flags management
+ * + Peripheral Control functions
+ * + Peripheral State functions
* Other functions (extended functions) are available in file
* "stm32f0xx_hal_adc_ex.c".
*
@@ -296,7 +288,6 @@
are set to the corresponding weak functions.
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1891,7 +1882,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes channel into regular group, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -1941,7 +1932,7 @@
/* ADC initialization structure with parameter "SamplingTimeCommon". */
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
{
- /* Modify sampling time if needed (not needed in case of reoccurrence */
+ /* Modify sampling time if needed (not needed in case of recurrence */
/* for several channels programmed consecutively into the sequencer) */
if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
{
@@ -2024,7 +2015,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes the selected analog watchdog, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -2496,3 +2487,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_adc_ex.c b/Src/stm32f0xx_hal_adc_ex.c
index 1af9b13..d0dd989 100644
--- a/Src/stm32f0xx_hal_adc_ex.c
+++ b/Src/stm32f0xx_hal_adc_ex.c
@@ -5,8 +5,7 @@
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
- * + Operation functions
- * ++ Calibration (ADC automatic self-calibration)
+ * + Peripheral Control functions
* Other functions (generic functions) are available in file
* "stm32f0xx_hal_adc.c".
*
@@ -27,7 +26,6 @@
available in file of generic functions "stm32l1xx_hal_adc.c".
[..]
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -115,8 +113,8 @@
HAL_ADC_STATE_BUSY_INTERNAL);
/* Disable ADC DMA transfer request during calibration */
- /* Note: Specificity of this STM32 serie: Calibration factor is */
- /* available in data register and also transfered by DMA. */
+ /* Note: Specificity of this STM32 series: Calibration factor is */
+ /* available in data register and also transferred by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
/* in array variable, DMA transfer must be disabled during */
/* calibration. */
@@ -188,3 +186,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_can.c b/Src/stm32f0xx_hal_can.c
index bbbbf99..5187d01 100644
--- a/Src/stm32f0xx_hal_can.c
+++ b/Src/stm32f0xx_hal_can.c
@@ -1236,15 +1236,6 @@
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
- /* Check transmit mailbox value */
- if (transmitmailbox > 2U)
- {
- /* Update error code */
- hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
-
- return HAL_ERROR;
- }
-
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
@@ -1529,7 +1520,15 @@
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
- pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
+ {
+ /* Truncate DLC to 8 if received field is over range */
+ pHeader->DLC = 8U;
+ }
+ else
+ {
+ pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ }
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
diff --git a/Src/stm32f0xx_hal_cec.c b/Src/stm32f0xx_hal_cec.c
index 706bf58..1e0a9e9 100644
--- a/Src/stm32f0xx_hal_cec.c
+++ b/Src/stm32f0xx_hal_cec.c
@@ -105,7 +105,6 @@
When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
-
@endverbatim
******************************************************************************
*/
@@ -234,7 +233,8 @@
/* Write to CEC Control Register */
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
- hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
+ hcec->Init.BroadcastMsgNoErrorBitGen | \
hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
hcec->Init.ListenMode;
@@ -413,10 +413,10 @@
* @param hcec CEC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
- * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
- * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
- * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -498,14 +498,14 @@
/**
* @brief Unregister an CEC Callback
- * CEC callabck is redirected to the weak predefined callback
+ * CEC callback is redirected to the weak predefined callback
* @param hcec uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
- * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
- * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
@@ -776,13 +776,13 @@
{
/* save interrupts register for further error or interrupts handling purposes */
- uint32_t reg;
- reg = hcec->Instance->ISR;
+ uint32_t itflag;
+ itflag = hcec->Instance->ISR;
/* ----------------------------Arbitration Lost Management----------------------------------*/
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
- if ((reg & CEC_FLAG_ARBLST) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
{
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
@@ -790,7 +790,7 @@
/* ----------------------------Rx Management----------------------------------*/
/* CEC RX byte received interrupt ---------------------------------------------------*/
- if ((reg & CEC_FLAG_RXBR) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
{
/* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
@@ -802,7 +802,7 @@
}
/* CEC RX end received interrupt ---------------------------------------------------*/
- if ((reg & CEC_FLAG_RXEND) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
{
/* clear IT */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
@@ -821,7 +821,7 @@
/* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
- if ((reg & CEC_FLAG_TXBR) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
{
--hcec->TxXferCount;
if (hcec->TxXferCount == 0U)
@@ -830,14 +830,14 @@
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* In all cases transmit the byte */
- hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr;
+ hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
hcec->pTxBuffPtr++;
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
}
/* CEC TX end interrupt ------------------------------------------------*/
- if ((reg & CEC_FLAG_TXEND) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
{
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
@@ -855,21 +855,21 @@
}
/* ----------------------------Rx/Tx Error Management----------------------------------*/
- if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
- CEC_ISR_TXACKE)) != 0U)
+ if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
+ CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
{
- hcec->ErrorCode = reg;
+ hcec->ErrorCode = itflag;
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
- if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
+ if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
{
hcec->Init.RxBuffer -= hcec->RxXferSize;
hcec->RxXferSize = 0U;
hcec->RxState = HAL_CEC_STATE_READY;
}
- else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
+ else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
{
/* Set the CEC state ready to be able to start again the process */
hcec->gState = HAL_CEC_STATE_READY;
@@ -960,7 +960,8 @@
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
{
- uint32_t temp1, temp2;
+ uint32_t temp1;
+ uint32_t temp2;
temp1 = hcec->gState;
temp2 = hcec->RxState;
diff --git a/Src/stm32f0xx_hal_comp.c b/Src/stm32f0xx_hal_comp.c
index c7088b5..e9c0eec 100644
--- a/Src/stm32f0xx_hal_comp.c
+++ b/Src/stm32f0xx_hal_comp.c
@@ -6,10 +6,9 @@
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
* + Initialization/de-initialization functions
- * + I/O operation functions
* + Peripheral Control functions
* + Peripheral State functions
- *
+ *
******************************************************************************
* @attention
*
@@ -980,3 +979,5 @@
#endif /* COMP1 || COMP2 */
#endif /* HAL_COMP_MODULE_ENABLED */
+
+
diff --git a/Src/stm32f0xx_hal_cortex.c b/Src/stm32f0xx_hal_cortex.c
index 305d633..a916c18 100644
--- a/Src/stm32f0xx_hal_cortex.c
+++ b/Src/stm32f0xx_hal_cortex.c
@@ -77,6 +77,16 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -337,3 +347,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_crc.c b/Src/stm32f0xx_hal_crc.c
index 2e196c4..2072092 100644
--- a/Src/stm32f0xx_hal_crc.c
+++ b/Src/stm32f0xx_hal_crc.c
@@ -21,9 +21,9 @@
*
******************************************************************************
@verbatim
- ==============================================================================
+ ===============================================================================
##### How to use this driver #####
- ==============================================================================
+ ===============================================================================
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
@@ -202,7 +202,7 @@
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+ __HAL_CRC_SET_IDR(hcrc, 0);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
diff --git a/Src/stm32f0xx_hal_crc_ex.c b/Src/stm32f0xx_hal_crc_ex.c
index 94fbd43..e12e13e 100644
--- a/Src/stm32f0xx_hal_crc_ex.c
+++ b/Src/stm32f0xx_hal_crc_ex.c
@@ -18,9 +18,9 @@
*
******************************************************************************
@verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
+================================================================================
+ ##### How to use this driver #####
+================================================================================
[..]
(+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@@ -95,44 +95,53 @@
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
- /* check polynomial definition vs polynomial size:
- * polynomial length must be aligned with polynomial
- * definition. HAL_ERROR is reported if Pol degree is
- * larger than that indicated by PolyLength.
- * Look for MSB position: msb will contain the degree of
- * the second to the largest polynomial member. E.g., for
- * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ /* Ensure that the generating polynomial is odd */
+ if ((Pol & (uint32_t)(0x1U)) == 0U)
{
+ status = HAL_ERROR;
}
-
- switch (PolyLength)
+ else
{
- case CRC_POLYLENGTH_7B:
- if (msb >= HAL_CRC_LENGTH_7B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_8B:
- if (msb >= HAL_CRC_LENGTH_8B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_16B:
- if (msb >= HAL_CRC_LENGTH_16B)
- {
- status = HAL_ERROR;
- }
- break;
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ {
+ }
- case CRC_POLYLENGTH_32B:
- /* no polynomial definition vs. polynomial length issue possible */
- break;
- default:
- status = HAL_ERROR;
- break;
+ switch (PolyLength)
+ {
+
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
}
if (status == HAL_OK)
{
diff --git a/Src/stm32f0xx_hal_dac.c b/Src/stm32f0xx_hal_dac.c
index 6866b3e..0eb27b0 100644
--- a/Src/stm32f0xx_hal_dac.c
+++ b/Src/stm32f0xx_hal_dac.c
@@ -6,7 +6,6 @@
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
* + Initialization and de-initialization functions
- * + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
@@ -22,7 +21,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- @verbatim
+ @verbatim
==============================================================================
##### DAC Peripheral features #####
==============================================================================
@@ -92,7 +91,7 @@
(#) 12-bit left alignment using DAC_ALIGN_12B_L
(#) 12-bit right alignment using DAC_ALIGN_12B_R
- *** DAC data value to voltage correspondance ***
+ *** DAC data value to voltage correspondence ***
================================================
[..]
The analog output voltage on each DAC channel pin is determined
@@ -229,7 +228,7 @@
[..]
(@) You can refer to the DAC HAL driver header file for more useful macros
- @endverbatim
+ @endverbatim
******************************************************************************
*/
@@ -959,7 +958,7 @@
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
@@ -1085,3 +1084,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f0xx_hal_dac_ex.c b/Src/stm32f0xx_hal_dac_ex.c
index c8d964c..f4d3a84 100644
--- a/Src/stm32f0xx_hal_dac_ex.c
+++ b/Src/stm32f0xx_hal_dac_ex.c
@@ -18,7 +18,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- @verbatim
+ @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
@@ -29,7 +29,7 @@
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
- @endverbatim
+ @endverbatim
******************************************************************************
*/
@@ -1179,3 +1179,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_dma.c b/Src/stm32f0xx_hal_dma.c
index 00bfd91..5662cb5 100644
--- a/Src/stm32f0xx_hal_dma.c
+++ b/Src/stm32f0xx_hal_dma.c
@@ -3,75 +3,74 @@
* @file stm32f0xx_hal_dma.c
* @author MCD Application Team
* @brief DMA HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ *
+ * This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary). Please refer to Reference manual for connection between peripherals
+ and DMA requests .
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ using HAL_DMA_Init() function.
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable and configure the peripheral to be connected to the DMA Channel
- (except for internal SRAM / FLASH memories: no initialization is
- necessary). Please refer to Reference manual for connection between peripherals
- and DMA requests .
-
- (#) For a given Channel, program the required configuration through the following parameters:
- Transfer Direction, Source and Destination data formats,
- Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
- using HAL_DMA_Init() function.
-
- (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
- detection.
-
- (#) Use HAL_DMA_Abort() function to abort the current transfer
-
- -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
- case a fixed Timeout can be configured by User depending from his application.
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred.
- In this case the DMA interrupt is configured
- (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e a member of DMA handle structure).
-
- *** DMA HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DMA HAL driver.
-
- [..]
- (@) You can refer to the DMA HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -110,41 +109,41 @@
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
- ===============================================================================
+ ===============================================================================
[..]
This section provides functions allowing to initialize the DMA Channel source
- and destination addresses, incrementation and data sizes, transfer direction,
+ and destination addresses, incrementation and data sizes, transfer direction,
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
[..]
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
- reference manual.
+ reference manual.
@endverbatim
* @{
*/
-
+
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
+{
uint32_t tmp = 0U;
-
+
/* Check the DMA handle allocation */
- if(NULL == hdma)
+ if (NULL == hdma)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
@@ -154,18 +153,18 @@
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
+
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Get the CR register value */
tmp = hdma->Instance->CCR;
-
+
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
-
+
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
hdma->Init.PeriphInc | hdma->Init.MemInc |
@@ -173,38 +172,38 @@
hdma->Init.Mode | hdma->Init.Priority;
/* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
- /* Initialize DmaBaseAddress and ChannelIndex parameters used
+ hdma->Instance->CCR = tmp;
+
+ /* Initialize DmaBaseAddress and ChannelIndex parameters used
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
DMA_CalcBaseAndBitshift(hdma);
-
+
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
-
+
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
-
+
return HAL_OK;
-}
-
+}
+
/**
- * @brief DeInitialize the DMA peripheral
+ * @brief DeInitialize the DMA peripheral
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
- if(NULL == hdma)
+ if (NULL == hdma)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
@@ -219,11 +218,11 @@
/* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0U;
-
+
/* Reset DMA Channel memory address register */
hdma->Instance->CMAR = 0U;
-/* Get DMA Base Address */
+ /* Get DMA Base Address */
DMA_CalcBaseAndBitshift(hdma);
/* Clear all flags */
@@ -251,20 +250,20 @@
* @}
*/
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
+ (+) Configure the source, destination address and data length and
Start DMA transfer with interrupt
(+) Abort DMA transfer
(+) Poll for transfer complete
- (+) Handle DMA interrupt request
+ (+) Handle DMA interrupt request
@endverbatim
* @{
@@ -273,7 +272,7 @@
/**
* @brief Start the DMA Transfer.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@@ -281,46 +280,46 @@
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
+
/* Process locked */
__HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
+
+ if (HAL_DMA_STATE_READY == hdma->State)
{
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- hdma->Instance->CCR |= DMA_CCR_EN;
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
- return status;
-}
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
+
+ return status;
+}
/**
* @brief Start the DMA Transfer with interrupt enabled.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@@ -328,53 +327,53 @@
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
+
/* Process locked */
__HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
+
+ if (HAL_DMA_STATE_READY == hdma->State)
{
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete, & transfer error interrupts */
- /* Half transfer interrupt is optional: enable it only if associated callback is available */
- if(NULL != hdma->XferHalfCpltCallback )
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete, & transfer error interrupts */
+ /* Half transfer interrupt is optional: enable it only if associated callback is available */
+ if (NULL != hdma->XferHalfCpltCallback)
{
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
}
- else
- {
- hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
- hdma->Instance->CCR &= ~DMA_IT_HT;
- }
-
- /* Enable the Peripheral */
- hdma->Instance->CCR |= DMA_CCR_EN;
+ else
+ {
+ hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
/* Remain BUSY */
status = HAL_BUSY;
- }
-
- return status;
-}
+ }
+
+ return status;
+}
/**
* @brief Abort the DMA Transfer.
@@ -384,33 +383,33 @@
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
- if(hdma->State != HAL_DMA_STATE_BUSY)
+ if (hdma->State != HAL_DMA_STATE_BUSY)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
+
return HAL_ERROR;
}
else
{
/* Disable DMA IT */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
+
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
-
+
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
}
/* Change the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
+ hdma->State = HAL_DMA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
+
return HAL_OK;
}
@@ -421,39 +420,39 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
+
+ if (HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
+
status = HAL_ERROR;
}
else
- {
-
+ {
+
/* Disable DMA IT */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
+
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
-
+
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
+
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
- /* Call User Abort callback */
- if(hdma->XferAbortCallback != NULL)
+
+ /* Call User Abort callback */
+ if (hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
- }
+ }
}
return status;
}
@@ -462,7 +461,7 @@
* @brief Polling for transfer complete.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CompleteLevel Specifies the DMA level complete.
+ * @param CompleteLevel Specifies the DMA level complete.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -470,24 +469,24 @@
{
uint32_t temp;
uint32_t tickstart = 0U;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
+
+ if (HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
-
+
/* Polling mode not supported in circular mode */
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
-
+
/* Get the level transfer complete flag */
- if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Transfer Complete flag */
temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
@@ -501,34 +500,34 @@
/* Get tick */
tickstart = HAL_GetTick();
- while(RESET == (hdma->DmaBaseAddress->ISR & temp))
+ while (RESET == (hdma->DmaBaseAddress->ISR & temp))
{
- if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
- {
+ if (RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
+ {
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
+
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
- hdma->State= HAL_DMA_STATE_READY;
-
+ hdma->State = HAL_DMA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
+
+ return HAL_ERROR;
+ }
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
+
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
@@ -540,23 +539,23 @@
}
}
- if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
+ if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
- /* The selected Channelx EN bit is cleared (DMA is disabled and
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
}
else
- {
+ {
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
}
-
+
/* Process unlocked */
- __HAL_UNLOCK(hdma);
+ __HAL_UNLOCK(hdma);
return HAL_OK;
}
@@ -564,141 +563,141 @@
/**
* @brief Handle DMA interrupt request.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t source_it = hdma->Instance->CCR;
-
+
/* Half Transfer Complete Interrupt management ******************************/
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
{
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the half transfer interrupt */
- hdma->Instance->CCR &= ~DMA_IT_HT;
- }
-
- /* Clear the half transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* State is updated only in Transfer Complete case */
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the half transfer interrupt */
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Clear the half transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
+
+ /* DMA peripheral state is not updated in Half Transfer */
+ /* State is updated only in Transfer Complete case */
+
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
}
-
+
/* Transfer Complete Interrupt management ***********************************/
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
{
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the transfer complete & transfer error interrupts */
- /* if the DMA mode is not CIRCULAR */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
-
- /* Clear the transfer complete flag */
- hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the transfer complete & transfer error interrupts */
+ /* if the DMA mode is not CIRCULAR */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ /* Clear the transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
}
-
+
/* Transfer Error Interrupt management ***************************************/
- else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
+ else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
{
- /* When a DMA transfer error occurs */
+ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Then, disable all DMA interrupts */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
+
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-
+
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
+
/* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
+ hdma->State = HAL_DMA_STATE_READY;
+
/* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferErrorCallback != NULL)
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL)
{
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
}
- }
-}
+ }
+}
/**
* @brief Register callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback pointer to private callback function which has pointer to
+ * @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Process locked */
__HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
+
+ if (HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = pCallback;
- break;
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = pCallback;
- break;
-
- default:
- status = HAL_ERROR;
- break;
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
}
}
else
{
status = HAL_ERROR;
- }
-
+ }
+
/* Release Lock */
__HAL_UNLOCK(hdma);
-
+
return status;
}
@@ -706,57 +705,57 @@
* @brief UnRegister callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
+ /* Process locked */
__HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
+
+ if (HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = NULL;
- break;
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ALL_CB_ID:
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
}
}
else
{
status = HAL_ERROR;
- }
-
+ }
+
/* Release Lock */
__HAL_UNLOCK(hdma);
-
+
return status;
}
@@ -765,12 +764,12 @@
*/
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DMA state
@@ -778,12 +777,12 @@
@endverbatim
* @{
- */
+ */
/**
* @brief Returns the DMA state.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
@@ -817,7 +816,7 @@
/**
* @brief Set the DMA Transfer parameters.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
@@ -825,18 +824,18 @@
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- /* Clear all flags */
+ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
-
+
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
-
+
/* Memory to Peripheral */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
+ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
-
+
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
}
@@ -845,7 +844,7 @@
{
/* Configure DMA Channel source address */
hdma->Instance->CPAR = SrcAddress;
-
+
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
@@ -854,7 +853,7 @@
/**
* @brief set the DMA base address and channel index depending on DMA instance
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
+ * the configuration information for the specified DMA Stream.
* @retval None
*/
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
@@ -867,7 +866,7 @@
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
}
- else
+ else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
@@ -893,7 +892,8 @@
/**
* @}
*/
-
- /**
+
+/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_exti.c b/Src/stm32f0xx_hal_exti.c
index 5ba4931..798a1f5 100644
--- a/Src/stm32f0xx_hal_exti.c
+++ b/Src/stm32f0xx_hal_exti.c
@@ -80,7 +80,6 @@
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -545,3 +544,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_flash.c b/Src/stm32f0xx_hal_flash.c
index 56afe48..f0f3522 100644
--- a/Src/stm32f0xx_hal_flash.c
+++ b/Src/stm32f0xx_hal_flash.c
@@ -9,17 +9,6 @@
* + Memory Control functions
* + Peripheral State functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### FLASH peripheral features #####
@@ -78,6 +67,15 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -690,3 +688,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_flash_ex.c b/Src/stm32f0xx_hal_flash_ex.c
index 99e3dc1..291877e 100644
--- a/Src/stm32f0xx_hal_flash_ex.c
+++ b/Src/stm32f0xx_hal_flash_ex.c
@@ -10,17 +10,6 @@
* + Extended I/O operation functions
* + Extended Peripheral Control functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### Flash peripheral extended features #####
@@ -37,6 +26,15 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -980,3 +978,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_gpio.c b/Src/stm32f0xx_hal_gpio.c
index 8c9fdd5..d693189 100644
--- a/Src/stm32f0xx_hal_gpio.c
+++ b/Src/stm32f0xx_hal_gpio.c
@@ -7,7 +7,7 @@
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- *
+ *
******************************************************************************
* @attention
*
@@ -249,23 +249,6 @@
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
SYSCFG->EXTICR[position >> 2u] = temp;
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- temp &= ~(iocurrent);
- if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->IMR = temp;
-
- temp = EXTI->EMR;
- temp &= ~(iocurrent);
- if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->EMR = temp;
-
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
temp &= ~(iocurrent);
@@ -282,6 +265,23 @@
temp |= iocurrent;
}
EXTI->FTSR = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->EMR;
+ temp &= ~(iocurrent);
+ if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->EMR = temp;
+
+ temp = EXTI->IMR;
+ temp &= ~(iocurrent);
+ if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->IMR = temp;
}
}
@@ -326,8 +326,8 @@
EXTI->EMR &= ~((uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
/* Configure the External Interrupt or event for the current IO */
tmp = 0x0FuL << (4u * (position & 0x03u));
@@ -441,7 +441,7 @@
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- /* get current Ouput Data Register value */
+ /* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
@@ -536,3 +536,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_i2c.c b/Src/stm32f0xx_hal_i2c.c
index 55f4c40..1c4eb10 100644
--- a/Src/stm32f0xx_hal_i2c.c
+++ b/Src/stm32f0xx_hal_i2c.c
@@ -317,7 +317,6 @@
(@) You can refer to the I2C HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -401,7 +400,16 @@
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Macro
+ * @{
+ */
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -416,6 +424,7 @@
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
@@ -436,10 +445,14 @@
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
@@ -452,7 +465,8 @@
uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
@@ -704,6 +718,8 @@
/**
* @brief Register a User I2C Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be registered
@@ -734,8 +750,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -824,14 +838,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
/**
* @brief Unregister an I2C Callback
* I2C callback is redirected to the weak predefined callback
+ * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be unregistered
@@ -854,9 +868,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
switch (CallbackID)
@@ -944,8 +955,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -968,8 +977,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -984,8 +991,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -1000,9 +1005,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
@@ -1016,8 +1018,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -1386,6 +1386,19 @@
return HAL_ERROR;
}
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@@ -1431,22 +1444,27 @@
hi2c->XferCount--;
}
+ /* Wait until AF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
@@ -1511,6 +1529,7 @@
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
@@ -1553,6 +1572,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
return HAL_ERROR;
@@ -1565,6 +1585,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
/* Wait until STOP flag is set */
@@ -1774,6 +1795,20 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_IT;
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2172,39 +2207,88 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
- if (hi2c->hdmatx != NULL)
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ if (hi2c->XferCount != 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
+ (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -2212,27 +2296,10 @@
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
}
return HAL_OK;
@@ -2346,6 +2413,7 @@
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2636,9 +2704,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2658,9 +2723,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2669,30 +2731,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2730,9 +2791,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2752,9 +2810,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2763,29 +2818,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2798,7 +2853,7 @@
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+ I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
return HAL_OK;
}
@@ -2807,6 +2862,7 @@
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2822,8 +2878,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2845,9 +2899,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2856,28 +2907,36 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
if (hi2c->hdmatx != NULL)
{
@@ -2912,12 +2971,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2925,11 +2980,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -2969,8 +3024,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2992,9 +3045,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -3003,25 +3053,35 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
if (hi2c->hdmarx != NULL)
@@ -3057,11 +3117,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3069,11 +3126,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -3316,6 +3373,10 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -3763,7 +3824,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
+ FlagStatus tmp;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3825,7 +3886,7 @@
hi2c->XferISR = I2C_Slave_ISR_IT;
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -3863,8 +3924,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
-
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -3899,7 +3959,7 @@
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA RX */
@@ -3921,7 +3981,7 @@
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA TX */
@@ -4007,7 +4067,7 @@
}
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4017,15 +4077,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
return HAL_OK;
}
else
@@ -4048,7 +4108,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
+ FlagStatus tmp;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -4110,7 +4170,7 @@
hi2c->XferISR = I2C_Slave_ISR_IT;
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4148,7 +4208,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -4291,7 +4351,7 @@
}
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4301,15 +4361,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
return HAL_OK;
}
else
@@ -4443,7 +4503,7 @@
* the configuration information for the specified I2C.
* @retval None
*/
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
@@ -4696,7 +4756,7 @@
* the configuration information for the specified I2C.
* @retval HAL state
*/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
{
/* Return I2C handle state */
return hi2c->State;
@@ -4708,7 +4768,7 @@
* the configuration information for I2C module
* @retval HAL mode
*/
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
{
return hi2c->Mode;
}
@@ -4719,7 +4779,7 @@
* the configuration information for the specified I2C.
* @retval I2C Error Code
*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
}
@@ -4883,6 +4943,143 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ if (hi2c->Memaddress == 0xFFFFFFFFU)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -5164,6 +5361,145 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ /* Enable only Error interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Prepare the new XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -5204,7 +5540,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
{
treatdmanack = 1U;
}
@@ -5216,7 +5552,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
{
treatdmanack = 1U;
}
@@ -5827,7 +6163,7 @@
if (hi2c->hdmatx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
}
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
@@ -5837,7 +6173,7 @@
if (hi2c->hdmarx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
}
}
else
@@ -5998,6 +6334,7 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
uint32_t tmppreviousstate;
/* Reset handle parameters */
@@ -6025,18 +6362,36 @@
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if a STOPF is detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
}
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
+
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
@@ -6211,6 +6566,7 @@
}
}
+
/**
* @brief DMA I2C slave transmit process complete callback.
* @param hdma DMA handle
@@ -6239,6 +6595,7 @@
}
}
+
/**
* @brief DMA I2C master receive process complete callback.
* @param hdma DMA handle
@@ -6289,6 +6646,7 @@
}
}
+
/**
* @brief DMA I2C slave receive process complete callback.
* @param hdma DMA handle
@@ -6300,7 +6658,7 @@
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
- if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+ if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Disable DMA Request */
@@ -6317,6 +6675,7 @@
}
}
+
/**
* @brief DMA I2C communication error callback.
* @param hdma DMA handle
@@ -6334,6 +6693,7 @@
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
+
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
@@ -6358,6 +6718,7 @@
I2C_TreatErrorCallback(hi2c);
}
+
/**
* @brief This function handles I2C Communication Timeout. It waits
* until a flag is no longer in the specified status.
@@ -6506,13 +6867,22 @@
}
else
{
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -6554,15 +6924,15 @@
HAL_StatusTypeDef status = HAL_OK;
uint32_t itflag = hi2c->Instance->ISR;
uint32_t error_code = 0;
+ uint32_t tickstart = Tickstart;
+ uint32_t tmp1;
+ HAL_I2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
{
- /* In case of Soft End condition, generate the STOP condition */
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
- }
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
@@ -6570,11 +6940,35 @@
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- error_code |= HAL_I2C_ERROR_TIMEOUT;
+ tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+ tmp2 = hi2c->Mode;
- status = HAL_ERROR;
+ /* In case of I2C still busy, try to regenerate a STOP manually */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+ (tmp1 != I2C_CR2_STOP) && \
+ (tmp2 != HAL_I2C_MODE_SLAVE))
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Update Tick with new reference */
+ tickstart = HAL_GetTick();
+ }
+
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+ {
+ error_code |= HAL_I2C_ERROR_TIMEOUT;
+
+ status = HAL_ERROR;
+
+ break;
+ }
+ }
}
}
}
@@ -6586,9 +6980,6 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
error_code |= HAL_I2C_ERROR_AF;
status = HAL_ERROR;
@@ -6597,7 +6988,7 @@
/* Refresh Content of Status register */
itflag = hi2c->Instance->ISR;
- /* Then verify if an additionnal errors occurs */
+ /* Then verify if an additional errors occurs */
/* Check if a Bus error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
{
@@ -6648,7 +7039,7 @@
}
return status;
- }
+}
/**
* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
@@ -6677,14 +7068,16 @@
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
/* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2,
+ MODIFY_REG(hi2c->Instance->CR2, \
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
- I2C_CR2_START | I2C_CR2_STOP)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request));
+ I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
/**
@@ -6698,8 +7091,9 @@
{
uint32_t tmpisr = 0U;
- if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Mem_ISR_DMA))
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
@@ -6707,32 +7101,6 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if (InterruptRequest == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if (InterruptRequest == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
- }
-
- if (InterruptRequest == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
- }
- else
- {
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
@@ -6745,6 +7113,12 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
@@ -6752,6 +7126,45 @@
}
}
+ else
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+ }
+
+ if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+ }
+
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
diff --git a/Src/stm32f0xx_hal_i2c_ex.c b/Src/stm32f0xx_hal_i2c_ex.c
index 3e1d528..d4c72b7 100644
--- a/Src/stm32f0xx_hal_i2c_ex.c
+++ b/Src/stm32f0xx_hal_i2c_ex.c
@@ -45,7 +45,6 @@
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_hal_i2s.c b/Src/stm32f0xx_hal_i2s.c
index 9c8d2bd..7c80598 100644
--- a/Src/stm32f0xx_hal_i2s.c
+++ b/Src/stm32f0xx_hal_i2s.c
@@ -8,7 +8,6 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
- *
******************************************************************************
* @attention
*
@@ -99,6 +98,10 @@
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+ In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
+ HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
+ In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
+ inside DR register and avoid using DeInit/Init process for the next transfer.
*** I2S HAL driver macros list ***
===================================
@@ -110,6 +113,7 @@
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+ (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
@@ -173,7 +177,7 @@
and weak (surcharged) callbacks are used.
@endverbatim
- ******************************************************************************
+
*/
/* Includes ------------------------------------------------------------------*/
@@ -193,6 +197,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -1348,35 +1353,86 @@
and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
*/
- /* Disable the I2S Tx/Rx DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Abort the I2S DMA tx Stream/Channel */
- if (hi2s->hdmatx != NULL)
+ if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
{
- /* Disable the I2S DMA tx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
{
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- errorcode = HAL_ERROR;
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+
+ /* Wait until BSY flag is Reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* Clear UDR flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Disable the I2S Tx DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
}
- /* Abort the I2S DMA rx Stream/Channel */
- if (hi2s->hdmarx != NULL)
+ else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
{
- /* Disable the I2S DMA rx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
{
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* Clear OVR flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Disable the I2S Rx DMA request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
+ else
+ {
+ /* Read DR to Flush RX Data */
+ READ_REG((hi2s->Instance)->DR);
+ }
}
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
hi2s->State = HAL_I2S_STATE_READY;
return errorcode;
@@ -1797,3 +1853,4 @@
#endif /* SPI_I2S_SUPPORT */
#endif /* HAL_I2S_MODULE_ENABLED */
+
diff --git a/Src/stm32f0xx_hal_irda.c b/Src/stm32f0xx_hal_irda.c
index adf921e..233a331 100644
--- a/Src/stm32f0xx_hal_irda.c
+++ b/Src/stm32f0xx_hal_irda.c
@@ -472,6 +472,8 @@
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -500,8 +502,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_READY)
{
@@ -586,15 +586,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
+ * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -614,9 +613,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hirda);
-
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
@@ -702,9 +698,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
@@ -814,7 +807,8 @@
* @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
@@ -918,9 +912,10 @@
*/
/**
* @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
@@ -1027,7 +1022,8 @@
* @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
@@ -1087,9 +1083,10 @@
*/
/**
* @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
@@ -1130,14 +1127,14 @@
__HAL_UNLOCK(hirda);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
- {
- /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ {
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
{
- /* Enable the IRDA Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
+ /* Enable the IRDA Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
}
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
@@ -1166,7 +1163,8 @@
* @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
@@ -1261,9 +1259,10 @@
*/
/**
* @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required
+ * to ensure proper alignment for pData.
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
@@ -1410,7 +1409,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (hirda->Init.Parity != IRDA_PARITY_NONE)
- {
+ {
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -2301,7 +2300,7 @@
* the configuration information for the specified IRDA module.
* @retval HAL state
*/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
uint32_t temp1;
@@ -2318,7 +2317,7 @@
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
}
@@ -2478,11 +2477,12 @@
}
/**
- * @brief Handle IRDA Communication Timeout.
+ * @brief Handle IRDA Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param Flag Specifies the IRDA flag to check.
- * @param Status Flag status (SET or RESET)
+ * @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
@@ -2531,7 +2531,6 @@
hirda->gState = HAL_IRDA_STATE_READY;
}
-
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
@@ -3008,3 +3007,5 @@
* @}
*/
#endif /* USART_IRDA_SUPPORT */
+
+
diff --git a/Src/stm32f0xx_hal_iwdg.c b/Src/stm32f0xx_hal_iwdg.c
index 8fec8e2..de6d579 100644
--- a/Src/stm32f0xx_hal_iwdg.c
+++ b/Src/stm32f0xx_hal_iwdg.c
@@ -97,7 +97,6 @@
the reload register
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -125,7 +124,7 @@
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds.
- LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT
+ LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
diff --git a/Src/stm32f0xx_hal_msp_template.c b/Src/stm32f0xx_hal_msp_template.c
index 167f294..7678668 100644
--- a/Src/stm32f0xx_hal_msp_template.c
+++ b/Src/stm32f0xx_hal_msp_template.c
@@ -5,7 +5,7 @@
* @brief HAL MSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
- *
+ *
******************************************************************************
* @attention
*
@@ -97,3 +97,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f0xx_hal_pcd.c b/Src/stm32f0xx_hal_pcd.c
index 9d81fcb..e82f244 100644
--- a/Src/stm32f0xx_hal_pcd.c
+++ b/Src/stm32f0xx_hal_pcd.c
@@ -37,7 +37,7 @@
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
+ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -88,8 +88,10 @@
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+#if (USE_USB_DOUBLE_BUFFER == 1U)
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/**
* @}
@@ -176,7 +178,6 @@
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
hpcd->IN_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0U;
@@ -292,7 +293,7 @@
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
@@ -396,7 +397,7 @@
/**
* @brief Unregister an USB PCD Callback
- * USB PCD callabck is redirected to the weak predefined callback
+ * USB PCD callback is redirected to the weak predefined callback
* @param hpcd USB PCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -406,7 +407,7 @@
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
@@ -1005,14 +1006,18 @@
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
+ uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+
+ if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))
+ if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
@@ -1023,19 +1028,25 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))
+ if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))
+ if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
+ if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
@@ -1057,9 +1068,11 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
+ if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
{
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
@@ -1074,10 +1087,12 @@
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
}
/* Handle LPM Interrupt */
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
+ if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
if (hpcd->LPM_State == LPM_L0)
@@ -1102,9 +1117,11 @@
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))
+ if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
@@ -1113,12 +1130,16 @@
#else
HAL_PCD_SOFCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))
+ if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+
+ return;
}
}
@@ -1386,11 +1407,6 @@
ep->maxpacket = ep_mps;
ep->type = ep_type;
- if (ep->is_in != 0U)
- {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = ep->num;
- }
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
{
@@ -1424,7 +1440,7 @@
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
- ep->num = ep_addr & EP_ADDR_MSK;
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
@@ -1454,14 +1470,7 @@
ep->is_in = 0U;
ep->num = ep_addr & EP_ADDR_MSK;
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- }
- else
- {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
@@ -1499,14 +1508,7 @@
ep->is_in = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- }
- else
- {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
@@ -1586,6 +1588,32 @@
}
/**
+ * @brief Abort an USB EP transaction.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ HAL_StatusTypeDef ret;
+ PCD_EPTypeDef *ep;
+
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ }
+
+ /* Stop Xfer */
+ ret = USB_EPStopXfer(hpcd->Instance, ep);
+
+ return ret;
+}
+
+/**
* @brief Flush an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
@@ -1671,9 +1699,16 @@
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
- uint16_t count, wIstr, wEPVal, TxByteNbre;
+ uint16_t count;
+ uint16_t wIstr;
+ uint16_t wEPVal;
+ uint16_t TxPctSize;
uint8_t epindex;
+#if (USE_USB_DOUBLE_BUFFER != 1U)
+ count = 0U;
+#endif /* USE_USB_DOUBLE_BUFFER */
+
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
{
@@ -1761,7 +1796,9 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
+ wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
@@ -1791,6 +1828,7 @@
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
@@ -1801,7 +1839,7 @@
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
@@ -1825,6 +1863,8 @@
}
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
ep->xfer_buff += count;
@@ -1840,7 +1880,7 @@
}
else
{
- (void) USB_EPStartXfer(hpcd->Instance, ep);
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
@@ -1851,18 +1891,23 @@
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- if (ep->type != EP_TYPE_BULK)
+ if (ep->type == EP_TYPE_ISOC)
{
ep->xfer_len = 0U;
- if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ if (ep->doublebuffer != 0U)
{
- PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+ {
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ }
+ else
+ {
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ }
}
- else
- {
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
- }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
@@ -1872,43 +1917,47 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
- /* Manage Bulk Single Buffer Transaction */
- if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))
{
- /* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ /* Manage Single Buffer Transaction */
+ if ((wEPVal & USB_EP_KIND) == 0U)
+ {
+ /* multi-packet on the NON control IN endpoint */
+ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len > TxByteNbre)
- {
- ep->xfer_len -= TxByteNbre;
- }
- else
- {
- ep->xfer_len = 0U;
- }
+ if (ep->xfer_len > TxPctSize)
+ {
+ ep->xfer_len -= TxPctSize;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
- /* Zero Length Packet? */
- if (ep->xfer_len == 0U)
- {
- /* TX COMPLETE */
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ /* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
+ hpcd->DataInStageCallback(hpcd, ep->num);
#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Transfer is not yet Done */
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+ }
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
- /* Transfer is not yet Done */
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
- (void)USB_EPStartXfer(hpcd->Instance, ep);
+ (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
}
- }
- /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
- else
- {
- (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
}
}
}
@@ -1918,6 +1967,7 @@
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
/**
* @brief Manage double buffer bulk out transaction from ISR
* @param hpcd PCD handle
@@ -1951,10 +2001,10 @@
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
- /* Check if Buffer1 is in blocked sate which requires to toggle */
+ /* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
@@ -1986,7 +2036,7 @@
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
@@ -2010,22 +2060,23 @@
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
uint32_t len;
- uint16_t TxByteNbre;
+ uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
/* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len > TxByteNbre)
+ if (ep->xfer_len > TxPctSize)
{
- ep->xfer_len -= TxByteNbre;
+ ep->xfer_len -= TxPctSize;
}
else
{
ep->xfer_len = 0U;
}
+
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
@@ -2041,7 +2092,7 @@
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
@@ -2049,14 +2100,14 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
@@ -2066,7 +2117,7 @@
}
else if (ep->xfer_len_db == 0U)
{
- len = TxByteNbre;
+ len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
@@ -2088,11 +2139,11 @@
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len >= TxByteNbre)
+ if (ep->xfer_len >= TxPctSize)
{
- ep->xfer_len -= TxByteNbre;
+ ep->xfer_len -= TxPctSize;
}
else
{
@@ -2115,7 +2166,7 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
@@ -2123,14 +2174,14 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
@@ -2140,7 +2191,7 @@
}
else if (ep->xfer_len_db == 0U)
{
- len = TxByteNbre;
+ len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
@@ -2164,6 +2215,7 @@
return HAL_OK;
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
diff --git a/Src/stm32f0xx_hal_pcd_ex.c b/Src/stm32f0xx_hal_pcd_ex.c
index b3b7caf..352b421 100644
--- a/Src/stm32f0xx_hal_pcd_ex.c
+++ b/Src/stm32f0xx_hal_pcd_ex.c
@@ -100,6 +100,7 @@
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
@@ -108,6 +109,7 @@
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
diff --git a/Src/stm32f0xx_hal_rcc.c b/Src/stm32f0xx_hal_rcc.c
index 79085d8..e3c7cab 100644
--- a/Src/stm32f0xx_hal_rcc.c
+++ b/Src/stm32f0xx_hal_rcc.c
@@ -8,17 +8,6 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### RCC specific features #####
@@ -57,6 +46,15 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1361,3 +1359,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_rcc_ex.c b/Src/stm32f0xx_hal_rcc_ex.c
index 3765b85..068f872 100644
--- a/Src/stm32f0xx_hal_rcc_ex.c
+++ b/Src/stm32f0xx_hal_rcc_ex.c
@@ -14,10 +14,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -959,3 +958,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_rtc.c b/Src/stm32f0xx_hal_rtc.c
index 8d58d94..f12443e 100644
--- a/Src/stm32f0xx_hal_rtc.c
+++ b/Src/stm32f0xx_hal_rtc.c
@@ -4,10 +4,10 @@
* @author MCD Application Team
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) peripheral:
+ * functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization and de-initialization functions
- * + RTC Time and Date functions
- * + RTC Alarm functions
+ * + RTC Calendar (Time and Date) configuration functions
+ * + RTC Alarm (Alarm A) configuration functions
* + Peripheral Control functions
* + Peripheral State functions
*
@@ -24,97 +24,155 @@
******************************************************************************
@verbatim
==============================================================================
- ##### How to use RTC Driver #####
- ===================================================================
- [..]
- (+) Enable the RTC domain access (see description in the section above).
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the HAL_RTC_Init() function.
+ ##### RTC and Backup Domain Operating Condition #####
+ ==============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC when
+ VDD is turned off, VBAT pin can be connected to an optional standby
+ voltage supplied by a battery or by another source.
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
- and HAL_RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned
+ off, the VBAT pin powers the following blocks:
+ (#) The RTC
+ (#) The LSE oscillator
+ (#) PC13 to PC15 I/Os, plus PA0 and PE6 I/Os (when available)
- *** Alarm configuration ***
- ===========================
- [..]
+ [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
+ the following pins are available:
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins
+ (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
+ (#) PA0 can be used as a GPIO or as the RTC_AF2 pin
+ (#) PE6 can be used as a GPIO or as the RTC_AF3 pin
+
+ [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
+ because VDD is not present), the following pins are available:
+ (#) PC14 and PC15 can be used as LSE pins only
+ (#) PC13 can be used as the RTC_AF1 pin
+ (#) PA0 can be used as the RTC_AF2 pin
+ (#) PE6 can be used as the RTC_AF3 pin
+
+ ##### Backup Domain Reset #####
+ ==================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
+ to their reset values.
+ [..] A backup domain reset is generated when one of the following events occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been powered off.
+
+ ##### Backup Domain Access #####
+ ==================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data registers
+ is protected against possible unwanted write accesses.
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() macro.
+ (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
+
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate()
+ functions.
+ (+) To manage the RTC summer or winter time change, use the following
+ functions:
+ (++) HAL_RTC_DST_Add1Hour() or HAL_RTC_DST_Sub1Hour to add or subtract
+ 1 hour from the calendar time.
+ (++) HAL_RTC_DST_SetStoreOperation() or HAL_RTC_DST_ClearStoreOperation
+ to memorize whether the time change has been performed or not.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
(+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the
- HAL_RTC_SetAlarm_IT() function.
- (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the
+ HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
##### RTC and low power modes #####
- ===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarm (Alarm A),
- RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby low power modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wake-up mode), by using the RTC alarm
- or the RTC wake-up events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
- is LSE or LSI.
+ ==================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC wakeup,
+ RTC tamper event detection and RTC timestamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+ or the RTC wakeup events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock
+ source is LSE or LSI.
*** Callback registration ***
=============================================
-
- The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
+ [..]
+ The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
-
+ [..]
Function HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
- (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) TimeStampEventCallback : RTC Timestamp Event callback.
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
(+) Tamper3EventCallback : RTC Tamper 3 Event callback.
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
- (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) TimeStampEventCallback : RTC Timestamp Event callback.
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
(+) Tamper3EventCallback : RTC Tamper 3 Event callback.
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
-
+ [..]
By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
- all callbacks are set to the corresponding weak functions :
+ all callbacks are set to the corresponding weak functions:
examples AlarmAEventCallback(), WakeUpTimerEventCallback().
- Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
- in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
- (not registered beforehand).
- If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
+ Exception done for MspInit() and MspDeInit() callbacks that are reset to the
+ legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only
+ when these callbacks are null (not registered beforehand).
+ If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
+ keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand).
+ [..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
+ Exception done MspInit()/MspDeInit() that can be registered/unregistered
+ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state.
+ Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the
+ Init/DeInit.
+ In that case first register the MspInit()/MspDeInit() user callbacks
using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
- or HAL_RTC_Init() function.
-
+ or HAL_RTC_Init() functions.
+ [..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
+ not defined, the callback registration feature is not available and all
+ callbacks are set to the corresponding weak functions.
@endverbatim
******************************************************************************
@@ -127,8 +185,8 @@
* @{
*/
-/** @addtogroup RTC
- * @brief RTC HAL module driver
+/** @defgroup RTC RTC
+ * @brief RTC HAL module driver
* @{
*/
@@ -139,15 +197,15 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
-/** @addtogroup RTC_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- *
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -168,11 +226,11 @@
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
(#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wake-up from low power modes
+ initialization, calendar update or after wakeup from low power modes
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
- RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function
implements the above software sequence (RSF clear and RSF check).
@endverbatim
@@ -180,14 +238,16 @@
*/
/**
- * @brief Initialize the RTC according to the specified parameters
- * in the RTC_InitTypeDef structure and initialize the associated handle.
- * @param hrtc RTC handle
+ * @brief Initializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
- /* Check the RTC peripheral state */
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check RTC handler validity */
if (hrtc == NULL)
{
return HAL_ERROR;
@@ -231,7 +291,7 @@
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
}
}
-#else
+#else /* USE_HAL_RTC_REGISTER_CALLBACKS */
if (hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -240,81 +300,68 @@
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ /* Check whether the calendar needs to be initialized */
+ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+
+ if (status == HAL_OK)
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ if (status == HAL_OK)
+ {
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL;
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+ }
+
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
}
else
{
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
- /* Set RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
- /* Configure the RTC PRER */
- hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
- hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
+ /* The calendar is already initialized */
+ status = HAL_OK;
}
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ return status;
}
/**
- * @brief DeInitialize the RTC peripheral.
- * @param hrtc RTC handle
- * @note This function doesn't reset the RTC Backup Data registers.
+ * @brief DeInitializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This function does not reset the RTC Backup Data registers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
-#if defined (STM32F030xC) || defined (STM32F070xB) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
- uint32_t tickstart = 0;
-#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) ||*/
+ HAL_StatusTypeDef status = HAL_ERROR;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
@@ -325,125 +372,75 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- else
+ if (status == HAL_OK)
{
- /* Reset TR, DR and CR registers */
+ /* Reset RTC registers */
hrtc->Instance->TR = 0x00000000U;
- hrtc->Instance->DR = 0x00002101U;
-
-#if defined (STM32F030xC) || defined (STM32F070xB) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
- /* Reset All CR bits except CR[2:0] */
- hrtc->Instance->CR &= 0x00000007U;
-
- tickstart = HAL_GetTick();
-
- /* Wait till WUTWF flag is set and if Time out is reached exit */
- while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
-#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) ||*/
-
- /* Reset all RTC CR register bits */
- hrtc->Instance->CR &= 0x00000000U;
-#if defined (STM32F030xC) || defined (STM32F070xB) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
- hrtc->Instance->WUTR = 0x0000FFFFU;
-#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) ||*/
- hrtc->Instance->PRER = 0x007F00FFU;
- hrtc->Instance->ALRMAR = 0x00000000U;
- hrtc->Instance->SHIFTR = 0x00000000U;
- hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
+ hrtc->Instance->CR &= 0x00000000U;
+#if defined(RTC_WAKEUP_SUPPORT)
+ hrtc->Instance->WUTR = RTC_WUTR_WUT;
+#endif /* RTC_WAKEUP_SUPPORT */
+ hrtc->Instance->PRER = (uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU);
+ hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->SHIFTR = 0x00000000U;
hrtc->Instance->ALRMASSR = 0x00000000U;
- /* Reset ISR register and exit initialization mode */
- hrtc->Instance->ISR = 0x00000000U;
-
- /* Reset Tamper and alternate functions configuration register */
- hrtc->Instance->TAFCR = 0x00000000;
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- if (hrtc->MspDeInitCallback == NULL)
+ if (status == HAL_OK)
{
- hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ /* Reset Tamper and alternate functions configuration register */
+ hrtc->Instance->TAFCR = 0x00000000U;
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hrtc->MspDeInitCallback(hrtc);
+#else /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+ hrtc->State = HAL_RTC_STATE_RESET;
}
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- hrtc->MspDeInitCallback(hrtc);
-
-#else
- /* De-Initialize RTC MSP */
- HAL_RTC_MspDeInit(hrtc);
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
- hrtc->State = HAL_RTC_STATE_RESET;
-
/* Release Lock */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
- * @brief Register a User RTC Callback
+ * @brief Registers a User RTC Callback
* To be used instead of the weak predefined callback
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
- * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
- * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices.
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -476,6 +473,7 @@
hrtc->WakeUpTimerEventCallback = pCallback;
break;
#endif /* RTC_WAKEUP_SUPPORT */
+
case HAL_RTC_TAMPER1_EVENT_CB_ID :
hrtc->Tamper1EventCallback = pCallback;
break;
@@ -488,7 +486,8 @@
case HAL_RTC_TAMPER3_EVENT_CB_ID :
hrtc->Tamper3EventCallback = pCallback;
break;
-#endif /* RTC_TAMPER3_SUPPORT */
+#endif /* RTC_TAMPER3_SUPPORT */
+
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = pCallback;
break;
@@ -534,19 +533,21 @@
}
/**
- * @brief Unregister an RTC Callback
- * RTC callabck is redirected to the weak predefined callback
- * @param hrtc RTC handle
+ * @brief Unregisters an RTC Callback
+ * RTC callback is redirected to the weak predefined callback
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
- * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
- * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
@@ -561,17 +562,19 @@
switch (CallbackID)
{
case HAL_RTC_ALARM_A_EVENT_CB_ID :
- hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
break;
case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
- hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
break;
+
#if defined(RTC_WAKEUP_SUPPORT)
case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
break;
-#endif /* RTC_WAKEUP_SUPPORT */
+#endif /* RTC_WAKEUP_SUPPORT */
+
case HAL_RTC_TAMPER1_EVENT_CB_ID :
hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
break;
@@ -579,11 +582,13 @@
case HAL_RTC_TAMPER2_EVENT_CB_ID :
hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
break;
-#if defined( RTC_TAMPER3_SUPPORT)
+
+#if defined(RTC_TAMPER3_SUPPORT)
case HAL_RTC_TAMPER3_EVENT_CB_ID :
hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
break;
#endif /* RTC_TAMPER3_SUPPORT */
+
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = HAL_RTC_MspInit;
break;
@@ -630,8 +635,9 @@
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
- * @brief Initialize the RTC MSP.
- * @param hrtc RTC handle
+ * @brief Initializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
@@ -639,14 +645,15 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitialize the RTC MSP.
- * @param hrtc RTC handle
+ * @brief DeInitializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
@@ -654,8 +661,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@@ -663,9 +670,9 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group2
- * @brief RTC Time and Date functions
- *
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ * @brief RTC Time and Date functions
+ *
@verbatim
===============================================================================
##### RTC Time and Date functions #####
@@ -678,8 +685,9 @@
*/
/**
- * @brief Set RTC current time.
- * @param hrtc RTC handle
+ * @brief Sets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime Pointer to Time structure
* @note DayLightSaving and StoreOperation interfaces are deprecated.
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions.
@@ -692,6 +700,7 @@
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg = 0U;
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -705,7 +714,7 @@
if (Format == RTC_FORMAT_BIN)
{
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
{
assert_param(IS_RTC_HOUR12(sTime->Hours));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
@@ -718,14 +727,14 @@
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
- (((uint32_t)sTime->TimeFormat) << 16U));
+ tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+ (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
}
else
{
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
{
assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
@@ -737,100 +746,79 @@
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
- tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
- ((uint32_t)(sTime->Minutes) << 8U) | \
- ((uint32_t)sTime->Seconds) | \
- ((uint32_t)(sTime->TimeFormat) << 16U));
+ tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ((uint32_t) sTime->Seconds) | \
+ ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ if (status == HAL_OK)
{
/* Set the RTC_TR register */
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
- hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
/* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+ status = RTC_ExitInitMode(hrtc);
}
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
}
/**
- * @brief Get RTC current time.
- * @param hrtc RTC handle
- * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
- * with input format (BIN or BCD), also SubSeconds field returning the
- * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
- * factor to be used for second fraction ratio computation.
+ * @brief Gets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime Pointer to Time structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
- * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
- * value in second fraction ratio with time unit following generic formula:
- * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
- * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
- * Reading RTC current time locks the values in calendar shadow registers until Current date is read
- * to ensure consistency between the time and date values.
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields
+ * returned) to convert SubSeconds value in second fraction ratio with
+ * time unit following generic formula:
+ * Second fraction ratio * time_unit =
+ * [(SecondFraction - SubSeconds) / (SecondFraction + 1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending
+ * (ie. SHFP=0) when PREDIV_S >= SS
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the
+ * values in the higher-order calendar shadow registers to ensure
+ * consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers
+ * until current date is read to ensure consistency between the time and
+ * date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- /* Get subseconds structure field from the corresponding register*/
+ /* Get subseconds value from the corresponding register */
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
/* Get SecondFraction structure field from the corresponding register field*/
@@ -840,10 +828,10 @@
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
- sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
- sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
- sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+ sTime->Seconds = (uint8_t)( tmpreg & (RTC_TR_ST | RTC_TR_SU));
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos);
/* Check the input parameters format */
if (Format == RTC_FORMAT_BIN)
@@ -858,8 +846,9 @@
}
/**
- * @brief Set RTC current date.
- * @param hrtc RTC handle
+ * @brief Sets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate Pointer to date structure
* @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
@@ -870,6 +859,7 @@
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg = 0U;
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -892,10 +882,10 @@
assert_param(IS_RTC_MONTH(sDate->Month));
assert_param(IS_RTC_DATE(sDate->Date));
- datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
- ((uint32_t)sDate->WeekDay << 13U));
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+ ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos));
}
else
{
@@ -903,77 +893,56 @@
assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
- datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
- (((uint32_t)sDate->Month) << 8U) | \
- ((uint32_t)sDate->Date) | \
- (((uint32_t)sDate->WeekDay) << 13U));
+ datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \
+ (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \
+ ((uint32_t) sDate->Date) | \
+ (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ if (status == HAL_OK)
{
/* Set the RTC_DR register */
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+ status = RTC_ExitInitMode(hrtc);
}
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
}
/**
- * @brief Get RTC current date.
- * @param hrtc RTC handle
+ * @brief Gets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate Pointer to Date structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN : Binary data format
- * @arg RTC_FORMAT_BCD : BCD data format
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
- * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the
+ * values in the higher-order calendar shadow registers to ensure
+ * consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers
+ * until current date is read to ensure consistency between the time and
+ * date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -987,24 +956,606 @@
datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
- sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
- sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
- sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
- sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
+ sDate->Date = (uint8_t) (datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos);
/* Check the input parameters format */
if (Format == RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to Binary format */
- sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
- sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
}
return HAL_OK;
}
/**
- * @brief Daylight Saving Time, adda one hour to the calendar in one
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Sets the specified RTC Alarm.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg = 0U;
+ uint32_t subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ /* Change RTC state to BUSY */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Check the data format (binary or BCD) and store the Alarm time and date
+ configuration accordingly */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t) sAlarm->AlarmMask));
+ }
+
+ /* Store the Alarm subseconds configuration */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \
+ (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Alarm A */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case interrupt mode is used, the interrupt source must be disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Subseconds register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state back to READY */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the specified RTC Alarm with Interrupt.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
+ uint32_t tmpreg = 0U;
+ uint32_t subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ /* Change RTC state to BUSY */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Check the data format (binary or BCD) and store the Alarm time and date
+ configuration accordingly */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t) sAlarm->AlarmMask));
+ }
+
+ /* Store the Alarm subseconds configuration */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \
+ (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Alarm A */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
+ do
+ {
+ count = count - 1U;
+ if (count == 0U)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U);
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Subseconds register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state back to READY */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates the specified RTC Alarm.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be:
+ * @arg RTC_ALARM_A: Alarm A
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable Alarm A */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case interrupt mode is used, the interrupt source must be disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the RTC Alarm value and masks.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be:
+ * @arg RTC_ALARM_A: Alarm A
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0U;
+ uint32_t subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint8_t) ((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos);
+ sAlarm->AlarmTime.Minutes = (uint8_t) ((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
+ sAlarm->AlarmTime.Seconds = (uint8_t) ( tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ sAlarm->AlarmTime.TimeFormat = (uint8_t) ((tmpreg & RTC_ALRMAR_PM) >> RTC_TR_PM_Pos);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint8_t) ((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t) (tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t) (tmpreg & RTC_ALARMMASK_ALL);
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles Alarm interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Clear the EXTI's line Flag for RTC Alarm */
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
+
+ /* Get the Alarm A interrupt source enable status */
+ if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
+ {
+ /* Get the pending status of the Alarm A Interrupt */
+ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
+ {
+ /* Clear the Alarm A interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Alarm A callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmAEventCallback(hrtc);
+#else
+ HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handles Alarm A Polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRAF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+ (+) Manage RTC Summer or Winter time change
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
+ hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Daylight Saving Time, adds one hour to the calendar in one
* single operation without going through the initialization procedure.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
@@ -1072,554 +1623,9 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group3
- * @brief RTC Alarm functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
- * @{
- */
-/**
- * @brief Set the specified RTC Alarm.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Alarm structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0U;
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if (Format == RTC_FORMAT_BIN)
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
-
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
-
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
-
- /* Configure the Alarm A Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the specified RTC Alarm with Interrupt.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Alarm structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the HAL_RTC_DeactivateAlarm()).
- * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0U;
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if (Format == RTC_FORMAT_BIN)
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- /* Configure the Alarm A Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate the specified RTC Alarm.
- * @param hrtc RTC handle
- * @param Alarm Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: AlarmA
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(Alarm));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Date structure
- * @param Alarm Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: AlarmA
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(Alarm));
-
- sAlarm->Alarm = RTC_ALARM_A;
-
- tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
-
- /* Fill the structure with the read parameters */
- sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
- sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
- sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
- sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
- sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
- sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
- if (Format == RTC_FORMAT_BIN)
- {
- sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
- sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
- sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Alarm interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Get the AlarmA interrupt source enable status */
- if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
- {
- /* Get the pending status of the AlarmA Interrupt */
- if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
- {
- /* AlarmA callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- hrtc->AlarmAEventCallback(hrtc);
-#else
- HAL_RTC_AlarmAEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the AlarmA interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
- }
- }
-
- /* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Alarm A callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_AlarmAEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle AlarmA Polling request.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-
- uint32_t tickstart = HAL_GetTick();
-
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group4
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Clear RSF flag */
- hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
- tickstart = HAL_GetTick();
-
- /* Wait the registers to be synchronised */
- while ((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group5
- * @brief Peripheral State functions
- *
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -1632,13 +1638,13 @@
* @{
*/
/**
- * @brief Return the RTC handle state.
- * @param hrtc RTC handle
+ * @brief Returns the RTC state.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
{
- /* Return RTC handle state */
return hrtc->State;
}
@@ -1646,6 +1652,7 @@
* @}
*/
+
/**
* @}
*/
@@ -1653,79 +1660,110 @@
/** @addtogroup RTC_Private_Functions
* @{
*/
+
/**
- * @brief Enter the RTC Initialization mode.
+ * @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Check if the Initialization mode is set */
- if ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ /* Check that Initialization mode is not already set */
+ if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U)
{
- /* Set the Initialization mode */
- hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+ /* Set INIT bit to enter Initialization mode */
+ SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ /* Wait till RTC is in INIT state and if timeout is reached exit */
+ while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR))
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+ status = HAL_ERROR;
}
}
}
- return HAL_OK;
+ return status;
}
+/**
+ * @brief Exits the RTC Initialization mode.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Clear INIT bit to exit Initialization mode */
+ CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro */
+ if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
/**
- * @brief Convert a 2 digit decimal to BCD format.
- * @param Value Byte to be converted
+ * @brief Converts a 2-digit number from decimal to BCD format.
+ * @param number decimal-formatted number (from 0 to 99) to be converted
* @retval Converted byte
*/
-uint8_t RTC_ByteToBcd2(uint8_t Value)
+uint8_t RTC_ByteToBcd2(uint8_t number)
{
uint32_t bcdhigh = 0U;
- while (Value >= 10U)
+ while (number >= 10U)
{
bcdhigh++;
- Value -= 10U;
+ number -= 10U;
}
- return ((uint8_t)(bcdhigh << 4U) | Value);
+ return ((uint8_t)(bcdhigh << 4U) | number);
}
/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value BCD value to be converted
+ * @brief Converts a 2-digit number from BCD to decimal format.
+ * @param number BCD-formatted number (from 00 to 99) to be converted
* @retval Converted word
*/
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
+uint8_t RTC_Bcd2ToByte(uint8_t number)
{
- uint32_t tmp = 0U;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
- return (tmp + (Value & (uint8_t)0x0FU));
+ uint32_t tens = 0U;
+ tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U;
+ return (uint8_t)(tens + ((uint32_t)number & 0x0FU));
}
+
/**
* @}
*/
#endif /* HAL_RTC_MODULE_ENABLED */
-
/**
* @}
*/
-
/**
* @}
*/
diff --git a/Src/stm32f0xx_hal_rtc_ex.c b/Src/stm32f0xx_hal_rtc_ex.c
index d283cbc..d030e99 100644
--- a/Src/stm32f0xx_hal_rtc_ex.c
+++ b/Src/stm32f0xx_hal_rtc_ex.c
@@ -4,10 +4,10 @@
* @author MCD Application Team
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) Extended peripheral:
- * + RTC Time Stamp functions
+ * functionalities of the Real-Time Clock (RTC) Extended peripheral:
+ * + RTC Timestamp functions
* + RTC Tamper functions
- * + RTC Wake-up functions
+ * + RTC Wakeup functions
* + Extended Control functions
* + Extended RTC features functions
*
@@ -24,50 +24,75 @@
******************************************************************************
@verbatim
==============================================================================
- ##### How to use this driver #####
+ ##### How to use this driver #####
==============================================================================
[..]
(+) Enable the RTC domain access.
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the HAL_RTC_Init() function.
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
- *** RTC Wake-up configuration ***
- ================================
- [..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
- using the HAL_RTCEx_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
- function.
- (@) Not available on F030x4/x6/x8 and F070x6
+ *** RTC Wakeup configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wakeup Clock source and Counter use the
+ HAL_RTCEx_SetWakeUpTimer() function.
+ You can also configure the RTC Wakeup timer in interrupt mode using the
+ HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (+) To read the RTC Wakeup Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ function.
+ This feature is not available on F030x4/x6/x8 nor on F070x6 Value Line
+ devices.
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
- HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
- interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
- function.
+ *** Timestamp configuration ***
+ ===============================
+ [..]
+ (+) To configure the RTC Timestamp use the HAL_RTCEx_SetTimeStamp() function.
+ You can also configure the RTC Timestamp with interrupt mode using the
+ HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC Timestamp Time and Date register, use the
+ HAL_RTCEx_GetTimeStamp() function.
+ (+) The Timestamp alternate function is mapped to RTC_AF1 (PC13).
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt
- mode using HAL_RTCEx_SetTamper_IT() function.
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger
+ Edge or Level according to the Tamper filter value (if equal to 0 Edge
+ else Level), sampling frequency, precharge or discharge and Pull-UP use
+ the HAL_RTCEx_SetTamper() function.
+ You can configure RTC Tamper in interrupt mode using HAL_RTCEx_SetTamper_IT()
+ function.
+ (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13).
+ (+) The TAMPER2 alternate function is mapped to RTC_AF2 (PA0).
+ (+) The TAMPER3 alternate function is mapped to RTC_AF3 (PE6).
+ Tamper 3 is only available on F071xB, F072xB, F078xx, F091xC, and F098xx
+ devices.
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
- function.
- (@) Not available on F030x6/x8/xC and F070x6/xB (F0xx Value Line devices)
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+ function.
+ This feature is not available on F030x6/x8/xC nor on F070x6/xB Value
+ Line devices.
+ *** Smooth Digital Calibration configuration ***
+ ================================================
+ [..]
+ (+) RTC frequency can be digitally calibrated with a resolution of about
+ 0.954 ppm with a range from -487.1 ppm to +488.5 ppm.
+ The correction of the frequency is performed using a series of small
+ adjustments (adding and/or subtracting individual RTCCLK pulses).
+ (+) The smooth digital calibration is performed during a cycle of about 2^20
+ RTCCLK pulses (or 32 seconds) when the input frequency is 32,768 Hz.
+ This cycle is maintained by a 20-bit counter clocked by RTCCLK.
+ (+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK
+ clock cycles to be masked during the 32-second cycle.
+ (+) The RTC Smooth Digital Calibration value and the corresponding calibration
+ cycle period (32s, 16s, or 8s) can be calibrated using the
+ HAL_RTCEx_SetSmoothCalib() function.
@endverbatim
******************************************************************************
@@ -80,10 +105,8 @@
* @{
*/
-
-
-/** @addtogroup RTCEx
- * @brief RTC Extended HAL module driver
+/** @defgroup RTCEx RTCEx
+ * @brief RTC Extended HAL module driver
* @{
*/
@@ -94,73 +117,88 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
- * @brief RTC TimeStamp and Tamper functions
- *
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC Timestamp and Tamper functions
+ * @brief RTC Timestamp and Tamper functions
+ *
@verbatim
===============================================================================
- ##### RTC TimeStamp and Tamper functions #####
+ ##### RTC Timestamp and Tamper functions #####
===============================================================================
- [..] This section provides functions allowing to configure TimeStamp feature
+ [..] This section provides functions allowing to configure Timestamp feature
@endverbatim
* @{
*/
/**
- * @brief Set TimeStamp.
- * @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc RTC handle
- * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * @brief Sets Timestamp.
+ * @note This API must be called before enabling the Timestamp feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is
* activated.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on
+ * the rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on
+ * the falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin.
+ * @note Although unused, parameter RTC_TimeStampPin has been kept for portability
+ * reasons.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge));
assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+ /* Prevent compilation warning due to unused argument(s) if assert_param check
+ is disabled */
+ UNUSED(RTC_TimeStampPin);
+
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state to BUSY */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
- tmpreg |= TimeStampEdge;
+ /* Configure the Timestamp TSEDGE bit */
+ tmpreg |= RTC_TimeStampEdge;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Time Stamp TSEDGE and Enable bits */
+ /* Copy the desired configuration into the CR register */
hrtc->Instance->CR = (uint32_t)tmpreg;
+ /* Clear RTC Timestamp flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ /* Clear RTC Timestamp overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Enable the Timestamp saving */
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
+ /* Change RTC state back to READY */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -170,58 +208,74 @@
}
/**
- * @brief Set TimeStamp with Interrupt.
- * @param hrtc RTC handle
- * @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * @brief Sets Timestamp with Interrupt.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This API must be called before enabling the Timestamp feature.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is
* activated.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on
+ * the rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on
+ * the falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin.
+ * @note Although unused, parameter RTC_TimeStampPin has been kept for portability
+ * reasons.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge));
assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+ /* Prevent compilation warning due to unused argument(s) if assert_param check
+ is disabled */
+ UNUSED(RTC_TimeStampPin);
+
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state to BUSY */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
- tmpreg |= TimeStampEdge;
+ /* Configure the Timestamp TSEDGE bit */
+ tmpreg |= RTC_TimeStampEdge;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Time Stamp TSEDGE and Enable bits */
+ /* Copy the desired configuration into the CR register */
hrtc->Instance->CR = (uint32_t)tmpreg;
+ /* Clear RTC Timestamp flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ /* Clear RTC Timestamp overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Enable the Timestamp saving */
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
- /* Enable IT timestamp */
+ /* Enable IT Timestamp */
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
- /* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* RTC Timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+ /* Change RTC state back to READY */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -231,8 +285,9 @@
}
/**
- * @brief Deactivate TimeStamp.
- * @param hrtc RTC handle
+ * @brief Deactivates Timestamp.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -253,7 +308,7 @@
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
- /* Configure the Time Stamp TSEDGE and Enable bits */
+ /* Configure the Timestamp TSEDGE and Enable bits */
hrtc->Instance->CR = (uint32_t)tmpreg;
/* Enable the write protection for RTC registers */
@@ -268,9 +323,9 @@
}
/**
- * @brief Get the RTC TimeStamp value.
- * @param hrtc RTC handle
-
+ * @brief Gets the RTC Timestamp value.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTimeStamp Pointer to Time structure
* @param sTimeStampDate Pointer to Date structure
* @param Format specifies the format of the entered parameters.
@@ -281,52 +336,54 @@
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
{
- uint32_t tmptime = 0U, tmpdate = 0U;
+ uint32_t tmptime = 0U;
+ uint32_t tmpdate = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- /* Get the TimeStamp time and date registers values */
+ /* Get the Timestamp time and date registers values */
tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
/* Fill the Time structure fields with the read parameters */
- sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
- sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
- sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos);
+ sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos);
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos);
sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
/* Fill the Date structure fields with the read parameters */
- sTimeStampDate->Year = 0;
- sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
- sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos);
+ sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos);
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos);
/* Check the input parameters format */
if (Format == RTC_FORMAT_BIN)
{
- /* Convert the TimeStamp structure parameters to Binary format */
- sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ /* Convert the Timestamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
/* Convert the DateTimeStamp structure parameters to Binary format */
- sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
- sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
}
- /* Clear the TIMESTAMP Flag */
+ /* Clear the Timestamp Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
return HAL_OK;
}
/**
- * @brief Set Tamper
- * @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc RTC handle
+ * @brief Sets Tamper.
+ * @note By calling this API the tamper global interrupt will be disabled.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper Pointer to Tamper Structure.
* @retval HAL status
*/
@@ -338,6 +395,7 @@
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
@@ -348,20 +406,44 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ /* Copy control register into temporary variable */
+ tmpreg = hrtc->Instance->TAFCR;
+
+ /* Enable selected tamper */
+ tmpreg |= (sTamper->Tamper);
+
+ /* Configure the tamper trigger bit (this bit is just on the right of the
+ tamper enable bit, hence the one-time right shift before updating it) */
+ if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)
{
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
+ /* Set the tamper trigger bit (case of falling edge or high level) */
+ tmpreg |= (uint32_t)(sTamper->Tamper << 1U);
+ }
+ else
+ {
+ /* Clear the tamper trigger bit (case of rising edge or low level) */
+ tmpreg &= (uint32_t)~(sTamper->Tamper << 1U);
}
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
- (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+ /* Clear remaining fields before setting them */
+ tmpreg &= ~(RTC_TAMPERFILTER_MASK | \
+ RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \
+ RTC_TAMPERPRECHARGEDURATION_MASK | \
+ RTC_TAMPER_PULLUP_MASK | \
+ RTC_TIMESTAMPONTAMPERDETECTION_MASK);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS | \
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
- (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
+ /* Set remaining parameters of desired configuration into temporary variable */
+ tmpreg |= ((uint32_t)sTamper->Filter | \
+ (uint32_t)sTamper->SamplingFrequency | \
+ (uint32_t)sTamper->PrechargeDuration | \
+ (uint32_t)sTamper->TamperPullUp | \
+ (uint32_t)sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR |= tmpreg;
+ /* Disable tamper global interrupt in case it is enabled */
+ tmpreg &= (uint32_t)~RTC_TAFCR_TAMPIE;
+
+ /* Copy desired configuration into configuration register */
+ hrtc->Instance->TAFCR = tmpreg;
hrtc->State = HAL_RTC_STATE_READY;
@@ -373,7 +455,7 @@
/**
* @brief Sets Tamper with interrupt.
- * @note By calling this API we force the tamper interrupt for all tampers.
+ * @note By calling this API the tamper global interrupt will be enabled.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sTamper Pointer to RTC Tamper.
@@ -387,6 +469,7 @@
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
@@ -397,28 +480,47 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Configure the tamper trigger */
- if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ /* Copy control register into temporary variable */
+ tmpreg = hrtc->Instance->TAFCR;
+
+ /* Enable selected tamper */
+ tmpreg |= (sTamper->Tamper);
+
+ /* Configure the tamper trigger bit (this bit is just on the right of the
+ tamper enable bit, hence the one-time right shift before updating it) */
+ if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)
{
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
+ /* Set the tamper trigger bit (case of falling edge or high level) */
+ tmpreg |= (uint32_t)(sTamper->Tamper << 1U);
+ }
+ else
+ {
+ /* Clear the tamper trigger bit (case of rising edge or low level) */
+ tmpreg &= (uint32_t)~(sTamper->Tamper << 1U);
}
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
- (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+ /* Clear remaining fields before setting them */
+ tmpreg &= ~(RTC_TAMPERFILTER_MASK | \
+ RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \
+ RTC_TAMPERPRECHARGEDURATION_MASK | \
+ RTC_TAMPER_PULLUP_MASK | \
+ RTC_TIMESTAMPONTAMPERDETECTION_MASK);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS | \
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
- (uint32_t)RTC_TAFCR_TAMPPUDIS);
+ /* Set remaining parameters of desired configuration into temporary variable */
+ tmpreg |= ((uint32_t)sTamper->Filter | \
+ (uint32_t)sTamper->SamplingFrequency | \
+ (uint32_t)sTamper->PrechargeDuration | \
+ (uint32_t)sTamper->TamperPullUp | \
+ (uint32_t)sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR |= tmpreg;
+ /* Enable global tamper interrupt */
+ tmpreg |= (uint32_t)RTC_TAFCR_TAMPIE;
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
+ /* Copy desired configuration into configuration register */
+ hrtc->Instance->TAFCR = tmpreg;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
hrtc->State = HAL_RTC_STATE_READY;
@@ -430,10 +532,16 @@
}
/**
- * @brief Deactivate Tamper.
- * @param hrtc RTC handle
+ * @brief Deactivates Tamper.
+ * @note The tamper global interrupt bit will remain unchanged.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Tamper Selected tamper pin.
- * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER_1: Tamper 1
+ * @arg RTC_TAMPER_2: Tamper 2
+ * @arg RTC_TAMPER_3: Tamper 3
+ * @note RTC_TAMPER_3 is not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
@@ -457,96 +565,99 @@
}
/**
- * @brief Handle TimeStamp interrupt request.
- * @param hrtc RTC handle
+ * @brief Handles Timestamp and Tamper interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Get the TimeStamp interrupt source enable status */
- if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
+ /* Clear the EXTI's Flag for RTC Timestamp and Tamper */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
+
+ /* Get the Timestamp interrupt source enable status */
+ if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
{
- /* Get the pending status of the TIMESTAMP Interrupt */
- if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
+ /* Get the pending status of the Timestamp Interrupt */
+ if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U)
{
- /* TIMESTAMP callback */
+ /* Timestamp callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->TimeStampEventCallback(hrtc);
#else
HAL_RTCEx_TimeStampEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the TIMESTAMP interrupt pending bit */
+ /* Clear the Timestamp interrupt pending bit after returning from callback
+ as RTC_TSTR and RTC_TSDR registers are cleared when TSF bit is reset */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
}
}
- /* Get the Tamper interrupts source enable status */
- if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ /* Get the Tamper 1 interrupt source enable status */
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U)
{
- /* Get the pending status of the Tamper1 Interrupt */
- if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
+ /* Get the pending status of the Tamper 1 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
{
- /* Tamper1 callback */
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+
+ /* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper1EventCallback(hrtc);
#else
HAL_RTCEx_Tamper1EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the Tamper1 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
}
}
- /* Get the Tamper interrupts source enable status */
- if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ /* Get the Tamper 2 interrupt source enable status */
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U)
{
- /* Get the pending status of the Tamper2 Interrupt */
- if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
+ /* Get the pending status of the Tamper 2 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
{
- /* Tamper2 callback */
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+
+ /* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper2EventCallback(hrtc);
#else
HAL_RTCEx_Tamper2EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the Tamper2 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
}
}
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
- /* Get the Tamper interrupts source enable status */
- if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+#if defined(RTC_TAMPER3_SUPPORT)
+ /* Get the Tamper 3 interrupt source enable status */
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U)
{
- /* Get the pending status of the Tamper3 Interrupt */
- if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
+ /* Get the pending status of the Tamper 3 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U)
{
- /* Tamper3 callback */
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+
+ /* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper3EventCallback(hrtc);
#else
HAL_RTCEx_Tamper3EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the Tamper3 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
}
}
-#endif
-
- /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
+#endif /* RTC_TAMPER3_SUPPORT */
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
- * @brief TimeStamp callback.
- * @param hrtc RTC handle
+ * @brief Timestamp callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
@@ -554,14 +665,15 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
*/
}
/**
* @brief Tamper 1 callback.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
@@ -569,14 +681,15 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
*/
}
/**
* @brief Tamper 2 callback.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
@@ -584,15 +697,16 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
*/
}
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Tamper 3 callback.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
@@ -600,35 +714,28 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
*/
}
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
/**
- * @brief Handle TimeStamp polling request.
- * @param hrtc RTC handle
+ * @brief Handles Timestamp polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
- while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
{
- if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
- {
- /* Clear the TIMESTAMP OverRun Flag */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
- /* Change TIMESTAMP state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
@@ -637,6 +744,17 @@
return HAL_TIMEOUT;
}
}
+
+ if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
+ {
+ /* Clear the Timestamp Overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Change Timestamp state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
}
/* Change RTC state */
@@ -646,17 +764,21 @@
}
/**
- * @brief Handle Tamper 1 Polling.
- * @param hrtc RTC handle
+ * @brief Handles Tamper 1 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
@@ -678,17 +800,21 @@
}
/**
- * @brief Handle Tamper 2 Polling.
- * @param hrtc RTC handle
+ * @brief Handles Tamper 2 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
@@ -709,10 +835,11 @@
return HAL_OK;
}
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(RTC_TAMPER3_SUPPORT)
/**
- * @brief Handle Tamper 3 Polling.
- * @param hrtc RTC handle
+ * @brief Handles Tamper 3 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
@@ -721,7 +848,7 @@
uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
@@ -741,32 +868,33 @@
return HAL_OK;
}
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
-#if defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-/** @addtogroup RTCEx_Exported_Functions_Group2
- * @brief RTC Wake-up functions
+#if defined(RTC_WAKEUP_SUPPORT)
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wakeup functions
+ * @brief RTC Wakeup functions
*
@verbatim
===============================================================================
- ##### RTC Wake-up functions #####
+ ##### RTC Wakeup functions #####
===============================================================================
- [..] This section provides functions allowing to configure Wake-up feature
+ [..] This section provides functions allowing to configure Wakeup feature
@endverbatim
* @{
*/
/**
- * @brief Set wake up timer.
- * @param hrtc RTC handle
- * @param WakeUpCounter Wake up counter
- * @param WakeUpClock Wake up clock
+ * @brief Sets wakeup timer.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter Wakeup counter
+ * @param WakeUpClock Wakeup clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -785,13 +913,13 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ /* Check RTC WUTWF flag is reset only when wakeup timer enabled*/
+ if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
{
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -808,12 +936,17 @@
}
}
+ /* Disable the Wakeup timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+ /* Clear the Wakeup flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ /* Wait till RTC WUTWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -853,15 +986,16 @@
}
/**
- * @brief Set wake up timer with interrupt.
- * @param hrtc RTC handle
- * @param WakeUpCounter Wake up counter
- * @param WakeUpClock Wake up clock
+ * @brief Sets wakeup timer with interrupt.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter Wakeup counter
+ * @param WakeUpClock Wakeup clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
- uint32_t tickstart = 0U;
+ __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
@@ -875,15 +1009,14 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ /* Check RTC WUTWF flag is reset only when wakeup timer enabled */
+ if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
{
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */
+ do
{
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ count = count - 1U;
+ if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -895,21 +1028,23 @@
return HAL_TIMEOUT;
}
- }
+ } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U);
}
- /* Disable the Wake-Up timer */
+ /* Disable the Wakeup timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
- /* Clear flag Wake-Up */
+ /* Clear the Wakeup flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
- tickstart = HAL_GetTick();
+ /* Reload the counter */
+ count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ /* Wait till RTC WUTWF flag is set and if timeout is reached exit */
+ do
{
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ count = count - 1U;
+ if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -921,10 +1056,7 @@
return HAL_TIMEOUT;
}
- }
-
- /* Configure the Wakeup Timer counter */
- hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+ } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U);
/* Clear the Wakeup Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
@@ -932,12 +1064,14 @@
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
- /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+ /* Configure the Wakeup Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+ /* RTC wakeup timer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
- /* Configure the Interrupt in the RTC_CR register */
+ /* Configure the interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
/* Enable the Wakeup Timer */
@@ -955,11 +1089,12 @@
}
/**
- * @brief Deactivate wake up timer counter.
- * @param hrtc RTC handle
+ * @brief Deactivates wakeup timer counter.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
@@ -977,9 +1112,11 @@
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+
+ /* Wait till RTC WUTWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -1007,8 +1144,9 @@
}
/**
- * @brief Get wake up timer counter.
- * @param hrtc RTC handle
+ * @brief Gets wakeup timer counter.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -1018,40 +1156,42 @@
}
/**
- * @brief Handle Wake Up Timer interrupt request.
- * @param hrtc RTC handle
+ * @brief Handles Wakeup Timer interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Get the WAKEUPTIMER interrupt source enable status */
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
+ /* Get the Wakeup timer interrupt source enable status */
if (__HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(hrtc, RTC_IT_WUT) != RESET)
{
- /* Get the pending status of the WAKEUPTIMER Interrupt */
- if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
+ /* Get the pending status of the Wakeup timer Interrupt */
+ if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
{
- /* WAKEUPTIMER callback */
+ /* Clear the Wakeup timer interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Wakeup timer callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->WakeUpTimerEventCallback(hrtc);
#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the WAKEUPTIMER interrupt pending bit */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
}
- /* Clear the EXTI's line Flag for RTC WakeUpTimer */
- __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
- * @brief Wake Up Timer callback.
- * @param hrtc RTC handle
+ * @brief Wakeup Timer callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1059,36 +1199,38 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
*/
}
-
/**
- * @brief Handle Wake Up Timer Polling.
- * @param hrtc RTC handle
+ * @brief Handles Wakeup Timer Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
return HAL_TIMEOUT;
}
}
}
- /* Clear the WAKEUPTIMER Flag */
+ /* Clear the Wakeup timer Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
/* Change RTC state */
@@ -1100,9 +1242,9 @@
/**
* @}
*/
-#endif /* defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) | defined(STM32F030xC) */
+#endif /* RTC_WAKEUP_SUPPORT */
-/** @addtogroup RTCEx_Exported_Functions_Group3
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
@@ -1113,8 +1255,6 @@
This subsection provides functions allowing to
(+) Write a data in a specified RTC Backup data register
(+) Read a data in a specified RTC Backup data register
- (+) Set the Coarse calibration parameters.
- (+) Deactivate the Coarse calibration parameters
(+) Set the Smooth calibration parameters.
(+) Configure the Synchronization Shift Control Settings.
(+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
@@ -1128,13 +1268,14 @@
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if defined(RTC_BACKUP_SUPPORT)
/**
- * @brief Write a data in a specified RTC Backup data register.
- * @param hrtc RTC handle
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
- * specify the register.
+ * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 4)
+ * to specify the register.
* @param Data Data to be written in the specified RTC Backup data register.
* @retval None
*/
@@ -1154,10 +1295,11 @@
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
- * specify the register.
+ * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 4)
+ * to specify the register.
* @retval Read value
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
@@ -1173,13 +1315,14 @@
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* RTC_BACKUP_SUPPORT */
/**
- * @brief Set the Smooth calibration parameters.
- * @param hrtc RTC handle
+ * @brief Sets the Smooth calibration parameters.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param SmoothCalibPeriod Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values :
+ * This parameter can be can be one of the following values:
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
@@ -1191,7 +1334,7 @@
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
- * SmoothCalibMinusPulsesValue mut be equal to 0.
+ * SmoothCalibMinusPulsesValue must be equal to 0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
@@ -1212,12 +1355,13 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* check if a calibration is pending*/
- if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
{
+ /* Get tick */
tickstart = HAL_GetTick();
/* check if a calibration is pending*/
- while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -1236,7 +1380,9 @@
}
/* Configure the Smooth calibration settings */
- hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | \
+ (uint32_t)SmoothCalibPlusPulses | \
+ (uint32_t)SmoothCalibMinusPulsesValue);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1251,11 +1397,12 @@
}
/**
- * @brief Configure the Synchronization Shift Control Settings.
+ * @brief Configures the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param ShiftAdd1S Select to add or not 1 second to the time calendar.
- * This parameter can be one of the following values :
+ * This parameter can be one of the following values:
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
* @arg RTC_SHIFTADD1S_RESET: No effect.
* @param ShiftSubFS Select the number of Second Fractions to substitute.
@@ -1278,10 +1425,11 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait until the shift is completed*/
- while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+ /* Wait until the shift is completed */
+ while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -1298,13 +1446,13 @@
}
/* Check if the reference clock detection is disabled */
- if ((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+ if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
{
/* Configure the Shift settings */
hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
{
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
@@ -1347,9 +1495,10 @@
}
/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc RTC handle
- * @param CalibOutput Select the Calibration output Selection .
+ * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param CalibOutput Select the Calibration output Selection.
* This parameter can be one of the following values:
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
@@ -1389,8 +1538,9 @@
}
/**
- * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc RTC handle
+ * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
@@ -1418,12 +1568,15 @@
}
/**
- * @brief Enable the RTC reference clock detection.
- * @param hrtc RTC handle
+ * @brief Enables the RTC reference clock detection.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
{
+ HAL_StatusTypeDef status;
+
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1432,47 +1585,42 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+
+ if (status == HAL_OK)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
+ /* Enable the reference clock detection */
__HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
{
+ HAL_StatusTypeDef status;
+
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1481,43 +1629,36 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+
+ if (status == HAL_OK)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
+ /* Disable the reference clock detection */
__HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
/**
- * @brief Enable the Bypass Shadow feature.
- * @param hrtc RTC handle
+ * @brief Enables the Bypass Shadow feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1548,8 +1689,9 @@
}
/**
- * @brief Disable the Bypass Shadow feature.
- * @param hrtc RTC handle
+ * @brief Disables the Bypass Shadow feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1565,7 +1707,7 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Reset the BYPSHAD bit */
- hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
+ hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1588,7 +1730,6 @@
*/
#endif /* HAL_RTC_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/Src/stm32f0xx_hal_smartcard.c b/Src/stm32f0xx_hal_smartcard.c
index a3a04ec..77d2470 100644
--- a/Src/stm32f0xx_hal_smartcard.c
+++ b/Src/stm32f0xx_hal_smartcard.c
@@ -175,7 +175,8 @@
@endverbatim
******************************************************************************
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) \
+ && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -198,7 +199,7 @@
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+ USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
@@ -461,6 +462,9 @@
/**
* @brief Register a User SMARTCARD Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -488,8 +492,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmartcard);
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
@@ -568,15 +570,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
/**
* @brief Unregister an SMARTCARD callback
* SMARTCARD callback is redirected to the weak predefined callback
+ * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -595,9 +597,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmartcard);
-
if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
{
switch (CallbackID)
@@ -676,9 +675,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -2162,7 +2158,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle state
*/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
uint32_t temp1;
@@ -2179,7 +2175,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle Error Code
*/
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard)
{
return hsmartcard->ErrorCode;
}
@@ -2930,4 +2926,4 @@
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* !STM32F030x6 && !STM32F030x8 && !STM32F070x6 && !STM32F070xB && !STM32F030xC */
diff --git a/Src/stm32f0xx_hal_smartcard_ex.c b/Src/stm32f0xx_hal_smartcard_ex.c
index fbeb430..b30f164 100644
--- a/Src/stm32f0xx_hal_smartcard_ex.c
+++ b/Src/stm32f0xx_hal_smartcard_ex.c
@@ -32,7 +32,8 @@
@endverbatim
******************************************************************************
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) \
+ && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -194,4 +195,4 @@
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* !STM32F030x6 && !STM32F030x8 && !STM32F070x6 && !STM32F070xB && !STM32F030xC */
diff --git a/Src/stm32f0xx_hal_smbus.c b/Src/stm32f0xx_hal_smbus.c
index 91837df..bca284c 100644
--- a/Src/stm32f0xx_hal_smbus.c
+++ b/Src/stm32f0xx_hal_smbus.c
@@ -167,7 +167,6 @@
(@) You can refer to the SMBUS HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -585,6 +584,9 @@
/**
* @brief Register a User SMBUS Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be registered
@@ -614,9 +616,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -692,14 +691,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
/**
* @brief Unregister an SMBUS Callback
* SMBUS callback is redirected to the weak predefined callback
+ * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be unregistered
@@ -720,9 +720,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -798,8 +795,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -823,8 +818,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
@@ -839,8 +832,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -855,9 +846,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
@@ -871,8 +859,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -1827,7 +1813,7 @@
* the configuration information for the specified SMBUS.
* @retval HAL state
*/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus)
{
/* Return SMBUS handle state */
return hsmbus->State;
@@ -1839,7 +1825,7 @@
* the configuration information for the specified SMBUS.
* @retval SMBUS Error Code
*/
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus)
{
return hsmbus->ErrorCode;
}
diff --git a/Src/stm32f0xx_hal_spi.c b/Src/stm32f0xx_hal_spi.c
index a1bd078..ccf21ba 100644
--- a/Src/stm32f0xx_hal_spi.c
+++ b/Src/stm32f0xx_hal_spi.c
@@ -9,7 +9,6 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
- *
******************************************************************************
* @attention
*
@@ -195,7 +194,6 @@
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -994,7 +992,7 @@
{
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
@@ -1246,7 +1244,7 @@
__IO uint32_t tmpreg = 0U;
uint32_t spi_cr1;
uint32_t spi_cr2;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
@@ -1498,7 +1496,15 @@
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
-
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
+
error :
__HAL_UNLOCK(hspi);
return errorcode;
@@ -3048,7 +3054,7 @@
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
@@ -3165,7 +3171,7 @@
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
@@ -3542,7 +3548,7 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
@@ -3662,7 +3668,7 @@
/* Read 16bit CRC to flush Data Register */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -3717,7 +3723,7 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
@@ -3934,7 +3940,7 @@
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
- if(count == 0U)
+ if (count == 0U)
{
tmp_timeout = 0U;
}
@@ -3961,7 +3967,7 @@
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Adjust Timeout value in case of end of transfer */
@@ -4016,10 +4022,10 @@
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
- if(count == 0U)
+ if (count == 0U)
{
tmp_timeout = 0U;
- }
+ }
count--;
}
}
@@ -4409,3 +4415,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_tim.c b/Src/stm32f0xx_hal_tim.c
index 955a8d4..3815770 100644
--- a/Src/stm32f0xx_hal_tim.c
+++ b/Src/stm32f0xx_hal_tim.c
@@ -275,6 +275,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -536,7 +537,7 @@
}
else if (htim->State == HAL_TIM_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -658,6 +659,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -1059,7 +1061,7 @@
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1322,6 +1324,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -1723,7 +1726,7 @@
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1985,6 +1988,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -2378,7 +2382,7 @@
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -2634,6 +2638,7 @@
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -3011,7 +3016,7 @@
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;
@@ -3037,6 +3042,7 @@
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
if (htim->State == HAL_TIM_STATE_RESET)
{
@@ -3546,7 +3552,7 @@
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData1 == NULL) && (Length > 0U))
+ if ((pData1 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -3571,7 +3577,7 @@
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData2 == NULL) && (Length > 0U))
+ if ((pData2 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -3600,7 +3606,7 @@
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -4472,13 +4478,11 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status;
- if (status == HAL_OK)
- {
- status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
- }
+ status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
return status;
@@ -4811,13 +4815,11 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status;
- if (status == HAL_OK)
- {
- status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
- }
+ status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
return status;
}
@@ -5192,8 +5194,8 @@
{
/* Clear the OCREF clear selection bit */
CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+ break;
}
- break;
case TIM_CLEARINPUTSOURCE_ETR:
{
@@ -5847,8 +5849,6 @@
{
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(htim);
if (htim->State == HAL_TIM_STATE_READY)
{
@@ -6040,9 +6040,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
@@ -6085,9 +6082,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(htim);
-
if (htim->State == HAL_TIM_STATE_READY)
{
switch (CallbackID)
@@ -6319,9 +6313,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
diff --git a/Src/stm32f0xx_hal_tim_ex.c b/Src/stm32f0xx_hal_tim_ex.c
index 0092ab8..a1464e1 100644
--- a/Src/stm32f0xx_hal_tim_ex.c
+++ b/Src/stm32f0xx_hal_tim_ex.c
@@ -152,6 +152,7 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -502,7 +503,7 @@
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -883,7 +884,7 @@
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1365,7 +1366,7 @@
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -2077,11 +2078,12 @@
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
{
- __HAL_LOCK(htim);
/* Check parameters */
assert_param(IS_TIM_REMAP(htim->Instance, Remap));
+ __HAL_LOCK(htim);
+
/* Set the Timer remapping configuration */
WRITE_REG(htim->Instance->OR, Remap);
@@ -2212,7 +2214,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
diff --git a/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c b/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c
index 7fe9c8b..a17df59 100644
--- a/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c
@@ -5,10 +5,10 @@
*
* This file override the native HAL time base functions (defined as weak)
* to use the RTC ALARM for time base generation:
- * + Intializes the RTC peripheral to increment the seconds registers each 1ms
+ * + Initializes the RTC peripheral to increment the seconds registers each 1ms
* + The alarm is configured to assert an interrupt when the RTC reaches 1ms
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
- * + HSE (default), LSE or LSI can be selected as RTC clock source
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
*
******************************************************************************
* @attention
@@ -315,3 +315,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c
index 13236a1..f4218d0 100644
--- a/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c
@@ -5,7 +5,7 @@
*
* This file overrides the native HAL time base functions (defined as weak)
* to use the RTC WAKEUP for the time base generation:
- * + Intializes the RTC peripheral and configures the wakeup timer to be
+ * + Initializes the RTC peripheral and configures the wakeup timer to be
* incremented each 1ms
* + The wakeup feature is configured to assert an interrupt each 1ms
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
@@ -22,7 +22,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- @verbatim
+ @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
@@ -292,3 +292,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f0xx_hal_timebase_tim_template.c b/Src/stm32f0xx_hal_timebase_tim_template.c
index 49a1800..d86a8fd 100644
--- a/Src/stm32f0xx_hal_timebase_tim_template.c
+++ b/Src/stm32f0xx_hal_timebase_tim_template.c
@@ -5,7 +5,7 @@
*
* This file override the native HAL time base functions (defined as weak)
* the TIM time base:
- * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
+ * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
******************************************************************************
@@ -174,3 +174,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f0xx_hal_tsc.c b/Src/stm32f0xx_hal_tsc.c
index dbb8187..41051c0 100644
--- a/Src/stm32f0xx_hal_tsc.c
+++ b/Src/stm32f0xx_hal_tsc.c
@@ -143,6 +143,7 @@
@endverbatim
******************************************************************************
+
*/
/* Includes ------------------------------------------------------------------*/
@@ -773,7 +774,7 @@
* @param gx_index Index of the group
* @retval Group status
*/
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index)
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
@@ -790,7 +791,7 @@
* @param gx_index Index of the group
* @retval Acquisition measure
*/
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index)
+uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
@@ -825,7 +826,7 @@
* @param config Pointer to the configuration structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
diff --git a/Src/stm32f0xx_hal_uart.c b/Src/stm32f0xx_hal_uart.c
index f8563c2..2322cd6 100644
--- a/Src/stm32f0xx_hal_uart.c
+++ b/Src/stm32f0xx_hal_uart.c
@@ -9,6 +9,7 @@
* + IO operation functions
* + Peripheral Control functions
*
+ *
******************************************************************************
* @attention
*
@@ -176,7 +177,7 @@
USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE |\
- USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+ USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
@@ -697,6 +698,7 @@
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -737,6 +739,9 @@
/**
* @brief Register a User UART Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -766,8 +771,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_READY)
{
switch (CallbackID)
@@ -854,14 +857,15 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
/**
* @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback
+ * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -882,8 +886,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- __HAL_LOCK(huart);
-
if (HAL_UART_STATE_READY == huart->gState)
{
switch (CallbackID)
@@ -971,8 +973,6 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -1149,10 +1149,10 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
@@ -1174,8 +1174,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
@@ -1189,7 +1187,7 @@
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
- pdata16bits = (uint16_t *) pData;
+ pdata16bits = (const uint16_t *) pData;
}
else
{
@@ -1197,12 +1195,13 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
+
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1220,6 +1219,8 @@
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
@@ -1276,8 +1277,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1304,13 +1303,13 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->RxState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1352,7 +1351,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
@@ -1373,8 +1372,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1393,8 +1390,6 @@
huart->TxISR = UART_TxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
@@ -1442,8 +1437,6 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1477,7 +1470,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
@@ -1498,8 +1491,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1527,8 +1518,6 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY;
@@ -1538,8 +1527,6 @@
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
- __HAL_UNLOCK(huart);
-
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
@@ -1590,8 +1577,6 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1620,8 +1605,6 @@
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
- __HAL_LOCK(huart);
-
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX))
{
@@ -1639,8 +1622,6 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1651,8 +1632,6 @@
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
@@ -1665,7 +1644,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (huart->Init.Parity != UART_PARITY_NONE)
- {
+ {
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -1674,8 +1653,6 @@
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1771,9 +1748,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1796,9 +1774,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1859,9 +1838,10 @@
/* Disable TXEIE and TCIE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1918,9 +1898,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -2018,7 +1999,7 @@
}
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
@@ -2042,9 +2023,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2124,9 +2106,10 @@
/* Disable interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
@@ -2215,9 +2198,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2394,9 +2378,10 @@
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
@@ -2498,6 +2483,11 @@
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
}
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
@@ -2531,6 +2521,11 @@
huart->RxISR = NULL;
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
@@ -3270,6 +3265,13 @@
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
+ /* Disable TXE interrupt for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
/* Timeout occurred */
return HAL_TIMEOUT;
}
@@ -3281,6 +3283,15 @@
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->RxState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
/* Timeout occurred */
return HAL_TIMEOUT;
}
@@ -3290,6 +3301,7 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -3317,33 +3329,39 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
- interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- __HAL_UNLOCK(huart);
return HAL_TIMEOUT;
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
{
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+ {
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_ERROR;
+ }
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
- interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO;
/* Process Unlocked */
@@ -3394,11 +3412,9 @@
huart->RxISR = UART_RxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
- {
+ {
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
@@ -3447,15 +3463,12 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->RxState to ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR;
}
}
- __HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
@@ -3599,6 +3612,10 @@
}
}
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3633,6 +3650,10 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Half Transfer */
+ huart->RxEventType = HAL_UART_RXEVENT_HT;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3920,7 +3941,7 @@
*/
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@@ -3935,7 +3956,7 @@
}
else
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4002,6 +4023,9 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
@@ -4024,6 +4048,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4088,6 +4113,9 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
@@ -4110,6 +4138,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4151,3 +4180,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_uart_ex.c b/Src/stm32f0xx_hal_uart_ex.c
index 4f94e75..5ab7e7e 100644
--- a/Src/stm32f0xx_hal_uart_ex.c
+++ b/Src/stm32f0xx_hal_uart_ex.c
@@ -8,6 +8,7 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
+ *
******************************************************************************
* @attention
*
@@ -519,11 +520,10 @@
}
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
@@ -547,8 +547,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* Initialize output number of received elements */
*RxLen = 0U;
@@ -565,6 +563,7 @@
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U)
{
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
@@ -656,10 +655,9 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_IT(huart, pData, Size);
@@ -734,10 +732,9 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_DMA(huart, pData, Size);
@@ -768,6 +765,36 @@
}
/**
+ * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+ * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+ * of reception process is provided to application through calls of Rx Event callback (either default one
+ * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+ * to Rx Event callback execution.
+ * @note This function is expected to be called within the user implementation of Rx Event Callback,
+ * in order to provide the accurate value :
+ * In Interrupt Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one)
+ * In DMA Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one).
+ * In DMA mode, RxEvent callback could be called several times;
+ * When DMA is configured in Normal Mode, HT event does not stop Reception process;
+ * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+ * @param huart UART handle.
+ * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+ */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+{
+ /* Return Rx Event type value, as stored in UART handle */
+ return (huart->RxEventType);
+}
+
+/**
* @}
*/
@@ -811,3 +838,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_usart.c b/Src/stm32f0xx_hal_usart.c
index 318153f..cbea4cb 100644
--- a/Src/stm32f0xx_hal_usart.c
+++ b/Src/stm32f0xx_hal_usart.c
@@ -127,6 +127,7 @@
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
*/
@@ -418,6 +419,8 @@
/**
* @brief Register a User USART Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+ * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -445,8 +448,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(husart);
if (husart->State == HAL_USART_STATE_READY)
{
@@ -528,15 +529,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(husart);
-
return status;
}
/**
* @brief Unregister an USART Callback
* USART callaback is redirected to the weak predefined callback
+ * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+ * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -555,9 +555,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(husart);
-
if (HAL_USART_STATE_READY == husart->State)
{
switch (CallbackID)
@@ -638,9 +635,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(husart);
-
return status;
}
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -746,7 +740,8 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+ uint32_t Timeout)
{
const uint8_t *ptxdata8bits;
const uint16_t *ptxdata16bits;
@@ -851,9 +846,10 @@
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pRxData.
* @param husart USART handle.
* @param pRxData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
@@ -970,9 +966,10 @@
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
- * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
+ * (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pTxData and pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
@@ -1134,9 +1131,10 @@
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
- * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier
+ * (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pTxData.
* @param husart USART handle.
* @param pTxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent.
@@ -1212,9 +1210,10 @@
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pRxData.
* @param husart USART handle.
* @param pRxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received.
@@ -1273,7 +1272,7 @@
/* Enable the USART Parity Error and Data Register not empty Interrupts */
if (husart->Init.Parity != USART_PARITY_NONE)
- {
+ {
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
@@ -1304,9 +1303,10 @@
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
- * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
+ * (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pTxData and pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
@@ -1371,7 +1371,7 @@
/* Enable the USART Parity Error and USART Data Register not empty Interrupts */
if (husart->Init.Parity != USART_PARITY_NONE)
- {
+ {
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
@@ -1839,7 +1839,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (husart->Init.Parity != USART_PARITY_NONE)
- {
+ {
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1931,9 +1931,10 @@
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the USART DMA Tx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1956,9 +1957,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -2053,7 +2055,7 @@
}
}
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
@@ -2077,9 +2079,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2236,9 +2239,10 @@
Disable Interrupts, and disable DMA requests, if ongoing */
USART_EndTransfer(husart);
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
/* Abort the USART DMA Tx channel */
@@ -2461,7 +2465,7 @@
* the configuration information for the specified USART.
* @retval USART handle state
*/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart)
{
return husart->State;
}
@@ -2472,7 +2476,7 @@
* the configuration information for the specified USART.
* @retval USART handle Error Code
*/
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
{
return husart->ErrorCode;
}
@@ -3284,3 +3288,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_usart_ex.c b/Src/stm32f0xx_hal_usart_ex.c
index 0721b7b..a589f65 100644
--- a/Src/stm32f0xx_hal_usart_ex.c
+++ b/Src/stm32f0xx_hal_usart_ex.c
@@ -134,3 +134,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f0xx_hal_wwdg.c b/Src/stm32f0xx_hal_wwdg.c
index 2ae45f6..9d8f76b 100644
--- a/Src/stm32f0xx_hal_wwdg.c
+++ b/Src/stm32f0xx_hal_wwdg.c
@@ -7,7 +7,6 @@
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and Configuration functions
* + IO operation functions
- *
******************************************************************************
* @attention
*
@@ -52,7 +51,7 @@
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) at 48MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 85.3µs
+ max timeout before reset: approximately 85.3us
(++) Counter max (T[5;0] = 0x3F) at 48MHz (PCLK1) with prescaler
dividing by 8:
max timeout before reset: approximately 43.7ms
@@ -67,7 +66,7 @@
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Configure the WWDG prescaler, refresh window value, counter value and early
interrupt status using HAL_WWDG_Init() function. This will automatically
- enable WWDG and start its downcounter. Time reference can be taken from
+ enable WWDG and start its downcounter. Time reference can be taken from
function exit. Care must be taken to provide a counter value
greater than 0x40 to prevent generation of immediate reset.
(+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
diff --git a/Src/stm32f0xx_ll_adc.c b/Src/stm32f0xx_ll_adc.c
index 43f3ed5..3c59b5f 100644
--- a/Src/stm32f0xx_ll_adc.c
+++ b/Src/stm32f0xx_ll_adc.c
@@ -328,7 +328,7 @@
/* ADC instance is in an unknown state */
/* Need to performing a hard reset of ADC instance, using high level */
/* clock source RCC ADC reset. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
status = ERROR;
@@ -492,7 +492,7 @@
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* - Set ADC group regular overrun behavior */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
MODIFY_REG(ADCx->CFGR1,
ADC_CFGR1_EXTSEL
@@ -529,7 +529,7 @@
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
@@ -557,3 +557,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_comp.c b/Src/stm32f0xx_ll_comp.c
index e16f003..c4d096f 100644
--- a/Src/stm32f0xx_ll_comp.c
+++ b/Src/stm32f0xx_ll_comp.c
@@ -56,7 +56,7 @@
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
)
-/* Note: On this STM32 serie, comparator input plus parameters are */
+/* Note: On this STM32 series, comparator input plus parameters are */
/* the different depending on COMP instances. */
#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
(((__COMP_INSTANCE__) == COMP1) \
@@ -70,7 +70,7 @@
) \
)
-/* Note: On this STM32 serie, comparator input minus parameters are */
+/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
@@ -311,3 +311,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_dac.c b/Src/stm32f0xx_ll_dac.c
index 4be3158..5214744 100644
--- a/Src/stm32f0xx_ll_dac.c
+++ b/Src/stm32f0xx_ll_dac.c
@@ -158,7 +158,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -271,3 +271,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_dma.c b/Src/stm32f0xx_ll_dma.c
index 7fc9b65..154915f 100644
--- a/Src/stm32f0xx_ll_dma.c
+++ b/Src/stm32f0xx_ll_dma.c
@@ -9,8 +9,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -192,72 +192,72 @@
/* Check the DMA Instance DMAx and Channel parameters*/
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
- tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+ tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
- /* Disable the selected DMAx_Channely */
- CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+ /* Disable the selected DMAx_Channely */
+ CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
- /* Reset DMAx_Channely control register */
- LL_DMA_WriteReg(tmp, CCR, 0U);
+ /* Reset DMAx_Channely control register */
+ LL_DMA_WriteReg(tmp, CCR, 0U);
- /* Reset DMAx_Channely remaining bytes register */
- LL_DMA_WriteReg(tmp, CNDTR, 0U);
+ /* Reset DMAx_Channely remaining bytes register */
+ LL_DMA_WriteReg(tmp, CNDTR, 0U);
- /* Reset DMAx_Channely peripheral address register */
- LL_DMA_WriteReg(tmp, CPAR, 0U);
+ /* Reset DMAx_Channely peripheral address register */
+ LL_DMA_WriteReg(tmp, CPAR, 0U);
- /* Reset DMAx_Channely memory address register */
- LL_DMA_WriteReg(tmp, CMAR, 0U);
+ /* Reset DMAx_Channely memory address register */
+ LL_DMA_WriteReg(tmp, CMAR, 0U);
#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
- /* Reset Request register field for DMAx Channel */
- LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
+ /* Reset Request register field for DMAx Channel */
+ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
#endif
- if (Channel == LL_DMA_CHANNEL_1)
- {
- /* Reset interrupt pending bits for DMAx Channel1 */
- LL_DMA_ClearFlag_GI1(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_2)
- {
- /* Reset interrupt pending bits for DMAx Channel2 */
- LL_DMA_ClearFlag_GI2(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_3)
- {
- /* Reset interrupt pending bits for DMAx Channel3 */
- LL_DMA_ClearFlag_GI3(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_4)
- {
- /* Reset interrupt pending bits for DMAx Channel4 */
- LL_DMA_ClearFlag_GI4(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_5)
- {
- /* Reset interrupt pending bits for DMAx Channel5 */
- LL_DMA_ClearFlag_GI5(DMAx);
- }
+ if (Channel == LL_DMA_CHANNEL_1)
+ {
+ /* Reset interrupt pending bits for DMAx Channel1 */
+ LL_DMA_ClearFlag_GI1(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_2)
+ {
+ /* Reset interrupt pending bits for DMAx Channel2 */
+ LL_DMA_ClearFlag_GI2(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_3)
+ {
+ /* Reset interrupt pending bits for DMAx Channel3 */
+ LL_DMA_ClearFlag_GI3(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_4)
+ {
+ /* Reset interrupt pending bits for DMAx Channel4 */
+ LL_DMA_ClearFlag_GI4(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_5)
+ {
+ /* Reset interrupt pending bits for DMAx Channel5 */
+ LL_DMA_ClearFlag_GI5(DMAx);
+ }
#if defined(DMA1_Channel6)
- else if (Channel == LL_DMA_CHANNEL_6)
- {
- /* Reset interrupt pending bits for DMAx Channel6 */
- LL_DMA_ClearFlag_GI6(DMAx);
- }
+ else if (Channel == LL_DMA_CHANNEL_6)
+ {
+ /* Reset interrupt pending bits for DMAx Channel6 */
+ LL_DMA_ClearFlag_GI6(DMAx);
+ }
#endif
#if defined(DMA1_Channel7)
- else if (Channel == LL_DMA_CHANNEL_7)
- {
- /* Reset interrupt pending bits for DMAx Channel7 */
- LL_DMA_ClearFlag_GI7(DMAx);
- }
+ else if (Channel == LL_DMA_CHANNEL_7)
+ {
+ /* Reset interrupt pending bits for DMAx Channel7 */
+ LL_DMA_ClearFlag_GI7(DMAx);
+ }
#endif
- else
- {
- status = ERROR;
- }
+ else
+ {
+ status = ERROR;
+ }
return status;
}
@@ -392,3 +392,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_exti.c b/Src/stm32f0xx_ll_exti.c
index d76e998..bdb7094 100644
--- a/Src/stm32f0xx_ll_exti.c
+++ b/Src/stm32f0xx_ll_exti.c
@@ -218,3 +218,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_gpio.c b/Src/stm32f0xx_ll_gpio.c
index 0e44f99..f5692a2 100644
--- a/Src/stm32f0xx_ll_gpio.c
+++ b/Src/stm32f0xx_ll_gpio.c
@@ -272,3 +272,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_i2c.c b/Src/stm32f0xx_ll_i2c.c
index 4d96bfc..722443e 100644
--- a/Src/stm32f0xx_ll_i2c.c
+++ b/Src/stm32f0xx_ll_i2c.c
@@ -83,7 +83,7 @@
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
@@ -125,7 +125,7 @@
* - SUCCESS: I2C registers are initialized
* - ERROR: Not applicable
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
diff --git a/Src/stm32f0xx_ll_rcc.c b/Src/stm32f0xx_ll_rcc.c
index 32bffdd..331b346 100644
--- a/Src/stm32f0xx_ll_rcc.c
+++ b/Src/stm32f0xx_ll_rcc.c
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -604,3 +603,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_rtc.c b/Src/stm32f0xx_ll_rtc.c
index 7af79d8..bcbd661 100644
--- a/Src/stm32f0xx_ll_rtc.c
+++ b/Src/stm32f0xx_ll_rtc.c
@@ -15,7 +15,6 @@
*
******************************************************************************
*/
-
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
@@ -85,11 +84,11 @@
|| ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
-#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
-#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
@@ -98,11 +97,9 @@
|| ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
-
#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
-
/**
* @}
*/
@@ -118,7 +115,7 @@
/**
* @brief De-Initializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * @note This function does not reset the RTC Clock source and RTC Backup Data
* registers.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
@@ -143,17 +140,19 @@
#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+
/* Reset All CR bits except CR[2:0] */
#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
-#else
+#else /* RTC_WAKEUP_SUPPORT */
LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+
+ LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
- LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
/* Reset ISR register and exit initialization mode */
@@ -356,7 +355,7 @@
if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
{
- RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+ RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
}
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
@@ -631,7 +630,7 @@
* synchronized with RTC APB clock.
* @note The RTC Resynchronization mode is write protected, use the
* @ref LL_RTC_DisableWriteProtection before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
+ * @note To read the calendar through the shadow registers after calendar
* initialization, calendar update or after wakeup from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
@@ -656,7 +655,7 @@
/* Wait the registers to be synchronised */
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- while ((timeout != 0U) && (tmp != 0U))
+ while ((timeout != 0U) && (tmp != 1U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
@@ -669,24 +668,6 @@
}
}
- if (status != ERROR)
- {
- timeout = RTC_SYNCHRO_TIMEOUT;
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- while ((timeout != 0U) && (tmp != 1U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout--;
- }
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
- }
-
return (status);
}
diff --git a/Src/stm32f0xx_ll_spi.c b/Src/stm32f0xx_ll_spi.c
index 5e1e3c9..2d5d2a2 100644
--- a/Src/stm32f0xx_ll_spi.c
+++ b/Src/stm32f0xx_ll_spi.c
@@ -532,3 +532,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_tim.c b/Src/stm32f0xx_ll_tim.c
index 642c207..0ac2fbc 100644
--- a/Src/stm32f0xx_ll_tim.c
+++ b/Src/stm32f0xx_ll_tim.c
@@ -165,7 +165,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: invalid TIMx instance
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
{
ErrorStatus result = SUCCESS;
@@ -1165,3 +1165,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f0xx_ll_usart.c b/Src/stm32f0xx_ll_usart.c
index 6c626e8..5ff5fd7 100644
--- a/Src/stm32f0xx_ll_usart.c
+++ b/Src/stm32f0xx_ll_usart.c
@@ -31,7 +31,8 @@
* @{
*/
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) || defined (USART6) || defined (USART7) || defined (USART8)
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) \
+ || defined(USART6) || defined(USART7) || defined(USART8)
/** @addtogroup USART_LL
* @{
@@ -40,6 +41,17 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+ * @{
+ */
+
+/* Definition of default baudrate value used for USART initialisation */
+#define USART_DEFAULT_BAUDRATE (9600U)
+
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
@@ -93,7 +105,7 @@
#else
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \
|| ((__VALUE__) == LL_USART_STOPBITS_2))
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
@@ -122,7 +134,7 @@
* - SUCCESS: USART registers are de-initialized
* - ERROR: USART registers are not de-initialized
*/
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
{
ErrorStatus status = SUCCESS;
@@ -229,7 +241,7 @@
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
{
ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
@@ -294,7 +306,7 @@
/* USART2 clock is PCLK */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
+#endif /* USART2 Clock selector flag */
}
#endif /* USART2 */
#if defined(USART3)
@@ -306,7 +318,7 @@
/* USART3 clock is PCLK */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
+#endif /* USART3 Clock selector flag */
}
#endif /* USART3 */
#if defined(USART4)
@@ -386,7 +398,7 @@
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
{
/* Set USART_InitStruct fields to default values */
- USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE;
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
@@ -409,7 +421,7 @@
* to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
ErrorStatus status = SUCCESS;
@@ -498,3 +510,5 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/Src/stm32f0xx_ll_usb.c b/Src/stm32f0xx_ll_usb.c
index 1ba0ccb..8298d30 100644
--- a/Src/stm32f0xx_ll_usb.c
+++ b/Src/stm32f0xx_ll_usb.c
@@ -11,18 +11,6 @@
* + Peripheral Control functions
* + Peripheral State functions
*
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
- (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
- (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
- @endverbatim
******************************************************************************
* @attention
*
@@ -34,6 +22,20 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
+
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+ @endverbatim
+
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -52,7 +54,6 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
/**
* @brief Initializes the USB Core
* @param USBx USB Instance
@@ -241,10 +242,19 @@
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure VALID status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ if (ep->num == 0U)
+ {
+ /* Configure VALID status for EP0 */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+ else
+ {
+ /* Configure NAK status for OUT Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
}
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
@@ -291,6 +301,7 @@
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
}
@@ -309,18 +320,20 @@
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
+ /* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
+
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
+ /* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
- /*Double Buffer*/
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
else
{
if (ep->is_in == 0U)
@@ -347,6 +360,7 @@
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
@@ -360,8 +374,10 @@
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
uint32_t len;
+#if (USE_USB_DOUBLE_BUFFER == 1U)
uint16_t pmabuffer;
uint16_t wEPVal;
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
@@ -382,6 +398,7 @@
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
@@ -493,6 +510,7 @@
}
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
}
@@ -514,6 +532,7 @@
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
@@ -532,7 +551,7 @@
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
{
- PCD_FreeUserBuffer(USBx, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
}
}
}
@@ -557,6 +576,7 @@
return HAL_ERROR;
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@@ -616,6 +636,51 @@
return HAL_OK;
}
+
+/**
+ * @brief USB_EPStoptXfer Stop transfer on an EP
+ * @param USBx usb device instance
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ }
+ }
+ else /* OUT endpoint */
+ {
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
+ else
+ {
+ /* Configure RX Endpoint to disabled state */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+ }
+
+ return HAL_OK;
+}
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
/**
@@ -684,9 +749,9 @@
/**
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
- * @retval HAL status
+ * @retval USB Global Interrupt status
*/
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
{
uint32_t tmpreg;
@@ -730,25 +795,26 @@
{
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i, temp1, temp2;
+ uint32_t count;
+ uint16_t WrVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
- for (i = n; i != 0U; i--)
+ for (count = n; count != 0U; count--)
{
- temp1 = *pBuf;
- pBuf++;
- temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
- *pdwVal = (uint16_t)temp2;
+ WrVal = pBuf[0];
+ WrVal |= (uint16_t)pBuf[1] << 8;
+ *pdwVal = (WrVal & 0xFFFFU);
pdwVal++;
#if PMA_ACCESS > 1U
pdwVal++;
-#endif
+#endif /* PMA_ACCESS */
pBuf++;
+ pBuf++;
}
}
@@ -764,30 +830,31 @@
{
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i, temp;
+ uint32_t count;
+ uint32_t RdVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
- for (i = n; i != 0U; i--)
+ for (count = n; count != 0U; count--)
{
- temp = *(__IO uint16_t *)pdwVal;
+ RdVal = *(__IO uint16_t *)pdwVal;
pdwVal++;
- *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
pBuf++;
- *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
+ *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
pBuf++;
#if PMA_ACCESS > 1U
pdwVal++;
-#endif
+#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
{
- temp = *pdwVal;
- *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ RdVal = *pdwVal;
+ *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
}
}
diff --git a/_htmresc/favicon.png b/_htmresc/favicon.png
new file mode 100644
index 0000000..06713ee
--- /dev/null
+++ b/_htmresc/favicon.png
Binary files differ
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st_2020.css
similarity index 77%
rename from _htmresc/mini-st.css
rename to _htmresc/mini-st_2020.css
index 71fbc14..3d9e81a 100644
--- a/_htmresc/mini-st.css
+++ b/_htmresc/mini-st_2020.css
@@ -1,39 +1,39 @@
@charset "UTF-8";
/*
- Flavor name: Default (mini-default)
- Author: Angelos Chalaris (chalarangelo@gmail.com)
- Maintainers: Angelos Chalaris
- mini.css version: v3.0.0-alpha.3
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
*/
/*
Browsers resets and base typography.
*/
/* Core module CSS variable definitions */
:root {
- --fore-color: #111;
- --secondary-fore-color: #444;
- --back-color: #f8f8f8;
- --secondary-back-color: #f0f0f0;
- --blockquote-color: #f57c00;
- --pre-color: #1565c0;
- --border-color: #aaa;
- --secondary-border-color: #ddd;
- --heading-ratio: 1.19;
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
--universal-margin: 0.5rem;
- --universal-padding: 0.125rem;
- --universal-border-radius: 0.125rem;
- --a-link-color: #0277bd;
- --a-visited-color: #01579b; }
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
html {
- font-size: 14px; }
+ font-size: 13.5px; }
a, b, del, em, i, ins, q, span, strong, u {
font-size: 1em; }
html, * {
- font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
- line-height: 1.4;
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
-webkit-text-size-adjust: 100%; }
* {
@@ -42,7 +42,10 @@
body {
margin: 0;
color: var(--fore-color);
- background: var(--back-color); }
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
details {
display: block; }
@@ -62,9 +65,9 @@
height: auto; }
h1, h2, h3, h4, h5, h6 {
- line-height: 1.2;
+ line-height: 1.25;
margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
- font-weight: 500; }
+ font-weight: 400; }
h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
color: var(--secondary-fore-color);
display: block;
@@ -74,21 +77,15 @@
font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
h2 {
- font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
- background: var(--mark-back-color);
- font-weight: 600;
- padding: 0.1em 0.5em 0.2em 0.5em;
- color: var(--mark-fore-color); }
-
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
h3 {
- font-size: calc(1rem * var(--heading-ratio));
- padding-left: calc(2 * var(--universal-margin));
- /* background: var(--border-color); */
- }
+ font-size: calc(1rem * var(--heading-ratio) ); }
h4 {
- font-size: 1rem;);
- padding-left: calc(4 * var(--universal-margin)); }
+ font-size: calc(1rem * var(--heading-ratio)); }
h5 {
font-size: 1rem; }
@@ -101,7 +98,7 @@
ol, ul {
margin: var(--universal-margin);
- padding-left: calc(6 * var(--universal-margin)); }
+ padding-left: calc(3 * var(--universal-margin)); }
b, strong {
font-weight: 700; }
@@ -111,7 +108,7 @@
border: 0;
line-height: 1.25em;
margin: var(--universal-margin);
- height: 0.0625rem;
+ height: 0.0714285714rem;
background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
blockquote {
@@ -121,16 +118,16 @@
color: var(--secondary-fore-color);
margin: var(--universal-margin);
padding: calc(3 * var(--universal-padding));
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.375rem solid var(--blockquote-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
blockquote:before {
position: absolute;
top: calc(0rem - var(--universal-padding));
left: 0;
font-family: sans-serif;
- font-size: 3rem;
- font-weight: 700;
+ font-size: 2rem;
+ font-weight: 800;
content: "\201c";
color: var(--blockquote-color); }
blockquote[cite]:after {
@@ -160,8 +157,8 @@
background: var(--secondary-back-color);
padding: calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.25rem solid var(--pre-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
sup, sub, code, kbd {
@@ -204,7 +201,8 @@
box-sizing: border-box;
display: flex;
flex: 0 1 auto;
- flex-flow: row wrap; }
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
.col-sm,
[class^='col-sm-'],
@@ -565,9 +563,9 @@
order: 999; } }
/* Card component CSS variable definitions */
:root {
- --card-back-color: #f8f8f8;
- --card-fore-color: #111;
- --card-border-color: #ddd; }
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
.card {
display: flex;
@@ -578,7 +576,7 @@
width: 100%;
background: var(--card-back-color);
color: var(--card-fore-color);
- border: 0.0625rem solid var(--card-border-color);
+ border: 0.0714285714rem solid var(--card-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
overflow: hidden; }
@@ -592,7 +590,7 @@
margin: 0;
border: 0;
border-radius: 0;
- border-bottom: 0.0625rem solid var(--card-border-color);
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
padding: var(--universal-padding);
width: 100%; }
.card > .sectione.media {
@@ -617,17 +615,18 @@
width: auto; }
.card.warning {
-/* --card-back-color: #ffca28; */
--card-back-color: #e5b8b7;
- --card-border-color: #e8b825; }
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
.card.error {
- --card-back-color: #b71c1c;
- --card-fore-color: #f8f8f8;
- --card-border-color: #a71a1a; }
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
.card > .sectione.dark {
- --card-back-color: #e0e0e0; }
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
.card > .sectione.double-padded {
padding: calc(1.5 * var(--universal-padding)); }
@@ -637,12 +636,12 @@
*/
/* Input_control module CSS variable definitions */
:root {
- --form-back-color: #f0f0f0;
- --form-fore-color: #111;
- --form-border-color: #ddd;
- --input-back-color: #f8f8f8;
- --input-fore-color: #111;
- --input-border-color: #ddd;
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
--input-focus-color: #0288d1;
--input-invalid-color: #d32f2f;
--button-back-color: #e2e2e2;
@@ -655,13 +654,13 @@
form {
background: var(--form-back-color);
color: var(--form-fore-color);
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
fieldset {
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 4);
padding: var(--universal-padding); }
@@ -671,7 +670,7 @@
display: table;
max-width: 100%;
white-space: normal;
- font-weight: 700;
+ font-weight: 500;
padding: calc(var(--universal-padding) / 2); }
label {
@@ -716,7 +715,7 @@
box-sizing: border-box;
background: var(--input-back-color);
color: var(--input-fore-color);
- border: 0.0625rem solid var(--input-border-color);
+ border: 0.0714285714rem solid var(--input-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 2);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
@@ -763,8 +762,8 @@
[type="radio"]:checked:before {
border-radius: 100%;
content: '';
- top: calc(0.0625rem + var(--universal-padding) / 2);
- left: calc(0.0625rem + var(--universal-padding) / 2);
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
background: var(--input-fore-color);
width: 0.5rem;
height: 0.5rem; }
@@ -793,7 +792,7 @@
display: inline-block;
background: var(--button-back-color);
color: var(--button-fore-color);
- border: 0.0625rem solid var(--button-border-color);
+ border: 0.0714285714rem solid var(--button-border-color);
border-radius: var(--universal-border-radius);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
@@ -814,7 +813,7 @@
.button-group {
display: flex;
- border: 0.0625rem solid var(--button-group-border-color);
+ border: 0.0714285714rem solid var(--button-group-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
.button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
@@ -826,13 +825,13 @@
border-radius: 0;
box-shadow: none; }
.button-group > :not(:first-child) {
- border-left: 0.0625rem solid var(--button-group-border-color); }
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
@media screen and (max-width: 499px) {
.button-group {
flex-direction: column; }
.button-group > :not(:first-child) {
border: 0;
- border-top: 0.0625rem solid var(--button-group-border-color); } }
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
/*
Custom elements for forms and input elements.
@@ -874,29 +873,29 @@
*/
/* Navigation module CSS variable definitions */
:root {
- --header-back-color: #f8f8f8;
- --header-hover-back-color: #f0f0f0;
- --header-fore-color: #444;
- --header-border-color: #ddd;
- --nav-back-color: #f8f8f8;
- --nav-hover-back-color: #f0f0f0;
- --nav-fore-color: #444;
- --nav-border-color: #ddd;
- --nav-link-color: #0277bd;
- --footer-fore-color: #444;
- --footer-back-color: #f8f8f8;
- --footer-border-color: #ddd;
- --footer-link-color: #0277bd;
- --drawer-back-color: #f8f8f8;
- --drawer-hover-back-color: #f0f0f0;
- --drawer-border-color: #ddd;
- --drawer-close-color: #444; }
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
header {
- height: 3.1875rem;
+ height: 2.75rem;
background: var(--header-back-color);
color: var(--header-fore-color);
- border-bottom: 0.0625rem solid var(--header-border-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
padding: calc(var(--universal-padding) / 4) 0;
white-space: nowrap;
overflow-x: auto;
@@ -927,7 +926,7 @@
nav {
background: var(--nav-back-color);
color: var(--nav-fore-color);
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
nav * {
@@ -946,10 +945,10 @@
nav .sublink-1:before {
position: absolute;
left: calc(var(--universal-padding) - 1 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
nav .sublink-2 {
position: relative;
@@ -957,16 +956,16 @@
nav .sublink-2:before {
position: absolute;
left: calc(var(--universal-padding) - 3 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
footer {
background: var(--footer-back-color);
color: var(--footer-fore-color);
- border-top: 0.0625rem solid var(--footer-border-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
padding: calc(2 * var(--universal-padding)) var(--universal-padding);
font-size: 0.875rem; }
footer a, footer a:visited {
@@ -1013,7 +1012,7 @@
height: 100vh;
overflow-y: auto;
background: var(--drawer-back-color);
- border: 0.0625rem solid var(--drawer-border-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
border-radius: 0;
margin: 0;
z-index: 1110;
@@ -1060,38 +1059,36 @@
*/
/* Table module CSS variable definitions. */
:root {
- --table-border-color: #aaa;
- --table-border-separator-color: #666;
- --table-head-back-color: #e6e6e6;
- --table-head-fore-color: #111;
- --table-body-back-color: #f8f8f8;
- --table-body-fore-color: #111;
- --table-body-alt-back-color: #eee; }
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
table {
border-collapse: separate;
border-spacing: 0;
- : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ margin: 0;
display: flex;
flex: 0 1 auto;
flex-flow: row wrap;
padding: var(--universal-padding);
- padding-top: 0;
- margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
+ padding-top: 0; }
table caption {
- font-size: 1.25 * rem;
+ font-size: 1rem;
margin: calc(2 * var(--universal-margin)) 0;
max-width: 100%;
- flex: 0 0 100%;
- text-align: left;}
+ flex: 0 0 100%; }
table thead, table tbody {
display: flex;
flex-flow: row wrap;
- border: 0.0625rem solid var(--table-border-color); }
+ border: 0.0714285714rem solid var(--table-border-color); }
table thead {
z-index: 999;
border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
- border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
table tbody {
border-top: 0;
margin-top: calc(0 - var(--universal-margin));
@@ -1109,11 +1106,11 @@
table td {
background: var(--table-body-back-color);
color: var(--table-body-fore-color);
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table:not(.horizontal) {
overflow: auto;
- max-height: 850px; }
+ max-height: 100%; }
table:not(.horizontal) thead, table:not(.horizontal) tbody {
max-width: 100%;
flex: 0 0 100%; }
@@ -1134,32 +1131,33 @@
border: 0; }
table.horizontal thead, table.horizontal tbody {
border: 0;
+ flex: .2 0 0;
flex-flow: row nowrap; }
table.horizontal tbody {
overflow: auto;
justify-content: space-between;
- flex: 1 0 0;
- margin-left: calc( 4 * var(--universal-margin));
+ flex: .8 0 0;
+ margin-left: 0;
padding-bottom: calc(var(--universal-padding) / 4); }
table.horizontal tr {
flex-direction: column;
flex: 1 0 auto; }
table.horizontal th, table.horizontal td {
- width: 100%;
+ width: auto;
border: 0;
- border-bottom: 0.0625rem solid var(--table-border-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
border-top: 0; }
table.horizontal th {
text-align: right;
- border-left: 0.0625rem solid var(--table-border-color);
- border-right: 0.0625rem solid var(--table-border-separator-color); }
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
table.horizontal thead tr:first-child {
padding-left: 0; }
table.horizontal th:first-child, table.horizontal td:first-child {
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td {
- border-right: 0.0625rem solid var(--table-border-color); }
+ border-right: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td:first-child {
border-top-right-radius: 0.25rem; }
table.horizontal tbody tr:last-child td:last-child {
@@ -1191,12 +1189,12 @@
display: table-row-group; }
table tr, table.horizontal tr {
display: block;
- border: 0.0625rem solid var(--table-border-color);
+ border: 0.0714285714rem solid var(--table-border-color);
border-radius: var(--universal-border-radius);
- background: #fafafa;
+ background: #ffffff;
padding: var(--universal-padding);
margin: var(--universal-margin);
- margin-bottom: calc(2 * var(--universal-margin)); }
+ margin-bottom: calc(1 * var(--universal-margin)); }
table th, table td, table.horizontal th, table.horizontal td {
width: auto; }
table td, table.horizontal td {
@@ -1211,9 +1209,6 @@
border-top: 0; }
table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
border-right: 0; } }
-:root {
- --table-body-alt-back-color: #eee; }
-
table tr:nth-of-type(2n) > td {
background: var(--table-body-alt-back-color); }
@@ -1234,8 +1229,8 @@
*/
/* Contextual module CSS variable definitions */
:root {
- --mark-back-color: #0277bd;
- --mark-fore-color: #fafafa; }
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
mark {
background: var(--mark-back-color);
@@ -1243,11 +1238,11 @@
font-size: 0.95em;
line-height: 1em;
border-radius: var(--universal-border-radius);
- padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
mark.inline-block {
display: inline-block;
font-size: 1em;
- line-height: 1.5;
+ line-height: 1.4;
padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
:root {
@@ -1314,8 +1309,8 @@
:root {
--modal-overlay-color: rgba(0, 0, 0, 0.45);
- --modal-close-color: #444;
- --modal-close-hover-color: #f0f0f0; }
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
[type="checkbox"].modal {
height: 1px;
@@ -1368,13 +1363,14 @@
z-index: 1211; }
:root {
- --collapse-label-back-color: #e8e8e8;
- --collapse-label-fore-color: #212121;
- --collapse-label-hover-back-color: #f0f0f0;
- --collapse-selected-label-back-color: #ececec;
- --collapse-border-color: #ddd;
- --collapse-content-back-color: #fafafa;
- --collapse-selected-label-border-color: #0277bd; }
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
.collapse {
width: calc(100% - 2 * var(--universal-margin));
@@ -1395,13 +1391,13 @@
.collapse > label {
flex-grow: 1;
display: inline-block;
- height: 1.5rem;
+ height: 1.25rem;
cursor: pointer;
- transition: background 0.3s;
+ transition: background 0.2s;
color: var(--collapse-label-fore-color);
background: var(--collapse-label-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
- padding: calc(1.5 * var(--universal-padding)); }
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
.collapse > label:hover, .collapse > label:focus {
background: var(--collapse-label-hover-back-color); }
.collapse > label + div {
@@ -1418,7 +1414,7 @@
max-height: 1px; }
.collapse > :checked + label {
background: var(--collapse-selected-label-back-color);
- border-bottom-color: var(--collapse-selected-label-border-color); }
+ border-color: var(--collapse-selected-label-border-color); }
.collapse > :checked + label + div {
box-sizing: border-box;
position: relative;
@@ -1427,13 +1423,13 @@
overflow: auto;
margin: 0;
background: var(--collapse-content-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
border-top: 0;
padding: var(--universal-padding);
clip: auto;
-webkit-clip-path: inset(0%);
clip-path: inset(0%);
- max-height: 850px; }
+ max-height: 100%; }
.collapse > label:not(:first-of-type) {
border-top: 0; }
.collapse > label:first-of-type {
@@ -1450,11 +1446,8 @@
/*
Custom elements for contextual background elements, toasts and tooltips.
*/
-mark.secondary {
- --mark-back-color: #d32f2f; }
-
mark.tertiary {
- --mark-back-color: #308732; }
+ --mark-back-color: #3cb4e6; }
mark.tag {
padding: calc(var(--universal-padding)/2) var(--universal-padding);
@@ -1463,9 +1456,9 @@
/*
Definitions for progress elements and spinners.
*/
-/* Progess module CSS variable definitions */
+/* Progress module CSS variable definitions */
:root {
- --progress-back-color: #ddd;
+ --progress-back-color: #3cb4e6;
--progress-fore-color: #555; }
progress {
@@ -1558,45 +1551,45 @@
filter: invert(100%); }
span.icon-alert {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-bookmark {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-calendar {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-credit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-edit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
span.icon-link {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-help {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-home {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-info {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-lock {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-mail {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-location {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-phone {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-rss {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-search {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-settings {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-share {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-cart {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-upload {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-user {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
/*
Definitions for utilities and helper classes.
@@ -1604,7 +1597,7 @@
/* Utility module CSS variable definitions */
:root {
--generic-border-color: rgba(0, 0, 0, 0.3);
- --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
.hidden {
display: none !important; }
@@ -1622,7 +1615,7 @@
overflow: hidden !important; }
.bordered {
- border: 0.0625rem solid var(--generic-border-color) !important; }
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
.rounded {
border-radius: var(--universal-border-radius) !important; }
@@ -1697,4 +1690,14 @@
clip-path: inset(100%) !important;
overflow: hidden !important; } }
-/*# sourceMappingURL=mini-default.css.map */
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/_htmresc/st_logo_2020.png b/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000..d6cebb5
--- /dev/null
+++ b/_htmresc/st_logo_2020.png
Binary files differ
