Release v1.7.8
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index b674da9..8ff52d7 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -5,9 +5,9 @@
This guide mainly focuses on the proper use of Git.
### 1. Before opening an issue
-To report a bug/request please file an issue in the right repository
-(example for [stm32f4xx_hal_driver](https://github.com/STMicroelectronics/stm32f4xx_hal_driver/issues/new/choose)).
-But check the following boxes before posting an issue:
+In order to centralize your bug reports and requests and to ease their tracking please file an issue into the firmware repository [STM32CubeF4](https://github.com/STMicroelectronics/STM32CubeF4/issues/new/choose).
+
+Please check the following boxes before posting an issue:
- [ ] `Make sure you are using the latest commit (major releases are Tagged, but corrections are available as new commits).`
- [ ] `Make sure your issue is a question/feedback/suggestions RELATED TO the software provided in this repo.` Otherwise, it should be discussed on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
@@ -15,7 +15,7 @@
### 2. Posting the issue
-When you have checked the previous boxes. You will find two templates Issues (Bug Report or Other Issue) available in the **Issues** tab of the repo
+Once you have checked the previous boxes, you will find two templates for issues (Bug Report or Other Issue) available in the **Issues** tab of the firmware repository.
### 3. Pull Requests
-For the moment, the Pull Request feature is not deployed. STMicrolectronics is working on a Contributor License Agreement procedure
+For the moment, the Pull Request feature is not deployed. STMicrolectronics is working on a Contributor License Agreement (CLA) procedure.
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index f085e2d..90767ed 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -241,7 +241,7 @@
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -955,7 +955,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1531,18 +1531,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -3245,7 +3245,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3373,7 +3373,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3496,7 +3496,7 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3751,9 +3751,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32L4)
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif
+#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/
diff --git a/Inc/stm32f4xx_hal_cryp.h b/Inc/stm32f4xx_hal_cryp.h
index 8251ebd..dc9de6e 100644
--- a/Inc/stm32f4xx_hal_cryp.h
+++ b/Inc/stm32f4xx_hal_cryp.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CRYP_H
#define __STM32F4xx_HAL_CRYP_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
@@ -51,87 +51,97 @@
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
- uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
- uint32_t* pKey; /*!< The key used for encryption/decryption */
- uint32_t* pInitVect; /*!< The initialization vector used also as initialization
+ uint32_t *pKey; /*!< The key used for encryption/decryption */
+ uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
- uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
+ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
AES Algorithm ECB/CBC/CTR/GCM or CCM
This parameter can be a value of @ref CRYP_Algorithm_Mode */
- uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
+ uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
- uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
+ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+ Vector only once and to skip configuration for consecutive processings.
+ This parameter can be a value of @ref CRYP_Configuration_Skip */
-}CRYP_ConfigTypeDef;
+} CRYP_ConfigTypeDef;
/**
* @brief CRYP State Structure definition
*/
-
+
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
-}HAL_CRYP_STATETypeDef;
-
+} HAL_CRYP_STATETypeDef;
+
/**
* @brief CRYP handle Structure definition
*/
-
+
typedef struct __CRYP_HandleTypeDef
{
#if defined (CRYP)
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
#else /* AES*/
- AES_TypeDef *Instance; /*!< AES Register base address */
+ AES_TypeDef *Instance; /*!< AES Register base address */
#endif /* End AES or CRYP */
- CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
-
- FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
- This parameter can be a value of ENABLE/DISABLE */
-
- uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
- uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+ FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
+ This parameter can be a value of ENABLE/DISABLE */
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
-
- __IO uint16_t CrypInCount; /*!< Counter of input data */
+ uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
-
- uint16_t Size; /*!< length of input data in word */
+ uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- uint32_t Phase; /*!< CRYP peripheral phase */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+ __IO uint16_t CrypInCount; /*!< Counter of input data */
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
+ uint16_t Size; /*!< length of input data in word */
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
+ uint32_t Phase; /*!< CRYP peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
+
+ uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
+ configuration can be skipped */
+
+ uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
+ for a single signature computation after several
+ messages processing */
+
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
- void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
- void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-
- void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
- void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
+ void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
+ void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
-#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-}CRYP_HandleTypeDef;
+ void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+} CRYP_HandleTypeDef;
/**
@@ -152,7 +162,7 @@
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
-}HAL_CRYP_CallbackIDTypeDef;
+} HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
@@ -162,7 +172,7 @@
* @{
*/
-typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
+typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
/**
* @}
@@ -181,7 +191,7 @@
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
-#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
+#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
@@ -189,21 +199,21 @@
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-/**
+/**
* @}
*/
-/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
* @{
*/
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
-/**
+/**
* @}
- */
-
+ */
+
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
@@ -212,14 +222,14 @@
#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
-#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
+#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
-#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
+#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
-#endif /* GCM CCM defined*/
+#endif /* GCM CCM defined*/
#else /* AES*/
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
@@ -228,7 +238,7 @@
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -240,10 +250,10 @@
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
#else /* AES*/
-#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
-#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
#endif /* End AES or CRYP */
-/**
+/**
* @}
*/
@@ -261,15 +271,15 @@
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
#endif /* End AES or CRYP */
-
-/**
+
+/**
* @}
*/
/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
-#if defined (CRYP)
+#if defined (CRYP)
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
#else /* AES*/
@@ -297,7 +307,7 @@
or a key preparation (for AES decryption). */
/* Flags in the RISR register */
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
-#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
+#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
#else /* AES*/
/* status flags */
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
@@ -312,7 +322,18 @@
/**
* @}
*/
-
+
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+ * @{
+ */
+
+#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
+
+/**
+ * @}
+ */
+
/**
* @}
@@ -336,7 +357,7 @@
#else
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
+
/**
* @brief Enable/Disable the CRYP peripheral.
* @param __HANDLE__: specifies the CRYP handle.
@@ -345,33 +366,33 @@
#if defined(CRYP)
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
#else /* AES*/
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#endif /* End AES or CRYP */
@@ -380,12 +401,12 @@
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
- * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(AES)
+#if defined(AES)
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
@@ -393,37 +414,39 @@
* @param __INTERRUPT__: CRYP interrupt source to check
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
- * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @param __HANDLE__: specifies the CRYP handle.
* @retval State of interruption (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* AES */
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values for TinyAES:
- * @arg @ref CRYP_IT_WRERR Write Error
- * @arg @ref CRYP_IT_RDERR Read Error
- * @arg @ref CRYP_IT_CCF Computation Complete
+ * @arg @ref CRYP_IT_WRERR Write Error
+ * @arg @ref CRYP_IT_RDERR Read Error
+ * @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
* @param __HANDLE__: specifies the CRYP handle.
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#if defined(CRYP)
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#if defined(CRYP)
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#else /* AES*/
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
- * @brief Enable the CRYP interrupt.
+ * @brief Enable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -432,16 +455,16 @@
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
#endif /* End AES or CRYP */
/**
* @brief Disable the CRYP interrupt.
* @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for TinyAES:
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
@@ -450,9 +473,9 @@
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#if defined(CRYP)
+#if defined(CRYP)
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
-#else /* AES*/
+#else /* AES*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
#endif /* End AES or CRYP */
@@ -462,7 +485,7 @@
#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
/* Include CRYP HAL Extended module */
#include "stm32f4xx_hal_cryp_ex.h"
-#endif /* AES or GCM CCM defined*/
+#endif /* AES or GCM CCM defined*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
@@ -470,28 +493,31 @@
/** @addtogroup CRYP_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group2
* @{
- */
+ */
/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
@@ -499,12 +525,12 @@
/**
* @}
- */
+ */
/** @addtogroup CRYP_Exported_Functions_Group3
* @{
- */
+ */
/* Interrupt Handler functions **********************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
@@ -515,8 +541,8 @@
/**
* @}
- */
-
+ */
+
/**
* @}
*/
@@ -532,32 +558,32 @@
#if defined(CRYP)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM) || \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM) || \
+ ((ALGORITHM) == CRYP_AES_CCM))
#else /*NO GCM CCM */
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR))
-#endif /* GCM CCM defined*/
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR))
+#endif /* GCM CCM defined*/
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
((KEYSIZE) == CRYP_KEYSIZE_256B))
-#else /* AES*/
+#else /* AES*/
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR) || \
- ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
- ((ALGORITHM) == CRYP_AES_CCM))
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
+ ((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
@@ -569,6 +595,8 @@
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/
@@ -585,7 +613,7 @@
/**
* @}
- */
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
@@ -593,8 +621,8 @@
/**
* @}
- */
-
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
@@ -602,7 +630,7 @@
/**
* @}
- */
+ */
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
* @{
@@ -620,21 +648,21 @@
/**
* @}
*/
-
-
-/**
- * @}
- */
/**
* @}
- */
+ */
+
+
+/**
+ * @}
+ */
#endif /* TinyAES or CRYP*/
/**
* @}
- */
+ */
#ifdef __cplusplus
}
diff --git a/Inc/stm32f4xx_hal_cryp_ex.h b/Inc/stm32f4xx_hal_cryp_ex.h
index f93a3b7..251e94b 100644
--- a/Inc/stm32f4xx_hal_cryp_ex.h
+++ b/Inc/stm32f4xx_hal_cryp_ex.h
@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CRYP_EX_H
#define __STM32F4xx_HAL_CRYP_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -35,14 +35,14 @@
/** @addtogroup CRYPEx
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
* @{
*/
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
* @{
@@ -50,8 +50,8 @@
/**
* @}
- */
-
+ */
+
/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
@@ -59,7 +59,7 @@
/**
* @}
- */
+ */
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
@@ -68,7 +68,7 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
@@ -77,17 +77,17 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
* @{
*/
- /**
+/**
* @}
- */
-
+ */
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
* @{
@@ -104,7 +104,7 @@
#if defined (CRYP) || defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
- */
+ */
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
@@ -112,10 +112,10 @@
*/
#endif /* CRYP||AES */
-#if defined (AES)
+#if defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
- */
+ */
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
@@ -125,16 +125,16 @@
/**
* @}
- */
-
-/**
- * @}
- */
+ */
/**
* @}
- */
-
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32f4xx_hal_exti.h b/Inc/stm32f4xx_hal_exti.h
index 8bb516c..ff74222 100644
--- a/Inc/stm32f4xx_hal_exti.h
+++ b/Inc/stm32f4xx_hal_exti.h
@@ -253,9 +253,7 @@
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
-#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
- ((__LINE__) == EXTI_TRIGGER_RISING) || \
- ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
diff --git a/Inc/stm32f4xx_hal_fmpsmbus.h b/Inc/stm32f4xx_hal_fmpsmbus.h
new file mode 100644
index 0000000..04531d9
--- /dev/null
+++ b/Inc/stm32f4xx_hal_fmpsmbus.h
@@ -0,0 +1,745 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpsmbus.h
+ * @author MCD Application Team
+ * @brief Header file of FMPSMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_FMPSMBUS_H
+#define STM32F4xx_HAL_FMPSMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMPSMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types
+ * @{
+ */
+
+/** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition
+ * @brief FMPSMBUS Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value.
+ This parameter calculated by referring to FMPSMBUS initialization
+ section in Reference manual */
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a value of @ref FMPSMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+ This parameter can be a value of @ref FMPSMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref FMPSMBUS_peripheral_mode */
+
+ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value.
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to FMPSMBUS initialization
+ section in Reference manual */
+} FMPSMBUS_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_definition HAL state definition
+ * @brief HAL State definition
+ * @{
+ */
+#define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */
+#define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */
+#define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */
+#define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
+#define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
+#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
+#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
+#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition
+ * @brief FMPSMBUS Error Code definition
+ * @{
+ */
+#define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
+#define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
+#define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
+#define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
+#define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+#define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition
+ * @brief FMPSMBUS handle Structure definition
+ * @{
+ */
+typedef struct __FMPSMBUS_HandleTypeDef
+{
+ FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */
+
+ FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< FMPSMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */
+
+ HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */
+
+ __IO uint32_t State; /*!< FMPSMBUS communication state */
+
+ __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Error callback */
+
+ void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPSMBUS Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp DeInit callback */
+
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+} FMPSMBUS_HandleTypeDef;
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL FMPSMBUS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */
+ HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */
+ HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */
+ HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */
+ HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */
+ HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */
+
+ HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */
+ HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */
+
+} HAL_FMPSMBUS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FMPSMBUS Callback pointer definition
+ */
+typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */
+typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */
+
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter
+ * @{
+ */
+#define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U)
+#define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode
+ * @{
+ */
+#define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
+#define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode
+ * @{
+ */
+
+#define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U)
+#define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks
+ * @{
+ */
+
+#define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U)
+#define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U)
+#define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U)
+#define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U)
+#define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U)
+#define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U)
+#define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U)
+#define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U)
+/**
+ * @}
+ */
+
+
+/** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode
+ * @{
+ */
+#define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U)
+#define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode
+ * @{
+ */
+#define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U)
+#define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode
+ * @{
+ */
+#define FMPSMBUS_PEC_DISABLE (0x00000000U)
+#define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode
+ * @{
+ */
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U)
+#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition
+ * @{
+ */
+
+#define FMPSMBUS_SOFTEND_MODE (0x00000000U)
+#define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD
+#define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND
+#define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition
+ * @{
+ */
+
+#define FMPSMBUS_NO_STARTSTOP (0x00000000U)
+#define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
+#define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition
+ * @{
+ */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE
+#define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE))
+#define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
+#define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
+#define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
+#define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
+#define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
+#define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
+#define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition
+ * @brief FMPSMBUS Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE
+#define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE
+#define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE
+#define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE
+#define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE
+#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
+#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
+#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)
+#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)
+#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
+#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI)
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXXXXXX : Flag mask
+ * @{
+ */
+
+#define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE
+#define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS
+#define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE
+#define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR
+#define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF
+#define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF
+#define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC
+#define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR
+#define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR
+#define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO
+#define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR
+#define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR
+#define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
+#define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT
+#define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY
+#define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset FMPSMBUS handle state.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET)
+#endif
+
+/** @brief Enable the specified FMPSMBUS interrupts.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified FMPSMBUS interrupts.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
+ * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __IT__ (SET or RESET).
+ */
+#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified FMPSMBUS flag is set or not.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty
+ * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status
+ * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty
+ * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
+ * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode)
+ * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload
+ * @arg @ref FMPSMBUS_FLAG_BERR Bus error
+ * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
+ * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy
+ * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define FMPSMBUS_FLAG_MASK (0x0001FFFFU)
+#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
+ * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref FMPSMBUS_FLAG_BERR Bus error
+ * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Enable the specified FMPSMBUS peripheral.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Disable the specified FMPSMBUS peripheral.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode.
+ * @param __HANDLE__ specifies the FMPSMBUS Handle.
+ * @retval None
+ */
+#define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros
+ * @{
+ */
+
+#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
+#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
+
+#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \
+ ((MASK) == FMPSMBUS_OA2_MASK01) || \
+ ((MASK) == FMPSMBUS_OA2_MASK02) || \
+ ((MASK) == FMPSMBUS_OA2_MASK03) || \
+ ((MASK) == FMPSMBUS_OA2_MASK04) || \
+ ((MASK) == FMPSMBUS_OA2_MASK05) || \
+ ((MASK) == FMPSMBUS_OA2_MASK06) || \
+ ((MASK) == FMPSMBUS_OA2_MASK07))
+
+#define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == FMPSMBUS_GENERALCALL_ENABLE))
+
+#define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
+
+#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \
+ ((PEC) == FMPSMBUS_PEC_ENABLE))
+
+#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \
+ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
+ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
+
+#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \
+ ((MODE) == FMPSMBUS_AUTOEND_MODE) || \
+ ((MODE) == FMPSMBUS_SOFTEND_MODE) || \
+ ((MODE) == FMPSMBUS_SENDPEC_MODE) || \
+ ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
+ ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE )))
+
+
+#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \
+ ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == FMPSMBUS_NO_STARTSTOP))
+
+
+#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
+ ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
+ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
+
+#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \
+ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN)))
+#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
+
+#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+
+#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U)
+#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
+#define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
+#define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE)
+#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN)
+
+#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
+#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions
+ * @{
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F4xx_HAL_FMPSMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_hcd.h b/Inc/stm32f4xx_hal_hcd.h
index 5f4cccd..4e76af4 100644
--- a/Inc/stm32f4xx_hal_hcd.h
+++ b/Inc/stm32f4xx_hal_hcd.h
@@ -109,8 +109,8 @@
* @{
*/
#define HCD_SPEED_HIGH USBH_HS_SPEED
-#define HCD_SPEED_FULL USBH_FS_SPEED
-#define HCD_SPEED_LOW USBH_LS_SPEED
+#define HCD_SPEED_FULL USBH_FSLS_SPEED
+#define HCD_SPEED_LOW USBH_FSLS_SPEED
/**
* @}
@@ -170,19 +170,15 @@
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address,
+ uint8_t speed, uint8_t ep_type, uint16_t mps);
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
@@ -191,14 +187,14 @@
*/
typedef enum
{
- HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
- HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
- HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
- HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
- HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
- HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
- HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
@@ -232,25 +228,20 @@
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t *pbuff,
- uint16_t length,
- uint8_t do_ping);
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t direction, uint8_t ep_type,
+ uint8_t token, uint8_t *pbuff,
+ uint16_t length, uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@@ -259,9 +250,9 @@
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@@ -272,8 +263,8 @@
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
diff --git a/Inc/stm32f4xx_hal_i2s.h b/Inc/stm32f4xx_hal_i2s.h
index 2d96315..203ffc1 100644
--- a/Inc/stm32f4xx_hal_i2s.h
+++ b/Inc/stm32f4xx_hal_i2s.h
@@ -181,6 +181,7 @@
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
@@ -421,6 +422,15 @@
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg_udr); \
}while(0U)
+/** @brief Flush the I2S DR Register.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
+ __IO uint32_t tmpreg_dr = 0x00U;\
+ tmpreg_dr = ((__HANDLE__)->Instance->DR);\
+ UNUSED(tmpreg_dr); \
+ }while(0U)
/**
* @}
*/
diff --git a/Inc/stm32f4xx_hal_i2s_ex.h b/Inc/stm32f4xx_hal_i2s_ex.h
index 872283b..10335f4 100644
--- a/Inc/stm32f4xx_hal_i2s_ex.h
+++ b/Inc/stm32f4xx_hal_i2s_ex.h
@@ -111,6 +111,16 @@
tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
UNUSED(tmpreg_udr); \
}while(0U)
+/** @brief Flush the I2S and I2SExt DR Registers.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_dr = 0x00U; \
+ tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \
+ tmpreg_dr = ((__HANDLE__)->Instance->DR); \
+ UNUSED(tmpreg_dr); \
+ }while(0U)
/**
* @}
*/
diff --git a/Inc/stm32f4xx_hal_pcd.h b/Inc/stm32f4xx_hal_pcd.h
index 2db595c..edbb7c6 100644
--- a/Inc/stm32f4xx_hal_pcd.h
+++ b/Inc/stm32f4xx_hal_pcd.h
@@ -96,16 +96,16 @@
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@@ -260,7 +260,7 @@
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@@ -379,14 +379,6 @@
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
diff --git a/Inc/stm32f4xx_hal_qspi.h b/Inc/stm32f4xx_hal_qspi.h
index 4c5de58..97e9324 100644
--- a/Inc/stm32f4xx_hal_qspi.h
+++ b/Inc/stm32f4xx_hal_qspi.h
@@ -6,82 +6,74 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_QSPI_H
-#define __STM32F4xx_HAL_QSPI_H
+#ifndef STM32F4xx_HAL_QSPI_H
+#define STM32F4xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup QSPI
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup QSPI_Exported_Types QSPI Exported Types
* @{
*/
-
-/**
- * @brief QSPI Init structure definition
- */
+/**
+ * @brief QSPI Init structure definition
+ */
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
- This parameter can be a number between 0 and 255 */
-
+ This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
-
- uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
-
- uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
- required to address the flash memory. The flash capacity can be up to 4GB
- (addressed using 32 bits) in indirect mode, but the addressable space in
+ uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+ required to address the flash memory. The flash capacity can be up to 4GB
+ (addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
-
- uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+ uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
- This parameter can be a value of @ref QSPI_ChipSelectHighTime */
-
+ This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
-
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
-
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
-/**
- * @brief HAL QSPI State structures definition
- */
+/**
+ * @brief HAL QSPI State structures definition
+ */
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
@@ -134,17 +126,17 @@
#endif
}QSPI_HandleTypeDef;
-/**
- * @brief QSPI Command structure definition
+/**
+ * @brief QSPI Command structure definition
*/
typedef struct
{
uint32_t Instruction; /* Specifies the Instruction to be sent
This parameter can be a value (8-bit) between 0x00 and 0xFF */
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
- This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
+ This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AddressSize; /* Specifies the Address Size
This parameter can be a value of @ref QSPI_AddressSize */
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
@@ -159,29 +151,29 @@
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
- uint32_t NbData; /* Specifies the number of data to transfer.
- This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
+ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
+ This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
- uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
- system clock in DDR mode.
+ uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
+ output by one half of system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
- uint32_t SIOOMode; /* Specifies the send instruction only once mode
+ uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
-/**
- * @brief QSPI Auto Polling mode configuration structure definition
+/**
+ * @brief QSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
- This parameter can be any value between 0 and 0xFFFFFFFFU */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
- This parameter can be any value between 0 and 0xFFFFFFFFU */
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
- This parameter can be any value between 0 and 0xFFFFU */
+ This parameter can be any value between 0 and 0xFFFF */
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
This parameter can be any value between 1 and 4 */
uint32_t MatchMode; /* Specifies the method used for determining a match.
@@ -190,14 +182,14 @@
This parameter can be a value of @ref QSPI_AutomaticStop */
}QSPI_AutoPollingTypeDef;
-/**
- * @brief QSPI Memory Mapped mode configuration structure definition
+/**
+ * @brief QSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
- This parameter can be any value between 0 and 0xFFFFU */
- uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
+ uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
@@ -235,41 +227,42 @@
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
+
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
- */
-#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
+ */
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
/**
* @}
- */
-
+ */
+
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
-#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
-#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
-#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
-#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
-#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
/**
* @}
*/
@@ -277,31 +270,31 @@
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
-#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
-#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
*/
-
+
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
-#define QSPI_FLASH_ID_1 0x00000000U
-#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
+#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
+#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
- */
+ */
- /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+ /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
* @{
*/
-#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
-#define QSPI_DUALFLASH_DISABLE 0x00000000U
+#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
+#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_AddressSize QSPI Address Size
+/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
@@ -310,7 +303,7 @@
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
/**
* @}
- */
+ */
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
@@ -343,10 +336,10 @@
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
-* @{
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
@@ -354,7 +347,7 @@
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
/**
* @}
- */
+ */
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
@@ -365,27 +358,27 @@
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
/**
* @}
- */
+ */
-/** @defgroup QSPI_DdrMode QSPI Ddr Mode
+/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
-#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
-#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
*/
-/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
-#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
-#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
+#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
/**
* @}
*/
-/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
@@ -397,63 +390,64 @@
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
-#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
-#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
- */
+ */
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
-#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
-#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
-/**
- * @}
- */
-
-/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
- * @{
- */
-#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
-#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
-/**
- * @}
- */
-
-/** @defgroup QSPI_Flags QSPI Flags
- * @{
- */
-#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
-#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
-#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
-#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
-#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
-#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
+#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
*/
-/** @defgroup QSPI_Interrupts QSPI Interrupts
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
- */
-#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
-#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
-#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
-#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
-#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+ */
+#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Flags QSPI Flags
+ * @{
+ */
+#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+ * @{
+ */
+#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
/**
* @}
*/
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+ * @brief QSPI Timeout definition
* @{
- */
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
+ */
+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
- */
-
+ */
+
/**
* @}
*/
@@ -462,9 +456,8 @@
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
* @{
*/
-
-/** @brief Reset QSPI handle state
- * @param __HANDLE__ QSPI handle.
+/** @brief Reset QSPI handle state.
+ * @param __HANDLE__ : QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@@ -477,23 +470,23 @@
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
#endif
-/** @brief Enable QSPI
- * @param __HANDLE__ specifies the QSPI Handle.
+/** @brief Enable the QSPI peripheral.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
- */
+ */
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-/** @brief Disable QSPI
- * @param __HANDLE__ specifies the QSPI Handle.
+/** @brief Disable the QSPI peripheral.
+ * @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
-/** @brief Enables the specified QSPI interrupt.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
+/** @brief Enable the specified QSPI interrupt.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
@@ -503,9 +496,9 @@
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-/** @brief Disables the specified QSPI interrupt.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
+/** @brief Disable the specified QSPI interrupt.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -516,39 +509,39 @@
*/
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-/** @brief Checks whether the specified QSPI interrupt source is enabled.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
+/** @brief Check whether the specified QSPI interrupt source is enabled or not.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
- * @arg QSPI_IT_TO: QSPI Time out interrupt
+ * @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
/**
- * @brief Get the selected QSPI's flag status.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __FLAG__ specifies the QSPI flag to check.
+ * @brief Check whether the selected QSPI flag is set or not.
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
- * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
-#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__ specifies the QSPI Handle.
- * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
+ * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
- * @arg QSPI_FLAG_TO: QSPI Time out flag
+ * @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
@@ -558,7 +551,7 @@
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup QSPI_Exported_Functions
* @{
@@ -578,7 +571,7 @@
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
- */
+ */
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
@@ -599,13 +592,7 @@
/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
-/**
- * @}
- */
-/** @addtogroup QSPI_Exported_Functions_Group3
- * @{
- */
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
@@ -633,9 +620,9 @@
* @}
*/
-/** @addtogroup QSPI_Exported_Functions_Group4
+/** @addtogroup QSPI_Exported_Functions_Group3
* @{
- */
+ */
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
@@ -644,164 +631,108 @@
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
/**
* @}
*/
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
-/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
- * @{
- */
-#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
+
+#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
+
+#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+ ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+ ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
+ ((FLASH_ID) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+ ((MODE) == QSPI_DUALFLASH_DISABLE))
+
+#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+ ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
+ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
+ ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+ ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
+ ((MODE) == QSPI_ADDRESS_1_LINE) || \
+ ((MODE) == QSPI_ADDRESS_2_LINES) || \
+ ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+ ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
+ ((MODE) == QSPI_DATA_1_LINE) || \
+ ((MODE) == QSPI_DATA_2_LINES) || \
+ ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
+
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
+
+#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
+ ((MODE) == QSPI_MATCH_MODE_OR))
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+ ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+ ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
/**
- * @}
- */
-
-/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
- * @{
- */
-#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
-/**
- * @}
- */
-
-#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
- ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
-
-/** @defgroup QSPI_FlashSize QSPI Flash Size
- * @{
- */
-#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
-/**
- * @}
- */
-
-#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
- ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
-
-#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
- ((CLKMODE) == QSPI_CLOCK_MODE_3))
-
-#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
- ((FLA) == QSPI_FLASH_ID_2))
-
-#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
- ((MODE) == QSPI_DUALFLASH_DISABLE))
-
-
-/** @defgroup QSPI_Instruction QSPI Instruction
- * @{
- */
-#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
-/**
- * @}
- */
-
-#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
- ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
-
-#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
- ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
-
-
-/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
- * @{
- */
-#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
-/**
- * @}
- */
-
-#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
- ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
- ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
- ((MODE) == QSPI_INSTRUCTION_4_LINES))
-
-#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
- ((MODE) == QSPI_ADDRESS_1_LINE) || \
- ((MODE) == QSPI_ADDRESS_2_LINES) || \
- ((MODE) == QSPI_ADDRESS_4_LINES))
-
-#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
- ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
-
-#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
- ((MODE) == QSPI_DATA_1_LINE) || \
- ((MODE) == QSPI_DATA_2_LINES) || \
- ((MODE) == QSPI_DATA_4_LINES))
-
-#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
- ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
-
-#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
- ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
-
-#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
- ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
-
-/** @defgroup QSPI_Interval QSPI Interval
- * @{
- */
-#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
-/**
- * @}
- */
-
-/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
- * @{
- */
-#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
-/**
- * @}
- */
-#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
- ((MODE) == QSPI_MATCH_MODE_OR))
-
-#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
- ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
-
-#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
- ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
-
-/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
- * @{
- */
-#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
-/**
- * @}
- */
-
-#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
- ((FLAG) == QSPI_FLAG_TO) || \
- ((FLAG) == QSPI_FLAG_SM) || \
- ((FLAG) == QSPI_FLAG_FT) || \
- ((FLAG) == QSPI_FLAG_TC) || \
- ((FLAG) == QSPI_FLAG_TE))
-
-#define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup QSPI_Private_Functions QSPI Private Functions
- * @{
- */
+* @}
+*/
+/* End of private macros -----------------------------------------------------*/
/**
* @}
@@ -809,22 +740,14 @@
/**
* @}
- */
+ */
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||
- STM32F413xx || STM32F423xx */
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_QSPI_H */
+#endif /* STM32F4xx_HAL_QSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_ll_fmpi2c.h b/Inc/stm32f4xx_ll_fmpi2c.h
new file mode 100644
index 0000000..b3779a4
--- /dev/null
+++ b/Inc/stm32f4xx_ll_fmpi2c.h
@@ -0,0 +1,2191 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmpi2c.h
+ * @author MCD Application Team
+ * @brief Header file of FMPI2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_FMPI2C_H
+#define STM32F4xx_LL_FMPI2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (FMPI2C1)
+
+/** @defgroup FMPI2C_LL FMPI2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Private_Constants FMPI2C Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_Private_Macros FMPI2C Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_ES_INIT FMPI2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */
+
+ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+ This parameter must be set by referring to the STM32CubeMX Tool and
+ the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS()
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */
+
+ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION
+
+ This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */
+
+ uint32_t DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */
+
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1
+
+ This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */
+} LL_FMPI2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Constants FMPI2C Exported Constants
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_FMPI2C_WriteReg function
+ * @{
+ */
+#define LL_FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF /*!< Address Matched flag */
+#define LL_FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF /*!< Not Acknowledge flag */
+#define LL_FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF /*!< Stop detection flag */
+#define LL_FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF /*!< Bus error flag */
+#define LL_FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF /*!< Arbitration Lost flag */
+#define LL_FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF /*!< Overrun/Underrun flag */
+#define LL_FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF /*!< PEC error flag */
+#define LL_FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF /*!< Timeout detection flag */
+#define LL_FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF /*!< Alert flag */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_FMPI2C_ReadReg function
+ * @{
+ */
+#define LL_FMPI2C_ISR_TXE FMPI2C_ISR_TXE /*!< Transmit data register empty */
+#define LL_FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS /*!< Transmit interrupt status */
+#define LL_FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE /*!< Receive data register not empty */
+#define LL_FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR /*!< Address matched (slave mode) */
+#define LL_FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF /*!< Not Acknowledge received flag */
+#define LL_FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF /*!< Stop detection flag */
+#define LL_FMPI2C_ISR_TC FMPI2C_ISR_TC /*!< Transfer Complete (master mode) */
+#define LL_FMPI2C_ISR_TCR FMPI2C_ISR_TCR /*!< Transfer Complete Reload */
+#define LL_FMPI2C_ISR_BERR FMPI2C_ISR_BERR /*!< Bus error */
+#define LL_FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO /*!< Arbitration lost */
+#define LL_FMPI2C_ISR_OVR FMPI2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
+#define LL_FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
+#define LL_FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY /*!< Bus busy */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_FMPI2C_ReadReg and LL_FMPI2C_WriteReg functions
+ * @{
+ */
+#define LL_FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE /*!< TX Interrupt enable */
+#define LL_FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE /*!< RX Interrupt enable */
+#define LL_FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
+#define LL_FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
+#define LL_FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
+#define LL_FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
+#define LL_FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */
+#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+ * @{
+ */
+#define LL_FMPI2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
+#define LL_FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF /*!< Analog filter is disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+ * @{
+ */
+#define LL_FMPI2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
+#define LL_FMPI2C_ADDRESSING_MODE_10BIT FMPI2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_FMPI2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
+#define LL_FMPI2C_OWNADDRESS1_10BIT FMPI2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+ * @{
+ */
+#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_FMPI2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
+#define LL_FMPI2C_NACK FMPI2C_CR2_NACK /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_ADDRSLAVE Slave Address Length
+ * @{
+ */
+#define LL_FMPI2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
+#define LL_FMPI2C_ADDRSLAVE_10BIT FMPI2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_REQUEST Transfer Request Direction
+ * @{
+ */
+#define LL_FMPI2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
+#define LL_FMPI2C_REQUEST_READ FMPI2C_CR2_RD_WRN /*!< Master request a read transfer. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode
+ * @{
+ */
+#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */
+#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode with no HW PEC comparison. */
+#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode with no HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation
+ * @{
+ */
+#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
+#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Start for write request. */
+#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
+#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+ * @{
+ */
+#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
+#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+ * @{
+ */
+#define LL_FMPI2C_SMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_FMPI2C_SMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
+#define LL_FMPI2C_SMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Macros FMPI2C Exported Macros
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in FMPI2C register
+ * @param __INSTANCE__ FMPI2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_FMPI2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in FMPI2C register
+ * @param __INSTANCE__ FMPI2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_FMPI2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+ * @{
+ */
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+ * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+ * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+ * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FMPI2C_LL_Exported_Functions FMPI2C Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPI2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable FMPI2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_FMPI2C_Enable
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_Enable(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
+}
+
+/**
+ * @brief Disable FMPI2C peripheral (PE = 0).
+ * @note When PE = 0, the FMPI2C SCL and SDA lines are released.
+ * Internal state machines and status bits are put back to their reset value.
+ * When cleared, PE must be kept low for at least 3 APB clock cycles.
+ * @rmtoll CR1 PE LL_FMPI2C_Disable
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the FMPI2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_FMPI2C_IsEnabled
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure Noise Filters (Analog and Digital).
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * The filters can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_ConfigFilters\n
+ * CR1 DNF LL_FMPI2C_ConfigFilters
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE
+ * @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF | FMPI2C_CR1_DNF, AnalogFilter | (DigitalFilter << FMPI2C_CR1_DNF_Pos));
+}
+
+/**
+ * @brief Configure Digital Noise Filter.
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 DNF LL_FMPI2C_SetDigitalFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_t DigitalFilter)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_DNF, DigitalFilter << FMPI2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Get the current Digital Noise Filter configuration.
+ * @rmtoll CR1 DNF LL_FMPI2C_GetDigitalFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Enable Analog Noise Filter.
+ * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_EnableAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Disable Analog Noise Filter.
+ * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_DisableAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Check if Analog Noise Filter is enabled or disabled.
+ * @rmtoll CR1 ANFOFF LL_FMPI2C_IsEnabledAnalogFilter
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_EnableDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_DisableDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR1 TXDMAEN LL_FMPI2C_IsEnabledDMAReq_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_EnableDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_DisableDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR1 RXDMAEN LL_FMPI2C_IsEnabledDMAReq_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll TXDR TXDATA LL_FMPI2C_DMA_GetRegAddr\n
+ * RXDR RXDATA LL_FMPI2C_DMA_GetRegAddr
+ * @param FMPI2Cx FMPI2C Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction)
+{
+ register uint32_t data_reg_addr;
+
+ if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TXDR register */
+ data_reg_addr = (uint32_t) & (FMPI2Cx->TXDR);
+ }
+ else
+ {
+ /* return address of RXDR register */
+ data_reg_addr = (uint32_t) & (FMPI2Cx->RXDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_EnableClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_DisableClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_FMPI2C_IsEnabledClockStretching
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_FMPI2C_EnableSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
+}
+
+/**
+ * @brief Disable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_FMPI2C_DisableSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
+}
+
+/**
+ * @brief Check if hardware byte control in slave mode is enabled or disabled.
+ * @rmtoll CR1 SBC LL_FMPI2C_IsEnabledSlaveByteControl
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 GCEN LL_FMPI2C_EnableGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 GCEN LL_FMPI2C_DisableGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 GCEN LL_FMPI2C_IsEnabledGeneralCall
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
+ * @note Changing this bit is not allowed, when the START bit is set.
+ * @rmtoll CR2 ADD10 LL_FMPI2C_SetMasterAddressingMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param AddressingMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t AddressingMode)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+ * @brief Get the Master addressing mode.
+ * @rmtoll CR2 ADD10 LL_FMPI2C_GetMasterAddressingMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 OA1 LL_FMPI2C_SetOwnAddress1\n
+ * OAR1 OA1MODE LL_FMPI2C_SetOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_FMPI2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetOwnAddress1(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1 | FMPI2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_EnableOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_DisableOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR1 OA1EN LL_FMPI2C_IsEnabledOwnAddress1
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 OA2 LL_FMPI2C_SetOwnAddress2\n
+ * OAR2 OA2MSK LL_FMPI2C_SetOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+ * @param OwnAddrMask This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_NOMASK
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK01
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK02
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK03
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK04
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK05
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK06
+ * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK07
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetOwnAddress2(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+ MODIFY_REG(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2 | FMPI2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_EnableOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_DisableOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 OA2EN LL_FMPI2C_IsEnabledOwnAddress2
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0).
+ * @rmtoll TIMINGR TIMINGR LL_FMPI2C_SetTiming
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+ * @note This parameter is computed with the STM32CubeMX Tool.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timing)
+{
+ WRITE_REG(FMPI2Cx->TIMINGR, Timing);
+}
+
+/**
+ * @brief Get the Timing Prescaler setting.
+ * @rmtoll TIMINGR PRESC LL_FMPI2C_GetTimingPrescaler
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+ * @brief Get the SCL low period setting.
+ * @rmtoll TIMINGR SCLL LL_FMPI2C_GetClockLowPeriod
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+ * @brief Get the SCL high period setting.
+ * @rmtoll TIMINGR SCLH LL_FMPI2C_GetClockHighPeriod
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+ * @brief Get the SDA hold time.
+ * @rmtoll TIMINGR SDADEL LL_FMPI2C_GetDataHoldTime
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+ * @brief Get the SDA setup time.
+ * @rmtoll TIMINGR SCLDEL LL_FMPI2C_GetDataSetupTime
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n
+ * CR1 SMBDEN LL_FMPI2C_SetMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_I2C
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n
+ * CR1 SMBDEN LL_FMPI2C_GetMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_I2C
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_EnableSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_DisableSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the SMBus Clock Timeout.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIDLE LL_FMPI2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIMEOUTB LL_FMPI2C_ConfigSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @param TimeoutB
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+ uint32_t TimeoutB)
+{
+ MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB,
+ TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+ * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note These bits can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA setting.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+ * @brief Set the SMBus Clock TimeoutA mode.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This bit can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA mode.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE));
+}
+
+/**
+ * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note These bits can only be programmed when TimeoutB is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutB)
+{
+ WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Enable the SMBus Clock Timeout.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ SET_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Disable the SMBus Clock Timeout.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ CLEAR_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Check if the SMBus Clock Timeout is enabled or disabled.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
+{
+ return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_FMPI2C_EnableIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
+}
+
+/**
+ * @brief Disable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_FMPI2C_DisableIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
+}
+
+/**
+ * @brief Check if the TXIS Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXIE LL_FMPI2C_IsEnabledIT_TX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_FMPI2C_EnableIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_FMPI2C_DisableIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXIE LL_FMPI2C_IsEnabledIT_RX
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_EnableIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Disable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_DisableIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Check if Address match interrupt is enabled or disabled.
+ * @rmtoll CR1 ADDRIE LL_FMPI2C_IsEnabledIT_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_EnableIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Disable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_DisableIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Check if Not acknowledge received interrupt is enabled or disabled.
+ * @rmtoll CR1 NACKIE LL_FMPI2C_IsEnabledIT_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_EnableIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Disable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_DisableIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Check if STOP detection interrupt is enabled or disabled.
+ * @rmtoll CR1 STOPIE LL_FMPI2C_IsEnabledIT_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_FMPI2C_EnableIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_FMPI2C_DisableIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
+}
+
+/**
+ * @brief Check if Transfer Complete interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_FMPI2C_IsEnabledIT_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_FMPI2C_EnableIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_FMPI2C_DisableIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR1 ERRIE LL_FMPI2C_IsEnabledIT_ERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXE LL_FMPI2C_IsActiveFlag_TXE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transmit interrupt flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXIS LL_FMPI2C_IsActiveFlag_TXIS
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll ISR RXNE LL_FMPI2C_IsActiveFlag_RXNE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the received slave address matched with one of the enabled slave address.
+ * @rmtoll ISR ADDR LL_FMPI2C_IsActiveFlag_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Not Acknowledge received flag.
+ * @note RESET: Clear default value.
+ * SET: When a NACK is received after a byte transmission.
+ * @rmtoll ISR NACKF LL_FMPI2C_IsActiveFlag_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag.
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll ISR STOPF LL_FMPI2C_IsActiveFlag_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+ * @rmtoll ISR TC LL_FMPI2C_IsActiveFlag_TC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=1 and NBYTES date have been transferred.
+ * @rmtoll ISR TCR LL_FMPI2C_IsActiveFlag_TCR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll ISR BERR LL_FMPI2C_IsActiveFlag_BERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll ISR ARLO LL_FMPI2C_IsActiveFlag_ARLO
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll ISR OVR LL_FMPI2C_IsActiveFlag_OVR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When the received PEC does not match with the PEC register content.
+ * @rmtoll ISR PECERR LL_FMPI2C_IsActiveSMBusFlag_PECERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When a timeout or extended clock timeout occurs.
+ * @rmtoll ISR TIMEOUT LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When SMBus host configuration, SMBus alert enabled and
+ * a falling edge event occurs on SMBA pin.
+ * @rmtoll ISR ALERT LL_FMPI2C_IsActiveSMBusFlag_ALERT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll ISR BUSY LL_FMPI2C_IsActiveFlag_BUSY
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @rmtoll ICR ADDRCF LL_FMPI2C_ClearFlag_ADDR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ADDRCF);
+}
+
+/**
+ * @brief Clear Not Acknowledge flag.
+ * @rmtoll ICR NACKCF LL_FMPI2C_ClearFlag_NACK
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_NACKCF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @rmtoll ICR STOPCF LL_FMPI2C_ClearFlag_STOP
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_STOPCF);
+}
+
+/**
+ * @brief Clear Transmit data register empty flag (TXE).
+ * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
+ * @rmtoll ISR TXE LL_FMPI2C_ClearFlag_TXE
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
+{
+ WRITE_REG(FMPI2Cx->ISR, FMPI2C_ISR_TXE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll ICR BERRCF LL_FMPI2C_ClearFlag_BERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_BERRCF);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll ICR ARLOCF LL_FMPI2C_ClearFlag_ARLO
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ARLOCF);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll ICR OVRCF LL_FMPI2C_ClearFlag_OVR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_OVRCF);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_PECCF);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_TIMOUTCF);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ALERTCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPI2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable automatic STOP condition generation (master mode).
+ * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+ * This bit has no effect in slave mode or when RELOAD bit is set.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_EnableAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Disable automatic STOP condition generation (master mode).
+ * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_DisableAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Check if automatic STOP condition is enabled or disabled.
+ * @rmtoll CR2 AUTOEND LL_FMPI2C_IsEnabledAutoEndMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable reload mode (master mode).
+ * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+ * @rmtoll CR2 RELOAD LL_FMPI2C_EnableReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Disable reload mode (master mode).
+ * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+ * @rmtoll CR2 RELOAD LL_FMPI2C_DisableReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Check if reload mode is enabled or disabled.
+ * @rmtoll CR2 RELOAD LL_FMPI2C_IsEnabledReloadMode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the number of bytes for transfer.
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 NBYTES LL_FMPI2C_SetTransferSize
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferSize)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES, TransferSize << FMPI2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Get the number of bytes configured for transfer.
+ * @rmtoll CR2 NBYTES LL_FMPI2C_GetTransferSize
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @note Usage in Slave mode only.
+ * @rmtoll CR2 NACK LL_FMPI2C_AcknowledgeNextData
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ACK
+ * @arg @ref LL_FMPI2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_AcknowledgeNextData(FMPI2C_TypeDef *FMPI2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or FMPI2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR2 START LL_FMPI2C_GenerateStartCondition
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_GenerateStartCondition(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR2 STOP LL_FMPI2C_GenerateStopCondition
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_STOP);
+}
+
+/**
+ * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master sends the complete 10bit slave address read sequence :
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_EnableAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master only sends the first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_DisableAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+ * @rmtoll CR2 HEAD10R LL_FMPI2C_IsEnabledAuto10BitRead
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure the transfer direction (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 RD_WRN LL_FMPI2C_SetTransferRequest
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param TransferRequest This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_REQUEST_WRITE
+ * @arg @ref LL_FMPI2C_REQUEST_READ
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferRequest)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+ * @brief Get the transfer direction requested (master mode).
+ * @rmtoll CR2 RD_WRN LL_FMPI2C_GetTransferRequest
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_REQUEST_WRITE
+ * @arg @ref LL_FMPI2C_REQUEST_READ
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN));
+}
+
+/**
+ * @brief Configure the slave address for transfer (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 SADD LL_FMPI2C_SetSlaveAddr
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+ * @brief Get the slave address programmed for transfer.
+ * @rmtoll CR2 SADD LL_FMPI2C_GetSlaveAddr
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD));
+}
+
+/**
+ * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @rmtoll CR2 SADD LL_FMPI2C_HandleTransfer\n
+ * CR2 ADD10 LL_FMPI2C_HandleTransfer\n
+ * CR2 RD_WRN LL_FMPI2C_HandleTransfer\n
+ * CR2 START LL_FMPI2C_HandleTransfer\n
+ * CR2 STOP LL_FMPI2C_HandleTransfer\n
+ * CR2 RELOAD LL_FMPI2C_HandleTransfer\n
+ * CR2 NBYTES LL_FMPI2C_HandleTransfer\n
+ * CR2 AUTOEND LL_FMPI2C_HandleTransfer\n
+ * CR2 HEAD10R LL_FMPI2C_HandleTransfer
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param SlaveAddr Specifies the slave address to be programmed.
+ * @param SlaveAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_ADDRSLAVE_7BIT
+ * @arg @ref LL_FMPI2C_ADDRSLAVE_10BIT
+ * @param TransferSize Specifies the number of bytes to be programmed.
+ * This parameter must be a value between Min_Data=0 and Max_Data=255.
+ * @param EndMode This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_MODE_RELOAD
+ * @arg @ref LL_FMPI2C_MODE_AUTOEND
+ * @arg @ref LL_FMPI2C_MODE_SOFTEND
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_RELOAD
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC
+ * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_FMPI2C_GENERATE_NOSTARTSTOP
+ * @arg @ref LL_FMPI2C_GENERATE_STOP
+ * @arg @ref LL_FMPI2C_GENERATE_START_READ
+ * @arg @ref LL_FMPI2C_GENERATE_START_WRITE
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_READ
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_READ
+ * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+ MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD |
+ FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R,
+ SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request);
+}
+
+/**
+ * @brief Indicate the value of transfer direction (slave mode).
+ * @note RESET: Write transfer, Slave enters in receiver mode.
+ * SET: Read transfer, Slave enters in transmitter mode.
+ * @rmtoll ISR DIR LL_FMPI2C_GetTransferDirection
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FMPI2C_DIRECTION_WRITE
+ * @arg @ref LL_FMPI2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR));
+}
+
+/**
+ * @brief Return the slave matched address.
+ * @rmtoll ISR ADDCODE LL_FMPI2C_GetAddressMatchCode
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+ * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+ * This bit has no effect when RELOAD bit is set.
+ * This bit has no effect in device mode when SBC bit is not set.
+ * @rmtoll CR2 PECBYTE LL_FMPI2C_EnableSMBusPECCompare
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
+{
+ SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
+ * SMBus feature is supported by the FMPI2Cx Instance.
+ * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+*/
+__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC));
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll RXDR RXDATA LL_FMPI2C_ReceiveData8
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx)
+{
+ return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll TXDR TXDATA LL_FMPI2C_TransmitData8
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Data)
+{
+ WRITE_REG(FMPI2Cx->TXDR, Data);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup FMPI2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
+ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx);
+void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C1 */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_FMPI2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_ll_gpio.h b/Inc/stm32f4xx_ll_gpio.h
index 8ff86ac..3f1b3a1 100644
--- a/Inc/stm32f4xx_ll_gpio.h
+++ b/Inc/stm32f4xx_ll_gpio.h
@@ -340,11 +340,10 @@
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
- MODIFY_REG(GPIOx->OTYPER, (GPIO_OTYPER_OT_0 << POSITION_VAL(Pin)), (OutputType << POSITION_VAL(Pin)));
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
}
-
/**
* @brief Return gpio output type for several pins on dedicated port.
diff --git a/Inc/stm32f4xx_ll_usb.h b/Inc/stm32f4xx_ll_usb.h
index a1f31b3..2f1907f 100644
--- a/Inc/stm32f4xx_ll_usb.h
+++ b/Inc/stm32f4xx_ll_usb.h
@@ -155,7 +155,7 @@
typedef struct
{
- uint8_t dev_addr ; /*!< USB device address.
+ uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
@@ -199,10 +199,10 @@
uint32_t ErrCnt; /*!< Host channel error count.*/
- USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
- USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -237,11 +237,11 @@
/** @defgroup USB_LL Device Speed
* @{
*/
-#define USBD_HS_SPEED 0U
-#define USBD_HSINFS_SPEED 1U
-#define USBH_HS_SPEED 0U
-#define USBD_FS_SPEED 2U
-#define USBH_FS_SPEED 1U
+#define USBD_HS_SPEED 0U
+#define USBD_HSINFS_SPEED 1U
+#define USBH_HS_SPEED 0U
+#define USBD_FS_SPEED 2U
+#define USBH_FSLS_SPEED 1U
/**
* @}
*/
@@ -269,11 +269,11 @@
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
-#define USBD_HS_TRDT_VALUE 9U
+#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
-#define USBD_FS_TRDT_VALUE 5U
-#define USBD_DEFAULT_TRDT_VALUE 9U
+#define USBD_FS_TRDT_VALUE 5U
+#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
@@ -282,9 +282,9 @@
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
-#define USB_OTG_HS_MAX_PACKET_SIZE 512U
-#define USB_OTG_FS_MAX_PACKET_SIZE 64U
-#define USB_OTG_MAX_EP0_SIZE 64U
+#define USB_OTG_HS_MAX_PACKET_SIZE 512U
+#define USB_OTG_FS_MAX_PACKET_SIZE 64U
+#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
@@ -294,7 +294,6 @@
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
@@ -403,7 +402,7 @@
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-#define EP_ADDR_MSK 0xFU
+#define EP_ADDR_MSK 0xFU
/**
* @}
*/
@@ -468,13 +467,9 @@
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
diff --git a/License.md b/License.md
index 62f908f..84a7fc4 100644
--- a/License.md
+++ b/License.md
@@ -1,3 +1,3 @@
# Copyright (c) 2016 STMicroelectronics
-This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
+This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
diff --git a/README.md b/README.md
index e22273f..c1a6aa5 100644
--- a/README.md
+++ b/README.md
@@ -5,27 +5,31 @@
**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
- * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
- * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
- * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
- * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
- * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+ * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio.
+ * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series.
+ * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library...
+ * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series.
Two models of publication are proposed for the STM32Cube embedded software:
- * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
+ * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
* The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
## Description
-This **stm32f4xx_hal_driver** MCU component repo is one element of the STM32CubeF4 MCU embedded software package, providing the **HAL-LL Drivers** part.
+This **stm32f4xx_hal_driver** MCU component repository is one element of the STM32CubeF4 MCU embedded software package, providing the **HAL-LL Drivers** part.
## License
Copyright (c) 2016 STMicroelectronics.
-This software component is licensed by STMicroelectronics under BSD 3-Clause license. You may not use this file except in compliance with the License.
+This software component is licensed by STMicroelectronics under BSD-3-Clause license. You may not use this file except in compliance with the License.
You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause).
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32f4xx_hal_driver/blob/master/Release_Notes.html).
+
## Compatibility information
In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
@@ -34,13 +38,14 @@
HAL Driver F4 | CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
-Tag v1.7.6 | Tag v2.6.3 | Tag v5.4.0_cm4 | Tag v1.24.1 (and following, if any, till next new tag)
-Tag v1.7.7 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.24.2 (and following, if any, till next new tag)
+Tag v1.7.6 | Tag v2.6.3 | Tag v5.4.0_cm4 | Tag v1.24.1 (and following, if any, till next tag)
+Tag v1.7.7 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.24.2 (and following, if any, till next tag)
+Tag v1.7.8 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.25.0 (and following, if any, till next tag)
The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4).
## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32f4xx_hal_driver/issues/new).
+If you have any issue with the **Software content** of this repository, you can file an issue into the firmware repository [STM32CubeF4](https://github.com/STMicroelectronics/STM32CubeF4/issues/new/choose).
For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index 0c67712..15c86e0 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -29,6 +29,11 @@
+
+
+
+
+
<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
<link rel="File-List" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/filelist.xml">
<link rel="Edit-Time-Data" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/editdata.mso"><!--[if !mso]>
@@ -907,8 +912,7 @@
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1"/>
</o:shapelayout></xml><![endif]-->
- <meta content="MCD Application Team" name="author"></head>
-<body link="blue" vlink="blue">
+ <meta content="MCD Application Team" name="author"></head><body link="blue" vlink="blue">
<div class="WordSection1">
@@ -940,8 +944,61 @@
<td style="padding: 0in;" valign="top">
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
<tbody><tr><td style="padding: 0in;" valign="top">
- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.7 / 06-December-2019</span></h3>
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.8 / 12-February-2020</span></h3>
+
+
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+
+
+
+
+ <span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span>
+ <ul style="margin-top: 0cm;" type="disc">
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new <span style="font-weight: bold;">HAL FMPSMBUS</span> and <span style="font-weight: bold;">LL FMPI2C</span> drivers</span></li>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">General updates to fix known defects and
+ enhancements implementation</span></li>
+</ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span>
+ <ul style="margin-top: 0cm;" type="disc">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL CRYP driver to support block by block decryption without reinitializes the IV and KEY for each call.</span></li>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Improve code quality by fixing MisraC-2012 violations<br>
+ <br>
+ </span></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL/LL USB </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Add handling USB host babble error interrupt</span></li>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Fix Enabling ULPI interface for platforms that integrates USB HS PHY</span></li>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Fix Host data toggling for IN Iso transfers</span></li>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Ensure to disable USB EP during endpoint deactivation<br>
+</span></li>
+</ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL CRYP </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> Update HAL CRYP driver to support block by block decryption without initializing the IV and KEY at each call.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><br>
+ </li>
+ <ul>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new CRYP Handler parameters: "KeyIVConfig" and "SizesSum"</span></li>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new CRYP init parameter: "KeyIVConfigSkip"<br>
+</span></li>
+ </ul>
+</ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL I2S </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li>
+ <ul>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_I2S_DMAStop() API to be more safe</span></li>
+ <ul>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add a check on BSY, TXE and RXNE flags before disabling the I2S</span></li>
+ </ul>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer).<br>
+</span></li>
+ <ul>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.</span></li>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX<br>
+ </span></li>
+ </ul>
+ </ul>
+
+ </ul>
+
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.7 / 06-December-2019</span></h3>
+
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
@@ -1019,7 +1076,7 @@
condition and handle it before clearing the ADDR flag</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL NAND </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
HAL_NAND_Write_Page_8b(), HAL_NAND_Write_Page_16b() and
HAL_NAND_Write_SpareArea_16b() to manage correctly the time out
-condition.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL SAI </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Optimize SAI_DMATxCplt() and SAI_DMARxCplt() APIs to check on "Mode" parameter instead of CIRC bit in the CR register.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove unused SAI_FIFO_SIZE define</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_SAI_Receive_DMA() programming sequence to be inline with reference manual<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.6 / 12-April-2019</span></h3>
+condition.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL SAI </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Optimize SAI_DMATxCplt() and SAI_DMARxCplt() APIs to check on "Mode" parameter instead of CIRC bit in the CR register.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove unused SAI_FIFO_SIZE define</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_SAI_Receive_DMA() programming sequence to be inline with reference manual<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.6 / 12-April-2019</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
@@ -1044,7 +1101,7 @@
CodeSonar warning on PCD_Port_IRQHandler() and HCD_Port_IRQHandler()
interrupt handlers<o:p></o:p></span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.5 / 08-February-2019</span></h3>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.5 / 08-February-2019</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
@@ -1436,9 +1493,9 @@
<span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></span>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.4 / 02-February-2018</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.4 / 02-February-2018</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
-to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update UNUSED() macro implementation to avoid GCC warning</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">The warning is detected when the UNUSED() macro is called from C++ file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the prototypes of the following APIs after change on RAMFUNC defines </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_StopFlashInterfaceClk()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_StartFlashInterfaceClk()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_EnableFlashSleepMode()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_DisableFlashSleepMode()<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.3 / 22-December-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update UNUSED() macro implementation to avoid GCC warning</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">The warning is detected when the UNUSED() macro is called from C++ file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the prototypes of the following APIs after change on RAMFUNC defines </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_StopFlashInterfaceClk()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_StartFlashInterfaceClk()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_EnableFlashSleepMode()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASHEx_DisableFlashSleepMode()<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.3 / 22-December-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on older HAL versions</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">Rework of HAL CAN driver (compatibility break) </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">A
new HAL CAN driver has been redesigned with new APIs, to bypass
@@ -1470,7 +1527,7 @@
allowing to get the HSE clock divider for RTC peripheral</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Ensure reset of CIR and CSR
registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update HAL_RCC_OscConfig() to keep backup domain enabled when configuring respectively LSE and RTC clock source</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new HAL interfaces allowing to control the activation or deactivation of PLLI2S and PLLSAI:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HAL_RCCEx_EnablePLLI2S()</span></li></ul></ul><ul style="margin-top: 0cm;" type="square"><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HAL_RCCEx_DisablePLLI2S()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_RCCEx_EnablePLLSAI()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">HAL_RCCEx_DisablePLLSAI()</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RCC</span> update </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new LL RCC macro </span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_RCC_PLL_SetMainSource()
allowing to configure PLL main clock source</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL FMC / LL FSMC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add clear of the PTYP bit to select the PCARD mode in </span><span style="font-size: 10pt; font-family: Verdana;">FMC_PCCARD_Init() / </span><span style="font-size: 10pt; font-family: Verdana;">FSMC_PCCARD_Init()</span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.2 / 06-October-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.2 / 06-October-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix compilation warning with GCC compiler</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt; font-weight: normal;">Remove Date and version from header files</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">POSITION_VAL() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_hal_def.h file changes: </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update __weak and __packed defined values for ARM compiler</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_ll_system.h file: add LL_SYSCFG_REMAP_SDRAM define</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ADC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong definition of ADC channel temperature sensor for STM32F413xx and STM32F423xx devices.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update values for the following defines: DMA_FLAG_FEIF0_4 and </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">DMA_FLAG_DMEIF0_4 </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DSI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix Extra warning with SW4STM32 compiler</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix DSI display issue when using EWARM w/ high level optimization </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix MISRAC errors</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL FMPI2C </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
Interface APIs headers to remove confusing message about device address</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
@@ -1501,7 +1558,7 @@
<p class="MsoListParagraph" style="margin: 4.5pt 0cm 4.5pt 36pt; text-indent: -18pt;"><span style="font-size: 10pt; font-family: Symbol; color: black;" lang="EN-US"><span style=""></span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"><o:p></o:p></span></p>
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RNG </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_RNG_Init() remove Lock()/Unlock()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL MMC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_MMC_Erase() API: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add missing () to fix compilation warning </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">detected </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">with SW4STM32 when extra feature is enabled.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_RTC_Init() API: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">update to force the wait for synchro before setting TAFCR register when BYPSHAD bit in CR register is 0.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update I2S DMA fullduplex process to handle I2S Rx and Tx DMA Half transfer complete callback</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIMEx_OCN_xxxx() and HAL_TIMEx_PWMN_xxx() API description to remove support of TIM_CHANNEL_4</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to clear DMA flags using WRITE_REG() instead SET_REG() API to avoid read access to the IFCR register that is write only.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL RTC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix warning with static analyzer</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USART </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add assert macros to check USART BaudRate register</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL I2C </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Rename IS_I2C_CLOCK_SPEED()
and IS_I2C_DUTY_CYCLE() respectively to IS_LL_I2C_CLOCK_SPEED() and
- IS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in TIM CR1 register instead of setting it.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in TIM CR1 register instead of clearing it.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USART </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix MISRA error w/ IS_LL_USART_BRR() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix wrong check when UART10 instance is used</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.1 / 14-April-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+ IS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in TIM CR1 register instead of setting it.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in TIM CR1 register instead of clearing it.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USART </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix MISRA error w/ IS_LL_USART_BRR() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix wrong check when UART10 instance is used</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.1 / 14-April-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update CHM UserManuals to support LL drivers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
@@ -1515,7 +1572,7 @@
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWREx_EnterUnderDriveSTOPMode() API: remove check on UDRDY flag</span></li></ul></ul>
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL ADC </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix wrong ADC group injected sequence configuration</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">LL_ADC_INJ_SetSequencerRanks()
and LL_ADC_INJ_GetSequencerRanks() API's update to take in
-consideration the ADC number of conversions</span></li></ul></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">defined values for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> ADC group injected seqencer ranks </span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.0 / 17-February-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+consideration the ADC number of conversions</span></li></ul></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">defined values for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> ADC group injected seqencer ranks </span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.0 / 17-February-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: bold; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add Low Layer drivers allowing performance and footprint optimization</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low
@@ -1541,10 +1598,10 @@
the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">I2S clock input frequency
calculation </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">to HAL RCC driver.</span></li><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update the
HAL I2SEx driver to keep only full duplex feature.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2S_Init() API updated to</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Fix wrong I2S clock calculation when PCM mode is used.</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Return state </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2S_ERROR_PRESCALER</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> when the I2S clock is wrongly configured</span></li></ul></ul></ul>
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL LTDC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Optimize HAL_LTDC_IRQHandler() function by using direct register read</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Rename the following API's</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_Relaod() by HAL_LTDC_Reload()</span><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr"> </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Remove unused asserts</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL USB</span><span class="Apple-converted-space"> <span style="font-weight: bold;">PCD</span> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Flush all TX FIFOs on USB Reset</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's</span></li></ul></ul><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr"></span><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL USB</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Enable DMA Burst mode for USB OTG HS</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Fix SD card detection issue</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL SDMMC</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Arial",sans-serif; color: rgb(0, 32, 82);" lang="EN-US"><span style=""></span></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.6.0 / 04-November-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL LTDC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Optimize HAL_LTDC_IRQHandler() function by using direct register read</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Rename the following API's</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_Relaod() by HAL_LTDC_Reload()</span><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr"> </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Remove unused asserts</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL USB</span><span class="Apple-converted-space"> <span style="font-weight: bold;">PCD</span> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Flush all TX FIFOs on USB Reset</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's</span></li></ul></ul><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr"></span><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL USB</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Enable DMA Burst mode for USB OTG HS</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Fix SD card detection issue</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL SDMMC</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Arial",sans-serif; color: rgb(0, 32, 82);" lang="EN-US"><span style=""></span></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.6.0 / 04-November-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">support of<span class="Apple-converted-space"> </span><b>STM32F413xx and </b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><b>STM32F423xx</b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CAN</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update to add the support of 3 CAN management</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CRYP</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update to add the support of AES features</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL DFSDM</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add definitions for new external trigger filters</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add definition for new Channels 4, 5, 6 and 7</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important;">Add functions and API for Filter state configuration and management</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Add new functions: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitstreamClock_Start()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitstreamClock_Stop()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitStreamClkDistribution_Config() </span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL DMA</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add the support of DMA Channels from 8 to 15</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update HAL_DMA_DeInit() function with the check on DMA stream instance</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL DSI</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL FLASH</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Enhance FLASH_WaitForLastOperation() function implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update __HAL_FLASH_GET_FLAG() macro implementation<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL GPIO</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add specific alternate functions definitions</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL I2C </span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update I2C_DMAError() function implementation to ignore DMA FIFO error</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL I2S </span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL IRDA</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Add new functions and call backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmitCpltCallback()<o:p></o:p></span></li></ul></ul><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceiveCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL PCD</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update HAL_PCD_GetRxCount() function implementation</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL RCC</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update __HAL_RCC_HSE_CONFIG() macro implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update<span class="Apple-converted-space"> </span></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">__HAL_RCC_LSE_CONFIG() macro implementation</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SMARTCARD</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Add new functions and call backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmitCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceiveCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL TIM</span><span class="Apple-converted-space"><span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL UART<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add Transfer abort functions and callbacks</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL USART<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add Transfer abort functions and callbacks</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.2 / 22-September-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">support of<span class="Apple-converted-space"> </span><b>STM32F413xx and </b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><b>STM32F423xx</b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CAN</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update to add the support of 3 CAN management</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CRYP</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update to add the support of AES features</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL DFSDM</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add definitions for new external trigger filters</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add definition for new Channels 4, 5, 6 and 7</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important;">Add functions and API for Filter state configuration and management</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Add new functions: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitstreamClock_Start()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitstreamClock_Stop()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitStreamClkDistribution_Config() </span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL DMA</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add the support of DMA Channels from 8 to 15</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update HAL_DMA_DeInit() function with the check on DMA stream instance</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL DSI</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL FLASH</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Enhance FLASH_WaitForLastOperation() function implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update __HAL_FLASH_GET_FLAG() macro implementation<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL GPIO</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add specific alternate functions definitions</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL I2C </span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update I2C_DMAError() function implementation to ignore DMA FIFO error</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL I2S </span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL IRDA</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Add new functions and call backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmitCpltCallback()<o:p></o:p></span></li></ul></ul><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceiveCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL PCD</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update HAL_PCD_GetRxCount() function implementation</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL RCC</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update __HAL_RCC_HSE_CONFIG() macro implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update<span class="Apple-converted-space"> </span></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">__HAL_RCC_LSE_CONFIG() macro implementation</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SMARTCARD</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Add new functions and call backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmitCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceiveCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL TIM</span><span class="Apple-converted-space"><span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL UART<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add Transfer abort functions and callbacks</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL USART<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add Transfer abort functions and callbacks</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.2 / 22-September-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL I2C</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong
@@ -1553,7 +1610,7 @@
<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update I2C API's </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">(Polling, IT and DMA interfaces)</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> to manage I2C </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">XferSize and XferCount</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> handle parameters instead of API size parameter to help user to get information of counter in case of error. </span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update Abort functionality to manage DMA use
-case</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL FMPI2C</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update to disable Own Address</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> before setting the </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">new Own Address</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> configuration:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update CAN receive processes to set CAN RxMsg FIFONumber parameter</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL UART </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update UART handle </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">TxXferCount and RxXferCount </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">parameters as volatile to avoid eventual issue with High Speed optimization </span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.1 / 01-July-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+case</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL FMPI2C</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update to disable Own Address</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> before setting the </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">new Own Address</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> configuration:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update CAN receive processes to set CAN RxMsg FIFONumber parameter</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL UART </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update UART handle </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">TxXferCount and RxXferCount </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">parameters as volatile to avoid eventual issue with High Speed optimization </span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.1 / 01-July-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL GPIO</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">HAL_GPIO_Init()/HAL_GPIO_DeInit() API's: update GPIO_GET_INDEX() macro implementation to support all GPIO's</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL SPI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Fix regression issue: retore HAL_SPI_DMAPause() and HAL_SPI_DMAResume() </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">API's</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> </span><span style="color: rgb(31, 73, 125);" lang="EN-US"></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL RCC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Fix FSMC macros compilation warnings with STM32F412Rx devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">HAL_DMA_PollFortransfer() API clean up <br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL PPP </span>update(PPP refers to IRDA, UART, USART and SMARTCARD)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update HAL_PPP_IRQHandler() to add a check on interrupt source before managing the error</span><span style="font-family: "Courier New"; color: rgb(31, 73, 125);" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"> </span></span></span><span style="color: rgb(31, 73, 125);" lang="EN-US"><o:p></o:p></span></li></ul></ul>
@@ -1562,7 +1619,7 @@
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL QSPI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Implement
workaround to fix the limitation </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">pronounced </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> in the Errata
sheet 2.1.8 section: In some specific cases, DMA2 data corruption
-occurs when managing AHB and APB2 peripherals in a concurrent way</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0 / 06-May-2016</span></h3>
+occurs when managing AHB and APB2 peripherals in a concurrent way</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0 / 06-May-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
@@ -1613,7 +1670,7 @@
devices</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> to provide the possibility to convert VrefInt channel when both
VrefInt and Vbat channels are selected.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL SPDIFRX<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver update for wait on flag management optimization<span class="Apple-converted-space"> </span></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL WWDG<span class="Apple-converted-space"> </span></span>update </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall rework of the driver for more efficient implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove the following APIs:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Start()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Start_IT()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_MspDeInit()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_GetState()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update implementation:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Init()</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">A new parameter in the Init Structure: EWIMode</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_MspInit()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Refresh() </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">This function insures the reload of the counter</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">The "counter" parameter has been removed</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_IRQHandler()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback()<br></span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the following example to identify the changes: WWDG_Example</span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.4 / 22-January-2016</span></h3>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.4 / 22-January-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
@@ -1825,11 +1882,11 @@
</li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;">
<span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update the FSMC_NORSRAM_Init() function to use
-BurstAccessMode field properly</span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.4 / 11-December-2015</span></h3><span style="font-size: 10pt; font-family: Arial; color: white;"></span><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+BurstAccessMode field properly</span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.4 / 11-December-2015</span></h3><span style="font-size: 10pt; font-family: Arial; color: white;"></span><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL
weak empty callbacks to prevent unused argument compilation warnings with some
compilers by calling the following line:</span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_ETH_Init() function to add timeout on the Software reset management</span><br><span style="font-size: 10pt; font-family: Arial; color: white;"></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.2 / 10-November-2015</span></h3>
+</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_ETH_Init() function to add timeout on the Software reset management</span><br><span style="font-size: 10pt; font-family: Arial; color: white;"></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.2 / 10-November-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -1842,7 +1899,7 @@
HAL weak empty callbacks to prevent unused argument compilation
warnings with some compilers by calling the following line:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);<br><br></span></li></ul></ul></ul>
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CORTEX </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new macros __HAL_RCC_<span style="font-style: italic;">PPP</span>_IS_CLK_ENABLED() to check on Clock enable/disable status</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update HAL_RCC_MCOConfig() API to use new defines for the GPIO Speed</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Generic update to improve the PLL VCO min value(100MHz): PLLN, PLLI2S and PLLSAI min value is 50 instead of 192</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: rgb(2, 3, 2); font-family: Verdana;" class="MsoNormal"><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">__HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">reset </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">ICRST </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">bit in the ACR register after setting it.</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: rgb(2, 3, 2); font-family: Verdana;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to support until 15 FLASH wait state (FLASH_LATENCY_15) for STM32F446xx devices </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">register </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">instead of vertical blanking reload register.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIM_ConfigClockSource() API to check only the required parameters</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use "=" instead of "|=" to clear flags in the MSR, TSR, RF0R and RF1R registers</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FSMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.1 / 09-October-2015</span></h3>
+<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">register </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">instead of vertical blanking reload register.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIM_ConfigClockSource() API to check only the required parameters</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use "=" instead of "|=" to clear flags in the MSR, TSR, RF0R and RF1R registers</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FSMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.1 / 09-October-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -1859,7 +1916,7 @@
HAL_DSI_ForceRXLowPower(), HAL_DSI_ForceDataLanesInRX(),
HAL_DSI_SetPullDown() and HAL_DSI_SetContentionDetectionOff() functions</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update DSI_HS_PM_ENABLE define value</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Implement
workaround for the hardware limitation: “The time to activate the clock
-between HS transmissions is not calculated correctly”</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0 / 14-August-2015</span></h3>
+between HS transmissions is not calculated correctly”</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0 / 14-August-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -1876,7 +1933,7 @@
HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), applicable only to </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F469xx and STM32F479xx devices</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add
new defines TIM_SYSTEMBREAKINPUT_HARDFAULT,
TIM_SYSTEMBREAKINPUT_PVD and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD,
-applicable only to STM32F410xx devices</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.2 / 26-June-2015</span></h3>
+applicable only to STM32F410xx devices</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.2 / 26-June-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -1897,7 +1954,7 @@
for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef
structure to select the ADC software trigger mode.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> __HAL_FLASH_GET_LATENCY() new macro </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add to get the flash latency</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix the wrong definition of HAL_SPI_ERROR_FLAG literal</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA2D </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_DMA2D_ConfigLayer() API update to use "=" instead of "|=" to erase </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">BGCOLR and</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> FGCOLR registers before setting the new configuration</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HASH_<span style="font-weight: bold;">MODE</span>_Start_IT() </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">(</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">MODE </span>stands for </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">MD5, SHA1, SHA224 and SHA36) updates:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix processing fail for small input buffers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
to unlock the process and call return HAL_OK at the end of HASH
-processing to avoid incorrectly repeating software</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to properly manage the HashITCounter</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> every each 512 bits </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_HASH_GET_FLAG() update to check the right register when the DINNE flag is selected</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HASH_SHA1_Accumulate() updates:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. </span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the following note in API description</span></li></ul></ul></ul><div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></div><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to define </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">hardware </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">independent l</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">iterals names</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PC13 by RTC_TAMPERPIN_DEFAULT</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local variable in USB Host channel re-activation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USB </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">USB_FlushTxFifo API: update to flush all Tx FIFO</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local variable in USB Host channel re-activation</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1 / 25-Mars-2015</span></h3>
+processing to avoid incorrectly repeating software</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to properly manage the HashITCounter</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> every each 512 bits </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_HASH_GET_FLAG() update to check the right register when the DINNE flag is selected</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HASH_SHA1_Accumulate() updates:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. </span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the following note in API description</span></li></ul></ul></ul><div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></div><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to define </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">hardware </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">independent l</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">iterals names</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PC13 by RTC_TAMPERPIN_DEFAULT</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local variable in USB Host channel re-activation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USB </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">USB_FlushTxFifo API: update to flush all Tx FIFO</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local variable in USB Host channel re-activation</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1 / 25-Mars-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -1907,7 +1964,7 @@
<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix compilation issue with STM32F417xx product: update <span style="font-weight: bold;">STM32F17xx</span> by </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">STM32F417xx</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove unused variable to avoid warning with TrueSTUDIO </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2C </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Update busy flag Timeout value</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">I2C Master Receive Processes update to disable ACK before generate the STOP </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DAC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix
-V1.3.0 regression issue with DAC software trigger configuration</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0 / 09-Mars-2015</span></h3>
+V1.3.0 regression issue with DAC software trigger configuration</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0 / 09-Mars-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -1964,7 +2021,7 @@
<div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.<br>
* User should request a
transition to LSE Off first and then LSE On or LSE Bypass.</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></div><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the
-following new macros for PLL source and PLLM selection :<o:p></o:p></span></li><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_PLL_PLLSOURCE_CONFIG()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_PLL_PLLM_CONFIG()</span></li></ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Macros rename:</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_FORCE_RESET() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_FORCE_RESET</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_RELEASE_RESET() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_RELEASE_RESET</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-family: Verdana;" class="MsoNormal"><span style="font-size: 10pt;">Add __HAL_RCC_SYSCLK_CONFIG() </span><span style="font-size: 10pt;">new macro</span><span style="font-size: 10pt;"> to configure the system clock source (</span><span style="font-size: 10pt;">SYSCLK</span><span style="font-size: 10pt;">)</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_RCC_GET_SYSCLK_SOURCE() updates:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new RCC Literals:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_HSI</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_HSE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_PLLCLK</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_PLLRCLK</span></li></ul></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update macro description to refer to the literals above</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span><span style="color: rgb(71, 71, 71); font-family: helvetica,arial,sans-serif; font-size: 26px; font-style: normal; font-variant: normal; font-weight: bold; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);"></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new define PWR_WAKEUP_PIN2</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new API to Control/Get </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">VOS bits of CR register</span></li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWR_HAL_PWREx_ControlVoltageScaling()</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWREx_GetVoltageRange()</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_PWR_</span><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US"> VOLTAGESCALING_CONFIG</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration</span><span style="background: rgb(252, 252, 252) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; font-size: 10pt; font-family: "Helvetica","sans-serif"; color: rgb(2, 3, 2);" lang="EN-US"><span style="text-align: start; float: none; word-spacing: 0px;"> </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the
+following new macros for PLL source and PLLM selection :<o:p></o:p></span></li><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_PLL_PLLSOURCE_CONFIG()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_PLL_PLLM_CONFIG()</span></li></ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Macros rename:</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_FORCE_RESET() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_FORCE_RESET</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_RELEASE_RESET() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_RELEASE_RESET</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-family: Verdana;" class="MsoNormal"><span style="font-size: 10pt;">Add __HAL_RCC_SYSCLK_CONFIG() </span><span style="font-size: 10pt;">new macro</span><span style="font-size: 10pt;"> to configure the system clock source (</span><span style="font-size: 10pt;">SYSCLK</span><span style="font-size: 10pt;">)</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_RCC_GET_SYSCLK_SOURCE() updates:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new RCC Literals:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_HSI</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_HSE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_PLLCLK</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_PLLRCLK</span></li></ul></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update macro description to refer to the literals above</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span><span style="color: rgb(71, 71, 71); font-family: helvetica,arial,sans-serif; font-size: 26px; font-style: normal; font-variant: normal; font-weight: bold; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);"></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new define PWR_WAKEUP_PIN2</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new API to Control/Get </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">VOS bits of CR register</span></li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWR_HAL_PWREx_ControlVoltageScaling()</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWREx_GetVoltageRange()</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_PWR_</span><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US"> VOLTAGESCALING_CONFIG</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration</span><span style="background: rgb(252, 252, 252) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; font-size: 10pt; font-family: "Helvetica","sans-serif"; color: rgb(2, 3, 2);" lang="EN-US"><span style="text-align: start; float: none; word-spacing: 0px;"> </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the
new Alternate functions literals related to remap for <span style="font-style: italic; font-weight: bold;">SPI, USART, I2C, SPDIFRX, CEC and
QSPI</span></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US"><small><span style="font-family: Verdana;">HAL_GPIO_DeInit():
Update to check if GPIO Pin x is already used in EXTI mode on
@@ -2013,7 +2070,7 @@
duplex management and add the attribute __weak in the Generic API</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">I2S_Init(), HAL_I2S_DMAPause(), </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_DMAStop(), </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_DMAResume(), </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_IRQHandle()</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"> <o:p></o:p></span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Move the following static functions from generic to extension driver</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> I2S_DMARxCplt() and I2S_DMATxCplt()</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove static attribute from I2S_Transmit_IT() and I2S_Receive_IT() functions</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Move I2SxEXT() macro to extension file</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add I2S_CLOCK_PLLR and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">I2S_CLOCK_PLLSRC defines for I2S clock source</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new function I2S_GetInputClock()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add WriteFifo and PageSize fields in the FMC_NORSRAM_InitTypeDef structure</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add
FMC_PAGE_SIZE_NONE, FMC_PAGE_SIZE_128, FMC_PAGE_SIZE_256,
FMC_PAGE_SIZE_1024, FMC_WRITE_FIFO_DISABLE, FMC_WRITE_FIFO_ENABLE
-defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LL USB </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update USB_OTG_CfgTypeDef structure to support LPM, </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">lpm_enable </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">field added</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 202px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 26-December-2014</span></h3>
+defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LL USB </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update USB_OTG_CfgTypeDef structure to support LPM, </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">lpm_enable </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">field added</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 202px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 26-December-2014</span></h3>
@@ -2232,7 +2289,7 @@
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 19-June-2014</span></h3>
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 19-June-2014</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -2737,7 +2794,7 @@
</ul>
</ul>
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;"></span></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014</span></h3>
+<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;"></span></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
@@ -2747,7 +2804,7 @@
<ul style="margin-top: 0cm;" type="square">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<div style="text-align: justify;">
<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
Redistribution and use in source and binary forms, with or without
diff --git a/Src/stm32f4xx_hal.c b/Src/stm32f4xx_hal.c
index 17a52b4..245147a 100644
--- a/Src/stm32f4xx_hal.c
+++ b/Src/stm32f4xx_hal.c
@@ -50,11 +50,11 @@
* @{
*/
/**
- * @brief STM32F4xx HAL Driver version number V1.7.7
+ * @brief STM32F4xx HAL Driver version number V1.7.8
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32f4xx_hal_can.c b/Src/stm32f4xx_hal_can.c
index 009a447..0fbc723 100644
--- a/Src/stm32f4xx_hal_can.c
+++ b/Src/stm32f4xx_hal_can.c
@@ -537,19 +537,19 @@
* the configuration information for CAN module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
- * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
- * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
- * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
- * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
- * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
- * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
- * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
- * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
@@ -680,19 +680,19 @@
* the configuration information for CAN module
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
- * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
- * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
- * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
- * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
- * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
- * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
- * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
- * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
diff --git a/Src/stm32f4xx_hal_cryp.c b/Src/stm32f4xx_hal_cryp.c
index 907db4a..97f8bd7 100644
--- a/Src/stm32f4xx_hal_cryp.c
+++ b/Src/stm32f4xx_hal_cryp.c
@@ -3,7 +3,7 @@
* @file stm32f4xx_hal_cryp.c
* @author MCD Application Team
* @brief CRYP HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
* + Initialization, de-initialization, set config and get config functions
* + DES/TDES, AES processing functions
@@ -64,6 +64,12 @@
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+ (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
+ without having to configure again the Key or the Initialization Vector between each API call,
+ the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
+ Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
+ or HAL_CRYP_Decrypt_DMA().
+
[..]
The cryptographic processor supports following standards:
(#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
@@ -237,16 +243,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -254,9 +260,9 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-
+
#if defined (AES) || defined (CRYP)
-
+
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
@@ -276,36 +282,36 @@
#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
-
+
#if defined(AES)
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
-#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
-#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
#else /* CRYP */
#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
-#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
-#endif /* End CRYP or AES */
+#endif /* End CRYP or AES */
- /* CTR1 information to use in CCM algorithm */
-#define CRYP_CCM_CTR1_0 0x07FFFFFFU
-#define CRYP_CCM_CTR1_1 0xFFFFFF00U
-#define CRYP_CCM_CTR1_2 0x00000001U
+/* CTR1 information to use in CCM algorithm */
+#define CRYP_CCM_CTR1_0 0x07FFFFFFU
+#define CRYP_CCM_CTR1_1 0xFFFFFF00U
+#define CRYP_CCM_CTR1_2 0x00000001U
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/** @addtogroup CRYP_Private_Macros
* @{
@@ -317,9 +323,9 @@
(__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
}while(0)
-#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
-
-#else /*AES*/
+#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
+
+#else /*AES*/
#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
(__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
}while(0)
@@ -328,14 +334,14 @@
/**
* @}
- */
-
+ */
+
/* Private struct -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup CRYP_Private_Functions_prototypes
* @{
- */
+ */
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
@@ -350,7 +356,7 @@
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
@@ -376,7 +382,7 @@
/**
* @}
- */
+ */
/* Exported functions ---------------------------------------------------------*/
@@ -384,27 +390,27 @@
* @{
*/
-
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
========================================================================================
##### Initialization, de-initialization and Set and Get configuration functions #####
========================================================================================
[..] This section provides functions allowing to:
- (+) Initialize the CRYP
- (+) DeInitialize the CRYP
+ (+) Initialize the CRYP
+ (+) DeInitialize the CRYP
(+) Initialize the CRYP MSP
- (+) DeInitialize the CRYP MSP
+ (+) DeInitialize the CRYP MSP
(+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
Parameters which are configured in This section are :
- (+) Key size
+ (+) Key size
(+) Data Type : 32,16, 8 or 1bit
- (+) AlgoMode :
- - for CRYP1 IP :
- ECB and CBC in DES/TDES Standard
- ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
+ (+) AlgoMode :
+ - for CRYP1 IP :
+ ECB and CBC in DES/TDES Standard
+ ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
- for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
@@ -422,152 +428,155 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
+{
/* Check the CRYP handle allocation */
- if(hcryp == NULL)
+ if (hcryp == NULL)
{
return HAL_ERROR;
- }
-
+ }
+
/* Check parameters */
assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
- assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
-
- #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- if(hcryp->State == HAL_CRYP_STATE_RESET)
+ assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
+ assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ if (hcryp->State == HAL_CRYP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcryp->Lock = HAL_UNLOCKED;
-
+
hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
-
- if(hcryp->MspInitCallback == NULL)
+
+ if (hcryp->MspInitCallback == NULL)
{
hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
}
-
+
/* Init the low level hardware */
- hcryp->MspInitCallback(hcryp);
+ hcryp->MspInitCallback(hcryp);
}
#else
- if(hcryp->State == HAL_CRYP_STATE_RESET)
+ if (hcryp->State == HAL_CRYP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcryp->Lock = HAL_UNLOCKED;
-
+
/* Init the low level hardware */
HAL_CRYP_MspInit(hcryp);
}
- #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
/* Set the key size(This bit field is donÂ’t care in the DES or TDES modes) data type and Algorithm */
#if defined (CRYP)
-
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
#else /*AES*/
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
#endif /* End AES or CRYP*/
-
+
/* Reset Error Code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
-
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief De-Initializes the CRYP peripheral.
+ * @brief De-Initializes the CRYP peripheral.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
{
/* Check the CRYP handle allocation */
- if(hcryp == NULL)
+ if (hcryp == NULL)
{
return HAL_ERROR;
}
-
+
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
-
+
/* Reset CrypInCount and CrypOutCount */
hcryp->CrypInCount = 0;
hcryp->CrypOutCount = 0;
- hcryp->CrypHeaderCount =0;
-
+ hcryp->CrypHeaderCount = 0;
+
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-
- if(hcryp->MspDeInitCallback == NULL)
+
+ if (hcryp->MspDeInitCallback == NULL)
{
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hcryp->MspDeInitCallback(hcryp);
-
+
#else
-
+
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_CRYP_MspDeInit(hcryp);
-
+
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(hcryp);
-
+
/* Return function status */
return HAL_OK;
}
-
+
/**
* @brief Configure the CRYP according to the specified
- * parameters in the CRYP_ConfigTypeDef
+ * parameters in the CRYP_ConfigTypeDef
* @param hcryp: pointer to a CRYP_HandleTypeDef structure
* @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
-{
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
/* Check the CRYP handle allocation */
- if((hcryp == NULL)|| (pConf == NULL) )
+ if ((hcryp == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
-
+
/* Check parameters */
assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
assert_param(IS_CRYP_DATATYPE(pConf->DataType));
assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Set CRYP parameters */
+ __HAL_LOCK(hcryp);
+
+ /* Set CRYP parameters */
hcryp->Init.DataType = pConf->DataType;
hcryp->Init.pKey = pConf->pKey;
hcryp->Init.Algorithm = pConf->Algorithm;
@@ -577,42 +586,44 @@
hcryp->Init.HeaderSize = pConf->HeaderSize;
hcryp->Init.B0 = pConf->B0;
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
-
- /* Set the key size(This bit field is donÂ’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
-#if defined (CRYP)
-
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+
+ /* Set the key size(This bit field is donÂ’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
+#if defined (CRYP)
+
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
#else /*AES*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
+ hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
/*clear error flags*/
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_ERR_CLEAR);
-
-#endif /* End AES or CRYP */
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
+
+#endif /* End AES or CRYP */
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Reset Error Code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
-
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
-
+
/* Return function status */
return HAL_OK;
}
else
{
/* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ __HAL_UNLOCK(hcryp);
+
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
}
@@ -624,23 +635,23 @@
* the configuration information for CRYP module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
-{
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
/* Check the CRYP handle allocation */
- if((hcryp == NULL)|| (pConf == NULL) )
+ if ((hcryp == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
- /* Get CRYP parameters */
+ __HAL_LOCK(hcryp);
+
+ /* Get CRYP parameters */
pConf->DataType = hcryp->Init.DataType;
pConf->pKey = hcryp->Init.pKey;
pConf->Algorithm = hcryp->Init.Algorithm;
@@ -650,23 +661,23 @@
pConf->HeaderSize = hcryp->Init.HeaderSize;
pConf->B0 = hcryp->Init.B0;
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
else
{
/* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ __HAL_UNLOCK(hcryp);
+
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
}
@@ -680,7 +691,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspInit could be implemented in the user file
*/
@@ -696,7 +707,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspDeInit could be implemented in the user file
*/
@@ -711,76 +722,77 @@
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
- * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+ pCRYP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
-
- if(pCallback == NULL)
+
+ if (pCallback == NULL)
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
-
+
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hcryp);
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
switch (CallbackID)
{
- case HAL_CRYP_INPUT_COMPLETE_CB_ID :
- hcryp->InCpltCallback = pCallback;
- break;
-
- case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
- hcryp->OutCpltCallback = pCallback;
- break;
-
- case HAL_CRYP_ERROR_CB_ID :
- hcryp->ErrorCallback = pCallback;
- break;
-
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = pCallback;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ else if (hcryp->State == HAL_CRYP_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = pCallback;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -790,10 +802,10 @@
/* Return error status */
status = HAL_ERROR;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hcryp);
-
+
return status;
}
@@ -805,7 +817,7 @@
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
- * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
@@ -813,60 +825,60 @@
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
switch (CallbackID)
{
- case HAL_CRYP_INPUT_COMPLETE_CB_ID :
- hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
- break;
-
- case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
- hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
- break;
-
- case HAL_CRYP_ERROR_CB_ID :
- hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
-
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = HAL_CRYP_MspInit;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ else if (hcryp->State == HAL_CRYP_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_CRYP_MSPINIT_CB_ID :
- hcryp->MspInitCallback = HAL_CRYP_MspInit;
- break;
-
- case HAL_CRYP_MSPDEINIT_CB_ID :
- hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
- break;
-
- default :
- /* Update the error code */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -876,10 +888,10 @@
/* Return error status */
status = HAL_ERROR;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hcryp);
-
+
return status;
}
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -887,16 +899,16 @@
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
- * @brief processing functions.
- *
-@verbatim
+/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
+ * @brief processing functions.
+ *
+@verbatim
==============================================================================
##### Encrypt Decrypt functions #####
- ==============================================================================
- [..] This section provides API allowing to Encrypt/Decrypt Data following
+ ==============================================================================
+ [..] This section provides API allowing to Encrypt/Decrypt Data following
Standard DES/TDES or AES, and Algorithm configured by the user:
- (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
+ (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
- Electronic Code Book(ECB)
- Cipher Block Chaining (CBC)
(+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
@@ -906,7 +918,7 @@
- Cipher Block Chaining (CBC)
- Counter mode (CTR)
- Galois/counter mode (GCM)
- - Counter with Cipher Block Chaining-Message(CCM)
+ - Counter with Cipher Block Chaining-Message(CCM)
[..] Three processing functions are available:
(+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
(+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
@@ -924,28 +936,29 @@
* @param Input: Pointer to the input buffer (plaintext)
* @param Size: Length of the plaintext buffer in word.
* @param Output: Pointer to the output buffer(ciphertext)
- * @param Timeout: Specify Timeout value
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout)
{
uint32_t algo;
HAL_StatusTypeDef status;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -953,132 +966,140 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
-#if defined (CRYP)
- /* Set Encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
+
+#if defined (CRYP)
+ /* Set Encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /*Set Initialization Vector (IV)*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Statrt DES/TDES encryption process */
- status = CRYP_TDES_Process(hcryp,Timeout);
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES encryption */
- status = CRYP_AES_Encrypt(hcryp, Timeout);
- break;
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- case CRYP_AES_GCM:
-
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process(hcryp, Timeout);
-
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process(hcryp,Timeout);
- break;
-#endif /* GCM CCM defined*/
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
-#else /*AES*/
-
- /* Set the operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES encryption */
- status = CRYP_AES_Encrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process (hcryp,Timeout) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process(hcryp,Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Statrt DES/TDES encryption process */
+ status = CRYP_TDES_Process(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout);
+
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+ #endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
-#endif /*end AES or CRYP */
-
+
+#else /*AES*/
+
+ /* Set the operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+#endif /*end AES or CRYP */
+
if (status == HAL_OK)
- {
+ {
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
- }
+ }
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1088,28 +1109,29 @@
* @param Input: Pointer to the input buffer (ciphertext )
* @param Size: Length of the plaintext buffer in word.
* @param Output: Pointer to the output buffer(plaintext)
- * @param Timeout: Specify Timeout value
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+ uint32_t Timeout)
{
HAL_StatusTypeDef status;
- uint32_t algo;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ uint32_t algo;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
+ __HAL_LOCK(hcryp);
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1117,133 +1139,141 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
+
/* Set Decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /*Set Initialization Vector (IV)*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DES/TDES decryption process */
- status = CRYP_TDES_Process(hcryp, Timeout);
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt(hcryp, Timeout);
- break;
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- case CRYP_AES_GCM:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process (hcryp, Timeout) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process(hcryp, Timeout);
- break;
-#endif /* GCM CCM defined*/
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
-#else /*AES*/
-
- /* Set Decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt(hcryp, Timeout);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process (hcryp, Timeout) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process(hcryp, Timeout);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DES/TDES decryption process */
+ status = CRYP_TDES_Process(hcryp, Timeout);
+
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+ #endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
-#endif /* End AES or CRYP */
-
+
+#else /*AES*/
+
+ /* Set Decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+#endif /* End AES or CRYP */
+
if (status == HAL_OK)
- {
+ {
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
- }
+ }
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1257,23 +1287,23 @@
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t algo;
+ uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
- hcryp->pCrypOutBuffPtr = Output;
-
+ hcryp->pCrypOutBuffPtr = Output;
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1281,124 +1311,132 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
- /* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP to start DES/TDES process*/
- __HAL_CRYP_ENABLE(hcryp);
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- status = CRYP_AES_Encrypt_IT(hcryp);
- break;
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- case CRYP_AES_GCM:
-
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-#endif /* GCM CCM defined*/
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
- }
-
-#else /* AES */
-
+
/* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES encryption */
- status = CRYP_AES_Encrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP to start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+ #endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /*end AES or CRYP*/
-
+
+#else /* AES */
+
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES encryption */
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
+ }
+#endif /*end AES or CRYP*/
+
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return status;
+ return status;
}
/**
@@ -1414,21 +1452,21 @@
{
uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
+ __HAL_LOCK(hcryp);
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1436,128 +1474,136 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
+
/* Set decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP and start DES/TDES process*/
- __HAL_CRYP_ENABLE(hcryp);
-
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_IT(hcryp);
- break;
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- case CRYP_AES_GCM:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCMdecryption */
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-#endif /* GCM CCM defined*/
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP and start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCMdecryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+ #endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-
+
#else /*AES*/
-
+
/* Set decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_IT(hcryp);
- break;
-
- case CRYP_AES_GCM_GMAC:
-
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_IT (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
-
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process_IT(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /* End AES or CRYP */
-
+#endif /* End AES or CRYP */
+
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return status;
+ return status;
}
/**
@@ -1571,23 +1617,24 @@
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t algo;
+ uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1595,150 +1642,200 @@
}
else
{
- hcryp->Size = Size;
+ hcryp->Size = Size;
}
-
+
#if defined (CRYP)
-
- /* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for DES/TDES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the Initialization Vector IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for AES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- case CRYP_AES_GCM:
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-#endif /* GCM CCM defined*/
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
- }
-
-#else /*AES*/
+
/* Set encryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* algo get algorithm selected */
- algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the Initialization Vector*/
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
- }
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for AES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_GCM_GMAC:
- /* AES GCM encryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM encryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector*/
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+ #endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /* End AES or CRYP */
-
+
+#else /*AES*/
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+ {
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector*/
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
+ }
+#endif /* End AES or CRYP */
+
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
- }
-
+ }
+
/* Return function status */
- return status;
+ return status;
}
/**
@@ -1752,24 +1849,24 @@
*/
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t algo;
+ uint32_t algo;
HAL_StatusTypeDef status = HAL_OK;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
-
+
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Process locked */
- __HAL_LOCK(hcryp);
-
+ __HAL_LOCK(hcryp);
+
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = Input;
hcryp->pCrypOutBuffPtr = Output;
-
+
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
@@ -1777,140 +1874,149 @@
}
else
{
- hcryp->Size = Size;
- }
-
+ hcryp->Size = Size;
+ }
+
#if defined (CRYP)
-
+
/* Set decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
-
- switch(algo)
- {
- case CRYP_DES_ECB:
- case CRYP_DES_CBC:
- case CRYP_TDES_ECB:
- case CRYP_TDES_CBC:
-
- /*Set Key */
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- }
-
- /* Set the Initialization Vector*/
- if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
- {
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- }
-
- /* Flush FIFO */
- HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Start DMA process transfer for DES/TDES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- break;
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_DMA(hcryp);
- break;
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- case CRYP_AES_GCM:
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-#endif /* GCM CCM defined*/
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ }
+
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ }
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+ #endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-
+
#else /*AES*/
-
+
/* Set decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
-
- /* algo get algorithm selected */
+
+ /* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
-
- switch(algo)
- {
-
- case CRYP_AES_ECB:
- case CRYP_AES_CBC:
- case CRYP_AES_CTR:
-
- /* AES decryption */
- status = CRYP_AES_Decrypt_DMA(hcryp);
- break;
-
- case CRYP_AES_GCM_GMAC:
- /* AES GCM decryption */
- status = CRYP_AESGCM_Process_DMA (hcryp) ;
- break;
-
- case CRYP_AES_CCM:
- /* AES CCM decryption */
- status = CRYP_AESCCM_Process_DMA(hcryp);
- break;
-
- default:
- hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
- status = HAL_ERROR;
- break;
+
+ switch (algo)
+ {
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA(hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ status = HAL_ERROR;
+ break;
}
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
-
+
/* Return function status */
- return status;
+ return status;
}
/**
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
- * @brief CRYP IRQ handler.
- *
-@verbatim
+/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
+ * @brief CRYP IRQ handler.
+ *
+@verbatim
==============================================================================
##### CRYP IRQ handler management #####
- ==============================================================================
+ ==============================================================================
[..] This section provides CRYP IRQ handler and callback functions.
(+) HAL_CRYP_IRQHandler CRYP interrupt request
(+) HAL_CRYP_InCpltCallback input data transfer complete callback
(+) HAL_CRYP_OutCpltCallback output data transfer complete callback
(+) HAL_CRYP_ErrorCallback CRYP error callback
- (+) HAL_CRYP_GetState return the CRYP state
+ (+) HAL_CRYP_GetState return the CRYP state
(+) HAL_CRYP_GetError return the CRYP error code
@endverbatim
* @{
@@ -1924,91 +2030,98 @@
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
-
+
#if defined (CRYP)
-
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U))
+
+ uint32_t itstatus = hcryp->Instance->MISR;
+
+ if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
{
- if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC)
+ || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
{
CRYP_TDES_IT(hcryp); /* DES or TDES*/
}
- else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
+ else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
+ || (hcryp->Init.Algorithm == CRYP_AES_CTR))
{
CRYP_AES_IT(hcryp); /*AES*/
}
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) )
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
{
/* if header phase */
- if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
{
CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
+ }
+ else /* if payload phase */
{
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
-#endif /* GCM CCM defined*/
+ #endif /* GCM CCM defined*/
else
{
/* Nothing to do */
}
- }
-
-#else /*AES*/
- if((__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_CCF) != 0x0U) && (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_CCFIE) != 0x0U))
+ }
+
+#else /*AES*/
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
{
-
- /* Clear computation complete flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
{
-
- /* if header phase */
- if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
+
+ /* Clear computation complete flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
{
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
+
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
+ }
+ else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
{
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ /* if header phase */
+ if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
+ }
+ else /* AES Algorithm ECB,CBC or CTR*/
+ {
+ CRYP_AES_IT(hcryp);
}
}
- else if(hcryp->Init.Algorithm == CRYP_AES_CCM)
- {
- /* if header phase */
- if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount )
- {
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
- {
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
- }
- }
- else /* AES Algorithm ECB,CBC or CTR*/
- {
- CRYP_AES_IT(hcryp);
- }
- }
+ }
/* Check if error occurred */
- if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
{
/* If write Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
}
/* If read Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
}
}
-#endif /* End AES or CRYP */
+#endif /* End AES or CRYP */
}
/**
@@ -2043,10 +2156,10 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_InCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -2059,7 +2172,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_OutCpltCallback could be implemented in the user file
*/
@@ -2071,14 +2184,14 @@
* the configuration information for CRYP module.
* @retval None
*/
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_ErrorCallback could be implemented in the user file
- */
+ */
}
/**
* @}
@@ -2089,88 +2202,94 @@
* @{
*/
- #if defined (CRYP)
+#if defined (CRYP)
/**
* @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout: specify Timeout value
+ * the configuration information for CRYP module
+ * @param Timeout: specify Timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t temp; /* Temporary CrypOutBuff */
- uint16_t incount; /* Temporary CrypInCount Value */
+ uint32_t temp[2]; /* Temporary CrypOutBuff */
+ uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
-
+ uint32_t i;
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- /*Start processing*/
- while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
- {
- /* Temporary CrypInCount Value */
- incount = hcryp->CrypInCount;
+
+ /*Start processing*/
+ while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
+ /* Temporary CrypInCount Value */
+ incount = hcryp->CrypInCount;
/* Write plain data and get cipher data */
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
-
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state & errorCode*/
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-
+
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
- /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 2U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
}
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
}
/* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
+ __HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
-/**
+/**
* @brief CRYP block input/output data handling under interruption with DES/TDES standard.
* @note The function is called under interruption only, once
* interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
@@ -2180,73 +2299,84 @@
*/
static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t temp; /* Temporary CrypOutBuff */
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U))
-
- {
- /* Write input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
- if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
- {
- /* Disable interruption */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
+ uint32_t temp[2]; /* Temporary CrypOutBuff */
+ uint32_t i;
+
+ if (hcryp->State == HAL_CRYP_STATE_BUSY)
+ {
+ if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
+ {
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
+ {
+ /* Write input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
}
- if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U))
+ if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
{
- /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
{
- /* Disable interruption */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Output complete callback*/
- hcryp->OutCpltCallback(hcryp);
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 2U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- /*Call legacy weak Output complete callback*/
- HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- }
+ }
}
else
{
/* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ __HAL_UNLOCK(hcryp);
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
@@ -2260,58 +2390,80 @@
/**
* @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure
- * @param Timeout: specify Timeout value
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: specify Timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
+{
uint16_t outcount; /* Temporary CrypOutCount Value */
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#endif /* End AES or CRYP */
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
}
-
+
+ if (DoKeyIVConfig == 1U)
+ {
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+#endif /* End AES or CRYP */
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
- {
+
+ while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
/* Write plain Ddta and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
+ CRYP_AES_ProcessData(hcryp, Timeout);
/*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
- }
-
+ outcount = hcryp->CrypOutCount;
+ }
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -2321,202 +2473,245 @@
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
-{
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+{
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
-#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#endif /* End AES or CRYP */
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
}
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+#endif /* End AES or CRYP */
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
- if(hcryp->Size != 0U)
- {
-#if defined (AES)
-
+
+ if (hcryp->Size != 0U)
+ {
+#if defined (AES)
+
/* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
-#else /* CRYP */
-
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+#else /* CRYP */
+
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
+
/* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
-#endif /* End AES or CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#endif /* End AES or CRYP */
}
else
- {
+ {
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
+ __HAL_UNLOCK(hcryp);
+ }
+
/* Return function status */
return HAL_OK;
}
/**
* @brief Decryption in ECB/CBC & CTR mode with AES Standard
- * @param hcryp: pointer to a CRYP_HandleTypeDef structure
- * @param Timeout: Specify Timeout value
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
-{
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
uint16_t outcount; /* Temporary CrypOutCount Value */
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
-#if defined (AES)
- if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
- {
- /* Set key preparation for decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & Key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
/* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+
+ /* Wait for BUSY flag to be raised */
+ if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
- /* Change state & error code*/
+
+ /* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+
+#endif /* End AES or CRYP */
}
- else /*Mode 4 : decryption & Key preparation*/
+ else /*Algorithm CTR */
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set decryption & Key preparation operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
- }
+ }
+
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#else /* CRYP */
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
-
-#endif /* End AES or CRYP */
- }
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
-
- /* Set IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#endif /* End AES or CRYP */
- }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
-
- while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
- {
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
+ CRYP_AES_ProcessData(hcryp, Timeout);
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
- }
-
+ }
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
@@ -2527,156 +2722,176 @@
static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
-#if defined (AES)
- if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
- {
- /* Set key preparation for decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
/* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
+
+ /* Wait for BUSY flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+
+#endif /* End AES or CRYP */
}
- else /*Mode 4 : decryption & key preparation*/
+
+ else /*Algorithm CTR */
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set decryption & key preparation operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
- }
-#else /* CRYP */
-
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- count-- ;
- if(count == 0U)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
}
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
-
-#endif /* End AES or CRYP */
- }
-
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
-
- /* Set IV */
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#endif /* End AES or CRYP */
- }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
- if(hcryp->Size != 0U)
- {
-
-#if defined (AES)
-
+ if (hcryp->Size != 0U)
+ {
+
+#if defined (AES)
+
/* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
#else /* CRYP */
-
+
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
-#endif /* End AES or CRYP */
+
+#endif /* End AES or CRYP */
}
- else
+ else
{
/* Process locked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -2689,131 +2904,150 @@
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
-
- /* Key preparation for ECB/CBC */
- if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
-#if defined (AES)
- if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
- {
- /* Set key preparation for decryption operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
-
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ }
+ }
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+ {
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
/* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for CCF flag to be raised */
+
+ /* Wait for BUSY flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Return to decryption operating mode(Mode 3)*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+
+#endif /* End AES or CRYP */
}
- else /*Mode 4 : decryption & key preparation*/
+ else /*Algorithm CTR */
{
/* Set the Key*/
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set decryption & Key preparation operating mode*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
- }
-#else /* CRYP */
- /* change ALGOMODE to key preparation for decryption*/
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
-
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Wait for BUSY flag to be raised */
- count = CRYP_TIMEOUT_KEYPREPARATION;
- do
- {
- count-- ;
- if(count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
}
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
- /* Turn back to ALGOMODE of the configuration */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
-
-#endif /* End AES or CRYP */
- }
- else /*Algorithm CTR */
- {
- /* Set the Key*/
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- }
-
- if (hcryp->Init.Algorithm != CRYP_AES_ECB)
- {
- /* Set the Initialization Vector*/
-#if defined (AES)
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#else /* CRYP */
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
#endif /* End AES or CRYP */
- }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
- if(hcryp->Size != 0U)
- {
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+
+ if (hcryp->Size != 0U)
+ {
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
- else
+ else
{
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -2824,40 +3058,40 @@
* @param hdma: DMA handle
* @retval None
*/
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
/* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
in the DMACR register */
-#if defined (CRYP)
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-
+#if defined (CRYP)
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+
#else /* AES */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
+
/* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
- if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
- {
+ if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
}
-#endif /* End AES or CRYP */
-
+#endif /* End AES or CRYP */
+
/* Call input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
@@ -2867,84 +3101,84 @@
*/
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
/* Disable the DMA transfer for output FIFO request by resetting
the DOEN bit in the DMACR register */
-
-#if defined (CRYP)
+
+#if defined (CRYP)
hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-#if defined (CRYP_CR_ALGOMODE_AES_GCM)
- if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
- {
+ #if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
+ {
/* Disable CRYP (not allowed in GCM)*/
__HAL_CRYP_DISABLE(hcryp);
}
-#else /*NO GCM CCM */
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-#endif /* GCM CCM defined*/
-#else /* AES */
-
+ #else /*NO GCM CCM */
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ #endif /* GCM CCM defined*/
+#else /* AES */
+
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
- if((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
- {
- /* Disable CRYP (not allowed in GCM)*/
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
+ {
+ /* Disable CRYP (not allowed in GCM)*/
__HAL_CRYP_DISABLE(hcryp);
- }
-#endif /* End AES or CRYP */
-
+ }
+#endif /* End AES or CRYP */
+
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ __HAL_UNLOCK(hcryp);
/* Call output data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
- * @brief DMA CRYP communication error callback.
+ * @brief DMA CRYP communication error callback.
* @param hdma: DMA handle
* @retval None
*/
static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Change the CRYP peripheral state */
- hcryp->State= HAL_CRYP_STATE_READY;
-
+ CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
-#if defined (AES)
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+#if defined (AES)
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
-
-#endif /* AES */
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* AES */
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
@@ -2960,44 +3194,44 @@
{
/* Set the CRYP DMA transfer complete callback */
hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
-
+
/* Set the DMA input error callback */
hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
+
/* Set the CRYP DMA transfer complete callback */
hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
-
+
/* Set the DMA output error callback */
hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
-#if defined (CRYP)
-
+
+#if defined (CRYP)
+
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Enable the input DMA Stream */
- if ( HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
/* Enable the output DMA Stream */
- if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
@@ -3007,189 +3241,188 @@
}
/* Enable In/Out DMA request */
hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
-
+
#else /* AES */
-
- if(((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
- {
- /* Enable CRYP (not allowed in GCM & CCM)*/
+
+ if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
+ && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
+ {
+ /* Enable CRYP (not allowed in GCM & CCM)*/
__HAL_CRYP_ENABLE(hcryp);
- }
-
+ }
+
/* Enable the DMA input stream */
- if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+ }
/* Enable the DMA output stream */
- if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size)!=HAL_OK)
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
{
/* DMA error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
-
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
/* Call error callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ }
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
/* Enable In and Out DMA requests */
- if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
- {
+ if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
/* Enable only In DMA requests for CCM*/
- SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN ));
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
}
else
{
/* Enable In and Out DMA requests */
SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
- }
+ }
#endif /* End AES or CRYP */
}
/**
- * @brief Process Data: Write Input data in polling mode and used in AES functions.
+ * @brief Process Data: Write Input data in polling mode and used in AES functions.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param Timeout: Specify Timeout value
+ * @param Timeout: Specify Timeout value
* @retval None
*/
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
-
- uint32_t temp; /* Temporary CrypOutBuff */
+
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
#if defined (CRYP)
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
-#endif
-
-#if defined (CRYP)
-
+#endif
+
+#if defined (CRYP)
+
/*Temporary CrypOutCount Value*/
- incount = hcryp->CrypInCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ incount = hcryp->CrypInCount;
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
}
-
+
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state & error code*/
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
-
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
- /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- }
-
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ }
+
#else /* AES */
-
+
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-
+
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
#endif /* End AES or CRYP */
}
-/**
+/**
* @brief Handle CRYP block input/output data handling under interruption.
* @note The function is called under interruption only, once
* interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
@@ -3199,36 +3432,37 @@
*/
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t temp; /* Temporary CrypOutBuff */
-#if defined (CRYP)
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
+#if defined (CRYP)
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
-#endif
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
-#if defined (CRYP)
-
+#endif
+
+ if (hcryp->State == HAL_CRYP_STATE_BUSY)
+ {
+#if defined (CRYP)
+
/*Temporary CrypOutCount Value*/
incount = hcryp->CrypInCount;
- if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
{
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
- {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
+ {
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
+
/* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
@@ -3239,79 +3473,77 @@
}
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+
+ if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Call Output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Output complete callback*/
- hcryp->OutCpltCallback(hcryp);
+
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- /*Call legacy weak Output complete callback*/
- HAL_CRYP_OutCpltCallback(hcryp);
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
-
+
#else /*AES*/
-
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
- if(hcryp->CrypOutCount == (hcryp->Size/4U))
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+
+ if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable Computation Complete flag and errors interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Call Output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
@@ -3320,116 +3552,116 @@
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
- {
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
-
- if(hcryp->CrypInCount == (hcryp->Size/4U))
- {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ {
/* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
+ }
+ }
#endif /* End AES or CRYP */
-
- }
+
+ }
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-}
+}
/**
- * @brief Writes Key in Key registers.
+ * @brief Writes Key in Key registers.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param KeySize: Size of Key
* @retval None
*/
static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
-{
+{
#if defined (CRYP)
-
- switch(KeySize)
+
+ switch (KeySize)
{
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
- break;
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
-
- break;
- default:
- break;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+
+ break;
+ default:
+ break;
}
#else /*AES*/
- switch(KeySize)
+ switch (KeySize)
{
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->KEYR7 =*(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->KEYR6 =*(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->KEYR5 =*(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->KEYR4 =*(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey+4);
- hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+5);
- hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+6);
- hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+7);
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey);
- hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+1);
- hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+2);
- hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+3);
-
- break;
- default:
- break;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3);
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1);
+ hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2);
+ hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3);
+
+ break;
+ default:
+ break;
}
#endif /* End AES or CRYP */
}
#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
/**
- * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Timeout: Timeout duration
@@ -3438,164 +3670,191 @@
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
- uint32_t wordsize = (uint32_t)(hcryp->Size)/4U ;
+ uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
uint16_t outcount; /* Temporary CrypOutCount Value */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /****************************** Init phase **********************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-#if defined(CRYP)
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /*Wait for the CRYPEN bit to be cleared*/
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (hcryp->KeyIVConfig == 1U)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
-
-#else /* AES */
- /* Workaround 1 : only AES.
- Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
- enabling the IP, datatype different from 32 bits can be configured.*/
- /* Select DATATYPE 32 */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* just wait for hash computation */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked & return error */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
- /************************ Header phase *************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ else
{
- return HAL_ERROR;
+ hcryp->SizesSum = hcryp->Size;
}
-
- /*************************Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
-#if defined(CRYP)
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
-#else /* AES */
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
-#endif /* End AES or CRYP */
-
- if ((hcryp->Size % 16U) != 0U)
+
+ if (DoKeyIVConfig == 1U)
{
- /* recalculate wordsize */
- wordsize = ((wordsize/4U)*4U) ;
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /****************************** Init phase **********************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+#if defined(CRYP)
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+
+#else /* AES */
+ /* Workaround 1 : only AES.
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
+ /************************ Header phase *************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /*************************Payload phase ************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+#if defined(CRYP)
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#else /* AES */
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+#endif /* End AES or CRYP */
+ } /* if (DoKeyIVConfig == 1U) */
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U) ;
}
-
+
/* Get tick */
tickstart = HAL_GetTick();
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
+
/* Write input data and get output Data */
- while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
- {
+ while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
/*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
-
+ outcount = hcryp->CrypOutCount;
+
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state & error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
-
- if ((hcryp->Size % 16U) != 0U)
+
+ if ((hcryp->Size % 16U) != 0U)
{
/* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
- is selected, then the TAG message will be wrong.*/
- CRYP_Workaround(hcryp,Timeout);
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp, Timeout);
}
-
+
/* Return function status */
return HAL_OK;
}
@@ -3609,246 +3868,272 @@
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
-#if defined(AES)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#if defined(AES)
uint32_t loopcounter;
- uint32_t lastwordsize;
+ uint32_t lastwordsize;
uint32_t npblb;
-#endif /* AES */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount =0U;
-
- /******************************* Init phase *********************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-#if defined(CRYP)
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+#endif /* AES */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- count-- ;
- if(count == 0U)
+ if (hcryp->KeyIVConfig == 1U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
-#else /* AES */
-
- /* Workaround 1 : only AES
- Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
- enabling the IP, datatype different from 32 bits can be configured.*/
- /* Select DATATYPE 32 */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* just wait for hash computation */
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- count-- ;
- if(count == 0U)
+ else
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
- /***************************** Header phase *********************************/
-
-#if defined(CRYP)
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
-#else /* AES */
-
- /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if(hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
- {
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
- /* Write the payload Input block in the IN FIFO */
- if(hcryp->Size == 0U)
- {
- /* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
- else if (hcryp->Size >= 16U)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(hcryp->CrypInCount == ( hcryp->Size/4U))
- {
- /* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- else /* Size < 16Bytes : first block is the last block*/
- {
- /* Workaround not implemented*/
- /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
-
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U- (uint32_t)(hcryp->Size);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
- }
- else
- {
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- }
- while(loopcounter < 4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
- }
- }
- else if ((hcryp->Init.HeaderSize) < 4U)
- {
- for(loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter < 4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- else if ((hcryp->Init.HeaderSize) >= 4U)
- {
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- }
else
{
- /* Nothing to do */
- }
-
-#endif /* End AES or CRYP */
-
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (DoKeyIVConfig == 1U)
+ {
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /******************************* Init phase *********************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+#if defined(CRYP)
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+#else /* AES */
+
+ /* Workaround 1 : only AES
+ Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
+ /***************************** Header phase *********************************/
+
+#if defined(CRYP)
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#else /* AES */
+
+ /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
+ {
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 16Bytes : first block is the last block*/
+ {
+ /* Workaround not implemented*/
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if ((hcryp->Init.HeaderSize) < 4U)
+ {
+ for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ else if ((hcryp->Init.HeaderSize) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+#endif /* End AES or CRYP */
+ } /* end of if (DoKeyIVConfig == 1U) */
+
/* Return function status */
return HAL_OK;
}
@@ -3864,147 +4149,174 @@
{
__IO uint32_t count = 0U;
uint32_t wordsize;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /*************************** Init phase ************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-#if defined(CRYP)
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- count-- ;
- if(count == 0U)
+ if (hcryp->KeyIVConfig == 1U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
-#else /* AES */
-
- /*Workaround 1 : only AES
- Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
- enabling the IP, datatype different from 32 bits can be configured.*/
- /* Select DATATYPE 32 */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
-
- /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
- hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
- hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
- hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
- hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* just wait for hash computation */
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+ else
{
- count-- ;
- if(count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ hcryp->SizesSum = hcryp->Size;
}
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
- /************************ Header phase *************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+
+ if (DoKeyIVConfig == 1U)
{
- return HAL_ERROR;
- }
-
- /************************ Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+ /*************************** Init phase ************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
#if defined(CRYP)
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
-#endif /* CRYP */
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- if(hcryp->Size != 0U)
- {
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+#else /* AES */
+
+ /*Workaround 1 : only AES
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
+ /************************ Header phase *************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /************************ Payload phase ************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+#if defined(CRYP)
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+#endif /* CRYP */
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ } /* if (DoKeyIVConfig == 1U) */
+
+ if (hcryp->Size != 0U)
+ {
/* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
- Workaround is implemented in polling mode, so if last block of
+ Workaround is implemented in polling mode, so if last block of
payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
- /* Set the input and output addresses and start DMA transfer */
- if ((hcryp->Size % 16U) == 0U)
- {
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
{
- wordsize = (uint32_t)(hcryp->Size)+(16U-((uint32_t)(hcryp->Size)%16U)) ;
-
- /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)wordsize/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
+ wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
}
- else
+ else
{
/* Process unLocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state and phase */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief AES CCM encryption/decryption processing in polling mode
+ * @brief AES CCM encryption/decryption processing in polling mode
* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
@@ -4014,395 +4326,425 @@
static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
- uint32_t wordsize= (uint32_t)(hcryp->Size)/4U;
- uint16_t outcount; /* Temporary CrypOutCount Value */
-#if defined(AES)
+ uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#if defined(AES)
uint32_t loopcounter;
uint32_t npblb;
- uint32_t lastwordsize;
+ uint32_t lastwordsize;
#endif /* AES */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
-#if defined(CRYP)
-
- /********************** Init phase ******************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write B0 packet into CRYP_DIN Register*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
}
else
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
+ hcryp->SizesSum = hcryp->Size;
}
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /*Wait for the CRYPEN bit to be cleared*/
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+
+ if (DoKeyIVConfig == 1U)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+#if defined(CRYP)
+
+ /********************** Init phase ******************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
+
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write B0 packet into CRYP_DIN Register*/
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
}
- }
-#else /* AES */
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* configured encryption mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector with zero values*/
- hcryp->Instance->IVR3 = 0U;
- hcryp->Instance->IVR2 = 0U;
- hcryp->Instance->IVR1 = 0U;
- hcryp->Instance->IVR0 = 0U;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN*/
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
-
- /* wait until the end of computation */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked & return error */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* From that point the whole message must be processed, first the Header then the payload.
- First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
-
- if (hcryp->Init.HeaderSize != 0U)
- {
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
}
else
- {
- /*Write Header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
- }
+#else /* AES */
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+ /* wait until the end of computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* From that point the whole message must be processed, first the Header then the payload.
+ First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
+
+ if (hcryp->Init.HeaderSize != 0U)
+ {
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write Header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
/* Then the payload: cleartext payload (not the ciphertext payload).
Write input Data, no output Data to get */
if (hcryp->Size != 0U)
{
- if ((hcryp->Size % 16U) != 0U)
+ if ((hcryp->Size % 16U) != 0U)
{
- /* recalculate wordsize */
- wordsize = ((wordsize/4U)*4U) ;
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U) ;
}
-
+
/* Get tick */
tickstart = HAL_GetTick();
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
- {
+
+ while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
- /*Temporary CrypOutCount Value*/
- outcount = hcryp->CrypOutCount;
-
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
-
- if ((hcryp->Size % 16U) != 0U)
- {
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
/* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
/* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
- }
- else
+ if ((npblb % 4U) == 0U)
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
- /* Last block optionally pad the data with zeros*/
- for(loopcounter=0U; loopcounter < lastwordsize; loopcounter ++)
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
{
/* Write the last input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(loopcounter < 4U)
+ }
+ while (loopcounter < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
- loopcounter++;
- }
+ loopcounter++;
+ }
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
+
}
- }
+ }
#endif /* End AES or CRYP */
-
-#if defined(CRYP)
-
- /************************* Header phase *************************************/
- /* Header block(B1) : associated data length expressed in bytes concatenated
- with Associated Data (A)*/
-
- if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+
+#if defined(CRYP)
+
+ /************************* Header phase *************************************/
+ /* Header block(B1) : associated data length expressed in bytes concatenated
+ with Associated Data (A)*/
+
+ if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /********************** Payload phase ***************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ } /* if (DoKeyIVConfig == 1U) */
+
+ if ((hcryp->Size % 16U) != 0U)
{
- return HAL_ERROR;
- }
-
- /********************** Payload phase ***************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Size % 16U) != 0U)
- {
- /* recalculate wordsize */
- wordsize = ((wordsize/4U)*4U) ;
+ /* recalculate wordsize */
+ wordsize = ((wordsize / 4U) * 4U) ;
}
/* Get tick */
tickstart = HAL_GetTick();
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
+
/* Write input data and get output data */
- while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
- {
+ while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
/* Write plain data and get cipher data */
- CRYP_AES_ProcessData(hcryp,Timeout);
-
+ CRYP_AES_ProcessData(hcryp, Timeout);
+
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
-
- if ((hcryp->Size % 16U) != 0U)
- {
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
/* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
- is selected, then the TAG message will be wrong.*/
- CRYP_Workaround(hcryp,Timeout);
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp, Timeout);
}
#endif /* CRYP */
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief AES CCM encryption/decryption process in interrupt mode
+ * @brief AES CCM encryption/decryption process in interrupt mode
* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
@@ -4410,310 +4752,565 @@
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
#if defined(CRYP)
__IO uint32_t count = 0U;
#endif /* CRYP */
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
-#if defined(CRYP)
-
- /************ Init phase ************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN Register*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
}
else
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
+ hcryp->SizesSum = hcryp->Size;
}
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
+
+ /* Configure Key, IV and process message (header and payload) */
+ if (DoKeyIVConfig == 1U)
{
- count-- ;
- if(count == 0U)
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+#if defined(CRYP)
+
+ /************ Init phase ************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
}
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+ }
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ } /* end of if (DoKeyIVConfig == 1U) */
+
/* Enable interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
-
+
/* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
-#else /* AES */
-
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* configured mode and encryption mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector with zero values*/
- hcryp->Instance->IVR3 = 0U;
- hcryp->Instance->IVR2 = 0U;
- hcryp->Instance->IVR1 = 0U;
- hcryp->Instance->IVR0 = 0U;
-
- /* Enable interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- /* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN*/
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
-
+
+#else /* AES */
+
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured mode and encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+ } /* end of if (DoKeyIVConfig == 1U) */
#endif /* End AES or CRYP */
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief AES CCM encryption/decryption process in DMA mode
+ * @brief AES CCM encryption/decryption process in DMA mode
* for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
-{
+{
uint32_t wordsize;
__IO uint32_t count = 0U;
-
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
-#if defined(CRYP)
-
- /************************** Init phase **************************************/
-
- CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with CTR1 information */
- hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
- hcryp->Instance->IV0RR = hcryp->Init.B0[1];
- hcryp->Instance->IV1LR = hcryp->Init.B0[2];
- hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN Register*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#if defined(AES)
+ uint32_t loopcounter;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+#endif
+
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
- hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
- hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
- }
- else
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
- }
-
- /*Wait for the CRYPEN bit to be cleared*/
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- count-- ;
- if(count == 0U)
+ if (hcryp->KeyIVConfig == 1U)
{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-
-#else /* AES */
-
- /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* configured CCM chaining mode and encryption mode */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector with zero values*/
- hcryp->Instance->IVR3 = 0U;
- hcryp->Instance->IVR2 = 0U;
- hcryp->Instance->IVR1 = 0U;
- hcryp->Instance->IVR0 = 0U;
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /*Write the B0 packet into CRYP_DIN*/
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
-
- /* wait until the end of computation */
- count = CRYP_TIMEOUT_GCMCCMINITPHASE;
- do
- {
- count-- ;
- if(count == 0U)
-{
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
-}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* AES */
-
- /********************* Header phase *****************************************/
-
- if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /******************** Payload phase *****************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
-#if defined(CRYP)
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
-#endif /* CRYP */
-
- if(hcryp->Size != 0U)
- {
- /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
- /* Set the input and output addresses and start DMA transfer */
- if ((hcryp->Size % 16U) == 0U)
- {
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
- wordsize = (uint32_t)(hcryp->Size)+16U-((uint32_t)(hcryp->Size) %16U) ;
-
- /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
- CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
+ }
+ else
+ {
+ hcryp->SizesSum = hcryp->Size;
+ }
+
+ if (DoKeyIVConfig == 1U)
+ {
+
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+#if defined(CRYP)
+
+ /************************** Init phase **************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+ }
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+ }
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+#else /* AES */
+
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* From that point the whole message must be processed, first the Header then the payload.
+ First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
+
+ if (hcryp->Init.HeaderSize != 0U)
+ {
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* wait until the end of computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write Header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ } /* if (DoKeyIVConfig == 1U) */
+ /* Then the payload: cleartext payload (not the ciphertext payload).
+ Write input Data, no output Data to get */
+ if (hcryp->Size != 0U)
+ {
+ if (hcryp->Size >= 16U)
+ {
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
+ {
+ wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ }
+ if ((hcryp->Size < 16U) != 0U)
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
+ {
+ /* Write the last input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ loopcounter++;
+ }
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ }
+ else
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+#endif /* AES */
+#if defined(CRYP)
+ /********************* Header phase *****************************************/
+
+ if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /******************** Payload phase *****************************************/
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ } /* if (DoKeyIVConfig == 1U) */
+ if (hcryp->Size != 0U)
+ {
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else
+ {
+ wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
}
else /*Size = 0*/
{
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state and phase */
hcryp->State = HAL_CRYP_STATE_READY;
- }
-
+ }
+#endif /* CRYP */
/* Return function status */
return HAL_OK;
}
@@ -4721,516 +5318,525 @@
/**
* @brief Sets the payload phase in iterrupt mode
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
+ * the configuration information for CRYP module
* @retval state
*/
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
-{
+{
uint32_t loopcounter;
- uint32_t temp; /* Temporary CrypOutBuff */
- uint32_t lastwordsize;
- uint32_t npblb;
- #if defined(AES)
- uint16_t outcount; /* Temporary CrypOutCount Value */
-#endif /* AES */
-
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ uint32_t i;
+#if defined(AES)
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif /* AES */
+
/***************************** Payload phase *******************************/
-
-#if defined(CRYP)
- if(hcryp->Size == 0U)
- {
+
+#if defined(CRYP)
+ if (hcryp->Size == 0U)
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
- {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+
+ else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if(((hcryp->Size/4U) == hcryp->CrypInCount) &&((hcryp->Size %16U )== 0U))
- {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
+ {
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
+
/* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- if(hcryp->CrypOutCount < (hcryp->Size/4U))
+ }
+ if (hcryp->CrypOutCount < (hcryp->Size / 4U))
{
- /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUT;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- if (((hcryp->Size/4U) == hcryp->CrypOutCount)&&((hcryp->Size %16U )== 0U))
- {
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ i = 0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
+ {
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- }
- else if ((hcryp->Size %16U )!= 0U)
- {
- /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
- Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
-
- /* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- else
+ }
+ else if ((hcryp->Size % 16U) != 0U)
+ {
+ /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
- while(loopcounter < 4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
loopcounter++;
}
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
- for(loopcounter = 0U; loopcounter < 4U; loopcounter++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer */
- temp= hcryp->Instance->DOUT;
-
- /*get CrypOutBuff from temporary buffer */
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp;
- hcryp->CrypOutCount++;
- }
- }
- if(hcryp->CrypOutCount >= (hcryp->Size/4U))
- {
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUT;
+ }
+ if (((hcryp->Size) / 4U) == 0U)
+ {
+ for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ }
+ }
+ i = 0x0U;
+ while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
+ }
+ if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
+
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
+
/* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
else
{
/* Nothing to do */
}
#else /* AES */
-
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i = 0U;
+ while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
/*Temporary CrypOutCount Value*/
outcount = hcryp->CrypOutCount;
-
- if((hcryp->CrypOutCount >= (hcryp->Size/4U)) && ((outcount*4U) >= hcryp->Size) )
+
+ if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
{
/* Disable computation complete flag and errors interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Output complete callback*/
- hcryp->OutCpltCallback(hcryp);
+
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- /*Call legacy weak Output complete callback*/
- HAL_CRYP_OutCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
-
- else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
- {
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
- {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ {
/* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
else /* Last block of payload < 128bit*/
- {
+ {
/* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
- generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
- payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
-
+ generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
+
/* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
}
- else
+ else
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
- while(loopcounter < 4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
- }
-#endif /* AES */
+ }
+#endif /* AES */
-}
+}
/**
* @brief Sets the header phase in polling mode
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
- * @param Timeout: Timeout value
+ * @param Timeout: Timeout value
* @retval state
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t loopcounter;
-
+
/***************************** Header phase for GCM/GMAC or CCM *********************************/
-
- if((hcryp->Init.HeaderSize != 0U))
+
+ if ((hcryp->Init.HeaderSize != 0U))
{
-
-#if defined(CRYP)
-
+
+#if defined(CRYP)
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /* Wait for IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while(loopcounter <4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- loopcounter++;
- }
- /* Wait for CCF IFEM to be raised */
- if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- /* Wait until the complete message has been processed */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked & return error */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
-#else /* AES */
-
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
{
- /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- }
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+= 4U)
- {
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
{
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* Last block optionally pad the data with zeros*/
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ /* Wait for CCF IFEM to be raised */
+ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* Wait until the complete message has been processed */
+ if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+
+#else /* AES */
+
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ }
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- while(loopcounter < 4U )
- {
- /*Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /*Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
- }
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ }
+
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
-#endif /* End AES or CRYP */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+#endif /* End AES or CRYP */
}
else
{
-#if defined(AES)
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
+#if defined(AES)
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
/*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
}
-#endif /* AES */
+#endif /* AES */
}
/* Return function status */
return HAL_OK;
@@ -5239,107 +5845,105 @@
/**
* @brief Sets the header phase when using DMA in process
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module(Header & HeaderSize)
+ * the configuration information for CRYP module(Header & HeaderSize)
* @retval None
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
__IO uint32_t count = 0U;
uint32_t loopcounter;
-
- /***************************** Header phase for GCM/GMAC or CCM *********************************/
- if((hcryp->Init.HeaderSize != 0U))
+
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if ((hcryp->Init.HeaderSize != 0U))
{
-
-#if defined(CRYP)
-
+
+#if defined(CRYP)
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
-
+
/* Wait for IFEM to be raised */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
}
}
else
- {
+ {
/*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
- {
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
-
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
/* Wait for IFEM to be raised */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
}
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- while(loopcounter < 4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
loopcounter++;
}
/* Wait for IFEM to be raised */
@@ -5347,189 +5951,184 @@
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
- }
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
/* Wait until the complete message has been processed */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-
-#else /* AES */
-
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+#else /* AES */
+
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
{
/* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
}
- if ((hcryp->Init.HeaderSize %4U )== 0U)
- {
- /* HeaderSize %4, no padding */
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
- {
+ if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ {
/* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
}
else
- {
+ {
/*Write header block in the IN FIFO without last block */
- for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
{
/* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
- }
-
- /*Wait on CCF flag*/
+ }
+
+ /*Wait on CCF flag*/
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
- if(count == 0U)
+ if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
- }
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
+ } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
-#endif /* End AES or CRYP */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+#endif /* End AES or CRYP */
}
else
{
-#if defined(AES)
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
+#if defined(AES)
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
/*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+
/* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
}
-#endif /* AES */
+#endif /* AES */
}
/* Return function status */
return HAL_OK;
@@ -5544,365 +6143,254 @@
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
-#if defined(AES)
- uint32_t lastwordsize;
- uint32_t npblb;
-#endif
+#if defined(AES)
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#endif
/***************************** Header phase *********************************/
-
-#if defined(CRYP)
- if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
- {
+
+#if defined(CRYP)
+ if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI );
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
/* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI );
-
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
/* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ __HAL_CRYP_ENABLE(hcryp);
+ }
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
-
- { /* HeaderSize %4, no padding */
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+
+ {
+ /* HeaderSize %4, no padding */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
else
- {
+ {
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
{
- hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount);
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
loopcounter++;
- }
- }
-#else /* AES */
-
- if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ }
+ }
+#else /* AES */
+
+ if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
-
+
/* Payload phase not supported in CCM AES2 */
- if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
{
/* Select payload phase once the header phase is performed */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
- }
- if(hcryp->Init.Algorithm == CRYP_AES_CCM)
+ }
+ if (hcryp->Init.Algorithm == CRYP_AES_CCM)
{
/* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
- hcryp->CrypHeaderCount++;
- }
- /* Write the payload Input block in the IN FIFO */
- if(hcryp->Size == 0U)
- {
+ hcryp->CrypHeaderCount++;
+ }
+ /* Write the payload Input block in the IN FIFO */
+ if (hcryp->Size == 0U)
+ {
/* Disable interrupts */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
-
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
- }
+ }
else if (hcryp->Size >= 16U)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
-
- if((hcryp->CrypInCount == (hcryp->Size/4U)) &&((hcryp->Size %16U )== 0U))
- {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+ {
/* Call the input data transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+ }
}
else /* Size < 4 words : first block is the last block*/
{
/* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
- generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
+ generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
-
+
/* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
-
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
/* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
}
- else
+ else
{
- lastwordsize = ((16U-npblb)/4U) +1U;
- }
-
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
- while(loopcounter <4U )
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
- }
+ }
else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
- {
+ {
/* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
- hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++;
}
else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
- {
+ {
/* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
{
- hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while(loopcounter <4U )
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ while (loopcounter < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
- }
-#endif /* End AES or CRYP */
-}
+ }
+#endif /* End AES or CRYP */
+}
/**
- * @brief Workaround used for GCM/CCM mode.
+ * @brief Workaround used for GCM/CCM mode.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param Timeout: specify Timeout value
+ * @param Timeout: specify Timeout value
* @retval None
*/
-static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
+static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t lastwordsize;
- uint32_t npblb;
-#if defined(CRYP)
+ uint32_t npblb;
+#if defined(CRYP)
uint32_t iv1temp;
uint32_t temp[4] = {0};
- uint32_t temp2[4]= {0};
+ uint32_t temp2[4] = {0};
#endif /* CRYP */
- uint32_t intermediate_data[4]={0};
+ uint32_t intermediate_data[4] = {0};
uint32_t index;
-
- /* Compute the number of padding bytes in last block of payload */
- npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
/* Number of valid words (lastwordsize) in last block */
- if ((npblb%4U) ==0U)
- { lastwordsize = (16U-npblb)/4U;
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
}
- else
- {lastwordsize = ((16U-npblb)/4U) +1U;
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
}
-
-#if defined(CRYP)
-
+
+#if defined(CRYP)
+
/* Workaround 2, case GCM encryption */
if (hcryp->Init.Algorithm == CRYP_AES_GCM)
{
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
- {/*Workaround in order to properly compute authentication tags while doing
- a GCM encryption with the last block of payload size inferior to 128 bits*/
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /*Workaround in order to properly compute authentication tags while doing
+ a GCM encryption with the last block of payload size inferior to 128 bits*/
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
-
+
/*Update CRYP_IV1R register and ALGOMODE*/
- hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1);
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-
+ hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
+
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
- /* Last block optionally pad the data with zeros*/
- for(index=0; index < lastwordsize; index ++)
+ /* Last block optionally pad the data with zeros*/
+ for (index = 0; index < lastwordsize; index ++)
{
/* Write the last input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DIN = 0U;
- index++;
- }
+ index++;
+ }
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
- {
- for(index=0U; index< 4U;index++)
- {
- /* Read the output block from the output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUT;
-
- /* Intermediate data buffer to be used in for the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
- hcryp->CrypOutCount++;
- }
- }
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
- {
- /*workaround in order to properly compute authentication tags while doing
- a GCM encryption with the last block of payload size inferior to 128 bits*/
- /* Change the AES mode to GCM mode and Select Final phase */
- /* configured CHMOD GCM */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
-
- /* configured final phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-
- if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
- {
- if ((npblb %4U)==1U)
- {
- intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
- }
- if ((npblb %4U)==2U)
- {
- intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
- }
- if ((npblb %4U)==3U)
- {
- intermediate_data[lastwordsize-1U] &= 0xFF000000U;
- }
- }
- else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
- {
- if ((npblb %4U)==1U)
- {
- intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U);
- }
- if ((npblb %4U)==2U)
- {
- intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U);
- }
- if ((npblb %4U)==3U)
- {
- intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U);
- }
- }
- else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
- {
- if ((npblb %4U)==1U)
- {
- intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16);
- }
- if ((npblb %4U)==2U)
- {
- intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16);
- }
- if ((npblb %4U)==3U)
- {
- intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16);
- }
- }
- else /*CRYP_DATATYPE_1B*/
- {
- if ((npblb %4U)==1U)
- {
- intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U);
- }
- if ((npblb %4U)==2U)
- {
- intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U);
- }
- if ((npblb %4U)==3U)
- {
- intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U);
- }
- }
- for (index=0U; index < lastwordsize; index ++)
- {
- /*Write the intermediate_data in the IN FIFO */
- hcryp->Instance->DIN=intermediate_data[index];
- }
- while(index < 4U)
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- index++;
- }
- /* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
@@ -5910,66 +6398,183 @@
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ }
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
+ {
+ for (index = 0U; index < 4U; index++)
{
- for( index=0U; index< 4U;index++)
+ /* Read the output block from the output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUT;
+
+ /* Intermediate data buffer to be used in for the workaround*/
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
+ }
+
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /*workaround in order to properly compute authentication tags while doing
+ a GCM encryption with the last block of payload size inferior to 128 bits*/
+ /* Change the AES mode to GCM mode and Select Final phase */
+ /* configured CHMOD GCM */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
+
+ /* configured final phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+
+ if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
+ {
+ if ((npblb % 4U) == 1U)
{
- intermediate_data[index]=hcryp->Instance->DOUT;
+ intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
+ }
+ }
+ else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
+ }
+ }
+ else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
+ }
+ }
+ else /*CRYP_DATATYPE_1B*/
+ {
+ if ((npblb % 4U) == 1U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
+ }
+ if ((npblb % 4U) == 2U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
+ }
+ if ((npblb % 4U) == 3U)
+ {
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
+ }
+ }
+ for (index = 0U; index < lastwordsize; index ++)
+ {
+ /*Write the intermediate_data in the IN FIFO */
+ hcryp->Instance->DIN = intermediate_data[index];
+ }
+ while (index < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ index++;
+ }
+ /* Wait for OFNE flag to be raised */
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
+ {
+ for (index = 0U; index < 4U; index++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUT;
}
}
}
} /* End of GCM encryption */
- else{ /* Workaround 2, case CCM decryption, in order to properly compute
- authentication tags while doing a CCM decryption with the last block
- of payload size inferior to 128 bits*/
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ else
+ {
+ /* Workaround 2, case CCM decryption, in order to properly compute
+ authentication tags while doing a CCM decryption with the last block
+ of payload size inferior to 128 bits*/
+
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
{
iv1temp = hcryp->Instance->CSGCMCCM7R;
-
+
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
-
- temp[0]= hcryp->Instance->CSGCMCCM0R;
- temp[1]= hcryp->Instance->CSGCMCCM1R;
- temp[2]= hcryp->Instance->CSGCMCCM2R;
- temp[3]= hcryp->Instance->CSGCMCCM3R;
-
- hcryp->Instance->IV1RR= iv1temp;
-
+
+ temp[0] = hcryp->Instance->CSGCMCCM0R;
+ temp[1] = hcryp->Instance->CSGCMCCM1R;
+ temp[2] = hcryp->Instance->CSGCMCCM2R;
+ temp[3] = hcryp->Instance->CSGCMCCM3R;
+
+ hcryp->Instance->IV1RR = iv1temp;
+
/* Configured CHMOD CTR */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-
+
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
- /* Last block optionally pad the data with zeros*/
- for(index=0; index < lastwordsize; index ++)
+ /* Last block optionally pad the data with zeros*/
+ for (index = 0; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
- hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DIN = 0U;
- index++;
+ index++;
}
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ __HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
@@ -5978,79 +6583,79 @@
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+
+ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
- for(index=0U; index< 4U;index++)
- {
+ for (index = 0U; index < 4U; index++)
+ {
/* Read the Output block from the Output FIFO */
intermediate_data[index] = hcryp->Instance->DOUT;
-
+
/*intermediate data buffer to be used in for the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
hcryp->CrypOutCount++;
}
}
-
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+
+ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
{
- temp2[0]= hcryp->Instance->CSGCMCCM0R;
- temp2[1]= hcryp->Instance->CSGCMCCM1R;
- temp2[2]= hcryp->Instance->CSGCMCCM2R;
- temp2[3]= hcryp->Instance->CSGCMCCM3R;
-
+ temp2[0] = hcryp->Instance->CSGCMCCM0R;
+ temp2[1] = hcryp->Instance->CSGCMCCM1R;
+ temp2[2] = hcryp->Instance->CSGCMCCM2R;
+ temp2[3] = hcryp->Instance->CSGCMCCM3R;
+
/* configured CHMOD CCM */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
-
+
/* configured Header phase */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
-
+
/*set to zero the bits corresponding to the padded bits*/
- for(index = lastwordsize; index<4U; index ++)
+ for (index = lastwordsize; index < 4U; index ++)
{
- intermediate_data[index] =0U;
+ intermediate_data[index] = 0U;
}
- if ((npblb %4U)==1U)
+ if ((npblb % 4U) == 1U)
{
- intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+ intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
}
- if ((npblb %4U)==2U)
+ if ((npblb % 4U) == 2U)
{
- intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+ intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
}
- if ((npblb %4U)==3U)
+ if ((npblb % 4U) == 3U)
{
- intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+ intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
}
- for(index=0U; index < 4U ; index ++)
+ for (index = 0U; index < 4U ; index ++)
{
intermediate_data[index] ^= temp[index];
- intermediate_data[index] ^= temp2[index];
+ intermediate_data[index] ^= temp2[index];
}
- for(index = 0U; index < 4U; index ++)
+ for (index = 0U; index < 4U; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DIN = intermediate_data[index] ;
}
-
+
/* Wait for BUSY flag to be raised */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -6061,144 +6666,144 @@
#else /* AES */
- /*Workaround 2: case GCM encryption, during payload phase and before inserting
- the last block of paylaod, which size is inferior to 128 bits */
-
- if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ /*Workaround 2: case GCM encryption, during payload phase and before inserting
+ the last block of paylaod, which size is inferior to 128 bits */
+
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* configured CHMOD CTR */
MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
- }
+ }
/* last block optionally pad the data with zeros*/
- for(index = 0U; index < lastwordsize; index ++)
+ for (index = 0U; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
- index++;
+ index++;
}
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
-
+
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- for(index = 0U; index< 4U;index++)
+
+ for (index = 0U; index < 4U; index++)
{
/* Read the Output block from the Output FIFO */
intermediate_data[index] = hcryp->Instance->DOUTR;
-
+
/*intermediate data buffer to be used in the workaround*/
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index];
- hcryp->CrypOutCount++;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
+ hcryp->CrypOutCount++;
}
-
- if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
- {
+
+ if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
/* configured CHMOD GCM */
MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
-
+
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
-
- if ( (hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
+
+ if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
{
- if ((npblb %4U)==1U)
+ if ((npblb % 4U) == 1U)
{
- intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+ intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
}
- if ((npblb %4U)==2U)
+ if ((npblb % 4U) == 2U)
{
- intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+ intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
}
- if ((npblb %4U)==3U)
+ if ((npblb % 4U) == 3U)
{
- intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+ intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
}
}
else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
{
- if ((npblb %4U)==1U)
+ if ((npblb % 4U) == 1U)
{
- intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U);
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
}
- if ((npblb %4U)==2U)
+ if ((npblb % 4U) == 2U)
{
- intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U);
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
}
- if ((npblb %4U)==3U)
+ if ((npblb % 4U) == 3U)
{
- intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U);
+ intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
}
}
else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
{
- if ((npblb %4U)==1U)
+ if ((npblb % 4U) == 1U)
{
- intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16);
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
}
- if ((npblb %4U)==2U)
+ if ((npblb % 4U) == 2U)
{
- intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16);
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
}
- if ((npblb %4U)==3U)
+ if ((npblb % 4U) == 3U)
{
- intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16);
+ intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
}
}
else /*CRYP_DATATYPE_1B*/
{
- if ((npblb %4U)==1U)
+ if ((npblb % 4U) == 1U)
{
- intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U);
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
}
- if ((npblb %4U)==2U)
+ if ((npblb % 4U) == 2U)
{
- intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U);
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
}
- if ((npblb %4U)==3U)
+ if ((npblb % 4U) == 3U)
{
- intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U);
+ intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
}
}
-
- /*Write the intermediate_data in the IN FIFO */
- for(index = 0U; index < lastwordsize; index ++)
+
+ /*Write the intermediate_data in the IN FIFO */
+ for (index = 0U; index < lastwordsize; index ++)
{
hcryp->Instance->DINR = intermediate_data[index];
- }
- while(index < 4U)
+ }
+ while (index < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
index++;
}
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -6207,104 +6812,104 @@
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- for( index = 0U; index< 4U;index++)
- {
- intermediate_data[index]=hcryp->Instance->DOUTR;
+
+ for (index = 0U; index < 4U; index++)
+ {
+ intermediate_data[index] = hcryp->Instance->DOUTR;
}
}/*End of Workaround 2*/
#endif /* End AES or CRYP */
}
#endif /* AES or GCM CCM defined*/
-#if defined (CRYP)
+#if defined (CRYP)
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
/**
* @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
- }
- return HAL_OK;
+ }
+ return HAL_OK;
}
#endif /* GCM CCM defined*/
/**
* @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+
+ while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
#else /* AES */
@@ -6312,29 +6917,29 @@
/**
* @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
+ * the configuration information for CRYP module.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
-
+
/* Get timeout */
tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
- {
+
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U) )
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
return HAL_ERROR;
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
#endif /* End AES or CRYP */
@@ -6342,8 +6947,8 @@
/**
* @}
- */
-
+ */
+
/**
diff --git a/Src/stm32f4xx_hal_cryp_ex.c b/Src/stm32f4xx_hal_cryp_ex.c
index c84f690..369a03c 100644
--- a/Src/stm32f4xx_hal_cryp_ex.c
+++ b/Src/stm32f4xx_hal_cryp_ex.c
@@ -3,17 +3,17 @@
* @file stm32f4xx_hal_cryp_ex.c
* @author MCD Application Team
* @brief Extended CRYP HAL module driver
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
- * + Extended AES processing functions
- *
+ * + Extended AES processing functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The CRYP extension HAL driver can be used as follows:
- (#)After AES-GCM or AES-CCM Encryption/Decryption user can start following API
+ (#)After AES-GCM or AES-CCM Encryption/Decryption user can start following API
to get the authentication messages :
(##) HAL_CRYPEx_AESGCM_GenerateAuthTAG
(##) HAL_CRYPEx_AESCCM_GenerateAuthTAG
@@ -22,16 +22,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -55,10 +55,10 @@
* @{
*/
#if defined(AES)
-#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
-#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */
@@ -77,11 +77,11 @@
#endif /* End AES or CRYP */
#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
-#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
+#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
- /* CTR0 information to use in CCM algorithm */
-#define CRYP_CCM_CTR0_0 0x07FFFFFFU
-#define CRYP_CCM_CTR0_3 0xFFFFFF00U
+/* CTR0 information to use in CCM algorithm */
+#define CRYP_CCM_CTR0_0 0x07FFFFFFU
+#define CRYP_CCM_CTR0_3 0xFFFFFF00U
/**
@@ -99,15 +99,15 @@
* @{
*/
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
- * @brief Extended processing functions.
- *
-@verbatim
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ * @brief Extended processing functions.
+ *
+@verbatim
==============================================================================
##### Extended AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to generate the authentication
- TAG in Polling mode
+ ==============================================================================
+ [..] This section provides functions allowing to generate the authentication
+ TAG in Polling mode
(#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
(#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
they should be used after Encrypt/Decrypt operation.
@@ -127,79 +127,79 @@
*/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
- uint32_t tickstart;
+ uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
- uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
- uint32_t tagaddr = (uint32_t)AuthTag;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+ uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
+ uint32_t tagaddr = (uint32_t)AuthTag;
+
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
/* Process locked */
__HAL_LOCK(hcryp);
-
+
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
-
+
/* Check if initialization phase has already been performed */
- if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
}
else /* Initialization phase has not been performed*/
- {
+ {
/* Disable the Peripheral */
__HAL_CRYP_DISABLE(hcryp);
-
- /* Sequence error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
-
+
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
/* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
-
+
#if defined(CRYP)
-
+
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-
- /*ALGODIR bit must be set to ‘0’.*/
+
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+
+ /*ALGODIR bit must be set to ‘0’.*/
hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
-
+
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
-
+
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
- hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
+ hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
@@ -210,68 +210,68 @@
{
/* Nothing to do */
}
-
+
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
/* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
- }
-
+ }
+
/* Read the authentication TAG in the output FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
-
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+
#else /* AES*/
-
+
/* Select final phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
-
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
/* Write the number of bits in header (64 bits) followed by the number of bits
- in the payload */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ in the payload */
+ if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __REV((uint32_t)(headerlength));
hcryp->Instance->DINR = 0U;
- hcryp->Instance->DINR = __REV((uint32_t)(inputlength));
+ hcryp->Instance->DINR = __REV((uint32_t)(inputlength));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = (uint32_t)(headerlength);
@@ -284,56 +284,56 @@
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
- {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
- }
-
+ }
+
/* Read the authentication TAG in the output FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
-
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+
/* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
-#endif /* End AES or CRYP */
-
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+#endif /* End AES or CRYP */
+
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
-
+
/* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Process unlocked */
__HAL_UNLOCK(hcryp);
}
else
{
/* Busy error code field */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
- }
+ }
/* Return function status */
return HAL_OK;
}
@@ -349,11 +349,11 @@
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tagaddr = (uint32_t)AuthTag;
- uint32_t ctr0 [4]={0};
+ uint32_t ctr0 [4] = {0};
uint32_t ctr0addr = (uint32_t)ctr0;
uint32_t tickstart;
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
@@ -362,7 +362,7 @@
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
- if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
@@ -383,72 +383,72 @@
return HAL_ERROR;
}
-#if defined(CRYP)
+#if defined(CRYP)
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
/* Select final phase & ALGODIR bit must be set to ‘0’. */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
- ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
- ctr0[1]=hcryp->Init.B0[1];
- ctr0[2]=hcryp->Init.B0[2];
- ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
+ ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1] = hcryp->Init.B0[1];
+ ctr0[2] = hcryp->Init.B0[2];
+ ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -465,13 +465,13 @@
}
/* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
#else /* AES */
@@ -480,75 +480,75 @@
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
- if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
- ctr0[0]=(__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
- ctr0[1]=__REV(hcryp->Init.B0[1]);
- ctr0[2]=__REV(hcryp->Init.B0[2]);
- ctr0[3]=(__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
+ ctr0[0] = (__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
+ ctr0[1] = __REV(hcryp->Init.B0[1]);
+ ctr0[2] = __REV(hcryp->Init.B0[2]);
+ ctr0[3] = (__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr));
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- ctr0[0]= ( __ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
- ctr0[1]= __ROR((hcryp->Init.B0[1]), 16U);
- ctr0[2]= __ROR((hcryp->Init.B0[2]), 16U);
- ctr0[3]= ( __ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
+ ctr0[0] = (__ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
+ ctr0[1] = __ROR((hcryp->Init.B0[1]), 16U);
+ ctr0[2] = __ROR((hcryp->Init.B0[2]), 16U);
+ ctr0[3] = (__ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
- ctr0addr+=4U;
- hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
- else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- ctr0[0]=(__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
- ctr0[1]=__RBIT(hcryp->Init.B0[1]);
- ctr0[2]=__RBIT(hcryp->Init.B0[2]);
- ctr0[3]=(__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
+ ctr0[0] = (__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
+ ctr0[1] = __RBIT(hcryp->Init.B0[1]);
+ ctr0[2] = __RBIT(hcryp->Init.B0[2]);
+ ctr0[3] = (__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
- ctr0addr+=4U;
- hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
- ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
- ctr0[1]=hcryp->Init.B0[1];
- ctr0[2]=hcryp->Init.B0[2];
- ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
+ ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1] = hcryp->Init.B0[1];
+ ctr0[2] = hcryp->Init.B0[2];
+ ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
- ctr0addr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
+ ctr0addr += 4U;
+ hcryp->Instance->DINR = *(uint32_t *)(ctr0addr);
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -565,13 +565,13 @@
}
/* Read the authentication TAG in the output FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr += 4U;
+ *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -594,7 +594,7 @@
return HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -603,12 +603,12 @@
#if defined (AES)
/** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions
- * @brief AutoKeyDerivation functions
- *
+ * @brief AutoKeyDerivation functions
+ *
@verbatim
==============================================================================
##### Key Derivation functions #####
- ==============================================================================
+ ==============================================================================
[..] This section provides functions allowing to Enable or Disable the
the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
These function are allowed only in TinyAES IP.
@@ -624,15 +624,15 @@
*/
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
+ if (hcryp->State == HAL_CRYP_STATE_READY)
+ {
hcryp->AutoKeyDerivation = ENABLE;
}
else
{
/* Busy error code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
- }
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+ }
}
/**
* @brief AES disable key derivation functions
@@ -641,22 +641,22 @@
*/
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if (hcryp->State == HAL_CRYP_STATE_READY)
{
hcryp->AutoKeyDerivation = DISABLE;
}
else
{
/* Busy error code field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
- }
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+ }
}
/**
* @}
*/
#endif /* AES or GCM CCM defined*/
-#endif /* AES */
+#endif /* AES */
#endif /* HAL_CRYP_MODULE_ENABLED */
/**
diff --git a/Src/stm32f4xx_hal_fmpi2c.c b/Src/stm32f4xx_hal_fmpi2c.c
index 44f64f3..d4f42d5 100644
--- a/Src/stm32f4xx_hal_fmpi2c.c
+++ b/Src/stm32f4xx_hal_fmpi2c.c
@@ -352,13 +352,13 @@
/* Private define to centralize the enable/disable of Interrupts */
-#define FMPI2C_XFER_TX_IT (0x00000001U)
-#define FMPI2C_XFER_RX_IT (0x00000002U)
-#define FMPI2C_XFER_LISTEN_IT (0x00000004U)
+#define FMPI2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */
+#define FMPI2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */
+#define FMPI2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref FMPI2C_XFER_TX_IT and @ref FMPI2C_XFER_RX_IT */
-#define FMPI2C_XFER_ERROR_IT (0x00000011U)
-#define FMPI2C_XFER_CPLT_IT (0x00000012U)
-#define FMPI2C_XFER_RELOAD_IT (0x00000012U)
+#define FMPI2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
+#define FMPI2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
+#define FMPI2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define FMPI2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -411,6 +411,9 @@
static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
static void FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+/* Private function to treat different error callback */
+static void FMPI2C_TreatErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+
/* Private function to flush TXDR register */
static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c);
@@ -3201,7 +3204,7 @@
FMPI2C_ConvertOtherXferOptions(hfmpi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hfmpi2c->XferOptions;
}
@@ -3286,7 +3289,7 @@
FMPI2C_ConvertOtherXferOptions(hfmpi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hfmpi2c->XferOptions;
}
@@ -3447,7 +3450,7 @@
FMPI2C_ConvertOtherXferOptions(hfmpi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hfmpi2c->XferOptions;
}
@@ -3532,7 +3535,7 @@
FMPI2C_ConvertOtherXferOptions(hfmpi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hfmpi2c->XferOptions;
}
@@ -4252,9 +4255,21 @@
/* Process Locked */
__HAL_LOCK(hfmpi2c);
- /* Disable Interrupts */
- FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
- FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
+ {
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ {
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+ hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Set State at HAL_FMPI2C_STATE_ABORT */
hfmpi2c->State = HAL_FMPI2C_STATE_ABORT;
@@ -5002,6 +5017,7 @@
{
uint32_t tmpoptions = hfmpi2c->XferOptions;
uint32_t treatdmanack = 0U;
+ HAL_FMPI2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hfmpi2c);
@@ -5080,8 +5096,24 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ /* Store current hfmpi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hfmpi2c->State;
+
if ((tmpoptions == FMPI2C_FIRST_FRAME) || (tmpoptions == FMPI2C_NEXT_FRAME))
{
+ if ((tmpstate == HAL_FMPI2C_STATE_BUSY_TX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
+ {
+ hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_FMPI2C_STATE_BUSY_RX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
+ {
+ hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
}
@@ -5370,9 +5402,27 @@
*/
static void FMPI2C_ITSlaveSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c)
{
+ uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1);
+
/* Reset FMPI2C handle mode */
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+ /* If a DMA is ongoing, Update handle size context */
+ if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+ }
+ else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
@@ -5427,19 +5477,36 @@
static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
{
uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ uint32_t tmp;
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ /* Disable Interrupts and Store Previous state */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
+ {
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ {
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+ hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Clear Configuration Register 2 */
FMPI2C_RESET_CR2(hfmpi2c);
/* Reset handle parameters */
- hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
hfmpi2c->XferISR = NULL;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
- if (FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET)
+ if (FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -5448,12 +5515,18 @@
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
+ /* Fetch Last receive data if any */
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) && (FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmp = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ UNUSED(tmp);
+ }
+
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
- /* Disable Interrupts */
- FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
-
/* Store current volatile hfmpi2c->ErrorCode, misra rule */
tmperror = hfmpi2c->ErrorCode;
@@ -5467,6 +5540,7 @@
else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
{
@@ -5501,6 +5575,7 @@
else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
{
@@ -5547,12 +5622,26 @@
{
uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State;
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
- /* Disable all interrupts */
- FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_FMPI2C_STATE_BUSY_TX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
+ {
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT);
+ hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_FMPI2C_STATE_BUSY_RX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
+ {
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT);
+ hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -5566,6 +5655,9 @@
/* If a DMA is ongoing, Update handle size context */
if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_TXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
if (hfmpi2c->hdmatx != NULL)
{
hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx);
@@ -5573,6 +5665,9 @@
}
else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
if (hfmpi2c->hdmarx != NULL)
{
hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx);
@@ -5609,7 +5704,6 @@
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
- hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
hfmpi2c->XferISR = NULL;
@@ -5632,6 +5726,7 @@
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -5647,6 +5742,7 @@
else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -5661,6 +5757,7 @@
else
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -5734,6 +5831,7 @@
static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
{
HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State;
+ uint32_t tmppreviousstate;
/* Reset handle parameters */
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
@@ -5753,7 +5851,6 @@
/* keep HAL_FMPI2C_STATE_LISTEN if set */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
- hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
}
else
@@ -5768,16 +5865,19 @@
/* Set HAL_FMPI2C_STATE_READY */
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
}
- hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
hfmpi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
- if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+ tmppreviousstate = hfmpi2c->PreviousState;
+ if ((hfmpi2c->hdmatx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX)))
{
- hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+ }
- if (hfmpi2c->hdmatx != NULL)
+ if (HAL_DMA_GetState(hfmpi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the FMPI2C DMA Abort callback :
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
@@ -5793,13 +5893,20 @@
hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
}
}
+ else
+ {
+ FMPI2C_TreatErrorCallback(hfmpi2c);
+ }
}
/* Abort DMA RX transfer if any */
- else if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+ else if ((hfmpi2c->hdmarx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX)))
{
- hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+ }
- if (hfmpi2c->hdmarx != NULL)
+ if (HAL_DMA_GetState(hfmpi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the FMPI2C DMA Abort callback :
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
@@ -5815,10 +5922,28 @@
hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
}
}
+ else
+ {
+ FMPI2C_TreatErrorCallback(hfmpi2c);
+ }
}
- else if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
+ else
+ {
+ FMPI2C_TreatErrorCallback(hfmpi2c);
+ }
+}
+
+/**
+ * @brief FMPI2C Error callback treatment.
+ * @param hfmpi2c FMPI2C handle.
+ * @retval None
+ */
+static void FMPI2C_TreatErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -5832,6 +5957,8 @@
}
else
{
+ hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -6066,27 +6193,7 @@
hfmpi2c->hdmatx->XferAbortCallback = NULL;
hfmpi2c->hdmarx->XferAbortCallback = NULL;
- /* Check if come from abort from user */
- if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
- {
- hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
- hfmpi2c->AbortCpltCallback(hfmpi2c);
-#else
- HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
-#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
- }
- else
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
- hfmpi2c->ErrorCallback(hfmpi2c);
-#else
- HAL_FMPI2C_ErrorCallback(hfmpi2c);
-#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
- }
+ FMPI2C_TreatErrorCallback(hfmpi2c);
}
/**
@@ -6363,19 +6470,19 @@
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
- if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+ if (InterruptRequest == FMPI2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
}
- if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ if (InterruptRequest == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= FMPI2C_IT_STOPI;
+ tmpisr |= (FMPI2C_IT_STOPI | FMPI2C_IT_TCI);
}
- if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+ if (InterruptRequest == FMPI2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= FMPI2C_IT_TCI;
@@ -6401,7 +6508,7 @@
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
}
- if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ if (InterruptRequest == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI;
@@ -6455,19 +6562,19 @@
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
- if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+ if (InterruptRequest == FMPI2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
}
- if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ if (InterruptRequest == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI;
}
- if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+ if (InterruptRequest == FMPI2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= FMPI2C_IT_TCI;
diff --git a/Src/stm32f4xx_hal_fmpsmbus.c b/Src/stm32f4xx_hal_fmpsmbus.c
new file mode 100644
index 0000000..3d0cd20
--- /dev/null
+++ b/Src/stm32f4xx_hal_fmpsmbus.c
@@ -0,0 +1,2675 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_fmpsmbus.c
+ * @author MCD Application Team
+ * @brief FMPSMBUS HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the System Management Bus (SMBus) peripheral,
+ * based on I2C principles of operation :
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The FMPSMBUS HAL driver can be used as follows:
+
+ (#) Declare a FMPSMBUS_HandleTypeDef handle structure, for example:
+ FMPSMBUS_HandleTypeDef hfmpsmbus;
+
+ (#)Initialize the FMPSMBUS low level resources by implementing the @ref HAL_FMPSMBUS_MspInit() API:
+ (##) Enable the FMPSMBUSx interface clock
+ (##) FMPSMBUS pins configuration
+ (+++) Enable the clock for the FMPSMBUS GPIOs
+ (+++) Configure FMPSMBUS pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the FMPSMBUSx interrupt priority
+ (+++) Enable the NVIC FMPSMBUS IRQ Channel
+
+ (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+ Peripheral mode and Packet Error Check mode in the hfmpsmbus Init structure.
+
+ (#) Initialize the FMPSMBUS registers by calling the @ref HAL_FMPSMBUS_Init() API:
+ (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized @ref HAL_FMPSMBUS_MspInit(&hfmpsmbus) API.
+
+ (#) To check if target device is ready for communication, use the function @ref HAL_FMPSMBUS_IsDeviceReady()
+
+ (#) For FMPSMBUS IO operations, only one mode of operations is available within this driver
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_FMPSMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Receive_IT()
+ (++) At reception end of transfer @ref HAL_FMPSMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host FMPSMBUS process communication with Interrupt using @ref HAL_FMPSMBUS_Master_Abort_IT()
+ (++) The associated previous transfer callback is called at the end of abort process
+ (++) mean @ref HAL_FMPSMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean @ref HAL_FMPSMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (+) Enable/disable the Address listen mode in slave/device or host/slave FMPSMBUS mode
+ using @ref HAL_FMPSMBUS_EnableListen_IT() @ref HAL_FMPSMBUS_DisableListen_IT()
+ (++) When address slave/device FMPSMBUS match, @ref HAL_FMPSMBUS_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
+ (++) At Listen mode end @ref HAL_FMPSMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPSMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer @ref HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the FMPSMBUS alert mode using @ref HAL_FMPSMBUS_EnableAlert_IT() @ref HAL_FMPSMBUS_DisableAlert_IT()
+ (++) When FMPSMBUS Alert is generated @ref HAL_FMPSMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback()
+ to check the Alert Error Code using function @ref HAL_FMPSMBUS_GetError()
+ (+) Get HAL state machine or error values using @ref HAL_FMPSMBUS_GetState() or @ref HAL_FMPSMBUS_GetError()
+ (+) In case of transfer Error, @ref HAL_FMPSMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback()
+ to check the Error Code using function @ref HAL_FMPSMBUS_GetError()
+
+ *** FMPSMBUS HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in FMPSMBUS HAL driver.
+
+ (+) @ref __HAL_FMPSMBUS_ENABLE: Enable the FMPSMBUS peripheral
+ (+) @ref __HAL_FMPSMBUS_DISABLE: Disable the FMPSMBUS peripheral
+ (+) @ref __HAL_FMPSMBUS_GET_FLAG: Check whether the specified FMPSMBUS flag is set or not
+ (+) @ref __HAL_FMPSMBUS_CLEAR_FLAG: Clear the specified FMPSMBUS pending flag
+ (+) @ref __HAL_FMPSMBUS_ENABLE_IT: Enable the specified FMPSMBUS interrupt
+ (+) @ref __HAL_FMPSMBUS_DISABLE_IT: Disable the specified FMPSMBUS interrupt
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_FMPSMBUS_RegisterCallback() or @ref HAL_FMPSMBUS_RegisterAddrCallback()
+ to register an interrupt callback.
+ [..]
+ Function @ref HAL_FMPSMBUS_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_RegisterAddrCallback.
+ [..]
+ Use function @ref HAL_FMPSMBUS_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_FMPSMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_UnRegisterAddrCallback.
+ [..]
+ By default, after the @ref HAL_FMPSMBUS_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_FMPSMBUS_MasterTxCpltCallback(), @ref HAL_FMPSMBUS_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+ Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_FMPSMBUS_RegisterCallback() before calling @ref HAL_FMPSMBUS_DeInit()
+ or @ref HAL_FMPSMBUS_Init() function.
+ [..]
+ When the compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ [..]
+ (@) You can refer to the FMPSMBUS HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FMPSMBUS FMPSMBUS
+ * @brief FMPSMBUS HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+
+#if defined(FMPI2C_CR1_PE)
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FMPSMBUS_Private_Define FMPSMBUS Private Constants
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< FMPSMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define MAX_NBYTE_SIZE 255U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+static void FMPSMBUS_Enable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
+static void FMPSMBUS_Disable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest);
+static HAL_StatusTypeDef FMPSMBUS_Master_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags);
+
+static void FMPSMBUS_ConvertOtherXferOptions(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+static void FMPSMBUS_ITErrorHandler(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
+
+static void FMPSMBUS_TransferConfig(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions
+ * @{
+ */
+
+/** @defgroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the FMPSMBUSx peripheral:
+
+ (+) User must Implement HAL_FMPSMBUS_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+ (+) Call the function HAL_FMPSMBUS_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Bus Timeout
+ (++) Analog Filer mode
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+ (++) Packet Error Check mode
+ (++) Peripheral mode
+
+
+ (+) Call the function HAL_FMPSMBUS_DeInit() to restore the default configuration
+ of the selected FMPSMBUSx peripheral.
+
+ (+) Enable/Disable Analog/Digital filters with HAL_FMPSMBUS_ConfigAnalogFilter() and
+ HAL_FMPSMBUS_ConfigDigitalFilter().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FMPSMBUS according to the specified parameters
+ * in the FMPSMBUS_InitTypeDef and initialize the associated handle.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Check the FMPSMBUS handle allocation */
+ if (hfmpsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance));
+ assert_param(IS_FMPSMBUS_ANALOG_FILTER(hfmpsmbus->Init.AnalogFilter));
+ assert_param(IS_FMPSMBUS_OWN_ADDRESS1(hfmpsmbus->Init.OwnAddress1));
+ assert_param(IS_FMPSMBUS_ADDRESSING_MODE(hfmpsmbus->Init.AddressingMode));
+ assert_param(IS_FMPSMBUS_DUAL_ADDRESS(hfmpsmbus->Init.DualAddressMode));
+ assert_param(IS_FMPSMBUS_OWN_ADDRESS2(hfmpsmbus->Init.OwnAddress2));
+ assert_param(IS_FMPSMBUS_OWN_ADDRESS2_MASK(hfmpsmbus->Init.OwnAddress2Masks));
+ assert_param(IS_FMPSMBUS_GENERAL_CALL(hfmpsmbus->Init.GeneralCallMode));
+ assert_param(IS_FMPSMBUS_NO_STRETCH(hfmpsmbus->Init.NoStretchMode));
+ assert_param(IS_FMPSMBUS_PEC(hfmpsmbus->Init.PacketErrorCheckMode));
+ assert_param(IS_FMPSMBUS_PERIPHERAL_MODE(hfmpsmbus->Init.PeripheralMode));
+
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfmpsmbus->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->MasterTxCpltCallback = HAL_FMPSMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hfmpsmbus->MasterRxCpltCallback = HAL_FMPSMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hfmpsmbus->SlaveTxCpltCallback = HAL_FMPSMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hfmpsmbus->SlaveRxCpltCallback = HAL_FMPSMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hfmpsmbus->ListenCpltCallback = HAL_FMPSMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hfmpsmbus->ErrorCallback = HAL_FMPSMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ hfmpsmbus->AddrCallback = HAL_FMPSMBUS_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hfmpsmbus->MspInitCallback == NULL)
+ {
+ hfmpsmbus->MspInitCallback = HAL_FMPSMBUS_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hfmpsmbus->MspInitCallback(hfmpsmbus);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_FMPSMBUS_MspInit(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY;
+
+ /* Disable the selected FMPSMBUS peripheral */
+ __HAL_FMPSMBUS_DISABLE(hfmpsmbus);
+
+ /*---------------------------- FMPSMBUSx TIMINGR Configuration ------------------------*/
+ /* Configure FMPSMBUSx: Frequency range */
+ hfmpsmbus->Instance->TIMINGR = hfmpsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- FMPSMBUSx TIMEOUTR Configuration ------------------------*/
+ /* Configure FMPSMBUSx: Bus Timeout */
+ hfmpsmbus->Instance->TIMEOUTR &= ~FMPI2C_TIMEOUTR_TIMOUTEN;
+ hfmpsmbus->Instance->TIMEOUTR &= ~FMPI2C_TIMEOUTR_TEXTEN;
+ hfmpsmbus->Instance->TIMEOUTR = hfmpsmbus->Init.SMBusTimeout;
+
+ /*---------------------------- FMPSMBUSx OAR1 Configuration -----------------------*/
+ /* Configure FMPSMBUSx: Own Address1 and ack own address1 mode */
+ hfmpsmbus->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN;
+
+ if (hfmpsmbus->Init.OwnAddress1 != 0UL)
+ {
+ if (hfmpsmbus->Init.AddressingMode == FMPSMBUS_ADDRESSINGMODE_7BIT)
+ {
+ hfmpsmbus->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpsmbus->Init.OwnAddress1);
+ }
+ else /* FMPSMBUS_ADDRESSINGMODE_10BIT */
+ {
+ hfmpsmbus->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpsmbus->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- FMPSMBUSx CR2 Configuration ------------------------*/
+ /* Configure FMPSMBUSx: Addressing Master mode */
+ if (hfmpsmbus->Init.AddressingMode == FMPSMBUS_ADDRESSINGMODE_10BIT)
+ {
+ hfmpsmbus->Instance->CR2 = (FMPI2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+ /* AUTOEND and NACK bit will be manage during Transfer process */
+ hfmpsmbus->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK);
+
+ /*---------------------------- FMPSMBUSx OAR2 Configuration -----------------------*/
+ /* Configure FMPSMBUSx: Dual mode and Own Address2 */
+ hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | (hfmpsmbus->Init.OwnAddress2Masks << 8U));
+
+ /*---------------------------- FMPSMBUSx CR1 Configuration ------------------------*/
+ /* Configure FMPSMBUSx: Generalcall and NoStretch mode */
+ hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | hfmpsmbus->Init.AnalogFilter);
+
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled and FMPSMBUS Peripheral is set in Slave mode */
+ if ((hfmpsmbus->Init.PacketErrorCheckMode == FMPSMBUS_PEC_ENABLE)
+ && ((hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || (hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)))
+ {
+ hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC;
+ }
+
+ /* Enable the selected FMPSMBUS peripheral */
+ __HAL_FMPSMBUS_ENABLE(hfmpsmbus);
+
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+ hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the FMPSMBUS peripheral.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Check the FMPSMBUS handle allocation */
+ if (hfmpsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance));
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY;
+
+ /* Disable the FMPSMBUS Peripheral Clock */
+ __HAL_FMPSMBUS_DISABLE(hfmpsmbus);
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ if (hfmpsmbus->MspDeInitCallback == NULL)
+ {
+ hfmpsmbus->MspDeInitCallback = HAL_FMPSMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hfmpsmbus->MspDeInitCallback(hfmpsmbus);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_FMPSMBUS_MspDeInit(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+ hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_RESET;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMPSMBUS MSP.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the FMPSMBUS MSP.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Configure Analog noise filter.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_ANALOGFILTER_ENABLE
+ * @arg @ref FMPSMBUS_ANALOGFILTER_DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance));
+ assert_param(IS_FMPSMBUS_ANALOG_FILTER(AnalogFilter));
+
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY;
+
+ /* Disable the selected FMPSMBUS peripheral */
+ __HAL_FMPSMBUS_DISABLE(hfmpsmbus);
+
+ /* Reset ANOFF bit */
+ hfmpsmbus->Instance->CR1 &= ~(FMPI2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hfmpsmbus->Instance->CR1 |= AnalogFilter;
+
+ __HAL_FMPSMBUS_ENABLE(hfmpsmbus);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure Digital noise filter.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg;
+
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance));
+ assert_param(IS_FMPSMBUS_DIGITAL_FILTER(DigitalFilter));
+
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY;
+
+ /* Disable the selected FMPSMBUS peripheral */
+ __HAL_FMPSMBUS_DISABLE(hfmpsmbus);
+
+ /* Get the old register value */
+ tmpreg = hfmpsmbus->Instance->CR1;
+
+ /* Reset FMPI2C DNF bits [11:8] */
+ tmpreg &= ~(FMPI2C_CR1_DNF);
+
+ /* Set FMPI2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << FMPI2C_CR1_DNF_Pos;
+
+ /* Store the new register value */
+ hfmpsmbus->Instance->CR1 = tmpreg;
+
+ __HAL_FMPSMBUS_ENABLE(hfmpsmbus);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User FMPSMBUS Callback
+ * To be used instead of the weak predefined callback
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_FMPSMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_FMPSMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FMPSMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hfmpsmbus->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hfmpsmbus->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hfmpsmbus->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hfmpsmbus->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID :
+ hfmpsmbus->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_ERROR_CB_ID :
+ hfmpsmbus->ErrorCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_MSPINIT_CB_ID :
+ hfmpsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_MSPDEINIT_CB_ID :
+ hfmpsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_FMPSMBUS_STATE_RESET == hfmpsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPSMBUS_MSPINIT_CB_ID :
+ hfmpsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMPSMBUS_MSPDEINIT_CB_ID :
+ hfmpsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpsmbus);
+ return status;
+}
+
+/**
+ * @brief Unregister an FMPSMBUS Callback
+ * FMPSMBUS callback is redirected to the weak predefined callback
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_FMPSMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_FMPSMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FMPSMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hfmpsmbus->MasterTxCpltCallback = HAL_FMPSMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hfmpsmbus->MasterRxCpltCallback = HAL_FMPSMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hfmpsmbus->SlaveTxCpltCallback = HAL_FMPSMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hfmpsmbus->SlaveRxCpltCallback = HAL_FMPSMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID :
+ hfmpsmbus->ListenCpltCallback = HAL_FMPSMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_FMPSMBUS_ERROR_CB_ID :
+ hfmpsmbus->ErrorCallback = HAL_FMPSMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_FMPSMBUS_MSPINIT_CB_ID :
+ hfmpsmbus->MspInitCallback = HAL_FMPSMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_FMPSMBUS_MSPDEINIT_CB_ID :
+ hfmpsmbus->MspDeInitCallback = HAL_FMPSMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_FMPSMBUS_STATE_RESET == hfmpsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPSMBUS_MSPINIT_CB_ID :
+ hfmpsmbus->MspInitCallback = HAL_FMPSMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_FMPSMBUS_MSPDEINIT_CB_ID :
+ hfmpsmbus->MspDeInitCallback = HAL_FMPSMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpsmbus);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match FMPSMBUS Callback
+ * To be used instead of the weak HAL_FMPSMBUS_AddrCallback() predefined callback
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
+ {
+ hfmpsmbus->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpsmbus);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match FMPSMBUS Callback
+ * Info Ready FMPSMBUS Callback is redirected to the weak HAL_FMPSMBUS_AddrCallback() predefined callback
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State)
+ {
+ hfmpsmbus->AddrCallback = HAL_FMPSMBUS_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpsmbus);
+ return status;
+}
+
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FMPSMBUS data
+ transfers.
+
+ (#) Blocking mode function to check if device is ready for usage is :
+ (++) HAL_FMPSMBUS_IsDeviceReady()
+
+ (#) There is only one mode of transfer:
+ (++) Non-Blocking mode : The communication is performed using Interrupts.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated FMPSMBUS IRQ when using Interrupt mode.
+
+ (#) Non-Blocking mode functions with Interrupt are :
+ (++) HAL_FMPSMBUS_Master_Transmit_IT()
+ (++) HAL_FMPSMBUS_Master_Receive_IT()
+ (++) HAL_FMPSMBUS_Slave_Transmit_IT()
+ (++) HAL_FMPSMBUS_Slave_Receive_IT()
+ (++) HAL_FMPSMBUS_EnableListen_IT() or alias HAL_FMPSMBUS_EnableListen_IT()
+ (++) HAL_FMPSMBUS_DisableListen_IT()
+ (++) HAL_FMPSMBUS_EnableAlert_IT()
+ (++) HAL_FMPSMBUS_DisableAlert_IT()
+
+ (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+ (++) HAL_FMPSMBUS_MasterTxCpltCallback()
+ (++) HAL_FMPSMBUS_MasterRxCpltCallback()
+ (++) HAL_FMPSMBUS_SlaveTxCpltCallback()
+ (++) HAL_FMPSMBUS_SlaveRxCpltCallback()
+ (++) HAL_FMPSMBUS_AddrCallback()
+ (++) HAL_FMPSMBUS_ListenCpltCallback()
+ (++) HAL_FMPSMBUS_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_TX;
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hfmpsmbus->pBuffPtr = pData;
+ hfmpsmbus->XferCount = Size;
+ hfmpsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hfmpsmbus->pBuffPtr == NULL)
+ {
+ hfmpsmbus->XferOptions &= ~FMPSMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hfmpsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_WRITE);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+
+ /* Store current volatile XferOptions, misra rule */
+ tmp = hfmpsmbus->XferOptions;
+
+ if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus);
+
+ /* Handle Transfer */
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_WRITE);
+ }
+
+ /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL)
+ {
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPSMBUS interrupt handle execution before current
+ process unlock */
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_RX;
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpsmbus->pBuffPtr = pData;
+ hfmpsmbus->XferCount = Size;
+ hfmpsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if (hfmpsmbus->pBuffPtr == NULL)
+ {
+ hfmpsmbus->XferOptions &= ~FMPSMBUS_AUTOEND_MODE;
+ }
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hfmpsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_READ);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+
+ /* Store current volatile XferOptions, Misra rule */
+ tmp = hfmpsmbus->XferOptions;
+
+ if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus);
+
+ /* Handle Transfer */
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_READ);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPSMBUS interrupt handle execution before current
+ process unlock */
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master/host FMPSMBUS process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress)
+{
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ /* Keep the same state as previous */
+ /* to perform as well the call of the corresponding end of transfer callback */
+ if (hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX)
+ {
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_TX;
+ }
+ else if (hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX)
+ {
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+
+ /* Set NBYTES to 1 to generate a dummy read on FMPSMBUS peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, 1, FMPSMBUS_AUTOEND_MODE, FMPSMBUS_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPSMBUS interrupt handle execution before current
+ process unlock */
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX)
+ {
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX);
+ }
+ else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX)
+ {
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR | FMPSMBUS_IT_TX);
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ hfmpsmbus->State = (HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX | HAL_FMPSMBUS_STATE_LISTEN);
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hfmpsmbus->pBuffPtr = pData;
+ hfmpsmbus->XferCount = Size;
+ hfmpsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus);
+
+ if (Size > MAX_NBYTE_SIZE)
+ {
+ hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hfmpsmbus->XferSize = Size;
+ }
+
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE))
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ /* Set NBYTE to transmit */
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP);
+
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL)
+ {
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPSMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX | FMPSMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR | FMPSMBUS_IT_RX);
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ hfmpsmbus->State = (HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX | HAL_FMPSMBUS_STATE_LISTEN);
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hfmpsmbus->pBuffPtr = pData;
+ hfmpsmbus->XferSize = Size;
+ hfmpsmbus->XferCount = Size;
+ hfmpsmbus->XferOptions = XferOptions;
+
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus);
+
+ /* Set NBYTE to receive */
+ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+ /* This RELOAD bit will be reset for last BYTE to be receive in FMPSMBUS_Slave_ISR */
+ if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U))
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, hfmpsmbus->XferOptions | FMPSMBUS_RELOAD_MODE, FMPSMBUS_NO_STARTSTOP);
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPSMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX | FMPSMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_LISTEN;
+
+ /* Enable the Address Match interrupt */
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_LISTEN)
+ {
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Disable the Address Match interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the FMPSMBUS alert mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Enable SMBus alert */
+ hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_ALERTEN;
+
+ /* Clear ALERT flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ALERT);
+
+ /* Enable Alert Interrupt */
+ FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+/**
+ * @brief Disable the FMPSMBUS alert mode with Interrupt.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Enable SMBus alert */
+ hfmpsmbus->Instance->CR1 &= ~FMPI2C_CR1_ALERTEN;
+
+ /* Disable Alert Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if target device is ready for communication.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ __IO uint32_t FMPSMBUS_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
+
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY)
+ {
+ if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_BUSY) != RESET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY;
+ hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hfmpsmbus->Instance->CR2 = FMPSMBUS_GENERATE_START(hfmpsmbus->Init.AddressingMode, DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+ tmp2 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Device is ready */
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Update FMPSMBUS error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+ return HAL_ERROR;
+ }
+ }
+
+ tmp1 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+ tmp2 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF);
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if (FMPSMBUS_WaitOnFlagUntilTimeout(hfmpsmbus, FMPSMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+
+ /* Device is ready */
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if (FMPSMBUS_WaitOnFlagUntilTimeout(hfmpsmbus, FMPSMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (FMPSMBUS_Trials == Trials)
+ {
+ /* Generate Stop */
+ hfmpsmbus->Instance->CR2 |= FMPI2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if (FMPSMBUS_WaitOnFlagUntilTimeout(hfmpsmbus, FMPSMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+ }
+
+ /* Increment Trials */
+ FMPSMBUS_Trials++;
+ }
+ while (FMPSMBUS_Trials < Trials);
+
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Update FMPSMBUS error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle FMPSMBUS event interrupt request.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Use a local variable to store the current ISR flags */
+ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+ uint32_t tmpisrvalue = READ_REG(hfmpsmbus->Instance->ISR);
+ uint32_t tmpcr1value = READ_REG(hfmpsmbus->Instance->CR1);
+
+ /* FMPSMBUS in mode Transmitter ---------------------------------------------------*/
+ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
+ {
+ /* Slave mode selected */
+ if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ (void)FMPSMBUS_Slave_ISR(hfmpsmbus, tmpisrvalue);
+ }
+ /* Master mode selected */
+ else if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX)
+ {
+ (void)FMPSMBUS_Master_ISR(hfmpsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* FMPSMBUS in mode Receiver ----------------------------------------------------*/
+ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
+ {
+ /* Slave mode selected */
+ if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ (void)FMPSMBUS_Slave_ISR(hfmpsmbus, tmpisrvalue);
+ }
+ /* Master mode selected */
+ else if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX)
+ {
+ (void)FMPSMBUS_Master_ISR(hfmpsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* FMPSMBUS in mode Listener Only --------------------------------------------------*/
+ if (((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_ADDRI) != RESET) || (FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_STOPI) != RESET) || (FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_NACKI) != RESET)) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_ADDR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET)))
+ {
+ if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN)
+ {
+ (void)FMPSMBUS_Slave_ISR(hfmpsmbus, tmpisrvalue);
+ }
+ }
+}
+
+/**
+ * @brief Handle FMPSMBUS error interrupt request.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ FMPSMBUS_ITErrorHandler(hfmpsmbus);
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_MasterTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_MasterRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_SlaveTxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_SlaveRxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param TransferDirection Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FMPSMBUS error callback.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval None
+ */
+__weak void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfmpsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FMPSMBUS_ErrorCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the FMPSMBUS handle state.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @retval HAL state
+ */
+uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* Return FMPSMBUS handle state */
+ return hfmpsmbus->State;
+}
+
+/**
+* @brief Return the FMPSMBUS error code.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+* @retval FMPSMBUS Error Code
+*/
+uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ return hfmpsmbus->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
+ * @brief Data transfers Private functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPSMBUS_Master_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->ErrorCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_ErrorCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_STOPF) != RESET)
+ {
+ /* Check and treat errors if errors occurs during STOP process */
+ FMPSMBUS_ITErrorHandler(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX);
+
+ /* Clear STOP Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPSMBUS_RESET_CR2(hfmpsmbus);
+
+ /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+ /* Disable the selected FMPSMBUS peripheral */
+ __HAL_FMPSMBUS_DISABLE(hfmpsmbus);
+
+ hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* REenable the selected FMPSMBUS peripheral */
+ __HAL_FMPSMBUS_ENABLE(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->MasterTxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_MasterTxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX)
+ {
+ /* Store Last receive data if any */
+ if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hfmpsmbus->pBuffPtr++;
+
+ if ((hfmpsmbus->XferSize > 0U))
+ {
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ }
+
+ /* Disable Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX);
+
+ /* Clear STOP Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPSMBUS_RESET_CR2(hfmpsmbus);
+
+ hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->MasterRxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_MasterRxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hfmpsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR */
+ hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hfmpsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TCR) != RESET)
+ {
+ if ((hfmpsmbus->XferCount != 0U) && (hfmpsmbus->XferSize == 0U))
+ {
+ DevAddress = (uint16_t)(hfmpsmbus->Instance->CR2 & FMPI2C_CR2_SADD);
+
+ if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP);
+ hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hfmpsmbus->XferSize = hfmpsmbus->XferCount;
+ FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL)
+ {
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ }
+ }
+ else if ((hfmpsmbus->XferCount == 0U) && (hfmpsmbus->XferSize == 0U))
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (FMPSMBUS_GET_STOP_MODE(hfmpsmbus) != FMPSMBUS_AUTOEND_MODE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX);
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->MasterTxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_MasterTxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX)
+ {
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX);
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->MasterRxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_MasterRxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TC) != RESET)
+ {
+ if (hfmpsmbus->XferCount == 0U)
+ {
+ /* Specific use case for Quick command */
+ if (hfmpsmbus->pBuffPtr == NULL)
+ {
+ /* Generate a Stop command */
+ hfmpsmbus->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ /* Call TxCpltCallback() if no stop mode is set */
+ else if (FMPSMBUS_GET_STOP_MODE(hfmpsmbus) != FMPSMBUS_AUTOEND_MODE)
+ {
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when FMPSMBUS_AUTOEND_MODE enable */
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX);
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->MasterTxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_MasterTxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX)
+ {
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX);
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->MasterRxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_MasterRxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags)
+{
+ uint8_t TransferDirection;
+ uint16_t SlaveAddrCode;
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpsmbus);
+
+ if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_AF) != RESET)
+ {
+ /* Check that FMPSMBUS transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hfmpsmbus->XferCount == 0U)
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+ /* Clear NACK Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF);
+
+ /* Set HAL State to "Idle" State, mean to LISTEN state */
+ /* So reset Slave Busy state */
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX);
+ hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX | FMPSMBUS_IT_TX);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->ErrorCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_ErrorCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_ADDR) != RESET)
+ {
+ TransferDirection = (uint8_t)(FMPSMBUS_GET_DIR(hfmpsmbus));
+ SlaveAddrCode = (uint16_t)(FMPSMBUS_GET_ADDR_MATCH(hfmpsmbus));
+
+ /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+ /* Other ADDRInterrupt will be treat in next Listen usecase */
+ __HAL_FMPSMBUS_DISABLE_IT(hfmpsmbus, FMPSMBUS_IT_ADDRI);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->AddrCallback(hfmpsmbus, TransferDirection, SlaveAddrCode);
+#else
+ HAL_FMPSMBUS_AddrCallback(hfmpsmbus, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else if ((FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TCR) != RESET))
+ {
+ if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ /* Read data from RXDR */
+ *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hfmpsmbus->pBuffPtr++;
+
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+
+ if (hfmpsmbus->XferCount == 1U)
+ {
+ /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+ /* or only the last Byte of Transfer */
+ /* So reset the RELOAD bit mode */
+ hfmpsmbus->XferOptions &= ~FMPSMBUS_RELOAD_MODE;
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP);
+ }
+ else if (hfmpsmbus->XferCount == 0U)
+ {
+ /* Last Byte is received, disable Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX);
+
+ /* Remove HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_FMPSMBUS_STATE_LISTEN */
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->SlaveRxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_SlaveRxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Set Reload for next Bytes */
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP);
+
+ /* Ack last Byte Read */
+ hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+ }
+ }
+ else if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ if ((hfmpsmbus->XferCount != 0U) && (hfmpsmbus->XferSize == 0U))
+ {
+ if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP);
+ hfmpsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hfmpsmbus->XferSize = hfmpsmbus->XferCount;
+ FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL)
+ {
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Data have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if (hfmpsmbus->XferCount > 0U)
+ {
+ /* Write data to TXDR */
+ hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hfmpsmbus->pBuffPtr++;
+
+ hfmpsmbus->XferCount--;
+ hfmpsmbus->XferSize--;
+ }
+
+ if (hfmpsmbus->XferCount == 0U)
+ {
+ /* Last Byte is Transmitted */
+ /* Remove HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_FMPSMBUS_STATE_LISTEN */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX);
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->SlaveTxCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_SlaveTxCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Check if STOPF is set */
+ if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_STOPF) != RESET)
+ {
+ if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN)
+ {
+ /* Store Last receive data if any */
+ if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hfmpsmbus->pBuffPtr++;
+
+ if ((hfmpsmbus->XferSize > 0U))
+ {
+ hfmpsmbus->XferSize--;
+ hfmpsmbus->XferCount--;
+ }
+ }
+
+ /* Disable RX and TX Interrupts */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX | FMPSMBUS_IT_TX);
+
+ /* Disable ADDR Interrupt */
+ FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR);
+
+ /* Disable Address Acknowledge */
+ hfmpsmbus->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ FMPSMBUS_RESET_CR2(hfmpsmbus);
+
+ /* Clear STOP Flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ADDR);
+
+ hfmpsmbus->XferOptions = 0;
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->ListenCpltCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_ListenCpltCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param InterruptRequest Value of @ref FMPSMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static void FMPSMBUS_Enable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest)
+{
+ uint32_t tmpisr = 0UL;
+
+ if ((InterruptRequest & FMPSMBUS_IT_ALERT) == FMPSMBUS_IT_ALERT)
+ {
+ /* Enable ERR interrupt */
+ tmpisr |= FMPSMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & FMPSMBUS_IT_ADDR) == FMPSMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & FMPSMBUS_IT_TX) == FMPSMBUS_IT_TX)
+ {
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ tmpisr |= FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI;
+ }
+
+ if ((InterruptRequest & FMPSMBUS_IT_RX) == FMPSMBUS_IT_RX)
+ {
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ tmpisr |= FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI;
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of FMPSMBUS interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_FMPSMBUS_ENABLE_IT(hfmpsmbus, tmpisr);
+}
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param InterruptRequest Value of @ref FMPSMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static void FMPSMBUS_Disable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest)
+{
+ uint32_t tmpisr = 0UL;
+ uint32_t tmpstate = hfmpsmbus->State;
+
+ if ((tmpstate == HAL_FMPSMBUS_STATE_READY) && ((InterruptRequest & FMPSMBUS_IT_ALERT) == FMPSMBUS_IT_ALERT))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= FMPSMBUS_IT_ERRI;
+ }
+
+ if ((InterruptRequest & FMPSMBUS_IT_TX) == FMPSMBUS_IT_TX)
+ {
+ /* Disable TC, STOP, NACK and TXI interrupt */
+ tmpisr |= FMPSMBUS_IT_TCI | FMPSMBUS_IT_TXI;
+
+ if ((FMPSMBUS_GET_ALERT_ENABLED(hfmpsmbus) == 0UL)
+ && ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= FMPSMBUS_IT_ERRI;
+ }
+
+ if ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN)
+ {
+ /* Disable STOP and NACK interrupt */
+ tmpisr |= FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & FMPSMBUS_IT_RX) == FMPSMBUS_IT_RX)
+ {
+ /* Disable TC, STOP, NACK and RXI interrupt */
+ tmpisr |= FMPSMBUS_IT_TCI | FMPSMBUS_IT_RXI;
+
+ if ((FMPSMBUS_GET_ALERT_ENABLED(hfmpsmbus) == 0UL)
+ && ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= FMPSMBUS_IT_ERRI;
+ }
+
+ if ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN)
+ {
+ /* Disable STOP and NACK interrupt */
+ tmpisr |= FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI;
+ }
+ }
+
+ if ((InterruptRequest & FMPSMBUS_IT_ADDR) == FMPSMBUS_IT_ADDR)
+ {
+ /* Disable ADDR, STOP and NACK interrupt */
+ tmpisr |= FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI;
+
+ if (FMPSMBUS_GET_ALERT_ENABLED(hfmpsmbus) == 0UL)
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= FMPSMBUS_IT_ERRI;
+ }
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_FMPSMBUS_DISABLE_IT(hfmpsmbus, tmpisr);
+}
+
+/**
+ * @brief FMPSMBUS interrupts error handler.
+ * @param hfmpsmbus FMPSMBUS handle.
+ * @retval None
+ */
+static void FMPSMBUS_ITErrorHandler(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ uint32_t itflags = READ_REG(hfmpsmbus->Instance->ISR);
+ uint32_t itsources = READ_REG(hfmpsmbus->Instance->CR1);
+ uint32_t tmpstate;
+ uint32_t tmperror;
+
+ /* FMPSMBUS Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & FMPSMBUS_FLAG_BERR) == FMPSMBUS_FLAG_BERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI))
+ {
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_BERR);
+ }
+
+ /* FMPSMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & FMPSMBUS_FLAG_OVR) == FMPSMBUS_FLAG_OVR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI))
+ {
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_OVR);
+ }
+
+ /* FMPSMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if (((itflags & FMPSMBUS_FLAG_ARLO) == FMPSMBUS_FLAG_ARLO) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI))
+ {
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ARLO);
+ }
+
+ /* FMPSMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if (((itflags & FMPSMBUS_FLAG_TIMEOUT) == FMPSMBUS_FLAG_TIMEOUT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI))
+ {
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TIMEOUT);
+ }
+
+ /* FMPSMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if (((itflags & FMPSMBUS_FLAG_ALERT) == FMPSMBUS_FLAG_ALERT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI))
+ {
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ALERT);
+ }
+
+ /* FMPSMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if (((itflags & FMPSMBUS_FLAG_PECERR) == FMPSMBUS_FLAG_PECERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI))
+ {
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_PECERR);
+ }
+
+ /* Store current volatile hfmpsmbus->State, misra rule */
+ tmperror = hfmpsmbus->ErrorCode;
+
+ /* Call the Error Callback in case of Error detected */
+ if ((tmperror != HAL_FMPSMBUS_ERROR_NONE) && (tmperror != HAL_FMPSMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the HAL state in case of ALERT error */
+ if ((tmperror & HAL_FMPSMBUS_ERROR_ALERT) != HAL_FMPSMBUS_ERROR_ALERT)
+ {
+ /* Store current volatile hfmpsmbus->State, misra rule */
+ tmpstate = hfmpsmbus->State;
+
+ if (((tmpstate & HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX)
+ || ((tmpstate & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_FMPSMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_FMPSMBUS_STATE_LISTEN if set */
+ hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to inform upper layer */
+#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
+ hfmpsmbus->ErrorCallback(hfmpsmbus);
+#else
+ HAL_FMPSMBUS_ErrorCallback(hfmpsmbus);
+#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Handle FMPSMBUS Communication Timeout.
+ * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPSMBUS.
+ * @param Flag Specifies the FMPSMBUS flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ while ((FlagStatus)(__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, Flag)) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ hfmpsmbus->PreviousState = hfmpsmbus->State;
+ hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY;
+
+ /* Update FMPSMBUS error code */
+ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_HALTIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpsmbus);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle FMPSMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hfmpsmbus FMPSMBUS handle.
+ * @param DevAddress specifies the slave address to be programmed.
+ * @param Size specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the FMPSMBUS START condition generation.
+ * This parameter can be one or a combination of the following values:
+ * @arg @ref FMPSMBUS_RELOAD_MODE Enable Reload mode.
+ * @arg @ref FMPSMBUS_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref FMPSMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+ * @arg @ref FMPSMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+ * @param Request New state of the FMPSMBUS START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref FMPSMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref FMPSMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref FMPSMBUS_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref FMPSMBUS_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void FMPSMBUS_TransferConfig(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance));
+ assert_param(IS_FMPSMBUS_TRANSFER_MODE(Mode));
+ assert_param(IS_FMPSMBUS_TRANSFER_REQUEST(Request));
+
+ /* update CR2 register */
+ MODIFY_REG(hfmpsmbus->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+ * @brief Convert FMPSMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @param hfmpsmbus FMPSMBUS handle.
+ * @retval None
+ */
+static void FMPSMBUS_ConvertOtherXferOptions(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus)
+{
+ /* if user set XferOptions to FMPSMBUS_OTHER_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to FMPSMBUS_FIRST_FRAME */
+ if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_FRAME_NO_PEC)
+ {
+ hfmpsmbus->XferOptions = FMPSMBUS_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to FMPSMBUS_OTHER_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to FMPSMBUS_FIRST_FRAME | FMPSMBUS_SENDPEC_MODE */
+ else if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_FRAME_WITH_PEC)
+ {
+ hfmpsmbus->XferOptions = FMPSMBUS_FIRST_FRAME | FMPSMBUS_SENDPEC_MODE;
+ }
+ /* else if user set XferOptions to FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
+ else if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+ {
+ hfmpsmbus->XferOptions = FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+ }
+ /* else if user set XferOptions to FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
+ else if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+ {
+ hfmpsmbus->XferOptions = FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f4xx_hal_hcd.c b/Src/stm32f4xx_hal_hcd.c
index 6d90fdc..1e384d6 100644
--- a/Src/stm32f4xx_hal_hcd.c
+++ b/Src/stm32f4xx_hal_hcd.c
@@ -373,14 +373,13 @@
uint16_t length,
uint8_t do_ping)
{
- UNUSED(do_ping);
-
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+ hhcd->hc[ch_num].do_ping = do_ping;
}
else
{
@@ -534,20 +533,19 @@
/* Handle Host Disconnect Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
+ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
-
- /* Handle Host Port Disconnect Interrupt */
+ if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
+ {
+ /* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
- hhcd->DisconnectCallback(hhcd);
+ hhcd->DisconnectCallback(hhcd);
#else
- HAL_HCD_Disconnect_Callback(hhcd);
+ HAL_HCD_Disconnect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
- (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+ }
}
/* Handle Host Port Interrupts */
@@ -1009,6 +1007,7 @@
__HAL_HCD_ENABLE(hhcd);
(void)USB_DriveVbus(hhcd->Instance, 1U);
__HAL_UNLOCK(hhcd);
+
return HAL_OK;
}
@@ -1023,6 +1022,7 @@
__HAL_LOCK(hhcd);
(void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd);
+
return HAL_OK;
}
@@ -1170,6 +1170,13 @@
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
}
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
+ {
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
+ hhcd->hc[ch_num].state = HC_BBLERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
@@ -1231,6 +1238,17 @@
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
+ else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
+ {
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+ }
else
{
/* ... */
@@ -1279,6 +1297,11 @@
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
+ else if (hhcd->hc[ch_num].state == HC_BBLERR)
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ }
else
{
/* ... */
@@ -1555,8 +1578,6 @@
{
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
-
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->ConnectCallback(hhcd);
#else
@@ -1593,10 +1614,8 @@
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortEnabledCallback(hhcd);
- hhcd->ConnectCallback(hhcd);
#else
HAL_HCD_PortEnabled_Callback(hhcd);
- HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
@@ -1607,12 +1626,6 @@
#else
HAL_HCD_PortDisabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
}
}
diff --git a/Src/stm32f4xx_hal_i2s.c b/Src/stm32f4xx_hal_i2s.c
index 20a0e95..35e29f8 100644
--- a/Src/stm32f4xx_hal_i2s.c
+++ b/Src/stm32f4xx_hal_i2s.c
@@ -88,6 +88,10 @@
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+ In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
+ HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
+ In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
+ inside DR register and avoid using DeInit/Init process for the next transfer.
*** I2S HAL driver macros list ***
===================================
@@ -100,6 +104,7 @@
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+ (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
@@ -194,6 +199,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -1454,6 +1460,9 @@
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ uint32_t tickstart;
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
@@ -1461,46 +1470,180 @@
and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
*/
- /* Disable the I2S Tx/Rx DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Abort the I2S DMA tx Stream/Channel */
- if (hi2s->hdmatx != NULL)
+ if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
{
- /* Disable the I2S DMA tx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
{
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- errorcode = HAL_ERROR;
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
- }
- /* Abort the I2S DMA rx Stream/Channel */
- if (hi2s->hdmarx != NULL)
- {
- /* Disable the I2S DMA rx Stream/Channel */
- if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
{
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
- errorcode = HAL_ERROR;
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
}
- }
+
+ /* Wait until BSY flag is Reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* Clear UDR flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Disable the I2S Tx DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- /* In case of Full-Duplex, disable the I2SxEXT Tx/Rx DMA requests*/
- if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
- {
- /* Disable the I2SxEXT DMA requests */
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
- /* Disable I2Sext peripheral */
- __HAL_I2SEXT_DISABLE(hi2s);
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Disable I2Sext peripheral */
+ __HAL_I2SEXT_DISABLE(hi2s);
+
+ /* Clear OVR flag */
+ __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
+
+ /* Disable the I2SxEXT DMA request */
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
+
+ if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Read DR to Flush RX Data */
+ READ_REG(I2SxEXT(hi2s->Instance)->DR);
+ }
+ }
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
}
+
+ else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
+ {
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
+ {
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until TXE flag is set */
+ while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_TXE) != SET)
+ {
+ if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Wait until BSY flag is Reset */
+ while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_BSY) != RESET)
+ {
+ if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Disable I2Sext peripheral */
+ __HAL_I2SEXT_DISABLE(hi2s);
+
+ /* Clear UDR flag */
+ __HAL_I2SEXT_CLEAR_UDRFLAG(hi2s);
+
+ /* Disable the I2SxEXT DMA request */
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
+ }
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ /* Clear OVR flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Disable the I2S Rx DMA request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Read DR to Flush RX Data */
+ READ_REG((hi2s->Instance)->DR);
+ }
+ }
hi2s->State = HAL_I2S_STATE_READY;
diff --git a/Src/stm32f4xx_hal_i2s_ex.c b/Src/stm32f4xx_hal_i2s_ex.c
index 11cfb82..791c219 100644
--- a/Src/stm32f4xx_hal_i2s_ex.c
+++ b/Src/stm32f4xx_hal_i2s_ex.c
@@ -52,6 +52,10 @@
add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) __HAL_I2SEXT_FLUSH_RX_DR: In Full-Duplex Slave mode, if HAL_I2S_DMAStop is used to stop the
+ communication, an error HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
+ In this case __HAL_I2SEXT_FLUSH_RX_DR macro must be used to flush the remaining data
+ inside I2Sx and I2Sx_ext DR registers and avoid using DeInit/Init process for the next transfer.
@endverbatim
Additional Figure: The Extended block uses the same clock sources as its master.
diff --git a/Src/stm32f4xx_hal_pcd.c b/Src/stm32f4xx_hal_pcd.c
index cc5081f..cda95be 100644
--- a/Src/stm32f4xx_hal_pcd.c
+++ b/Src/stm32f4xx_hal_pcd.c
@@ -1058,6 +1058,38 @@
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
+ /* Handle RxQLevel Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ {
+ USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ temp = USBx->GRXSTSP;
+
+ ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+
+ if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
+ {
+ if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+ {
+ (void)USB_ReadPacket(USBx, ep->xfer_buff,
+ (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ }
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+ {
+ (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ else
+ {
+ /* ... */
+ }
+ USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
@@ -1079,9 +1111,9 @@
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
@@ -1092,10 +1124,6 @@
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
- if (hpcd->Init.dma_enable == 1U)
- {
- (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
- }
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
@@ -1133,16 +1161,7 @@
if (hpcd->Init.dma_enable == 1U)
{
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
- }
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
-#else
- HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- if (hpcd->Init.dma_enable == 1U)
- {
/* this is ZLP, so prepare EP0 for next setup */
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
{
@@ -1150,6 +1169,12 @@
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
@@ -1255,8 +1280,10 @@
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+ USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+ USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
@@ -1313,38 +1340,6 @@
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
- /* Handle RxQLevel Interrupt */
- if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
- {
- USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
- temp = USBx->GRXSTSP;
-
- ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-
- if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
- {
- if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
- {
- (void)USB_ReadPacket(USBx, ep->xfer_buff,
- (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
-
- ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- }
- }
- else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
- {
- (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- }
- else
- {
- /* ... */
- }
- USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
-
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
@@ -2071,16 +2066,6 @@
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
-
- /* Inform the upper layer that a setup packet is available */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SetupStageCallback(hpcd);
-#else
- HAL_PCD_SetupStageCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
{
@@ -2103,17 +2088,16 @@
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
-#else
- HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
@@ -2146,6 +2130,12 @@
}
else
{
+ if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
+ }
+
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
@@ -2171,22 +2161,10 @@
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
- if (hpcd->Init.dma_enable == 1U)
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
- /* StupPktRcvd = 1 pending setup packet int */
- if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
- ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
- }
- }
- else
- {
- if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
- ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
- }
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */
diff --git a/Src/stm32f4xx_hal_qspi.c b/Src/stm32f4xx_hal_qspi.c
index b143e35..02ab62a 100644
--- a/Src/stm32f4xx_hal_qspi.c
+++ b/Src/stm32f4xx_hal_qspi.c
@@ -3,7 +3,7 @@
* @file stm32f4xx_hal_qspi.c
* @author MCD Application Team
* @brief QSPI HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
* + Initialization and de-initialization functions
* + Indirect functional mode management
@@ -24,14 +24,14 @@
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
- (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure QuadSPI global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
- with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
- link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
+ (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the flash size, the clock prescaler, the fifo threshold, the
clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
@@ -39,47 +39,47 @@
*** Indirect functional mode ***
================================
[..]
- (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
+ (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
functions :
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used and if present the number of bytes.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(#) If no data is required for the command, it is sent directly to the memory :
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
- (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
+ (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
HAL_QSPI_Transmit_IT() after the command configuration :
(++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+ (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
- (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
+ (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
HAL_QSPI_Receive_IT() after the command configuration :
(++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+ (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+ (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
[..]
- (#) Configure the command sequence and the auto-polling functional mode using the
+ (#) Configure the command sequence and the auto-polling functional mode using the
HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and if present the size and the address value.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
@@ -92,31 +92,31 @@
*** Memory-mapped functional mode ***
=====================================
[..]
- (#) Configure the command sequence and the memory-mapped functional mode using the
+ (#) Configure the command sequence and the memory-mapped functional mode using the
HAL_QSPI_MemoryMapped() functions :
(++) Instruction phase : the mode used and if present the instruction opcode.
(++) Address phase : the mode used and the size.
- (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+ (++) Alternate-bytes phase : the mode used and if present the size and the alternate
bytes values.
(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(++) Data phase : the mode used.
- (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+ (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
if activated.
(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(++) The timeout activation and the timeout period.
- (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
+ (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
*** Errors management and abort functionality ***
- ==================================================
+ =================================================
[..]
(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
+ (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
flushes the fifo :
- (++) In polling mode, the output of the function is done when the transfer
+ (++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
- (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
- the transfer complete bi is set.
+ (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
+ the transfer complete bit is set.
*** Control functions ***
=========================
@@ -125,6 +125,7 @@
(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+ (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
*** Callback registration ***
=============================================
@@ -195,13 +196,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
+ * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -209,6 +210,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -219,12 +222,10 @@
*/
#ifdef HAL_QSPI_MODULE_ENABLED
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-
/* Private typedef -----------------------------------------------------------*/
+
/* Private define ------------------------------------------------------------*/
-/** @addtogroup QSPI_Private_Constants
+/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
@@ -234,9 +235,9 @@
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
-/** @addtogroup QSPI_Private_Macros QSPI Private Macros
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
@@ -246,34 +247,29 @@
/**
* @}
*/
-
+
/* Private variables ---------------------------------------------------------*/
+
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup QSPI_Private_Functions QSPI Private Functions
- * @{
- */
static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
* @{
*/
-/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@@ -281,22 +277,22 @@
This subsection provides a set of functions allowing to :
(+) Initialize the QuadSPI.
(+) De-initialize the QuadSPI.
-
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the QSPI mode according to the specified parameters
- * in the QSPI_InitTypeDef and creates the associated handle.
- * @param hqspi qspi handle
+ * @brief Initialize the QSPI mode according to the specified parameters
+ * in the QSPI_InitTypeDef and initialize the associated handle.
+ * @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the QSPI handle allocation */
if(hqspi == NULL)
{
@@ -317,9 +313,9 @@
{
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
-
+
if(hqspi->State == HAL_QSPI_STATE_RESET)
- {
+ {
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
@@ -349,35 +345,38 @@
#endif
/* Configure the default timeout for the QSPI memory access */
- HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+ HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
}
-
+
/* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U));
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+ ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
if(status == HAL_OK)
{
-
/* Configure QSPI Clock Prescaler and Sample Shift */
- MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
-
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
+ ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
+ hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
+
/* Configure QSPI Flash Size, CS High Time and Clock Mode */
- MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
- ((hqspi->Init.FlashSize << 16U) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
-
+ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+ ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
+ hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
/* Enable the QSPI peripheral */
__HAL_QSPI_ENABLE(hqspi);
-
+
/* Set QSPI error code to none */
- hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
}
-
+
/* Release Lock */
__HAL_UNLOCK(hqspi);
@@ -386,8 +385,8 @@
}
/**
- * @brief DeInitializes the QSPI peripheral
- * @param hqspi qspi handle
+ * @brief De-Initialize the QSPI peripheral.
+ * @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -427,47 +426,47 @@
}
/**
- * @brief QSPI MSP Init
- * @param hqspi QSPI handle
+ * @brief Initialize the QSPI MSP.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_MspInit can be implemented in the user file
- */
+ */
}
/**
- * @brief QSPI MSP DeInit
- * @param hqspi QSPI handle
+ * @brief DeInitialize the QSPI MSP.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_MspDeInit can be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
- * @brief QSPI Transmit/Receive functions
+/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
+ * @brief QSPI Transmit/Receive functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
- [..]
+ [..]
This subsection provides a set of functions allowing to :
(+) Handle the interrupts.
(+) Handle the command sequence.
@@ -481,9 +480,9 @@
*/
/**
- * @brief This function handles QSPI interrupt request.
- * @param hqspi QSPI handle
- * @retval None.
+ * @brief Handle QSPI interrupt request.
+ * @param hqspi : QSPI handle
+ * @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
{
@@ -492,19 +491,20 @@
uint32_t itsource = READ_REG(hqspi->Instance->CR);
/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
- if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
+ if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
{
data_reg = &hqspi->Instance->DR;
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
/* Transmission process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
{
if (hqspi->TxXferCount > 0U)
{
- /* Fill the FIFO until it is full */
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ /* Fill the FIFO until the threshold is reached */
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+ hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
else
@@ -519,12 +519,13 @@
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
/* Receiving Process */
- while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
+ while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
{
if (hqspi->RxXferCount > 0U)
{
- /* Read the FIFO until it is empty */
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ /* Read the FIFO until the threshold is reached */
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
else
@@ -536,7 +537,11 @@
}
}
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
/* FIFO Threshold callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->FifoThresholdCallback(hqspi);
@@ -546,29 +551,29 @@
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
- else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
+ else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
-
+
/* Transfer complete callback */
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hqspi->hdma);
}
/* Clear Busy bit */
HAL_QSPI_Abort_IT(hqspi);
-
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -581,11 +586,11 @@
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hqspi->hdma);
}
@@ -597,7 +602,8 @@
if (hqspi->RxXferCount > 0U)
{
/* Read the last data received in the FIFO until it is empty */
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
else
@@ -607,9 +613,10 @@
}
}
}
+
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
HAL_QSPI_Abort_IT(hqspi);
-
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -634,6 +641,9 @@
}
else if(hqspi->State == HAL_QSPI_STATE_ABORT)
{
+ /* Reset functional mode configuration to indirect write mode by default */
+ CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -648,7 +658,7 @@
HAL_QSPI_AbortCpltCallback(hqspi);
#endif
}
- else
+ else
{
/* Abort due to an error (eg : DMA error) */
@@ -660,14 +670,18 @@
#endif
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/* QSPI Status Match interrupt occurred ------------------------------------*/
- else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
+ else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
-
+
/* Check if the automatic poll mode stop is activated */
if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
{
@@ -687,22 +701,22 @@
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
- else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
+ else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
-
+
/* Disable all the QSPI Interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
/* Set error code */
hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
-
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Disable the DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
@@ -725,7 +739,7 @@
{
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Error callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->ErrorCallback(hqspi);
@@ -736,7 +750,7 @@
}
/* QSPI Timeout interrupt occurred -----------------------------------------*/
- else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
+ else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
@@ -748,21 +762,26 @@
HAL_QSPI_TimeOutCallback(hqspi);
#endif
}
+
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
- * @brief Sets the command configuration.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information
- * @param Timeout Time out duration
+ * @brief Set the command configuration.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param Timeout : Timeout duration
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
@@ -788,52 +807,51 @@
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
+
if (status == HAL_OK)
{
/* Call the configuration function */
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
+
if (cmd->DataMode == QSPI_DATA_NONE)
{
- /* When there is no data phase, the transfer start as soon as the configuration is done
+ /* When there is no data phase, the transfer start as soon as the configuration is done
so wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
-
}
else
{
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
}
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -842,17 +860,17 @@
}
/**
- * @brief Sets the command configuration in interrupt mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information
+ * @brief Set the command configuration in interrupt mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
{
- __IO uint32_t count = 0U;
- HAL_StatusTypeDef status = HAL_OK;
-
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
@@ -878,30 +896,20 @@
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_BUSY;
-
+ hqspi->State = HAL_QSPI_STATE_BUSY;
+
/* Wait till BUSY flag reset */
- count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
- do
- {
- if (count-- == 0U)
- {
- hqspi->State = HAL_QSPI_STATE_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
- status = HAL_TIMEOUT;
- }
- }
- while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
-
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
if (status == HAL_OK)
{
if (cmd->DataMode == QSPI_DATA_NONE)
@@ -909,13 +917,13 @@
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
}
-
+
/* Call the configuration function */
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
+
if (cmd->DataMode == QSPI_DATA_NONE)
{
- /* When there is no data phase, the transfer start as soon as the configuration is done
+ /* When there is no data phase, the transfer start as soon as the configuration is done
so activate TC and TE interrupts */
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -926,7 +934,7 @@
else
{
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -940,27 +948,27 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
-
+
/* Return function status */
return status;
}
/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
- * @param Timeout Time out duration
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
+ * @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart = HAL_GetTick();
__IO uint32_t *data_reg = &hqspi->Instance->DR;
@@ -975,12 +983,12 @@
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
-
+
/* Configure counters and size of the handle */
hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pTxBuffPtr = pData;
-
+
/* Configure QSPI: CCR register with functional as indirect write */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
@@ -990,14 +998,15 @@
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
if (status != HAL_OK)
- {
+ {
break;
}
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+ hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
-
+
if (status == HAL_OK)
{
/* Wait until TC flag is set to go back in idle state */
@@ -1007,14 +1016,14 @@
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Clear Busy bit */
status = HAL_QSPI_Abort(hqspi);
}
}
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
else
{
@@ -1035,10 +1044,10 @@
/**
- * @brief Receive an amount of data in blocking mode
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
- * @param Timeout Time out duration
+ * @brief Receive an amount of data in blocking mode.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
+ * @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1051,15 +1060,16 @@
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
if(pData != NULL )
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
+
/* Configure counters and size of the handle */
hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
@@ -1070,21 +1080,22 @@
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
-
+
while(hqspi->RxXferCount > 0U)
{
/* Wait until FT or TC flag is set to read received data */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
if (status != HAL_OK)
- {
+ {
break;
}
- *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
-
+
if (status == HAL_OK)
{
/* Wait until TC flag is set to go back in idle state */
@@ -1094,14 +1105,14 @@
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
- /* Workaround - Extra data written in the FIFO at the end of a read transfer */
- status = HAL_QSPI_Abort(hqspi);
+
+ /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+ status = HAL_QSPI_Abort(hqspi);
}
}
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_READY;
+ hqspi->State = HAL_QSPI_STATE_READY;
}
else
{
@@ -1113,7 +1124,7 @@
{
status = HAL_BUSY;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1121,22 +1132,23 @@
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
+ * @brief Send an amount of data in non-blocking mode with interrupt.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
if(pData != NULL )
{
/* Update state */
@@ -1146,19 +1158,18 @@
hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pTxBuffPtr = pData;
-
- /* Configure QSPI: CCR register with functional as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
-
+
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+ /* Configure QSPI: CCR register with functional as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
-
}
else
{
@@ -1181,9 +1192,9 @@
}
/**
- * @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
+ * @brief Receive an amount of data in non-blocking mode with interrupt.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1191,33 +1202,33 @@
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
-
+
/* Process locked */
__HAL_LOCK(hqspi);
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
if(pData != NULL )
{
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
+
/* Configure counters and size of the handle */
hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
hqspi->pRxBuffPtr = pData;
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
/* Configure QSPI: CCR register with functional as indirect read */
MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Start the transfer by re-writing the address in AR register */
WRITE_REG(hqspi->Instance->AR, addr_reg);
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
-
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1235,7 +1246,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1245,20 +1256,19 @@
}
/**
- * @brief Sends an amount of data in non blocking mode with DMA.
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer
+ * @brief Send an amount of data in non-blocking mode with DMA.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
- * @note If DMA peripheral access is configured as halfword, the number
+ * @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
- * @note If DMA peripheral access is configured as word, the number
+ * @note If DMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
@@ -1266,10 +1276,10 @@
if(hqspi->State == HAL_QSPI_STATE_READY)
{
- /* Clear the error code */
+ /* Clear the error code */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
- if(pData != NULL )
+ if(pData != NULL )
{
/* Configure counters of the handle */
if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
@@ -1280,7 +1290,7 @@
{
if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on halfword
+ /* The number of data or the fifo threshold is not aligned on halfword
=> no transfer possible with DMA peripheral access configured as halfword */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
@@ -1290,14 +1300,14 @@
}
else
{
- hqspi->TxXferCount = (data_size >> 1);
+ hqspi->TxXferCount = (data_size >> 1U);
}
}
else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
{
if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on word
+ /* The number of data or the fifo threshold is not aligned on word
=> no transfer possible with DMA peripheral access configured as word */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
@@ -1310,79 +1320,91 @@
hqspi->TxXferCount = (data_size >> 2U);
}
}
+ else
+ {
+ /* Nothing to do */
+ }
if (status == HAL_OK)
{
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
- /* Configure size and pointer of the handle */
- hqspi->TxXferSize = hqspi->TxXferCount;
- hqspi->pTxBuffPtr = pData;
+ /* Configure size and pointer of the handle */
+ hqspi->TxXferSize = hqspi->TxXferCount;
+ hqspi->pTxBuffPtr = pData;
- /* Configure QSPI: CCR register with functional mode as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+ /* Configure QSPI: CCR register with functional mode as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
- /* Set the QSPI DMA transfer complete callback */
- hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
+ /* Set the QSPI DMA transfer complete callback */
+ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
- /* Set the QSPI DMA Half transfer complete callback */
- hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
+ /* Set the QSPI DMA Half transfer complete callback */
+ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
- /* Set the DMA error callback */
- hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+ /* Set the DMA error callback */
+ hqspi->hdma->XferErrorCallback = QSPI_DMAError;
- /* Clear the DMA abort callback */
- hqspi->hdma->XferAbortCallback = NULL;
+ /* Clear the DMA abort callback */
+ hqspi->hdma->XferAbortCallback = NULL;
#if defined (QSPI1_V2_1L)
- /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
- AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
- Change the following configuration of DMA peripheral
- - Enable peripheral increment
- - Disable memory increment
- - Set DMA direction as peripheral to memory mode */
+ /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
+ AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
+ Change the following configuration of DMA peripheral
+ - Enable peripheral increment
+ - Disable memory increment
+ - Set DMA direction as peripheral to memory mode */
/* Enable peripheral increment mode of the DMA */
hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
/* Disable memory increment mode of the DMA */
hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
-
+
/* Update peripheral/memory increment mode bits */
MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
/* Configure the direction of the DMA */
hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
-#else
- /* Configure the direction of the DMA */
- hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+#else
+ /* Configure the direction of the DMA */
+ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
#endif /* QSPI1_V2_1L */
- /* Update direction mode bit */
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+ /* Update direction mode bit */
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
- /* Enable the QSPI transmit DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
+ /* Enable the QSPI transmit DMA Channel */
+ if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
+ }
}
else
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
-
status = HAL_ERROR;
/* Process unlocked */
@@ -1391,7 +1413,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1401,20 +1423,19 @@
}
/**
- * @brief Receives an amount of data in non blocking mode with DMA.
- * @param hqspi QSPI handle
- * @param pData pointer to data buffer.
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
- * @note If DMA peripheral access is configured as halfword, the number
+ * @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
- * @note If DMA peripheral access is configured as word, the number
+ * @note If DMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
@@ -1423,9 +1444,10 @@
if(hqspi->State == HAL_QSPI_STATE_READY)
{
+ /* Clear the error code */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
- if(pData != NULL )
+ if(pData != NULL )
{
/* Configure counters of the handle */
if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
@@ -1436,8 +1458,8 @@
{
if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on halfword
- => no transfer possible with DMA peripheral access configured as halfword */
+ /* The number of data or the fifo threshold is not aligned on halfword
+ => no transfer possible with DMA peripheral access configured as halfword */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
@@ -1453,8 +1475,8 @@
{
if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
{
- /* The number of data or the fifo threshold is not aligned on word
- => no transfer possible with DMA peripheral access configured as word */
+ /* The number of data or the fifo threshold is not aligned on word
+ => no transfer possible with DMA peripheral access configured as word */
hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
@@ -1466,6 +1488,10 @@
hqspi->RxXferCount = (data_size >> 2U);
}
}
+ else
+ {
+ /* Nothing to do */
+ }
if (status == HAL_OK)
{
@@ -1513,56 +1539,43 @@
/* Configure the direction of the DMA */
hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
- /* 4 Extra words (32-bits) are needed for read operation to guarantee
+ /* 4 Extra words (32-bits) are needed for read operation to guarantee
the last data is transferred from DMA FIFO to RAM memory */
WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
-
- /* Update direction mode bit */
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
-
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
-
- /* Enable the DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
-
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
#else
/* Configure the direction of the DMA */
hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
-
+#endif
+ /* Update direction mode bit */
MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
/* Enable the DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
+ if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
+ {
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+ /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
-
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
-
- /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-#endif /* QSPI1_V2_1L */
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
}
}
else
@@ -1576,7 +1589,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -1586,90 +1599,89 @@
}
/**
- * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information.
- * @param cfg structure that contains the polling configuration information.
- * @param Timeout Time out duration
+ * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
+ * @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
{
assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
}
-
+
assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != QSPI_ADDRESS_NONE)
{
assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
}
-
+
assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
{
assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
}
-
+
assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
assert_param(IS_QSPI_INTERVAL(cfg->Interval));
assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
-
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
-
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
-
+
if (status == HAL_OK)
{
/* Configure QSPI: PSMAR register with the status match value */
WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
+
/* Configure QSPI: PSMKR register with the status mask value */
WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
+
/* Configure QSPI: PIR register with the interval value */
WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
- /* Configure QSPI: CR register with Match mode and Automatic stop enabled
+
+ /* Configure QSPI: CR register with Match mode and Automatic stop enabled
(otherwise there will be an infinite loop in blocking mode) */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
(cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
-
+
/* Call the configuration function */
cmd->NbData = cfg->StatusBytesSize;
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
-
+
/* Wait until SM flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@@ -1677,107 +1689,98 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Return function status */
- return status;
+ return status;
}
/**
- * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information.
- * @param cfg structure that contains the polling configuration information.
+ * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
{
- __IO uint32_t count = 0U;
- HAL_StatusTypeDef status = HAL_OK;
-
+ HAL_StatusTypeDef status;
+ uint32_t tickstart = HAL_GetTick();
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
{
assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
}
-
+
assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != QSPI_ADDRESS_NONE)
{
assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
}
-
+
assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
{
assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
}
-
+
assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
-
+
assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
-
+
assert_param(IS_QSPI_INTERVAL(cfg->Interval));
assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
/* Wait till BUSY flag reset */
- count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
- do
- {
- if (count-- == 0U)
- {
- hqspi->State = HAL_QSPI_STATE_ERROR;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
- status = HAL_TIMEOUT;
- }
- }
- while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
-
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
if (status == HAL_OK)
{
/* Configure QSPI: PSMAR register with the status match value */
WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
-
+
/* Configure QSPI: PSMKR register with the status mask value */
WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
-
+
/* Configure QSPI: PIR register with the interval value */
WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
-
+
/* Configure QSPI: CR register with Match mode and Automatic stop mode */
- MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
(cfg->MatchMode | cfg->AutomaticStop));
-
+
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
-
+
/* Call the configuration function */
cmd->NbData = cfg->StatusBytesSize;
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Enable the QSPI Transfer Error and status match Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
@@ -1790,29 +1793,29 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hqspi);
}
-
+
/* Return function status */
- return status;
+ return status;
}
/**
- * @brief Configure the Memory Mapped mode.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information.
- * @param cfg structure that contains the memory mapped configuration information.
+ * @brief Configure the Memory Mapped mode.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
{
- HAL_StatusTypeDef status = HAL_ERROR;
+ HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check the parameters */
assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
@@ -1840,20 +1843,20 @@
assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
-
+
/* Process locked */
__HAL_LOCK(hqspi);
-
+
if(hqspi->State == HAL_QSPI_STATE_READY)
{
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
-
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
-
+
/* Wait till BUSY flag reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
-
+
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
@@ -1862,51 +1865,51 @@
if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
-
+
/* Configure QSPI: LPTR register with the low-power timeout value */
WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
-
+
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
/* Enable the QSPI TimeOut Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
}
-
+
/* Call the configuration function */
QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
}
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Return function status */
- return status;
+ return status;
}
/**
- * @brief Transfer Error callbacks
- * @param hqspi QSPI handle
+ * @brief Transfer Error callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Abort completed callback.
- * @param hqspi QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1921,120 +1924,120 @@
/**
* @brief Command completed callback.
- * @param hqspi QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_CmdCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Rx Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Rx Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_RxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Tx Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Tx Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_TxCpltCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Rx Half Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Rx Half Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Tx Half Transfer completed callbacks.
- * @param hqspi QSPI handle
+ * @brief Tx Half Transfer completed callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief FIFO Threshold callbacks
- * @param hqspi QSPI handle
+ * @brief FIFO Threshold callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
*/
}
/**
- * @brief Status Match callbacks
- * @param hqspi QSPI handle
+ * @brief Status Match callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_StatusMatchCallback could be implemented in the user file
*/
}
/**
- * @brief Timeout callbacks
- * @param hqspi QSPI handle
+ * @brief Timeout callback.
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_QSPI_TimeOutCallback could be implemented in the user file
*/
}
@@ -2264,26 +2267,27 @@
* @}
*/
-/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
- * @brief QSPI control and State functions
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
+ * @brief QSPI control and State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control and State functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to :
- (+) Check in run-time the state of the driver.
+ (+) Check in run-time the state of the driver.
(+) Check the error code set during last operation.
(+) Abort any operation.
+
@endverbatim
* @{
*/
/**
* @brief Return the QSPI handle state.
- * @param hqspi QSPI handle
+ * @param hqspi : QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -2293,8 +2297,8 @@
}
/**
-* @brief Return the QSPI error code
-* @param hqspi QSPI handle
+* @brief Return the QSPI error code.
+* @param hqspi : QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -2303,50 +2307,53 @@
}
/**
-* @brief Abort the current transmission
-* @param hqspi QSPI handle
+* @brief Abort the current transmission.
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart = HAL_GetTick();
-
+
/* Check if the state is in one of the busy states */
- if ((hqspi->State & 0x2U) != 0U)
+ if (((uint32_t)hqspi->State & 0x2U) != 0U)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Abort DMA channel */
status = HAL_DMA_Abort(hqspi->hdma);
if(status != HAL_OK)
{
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
}
- }
-
+ }
+
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-
+
/* Wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Wait until BUSY flag is reset */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
}
-
+
if (status == HAL_OK)
{
+ /* Reset functional mode configuration to indirect write mode by default */
+ CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@@ -2357,30 +2364,30 @@
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi QSPI handle
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check if the state is in one of the busy states */
- if ((hqspi->State & 0x2U) != 0U)
+ if (((uint32_t)hqspi->State & 0x2U) != 0U)
{
/* Process unlocked */
__HAL_UNLOCK(hqspi);
-
+
/* Update QSPI state */
- hqspi->State = HAL_QSPI_STATE_ABORT;
-
+ hqspi->State = HAL_QSPI_STATE_ABORT;
+
/* Disable all interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
-
- if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
+
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
+
/* Abort DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
@@ -2400,21 +2407,20 @@
{
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Enable the QSPI Transfer Complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
+
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
}
}
-
return status;
}
-/** @brief Set QSPI timeout
- * @param hqspi QSPI handle.
- * @param Timeout Timeout for the QSPI memory access.
+/** @brief Set QSPI timeout.
+ * @param hqspi : QSPI handle.
+ * @param Timeout : Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2423,8 +2429,8 @@
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi QSPI handle.
- * @param Threshold Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi : QSPI handle.
+ * @param Threshold : Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2438,16 +2444,16 @@
{
/* Synchronize init structure with new FIFO threshold value */
hqspi->Init.FifoThreshold = Threshold;
-
+
/* Configure QSPI FIFO Threshold */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
}
else
{
- status = HAL_BUSY;
+ status = HAL_BUSY;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hqspi);
@@ -2456,7 +2462,7 @@
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi QSPI handle.
+ * @param hqspi : QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@@ -2464,48 +2470,91 @@
return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
}
+/** @brief Set FlashID.
+ * @param hqspi : QSPI handle.
+ * @param FlashID : Index of the flash memory to be accessed.
+ * This parameter can be a value of @ref QSPI_Flash_Select.
+ * @note The FlashID is ignored when dual flash mode is enabled.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameter */
+ assert_param(IS_QSPI_FLASH_ID(FlashID));
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ /* Synchronize init structure with new FlashID value */
+ hqspi->Init.FlashID = FlashID;
+
+ /* Configure QSPI FlashID */
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
+ }
+ else
+ {
+ status = HAL_BUSY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+
+ /* Return function status */
+ return status;
+}
+
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-
/**
- * @brief DMA QSPI receive process complete callback.
- * @param hdma DMA handle
+ * @}
+ */
+
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA QSPI receive process complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
hqspi->RxXferCount = 0U;
-
+
/* Enable the QSPI transfer complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
}
/**
- * @brief DMA QSPI transmit process complete callback.
- * @param hdma DMA handle
+ * @brief DMA QSPI transmit process complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
hqspi->TxXferCount = 0U;
-
+
/* Enable the QSPI transfer complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
}
/**
- * @brief DMA QSPI receive process half complete callback
- * @param hdma DMA handle
+ * @brief DMA QSPI receive process half complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->RxHalfCpltCallback(hqspi);
@@ -2515,13 +2564,13 @@
}
/**
- * @brief DMA QSPI transmit process half complete callback
- * @param hdma DMA handle
+ * @brief DMA QSPI transmit process half complete callback.
+ * @param hdma : DMA handle
* @retval None
*/
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->TxHalfCpltCallback(hqspi);
@@ -2532,36 +2581,37 @@
/**
* @brief DMA QSPI communication error callback.
- * @param hdma DMA handle
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
+
/* if DMA error is FIFO error ignore it */
if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
- hqspi->RxXferCount = 0U;
- hqspi->TxXferCount = 0U;
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
-
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
- CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
-
- /* Abort the QSPI */
- HAL_QSPI_Abort_IT(hqspi);
+ hqspi->RxXferCount = 0U;
+ hqspi->TxXferCount = 0U;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+ /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+ /* Abort the QSPI */
+ (void)HAL_QSPI_Abort_IT(hqspi);
+
}
}
/**
* @brief DMA QSPI abort complete callback.
- * @param hdma DMA handle
+ * @param hdma : DMA handle
* @retval None
*/
-static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@@ -2571,10 +2621,10 @@
/* DMA Abort called by QSPI abort */
/* Clear interrupt */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
+
/* Enable the QSPI Transfer Complete Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
+
/* Configure QSPI: CR register with Abort request */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
}
@@ -2583,34 +2633,39 @@
/* DMA Abort called due to a transfer error interrupt */
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
-
+
/* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
HAL_QSPI_ErrorCallback(hqspi);
+#endif
}
}
+
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi QSPI handle
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the time out
- * @param tickstart tick start value
+ * @param hqspi : QSPI handle
+ * @param Flag : Flag checked
+ * @param State : Value of the flag expected
+ * @param Tickstart : Tick start value
+ * @param Timeout : Duration of the timeout
* @retval HAL status
*/
-static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
- FlagStatus State, uint32_t tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+ FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
- /* Wait until flag is in expected state */
- while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+ /* Wait until flag is in expected state */
+ while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hqspi->State = HAL_QSPI_STATE_ERROR;
hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
-
+
return HAL_ERROR;
}
}
@@ -2620,9 +2675,9 @@
/**
* @brief Configure the communication registers.
- * @param hqspi QSPI handle
- * @param cmd structure that contains the command configuration information
- * @param FunctionalMode functional mode to configured
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param FunctionalMode : functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@@ -2639,7 +2694,7 @@
/* Configure QSPI: DLR register with the number of data to read or write */
WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
}
-
+
if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
{
if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
@@ -2652,9 +2707,10 @@
/*---- Command with instruction, address and alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
- cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+ cmd->Instruction | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
{
@@ -2667,8 +2723,9 @@
/*---- Command with instruction and alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode |
cmd->Instruction | FunctionalMode));
}
}
@@ -2679,9 +2736,9 @@
/*---- Command with instruction and address ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
- cmd->Instruction | FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
{
@@ -2694,9 +2751,9 @@
/*---- Command with only instruction ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
- FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressMode |
+ cmd->InstructionMode | cmd->Instruction | FunctionalMode));
}
}
}
@@ -2712,8 +2769,9 @@
/*---- Command with address and alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressSize | cmd->AddressMode |
cmd->InstructionMode | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
@@ -2727,9 +2785,9 @@
/*---- Command with only alternate bytes ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
- cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
- FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateBytesSize | cmd->AlternateByteMode |
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
}
}
else
@@ -2739,9 +2797,9 @@
/*---- Command with only address ----*/
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
- cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
- FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressSize |
+ cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
{
@@ -2756,18 +2814,22 @@
{
/* Configure QSPI: CCR register with all communications parameters */
WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
- cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
- cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+ cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+ cmd->AlternateByteMode | cmd->AddressMode |
+ cmd->InstructionMode | FunctionalMode));
}
}
}
}
}
+
/**
* @}
*/
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx
- STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
#endif /* HAL_QSPI_MODULE_ENABLED */
/**
@@ -2778,4 +2840,6 @@
* @}
*/
+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f4xx_hal_rcc.c b/Src/stm32f4xx_hal_rcc.c
index 1857df2..7640b65 100644
--- a/Src/stm32f4xx_hal_rcc.c
+++ b/Src/stm32f4xx_hal_rcc.c
@@ -539,7 +539,7 @@
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
- pll_config = RCC->CFGR;
+ pll_config = RCC->PLLCFGR;
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
diff --git a/Src/stm32f4xx_hal_spi.c b/Src/stm32f4xx_hal_spi.c
index d166674..99531f7 100644
--- a/Src/stm32f4xx_hal_spi.c
+++ b/Src/stm32f4xx_hal_spi.c
@@ -2710,8 +2710,17 @@
}
#endif /* USE_SPI_CRC */
- /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ /* Check if we are in Master RX 2 line mode */
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* Normal case */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
diff --git a/Src/stm32f4xx_ll_fmpi2c.c b/Src/stm32f4xx_ll_fmpi2c.c
new file mode 100644
index 0000000..7d7aeaa
--- /dev/null
+++ b/Src/stm32f4xx_ll_fmpi2c.c
@@ -0,0 +1,220 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmpi2c.c
+ * @author MCD Application Team
+ * @brief FMPI2C LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+#if defined(FMPI2C_CR1_PE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_fmpi2c.h"
+#include "stm32f4xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F4xx_LL_Driver
+ * @{
+ */
+
+#if defined (FMPI2C1)
+
+/** @defgroup FMPI2C_LL FMPI2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup FMPI2C_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_FMPI2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_FMPI2C_MODE_I2C) || \
+ ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_HOST) || \
+ ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE) || \
+ ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_FMPI2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_FMPI2C_ANALOGFILTER_ENABLE) || \
+ ((__VALUE__) == LL_FMPI2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_FMPI2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_FMPI2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_FMPI2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_FMPI2C_ACK) || \
+ ((__VALUE__) == LL_FMPI2C_NACK))
+
+#define IS_LL_FMPI2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_FMPI2C_OWNADDRESS1_7BIT) || \
+ ((__VALUE__) == LL_FMPI2C_OWNADDRESS1_10BIT))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FMPI2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMPI2C_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the FMPI2C registers to their default reset values.
+ * @param FMPI2Cx FMPI2C Instance.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: FMPI2C registers are de-initialized
+ * - ERROR: FMPI2C registers are not de-initialized
+ */
+ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the FMPI2C Instance FMPI2Cx */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(FMPI2Cx));
+
+ if (FMPI2Cx == FMPI2C1)
+ {
+ /* Force reset of FMPI2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_FMPI2C1);
+
+ /* Release reset of FMPI2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_FMPI2C1);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the FMPI2C registers according to the specified parameters in FMPI2C_InitStruct.
+ * @param FMPI2Cx FMPI2C Instance.
+ * @param FMPI2C_InitStruct pointer to a @ref LL_FMPI2C_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: FMPI2C registers are initialized
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct)
+{
+ /* Check the FMPI2C Instance FMPI2Cx */
+ assert_param(IS_FMPI2C_ALL_INSTANCE(FMPI2Cx));
+
+ /* Check the FMPI2C parameters from FMPI2C_InitStruct */
+ assert_param(IS_LL_FMPI2C_PERIPHERAL_MODE(FMPI2C_InitStruct->PeripheralMode));
+ assert_param(IS_LL_FMPI2C_ANALOG_FILTER(FMPI2C_InitStruct->AnalogFilter));
+ assert_param(IS_LL_FMPI2C_DIGITAL_FILTER(FMPI2C_InitStruct->DigitalFilter));
+ assert_param(IS_LL_FMPI2C_OWN_ADDRESS1(FMPI2C_InitStruct->OwnAddress1));
+ assert_param(IS_LL_FMPI2C_TYPE_ACKNOWLEDGE(FMPI2C_InitStruct->TypeAcknowledge));
+ assert_param(IS_LL_FMPI2C_OWN_ADDRSIZE(FMPI2C_InitStruct->OwnAddrSize));
+
+ /* Disable the selected FMPI2Cx Peripheral */
+ LL_FMPI2C_Disable(FMPI2Cx);
+
+ /*---------------------------- FMPI2Cx CR1 Configuration ------------------------
+ * Configure the analog and digital noise filters with parameters :
+ * - AnalogFilter: FMPI2C_CR1_ANFOFF bit
+ * - DigitalFilter: FMPI2C_CR1_DNF[3:0] bits
+ */
+ LL_FMPI2C_ConfigFilters(FMPI2Cx, FMPI2C_InitStruct->AnalogFilter, FMPI2C_InitStruct->DigitalFilter);
+
+ /*---------------------------- FMPI2Cx TIMINGR Configuration --------------------
+ * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+ * - Timing: FMPI2C_TIMINGR_PRESC[3:0], FMPI2C_TIMINGR_SCLDEL[3:0], FMPI2C_TIMINGR_SDADEL[3:0],
+ * FMPI2C_TIMINGR_SCLH[7:0] and FMPI2C_TIMINGR_SCLL[7:0] bits
+ */
+ LL_FMPI2C_SetTiming(FMPI2Cx, FMPI2C_InitStruct->Timing);
+
+ /* Enable the selected FMPI2Cx Peripheral */
+ LL_FMPI2C_Enable(FMPI2Cx);
+
+ /*---------------------------- FMPI2Cx OAR1 Configuration -----------------------
+ * Disable, Configure and Enable FMPI2Cx device own address 1 with parameters :
+ * - OwnAddress1: FMPI2C_OAR1_OA1[9:0] bits
+ * - OwnAddrSize: FMPI2C_OAR1_OA1MODE bit
+ */
+ LL_FMPI2C_DisableOwnAddress1(FMPI2Cx);
+ LL_FMPI2C_SetOwnAddress1(FMPI2Cx, FMPI2C_InitStruct->OwnAddress1, FMPI2C_InitStruct->OwnAddrSize);
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (FMPI2C_InitStruct->OwnAddress1 != 0U)
+ {
+ LL_FMPI2C_EnableOwnAddress1(FMPI2Cx);
+ }
+
+ /*---------------------------- FMPI2Cx MODE Configuration -----------------------
+ * Configure FMPI2Cx peripheral mode with parameter :
+ * - PeripheralMode: FMPI2C_CR1_SMBDEN and FMPI2C_CR1_SMBHEN bits
+ */
+ LL_FMPI2C_SetMode(FMPI2Cx, FMPI2C_InitStruct->PeripheralMode);
+
+ /*---------------------------- FMPI2Cx CR2 Configuration ------------------------
+ * Configure the ACKnowledge or Non ACKnowledge condition
+ * after the address receive match code or next received byte with parameter :
+ * - TypeAcknowledge: FMPI2C_CR2_NACK bit
+ */
+ LL_FMPI2C_AcknowledgeNextData(FMPI2Cx, FMPI2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_FMPI2C_InitTypeDef field to default value.
+ * @param FMPI2C_InitStruct Pointer to a @ref LL_FMPI2C_InitTypeDef structure.
+ * @retval None
+ */
+void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct)
+{
+ /* Set FMPI2C_InitStruct fields to default values */
+ FMPI2C_InitStruct->PeripheralMode = LL_FMPI2C_MODE_I2C;
+ FMPI2C_InitStruct->Timing = 0U;
+ FMPI2C_InitStruct->AnalogFilter = LL_FMPI2C_ANALOGFILTER_ENABLE;
+ FMPI2C_InitStruct->DigitalFilter = 0U;
+ FMPI2C_InitStruct->OwnAddress1 = 0U;
+ FMPI2C_InitStruct->TypeAcknowledge = LL_FMPI2C_NACK;
+ FMPI2C_InitStruct->OwnAddrSize = LL_FMPI2C_OWNADDRESS1_7BIT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C1 */
+
+/**
+ * @}
+ */
+
+#endif /* FMPI2C_CR1_PE */
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f4xx_ll_usb.c b/Src/stm32f4xx_ll_usb.c
index 9263fc3..8e7c747 100644
--- a/Src/stm32f4xx_ll_usb.c
+++ b/Src/stm32f4xx_ll_usb.c
@@ -290,6 +290,8 @@
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
{
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
@@ -310,6 +312,7 @@
* Disable HW VBUS sensing. VBUS is internally considered to be always
* at VBUS-Valid level (5V).
*/
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
@@ -317,7 +320,7 @@
else
{
/* Enable HW VBUS sensing */
- USBx->GOTGCTL &= ~USB_OTG_GCCFG_NOVBUSSENS;
+ USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
@@ -409,17 +412,6 @@
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
- if (cfg.dma_enable == 1U)
- {
- /*Set threshold parameters */
- USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |
- USB_OTG_DTHRCTL_RXTHRLEN_6;
-
- USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |
- USB_OTG_DTHRCTL_ISOTHREN |
- USB_OTG_DTHRCTL_NONISOTHREN;
- }
-
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
@@ -641,6 +633,12 @@
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
@@ -651,6 +649,12 @@
}
else
{
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
@@ -676,11 +680,23 @@
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+ }
+
USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
else
{
+ if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+ }
+
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
@@ -1247,13 +1263,9 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
- /* Set the MPS of the IN EP based on the enumeration speed */
+ /* Set the MPS of the IN EP0 to 64 bytes */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
- if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
- {
- USBx_INEP(0U)->DIEPCTL |= 3U;
- }
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
return HAL_OK;
@@ -1367,7 +1379,7 @@
if ((USBx->CID & (0x1U << 8)) != 0U)
{
- if (cfg.speed == USB_OTG_SPEED_FULL)
+ if (cfg.speed == USBH_FSLS_SPEED)
{
/* Force Device Enumeration to FS/LS mode only */
USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
@@ -1936,7 +1948,6 @@
uint32_t value;
uint32_t i;
-
(void)USB_DisableGlobalInt(USBx);
/* Flush FIFO */
@@ -1975,6 +1986,7 @@
/* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFFU;
USBx->GINTSTS = 0xFFFFFFFFU;
+
(void)USB_EnableGlobalInt(USBx);
return HAL_OK;
