Release v1.4.5
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index fc8bb49..934f1f9 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -37,14 +37,16 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
+#endif /* STM32U5 || STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -110,6 +112,7 @@
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
+
/**
* @}
*/
@@ -231,9 +234,11 @@
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
+#if defined(STM32C0)
+#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-
+#endif
/**
* @}
*/
@@ -500,7 +505,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@@ -1084,8 +1089,8 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1096,15 +1101,22 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+#if defined(STM32F7) || defined(STM32H7)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 */
/**
* @}
@@ -3411,7 +3423,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3524,8 +3536,8 @@
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
-#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3541,16 +3553,20 @@
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
-#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
-#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
-#endif
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
/**
* @}
@@ -3568,7 +3584,9 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
+ defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3632,7 +3650,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3969,6 +3987,16 @@
* @}
*/
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
diff --git a/Inc/stm32g0xx_hal_adc.h b/Inc/stm32g0xx_hal_adc.h
index acc9fb6..3486689 100644
--- a/Inc/stm32g0xx_hal_adc.h
+++ b/Inc/stm32g0xx_hal_adc.h
@@ -62,27 +62,33 @@
/**
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+ * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC
+ * groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
- * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
+ * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on
+ * group regular.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
- * (which fulfills the ADC state condition) on the fly).
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
- uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
+ clock derived from system clock or PLL (Refer to reference manual for list of
+ clocks available)) and clock prescaler.
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
Note: The ADC clock configuration is common to all ADC instances.
- Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
- if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
- must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
- Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
+ Note: In case of synchronous clock mode based on HCLK/1, the configuration must
+ be enabled only if the system clock has a 50% duty clock cycle (APB
+ prescaler configured inside RCC must be bypassed and PCLK clock must have
+ 50% duty cycle). Refer to reference manual for details.
+ Note: In case of usage of asynchronous clock, the selected clock must be
+ preliminarily enabled at RCC top level.
Note: This parameter can be modified only if all ADC instances are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
@@ -93,15 +99,16 @@
This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular.
- On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are
- available:
+ On this STM32 series, ADC group regular sequencer both modes "fully configurable"
+ or "not fully configurable" are available:
- sequencer configured to fully configurable:
sequencer length and each rank affectation to a channel are configurable.
- Sequence length: Set number of ranks in the scan sequence.
- Sequence direction: Unless specified in parameters, sequencer
scan direction is forward (from rank 1 to rank n).
- sequencer configured to not fully configurable:
- sequencer length and each rank affectation to a channel are fixed by channel HW number.
+ sequencer length and each rank affectation to a channel are fixed by channel
+ HW number.
- Sequence length: Number of ranks in the scan sequence is
defined by number of channels set in the sequence,
rank of each channel is fixed by channel HW number.
@@ -109,101 +116,156 @@
- Sequence direction: Unless specified in parameters, sequencer
scan direction is forward (from lowest channel number to
highest channel number).
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have
+ main sequence subdivided in successive parts. Sequencer is automatically enabled
+ if several channels are set (sequencer cannot be disabled, as it can be the case
+ on other STM32 devices):
If only 1 channel is set: Conversion is performed in single mode.
If several channels are set: Conversions are performed in sequence mode.
This parameter can be a value of @ref ADC_Scan_mode */
- uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
+ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
+ interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
- FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
- conversion (for ADC group regular) has been retrieved by user software,
+ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
+ previous conversion (for ADC group regular) has been retrieved by user software,
using function HAL_ADC_GetValue().
- This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
- for low frequency applications.
+ This feature automatically adapts the frequency of ADC conversions triggers to
+ the speed of the system that reads the data. Moreover, this avoids risk of
+ overrun for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
- Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
- Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
- Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
- use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
+ HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
+ flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended
+ benefit (except specific case of high load of CPU or DMA transfers which
+ can justify usage of auto wait).
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
+ when ADC conversion data is needed:
+ use HAL_ADC_PollForConversion() to ensure that conversion is completed and
+ HAL_ADC_GetValue() to retrieve conversion result and trig another
+ conversion start. */
- FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
- This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
- This parameter can be set to ENABLE or DISABLE. */
+ FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a
+ conversion and automatically wakes-up when a new conversion is triggered
+ (with startup time between trigger and start of sampling).
+ This feature can be combined with automatic wait mode
+ (parameter 'LowPowerAutoWait').
+ This parameter can be set to ENABLE or DISABLE. */
- FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
- after the first ADC conversion start trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
+ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
+ or continuous mode for ADC group regular, after the first ADC conversion
+ start trigger occurred (software start or external trigger). This parameter
+ can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
+ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
+ sequencer.
This parameter is dependent on ScanConvMode:
- sequencer configured to fully configurable:
Number of ranks in the scan sequence is configurable using this parameter.
- Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
- Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks
- (sequencer ranks above 'NbrOfConversion' are discarded).
+ Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
+ parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
+ Afterwards, when all needed sequencer ranks are set, parameter
+ 'NbrOfConversion' can be updated without modifying configuration of
+ sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
- sequencer configured to not fully configurable:
- Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded.
+ Number of ranks in the scan sequence is defined by number of channels set in
+ the sequence. This parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8.
- Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+ Note: This parameter must be modified when no conversion is on going on regular
+ group (ADC disabled, or ADC enabled without continuous mode or external
+ trigger that could launch a conversion). */
- FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
- (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
+ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
+ in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
+ successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter
+ 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled.
+ If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: On this STM32 series, ADC group regular number of discontinuous
+ ranks increment is fixed to one-by-one. */
- uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
- If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion
+ start.
+ If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
+ is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
- uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
- FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
- or in continuous mode (DMA transfer unlimited, whatever number of conversions).
- This parameter can be set to ENABLE or DISABLE.
- Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
+ FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
+ transfer stops when number of conversions is reached) or in continuous
+ mode (DMA transfer unlimited, whatever number of conversions).
+ This parameter can be set to ENABLE or DISABLE.
+ Note: In continuous mode, DMA must be configured in circular mode.
+ Otherwise an overrun will be triggered when DMA buffer maximum
+ pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
- Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
- end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
- HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
+ Note: In case of overrun set to data preserved and usage with programming model
+ with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
+ conversion flags, this induces the release of the preserved data. If
+ needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
+ placed in user program code (called before end of conversion flags clear)
Note: Error reporting with respect to the conversion mode:
- - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
- overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+ - Usage with ADC conversion by polling for event or interruption: Error is
+ reported only if overrun is set to data preserved. If overrun is set to
+ data overwritten, user can willingly not read all the converted data,
+ this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun
+ setting (DMA is expected to process all data from data register). */
uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
- Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits,
+ 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits,
+ 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available,
+ each channel can use one of these two settings. On some other STM32 devices
+ this parameter in channel wise and is located into ADC channel
+ initialization structure.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
+ sampling time constraints must be respected (sampling time can be adjusted
+ in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint,
+ TS_vbat, TS_temp (values rough order: few tens of microseconds). */
uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible.
Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
- Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits,
+ 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits,
+ 6.5 cycles at 6 bits).
+ Note: On this STM32 family, two different sampling time settings are available,
+ each channel can use one of these two settings. On some other STM32 devices
+ this parameter in channel wise and is located into ADC channel
+ initialization structure.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
+ sampling time constraints must be respected (sampling time can be adjusted
+ in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint,
+ TS_vbat, TS_temp (values rough order: few tens of microseconds). */
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
- Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
+ Note: This parameter can be modified only if there is no conversion is
+ ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
- Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+ Caution: this setting overwrites the previous oversampling configuration
+ if oversampling is already enabled. */
uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
@@ -224,16 +286,19 @@
* ADC state can be either:
* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
- * on the fly).
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
- Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+ Note: Depending on devices and ADC instances, some channels may not be available
+ on device package pins. Refer to device datasheet for channels
+ availability. */
- uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank.
+ uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its
+ conversion rank.
This parameter is dependent on ScanConvMode:
- sequencer configured to fully configurable:
Channels ordering into each rank of scan sequence:
@@ -241,18 +306,26 @@
- sequencer configured to not fully configurable:
rank of each channel is fixed by channel HW number.
(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+ Despite the channel rank is fixed, this parameter allow an additional
+ possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time
- (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ (12.5 ADC clock cycles at ADC resolution 12 bits,
+ 10.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits,
+ 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON
- Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings.
+ Note: On this STM32 family, two different sampling time settings are available
+ (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"),
+ each channel can use one of these two settings.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/
+ TempSensor), sampling time constraints must be respected (sampling time
+ can be adjusted in function of ADC clock frequency and sampling time
+ setting)
Refer to device datasheet for timings values. */
} ADC_ChannelConfTypeDef;
@@ -261,48 +334,62 @@
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
- * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular.
+ * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion
+ on going on ADC groups regular.
* - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.
*/
typedef struct
{
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
- For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
- For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
+ by setting parameter 'WatchdogMode')
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
+ of 'HAL_ADC_AnalogWDGConfig()' for each channel)
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
- For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular.
- For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure.
+ For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
+ channels, ADC group regular.
+ For Analog Watchdog 2 and 3: Several channels can be monitored by applying
+ successively the AWD init structure.
This parameter can be a value of @ref ADC_analog_watchdog_mode. */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
- For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
- For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
+ is configured on single channel (only 1 channel can be
+ monitored).
+ For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
+ call successively the function HAL_ADC_AnalogWDGConfig()
+ for each channel to be added (or removed with value
+ 'ADC_ANALOGWATCHDOG_NONE').
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
- between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
- Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
- the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
- Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+ number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+ respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+ resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+ LSB are ignored. */
+ /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
ADC data register bitfield [15:4] (12 most significant bits). */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
- between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
- Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
- the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
- Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+ number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+ respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+ resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+ LSB are ignored.*/
+ /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
- ADC data register bitfield [15:4] (12 most significant bits). */
+ ADC data register bitfield [15:4] (12 most significant bits).*/
} ADC_AnalogWDGConfTypeDef;
/** @defgroup ADC_States ADC States
@@ -320,7 +407,7 @@
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to internal process (ex : calibration) */
#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
/* States of ADC errors */
@@ -329,17 +416,25 @@
#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
+ (either by continuous mode, external trigger, low power
+ auto power-on (if feature available), multimode ADC master
+ control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag
+ raised */
/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/
-#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow occurrence */
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group
+ injected is ongoing or can occur (either by auto-injection
+ mode, external trigger, low power auto power-on (if feature
+ available), multimode ADC master control (if feature
+ available))*/
+#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data
+ available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow
+ occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
@@ -347,7 +442,9 @@
#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave
+ state, controlled by another ADC master (when feature
+ available) */
/**
@@ -363,17 +460,20 @@
typedef struct
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
{
- ADC_TypeDef *Instance; /*!< Register base address */
- ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
- HAL_LockTypeDef Lock; /*!< ADC locking object */
- __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
- __IO uint32_t ErrorCode; /*!< ADC Error code */
+ ADC_TypeDef *Instance; /*!< Register base address */
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
- uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
+ uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks
+ setting, used in mode "fully configurable" (refer to
+ parameter 'ScanConvMode') */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
- void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer
+ callback */
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
@@ -437,22 +537,38 @@
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
-#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock
+ without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler
+ configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock
+ with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock
+ with prescaler division by 4 */
-#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
-#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
-#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
-#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
-#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
-#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
-#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
-#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
-#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
-#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
-#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
-#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
+#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without
+ prescaler */
+#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler
+ division by 2 */
+#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler
+ division by 4 */
+#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler
+ division by 6 */
+#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler
+ division by 8 */
+#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler
+ division by 10 */
+#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler
+ division by 12 */
+#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler
+ division by 16 */
+#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler
+ division by 32 */
+#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler
+ division by 64 */
+#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler
+ division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler
+ division by 256 */
/**
* @}
*/
@@ -471,8 +587,10 @@
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
* @{
*/
-#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
+ (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned
+ (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -493,14 +611,23 @@
/* as default setting equivalent to scan enable. */
/* In case of migration from another STM32 device, the user will be */
/* warned of change of setting choices with assert check. */
-#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
-#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
+/* Sequencer set to fully configurable */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable:
+ only the rank 1 is enabled (no scan sequence on several ranks) */
+#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable:
+ sequencer length and each rank affectation to a channel are configurable. */
-#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
-#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
+/* Sequencer set to not fully configurable */
+#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable:
+ sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0,
+ channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \
+ | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable:
+ sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0,
+ channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
-#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
-#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */
+#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */
+#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */
/**
* @}
*/
@@ -509,23 +636,35 @@
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
-#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
-#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< Software start. */
+/** ADC group regular conversion trigger from external peripheral */
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< TIM1 TRGO. Trigger edge set to
+ rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< TIM1 channel 4 event (capture
+ compare: input capture or output
+ capture). Trigger edge set to
+ rising edge (default setting). */
#if defined(TIM2)
-#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< TIM2 TRGO. Trigger edge set to
+ rising edge (default setting). */
#endif /* TIM2 */
-#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< TIM3 TRGO. Trigger edge set to
+ rising edge (default setting). */
#if defined(TIM4)
-#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< TIM4 TRGO. Trigger edge set to
+ rising edge (default setting). */
#endif /* TIM4 */
#if defined(TIM6)
-#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< TIM6 TRGO. Trigger edge set to
+ rising edge (default setting). */
#endif /* TIM6 */
#if defined(TIM15)
-#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< TIM15 TRGO. Trigger edge set to
+ rising edge (default setting). */
#endif /* TIM15 */
-#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< External interrupt line 11. Trigger
+ edge set to rising edge (default
+ setting). */
/**
* @}
*/
@@ -533,10 +672,15 @@
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
* @{
*/
-#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
-#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger
+ detection disabled (SW start)*/
+#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular trigger
+ polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular trigger
+ polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular trigger
+ polarity set to both rising and
+ falling edges */
/**
* @}
*/
@@ -553,8 +697,13 @@
/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
-#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
-#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @brief ADC group regular behavior in case of overrun
+ */
+#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of
+ overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of
+ overrun: data overwritten */
/**
* @}
*/
@@ -562,17 +711,24 @@
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
-#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
-#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
+#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of ranks in
+ the sequence is defined by number of channels enabled, rank
+ of each channel is defined by channel number (channel 0 fixed
+ on rank 0, channel 1 fixed on rank1, ...).
+ Setting relevant if parameter "ScanConvMode" is set to
+ sequencer not fully configurable. */
+#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from sequencer.
+ Setting relevant if parameter "ScanConvMode" is set to
+ sequencer not fully configurable. */
-#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
-#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
-#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
-#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
-#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
-#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
-#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
-#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
/**
* @}
*/
@@ -580,8 +736,10 @@
/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
* @{
*/
-#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
-#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of
+ channels: sampling time nb 1 */
+#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of
+ channels: sampling time nb 2 */
/**
* @}
*/
@@ -589,14 +747,14 @@
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
-#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
-#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
-#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
-#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
-#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
-#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
-#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
+#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
+#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
+#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
/**
* @}
*/
@@ -604,28 +762,30 @@
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
* @{
*/
-#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
-#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
-#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
-#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
-#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
-#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
-#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
-#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
-#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
-#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
-#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
-#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
-#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
-#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
+#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */
+#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */
+#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */
+#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */
+#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */
+#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */
+#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */
+#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */
+#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */
+#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */
+#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel Internal voltage reference*/
+#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor */
+#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3:
+ Vbat voltage through a divider ladder of
+ factor 1/3 to have Vbat always below Vdda. */
/**
* @}
*/
@@ -643,9 +803,11 @@
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
-#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
-#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a
+ regular group, single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to
+ regular group, all channels */
/**
* @}
*/
@@ -653,14 +815,18 @@
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
-#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+ * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
+ * to result as the ADC oversampling conversion data (before potential shift)
+ */
+#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */
+#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */
+#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */
+#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */
+#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */
+#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */
+#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */
+#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */
/**
* @}
*/
@@ -668,15 +834,19 @@
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
-#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+/**
+ * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
+ * conversion data)
+ */
+#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */
+#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
+#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
+#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
+#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
+#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
+#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
+#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
+#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
/**
* @}
*/
@@ -684,8 +854,12 @@
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
-#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
-#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode:
+ continuous mode (all conversions of
+ OVS ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode:
+ discontinuous mode (each conversion of
+ OVS ratio needs a trigger) */
/**
* @}
*/
@@ -693,8 +867,15 @@
/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
* @{
*/
-#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
-#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+
+/**
+ * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion
+ * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion
+ * start trigger event).
+ * Duration value: Refer to device datasheet, parameter "tIdle".
+ */
+#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */
+#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */
/**
* @}
*/
@@ -702,28 +883,33 @@
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
+/**
+ * @note Analog watchdog 1 is available on all stm32 series
+ * Analog watchdog 2 and 3 are not available on all series
+ */
#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
-#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
-#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
-#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */
+#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
+#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
/**
* @}
*/
-#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility
+ with other STM32 devices having only one analog watchdog */
/** @defgroup ADC_interrupts_definition ADC interrupts definition
* @{
*/
#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */
-#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
-#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
-#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
-#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
-#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
-#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
-#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< End of sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< End of regular conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< overrun interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< Analog watchdog 2 interrupt source (additional analog watchdog) */
+#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< Analog watchdog 3 interrupt source (additional analog watchdog) */
/**
* @}
*/
@@ -1038,7 +1224,8 @@
/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
-#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */
+/* Internal definition to differentiate sequencer setting fixed or configurable */
+#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U
/**
* @}
@@ -1301,7 +1488,8 @@
* (1) On STM32G0, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
- * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+ * (channel connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
@@ -1603,11 +1791,14 @@
* @note ADC measurement data must correspond to a resolution of 12bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 12 bits.
- * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
+ (unit: uV/DegCelsius).
* On STM32G0, refer to device datasheet parameter "Avg_Slope".
- * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
- * On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
- * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at
+ temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see
+ parameter above) is corresponding (unit: mV)
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
diff --git a/Inc/stm32g0xx_hal_adc_ex.h b/Inc/stm32g0xx_hal_adc_ex.h
index c14d4a5..dbf21eb 100644
--- a/Inc/stm32g0xx_hal_adc_ex.h
+++ b/Inc/stm32g0xx_hal_adc_ex.h
@@ -53,7 +53,8 @@
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
* @{
*/
-#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
+#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on
+ all STM32 devices) */
/**
* @}
*/
diff --git a/Inc/stm32g0xx_hal_hcd.h b/Inc/stm32g0xx_hal_hcd.h
index c14b352..16e489c 100644
--- a/Inc/stm32g0xx_hal_hcd.h
+++ b/Inc/stm32g0xx_hal_hcd.h
@@ -309,10 +309,10 @@
/** @addtogroup PMA Allocation
* @{
*/
-HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t pipe,
- uint16_t pipe_kind, uint16_t mps);
+HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint16_t ch_kind, uint16_t mps);
-HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t pipe);
+HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
/**
@@ -475,7 +475,7 @@
* @param bChNum channel Number.
* @retval Counter value
*/
-__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
+__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
@@ -509,7 +509,7 @@
* @param bChNum channel Number.
* @retval Counter value
*/
-__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
+__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
@@ -529,7 +529,7 @@
* @param bChNum channel Number.
* @retval Counter value
*/
-__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
+__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
diff --git a/Inc/stm32g0xx_hal_i2c.h b/Inc/stm32g0xx_hal_i2c.h
index 6a1dc38..9a7b222 100644
--- a/Inc/stm32g0xx_hal_i2c.h
+++ b/Inc/stm32g0xx_hal_i2c.h
@@ -217,6 +217,10 @@
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+ __IO uint32_t Devaddress; /*!< I2C Target device address */
+
+ __IO uint32_t Memaddress; /*!< I2C Target memory address */
+
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
diff --git a/Inc/stm32g0xx_hal_irda.h b/Inc/stm32g0xx_hal_irda.h
index b22a6db..1d4cbc1 100644
--- a/Inc/stm32g0xx_hal_irda.h
+++ b/Inc/stm32g0xx_hal_irda.h
@@ -864,8 +864,8 @@
*/
/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
/**
* @}
diff --git a/Inc/stm32g0xx_hal_pcd.h b/Inc/stm32g0xx_hal_pcd.h
index d507849..d533fc4 100644
--- a/Inc/stm32g0xx_hal_pcd.h
+++ b/Inc/stm32g0xx_hal_pcd.h
@@ -527,7 +527,7 @@
* @param bEpNum channel Number.
* @retval Counter value
*/
-__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(PCD_TypeDef *Instance, uint16_t bEpNum)
+__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
@@ -570,7 +570,7 @@
* @param bEpNum channel Number.
* @retval Counter value
*/
-__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(PCD_TypeDef *Instance, uint16_t bEpNum)
+__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
@@ -590,7 +590,7 @@
* @param bEpNum channel Number.
* @retval Counter value
*/
-__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(PCD_TypeDef *Instance, uint16_t bEpNum)
+__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum)
{
UNUSED(Instance);
__IO uint32_t count = 10U;
diff --git a/Inc/stm32g0xx_hal_rtc.h b/Inc/stm32g0xx_hal_rtc.h
index 30bbe98..6855d3a 100644
--- a/Inc/stm32g0xx_hal_rtc.h
+++ b/Inc/stm32g0xx_hal_rtc.h
@@ -563,6 +563,13 @@
} while(0U)
/**
+ * @brief Check whether the RTC Calendar is initialized.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
+
+/**
* @brief Add 1 hour (summer time change).
* @note This interface is deprecated.
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
diff --git a/Inc/stm32g0xx_hal_smartcard.h b/Inc/stm32g0xx_hal_smartcard.h
index 7cb4e0e..7e7ff58 100644
--- a/Inc/stm32g0xx_hal_smartcard.h
+++ b/Inc/stm32g0xx_hal_smartcard.h
@@ -1109,8 +1109,8 @@
* @{
*/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
diff --git a/Inc/stm32g0xx_hal_uart.h b/Inc/stm32g0xx_hal_uart.h
index 36eccc2..e8f3c25 100644
--- a/Inc/stm32g0xx_hal_uart.h
+++ b/Inc/stm32g0xx_hal_uart.h
@@ -193,7 +193,7 @@
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
- * It is expected to admit following values :
+ * This parameter can be a value of @ref UART_Reception_Type_Values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
@@ -202,6 +202,17 @@
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
+ * @brief HAL UART Rx Event type definition
+ * @note HAL UART Rx Event type value aims to identify which type of Event has occurred
+ * leading to call of the RxEvent callback.
+ * This parameter can be a value of @ref UART_RxEvent_Type_Values :
+ * HAL_UART_RXEVENT_TC = 0x00U,
+ * HAL_UART_RXEVENT_HT = 0x01U,
+ * HAL_UART_RXEVENT_IDLE = 0x02U,
+ */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -235,6 +246,8 @@
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+ __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -804,7 +817,7 @@
* @}
*/
-/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+/** @defgroup UART_Reception_Type_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
@@ -815,6 +828,16 @@
* @}
*/
+/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
+ * @{
+ */
+#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
+#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/Inc/stm32g0xx_hal_uart_ex.h b/Inc/stm32g0xx_hal_uart_ex.h
index b9a2458..89e63a3 100644
--- a/Inc/stm32g0xx_hal_uart_ex.h
+++ b/Inc/stm32g0xx_hal_uart_ex.h
@@ -178,6 +178,8 @@
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+
/**
* @}
diff --git a/Inc/stm32g0xx_hal_usart.h b/Inc/stm32g0xx_hal_usart.h
index a8ba195..300c1dc 100644
--- a/Inc/stm32g0xx_hal_usart.h
+++ b/Inc/stm32g0xx_hal_usart.h
@@ -881,8 +881,8 @@
*/
/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
/**
* @}
diff --git a/Inc/stm32g0xx_ll_adc.h b/Inc/stm32g0xx_ll_adc.h
index b889d42..4c2fdcf 100644
--- a/Inc/stm32g0xx_ll_adc.h
+++ b/Inc/stm32g0xx_ll_adc.h
@@ -68,23 +68,25 @@
/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
/* - regular trigger source */
/* - regular trigger edge */
-#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
+ compatibility with some ADC on other STM32 families
+ having this setting set by HW default value) */
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
- ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
- ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
- ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
+ ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
+ ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
+ ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
/* Definition of ADC group regular trigger bits information. */
#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
@@ -100,12 +102,17 @@
/* GPIO pins) and internal channels (connected to internal paths) */
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
-#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
+#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
+ ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
+ if set to mode "fully configurable", can contain channels with a restricted channel number.
+ Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
+ position in register */
#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
+ >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
/* Channel differentiation between external and internal channels */
#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
@@ -194,17 +201,22 @@
#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
-#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
+#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
+ in ADC_AWD_CRX_REGOFFSET_MASK */
/* Internal register offset for ADC analog watchdog threshold configuration */
#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
-#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
-#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
-#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
-#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
+#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
+ in ADC_AWD_TRX_REGOFFSET_MASK */
+#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
+ threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
+ threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
+ position to perform a shift of 4 ranks */
#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
@@ -238,19 +250,31 @@
/* ADC registers bits groups */
-#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
+ | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
+ HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference,
+ address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC),
+ Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value
+ with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G0,
+ temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC),
+ Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G0,
+ temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC),
+ Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor
+ has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor
+ has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) value
+ with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/**
* @}
@@ -298,8 +322,8 @@
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetCommonClock(). */
} LL_ADC_CommonInitTypeDef;
@@ -325,27 +349,29 @@
{
uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
- @note On this STM32 series, this parameter has some clock ratio constraints:
- ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
- (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
+ @note On this STM32 series, this parameter has some clock ratio constraints:
+ ADC clock synchronous (from PCLK) with prescaler 1 must be enabled
+ only if PCLK has a 50% duty clock cycle (APB prescaler configured
+ inside the RCC must be bypassed and the system clock must by 50% duty
+ cycle).
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetClock().
For more details, refer to description of this function. */
uint32_t Resolution; /*!< Set ADC resolution.
This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetResolution(). */
uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetDataAlignment(). */
uint32_t LowPowerMode; /*!< Set ADC low power mode.
This parameter can be a value of @ref ADC_LL_EC_LP_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_SetLowPowerMode(). */
} LL_ADC_InitTypeDef;
@@ -370,43 +396,57 @@
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
+ from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
- (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
- In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+ @note On this STM32 series, setting trigger source to external trigger also
+ set trigger polarity to rising edge(default setting for compatibility
+ with some ADC on other STM32 families having this setting set by HW
+ default value).
+ In case of need to modify trigger edge, use function
+ @ref LL_ADC_REG_SetTriggerEdge().
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetTriggerSource(). */
uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
- @note This parameter has an effect only if group regular sequencer is set to mode "fully configurable". Refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ @note This parameter has an effect only if group regular sequencer is set
+ to mode "fully configurable". Refer to function
+ @ref LL_ADC_REG_SetSequencerConfigurable().
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetSequencerLength(). */
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
+ and scan conversions interrupted every selected number of ranks.
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group regular sequencer is enabled
- (depending on the sequencer mode: scan length of 2 ranks or more, or several ADC channels enabled in group regular sequencer. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
+ @note This parameter has an effect only if group regular sequencer is
+ enabled (depending on the sequencer mode: scan length of 2 ranks or
+ more, or several ADC channels enabled in group regular sequencer.
+ Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetSequencerDiscont(). */
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
-
- uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
+ conversions are performed in single mode (one conversion per trigger) or in
+ continuous mode (after the first trigger, following conversions launched
+ successively automatically).
This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
- Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+ Note: It is not possible to enable both ADC group regular continuous mode
+ and discontinuous mode.
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetContinuousMode(). */
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
-
- uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
+ by DMA, and DMA requests mode.
This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetDMATransfer(). */
uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
data preserved or overwritten.
This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_ADC_REG_SetOverrun(). */
} LL_ADC_REG_InitTypeDef;
@@ -426,8 +466,10 @@
*/
#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
-#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
-#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
+ conversion */
+#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
+ conversions */
#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
@@ -444,10 +486,13 @@
*/
#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
-#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
-#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
+#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
+ conversion */
+#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
+ conversions */
#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
-#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
+#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
+ phase */
#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
@@ -462,7 +507,12 @@
/* List of ADC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
-#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
+ (corresponding to register DR) to be used with ADC
+ configured in independent mode. Without DMA transfer,
+ register accessed by LL function
+ @ref LL_ADC_REG_ReadConversionData32() and other
+ functions @ref LL_ADC_REG_ReadConversionDatax() */
/**
* @}
*/
@@ -470,18 +520,43 @@
/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
-#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
-#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
-#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
+prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+prescaler division by 2. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
+prescaler division by 4. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+prescaler division by 6. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
+prescaler division by 8. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+prescaler division by 10. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
+prescaler division by 12. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
+ | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+prescaler division by 16. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
+prescaler division by 32. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+prescaler division by 64. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
+prescaler division by 128. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
+ | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+prescaler division by 256. Setting common to ADC instances of ADC common group, applied ADC instance wise to each
+instance clock set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
/**
* @}
*/
@@ -489,8 +564,10 @@
/** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode
* @{
*/
-#define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL) /*!< ADC clock mode to high frequency. On STM32G0, ADC clock frequency above 3.5MHz. */
-#define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low frequency. On STM32G0, ADC clock frequency below 3.5MHz. */
+#define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL) /*!< ADC clock mode to high frequency.
+ On STM32G0, ADC clock frequency above 3.5MHz. */
+#define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low frequency.
+ On STM32G0,ADC clock frequency below 3.5MHz. */
/**
* @}
*/
@@ -503,10 +580,11 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
-#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
-#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
-#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
+ temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
/**
* @}
*/
@@ -514,10 +592,15 @@
/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
* @{
*/
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
-#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock
+ divided by 4 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
+ divided by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived
+ from AHB clock not divided */
+#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock
+ prescaler can be configured using function
+ @ref LL_ADC_SetCommonClock(). */
/**
* @}
*/
@@ -536,8 +619,10 @@
/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
* @{
*/
-#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
+ (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
+ (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -545,10 +630,16 @@
/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
* @{
*/
-#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
-#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
-#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
-#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power
+mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read).
+See description with function @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC
+automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered
+(with startup time between trigger and start of sampling). See description with function
+@ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait
+and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
/**
* @}
*/
@@ -556,8 +647,14 @@
/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
* @{
*/
-#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
-#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency.
+Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion
+start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start
+trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
+#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency.
+Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion
+start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start
+trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
/**
* @}
*/
@@ -565,8 +662,11 @@
/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
* @{
*/
-#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
-#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
+#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group
+ of channels: sampling time nb 1 */
+#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \
+ | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group
+ of channels: sampling time nb 2 */
/**
* @}
*/
@@ -574,7 +674,7 @@
/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
* @{
*/
-#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
/**
* @}
*/
@@ -582,28 +682,31 @@
/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
* @{
*/
-#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
-#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
-#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
-#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
-#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
-#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
-#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
-#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
-#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
-#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
-#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
-#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
-#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
-#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+connected to VrefInt: Internal voltage reference. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+connected to Temperature sensor. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
/**
* @}
*/
@@ -611,23 +714,39 @@
/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
* @{
*/
-#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
-#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
+conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture).
+Trigger edge set to rising edge (default setting). */
#if defined(TIM2)
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#endif /* TIM2 */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+
+conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#if defined(TIM4)
-#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#endif /* TIM4 */
#if defined(TIM6)
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | \
+ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#endif /* TIM6 */
#if defined(TIM15)
-#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#endif /* TIM15 */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | \
+ ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge
+(default setting). */
/**
* @}
*/
@@ -635,9 +754,12 @@
/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
* @{
*/
-#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
+trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion
+trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
+trigger polarity set to both rising and falling edges */
/**
* @}
*/
@@ -645,8 +767,10 @@
/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
* @{
*/
-#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
-#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
+one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode:
+after the first trigger, following conversions launched successively automatically */
/**
* @}
*/
@@ -654,9 +778,13 @@
/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
* @{
*/
-#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
-#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
-#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA,
+in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of
+ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are
+transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred
+(number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
/**
* @}
*/
@@ -664,8 +792,10 @@
/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
-#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
-#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
+#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
+ data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
+ data overwritten */
/**
* @}
*/
@@ -673,8 +803,12 @@
/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
* @{
*/
-#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
-#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
+#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable:
+sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of
+function @ref LL_ADC_REG_SetSequencerChannels(). */
+#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable:
+sequencer length and each rank affectation to a channel are configurable. Refer to description of
+function @ref LL_ADC_REG_SetSequencerLength(). */
/**
* @}
*/
@@ -682,14 +816,23 @@
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
* @{
*/
-#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable
+ (equivalent to sequencer of 1 rank:
+ ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable
+ with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable
+ with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable
+ with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable
+ with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable
+ with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable
+ with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable
+ with 8 ranks in the sequence */
/**
* @}
*/
@@ -697,8 +840,15 @@
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
* @{
*/
-#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
-#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
+#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if
+sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of
+all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 series, this setting
+is not available and the default scan direction is forward. */
+#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if
+sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of
+all ranks, ADC conversion of ranks with channels enabled in sequencer) */
/**
* @}
*/
@@ -706,8 +856,10 @@
/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
* @{
*/
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
-#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
+discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
+discontinuous mode enable with sequence interruption every rank */
/**
* @}
*/
@@ -715,14 +867,14 @@
/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
-#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
-#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
-#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
-#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
-#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
-#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
-#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
-#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */
/**
* @}
*/
@@ -730,14 +882,19 @@
/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
-#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
-#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \
+ | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \
+ | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \
+ | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \
+ | ADC_SMPR_SMP1_1 \
+ | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
/**
* @}
*/
@@ -745,9 +902,12 @@
/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
* @{
*/
-#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
-#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
+ | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
+ | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
+ | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
/**
* @}
*/
@@ -755,30 +915,78 @@
/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
* @{
*/
-#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
-#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
-#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
-#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
+disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
+ | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
+of all channels, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC channel ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
+ | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat
+always below Vdda, converted by group regular only */
/**
* @}
*/
@@ -786,9 +994,11 @@
/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
* @{
*/
-#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 ) /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
-#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \
+ | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low
+ concatenated into the same data */
/**
* @}
*/
@@ -796,8 +1006,10 @@
/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
* @{
*/
-#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
-#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
+#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of
+ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group
+injected, in this case other oversampling scope parameters are available. */
/**
* @}
*/
@@ -805,8 +1017,10 @@
/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
-#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
-#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
+(all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous
+mode (each conversion of oversampling ratio needs a trigger) */
/**
* @}
*/
@@ -814,30 +1028,49 @@
/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
-#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
+ | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
+(sum of conversions data computed to result as oversampling conversion data (before potential shift) */
/**
* @}
*/
-/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
+/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
* @{
*/
-#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
-#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
+(sum of the ADC conversions data is not divided to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
+(sum of the ADC conversions data (after OVS ratio) is divided by 2 to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
+(sum of the ADC conversions data (after OVS ratio) is divided by 4 to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
+(sum of the ADC conversions data (after OVS ratio) is divided by 8 to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
+(sum of the ADC conversions data (after OVS ratio) is divided by 16 to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
+(sum of the ADC conversions data (after OVS ratio) is divided by 32 to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
+(sum of the ADC conversions data (after OVS ratio) is divided by 64 to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
+ | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
+(sum of the ADC conversions data (after OVS ratio) is divided by 128 to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
+(sum of the ADC conversions data (after OVS ratio) is divided by 256 to result as oversampling conversion data) */
/**
* @}
*/
@@ -845,7 +1078,11 @@
/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
* @{
*/
-#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */
+#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
+ @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
+ calibration parameters. This value is coded on 16 bits
+ (to fit on signed word or double word) and corresponds
+ to an inconsistent temperature value. */
/**
* @}
*/
@@ -880,20 +1117,26 @@
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tADCVREG_STUP"). */
/* Unit: us */
-#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
+ regulator start-up time) */
/* Delay for internal voltage reference stabilization time. */
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tstart_vrefint"). */
/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
+ time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time (starting from temperature sensor enable, refer to @ref LL_ADC_SetCommonPathInternalCh()) */
-#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time
+ (starting from temperature sensor enable, refer to
+ @ref LL_ADC_SetCommonPathInternalCh()) */
+#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
+ time (starting from ADC enable, refer to
+ @ref LL_ADC_Enable()) */
/* Delay required between ADC end of calibration and ADC enable. */
/* Note: On this STM32 series, a minimum number of ADC clock cycles */
@@ -902,7 +1145,8 @@
/* equivalent number of CPU cycles, by taking into account */
/* ratio of CPU clock versus ADC clock prescalers. */
/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration and ADC enable */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration
+ and ADC enable */
/**
* @}
@@ -1097,7 +1341,8 @@
* (1) On STM32G0, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
- * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
+ connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
@@ -1320,8 +1565,9 @@
* @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
- (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
+ (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
+ & LL_ADC_AWD_THRESHOLD_LOW)
/**
* @brief Helper macro to select the ADC common instance
@@ -1547,12 +1793,15 @@
* @note ADC measurement data must correspond to a resolution of 12 bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 12 bits.
- * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
+ (unit: uV/DegCelsius).
* On STM32G0, refer to device datasheet parameter "Avg_Slope".
- * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
- * On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
- * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
- * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
+ (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32G0, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
+ (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
* This parameter can be one of the following values:
@@ -1638,7 +1887,8 @@
* @}
*/
-/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
+ * ADC instances
* @{
*/
@@ -2806,7 +3056,8 @@
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->CHSELR,
ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
- ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
/**
@@ -3572,8 +3823,9 @@
/* Retrieve sampling time bit corresponding to the selected channel */
/* and shift it to position 0. */
uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
- >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) &
- 0x1FUL));
+ >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
+ & 0x1FUL));
/* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
@@ -3671,7 +3923,8 @@
}
else
{
- preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
+ preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
+ ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
}
MODIFY_REG(*preg,
@@ -3759,8 +4012,10 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
+ ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
+ * ADC_AWD_CR12_REGOFFSETGAP_VAL));
uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
@@ -3882,7 +4137,12 @@
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
+ (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+ >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+ >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
+ );
MODIFY_REG(*preg,
ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
@@ -3961,8 +4221,10 @@
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
- (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
- + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+ (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+ >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+ >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
@@ -4005,8 +4267,10 @@
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
- (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
- + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+ (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+ >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+ + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+ >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
return (uint32_t)(READ_BIT(*preg,
(AWDThresholdsHighLow | ADC_AWD1TR_LT1))
diff --git a/Inc/stm32g0xx_ll_bus.h b/Inc/stm32g0xx_ll_bus.h
index 7558e9c..4309003 100644
--- a/Inc/stm32g0xx_ll_bus.h
+++ b/Inc/stm32g0xx_ll_bus.h
@@ -619,7 +619,6 @@
* APBRSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
* APBRSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
* APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset\n
- * APBRSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n
* APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
* APBRSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
* APBRSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
@@ -649,7 +648,6 @@
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
@@ -687,7 +685,6 @@
* APBRSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
* APBRSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
* APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset\n
- * APBRSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n
* APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
* APBRSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
* APBRSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
@@ -717,7 +714,6 @@
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
diff --git a/Inc/stm32g0xx_ll_lpuart.h b/Inc/stm32g0xx_ll_lpuart.h
index ffc13d7..23f723a 100644
--- a/Inc/stm32g0xx_ll_lpuart.h
+++ b/Inc/stm32g0xx_ll_lpuart.h
@@ -1398,7 +1398,8 @@
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @retval Baud Rate
*/
-__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
+ uint32_t PrescalerValue)
{
uint32_t lpuartdiv;
uint32_t brrresult;
diff --git a/Inc/stm32g0xx_ll_ucpd.h b/Inc/stm32g0xx_ll_ucpd.h
index 89f9534..29d5ae2 100644
--- a/Inc/stm32g0xx_ll_ucpd.h
+++ b/Inc/stm32g0xx_ll_ucpd.h
@@ -1790,7 +1790,7 @@
/**
* @brief Read data
- * @rmtoll TXDR RXDATA LL_UCPD_ReadData
+ * @rmtoll RXDR RXDATA LL_UCPD_ReadData
* @param UCPDx UCPD Instance
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
*/
diff --git a/Inc/stm32g0xx_ll_usart.h b/Inc/stm32g0xx_ll_usart.h
index 0ed00e2..69405e8 100644
--- a/Inc/stm32g0xx_ll_usart.h
+++ b/Inc/stm32g0xx_ll_usart.h
@@ -650,7 +650,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
@@ -689,7 +689,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
}
@@ -728,7 +728,7 @@
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
}
@@ -767,7 +767,7 @@
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
-__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
}
@@ -838,7 +838,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
@@ -916,7 +916,7 @@
* @arg @ref LL_USART_DIRECTION_TX
* @arg @ref LL_USART_DIRECTION_TX_RX
*/
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
@@ -950,7 +950,7 @@
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
*/
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
@@ -977,7 +977,7 @@
* @arg @ref LL_USART_WAKEUP_IDLELINE
* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
*/
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
}
@@ -1008,7 +1008,7 @@
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
*/
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
}
@@ -1041,7 +1041,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
@@ -1068,7 +1068,7 @@
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
*/
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
}
@@ -1100,7 +1100,7 @@
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
*/
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
}
@@ -1131,7 +1131,7 @@
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
}
@@ -1162,7 +1162,7 @@
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
}
@@ -1241,7 +1241,7 @@
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
*/
-__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
}
@@ -1280,7 +1280,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
}
@@ -1311,7 +1311,7 @@
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
*/
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
}
@@ -1372,7 +1372,7 @@
* @arg @ref LL_USART_TXRX_STANDARD
* @arg @ref LL_USART_TXRX_SWAPPED
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
}
@@ -1399,7 +1399,7 @@
* @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
}
@@ -1426,7 +1426,7 @@
* @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
}
@@ -1455,7 +1455,7 @@
* @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
*/
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
}
@@ -1486,7 +1486,7 @@
* @arg @ref LL_USART_BITORDER_LSBFIRST
* @arg @ref LL_USART_BITORDER_MSBFIRST
*/
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
}
@@ -1525,7 +1525,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
}
@@ -1593,7 +1593,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
}
@@ -1637,7 +1637,7 @@
* @param USARTx USART Instance
* @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
*/
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
@@ -1650,7 +1650,7 @@
* @arg @ref LL_USART_ADDRESS_DETECT_4B
* @arg @ref LL_USART_ADDRESS_DETECT_7B
*/
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
}
@@ -1739,7 +1739,7 @@
* @arg @ref LL_USART_HWCONTROL_CTS
* @arg @ref LL_USART_HWCONTROL_RTS_CTS
*/
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
@@ -1772,7 +1772,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
}
@@ -1805,7 +1805,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
@@ -1838,7 +1838,7 @@
* @arg @ref LL_USART_WAKEUP_ON_STARTBIT
* @arg @ref LL_USART_WAKEUP_ON_RXNE
*/
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
}
@@ -1926,7 +1926,7 @@
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
uint32_t usartdiv;
@@ -1975,7 +1975,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
*/
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
}
@@ -1998,7 +1998,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
}
@@ -2045,7 +2045,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
}
@@ -2076,7 +2076,7 @@
* @arg @ref LL_USART_IRDA_POWER_NORMAL
* @arg @ref LL_USART_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
}
@@ -2105,7 +2105,7 @@
* @param USARTx USART Instance
* @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
@@ -2152,7 +2152,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
}
@@ -2191,7 +2191,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
}
@@ -2223,7 +2223,7 @@
* @param USARTx USART Instance
* @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
}
@@ -2252,7 +2252,7 @@
* @param USARTx USART Instance
* @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
@@ -2281,7 +2281,7 @@
* @param USARTx USART Instance
* @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
}
@@ -2328,7 +2328,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
@@ -2374,7 +2374,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
}
@@ -2416,7 +2416,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
}
@@ -2455,7 +2455,7 @@
* @arg @ref LL_USART_LINBREAK_DETECT_10B
* @arg @ref LL_USART_LINBREAK_DETECT_11B
*/
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
}
@@ -2494,7 +2494,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
}
@@ -2529,7 +2529,7 @@
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
@@ -2556,7 +2556,7 @@
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
@@ -2595,7 +2595,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
@@ -2626,7 +2626,7 @@
* @arg @ref LL_USART_DE_POLARITY_HIGH
* @arg @ref LL_USART_DE_POLARITY_LOW
*/
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
}
@@ -2929,7 +2929,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
@@ -2940,7 +2940,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
@@ -2951,7 +2951,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
@@ -2962,7 +2962,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
@@ -2973,7 +2973,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
@@ -2989,7 +2989,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
}
@@ -3000,7 +3000,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
@@ -3016,7 +3016,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
}
@@ -3029,7 +3029,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
}
@@ -3042,7 +3042,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
@@ -3055,7 +3055,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
@@ -3066,7 +3066,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
}
@@ -3079,7 +3079,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
}
@@ -3092,7 +3092,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
}
@@ -3105,7 +3105,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
}
@@ -3118,7 +3118,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
}
@@ -3129,7 +3129,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
@@ -3140,7 +3140,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
@@ -3151,7 +3151,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
@@ -3162,7 +3162,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
@@ -3175,7 +3175,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
@@ -3186,7 +3186,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
@@ -3197,7 +3197,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
@@ -3210,7 +3210,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
}
@@ -3223,7 +3223,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
}
@@ -3234,7 +3234,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
@@ -3247,7 +3247,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
}
@@ -3260,7 +3260,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
}
@@ -3892,7 +3892,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
@@ -3908,7 +3908,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
}
@@ -3919,7 +3919,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
@@ -3935,7 +3935,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
}
@@ -3946,7 +3946,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
@@ -3957,7 +3957,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
@@ -3968,7 +3968,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
}
@@ -3981,7 +3981,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
}
@@ -3994,7 +3994,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
}
@@ -4007,7 +4007,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
}
@@ -4020,7 +4020,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
}
@@ -4031,7 +4031,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
@@ -4044,7 +4044,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
@@ -4057,7 +4057,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
@@ -4070,7 +4070,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
}
@@ -4083,7 +4083,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
}
@@ -4096,7 +4096,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
}
@@ -4137,7 +4137,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
@@ -4170,7 +4170,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
@@ -4203,7 +4203,7 @@
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
@@ -4218,7 +4218,7 @@
* @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
@@ -4250,7 +4250,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
@@ -4261,7 +4261,7 @@
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x1FF
*/
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
{
return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
}
@@ -4369,10 +4369,10 @@
/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
/**
* @}
diff --git a/Inc/stm32g0xx_ll_usb.h b/Inc/stm32g0xx_ll_usb.h
index 54ab823..fc419a7 100644
--- a/Inc/stm32g0xx_ll_usb.h
+++ b/Inc/stm32g0xx_ll_usb.h
@@ -70,13 +70,13 @@
HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
+ HC_ACK,
HC_NAK,
HC_NYET,
HC_STALL,
HC_XACTERR,
HC_BBLERR,
- HC_DATATGLERR,
- HC_ACK
+ HC_DATATGLERR
} USB_DRD_HCStateTypeDef;
diff --git a/README.md b/README.md
index 2060cb0..19c7bcf 100644
--- a/README.md
+++ b/README.md
@@ -33,4 +33,6 @@
## Troubleshooting
-Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
+If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32g0xx_hal_driver/issues/new).
+
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index c02a39a..ee4a9a8 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -39,11 +39,69 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.4.4 / 01-April-2022</label>
+<input type="checkbox" id="collapse-section8" checked aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.4.5 / 10-June-2022</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<ul>
+<li>General updates to fix known defects and enhancements implementation.</li>
+<li><p>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</p></li>
+<li><strong>HAL/LL Drivers</strong> updates
+<ul>
+<li><strong>HAL CEC</strong> updates
+<ul>
+<li>Better performance by removing multiple volatile reads or writes in interrupt handler.</li>
+</ul></li>
+<li><strong>HAL RTC</strong> updates
+<ul>
+<li>Check if the RTC calendar has been previously initialized before entering Initialization mode.</li>
+</ul></li>
+<li><strong>HAL I2C</strong> updates
+<ul>
+<li>I2C_IsErrorOccurred does not return error if timeout is detected.</li>
+<li>The ADDRF flag is cleared too early when the restart is received but the direction has changed</li>
+</ul></li>
+<li><strong>HAL UART</strong> updates
+<ul>
+<li>Removal of HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs</li>
+</ul></li>
+<li><strong>HAL USB</strong> updates
+<ul>
+<li>HAL: HCD: add missing call to MspDeInit API during HCD DeInit</li>
+</ul></li>
+</ul></li>
+</ul>
+<h2 id="known-limitations">Known limitations</h2>
+<ul>
+<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
+</ul>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31</li>
+<li>STM32CubeIDE toolchain (gcc9_2020_q2_update) v1.7.0</li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<p>Supported Devices:</p>
+<ul>
+<li>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</li>
+<li>STM32G061xx, STM32G051xx, STM32G050xx</li>
+<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
+<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
+</ul>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+<h2 id="dependencies">Dependencies</h2>
+<p><br />
+</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.4.4 / 01-April-2022</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-1">Maintenance release</h3>
+<ul>
<li><p>General updates to fix known defects and enhancements implementation.</p></li>
<li><strong>HAL/LL Drivers</strong> updates
<ul>
@@ -176,17 +234,17 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations">Known limitations</h2>
+<h2 id="known-limitations-1">Known limitations</h2>
<ul>
<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
</ul>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31</li>
<li>STM32CubeIDE toolchain (gcc9_2020_q2_update) v1.7.0</li>
</ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</li>
@@ -194,9 +252,9 @@
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
</ul>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies">Dependencies</h2>
+<h2 id="dependencies-1">Dependencies</h2>
<p><br />
</p>
</div>
@@ -204,8 +262,8 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.4.3 / 15-December-2021</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance release</h3>
+<h2 id="main-changes-2">Main Changes</h2>
+<h3 id="maintenance-release-2">Maintenance release</h3>
<ul>
<li><strong>HAL/LL Drivers</strong> updates
<ul>
@@ -218,17 +276,17 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-1">Known limitations</h2>
+<h2 id="known-limitations-2">Known limitations</h2>
<ul>
<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
</ul>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31</li>
<li>STM32CubeIDE toolchain v1.7.0</li>
</ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</li>
@@ -237,7 +295,7 @@
<li>STM32G041xx, STM32G031xx, STM32G030xx ## Backward Compatibility</li>
</ul>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-1">Dependencies</h2>
+<h2 id="dependencies-2">Dependencies</h2>
<p><br />
</p>
</div>
@@ -245,8 +303,8 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.2 / 17-Juin-2021</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance release</h3>
+<h2 id="main-changes-3">Main Changes</h2>
+<h3 id="maintenance-release-3">Maintenance release</h3>
<ul>
<li><p>General updates to fix known defects and enhancements implementation.</p></li>
<li><p><strong>HAL/LL Drivers</strong> updates</p></li>
@@ -376,17 +434,17 @@
<li>Add fix transfer complete for IN Interrupt transaction in single buffer mode.</li>
</ul></li>
</ul>
-<h2 id="known-limitations-2">Known limitations</h2>
+<h2 id="known-limitations-3">Known limitations</h2>
<ul>
<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
</ul>
-<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31</li>
<li>STM32CubeIDE toolchain v1.7.0</li>
</ul>
-<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</li>
@@ -395,7 +453,7 @@
<li>STM32G041xx, STM32G031xx, STM32G030xx ## Backward Compatibility</li>
</ul>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-2">Dependencies</h2>
+<h2 id="dependencies-3">Dependencies</h2>
<p><br />
</p>
</div>
@@ -403,7 +461,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.4.1 / 25-February-2021</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<h3 id="patch-release">Patch release</h3>
<p>Patch release of <strong>HAL and Low Layer</strong> drivers</p>
<p><strong>Additional features</strong></p>
@@ -419,17 +477,17 @@
</tr>
</tbody>
</table>
-<h2 id="known-limitations-3">Known limitations</h2>
+<h2 id="known-limitations-4">Known limitations</h2>
<ul>
<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
</ul>
-<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29</li>
<li>STM32CubeIDE toolchain v1.5.0</li>
</ul>
-<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</li>
@@ -437,9 +495,9 @@
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
</ul>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-3">Dependencies</h2>
+<h2 id="dependencies-4">Dependencies</h2>
<p><br />
</p>
</div>
@@ -447,7 +505,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.0 / 29-October-2020</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="maintenance-release-and-product-update">Maintenance release and Product Update</h3>
<p><strong>Official release</strong> of HAL and Low layers drivers introducing <strong>STM32G0C1xx/STM32G0B1xx/STM32G0B0xx</strong> devices and <strong>STM32G061xx/STM32G051xx/STM32G050xx</strong> devices.</p>
<p>Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.</p>
@@ -914,17 +972,17 @@
</tr>
</tbody>
</table>
-<h2 id="known-limitations-4">Known limitations</h2>
+<h2 id="known-limitations-5">Known limitations</h2>
<ul>
<li>USB HAL limitation: Double buffer mode is not functional with isochronous data transfers in host mode.</li>
</ul>
-<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29</li>
<li>STM32CubeIDE toolchain v1.5.0</li>
</ul>
-<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li><strong>STM32G0C1xx, STM32G0B1xx, STM32G0B0xx</strong></li>
@@ -932,9 +990,9 @@
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
</ul>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-4">Dependencies</h2>
+<h2 id="dependencies-5">Dependencies</h2>
<p><br />
</p>
</div>
@@ -942,8 +1000,8 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0 / 25-June-2019</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance release</h3>
+<h2 id="main-changes-6">Main Changes</h2>
+<h3 id="maintenance-release-4">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32G041xx/STM32G031xx/STM32G030xx and STM32G081xx/STM32G071xx/STM32G070xx devices.</p>
<p><strong>Fixed bugs list</strong></p>
<table>
@@ -1012,27 +1070,27 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-6">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-6">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li>STM32G041xx, STM32G031xx, STM32G030xx</li>
</ul>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-5">Dependencies</h2>
+<h2 id="dependencies-6">Dependencies</h2>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<h3 id="maintenance-release-and-product-update-1">Maintenance release and product update</h3>
<p>First release of HAL and Low layers drivers to introduce support of <strong>STM32G041xx/STM32G031xx/STM32G030xx devices</strong>.</p>
<p>Maintenance release of HAL and Low layers drivers supporting STM32G081xx/STM32G071xx/STM32G070xx devices.</p>
@@ -1119,27 +1177,27 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-6">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-7">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards-6">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-7">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
<li>STM32G081xx, STM32G071xx, STM32G070xx</li>
<li><strong>STM32G041xx, STM32G031xx, STM32G030xx</strong></li>
</ul>
-<h2 id="backward-compatibility-4">Backward Compatibility</h2>
+<h2 id="backward-compatibility-5">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-6">Dependencies</h2>
+<h2 id="dependencies-7">Dependencies</h2>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<h3 id="maintenance-release-and-product-update-2">Maintenance release and product update</h3>
<p>Maintenance release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx devices.</p>
<p><strong>Additional features</strong></p>
@@ -1228,24 +1286,6 @@
</tr>
</tbody>
</table>
-<h2 id="supported-devices-and-boards-7">Supported Devices and boards</h2>
-<p>Supported Devices:</p>
-<ul>
-<li>STM32G0<strong>81</strong>xx</li>
-<li>STM32G0<strong>71</strong>xx</li>
-<li>STM32G0<strong>70</strong>xx</li>
-</ul>
-<h2 id="backward-compatibility-5">Backward Compatibility</h2>
-<p>This release is compatible with the previous versions.</p>
-<h2 id="dependencies-7">Dependencies</h2>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 26-October-2018</label>
-<div>
-<h2 id="main-changes-8">Main Changes</h2>
-<h3 id="first-release">First release</h3>
-<p>First official release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx</p>
<h2 id="supported-devices-and-boards-8">Supported Devices and boards</h2>
<p>Supported Devices:</p>
<ul>
@@ -1253,9 +1293,27 @@
<li>STM32G0<strong>71</strong>xx</li>
<li>STM32G0<strong>70</strong>xx</li>
</ul>
+<h2 id="backward-compatibility-6">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-8">Dependencies</h2>
</div>
</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 26-October-2018</label>
+<div>
+<h2 id="main-changes-9">Main Changes</h2>
+<h3 id="first-release">First release</h3>
+<p>First official release of HAL and Low layers drivers to support STM32G071xx/STM32G081xx/STM32G070xx</p>
+<h2 id="supported-devices-and-boards-9">Supported Devices and boards</h2>
+<p>Supported Devices:</p>
+<ul>
+<li>STM32G0<strong>81</strong>xx</li>
+<li>STM32G0<strong>71</strong>xx</li>
+<li>STM32G0<strong>70</strong>xx</li>
+</ul>
+<h2 id="dependencies-9">Dependencies</h2>
+</div>
+</div>
</div>
</div>
<footer class="sticky">
diff --git a/Src/stm32g0xx_hal.c b/Src/stm32g0xx_hal.c
index 708aee5..7e4ffcf 100644
--- a/Src/stm32g0xx_hal.c
+++ b/Src/stm32g0xx_hal.c
@@ -57,7 +57,7 @@
*/
#define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
-#define __STM32G0xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
+#define __STM32G0xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32g0xx_hal_adc.c b/Src/stm32g0xx_hal_adc.c
index 9d55507..778eecc 100644
--- a/Src/stm32g0xx_hal_adc.c
+++ b/Src/stm32g0xx_hal_adc.c
@@ -665,8 +665,9 @@
/* - Set sequencer scan length by clearing ranks above maximum rank */
/* and do not modify other ranks value. */
MODIFY_REG(hadc->Instance->CHSELR,
- ADC_CHSELR_SQ_ALL,
- (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks)
+ ADC_CHSELR_SQ_ALL,
+ (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL))
+ | (hadc->ADCGroupRegularSequencerRanks)
);
}
@@ -1368,9 +1369,12 @@
* @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
- * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
- * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
- * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+ * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all
+ * STM32 series)
+ * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all
+ * STM32 series)
+ * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all
+ * STM32 series)
* @arg @ref ADC_OVR_EVENT ADC Overrun event
* @param Timeout Timeout value in millisecond.
* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
@@ -2258,7 +2262,8 @@
wait_loop_index--;
}
}
- else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
@@ -2418,7 +2423,8 @@
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
- __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR));
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
@@ -2476,7 +2482,9 @@
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
- LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
+ pAnalogWDGConfig->WatchdogNumber,
+ LL_ADC_AWD_ALL_CHANNELS_REG);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
@@ -2712,14 +2720,16 @@
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
- if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
+ if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ != 0UL)
{
/* Delay for temperature sensor buffer stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL)
+ * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
diff --git a/Src/stm32g0xx_hal_cec.c b/Src/stm32g0xx_hal_cec.c
index f926434..2ae97e4 100644
--- a/Src/stm32g0xx_hal_cec.c
+++ b/Src/stm32g0xx_hal_cec.c
@@ -776,13 +776,13 @@
{
/* save interrupts register for further error or interrupts handling purposes */
- uint32_t reg;
- reg = hcec->Instance->ISR;
+ uint32_t itflag;
+ itflag = hcec->Instance->ISR;
/* ----------------------------Arbitration Lost Management----------------------------------*/
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
- if ((reg & CEC_FLAG_ARBLST) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
{
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
@@ -790,7 +790,7 @@
/* ----------------------------Rx Management----------------------------------*/
/* CEC RX byte received interrupt ---------------------------------------------------*/
- if ((reg & CEC_FLAG_RXBR) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
{
/* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
@@ -802,7 +802,7 @@
}
/* CEC RX end received interrupt ---------------------------------------------------*/
- if ((reg & CEC_FLAG_RXEND) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
{
/* clear IT */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
@@ -821,7 +821,7 @@
/* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
- if ((reg & CEC_FLAG_TXBR) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
{
--hcec->TxXferCount;
if (hcec->TxXferCount == 0U)
@@ -837,7 +837,7 @@
}
/* CEC TX end interrupt ------------------------------------------------*/
- if ((reg & CEC_FLAG_TXEND) != 0U)
+ if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
{
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
@@ -855,21 +855,21 @@
}
/* ----------------------------Rx/Tx Error Management----------------------------------*/
- if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
+ if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
{
- hcec->ErrorCode = reg;
+ hcec->ErrorCode = itflag;
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
- if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
+ if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
{
hcec->Init.RxBuffer -= hcec->RxXferSize;
hcec->RxXferSize = 0U;
hcec->RxState = HAL_CEC_STATE_READY;
}
- else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
+ else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
{
/* Set the CEC state ready to be able to start again the process */
hcec->gState = HAL_CEC_STATE_READY;
diff --git a/Src/stm32g0xx_hal_hcd.c b/Src/stm32g0xx_hal_hcd.c
index f8aaac9..90ed5c7 100644
--- a/Src/stm32g0xx_hal_hcd.c
+++ b/Src/stm32g0xx_hal_hcd.c
@@ -473,6 +473,12 @@
{
uint8_t idx;
+ /* Check the HCD handle allocation */
+ if (hhcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Host Port State */
hhcd->HostState = HCD_HCD_STATE_DISCONNECTED;
@@ -488,6 +494,23 @@
/* reset Ep0 Pma allocation state */
hhcd->ep0_PmaAllocState = 0U;
+ hhcd->State = HAL_HCD_STATE_BUSY;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ if (hhcd->MspDeInitCallback == NULL)
+ {
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hhcd->MspDeInitCallback(hhcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC. */
+ HAL_HCD_MspDeInit(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+ hhcd->State = HAL_HCD_STATE_RESET;
+
return HAL_OK;
}
@@ -2555,7 +2578,7 @@
* @param mps Channel Max Packet Size
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint16_t ch_kind, uint16_t mps)
{
uint16_t pma_addr0;
@@ -2658,9 +2681,10 @@
* @param ch_num Channel number
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status;
+
#if (USE_USB_DOUBLE_BUFFER == 1U)
uint8_t Err = 0U;
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
@@ -2673,9 +2697,9 @@
{
status = HAL_HCD_PMAFree(hhcd, hc->pmaadress, hc->max_packet);
}
-#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* Double buffer */
{
+#if (USE_USB_DOUBLE_BUFFER == 1U)
status = HAL_HCD_PMAFree(hhcd, hc->pmaaddr0, hc->max_packet);
if (status != HAL_OK)
{
@@ -2692,8 +2716,10 @@
{
return HAL_ERROR;
}
- }
+#else
+ status = HAL_ERROR;
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+ }
return status;
}
diff --git a/Src/stm32g0xx_hal_i2c.c b/Src/stm32g0xx_hal_i2c.c
index c557e49..4a5093e 100644
--- a/Src/stm32g0xx_hal_i2c.c
+++ b/Src/stm32g0xx_hal_i2c.c
@@ -438,10 +438,14 @@
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
@@ -707,6 +711,8 @@
/**
* @brief Register a User I2C Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be registered
@@ -737,8 +743,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -827,14 +831,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
/**
* @brief Unregister an I2C Callback
* I2C callback is redirected to the weak predefined callback
+ * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be unregistered
@@ -857,9 +861,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
switch (CallbackID)
@@ -947,8 +948,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -971,8 +970,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -987,8 +984,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -1003,9 +998,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
@@ -1019,8 +1011,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -2647,9 +2637,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2669,9 +2656,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2680,30 +2664,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2741,9 +2724,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2763,9 +2743,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2774,29 +2751,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2809,7 +2786,7 @@
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+ I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
return HAL_OK;
}
@@ -2833,8 +2810,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2856,9 +2831,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2867,28 +2839,36 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
if (hi2c->hdmatx != NULL)
{
@@ -2923,12 +2903,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2936,11 +2912,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -2980,8 +2956,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -3003,9 +2977,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -3014,25 +2985,35 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
if (hi2c->hdmarx != NULL)
@@ -3068,11 +3049,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3080,11 +3058,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -3327,6 +3305,10 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -3773,6 +3755,9 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
+
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3832,7 +3817,8 @@
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -3869,6 +3855,8 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -4010,7 +3998,8 @@
return HAL_ERROR;
}
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4050,6 +4039,9 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
+
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -4109,7 +4101,8 @@
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4146,6 +4139,8 @@
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -4287,7 +4282,8 @@
return HAL_ERROR;
}
- if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4879,6 +4875,143 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ if (hi2c->Memaddress == 0xFFFFFFFFU)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -5160,6 +5293,145 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ /* Enable only Error interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Prepare the new XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -6585,14 +6857,11 @@
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ error_code |=HAL_I2C_ERROR_TIMEOUT;
status = HAL_ERROR;
+
+ break;
}
}
}
@@ -6764,6 +7033,12 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
diff --git a/Src/stm32g0xx_hal_irda.c b/Src/stm32g0xx_hal_irda.c
index 00d47e2..fbee134 100644
--- a/Src/stm32g0xx_hal_irda.c
+++ b/Src/stm32g0xx_hal_irda.c
@@ -1401,7 +1401,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (hirda->Init.Parity != IRDA_PARITY_NONE)
- {
+ {
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -2294,7 +2294,7 @@
* the configuration information for the specified IRDA module.
* @retval HAL state
*/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
uint32_t temp1;
@@ -2311,7 +2311,7 @@
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
}
diff --git a/Src/stm32g0xx_hal_rcc.c b/Src/stm32g0xx_hal_rcc.c
index 4b19a0c..656db75 100644
--- a/Src/stm32g0xx_hal_rcc.c
+++ b/Src/stm32g0xx_hal_rcc.c
@@ -680,14 +680,20 @@
}
/* Configure the main PLL clock source, multiplication and division factors. */
+#if defined(RCC_PLLQ_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PLLM,
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
-#if defined(RCC_PLLQ_SUPPORT)
RCC_OscInitStruct->PLL.PLLQ,
-#endif /* RCC_PLLQ_SUPPORT */
RCC_OscInitStruct->PLL.PLLR);
+#else /* !RCC_PLLQ_SUPPORT */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLR);
+#endif /* RCC_PLLQ_SUPPORT */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
diff --git a/Src/stm32g0xx_hal_rtc.c b/Src/stm32g0xx_hal_rtc.c
index 6cde434..515837d 100644
--- a/Src/stm32g0xx_hal_rtc.c
+++ b/Src/stm32g0xx_hal_rtc.c
@@ -257,76 +257,88 @@
assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
- if(hrtc->State == HAL_RTC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hrtc->Lock = HAL_UNLOCKED;
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
- /* Process TAMP peripheral offset from RTC one */
- hrtc->TampOffset = (TAMP_BASE - RTC_BASE);
+ /* Process TAMP peripheral offset from RTC one */
+ hrtc->TampOffset = (TAMP_BASE - RTC_BASE);
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
- hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
- hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
- hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
- hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
- hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
#if defined(TAMP_CR1_TAMP3E)
- hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
#endif /* TAMP_CR1_TAMP3E */
- hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /*!< Legacy weak InternalTamper3EventCallback */
- hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; /*!< Legacy weak InternalTamper4EventCallback */
- hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /*!< Legacy weak InternalTamper5EventCallback */
- hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; /*!< Legacy weak InternalTamper6EventCallback */
+ hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /*!< Legacy weak InternalTamper3EventCallback */
+ hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; /*!< Legacy weak InternalTamper4EventCallback */
+ hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /*!< Legacy weak InternalTamper5EventCallback */
+ hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; /*!< Legacy weak InternalTamper6EventCallback */
- if(hrtc->MspInitCallback == NULL)
- {
- hrtc->MspInitCallback = HAL_RTC_MspInit;
- }
- /* Init the low level hardware */
- hrtc->MspInitCallback(hrtc);
+ if(hrtc->MspInitCallback == NULL)
+ {
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ }
- if(hrtc->MspDeInitCallback == NULL)
- {
- hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
- }
+ /* Init the low level hardware */
+ hrtc->MspInitCallback(hrtc);
+
+ if(hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
#else
- /* Initialize RTC MSP */
- HAL_RTC_MspInit(hrtc);
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
- }
+ }
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Enter Initialization mode */
- status = RTC_EnterInitMode(hrtc);
- if(status == HAL_OK)
+ /* Check whether the calendar needs to be initialized */
+ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
- /* Set RTC_CR register */
- hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the RTC PRER */
- hrtc->Instance->PRER = (hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Exit Initialization mode */
- status = RTC_ExitInitMode(hrtc);
+ if(status == HAL_OK)
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
if (status == HAL_OK)
{
hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU |RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
}
- }
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ }
+ else
+ {
+ /* The calendar is already initialized */
+ status = HAL_OK;
+ }
if (status == HAL_OK)
{
diff --git a/Src/stm32g0xx_hal_smartcard.c b/Src/stm32g0xx_hal_smartcard.c
index c4f3e1e..acc7987 100644
--- a/Src/stm32g0xx_hal_smartcard.c
+++ b/Src/stm32g0xx_hal_smartcard.c
@@ -2276,7 +2276,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle state
*/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
uint32_t temp1;
@@ -2293,7 +2293,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle Error Code
*/
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard)
{
return hsmartcard->ErrorCode;
}
diff --git a/Src/stm32g0xx_hal_smbus.c b/Src/stm32g0xx_hal_smbus.c
index cf7b765..ab7837e 100644
--- a/Src/stm32g0xx_hal_smbus.c
+++ b/Src/stm32g0xx_hal_smbus.c
@@ -584,6 +584,9 @@
/**
* @brief Register a User SMBUS Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be registered
@@ -613,9 +616,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -691,14 +691,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
/**
* @brief Unregister an SMBUS Callback
* SMBUS callback is redirected to the weak predefined callback
+ * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be unregistered
@@ -719,9 +720,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -797,8 +795,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -822,8 +818,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
@@ -838,8 +832,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -854,9 +846,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
@@ -870,8 +859,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
diff --git a/Src/stm32g0xx_hal_uart.c b/Src/stm32g0xx_hal_uart.c
index 40da323..a7703e7 100644
--- a/Src/stm32g0xx_hal_uart.c
+++ b/Src/stm32g0xx_hal_uart.c
@@ -656,6 +656,7 @@
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -1148,8 +1149,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
@@ -1171,8 +1170,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@@ -1254,8 +1251,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1282,8 +1277,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@@ -1351,8 +1344,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1374,8 +1365,6 @@
huart->TxISR = UART_TxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the TX FIFO threshold interrupt */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
}
@@ -1391,8 +1380,6 @@
huart->TxISR = UART_TxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
}
@@ -1441,8 +1428,6 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1500,8 +1485,6 @@
}
}
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1529,8 +1512,6 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY;
@@ -1540,8 +1521,6 @@
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
- __HAL_UNLOCK(huart);
-
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
@@ -1592,8 +1571,6 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1625,8 +1602,6 @@
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
- __HAL_LOCK(huart);
-
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX))
{
@@ -1644,8 +1619,6 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1656,8 +1629,6 @@
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
@@ -1679,8 +1650,6 @@
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -2537,6 +2506,11 @@
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
}
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
@@ -2570,6 +2544,11 @@
huart->RxISR = NULL;
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
@@ -3437,6 +3416,7 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -3546,8 +3526,6 @@
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
{
@@ -3567,8 +3545,6 @@
huart->RxISR = UART_RxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
{
@@ -3621,15 +3597,12 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->RxState to ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR;
}
}
- __HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
@@ -3774,6 +3747,10 @@
}
}
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3808,6 +3785,10 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Half Transfer */
+ huart->RxEventType = HAL_UART_RXEVENT_HT;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4268,6 +4249,9 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4283,6 +4267,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4347,6 +4332,9 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4362,6 +4350,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4477,6 +4466,9 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4492,6 +4484,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4627,6 +4620,9 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4642,6 +4638,7 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
diff --git a/Src/stm32g0xx_hal_uart_ex.c b/Src/stm32g0xx_hal_uart_ex.c
index abaa8bd..e40c2e6 100644
--- a/Src/stm32g0xx_hal_uart_ex.c
+++ b/Src/stm32g0xx_hal_uart_ex.c
@@ -740,11 +740,10 @@
}
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
@@ -768,8 +767,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* Initialize output number of received elements */
*RxLen = 0U;
@@ -786,6 +783,7 @@
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U)
{
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
@@ -877,10 +875,9 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_IT(huart, pData, Size);
@@ -955,10 +952,9 @@
}
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_DMA(huart, pData, Size);
@@ -989,6 +985,36 @@
}
/**
+ * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+ * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+ * of reception process is provided to application through calls of Rx Event callback (either default one
+ * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+ * to Rx Event callback execution.
+ * @note This function is expected to be called within the user implementation of Rx Event Callback,
+ * in order to provide the accurate value :
+ * In Interrupt Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one)
+ * In DMA Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one).
+ * In DMA mode, RxEvent callback could be called several times;
+ * When DMA is configured in Normal Mode, HT event does not stop Reception process;
+ * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+ * @param huart UART handle.
+ * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+ */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+{
+ /* Return Rx Event type value, as stored in UART handle */
+ return(huart->RxEventType);
+}
+
+/**
* @}
*/
diff --git a/Src/stm32g0xx_hal_usart.c b/Src/stm32g0xx_hal_usart.c
index 86bd320..2f4e5a2 100644
--- a/Src/stm32g0xx_hal_usart.c
+++ b/Src/stm32g0xx_hal_usart.c
@@ -857,9 +857,10 @@
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pRxData.
* @param husart USART handle.
* @param pRxData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
@@ -983,9 +984,10 @@
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
- * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
+ * (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pTxData and pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
@@ -1147,9 +1149,10 @@
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
- * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+ * address of user data buffer containing data to be sent, should be aligned on a half word frontier
+ * (16 bits) (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pTxData.
* @param husart USART handle.
* @param pTxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be sent.
@@ -1245,9 +1248,10 @@
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
- * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * address of user data buffer for storing data to be received, should be aligned on a half word frontier
+ * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pRxData.
* @param husart USART handle.
* @param pRxData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data elements (u8 or u16) to be received.
@@ -1373,9 +1377,10 @@
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
- * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
- * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
- * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
+ * (16 bits) (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
+ * use of specific alignment compilation directives or pragmas might be required to ensure
+ * proper alignment for pTxData and pRxData.
* @param husart USART handle.
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
@@ -2625,7 +2630,7 @@
* the configuration information for the specified USART.
* @retval USART handle state
*/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart)
{
return husart->State;
}
@@ -2636,7 +2641,7 @@
* the configuration information for the specified USART.
* @retval USART handle Error Code
*/
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
{
return husart->ErrorCode;
}
diff --git a/Src/stm32g0xx_ll_rcc.c b/Src/stm32g0xx_ll_rcc.c
index f994063..3575197 100644
--- a/Src/stm32g0xx_ll_rcc.c
+++ b/Src/stm32g0xx_ll_rcc.c
@@ -585,6 +585,7 @@
#endif /* LPUART2 */
else
{
+ /*nothing to do*/
}
return lpuart_frequency;
diff --git a/Src/stm32g0xx_ll_usart.c b/Src/stm32g0xx_ll_usart.c
index a26e58d..d77ee9a 100644
--- a/Src/stm32g0xx_ll_usart.c
+++ b/Src/stm32g0xx_ll_usart.c
@@ -125,7 +125,7 @@
* - SUCCESS: USART registers are de-initialized
* - ERROR: USART registers are not de-initialized
*/
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
{
ErrorStatus status = SUCCESS;
@@ -210,13 +210,13 @@
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
{
ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
#if !defined(RCC_CCIPR_USART3SEL)&&!defined(RCC_CCIPR_USART4SEL)||(!defined(RCC_CCIPR_USART2SEL))||!defined(RCC_CCIPR_USART5SEL)||!defined(RCC_CCIPR_USART6SEL)
LL_RCC_ClocksTypeDef RCC_Clocks;
-#endif
+#endif /* USART clock selection flags */
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
@@ -275,7 +275,7 @@
/* USART2 clock is PCLK */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
+#endif /* USART2 Clock selector flag */
}
#if defined(USART3)
else if (USARTx == USART3)
@@ -286,7 +286,7 @@
/* USART3 clock is PCLK */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
+#endif /* USART3 Clock selector flag */
}
#endif /* USART3 */
#if defined(USART4)
@@ -386,7 +386,7 @@
* to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32g0xx_ll_usb.c b/Src/stm32g0xx_ll_usb.c
index 47a0158..4356814 100644
--- a/Src/stm32g0xx_ll_usb.c
+++ b/Src/stm32g0xx_ll_usb.c
@@ -269,8 +269,16 @@
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure VALID status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ if (ep->num == 0U)
+ {
+ /* Configure VALID status for EP0 */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+ else
+ {
+ /* Configure NAK status for OUT Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
}
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
@@ -768,9 +776,9 @@
/**
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
- * @retval HAL status
+ * @retval USB Global Interrupt status
*/
-uint32_t USB_ReadInterrupts(USB_DRD_TypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_DRD_TypeDef *USBx)
{
uint32_t tmpreg;
