| /** |
| ****************************************************************************** |
| * @file stm32l0xx_ll_rcc.c |
| * @author MCD Application Team |
| * @brief RCC LL module driver. |
| ****************************************************************************** |
| * @attention |
| * |
| * <h2><center>© Copyright(c) 2016 STMicroelectronics. |
| * All rights reserved.</center></h2> |
| * |
| * This software component is licensed by ST under BSD 3-Clause license, |
| * the "License"; You may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at: |
| * opensource.org/licenses/BSD-3-Clause |
| * |
| ****************************************************************************** |
| */ |
| #if defined(USE_FULL_LL_DRIVER) |
| |
| /* Includes ------------------------------------------------------------------*/ |
| #include "stm32l0xx_ll_rcc.h" |
| #ifdef USE_FULL_ASSERT |
| #include "stm32_assert.h" |
| #else |
| #define assert_param(expr) ((void)0U) |
| #endif /* USE_FULL_ASSERT */ |
| /** @addtogroup STM32L0xx_LL_Driver |
| * @{ |
| */ |
| |
| #if defined(RCC) |
| |
| /** @defgroup RCC_LL RCC |
| * @{ |
| */ |
| |
| /* Private types -------------------------------------------------------------*/ |
| /* Private variables ---------------------------------------------------------*/ |
| |
| /* Private constants ---------------------------------------------------------*/ |
| /* Private macros ------------------------------------------------------------*/ |
| /** @addtogroup RCC_LL_Private_Macros |
| * @{ |
| */ |
| #if defined(RCC_CCIPR_USART1SEL) && defined(RCC_CCIPR_USART2SEL) |
| #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ |
| || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) |
| #elif defined(RCC_CCIPR_USART1SEL) && !defined(RCC_CCIPR_USART2SEL) |
| #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) |
| #else |
| #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) |
| #endif /* RCC_CCIPR_USART1SEL && RCC_CCIPR_USART2SEL */ |
| |
| #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) |
| |
| #if defined(RCC_CCIPR_I2C3SEL) |
| #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ |
| || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) |
| #else |
| #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) |
| #endif /* RCC_CCIPR_I2C3SEL */ |
| |
| #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) |
| |
| #if defined(USB) |
| #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) |
| #endif /* USB */ |
| |
| /** |
| * @} |
| */ |
| |
| /* Private function prototypes -----------------------------------------------*/ |
| /** @defgroup RCC_LL_Private_Functions RCC Private functions |
| * @{ |
| */ |
| uint32_t RCC_GetSystemClockFreq(void); |
| uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); |
| uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); |
| uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); |
| uint32_t RCC_PLL_GetFreqDomain_SYS(void); |
| /** |
| * @} |
| */ |
| |
| |
| /* Exported functions --------------------------------------------------------*/ |
| /** @addtogroup RCC_LL_Exported_Functions |
| * @{ |
| */ |
| |
| /** @addtogroup RCC_LL_EF_Init |
| * @{ |
| */ |
| |
| /** |
| * @brief Reset the RCC clock configuration to the default reset state. |
| * @note The default reset state of the clock configuration is given below: |
| * - MSI ON and used as system clock source |
| * - HSE, HSI and PLL OFF |
| * - AHB, APB1 and APB2 prescaler set to 1. |
| * - CSS, MCO OFF |
| * - All interrupts disabled |
| * @note This function doesn't modify the configuration of the |
| * - Peripheral clocks |
| * - LSI, LSE and RTC clocks |
| * @retval An ErrorStatus enumeration value: |
| * - SUCCESS: RCC registers are de-initialized |
| * - ERROR: not applicable |
| */ |
| ErrorStatus LL_RCC_DeInit(void) |
| { |
| uint32_t vl_mask; |
| |
| /* Set MSION bit */ |
| LL_RCC_MSI_Enable(); |
| |
| /* Insure MSIRDY bit is set before writing default MSIRANGE value */ |
| while (LL_RCC_MSI_IsReady() == 0U) |
| { |
| __NOP(); |
| } |
| |
| /* Set MSIRANGE default value */ |
| LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5); |
| /* Set MSITRIM bits to the reset value*/ |
| LL_RCC_MSI_SetCalibTrimming(0U); |
| |
| /* Set HSITRIM bits to the reset value*/ |
| LL_RCC_HSI_SetCalibTrimming(0x10U); |
| |
| /* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */ |
| vl_mask = 0xFFFFFFFFU; |
| CLEAR_BIT(vl_mask, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | \ |
| RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE); |
| LL_RCC_WriteReg(CFGR, vl_mask); |
| |
| /* Reset HSI, HSE, PLL */ |
| vl_mask = LL_RCC_ReadReg(CR); |
| #if defined(RCC_CR_HSIOUTEN) |
| CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ |
| RCC_CR_HSEON | RCC_CR_PLLON); |
| #else |
| CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ |
| RCC_CR_HSEON | RCC_CR_PLLON); |
| #endif |
| LL_RCC_WriteReg(CR, vl_mask); |
| /* Delay after an RCC peripheral clock */ |
| vl_mask = LL_RCC_ReadReg(CR); |
| |
| /* Reset HSEBYP bit */ |
| LL_RCC_HSE_DisableBypass(); |
| |
| /* Set RCC_CR_RTCPRE to 0b00*/ |
| CLEAR_BIT(vl_mask, RCC_CR_RTCPRE); |
| LL_RCC_WriteReg(CR, vl_mask); |
| |
| /* Insure PLL is disabled before to reset PLLSRC/PLLMUL/PLLDIV in CFGR register */ |
| while(LL_RCC_PLL_IsReady() != 0U) {}; |
| |
| /* Reset CFGR register */ |
| LL_RCC_WriteReg(CFGR, 0x00000000U); |
| |
| #if defined(RCC_HSI48_SUPPORT) |
| |
| /* Reset CRRCR register to disable HSI48 */ |
| #if defined(RCC_CRRCR_HSI48DIV6OUTEN) |
| CLEAR_BIT(RCC->CRRCR, (RCC_CRRCR_HSI48ON | RCC_CRRCR_HSI48DIV6OUTEN)); |
| #else |
| CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); |
| #endif |
| |
| #endif /*RCC_HSI48_SUPPORT*/ |
| |
| /* Disable all interrupts */ |
| LL_RCC_WriteReg(CIER, 0x00000000U); |
| |
| /* Disable all interrupt flags */ |
| LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); |
| |
| /* Clear reset flags */ |
| LL_RCC_ClearResetFlags(); |
| |
| return SUCCESS; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup RCC_LL_EF_Get_Freq |
| * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
| * and different peripheral clocks available on the device. |
| * @note If SYSCLK source is MSI, function returns values based on MSI clock(*) |
| * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) |
| * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) |
| * @note If SYSCLK source is PLL, function returns values based on |
| * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. |
| * @note (*) MSI clock depends on the selected MSI range but the real value |
| * may vary depending on the variations in voltage and temperature. |
| * @note (**) HSI_VALUE is a defined constant but the real value may vary |
| * depending on the variations in voltage and temperature. |
| * @note (***) HSE_VALUE is a defined constant, user has to ensure that |
| * HSE_VALUE is same as the real frequency of the crystal used. |
| * Otherwise, this function may have wrong result. |
| * @note The result of this function could be incorrect when using fractional |
| * value for HSE crystal. |
| * @note This function can be used by the user application to compute the |
| * baud-rate for the communication peripherals or configure other parameters. |
| * @{ |
| */ |
| |
| /** |
| * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
| * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function |
| * must be called to update structure fields. Otherwise, any |
| * configuration based on this function will be incorrect. |
| * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies |
| * @retval None |
| */ |
| void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) |
| { |
| /* Get SYSCLK frequency */ |
| RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); |
| |
| /* HCLK clock frequency */ |
| RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); |
| |
| /* PCLK1 clock frequency */ |
| RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); |
| |
| /* PCLK2 clock frequency */ |
| RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); |
| } |
| |
| /** |
| * @brief Return USARTx clock frequency |
| * @param USARTxSource This parameter can be one of the following values: |
| * @arg @ref LL_RCC_USART1_CLKSOURCE |
| * @arg @ref LL_RCC_USART2_CLKSOURCE (*) |
| * |
| * (*) value not defined in all devices. |
| * @retval USART clock frequency (in Hz) |
| * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready |
| */ |
| uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) |
| { |
| uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
| |
| /* Check parameter */ |
| assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); |
| #if defined(RCC_CCIPR_USART1SEL) |
| if (USARTxSource == LL_RCC_USART1_CLKSOURCE) |
| { |
| /* USART1CLK clock frequency */ |
| switch (LL_RCC_GetUSARTClockSource(USARTxSource)) |
| { |
| case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ |
| usart_frequency = RCC_GetSystemClockFreq(); |
| break; |
| |
| case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ |
| if (LL_RCC_HSI_IsReady() != 0U) |
| { |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| usart_frequency = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| usart_frequency = HSI_VALUE; |
| } |
| } |
| break; |
| |
| case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ |
| if (LL_RCC_LSE_IsReady() != 0U) |
| { |
| usart_frequency = LSE_VALUE; |
| } |
| break; |
| |
| case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ |
| default: |
| usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
| break; |
| } |
| } |
| #endif /* RCC_CCIPR_USART1SEL */ |
| |
| #if defined(RCC_CCIPR_USART2SEL) |
| if (USARTxSource == LL_RCC_USART2_CLKSOURCE) |
| { |
| /* USART2CLK clock frequency */ |
| switch (LL_RCC_GetUSARTClockSource(USARTxSource)) |
| { |
| case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ |
| usart_frequency = RCC_GetSystemClockFreq(); |
| break; |
| |
| case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ |
| if (LL_RCC_HSI_IsReady() != 0U) |
| { |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| usart_frequency = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| usart_frequency = HSI_VALUE; |
| } |
| } |
| break; |
| |
| case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ |
| if (LL_RCC_LSE_IsReady() != 0U) |
| { |
| usart_frequency = LSE_VALUE; |
| } |
| break; |
| |
| case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ |
| default: |
| usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
| break; |
| } |
| } |
| #endif /* RCC_CCIPR_USART2SEL */ |
| |
| return usart_frequency; |
| } |
| |
| /** |
| * @brief Return I2Cx clock frequency |
| * @param I2CxSource This parameter can be one of the following values: |
| * @arg @ref LL_RCC_I2C1_CLKSOURCE |
| * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) |
| * |
| * (*) value not defined in all devices |
| * @retval I2C clock frequency (in Hz) |
| * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready |
| */ |
| uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) |
| { |
| uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
| |
| /* Check parameter */ |
| assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); |
| |
| /* I2C1 CLK clock frequency */ |
| if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) |
| { |
| switch (LL_RCC_GetI2CClockSource(I2CxSource)) |
| { |
| case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ |
| i2c_frequency = RCC_GetSystemClockFreq(); |
| break; |
| |
| case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ |
| if (LL_RCC_HSI_IsReady() != 0U) |
| { |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| i2c_frequency = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| i2c_frequency = HSI_VALUE; |
| } |
| } |
| break; |
| |
| case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ |
| default: |
| i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
| break; |
| } |
| } |
| |
| #if defined(RCC_CCIPR_I2C3SEL) |
| /* I2C3 CLK clock frequency */ |
| if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) |
| { |
| switch (LL_RCC_GetI2CClockSource(I2CxSource)) |
| { |
| case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ |
| i2c_frequency = RCC_GetSystemClockFreq(); |
| break; |
| |
| case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ |
| if (LL_RCC_HSI_IsReady() != 0U) |
| { |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| i2c_frequency = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| i2c_frequency = HSI_VALUE; |
| } |
| } |
| break; |
| |
| case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ |
| default: |
| i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
| break; |
| } |
| } |
| #endif /*RCC_CCIPR_I2C3SEL*/ |
| |
| return i2c_frequency; |
| } |
| |
| /** |
| * @brief Return LPUARTx clock frequency |
| * @param LPUARTxSource This parameter can be one of the following values: |
| * @arg @ref LL_RCC_LPUART1_CLKSOURCE |
| * @retval LPUART clock frequency (in Hz) |
| * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready |
| */ |
| uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) |
| { |
| uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
| |
| /* Check parameter */ |
| assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); |
| |
| /* LPUART1CLK clock frequency */ |
| switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) |
| { |
| case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ |
| lpuart_frequency = RCC_GetSystemClockFreq(); |
| break; |
| |
| case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ |
| if (LL_RCC_HSI_IsReady() != 0U) |
| { |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| lpuart_frequency = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| lpuart_frequency = HSI_VALUE; |
| } |
| } |
| break; |
| |
| case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ |
| if (LL_RCC_LSE_IsReady() != 0U) |
| { |
| lpuart_frequency = LSE_VALUE; |
| } |
| break; |
| |
| case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ |
| default: |
| lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
| break; |
| } |
| |
| return lpuart_frequency; |
| } |
| |
| /** |
| * @brief Return LPTIMx clock frequency |
| * @param LPTIMxSource This parameter can be one of the following values: |
| * @arg @ref LL_RCC_LPTIM1_CLKSOURCE |
| * @retval LPTIM clock frequency (in Hz) |
| * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready |
| */ |
| uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) |
| { |
| uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
| |
| /* Check parameter */ |
| assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); |
| |
| if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) |
| { |
| /* LPTIM1CLK clock frequency */ |
| switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) |
| { |
| case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ |
| if (LL_RCC_LSI_IsReady() != 0U) |
| { |
| lptim_frequency = LSI_VALUE; |
| } |
| break; |
| |
| case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ |
| if (LL_RCC_HSI_IsReady() != 0U) |
| { |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| lptim_frequency = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| lptim_frequency = HSI_VALUE; |
| } |
| } |
| break; |
| |
| case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ |
| if (LL_RCC_LSE_IsReady() != 0U) |
| { |
| lptim_frequency = LSE_VALUE; |
| } |
| break; |
| |
| case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ |
| default: |
| lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); |
| break; |
| } |
| } |
| |
| return lptim_frequency; |
| } |
| |
| #if defined(USB) |
| /** |
| * @brief Return USBx clock frequency |
| * @param USBxSource This parameter can be one of the following values: |
| * @arg @ref LL_RCC_USB_CLKSOURCE |
| * @retval USB clock frequency (in Hz) |
| * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready |
| * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected |
| */ |
| uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) |
| { |
| uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
| |
| /* Check parameter */ |
| assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); |
| |
| /* USBCLK clock frequency */ |
| switch (LL_RCC_GetUSBClockSource(USBxSource)) |
| { |
| case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ |
| if (LL_RCC_PLL_IsReady() != 0U) |
| { |
| usb_frequency = RCC_PLL_GetFreqDomain_SYS(); |
| } |
| break; |
| |
| case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ |
| default: |
| if (LL_RCC_HSI48_IsReady() != 0U) |
| { |
| usb_frequency = HSI48_VALUE; |
| } |
| break; |
| } |
| |
| return usb_frequency; |
| } |
| #endif /* USB */ |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup RCC_LL_Private_Functions |
| * @{ |
| */ |
| |
| /** |
| * @brief Return SYSTEM clock frequency |
| * @retval SYSTEM clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetSystemClockFreq(void) |
| { |
| uint32_t frequency; |
| |
| /* Get SYSCLK source -------------------------------------------------------*/ |
| switch (LL_RCC_GetSysClkSource()) |
| { |
| case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ |
| frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); |
| break; |
| |
| case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| frequency = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| frequency = HSI_VALUE; |
| } |
| break; |
| |
| case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ |
| frequency = HSE_VALUE; |
| break; |
| |
| case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ |
| frequency = RCC_PLL_GetFreqDomain_SYS(); |
| break; |
| |
| default: |
| frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); |
| break; |
| } |
| |
| return frequency; |
| } |
| |
| /** |
| * @brief Return HCLK clock frequency |
| * @param SYSCLK_Frequency SYSCLK clock frequency |
| * @retval HCLK clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) |
| { |
| /* HCLK clock frequency */ |
| return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); |
| } |
| |
| /** |
| * @brief Return PCLK1 clock frequency |
| * @param HCLK_Frequency HCLK clock frequency |
| * @retval PCLK1 clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) |
| { |
| /* PCLK1 clock frequency */ |
| return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); |
| } |
| |
| /** |
| * @brief Return PCLK2 clock frequency |
| * @param HCLK_Frequency HCLK clock frequency |
| * @retval PCLK2 clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) |
| { |
| /* PCLK2 clock frequency */ |
| return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); |
| } |
| |
| /** |
| * @brief Return PLL clock frequency used for system domain |
| * @retval PLL clock frequency (in Hz) |
| */ |
| uint32_t RCC_PLL_GetFreqDomain_SYS(void) |
| { |
| uint32_t pllinputfreq, pllsource; |
| |
| /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ |
| |
| /* Get PLL source */ |
| pllsource = LL_RCC_PLL_GetMainSource(); |
| |
| switch (pllsource) |
| { |
| case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ |
| if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) |
| { |
| pllinputfreq = (HSI_VALUE >> 2U); |
| } |
| else |
| { |
| pllinputfreq = HSI_VALUE; |
| } |
| break; |
| |
| default: /* HSE used as PLL clock source */ |
| pllinputfreq = HSE_VALUE; |
| break; |
| } |
| return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider()); |
| } |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| #endif /* defined(RCC) */ |
| |
| /** |
| * @} |
| */ |
| |
| #endif /* USE_FULL_LL_DRIVER */ |
| |
| /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
